From 9ad6ae0cc604ad6275ef94f11d2053533b43344d Mon Sep 17 00:00:00 2001 From: rtel Date: Tue, 30 Sep 2014 15:32:19 +0000 Subject: [PATCH] Added project for Altera Cyclone V SoC, currently running from internal RAM. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2307 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject | 89 + .../Demo/CORTEX_A9_Cyclone_V_SoC_DK/.project | 77 + .../.settings/language.settings.xml | 13 + .../HardwareLibrary/alt_16550_uart.c | 1179 + .../HardwareLibrary/alt_address_space.c | 509 + .../HardwareLibrary/alt_bridge_manager.c | 189 + .../Altera_Code/HardwareLibrary/alt_cache.c | 1776 + .../HardwareLibrary/alt_clock_manager.c | 5556 + .../Altera_Code/HardwareLibrary/alt_dma.c | 3749 + .../HardwareLibrary/alt_dma_program.c | 1064 + .../Altera_Code/HardwareLibrary/alt_ecc.c | 875 + .../HardwareLibrary/alt_fpga_manager.c | 1042 + .../HardwareLibrary/alt_generalpurpose_io.c | 777 + .../HardwareLibrary/alt_globaltmr.c | 557 + .../Altera_Code/HardwareLibrary/alt_i2c.c | 2004 + .../HardwareLibrary/alt_interrupt.c | 1228 + .../HardwareLibrary/alt_interrupt_armcc.s | 121 + .../Altera_Code/HardwareLibrary/alt_mmu.c | 1356 + .../Altera_Code/HardwareLibrary/alt_nand.c | 932 + .../Altera_Code/HardwareLibrary/alt_qspi.c | 2619 + .../HardwareLibrary/alt_reset_manager.c | 135 + .../Altera_Code/HardwareLibrary/alt_sdmmc.c | 2529 + .../Altera_Code/HardwareLibrary/alt_spi.c | 2232 + .../HardwareLibrary/alt_system_manager.c | 265 + .../Altera_Code/HardwareLibrary/alt_timers.c | 1340 + .../HardwareLibrary/alt_watchdog.c | 1101 + .../HardwareLibrary/include/alt_16550_uart.h | 1555 + .../include/alt_address_space.h | 825 + .../include/alt_bridge_manager.h | 269 + .../HardwareLibrary/include/alt_cache.h | 964 + .../HardwareLibrary/include/alt_clock_group.h | 114 + .../include/alt_clock_manager.h | 1434 + .../HardwareLibrary/include/alt_dma.h | 1007 + .../HardwareLibrary/include/alt_dma_common.h | 162 + .../HardwareLibrary/include/alt_dma_program.h | 951 + .../HardwareLibrary/include/alt_ecc.h | 445 + .../include/alt_fpga_manager.h | 1052 + .../include/alt_generalpurpose_io.h | 1254 + .../HardwareLibrary/include/alt_globaltmr.h | 488 + .../HardwareLibrary/include/alt_hwlibs_ver.h | 56 + .../HardwareLibrary/include/alt_i2c.h | 2024 + .../HardwareLibrary/include/alt_interrupt.h | 1039 + .../include/alt_interrupt_common.h | 533 + .../HardwareLibrary/include/alt_mmu.h | 1644 + .../include/alt_mpu_registers.h | 156 + .../HardwareLibrary/include/alt_nand_flash.h | 1019 + .../include/alt_nand_private.h | 190 + .../HardwareLibrary/include/alt_qspi.h | 1535 + .../include/alt_qspi_private.h | 167 + .../include/alt_reset_manager.h | 291 + .../HardwareLibrary/include/alt_sdmmc.h | 1508 + .../HardwareLibrary/include/alt_spi.h | 1847 + .../include/alt_system_manager.h | 209 + .../HardwareLibrary/include/alt_timers.h | 681 + .../HardwareLibrary/include/alt_watchdog.h | 797 + .../HardwareLibrary/include/hwlib.h | 189 + .../include/socal/alt_acpidmap.h | 3569 + .../HardwareLibrary/include/socal/alt_can.h | 36873 +++++ .../include/socal/alt_clkmgr.h | 6464 + .../HardwareLibrary/include/socal/alt_dap.h | 144 + .../include/socal/alt_dmanonsecure.h | 144 + .../include/socal/alt_dmasecure.h | 144 + .../HardwareLibrary/include/socal/alt_emac.h | 103305 +++++++++++++ .../HardwareLibrary/include/socal/alt_f2h.h | 1075 + .../include/socal/alt_fpgamgr.h | 7090 + .../include/socal/alt_fpgamgrdata.h | 158 + .../HardwareLibrary/include/socal/alt_gpio.h | 1991 + .../HardwareLibrary/include/socal/alt_h2f.h | 1073 + .../HardwareLibrary/include/socal/alt_i2c.h | 5940 + .../HardwareLibrary/include/socal/alt_l3.h | 6299 + .../HardwareLibrary/include/socal/alt_l4wd.h | 1801 + .../include/socal/alt_lwfpgaslvs.h | 52 + .../HardwareLibrary/include/socal/alt_lwh2f.h | 1450 + .../HardwareLibrary/include/socal/alt_mpul2.h | 144 + .../include/socal/alt_mpuscu.h | 144 + .../HardwareLibrary/include/socal/alt_nand.h | 10617 ++ .../include/socal/alt_nanddata.h | 52 + .../HardwareLibrary/include/socal/alt_ocram.h | 52 + .../HardwareLibrary/include/socal/alt_qspi.h | 5951 + .../include/socal/alt_qspidata.h | 52 + .../HardwareLibrary/include/socal/alt_rom.h | 52 + .../include/socal/alt_rstmgr.h | 3382 + .../include/socal/alt_scanmgr.h | 927 + .../HardwareLibrary/include/socal/alt_sdmmc.h | 9115 ++ .../HardwareLibrary/include/socal/alt_sdr.h | 4149 + .../HardwareLibrary/include/socal/alt_spim.h | 3293 + .../HardwareLibrary/include/socal/alt_spis.h | 2958 + .../HardwareLibrary/include/socal/alt_stm.h | 144 + .../include/socal/alt_sysmgr.h | 24810 ++++ .../HardwareLibrary/include/socal/alt_tmr.h | 864 + .../HardwareLibrary/include/socal/alt_uart.h | 5158 + .../HardwareLibrary/include/socal/alt_usb.h | 114043 +++++++++++++++ .../HardwareLibrary/include/socal/hps.h | 8026 + .../HardwareLibrary/include/socal/socal.h | 259 + .../Altera_Code/SoCSupport/cache_support.c | 97 + .../Altera_Code/SoCSupport/fpga_support.c | 80 + .../SoCSupport/include/cache_support.h | 55 + .../SoCSupport/include/fpga_support.h | 42 + .../SoCSupport/include/mmu_support.h | 40 + .../Altera_Code/SoCSupport/mmu_support.c | 125 + .../FreeRTOSConfig.h | 232 + .../cycloneV-dk-oc-ram.ld | 257 + .../cycloneV-dk-ram.ld | 257 + .../Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c | 196 + .../CORTEX_A9_Cyclone_V_SoC_DK/preloader.ds | 48 + .../printf-stdarg.c | 312 + .../uboot-socfpga/spl/u-boot-spl | Bin 0 -> 454581 bytes .../Demo/CORTEX_A9_Cyclone_V_SoC_DK/uboot.ds | 52 + 108 files changed, 431276 insertions(+) create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.project create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.settings/language.settings.xml create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_16550_uart.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_address_space.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_bridge_manager.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_cache.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_clock_manager.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_dma.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_dma_program.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_ecc.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_fpga_manager.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_generalpurpose_io.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_globaltmr.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_i2c.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_interrupt.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_interrupt_armcc.s create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_mmu.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_nand.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_qspi.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_reset_manager.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_sdmmc.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_spi.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_system_manager.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_timers.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_watchdog.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_16550_uart.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_address_space.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_bridge_manager.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_cache.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_clock_group.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_clock_manager.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_dma.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_dma_common.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_dma_program.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_ecc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_fpga_manager.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_generalpurpose_io.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_globaltmr.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_hwlibs_ver.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_i2c.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_interrupt.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_interrupt_common.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_mmu.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_mpu_registers.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_nand_flash.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_nand_private.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_qspi.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_qspi_private.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_reset_manager.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_sdmmc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_spi.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_system_manager.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_timers.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_watchdog.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/hwlib.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_acpidmap.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_can.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_clkmgr.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dap.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dmanonsecure.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dmasecure.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_emac.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_f2h.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_fpgamgr.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_fpgamgrdata.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_gpio.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_h2f.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_i2c.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_l3.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_l4wd.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_lwfpgaslvs.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_lwh2f.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_mpul2.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_mpuscu.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_nand.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_nanddata.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_ocram.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_qspi.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_qspidata.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_rom.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_rstmgr.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_scanmgr.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdmmc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdr.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_spim.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_spis.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_stm.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sysmgr.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_tmr.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_uart.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_usb.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/hps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/socal.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/cache_support.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/fpga_support.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/cache_support.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/fpga_support.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/mmu_support.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/mmu_support.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/FreeRTOSConfig.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/cycloneV-dk-oc-ram.ld create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/cycloneV-dk-ram.ld create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/preloader.ds create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/printf-stdarg.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/uboot-socfpga/spl/u-boot-spl create mode 100644 FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/uboot.ds diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject new file mode 100644 index 000000000..612e1a4a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject @@ -0,0 +1,89 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.project b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.project new file mode 100644 index 000000000..8d3b688ee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.project @@ -0,0 +1,77 @@ + + + RTOSDemo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + + + 1411907231532 + FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1411907231540 + FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1411907280295 + FreeRTOS_Source/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ARM_CA9 + + + + 1411907250859 + FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + + + FREERTOS_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.settings/language.settings.xml b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.settings/language.settings.xml new file mode 100644 index 000000000..3654c793f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.settings/language.settings.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_16550_uart.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_16550_uart.c new file mode 100644 index 000000000..6accb102d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_16550_uart.c @@ -0,0 +1,1179 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_16550_uart.h" +#include "alt_clock_manager.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_uart.h" +#include "socal/hps.h" +#include "socal/socal.h" + +///// + +#define ALT_16550_HANDLE_DATA_UART_ENABLED_MSK (1UL << 31) +#define ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(value) (value & 0xffff) + +#define ALT_ALTERA_16550_CPR_OFST (0xF4) +#define ALT_ALTERA_16550_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ALTERA_16550_CPR_OFST)) +#define ALT_ALTERA_16550_CPR_FIFO_MODE_GET(value) (((value) >> 16) & 0xff) +#define ALT_ALTERA_16550_CPR_AFCE_MODE_SET_MSK (1 << 4) + +///// + +// Remove these macros as part of case:123835. +#define ALT_UART_IER_DLH_VALUE_SET(value) ((value) & 0xff) +#define ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK + +///// + +// +// Helper function which resets the UART and if requested, initializes the UART +// to the default settings. Currently the default settings are: +// - 8 databits +// - no parity +// - 1 stopbit +// - 57600 baudrate +// The reset routines depends on the hardware implementation of the UART. +// + +// This helper is needed because the regular alt_read_word(src) essentially +// resolves to "*(volatile uint32_t *)src". As there is no assignment, this +// could potentially be optimized away. With the helper, the actual register +// read should occur and be returned (and subsequently discarded). +static inline uint32_t alt_read_word_helper(const void * addr) +{ + return alt_read_word(addr); +} + +// +// Helper function write the divisor in hardware. +// +static ALT_STATUS_CODE alt_16550_write_divisor_helper(ALT_16550_HANDLE_t * handle, + uint32_t divisor) +{ + // Validate the divisor parameter. + if (divisor > 0xffff) + { + // This should never happen as it is verified in divisor_set. + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set LCR::DLAB (Line Control Register :: Divisor Latch Access Bit) + alt_setbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_DLAB_SET_MSK); + + // Write DLL (Divisor Latch Low). + alt_write_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location), ALT_UART_RBR_THR_DLL_VALUE_SET(divisor)); + + // Write DLH (Divisor Latch High). + alt_write_word(ALT_UART_IER_DLH_ADDR(handle->location), ALT_UART_IER_DLH_VALUE_SET(divisor >> 8)); + + // Clear LCR::DLAB (Line Control Register :: Divisor Latch Access Bit) + alt_clrbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_DLAB_SET_MSK); + + break; + + default: + return ALT_E_ERROR; + } + + // Update the enabled state in the handle data. + if (divisor != 0) + { + handle->data |= ALT_16550_HANDLE_DATA_UART_ENABLED_MSK; + } + else + { + handle->data &= ~ALT_16550_HANDLE_DATA_UART_ENABLED_MSK; + } + + return ALT_E_SUCCESS; +} + +// +// Helper function to reset the UART. +// +static ALT_STATUS_CODE alt_16550_reset_helper(ALT_16550_HANDLE_t * handle, bool enable_init) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::UR (Shadow Reset Register :: UART Reset) + alt_write_word(ALT_UART_SRR_ADDR(handle->location), ALT_UART_SRR_UR_SET_MSK); + + // Read the MSR to work around case:119085. + alt_read_word_helper(ALT_UART_MSR_ADDR(handle->location)); + break; + + case ALT_16550_DEVICE_ALTERA_16550_UART: + alt_16550_write_divisor_helper(handle, 0); // Disable UART + alt_16550_int_disable_all(handle); // Disable interrupts + alt_16550_fifo_disable(handle); // Disable FIFOs + alt_write_word(ALT_UART_MCR_ADDR(handle->location), 0); // 0 -> MCR (AFCE, LP, OUT2, OUT1, RTS, DTR) + break; + + default: + return ALT_E_ERROR; + } + + // If we are initializing (as opposed to just uninitializing) + if (enable_init) + { + ALT_STATUS_CODE status; + + // Set bit IER::PTIME (Interrupt Enable Register :: Programmable THRE Mode Enable) + alt_setbits_word(ALT_UART_IER_DLH_ADDR(handle->location), ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK); + + // Set the line configuration to use 8-N-1. + status = alt_16550_line_config_set(handle, ALT_16550_DATABITS_8, + ALT_16550_PARITY_DISABLE, + ALT_16550_STOPBITS_1); + if (status != ALT_E_SUCCESS) + { + return status; + } + + uint32_t divisor = ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data); + if (divisor == 0) + { + // Set the default baudrate to 57600. + status = alt_16550_baudrate_set(handle, ALT_16550_BAUDRATE_57600); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device, + void * location, + alt_freq_t clock_freq, + ALT_16550_HANDLE_t * handle) +{ + handle->device = device; + handle->data = 0; + handle->fcr = 0; + + switch (device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // The ALT_CLK_L4_SP is required for all SoCFPGA UARTs. Check that it's enabled. + if (alt_clk_is_enabled(ALT_CLK_L4_SP) != ALT_E_TRUE) + { + return ALT_E_BAD_CLK; + } + else + { + ALT_STATUS_CODE status; + status = alt_clk_freq_get(ALT_CLK_L4_SP, &handle->clock_freq); + if (status != ALT_E_SUCCESS) + { + return status; + } + + if (device == ALT_16550_DEVICE_SOCFPGA_UART0) + { + handle->location = ALT_UART0_ADDR; + + // Bring UART0 out of reset. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART0_SET_MSK); + } + else // device == ALT_16550_DEVICE_SOCFPGA_UART1 + { + handle->location = ALT_UART1_ADDR; + + // Bring UART1 out of reset. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART1_SET_MSK); + } + + // Verify the UCR (UART Component Version) + uint32_t ucr = alt_read_word(ALT_UART_UCV_ADDR(handle->location)); + if (ucr != ALT_UART_UCV_UART_COMPONENT_VER_RESET) + { + return ALT_E_ERROR; + } + } + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + handle->location = location; + handle->clock_freq = clock_freq; + break; + default: + return ALT_E_BAD_ARG; + } + + return alt_16550_reset_helper(handle, true); +} + +ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART0_SET_MSK); + return ALT_E_SUCCESS; + case ALT_16550_DEVICE_SOCFPGA_UART1: + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_UART1_SET_MSK); + return ALT_E_SUCCESS; + case ALT_16550_DEVICE_ALTERA_16550_UART: + default: + return alt_16550_reset_helper(handle, false); + } +} + +ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle) +{ + return alt_16550_reset_helper(handle, true); +} + +ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle) +{ + // Write the divisor cached in the handle data to the divisor registers. + // This will effectively enable the UART. + return alt_16550_write_divisor_helper(handle, + ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data)); +} + +ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle) +{ + // Write 0 to the divisor the divisor registers. This will effectively + // disable the UART. + return alt_16550_write_divisor_helper(handle, 0); +} + +ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle, + char * item) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is disabled + if (handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the RBR (Receive Buffer Register) into *item. + *item = ALT_UART_RBR_THR_DLL_VALUE_GET(alt_read_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location))); + break; + default: + return ALT_E_ERROR; + } + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle, + char item) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is disabled + if (handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write the buffer into the THR (Transmit Holding Register) + alt_write_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location), item); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set FCR::FIFOE (FIFO Control Register :: FIFO Enable) bit. + handle->fcr |= ALT_UART_FCR_FIFOE_SET_MSK; + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + // No need to reset / clear the FIFOs. This is done automatically when + // FCR::FIFOE is changed. + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear FCR::FIFOE (FIFO Control Register :: FIFO Enable) bit. + handle->fcr &= ~ALT_UART_FCR_FIFOE_SET_MSK; + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle, + char * buffer, + size_t count) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the RBR (Receive Buffer Register) into the buffer + for (size_t i = 0; i < count; ++i) + { + buffer[i] = ALT_UART_RBR_THR_DLL_VALUE_GET(alt_read_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location))); + } + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle, + const char * buffer, + size_t count) +{ + // Verify that the UART is enabled + if (!(handle->data & ALT_16550_HANDLE_DATA_UART_ENABLED_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write the buffer into the THR (Transmit Holding Register) + for (size_t i = 0; i < count; ++i) + { + alt_write_word(ALT_UART_RBR_THR_DLL_ADDR(handle->location), buffer[i]); + } + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::RFR (Shadow Reset Register :: Receiver FIFO Reset) bit. + alt_write_word(ALT_UART_SRR_ADDR(handle->location), ALT_UART_SRR_RFR_SET_MSK); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write FCR::RFIFOR (FIFO Control Register :: Receiver FIFO Reset) bit. + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr | ALT_UART_FCR_RFIFOR_SET_MSK); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::XFR (Shadow Reset Register :: Xmitter FIFO Reset) bit. + alt_write_word(ALT_UART_SRR_ADDR(handle->location), ALT_UART_SRR_XFR_SET_MSK); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write FCR::XFIFOR (FIFO Control Register :: Xmitter FIFO Reset) bit. + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr | ALT_UART_FCR_XFIFOR_SET_MSK); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Write SRR::(RFR | XFR) + // (Shadow Reset Register :: (Receiver FIFO Reset | Xmitter FIFO Reset)) bits. + alt_write_word(ALT_UART_SRR_ADDR(handle->location), + ALT_UART_SRR_RFR_SET_MSK | ALT_UART_SRR_XFR_SET_MSK); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Write FCR::(RFIFOR |XFIFOR) + // (FIFO Control Register :: (Receiver FIFO Reset | Xmitter FIFO Reset)) bits. + alt_write_word(ALT_UART_FCR_ADDR(handle->location), + handle->fcr | ALT_UART_FCR_RFIFOR_SET_MSK | ALT_UART_FCR_XFIFOR_SET_MSK); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * size) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read the CPR::FIFO_Mod (Component Parameter Register :: FIFO Mode). + // The FIFO size is 16x this value. + *size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Altera 16550 Compatible Soft UARTs have a configurable size and is + // stored in the CPR::FIFO_Mode (Component Parameter Register :: FIFO Depth). + *size = ALT_ALTERA_16550_CPR_FIFO_MODE_GET(alt_read_word(ALT_ALTERA_16550_CPR_ADDR(handle->location))) << 4; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * size) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read the CPR::FIFO_Mod (Component Parameter Register :: FIFO Mode). + // The FIFO size is 16x this value. + *size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Altera 16550 Compatible Soft UARTs have a configurable size and is + // stored in the CPR::FIFO_Mode (Component Parameter Register :: FIFO Depth). + // The FIFO size is 16x this value. + *size = ALT_ALTERA_16550_CPR_FIFO_MODE_GET(alt_read_word(ALT_ALTERA_16550_CPR_ADDR(handle->location))) << 4; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * level) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read RFL (Receive FIFO Level). + *level = alt_read_word(ALT_UART_RFL_ADDR(handle->location)); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // RFL not implemented. Return 0. + *level = 0; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * level) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + // Read TFL (Transmit FIFO Level). + *level = alt_read_word(ALT_UART_TFL_ADDR(handle->location)); + break; + case ALT_16550_DEVICE_ALTERA_16550_UART: + // TFL not implemented. Return 0. + *level = 0; + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_RX_t trigger) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + // Verify triggering parameter + switch (trigger) + { + case ALT_16550_FIFO_TRIGGER_RX_ANY: + case ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL: + case ALT_16550_FIFO_TRIGGER_RX_HALF_FULL: + case ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Update FCR::RT (FIFO Control Register :: Receiver Trigger) + handle->fcr &= ~ALT_UART_FCR_RT_SET_MSK; + handle->fcr |= ALT_UART_FCR_RT_SET(trigger); + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_TX_t trigger) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + // Verify triggering parameter + switch (trigger) + { + case ALT_16550_FIFO_TRIGGER_TX_EMPTY: + case ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY: + case ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL: + case ALT_16550_FIFO_TRIGGER_TX_HALF_FULL: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Update FCR::TET (FIFO Control Register :: Transmit Empty Trigger) + handle->fcr &= ~ALT_UART_FCR_TET_SET_MSK; + handle->fcr |= ALT_UART_FCR_TET_SET(trigger); + alt_write_word(ALT_UART_FCR_ADDR(handle->location), handle->fcr); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle, + uint32_t * baudrate) +{ + // Query the divisor cached in the handle data + uint32_t divisor = ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data); + + // The divisor should never be zero. It is set to allow for a baud of 57600 + // on initialization and a valid value is checked at + // alt_16550_divisor_set(). We do not check for users altering the data in + // the handle structure. + + // Formula for calculating the baudrate: + // baudrate = clock / (16 * divisor) + + *baudrate = (handle->clock_freq >> 4) / divisor; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle, + uint32_t baudrate) +{ + if (baudrate == 0) + { + return ALT_E_ARG_RANGE; + } + + // Formula for calculating the divisor: + // baudrate = clock / (16 * divisor) + // => baudrate * 16 * divisor = clock + // => divisor = clock / (baudrate * 16) + // => divisor = (clock / 16) / baudrate + + // Add half of the denominator to address rounding errors. + uint32_t divisor = ((handle->clock_freq + (8 * baudrate)) / (16 * baudrate)); + + // Check for divisor range is in alt_16550_divisor_set(). + return alt_16550_divisor_set(handle, divisor); +} + +ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle, + uint32_t * divisor) +{ + // Just read the divisor portion of the handle data. + *divisor = ALT_16550_HANDLE_DATA_DIVISOR_VALUE_GET(handle->data); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle, + uint32_t divisor) +{ + // Verify divisor value is in range. + if ((divisor > 0xffff) || (divisor == 0)) + { + return ALT_E_ARG_RANGE; + } + + // Set the divisor portion of the handle data. + handle->data &= ~(0xffff); + handle->data |= divisor; + + // Even if the UART is enabled, don't do anything. It is documented that + // the change will take effect when the UART move to the enabled state. + + return ALT_E_SUCCESS; +} + +///// + +static ALT_STATUS_CODE alt_16550_ier_mask_set_helper(ALT_16550_HANDLE_t * handle, uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set bit in IER (Interrupt Enable Register) + alt_setbits_word(ALT_UART_IER_DLH_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +static ALT_STATUS_CODE alt_16550_ier_mask_clr_helper(ALT_16550_HANDLE_t * handle, uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear bit in IER (Interrupt Enable Register) + alt_clrbits_word(ALT_UART_IER_DLH_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::ERBFI (Interrupt Enable Register :: Enable Receive Buffer Full Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::ERBFI (Interrupt Enable Register :: Enable Receive Buffer Full Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::ETBEI (Interrupt Enable Register :: Enable Transmit Buffer Empty Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::ETBEI (Interrupt Enable Register :: Enable Transmit Buffer Empty Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::ELSI (Interrupt Enable Register :: Enable Line Status Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::ELSI (Interrupt Enable Register :: Enable Line Status Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle) +{ + // Set the IER::EDSSI (Interrupt Enable Register :: Enable Modem Status Interrupt) bit. + return alt_16550_ier_mask_set_helper(handle, ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::EDSSI (Interrupt Enable Register :: Enable Modem Status Interrupt) bit. + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle) +{ + // Clear the IER::(ERBFI | ETBEI | ELSI | EDSSI) + // (Interrupt Enable Register :: (Enable Receive Buffer Full Interrupt | + // Enable Transmit Buffer Empty Interrupt | + // Enable Line Status Interrupt | + // Enable Modem Status Interrupt)) bits + return alt_16550_ier_mask_clr_helper(handle, ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK | + ALT_UART_IER_DLH_ETBEI_DLH1_SET_MSK | + ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK | + ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_int_status_get(ALT_16550_HANDLE_t * handle, + ALT_16550_INT_STATUS_t * status) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read IIR::IID (Interrupt Identity Register :: Interrupt ID) + *status = (ALT_16550_INT_STATUS_t) ALT_UART_IIR_ID_GET(alt_read_word(ALT_UART_IIR_ADDR(handle->location))); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle, + ALT_16550_DATABITS_t databits, + ALT_16550_PARITY_t parity, + ALT_16550_STOPBITS_t stopbits) +{ + // Validate the databits parameter. + switch (databits) + { + case ALT_16550_DATABITS_5: + case ALT_16550_DATABITS_6: + case ALT_16550_DATABITS_7: + case ALT_16550_DATABITS_8: + break; + default: + return ALT_E_ERROR; + } + + // Validate the parity parameter. + switch (parity) + { + case ALT_16550_PARITY_DISABLE: + case ALT_16550_PARITY_ODD: + case ALT_16550_PARITY_EVEN: + break; + default: + return ALT_E_ERROR; + } + + // Validate the stopbits parameter. + switch (stopbits) + { + case ALT_16550_STOPBITS_1: + case ALT_16550_STOPBITS_2: + break; + default: + return ALT_E_ERROR; + } + + // LCR (Line Control Register) cache. + uint32_t lcr = 0; + + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + + // Configure the number of databits + lcr |= ALT_UART_LCR_DLS_SET(databits); + + // Configure the number of stopbits + lcr |= ALT_UART_LCR_STOP_SET(stopbits); + + // Configure the parity + if (parity != ALT_16550_PARITY_DISABLE) + { + // Enable parity in LCR + lcr |= ALT_UART_LCR_PEN_SET_MSK; + + if (parity == ALT_16550_PARITY_EVEN) + { + // Enable even parity in LCR; otherwise it's odd parity. + lcr |= ALT_UART_LCR_EPS_SET_MSK; + } + } + + // Update LCR (Line Control Register) + alt_replbits_word(ALT_UART_LCR_ADDR(handle->location), + ALT_UART_LCR_DLS_SET_MSK + | ALT_UART_LCR_STOP_SET_MSK + | ALT_UART_LCR_PEN_SET_MSK + | ALT_UART_LCR_EPS_SET_MSK, + lcr); + + break; + + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set the LCR::Break (Line Control Register :: Break) bit. + alt_setbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_BREAK_SET_MSK); + break; + + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear the LCR::Break (Line Control Register :: Break) bit. + alt_clrbits_word(ALT_UART_LCR_ADDR(handle->location), ALT_UART_LCR_BREAK_SET_MSK); + break; + + default: + return ALT_E_ERROR; + } + + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the LSR (Line Status Register). + *status = alt_read_word(ALT_UART_LSR_ADDR(handle->location)); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +///// + +static ALT_STATUS_CODE alt_16550_mcr_mask_set_helper(ALT_16550_HANDLE_t * handle, + uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Set the bit in MCR (Modem Control Register). + alt_setbits_word(ALT_UART_MCR_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +static ALT_STATUS_CODE alt_16550_mcr_mask_clr_helper(ALT_16550_HANDLE_t * handle, uint32_t setmask) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Clear the bit in MCR (Modem Control Register). + alt_clrbits_word(ALT_UART_MCR_ADDR(handle->location), setmask); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle) +{ + // Verify that the FIFO is enabled + if (!(handle->fcr & ALT_UART_FCR_FIFOE_SET_MSK)) + { + return ALT_E_ERROR; + } + + // For the Altera 16550 Compatible Soft UART, check that Hardware Flowcontrol is enabled. + if (handle->device == ALT_16550_DEVICE_ALTERA_16550_UART) + { + // Read the CPR::AFCE_Mode (Component Parameter Register :: Auto Flow Control mode) bit. + uint32_t cpr = alt_read_word(ALT_ALTERA_16550_CPR_ADDR(handle->location)); + if (!(ALT_ALTERA_16550_CPR_AFCE_MODE_SET_MSK & cpr)) + { + return ALT_E_ERROR; + } + } + + // Set MCR::AFCE (Modem Control Register :: Automatic FlowControl Enable) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_AFCE_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::AFCE (Modem Control Register :: Automatic FlowControl Enable) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_AFCE_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle) +{ + // Loopback is not implemented in the Altera 16550 Compatible Soft UART. + if (handle->device == ALT_16550_DEVICE_ALTERA_16550_UART) + { + return ALT_E_ERROR; + } + + // Set MCR::Loopback (Modem Control Register :: Loopback) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_LOOPBACK_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::Loopback (Modem Control Register :: Loopback) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_LOOPBACK_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::Out1 (Modem Control Register :: Out1) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_OUT1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::Out1 (Modem Control Register :: Out1) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_OUT1_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::Out2 (Modem Control Register :: Out2) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_OUT2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::Out2 (Modem Control Register :: Out2) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_OUT2_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::RTS (Modem Control Register :: Request To Send) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_RTS_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::RTS (Modem Control Register :: Request To Send) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_RTS_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle) +{ + // Set MCR::DTR (Modem Control Register :: Data Terminal Ready) bit. + return alt_16550_mcr_mask_set_helper(handle, ALT_UART_MCR_DTR_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle) +{ + // Clear MCR::DTR (Modem Control Register :: Data Terminal Ready) bit. + return alt_16550_mcr_mask_clr_helper(handle, ALT_UART_MCR_DTR_SET_MSK); +} + +ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status) +{ + switch (handle->device) + { + case ALT_16550_DEVICE_SOCFPGA_UART0: + case ALT_16550_DEVICE_SOCFPGA_UART1: + case ALT_16550_DEVICE_ALTERA_16550_UART: + // Read the MSR (Modem Status Register). + *status = alt_read_word(ALT_UART_MSR_ADDR(handle->location)); + break; + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_address_space.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_address_space.c new file mode 100644 index 000000000..c11e8e414 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_address_space.c @@ -0,0 +1,509 @@ +/****************************************************************************** + * + * alt_address_space.c - API for the Altera SoC FPGA address space. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include "alt_address_space.h" +#include "socal/alt_l3.h" +#include "socal/socal.h" +#include "socal/alt_acpidmap.h" +#include "hwlib.h" + + +#define ALT_ACP_ID_MAX_INPUT_ID 7 +#define ALT_ACP_ID_MAX_OUTPUT_ID 4096 + +/******************************************************************************/ +ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, + ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr, + ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_bridge_attr, + ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_bridge_attr) +{ + uint32_t remap_reg_val = 0; + + // Parameter checking and validation... + if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM) + { + remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_BOOTROM); + } + else if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM) + { + remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_OCRAM); + } + else + { + return ALT_E_INV_OPTION; + } + + if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM) + { + remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_SDRAM); + } + else if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM) + { + remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_OCRAM); + } + else + { + return ALT_E_INV_OPTION; + } + + if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_INACCESSIBLE) + { + remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_INVISIBLE); + } + else if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_ACCESSIBLE) + { + remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_VISIBLE); + } + else + { + return ALT_E_INV_OPTION; + } + + if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_INACCESSIBLE) + { + remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_INVISIBLE); + } + else if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_ACCESSIBLE) + { + remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_VISIBLE); + } + else + { + return ALT_E_INV_OPTION; + } + + // Perform the remap. + alt_write_word(ALT_L3_REMAP_ADDR, remap_reg_val); + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +// Remap the MPU address space view of address 0 to access the SDRAM controller. +// This is done by setting the L2 cache address filtering register start address +// to 0 and leaving the address filtering address end address value +// unmodified. This causes all physical addresses in the range +// address_filter_start <= physical_address < address_filter_end to be directed +// to the to the AXI Master Port M1 which is connected to the SDRAM +// controller. All other addresses are directed to AXI Master Port M0 which +// connect the MPU subsystem to the L3 interconnect. +// +// It is unnecessary to modify the MPU remap options in the L3 remap register +// because those options only affect addresses in the MPU subsystem address +// ranges that are now redirected to the SDRAM controller and never reach the L3 +// interconnect anyway. +ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void) +{ + uint32_t addr_filt_end = (alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR) & + L2_CACHE_ADDR_FILTERING_END_ADDR_MASK); + return alt_l2_addr_filter_cfg_set(0x0, addr_filt_end); +} + +/******************************************************************************/ +// Return the L2 cache address filtering registers configuration settings in the +// user provided start and end address range out parameters. +ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start, + uint32_t* addr_filt_end) +{ + if (addr_filt_start == NULL || addr_filt_end == NULL) + { + return ALT_E_BAD_ARG; + } + + uint32_t addr_filt_start_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_START_ADDR); + uint32_t addr_filt_end_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR); + + *addr_filt_start = (addr_filt_start_reg & L2_CACHE_ADDR_FILTERING_START_ADDR_MASK); + *addr_filt_end = (addr_filt_end_reg & L2_CACHE_ADDR_FILTERING_END_ADDR_MASK); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, + uint32_t addr_filt_end) +{ + // Address filtering start and end values must be 1 MB aligned. + if ( (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK) + || (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK) ) + { + return ALT_E_ARG_RANGE; + } + + // While it is possible to set the address filtering end value above its + // reset value and thereby access a larger SDRAM address range, it is not + // recommended. Doing so would potentially obscure any mapped HPS to FPGA + // bridge address spaces and peripherals on the L3 interconnect. + if (addr_filt_end > L2_CACHE_ADDR_FILTERING_END_RESET) + { + return ALT_E_ARG_RANGE; + } + + // NOTE: ARM (ARM DDI 0246F CoreLink Level 2 Cache Controller L2C-310 TRM) + // recommends programming the Address Filtering End Register before the + // Address Filtering Start Register to avoid unpredictable behavior between + // the two writes. + alt_write_word(L2_CACHE_ADDR_FILTERING_END_ADDR, addr_filt_end); + // It is recommended that address filtering always remain enabled. + addr_filt_start |= L2_CACHE_ADDR_FILTERING_ENABLE_MASK; + alt_write_word(L2_CACHE_ADDR_FILTERING_START_ADDR, addr_filt_start); + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser) +{ + if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR, + ALT_ACPIDMAP_VID2RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID2RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID2RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR, + ALT_ACPIDMAP_VID3RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID3RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID3RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR, + ALT_ACPIDMAP_VID4RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID4RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID4RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR, + ALT_ACPIDMAP_VID5RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID5RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID5RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR, + ALT_ACPIDMAP_VID6RD_MID_SET(input_id) + | ALT_ACPIDMAP_VID6RD_PAGE_SET(page) + | ALT_ACPIDMAP_VID6RD_USER_SET(aruser) + | ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser) +{ + if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR, + ALT_ACPIDMAP_VID2WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID2WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID2WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR, + ALT_ACPIDMAP_VID3WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID3WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID3WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR, + ALT_ACPIDMAP_VID4WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID4WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID4WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR, + ALT_ACPIDMAP_VID5WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID5WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID5WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR, + ALT_ACPIDMAP_VID6WR_MID_SET(input_id) + | ALT_ACPIDMAP_VID6WR_PAGE_SET(page) + | ALT_ACPIDMAP_VID6WR_USER_SET(awuser) + | ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL) + ); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + uint32_t aruser, page; + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR)); + page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR)); + page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR)); + page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR)); + page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR)); + page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR, + ALT_ACPIDMAP_DYNRD_PAGE_SET(page) + | ALT_ACPIDMAP_DYNRD_USER_SET(aruser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + uint32_t awuser, page; + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR)); + page = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR)); + page = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR)); + page = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR)); + page = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR)); + page = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR, + ALT_ACPIDMAP_DYNWR_PAGE_SET(page) + | ALT_ACPIDMAP_DYNWR_USER_SET(awuser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser) +{ + alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR, + ALT_ACPIDMAP_DYNRD_PAGE_SET(page) + | ALT_ACPIDMAP_DYNRD_USER_SET(aruser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser) +{ + alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR, + ALT_ACPIDMAP_DYNWR_PAGE_SET(page) + | ALT_ACPIDMAP_DYNWR_USER_SET(awuser)); + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, + bool * fixed, + uint32_t * input_id, + ALT_ACP_ID_MAP_PAGE_t * page, + uint32_t * aruser) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + *aruser = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + *aruser = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + *aruser = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + *aruser = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + *aruser = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_7: + *aruser = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, + bool * fixed, + uint32_t * input_id, + ALT_ACP_ID_MAP_PAGE_t * page, + uint32_t * awuser) +{ + if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID) + { + return ALT_E_BAD_ARG; + } + + switch (output_id) + { + case ALT_ACP_ID_OUT_FIXED_ID_2: + *awuser = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_3: + *awuser = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_4: + *awuser = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_5: + *awuser = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_6: + *awuser = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + *fixed = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR)); + break; + case ALT_ACP_ID_OUT_DYNAM_ID_7: + *awuser = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR)); + *page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_bridge_manager.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_bridge_manager.c new file mode 100644 index 000000000..37d4ac0f5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_bridge_manager.c @@ -0,0 +1,189 @@ + +/****************************************************************************** +* +* alt_bridge_manager.c - API for the Altera SoC FPGA bridge manager. +* +******************************************************************************/ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include "alt_bridge_manager.h" +#include "alt_clock_manager.h" +#include "alt_fpga_manager.h" +#include "socal/hps.h" +#include "socal/socal.h" +#include "socal/alt_rstmgr.h" + + +/******************************************************************************/ +ALT_STATUS_CODE alt_bridge_init(ALT_BRIDGE_t bridge, + alt_bridge_fpga_is_ready_t fpga_is_ready, + void* user_arg) +{ + uint32_t bridge_reset_mask = 0; + + // Validate the bridge parameter and set the appropriate bridge reset mask. + if (bridge == ALT_BRIDGE_LWH2F) + { + bridge_reset_mask = ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK; + } + else if (bridge == ALT_BRIDGE_H2F) + { + bridge_reset_mask = ALT_RSTMGR_BRGMODRST_H2F_SET_MSK; + } + else if (bridge == ALT_BRIDGE_F2H) + { + bridge_reset_mask = ALT_RSTMGR_BRGMODRST_F2H_SET_MSK; + } + else + { + // Invalid bridge argument specified. + return ALT_E_BAD_ARG; + } + + // Place and hold the specified bridge in reset. + alt_setbits_word(ALT_RSTMGR_BRGMODRST_ADDR, bridge_reset_mask); + + // Validate that bridge clock(s) are configured and stable. Perform the + // clock checks prior other validations that might depend on clocks being + // checked (e.g. FPGA manager dependency on ALT_CLK_L4_MP). + + // l4_mp_clk is required for all bridges. + if (alt_clk_is_enabled(ALT_CLK_L4_MP) != ALT_E_TRUE) + { + return ALT_E_BAD_CLK; + } + + // Although a stable l3_main_clk is required for H2F and F2H bridges, the + // l3_main_clk is not gated and it runs directly from the Main PLL C1 output + // so if this code is executing it effectively means that this clock is stable + // and hence there are no meaningful validation checks that software can perform + // on the ALT_CLK_L3_MAIN. + + // lws2f_axi_clk is required for LWH2F bridge and clocks all LWH2F AXI transactions. + // s2f_axi_clk is required for H2F bridge and clocks all H2F AXI transactions. + // f2s_axi_clk is required for F2H bridge and clocks all F2H AXI transactions. + // + // NOTE: All of these clocks are sourced from the FPGA and provided to the HPS. + // The FPGA must be configured to drive these clocks. Beyond checking that + // the FPGA is configured, there are no HPS control and status mechanisms + // available to check the operational status of these clocks. + + // Check that FPGA is powered on. + ALT_FPGA_STATE_t fpga_state = alt_fpga_state_get(); + if (fpga_state == ALT_FPGA_STATE_POWER_OFF) + { + return ALT_E_FPGA_PWR_OFF; + } + + // Check that FPGA has been configured and is in USER mode. + if (fpga_state != ALT_FPGA_STATE_USER_MODE) + { + return ALT_E_FPGA_NOT_USER_MODE; + } + + // If specified, invoke user defined callback function to determine whether the + // FPGA is ready to commence bridge interface transactions. If no user defined + // callback function is specified then proceed on the assumption that the FPGA + // is ready to commence bridge transactions. + if (fpga_is_ready != NULL) + { + ALT_STATUS_CODE fpga_ready_status = fpga_is_ready(user_arg); + if (fpga_ready_status != ALT_E_SUCCESS) + { + // Return the value of the non successful status code as returned from + // the user defined callback function. + return fpga_ready_status; + } + } + + // Release the bridge from reset. + alt_clrbits_word(ALT_RSTMGR_BRGMODRST_ADDR, bridge_reset_mask); + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ +ALT_STATUS_CODE alt_bridge_uninit(ALT_BRIDGE_t bridge, + alt_bridge_teardown_handshake_t handshake, + void* user_arg) +{ + uint32_t bridge_reset_mask = 0; + + // Validate the bridge parameter and set the appropriate bridge reset mask. + if (bridge == ALT_BRIDGE_LWH2F) + { + bridge_reset_mask = ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK; + } + else if (bridge == ALT_BRIDGE_H2F) + { + bridge_reset_mask = ALT_RSTMGR_BRGMODRST_H2F_SET_MSK; + } + else if (bridge == ALT_BRIDGE_F2H) + { + bridge_reset_mask = ALT_RSTMGR_BRGMODRST_F2H_SET_MSK; + } + else + { + // Invalid bridge argument specified. + return ALT_E_BAD_ARG; + } + + if ((alt_read_word(ALT_RSTMGR_BRGMODRST_ADDR) & bridge_reset_mask) == bridge_reset_mask) + { + // The bridge is already in reset and therefore considered uninitialized. + return ALT_E_SUCCESS; + } + + // If specified, invoke user defined callback function to perform the tear-down + // handshake notification protocol with the FPGA. If no user defined callback + // function is specified then proceed without performing any tear-down handshake + // notification protocol with the FPGA. + if (handshake != NULL) + { + ALT_STATUS_CODE handshake_status = handshake(user_arg); + if (handshake_status != ALT_E_SUCCESS) + { + // Return the value of the non successful status code as returned from + // the user defined callback function. + return handshake_status; + } + } + + // Place and hold the bridge in reset. + alt_setbits_word(ALT_RSTMGR_BRGMODRST_ADDR, bridge_reset_mask); + + return ALT_E_SUCCESS; +} + +/******************************************************************************/ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_cache.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_cache.c new file mode 100644 index 000000000..63fe012e8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_cache.c @@ -0,0 +1,1776 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_cache.h" +#include "alt_interrupt_common.h" +#include "alt_mmu.h" +#include "socal/alt_sysmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" +#include +#include + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf printf + +///// + +#ifndef MIN +#define MIN(a, b) ((a) > (b) ? (b) : (a)) +#endif + +///// + +// System Level API here + +ALT_STATUS_CODE alt_cache_system_enable(void) +{ + alt_cache_l1_enable_all(); + + alt_cache_l2_init(); + alt_cache_l2_prefetch_enable(); + alt_cache_l2_parity_enable(); + alt_cache_l2_enable(); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_system_disable(void) +{ + alt_cache_l2_disable(); + alt_cache_l2_parity_disable(); + alt_cache_l2_prefetch_disable(); + alt_cache_l2_uninit(); + + alt_cache_l1_disable_all(); + + return ALT_E_SUCCESS; +} + +#define ALT_CPU_PAR_FS_VALUE_GET(par) ((par >> 1) & 0x3f) +#define ALT_CPU_PAR_SS_SET_MSK 0x00000002 +#define ALT_CPU_PAR_F_SET_MSK 0x00000001 + +static inline uintptr_t alt_mmu_va_to_pa(void * va, uint32_t * seglength, uint32_t * dfsr) +{ +#if ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY + + uintptr_t pa = 0; + + // ATS1CPR [Address Translate Stage 1 Current state PL1 Read]; See ARMv7-A,R, section B4.2.4. + // ISB + // Read the PAR +#ifdef __ARMCC_VERSION + __asm("mcr p15, 0, va, c7, c8, 0"); + __asm("isb"); + __asm("mrc p15, 0, pa, c7, c4, 0"); +#else + __asm("mcr p15, 0, %0, c7, c8, 0" : : "r" (va)); + __asm("isb"); + __asm("mrc p15, 0, %0, c7, c4, 0" : "=r" (pa)); +#endif + + if (pa & ALT_CPU_PAR_F_SET_MSK) + { + // If the F bit (fault) is set, then report the error. + + // Extract the PAR::FS field value. + uint32_t fs = ALT_CPU_PAR_FS_VALUE_GET(pa); + + // Translate PAR::FS[5:0] (field value) or PAR[6:1] => DFSR[12,10,3:0] to report error. + *dfsr = ((fs & 0x20) << 7) | // bit 12 + ((fs & 0x10) << 6) | // bit 10 + ((fs & 0x0f) << 0); // bit 3:0 + + dprintf("DEBUG[cache][va->pa]: Fault detected. DFSR = 0x%" PRIx32 ".\n", dfsr); + } + else if (pa & ALT_CPU_PAR_SS_SET_MSK) + { + // If the page is a supersection, PAR contains PA[31:24]. VA contains PA[23:0]. + + uint32_t offset = (uintptr_t)va & (ALT_MMU_SUPERSECTION_SIZE - 1); + pa &= ~(ALT_MMU_SUPERSECTION_SIZE - 1); + pa |= offset; + + dprintf("DEBUG[cache][va->pa]: pa[SS] = 0x%x; offset = 0x%" PRIx32 ".\n", + pa & ~(ALT_MMU_SUPERSECTION_SIZE - 1), + offset); + + *seglength = ALT_MMU_SUPERSECTION_SIZE - offset; + *dfsr = 0; + } + else + { + // If the page is not a supersection, PAR contains PA[31:12]. VA contains PA[11:0]. + + uint32_t offset = (uintptr_t)va & (ALT_MMU_SMALL_PAGE_SIZE - 1); + pa &= ~(ALT_MMU_SMALL_PAGE_SIZE - 1); + pa |= offset; + + dprintf("DEBUG[cache][va->pa]: pa[page] = 0x%x; offset = 0x%" PRIx32 ".\n", + pa & ~(ALT_MMU_SMALL_PAGE_SIZE - 1), + offset); + + *seglength = ALT_MMU_SMALL_PAGE_SIZE - offset; + *dfsr = 0; + } + + return pa; + +#else + + *seglength = 0xffffffff - (uintptr_t)va + 1; + *dfsr = 0; + return (uintptr_t)va; + +#endif +} + +// Internal functions that expect all inputs to be aligned properly. + +static void alt_cache_l1_data_invalidate_helper(void * vaddress, size_t length); +static void alt_cache_l1_data_clean_helper(void * vaddress, size_t length); +static void alt_cache_l1_data_purge_helper(void * vaddress, size_t length); + +static ALT_STATUS_CODE alt_cache_l2_invalidate_helper(uintptr_t paddress, size_t length); +static ALT_STATUS_CODE alt_cache_l2_clean_helper(uintptr_t paddress, size_t length); +static ALT_STATUS_CODE alt_cache_l2_purge_helper(uintptr_t paddress, size_t length); + +ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length) +{ + // Verify preconditions: + // - address and length are on the cache boundaries + if (((uintptr_t)vaddress & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + if ((length & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + + dprintf("DEBUG[cache][sys]: invalidate: vaddr = %p; length = 0x%x.\n", vaddress, length); + + char * va = vaddress; + + while (length) + { + uint32_t dfsr = 0; + uint32_t seg_size = 0; + uintptr_t pa = alt_mmu_va_to_pa(va, &seg_size, &dfsr); + if (dfsr) + { + return ALT_E_ERROR; + } + + seg_size = MIN(length, seg_size); + + dprintf("DEBUG[cache][sys]: (loop): va = %p; pa = 0x%x; size = 0x%" PRIx32 ".\n", va, pa, seg_size); + + alt_cache_l2_invalidate_helper(pa, seg_size); + alt_cache_l2_sync(); + alt_cache_l1_data_invalidate_helper(va, seg_size); + // __asm("dsb") handled by l1_data_invalidate(). + + va += seg_size; + length -= seg_size; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length) +{ + // Verify preconditions: + // - address and length are on the cache boundaries + if (((uintptr_t)vaddress & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + if ((length & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + + dprintf("DEBUG[cache][sys]: clean: vaddr = %p; length = 0x%x.\n", vaddress, length); + + char * va = vaddress; + + while (length) + { + uint32_t dfsr = 0; + uint32_t seg_size = 0; + uintptr_t pa = alt_mmu_va_to_pa(va, &seg_size, &dfsr); + if (dfsr) + { + return ALT_E_ERROR; + } + + seg_size = MIN(length, seg_size); + + dprintf("DEBUG[cache][sys]: (loop): va = %p; pa = 0x%x; size = 0x%" PRIx32 ".\n", va, pa, seg_size); + + alt_cache_l1_data_clean_helper(va, seg_size); + // __asm("dsb") handled by l1_data_clean(). + alt_cache_l2_clean_helper(pa, seg_size); + alt_cache_l2_sync(); + + va += seg_size; + length -= seg_size; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length) +{ + // Verify preconditions: + // - address and length are on the cache boundaries + if (((uintptr_t)vaddress & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + if ((length & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + + dprintf("DEBUG[cache][sys]: clean: vaddr = %p; length = 0x%x.\n", vaddress, length); + + char * va = vaddress; + + while (length) + { + uint32_t dfsr = 0; + uint32_t seg_size = 0; + uintptr_t pa = alt_mmu_va_to_pa(va, &seg_size, &dfsr); + if (dfsr) + { + return ALT_E_ERROR; + } + + seg_size = MIN(length, seg_size); + + dprintf("DEBUG[cache][sys]: (loop): va = %p; pa = 0x%x; size = 0x%" PRIx32 ".\n", va, pa, seg_size); + + alt_cache_l1_data_clean_helper(va, seg_size); + // __asm("dsb") handled by l1_data_clean(). + alt_cache_l2_purge_helper(pa, seg_size); + alt_cache_l2_sync(); + alt_cache_l1_data_invalidate_helper(va, seg_size); + // __asm("dsb") handled by l1_data_invalidate(). + + va += seg_size; + length -= seg_size; + } + + return ALT_E_SUCCESS; +} + +///// + +// +// Stand-in SoCAL for ARM CPU registers needed for L1 cache functions. +// + +// System Control Register. See Cortex-A9, section 4.3.9. +#define ALT_CPU_SCTLR_TE_SET_MSK (1 << 30) +#define ALT_CPU_SCTLR_AFE_SET_MSK (1 << 29) +#define ALT_CPU_SCTLR_TRE_SET_MSK (1 << 28) +#define ALT_CPU_SCTLR_NMFI_SET_MSK (1 << 27) +#define ALT_CPU_SCTLR_EE_SET_MSK (1 << 25) +#define ALT_CPU_SCTLR_HA_SET_MSK (1 << 17) +#define ALT_CPU_SCTLR_RR_SET_MSK (1 << 14) +#define ALT_CPU_SCTLR_V_SET_MSK (1 << 13) +#define ALT_CPU_SCTLR_I_SET_MSK (1 << 12) +#define ALT_CPU_SCTLR_Z_SET_MSK (1 << 11) +#define ALT_CPU_SCTLR_SW_SET_MSK (1 << 10) +#define ALT_CPU_SCTLR_C_SET_MSK (1 << 2) +#define ALT_CPU_SCTLR_A_SET_MSK (1 << 1) +#define ALT_CPU_SCTLR_M_SET_MSK (1 << 0) + +// Auxiliary Control Register. See Cortex-A9, section 4.3.10. +#define ALT_CPU_ACTLR_PARITYON_SET_MSK (1 << 9) +#define ALT_CPU_ACTLR_ALLOCINONEWAY_SET_MSK (1 << 8) +#define ALT_CPU_ACTLR_EXCL_SET_MSK (1 << 7) +#define ALT_CPU_ACTLR_SMP_SET_MSK (1 << 6) +#define ALT_CPU_ACTLR_WRITEFULLLINEZEROS_SET_MSK (1 << 3) +#define ALT_CPU_ACTLR_L1PREFETCHEN_SET_MSK (1 << 2) +#define ALT_CPU_ACTLR_L2PREFETCHEN_SET_MSK (1 << 1) +#define ALT_CPU_ACTLR_FW_SET_MSK (1 << 0) + +// Cache Size Selection Register. See Cortex-A9, section 4.3.8. +#define ALT_CPU_ACTLR_LEVEL_SET_MSK (7 << 1) +#define ALT_CPU_ACTLR_IND_SET_MSK (1 << 0) + +// Cache Size Identification Register. See Cortex-A9, section 4.3.5. +#define ALT_CPU_CCSIDR_WT_SET_MSK (0x1 << 31) +#define ALT_CPU_CCSIDR_WB_SET_MSK (0x1 << 30) +#define ALT_CPU_CCSIDR_RA_SET_MSK (0x1 << 29) +#define ALT_CPU_CCSIDR_WA_SET_MSK (0x1 << 28) +#define ALT_CPU_CCSIDR_NUMSETS_SET_MSK (0x7fff << 13) +#define ALT_CPU_CCSIDR_ASSOCIATIVITY_SET_MSK (0x3ff << 3) +#define ALT_CPU_CCSIDR_LINESIZE_SET_MSK (0x7 << 0) + +#define ALT_CPU_CCSIDR_NUMSETS_VALUE_GET(value) (((value) & ALT_CPU_CCSIDR_NUMSETS_SET_MSK) >> 13) +#define ALT_CPU_CCSIDR_ASSOCIATIVITY_VALUE_GET(value) (((value) & ALT_CPU_CCSIDR_ASSOCIATIVITY_SET_MSK) >> 3) +#define ALT_CPU_CCSIDR_LINESIZE_VALUE_GET(value) (((value) & ALT_CPU_CCSIDR_LINESIZE_SET_MSK) >> 0) + +///// + +static inline __attribute__((always_inline)) uint32_t sctlr_read_helper(void) +{ + uint32_t sctlr; + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, sctlr, c1, c0, 0"); +#else + __asm("MRC p15, 0, %0, c1, c0, 0" : "=r" (sctlr)); +#endif + + return sctlr; +} + +static inline __attribute__((always_inline)) void sctlr_write_helper(uint32_t sctlr) +{ +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, sctlr, c1, c0, 0"); +#else + __asm("MCR p15, 0, %0, c1, c0, 0" : : "r" (sctlr)); +#endif +} + +static inline __attribute__((always_inline)) uint32_t actlr_read_helper(void) +{ + uint32_t actlr; + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, actlr, c1, c0, 1"); +#else + __asm("MRC p15, 0, %0, c1, c0, 1" : "=r" (actlr)); +#endif + + return actlr; +} + +static inline __attribute__((always_inline)) void actlr_write_helper(uint32_t actlr) +{ +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, actlr, c1, c0, 1"); +#else + __asm("MCR p15, 0, %0, c1, c0, 1" : : "r" (actlr)); +#endif +} + +static void cssidr_decode_helper(bool query_i_cache, uint32_t * log2_L, uint32_t * log2_A, uint32_t * log2_S) +{ + // First query the D cache information using CSSELR to select the data cache + // See ARM Cortex-A9 TRM, section 4.3.8. + + // Wait for the CSSELR to flush. + + // Then use CSSIDR to get the cache charateristics + // See ARMv7-A,R, section B4.1.19 + + uint32_t csselr; + uint32_t cssidr; + + if (query_i_cache) + { + csselr = ALT_CPU_ACTLR_IND_SET_MSK; + } + else + { + csselr = 0; + } + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 2, csselr, c0, c0, 0"); + __asm("ISB"); + __asm("MRC p15, 1, cssidr, c0, c0, 0"); +#else + __asm("MCR p15, 2, %0, c0, c0, 0" : : "r" (csselr)); + __asm("ISB"); + __asm("MRC p15, 1, %0, c0, c0, 0" : "=r" (cssidr)); +#endif + + // Extract the associativity, line length, and number of sets. + int linesize = ALT_CPU_CCSIDR_LINESIZE_VALUE_GET(cssidr) + 2 + 2; // {log2(line length in words) - 2} + 2 + 2 => (... in bytes) + int associativity = ALT_CPU_CCSIDR_ASSOCIATIVITY_VALUE_GET(cssidr) + 1; + int numsets = ALT_CPU_CCSIDR_NUMSETS_VALUE_GET(cssidr) + 1; + + // Determine the log2 of the associativity and numsets, rounded up + int L = linesize; // log2(line length in bytes) + int A = 0; // log2(associativity) rounded up + int S = 0; // log2(number of sets) rounded up + + while ((1 << A) < associativity) + { + ++A; + } + + while ((1 << S) < numsets) + { + ++S; + } + + // Output the parameters + *log2_L = L; + *log2_A = A; + *log2_S = S; +} + +///// + +ALT_STATUS_CODE alt_cache_l1_enable_all(void) +{ + alt_cache_l1_disable_all(); + + // Parity should be turned on before anything else. + alt_cache_l1_parity_enable(); + alt_cache_l1_instruction_enable(); + alt_cache_l1_data_enable(); + alt_cache_l1_branch_enable(); + alt_cache_l1_prefetch_enable(); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_disable_all(void) +{ + alt_cache_l1_parity_disable(); + alt_cache_l1_instruction_disable(); + alt_cache_l1_data_disable(); + alt_cache_l1_branch_disable(); + alt_cache_l1_prefetch_disable(); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_instruction_enable(void) +{ + // Update SCTLR.I bit (bit 12) + // See Cortex-A9 TRM, section 4.3.9 + + uint32_t sctlr = sctlr_read_helper(); + if ((sctlr & ALT_CPU_SCTLR_I_SET_MSK) == 0) + { + alt_cache_l1_instruction_invalidate(); + + sctlr |= ALT_CPU_SCTLR_I_SET_MSK; + sctlr_write_helper(sctlr); + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_instruction_disable(void) +{ + // Update SCTLR.I bit (bit 12) + // See Cortex-A9 TRM, section 4.3.9 + + uint32_t sctlr = sctlr_read_helper(); + sctlr &= ~ALT_CPU_SCTLR_I_SET_MSK; + sctlr_write_helper(sctlr); + + return ALT_E_SUCCESS; +} + +bool alt_cache_l1_instruction_is_enabled(void) +{ + // Query SCTLR.I bit (bit 12) + // See Cortex-A9 TRM, section 4.3.9 + + uint32_t sctlr = sctlr_read_helper(); + if ( (sctlr & ALT_CPU_SCTLR_I_SET_MSK) != 0 ) + { + return true; + } + else + { + return false; + } +} + +ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void) +{ + // Issue the ICIALLUIS (Instruction Cache Invalidate ALL to point of + // Unification Inner Shareable) cache maintenance operation + // See ARMv7-A,R, section B4.2.1. + + uint32_t dummy = 0; + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, dummy, c7, c1, 0"); +#else + __asm("MCR p15, 0, %0, c7, c1, 0" : : "r" (dummy)); +#endif + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_data_enable(void) +{ + // Update SCTLR.C bit (bit 2) + // See Cortex-A9 TRM, section 4.3.9 + + uint32_t sctlr = sctlr_read_helper(); + if ((sctlr & ALT_CPU_SCTLR_C_SET_MSK) == 0) + { + alt_cache_l1_data_invalidate_all(); + + sctlr |= ALT_CPU_SCTLR_C_SET_MSK; + sctlr_write_helper(sctlr); + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_data_disable(void) +{ + // Update SCTLR.C bit (bit 2) + // See Cortex-A9 TRM, section 4.3.9 + + uint32_t sctlr = sctlr_read_helper(); + if ((sctlr & ALT_CPU_SCTLR_C_SET_MSK) != 0) + { + alt_cache_l1_data_clean_all(); + + sctlr &= ~ALT_CPU_SCTLR_C_SET_MSK; + + sctlr_write_helper(sctlr); + } + + return ALT_E_SUCCESS; +} + +bool alt_cache_l1_data_is_enabled(void) +{ + // Query SCTLR.C bit (bit 2) + // See Cortex-A9 TRM, section 4.3.9 + + uint32_t sctlr = sctlr_read_helper(); + if ( (sctlr & ALT_CPU_SCTLR_C_SET_MSK) != 0 ) + { + return true; + } + else + { + return false; + } +} + +static void alt_cache_l1_data_invalidate_helper(void * vaddress, size_t length) +{ + // Repeatedly call DCIMVAC (Data Cache Invalidate by Modified Virtual + // Address to the point of Coherency) and loop for the length of the + // segment. + + // The DCIMVAC uses the MVA format for the register. This is simply the + // virtual address of the line to be invalidated. + // See ARMv7-A,R, section B4.2.1. + + for (uintptr_t va = (uintptr_t)vaddress; va < (uintptr_t)vaddress + length; va += ALT_CACHE_LINE_SIZE) + { +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, va, c7, c6, 1"); +#else + __asm("MCR p15, 0, %0, c7, c6, 1" : : "r" (va)); +#endif + } + + // Ensure all cache maintenance operations complete before returning. + __asm("dsb"); +} + +ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length) +{ + // Verify preconditions: + // - length is non-zero + // - address and length are on the cache boundaries + if (length == 0) + { + return ALT_E_BAD_ARG; + } + if (((uintptr_t)vaddress & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + if ((length & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + + alt_cache_l1_data_invalidate_helper(vaddress, length); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void) +{ + // Gather parameters for DCISW (Data Cache Invalidate by Set / Way) data format. + // See ARMv7-A,R, section B4.2.1 + + // Query the log2(line size in bytes), log2(associativity), log2(set count) for the data cache. + + uint32_t L = 0; + uint32_t A = 0; + uint32_t S = 0; + + cssidr_decode_helper(false, &L, &A, &S); + + // Repeatedly call DCISW and loop for every cache way and set. + + for (int way = 0; way < (1 << A); ++way) + { + for (int set = 0; set < (1 << S); ++set) + { + uint32_t way_set_info = 0; + way_set_info |= way << (32 - A); + way_set_info |= set << (L); + // Level is 0 because we're invalidating the L1. + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, way_set_info, c7, c6, 2"); +#else + __asm("MCR p15, 0, %0, c7, c6, 2" : : "r" (way_set_info)); +#endif + } + } + + // Ensure all cache maintenance operations complete before returning. + __asm("dsb"); + + return ALT_E_SUCCESS; +} + +static void alt_cache_l1_data_clean_helper(void * vaddress, size_t length) +{ + // Repeatedly call DCCMVAC (Data Cache Clean by Modified Virtual Address to + // point of Coherency) and loop for the length of the segment. + + // The DCCMVAC uses the MVA format for the register. This is simply the + // virtual address of the line to be invalidated. + // See ARMv7-A,R, section B4.2.1. + + for (uintptr_t va = (uintptr_t)vaddress; va < (uintptr_t)vaddress + length; va += ALT_CACHE_LINE_SIZE) + { +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, va, c7, c10, 1"); +#else + __asm("MCR p15, 0, %0, c7, c10, 1" : : "r" (va)); +#endif + } + + // Ensure all cache maintenance operations complete before returning. + __asm("dsb"); +} + +ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length) +{ + // Verify preconditions: + // - length is non-zero + // - address and length are on the cache boundaries + if (length == 0) + { + return ALT_E_BAD_ARG; + } + if (((uintptr_t)vaddress & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + if ((length & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + + alt_cache_l1_data_clean_helper(vaddress, length); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_data_clean_all(void) +{ + // Gather parameters for DCCSW (Data Cache Clean by Set / Way) data format + // See ARMv7-A,R, section B4.2.1 + + // Query the log2(line size in bytes), log2(associativity), log2(set count) for the data cache. + + uint32_t L = 0; + uint32_t A = 0; + uint32_t S = 0; + + cssidr_decode_helper(false, &L, &A, &S); + + // Repeatedly call DCCSW and loop for every cache way and set. + + for (int way = 0; way < (1 << A); ++way) + { + for (int set = 0; set < (1 << S); ++set) + { + uint32_t way_set_info = 0; + way_set_info |= way << (32 - A); + way_set_info |= set << (L); + // Level is 0 because we're invalidating the L1. + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, way_set_info, c7, c10, 2"); +#else + __asm("MCR p15, 0, %0, c7, c10, 2" : : "r" (way_set_info)); +#endif + } + } + + // Ensure all cache maintenance operations complete before returning. + __asm("dsb"); + + return ALT_E_SUCCESS; +} + +static void alt_cache_l1_data_purge_helper(void * vaddress, size_t length) +{ + // Repeatedly call DCCIMVAC (Data Cache Clean and Invalidate by Modified + // Virtual Address to point of Coherency) and loop for the length of the + // segment. + + // The DCCIMVAC uses the MVA format for the register. This is simply the + // virtual address of the line to be invalidated. + // See ARMv7-A,R, section B4.2.1. + + for (uintptr_t va = (uintptr_t)vaddress; va < (uintptr_t)vaddress + length; va += ALT_CACHE_LINE_SIZE) + { +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, va, c7, c14, 1"); +#else + __asm("MCR p15, 0, %0, c7, c14, 1" : : "r" (va)); +#endif + } + + // Ensure all cache maintenance operations complete before returning. + __asm("dsb"); +} + +ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length) +{ + // Verify preconditions: + // - length is non-zero + // - address and length are on the cache boundaries + if (length == 0) + { + return ALT_E_BAD_ARG; + } + if (((uintptr_t)vaddress & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + if ((length & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + + alt_cache_l1_data_purge_helper(vaddress, length); + + return ALT_E_SUCCESS; + +} + +ALT_STATUS_CODE alt_cache_l1_data_purge_all(void) +{ + // Gather parameters for DCCISW (Data Cache Clean and Invalidate by Set / Way) data format + // See ARMv7-A,R, section B4.2.1 + + // Query the log2(line size in bytes), log2(associativity), log2(set count) for the data cache. + + uint32_t L = 0; + uint32_t A = 0; + uint32_t S = 0; + + cssidr_decode_helper(false, &L, &A, &S); + + // Repeatedly call DCCISW and loop for every cache way and set. + + for (int way = 0; way < (1 << A); ++way) + { + for (int set = 0; set < (1 << S); ++set) + { + uint32_t way_set_info = 0; + way_set_info |= way << (32 - A); + way_set_info |= set << (L); + // Level is 0 because we're invalidating the L1. + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, way_set_info, c7, c14, 2"); +#else + __asm("MCR p15, 0, %0, c7, c14, 2" : : "r" (way_set_info)); +#endif + } + } + + // Ensure all cache maintenance operations complete before returning. + __asm("dsb"); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_parity_enable(void) +{ + uint32_t actlr = actlr_read_helper(); + if ((actlr & ALT_CPU_ACTLR_PARITYON_SET_MSK) == 0) + { + // Determine which caches which will be affected by parity being enabled + // are currently enabled. + bool dcache_en = alt_cache_l1_data_is_enabled(); + bool icache_en = alt_cache_l1_instruction_is_enabled(); + bool branch_en = alt_cache_l1_branch_is_enabled(); + + // For those caches, disable them temporarily + if (icache_en == true) + { + alt_cache_l1_instruction_disable(); + } + if (dcache_en == true) + { + alt_cache_l1_data_disable(); + } + if (branch_en == true) + { + alt_cache_l1_branch_disable(); + } + + // Turn on parity in the L1. + actlr |= ALT_CPU_ACTLR_PARITYON_SET_MSK; + actlr_write_helper(actlr); + + // Now enable them again. + if (icache_en == true) + { + alt_cache_l1_instruction_enable(); + } + if (dcache_en == true) + { + alt_cache_l1_data_enable(); + } + if (branch_en == true) + { + alt_cache_l1_branch_enable(); + } + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_parity_disable(void) +{ + uint32_t actlr = actlr_read_helper(); + actlr &= ~ALT_CPU_ACTLR_PARITYON_SET_MSK; + actlr_write_helper(actlr); + + return ALT_E_SUCCESS; +} + +bool alt_cache_l1_parity_is_enabled(void) +{ + uint32_t actlr = actlr_read_helper(); + if ((actlr & ALT_CPU_ACTLR_PARITYON_SET_MSK) != 0) + { + return true; + } + else + { + return false; + } +} + +ALT_STATUS_CODE alt_cache_l1_branch_enable(void) +{ + alt_cache_l1_branch_invalidate(); + + uint32_t sctlr = sctlr_read_helper(); + sctlr |= ALT_CPU_SCTLR_Z_SET_MSK; + sctlr_write_helper(sctlr); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_branch_disable(void) +{ + uint32_t sctlr = sctlr_read_helper(); + sctlr &= ~ALT_CPU_SCTLR_Z_SET_MSK; + sctlr_write_helper(sctlr); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void) +{ + // Issue BPIALLIS (Branch Predictor Invalidate ALL, Inner Shareable). + + uint32_t dummy = 0; + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, dummy, c7, c1, 6"); +#else + __asm("MCR p15, 0, %0, c7, c1, 6" : : "r" (dummy)); +#endif + + // Ensure all branch predictor maintenance operations complete before returning. + __asm("dsb"); + + return ALT_E_SUCCESS; +} + +bool alt_cache_l1_branch_is_enabled(void) +{ + uint32_t sctlr = sctlr_read_helper(); + if ((sctlr & ALT_CPU_SCTLR_Z_SET_MSK) != 0) + { + return true; + } + else + { + return false; + } +} + +ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void) +{ + uint32_t actlr = actlr_read_helper(); + actlr |= ALT_CPU_ACTLR_L1PREFETCHEN_SET_MSK; + actlr_write_helper(actlr); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void) +{ + uint32_t actlr = actlr_read_helper(); + actlr &= ~ALT_CPU_ACTLR_L1PREFETCHEN_SET_MSK; + actlr_write_helper(actlr); + + return ALT_E_SUCCESS; +} + +bool alt_cache_l1_prefetch_is_enabled(void) +{ + uint32_t actlr = actlr_read_helper(); + if ((actlr & ALT_CPU_ACTLR_L1PREFETCHEN_SET_MSK) != 0) + { + return true; + } + else + { + return false; + } +} + +///// + +// +// Stand-in SoCAL for MPU L2 registers. +// +// All offsets are from ALT_MPUL2_OFST. +// + +#define ALT_MPUL2_CACHE_ID_OFST 0x000 +#define ALT_MPUL2_CACHE_TYPE_OFST 0x004 +#define ALT_MPUL2_CONTROL_OFST 0x100 +#define ALT_MPUL2_AUX_CONTROL_OFST 0x104 +#define ALT_MPUL2_TAG_RAM_CONTROL_OFST 0x108 +#define ALT_MPUL2_DATA_RAM_CONTROL_OFST 0x10c +#define ALT_MPUL2_EV_COUNTER_CTRL_OFST 0x200 +#define ALT_MPUL2_EV_COUNTER1_CFG_OFST 0x204 +#define ALT_MPUL2_EV_COUNTER0_CFG_OFST 0x208 +#define ALT_MPUL2_EV_COUNTER1_OFST 0x20c +#define ALT_MPUL2_EV_COUNTER0_OFST 0x210 +#define ALT_MPUL2_INT_MASK_OFST 0x214 +#define ALT_MPUL2_INT_MASK_STATUS_OFST 0x218 +#define ALT_MPUL2_INT_RAW_STATUS_OFST 0x21c +#define ALT_MPUL2_INT_CLEAR_OFST 0x220 +#define ALT_MPUL2_CACHE_SYNC_OFST 0x730 +#define ALT_MPUL2_INV_PA_OFST 0x770 +#define ALT_MPUL2_INV_WAY_OFST 0x77c +#define ALT_MPUL2_CLEAN_PA_OFST 0x7b0 +#define ALT_MPUL2_CLEAN_INDEX_OFST 0x7b8 +#define ALT_MPUL2_CLEAN_WAY_OFST 0x7bc +#define ALT_MPUL2_CLEAN_INV_PA_OFST 0x7f0 +#define ALT_MPUL2_CLEAN_INV_INDEX_OFST 0x7f8 +#define ALT_MPUL2_CLEAN_INV_WAY_OFST 0x7fc +#define ALT_MPUL2_D_LOCKDOWN0_OFST 0x900 +#define ALT_MPUL2_I_LOCKDOWN0_OFST 0x904 +#define ALT_MPUL2_D_LOCKDOWN1_OFST 0x908 +#define ALT_MPUL2_I_LOCKDOWN1_OFST 0x90c +#define ALT_MPUL2_D_LOCKDOWN2_OFST 0x910 +#define ALT_MPUL2_I_LOCKDOWN2_OFST 0x914 +#define ALT_MPUL2_D_LOCKDOWN3_OFST 0x918 +#define ALT_MPUL2_I_LOCKDOWN3_OFST 0x91c +#define ALT_MPUL2_D_LOCKDOWN4_OFST 0x920 +#define ALT_MPUL2_I_LOCKDOWN4_OFST 0x924 +#define ALT_MPUL2_D_LOCKDOWN5_OFST 0x928 +#define ALT_MPUL2_I_LOCKDOWN5_OFST 0x92c +#define ALT_MPUL2_D_LOCKDOWN6_OFST 0x930 +#define ALT_MPUL2_I_LOCKDOWN6_OFST 0x934 +#define ALT_MPUL2_D_LOCKDOWN7_OFST 0x938 +#define ALT_MPUL2_I_LOCKDOWN7_OFST 0x93c +#define ALT_MPUL2_D_LOCKDOWNx_OFST(x) (0x900 + ((x) * 0x8)) +#define ALT_MPUL2_I_LOCKDOWNx_OFST(x) (0x904 + ((x) * 0x8)) +#define ALT_MPUL2_LOCK_LINE_EN_OFST 0x950 +#define ALT_MPUL2_UNLOCK_WAY_OFST 0x954 +#define ALT_MPUL2_ADDR_FILTERING_START_OFST 0xc00 +#define ALT_MPUL2_ADDR_FILTERING_END_OFST 0xc04 +#define ALT_MPUL2_DEBUG_CTRL_OFST 0xf40 +#define ALT_MPUL2_PREFETCH_CTRL_OFST 0xf60 +#define ALT_MPUL2_POWER_CTRL_OFST 0xf80 + +#define ALT_MPUL2_CACHE_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_CACHE_ID_OFST)) +#define ALT_MPUL2_CACHE_TYPE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_CACHE_TYPE_OFST)) +#define ALT_MPUL2_CONTROL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_CONTROL_OFST)) +#define ALT_MPUL2_AUX_CONTROL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_AUX_CONTROL_OFST)) +#define ALT_MPUL2_TAG_RAM_CONTROL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_TAG_RAM_CONTROL_OFST)) +#define ALT_MPUL2_DATA_RAM_CONTROL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_DATA_RAM_CONTROL_OFST)) +#define ALT_MPUL2_EV_COUNTER_CTRL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_EV_COUNTER_CTRL_OFST)) +#define ALT_MPUL2_EV_COUNTER1_CFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_EV_COUNTER1_CFG_OFST)) +#define ALT_MPUL2_EV_COUNTER0_CFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_EV_COUNTER0_CFG_OFST)) +#define ALT_MPUL2_EV_COUNTER1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_EV_COUNTER1_OFST)) +#define ALT_MPUL2_EV_COUNTER0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_EV_COUNTER0_OFST)) +#define ALT_MPUL2_INT_MASK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_INT_MASK_OFST)) +#define ALT_MPUL2_INT_MASK_STATUS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_INT_MASK_STATUS_OFST)) +#define ALT_MPUL2_INT_RAW_STATUS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_INT_RAW_STATUS_OFST)) +#define ALT_MPUL2_INT_CLEAR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_INT_CLEAR_OFST)) +#define ALT_MPUL2_CACHE_SYNC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_CACHE_SYNC_OFST)) +#define ALT_MPUL2_INV_PA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_INV_PA_OFST)) +#define ALT_MPUL2_INV_WAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_INV_WAY_OFST)) +#define ALT_MPUL2_CLEAN_PA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_CLEAN_PA_OFST)) +#define ALT_MPUL2_CLEAN_INDEX_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_CLEAN_INDEX_OFST)) +#define ALT_MPUL2_CLEAN_WAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_CLEAN_WAY_OFST)) +#define ALT_MPUL2_CLEAN_INV_PA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_CLEAN_INV_PA_OFST)) +#define ALT_MPUL2_CLEAN_INV_INDEX_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_CLEAN_INV_INDEX_OFST)) +#define ALT_MPUL2_CLEAN_INV_WAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_CLEAN_INV_WAY_OFST)) +#define ALT_MPUL2_D_LOCKDOWN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_D_LOCKDOWN0_OFST)) +#define ALT_MPUL2_I_LOCKDOWN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_I_LOCKDOWN0_OFST)) +#define ALT_MPUL2_D_LOCKDOWN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_D_LOCKDOWN1_OFST)) +#define ALT_MPUL2_I_LOCKDOWN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_I_LOCKDOWN1_OFST)) +#define ALT_MPUL2_D_LOCKDOWN2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_D_LOCKDOWN2_OFST)) +#define ALT_MPUL2_I_LOCKDOWN2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_I_LOCKDOWN2_OFST)) +#define ALT_MPUL2_D_LOCKDOWN3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_D_LOCKDOWN3_OFST)) +#define ALT_MPUL2_I_LOCKDOWN3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_I_LOCKDOWN3_OFST)) +#define ALT_MPUL2_D_LOCKDOWN4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_D_LOCKDOWN4_OFST)) +#define ALT_MPUL2_I_LOCKDOWN4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_I_LOCKDOWN4_OFST)) +#define ALT_MPUL2_D_LOCKDOWN5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_D_LOCKDOWN5_OFST)) +#define ALT_MPUL2_I_LOCKDOWN5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_I_LOCKDOWN5_OFST)) +#define ALT_MPUL2_D_LOCKDOWN6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_D_LOCKDOWN6_OFST)) +#define ALT_MPUL2_I_LOCKDOWN6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_I_LOCKDOWN6_OFST)) +#define ALT_MPUL2_D_LOCKDOWN7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_D_LOCKDOWN7_OFST)) +#define ALT_MPUL2_I_LOCKDOWN7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_I_LOCKDOWN7_OFST)) +#define ALT_MPUL2_D_LOCKDOWNx_ADDR(x) ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_D_LOCKDOWNx_OFST(x))) +#define ALT_MPUL2_I_LOCKDOWNx_ADDR(x) ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_I_LOCKDOWNx_OFST(x))) +#define ALT_MPUL2_LOCK_LINE_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_LOCK_LINE_EN_OFST)) +#define ALT_MPUL2_UNLOCK_WAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_UNLOCK_WAY_OFST)) +#define ALT_MPUL2_ADDR_FILTERING_START_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_ADDR_FILTERING_START_OFST)) +#define ALT_MPUL2_ADDR_FILTERING_END_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_ADDR_FILTERING_END_OFST)) +#define ALT_MPUL2_DEBUG_CTRL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_DEBUG_CTRL_OFST)) +#define ALT_MPUL2_PREFETCH_CTRL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_PREFETCH_CTRL_OFST)) +#define ALT_MPUL2_POWER_CTRL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_POWER_CTRL_OFST)) + +#define ALT_MPUL2_CONTROL_EN_SET_MSK (1 << 0) + +#define ALT_MPUL2_AUX_CONTROL_PARITY_EN_SET_MSK (1 << 21) +#define ALT_MPUL2_AUX_CONTROL_WAYSIZE_SET_MSK (7 << 17) +#define ALT_MPUL2_AUX_CONTROL_ASSOCIATIVITY_SET_MSK (1 << 16) +#define ALT_MPUL2_AUX_CONTROL_WAYSIZE_VALUE_GET(value) (((value) >> 17) & 0x7) +#define ALT_MPUL2_AUX_CONTROL_FULLLINEOFZERO_EN_SET_MSK (1 << 0) + +#define ALT_MPUL2_TAG_RAM_CONTROL_WRITE_LATENCY_VALUE_GET(value) (((value) >> 8) & 0x7) +#define ALT_MPUL2_TAG_RAM_CONTROL_WRITE_LATENCY_VALUE_SET(value) (((value) & 0x7) << 8) +#define ALT_MPUL2_TAG_RAM_CONTROL_READ_LATENCY_VALUE_GET(value) (((value) >> 4) & 0x7) +#define ALT_MPUL2_TAG_RAM_CONTROL_READ_LATENCY_VALUE_SET(value) (((value) & 0x7) << 4) +#define ALT_MPUL2_TAG_RAM_CONTROL_SETUP_LATENCY_VALUE_GET(value) (((value) >> 0) & 0x7) +#define ALT_MPUL2_TAG_RAM_CONTROL_SETUP_LATENCY_VALUE_SET(value) (((value) & 0x7) << 0) + +#define ALT_MPUL2_DATA_RAM_CONTROL_WRITE_LATENCY_VALUE_GET(value) (((value) >> 8) & 0x7) +#define ALT_MPUL2_DATA_RAM_CONTROL_WRITE_LATENCY_VALUE_SET(value) (((value) & 0x7) << 8) +#define ALT_MPUL2_DATA_RAM_CONTROL_READ_LATENCY_VALUE_GET(value) (((value) >> 4) & 0x7) +#define ALT_MPUL2_DATA_RAM_CONTROL_READ_LATENCY_VALUE_SET(value) (((value) & 0x7) << 4) +#define ALT_MPUL2_DATA_RAM_CONTROL_SETUP_LATENCY_VALUE_GET(value) (((value) >> 0) & 0x7) +#define ALT_MPUL2_DATA_RAM_CONTROL_SETUP_LATENCY_VALUE_SET(value) (((value) & 0x7) << 0) + +#define ALT_MPUL2_PREFETCH_CTRL_I_PF_EN_SET_MSK (1 << 29) +#define ALT_MPUL2_PREFETCH_CTRL_D_PF_EN_SET_MSK (1 << 28) + +///// + +#define ALT_CACHE_L2_INTERRUPT_ALL (ALT_CACHE_L2_INTERRUPT_DECERR | \ + ALT_CACHE_L2_INTERRUPT_SLVERR | \ + ALT_CACHE_L2_INTERRUPT_ERRRD | \ + ALT_CACHE_L2_INTERRUPT_ERRRT | \ + ALT_CACHE_L2_INTERRUPT_ERRWD | \ + ALT_CACHE_L2_INTERRUPT_ERRWT | \ + ALT_CACHE_L2_INTERRUPT_PARRD | \ + ALT_CACHE_L2_INTERRUPT_PARRT | \ + ALT_CACHE_L2_INTERRUPT_ECNTR) + +///// + +static uint32_t alt_cache_l2_waymask = 0x0000ffff; + +ALT_STATUS_CODE alt_cache_l2_init(void) +{ + // Query the cache characteristics + + uint32_t auxctrl = alt_read_word(ALT_MPUL2_AUX_CONTROL_ADDR); + + if (auxctrl & ALT_MPUL2_AUX_CONTROL_ASSOCIATIVITY_SET_MSK) + { + alt_cache_l2_waymask = 0x0000ffff; + } + else + { + alt_cache_l2_waymask = 0x000000ff; + } + + ///// + + // Initialize the L2CC using instructions from L2C-310, section 3.1.1. + + // Write global configuration: + // - Associativity, way size + // - Latencies for RAM accesses + // - Allocation policy + // - Prefetch and power capability + // (Not needed as the associated lines are by default set to the instantiation parameters) + + // Invalidate by way all cache entries + // (Not needed as it will be invalidated when L2 is enabled) + + alt_write_word(ALT_MPUL2_TAG_RAM_CONTROL_ADDR, + ALT_MPUL2_TAG_RAM_CONTROL_WRITE_LATENCY_VALUE_SET(0) + | ALT_MPUL2_TAG_RAM_CONTROL_READ_LATENCY_VALUE_SET(0) + | ALT_MPUL2_TAG_RAM_CONTROL_SETUP_LATENCY_VALUE_SET(0)); + + alt_write_word(ALT_MPUL2_DATA_RAM_CONTROL_ADDR, + ALT_MPUL2_DATA_RAM_CONTROL_WRITE_LATENCY_VALUE_SET(0) + | ALT_MPUL2_DATA_RAM_CONTROL_READ_LATENCY_VALUE_SET(1) + | ALT_MPUL2_DATA_RAM_CONTROL_SETUP_LATENCY_VALUE_SET(0)); + + // Clear interrupts just in case. + alt_cache_l2_int_status_clear(ALT_CACHE_L2_INTERRUPT_ALL); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l2_uninit(void) +{ + return ALT_E_SUCCESS; +} + +#define ALT_MPUL2_PREFETCH_CTRL_PF_EN_SET_MSK \ + (ALT_MPUL2_PREFETCH_CTRL_I_PF_EN_SET_MSK | ALT_MPUL2_PREFETCH_CTRL_D_PF_EN_SET_MSK) + +ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void) +{ + // Use the Prefetch Control Register instead of Aux Control. This is + // because the Prefetch Control can be changed while the L2 is enabled. + // For more information, see L2C-310, section 3.3.14. + + alt_setbits_word(ALT_MPUL2_PREFETCH_CTRL_ADDR, ALT_MPUL2_PREFETCH_CTRL_PF_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void) +{ + // Use the Prefetch Control Register instead of Aux Control. This is + // because the Prefetch Control can be changed while the L2 is enabled. + // For more information, see L2C-310, section 3.3.14. + + alt_clrbits_word(ALT_MPUL2_PREFETCH_CTRL_ADDR, ALT_MPUL2_PREFETCH_CTRL_PF_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +bool alt_cache_l2_prefetch_is_enabled(void) +{ + // Query the Prefetch Control Register. + // For more information, see L2C-310, section 3.3.14. + + uint32_t pfctrl = alt_read_word(ALT_MPUL2_PREFETCH_CTRL_ADDR); + + if ((pfctrl & ALT_MPUL2_PREFETCH_CTRL_PF_EN_SET_MSK) == ALT_MPUL2_PREFETCH_CTRL_PF_EN_SET_MSK) + { + return true; + } + else + { + return false; + } +} + +ALT_STATUS_CODE alt_cache_l2_parity_enable(void) +{ + bool l2_enabled = alt_cache_l2_is_enabled(); + + if (l2_enabled) + { + alt_cache_l2_disable(); + } + + alt_setbits_word(ALT_MPUL2_AUX_CONTROL_ADDR, ALT_MPUL2_AUX_CONTROL_PARITY_EN_SET_MSK); + + if (l2_enabled) + { + alt_cache_l2_enable(); + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l2_parity_disable(void) +{ + alt_clrbits_word(ALT_MPUL2_AUX_CONTROL_ADDR, ALT_MPUL2_AUX_CONTROL_PARITY_EN_SET_MSK); + return ALT_E_SUCCESS; +} + +bool alt_cache_l2_parity_is_enabled(void) +{ + uint32_t auxctrl = alt_read_word(ALT_MPUL2_AUX_CONTROL_ADDR); + if ((auxctrl & ALT_MPUL2_AUX_CONTROL_PARITY_EN_SET_MSK) == ALT_MPUL2_AUX_CONTROL_PARITY_EN_SET_MSK) + { + return true; + } + else + { + return false; + } +} + +ALT_STATUS_CODE alt_cache_l2_enable(void) +{ + if (!alt_cache_l2_is_enabled()) + { + alt_cache_l2_invalidate_all(); + alt_write_word(ALT_MPUL2_CONTROL_ADDR, ALT_MPUL2_CONTROL_EN_SET_MSK); + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l2_disable(void) +{ + if (alt_cache_l2_is_enabled()) + { + alt_cache_l2_purge_all(); + alt_write_word(ALT_MPUL2_CONTROL_ADDR, 0); + } + + return ALT_E_SUCCESS; +} + +bool alt_cache_l2_is_enabled(void) +{ + uint32_t ctrl = alt_read_word(ALT_MPUL2_CONTROL_ADDR); + if ((ctrl & ALT_MPUL2_CONTROL_EN_SET_MSK) != 0) + { + return true; + } + else + { + return false; + } +} + +// +// Common cache maintenance operation register formats +// + +#define ALT_MPUL2_COMMON_PA_TAG_SET_MSK (0xfffff << 12) +#define ALT_MPUL2_COMMON_PA_INDEX_SET_MSK (0x7f << 5) +#define ALT_MPUL2_COMMON_PA_C_SET_MSK (0x1 << 0) + +#define ALT_MPUL2_COMMON_INDEXWAY_WAY_SET_MSK (0xf << 28) +#define ALT_MPUL2_COMMON_INDEXWAY_INDEX_SET_MSK (0x7f << 5) +#define ALT_MPUL2_COMMON_INDEXWAY_C_SET_MSK (0x1 << 0) + +#define ALT_MPUL2_COMMON_SYNC_C_SET_MSK (1 << 0) + +#define ALT_MPUL2_COMMON_WAY_WAY_SET_MSK (0xffff << 0) + +///// + +// Timeouts for various L2 cache maintenance operations. +// The ranges of the operations can be determined by enabling debug printing. +#define ALT_CACHE_L2_SYNC_TIMEOUT 128 + +#define ALT_CACHE_L2_INVALIDATE_ALL_TIMEOUT 4096 +#define ALT_CACHE_L2_CLEAN_ALL_TIMEOUT 65536 +#define ALT_CACHE_L2_PURGE_ALL_TIMEOUT 65536 + +#define ALT_CACHE_L2_INVALIDATE_ADDR_TIMEOUT 128 +#define ALT_CACHE_L2_CLEAN_ADDR_TIMEOUT 128 +#define ALT_CACHE_L2_PURGE_ADDR_TIMEOUT 128 + +ALT_STATUS_CODE alt_cache_l2_sync(void) +{ + // Issue cache sync command, then wait for it to complete by polling the same register. + // For more information, see L2C-310, section 3.3.10. + + alt_write_word(ALT_MPUL2_CACHE_SYNC_ADDR, 0); + + int i = 0; + + while (alt_read_word(ALT_MPUL2_CACHE_SYNC_ADDR)) + { + // Atomic operation still in progress. + + if (i == ALT_CACHE_L2_SYNC_TIMEOUT) + { + return ALT_E_TMO; + } + ++i; + } + + dprintf("DEBUG[cache][l2]: L2 Sync time = %d.\n", i); + + return ALT_E_SUCCESS; +} + +static ALT_STATUS_CODE alt_cache_l2_invalidate_helper(uintptr_t paddress, size_t length) +{ + int i = 0; + int seg = 0; + + // For each stride: Issue invalidate line by PA command, then wait for it + // to complete by polling the same register. + // For more information, see L2C-310, section 3.3.10. + + for (uintptr_t pa = paddress; pa < paddress + length; pa += ALT_CACHE_LINE_SIZE) + { + alt_write_word(ALT_MPUL2_INV_PA_ADDR, pa); + + ++seg; + } + + while (alt_read_word(ALT_MPUL2_INV_PA_ADDR)) + { + // Atomic operation still in progress. + + if (i == ALT_CACHE_L2_INVALIDATE_ADDR_TIMEOUT) + { + return ALT_E_TMO; + } + ++i; + } + + dprintf("DEBUG[cache][l2]: L2 Invalidate PA time = %d for %d segment(s)\n", i, seg); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length) +{ + // Verify preconditions: + // - length is non-zero + // - address and length are on the cache boundaries + if (length == 0) + { + return ALT_E_BAD_ARG; + } + if (((uintptr_t)paddress & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + if ((length & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + + return alt_cache_l2_invalidate_helper((uintptr_t)paddress, length); +} + +ALT_STATUS_CODE alt_cache_l2_invalidate_all(void) +{ + // Invalidate by way, all ways. + // For more information, see L2C-310, section 3.3.10. + + alt_write_word(ALT_MPUL2_INV_WAY_ADDR, alt_cache_l2_waymask); + + int i = 0; + + while (alt_read_word(ALT_MPUL2_INV_WAY_ADDR)) + { + // Background operation still in progress. + + if (i == ALT_CACHE_L2_INVALIDATE_ALL_TIMEOUT) + { + return ALT_E_TMO; + } + ++i; + } + + dprintf("DEBUG[cache][l2]: L2 Invalidate All time = %d.\n", i); + + return ALT_E_SUCCESS; +} + +static ALT_STATUS_CODE alt_cache_l2_clean_helper(uintptr_t paddress, size_t length) +{ + int i = 0; + int seg = 0; + + // For each stride: Issue clean line by PA command, then wait for it to + // complete by polling the same register. + // For more information, see L2C-310, section 3.3.10. + + for (uintptr_t pa = paddress; pa < paddress + length; pa += ALT_CACHE_LINE_SIZE) + { + alt_write_word(ALT_MPUL2_CLEAN_PA_ADDR, pa); + + ++seg; + } + + while (alt_read_word(ALT_MPUL2_CLEAN_PA_ADDR) & ALT_MPUL2_COMMON_PA_C_SET_MSK) + { + // Atomic operation still in progress. + + if (i == ALT_CACHE_L2_CLEAN_ADDR_TIMEOUT) + { + return ALT_E_TMO; + } + ++i; + } + + dprintf("DEBUG[cache][l2]: L2 Clean PA time = %d for %d segment(s)\n", i, seg); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length) +{ + // Verify preconditions: + // - length is non-zero + // - address and length are on the cache boundaries + if (length == 0) + { + return ALT_E_BAD_ARG; + } + if (((uintptr_t)paddress & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + if ((length & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + + return alt_cache_l2_clean_helper((uintptr_t)paddress, length); +} + +ALT_STATUS_CODE alt_cache_l2_clean_all(void) +{ + // Clean by way, all ways. + // For more information, see L2C-310, section 3.3.10. + + alt_write_word(ALT_MPUL2_CLEAN_WAY_ADDR, alt_cache_l2_waymask); + + int i = 0; + + while (alt_read_word(ALT_MPUL2_CLEAN_WAY_ADDR)) + { + // Background operation still in progress. + + if (i == ALT_CACHE_L2_CLEAN_ALL_TIMEOUT) + { + return ALT_E_TMO; + } + ++i; + } + + dprintf("DEBUG[cache][l2]: L2 Invalidate All time = %d.\n", i); + + return ALT_E_SUCCESS; +} + +static ALT_STATUS_CODE alt_cache_l2_purge_helper(uintptr_t paddress, size_t length) +{ + int i = 0; + int seg = 0; + + // For each stride: Issue clean and invalidate line by PA command, then + // wait for it to complete by polling the same register. + // For more information, see L2C-310, section 3.3.10. + + for (uintptr_t pa = paddress; pa < paddress + length; pa += ALT_CACHE_LINE_SIZE) + { + alt_write_word(ALT_MPUL2_CLEAN_INV_PA_ADDR, pa); + + ++seg; + } + + while (alt_read_word(ALT_MPUL2_CLEAN_INV_PA_ADDR) & ALT_MPUL2_COMMON_PA_C_SET_MSK) + { + // Atomic operation still in progress. + + if (i == ALT_CACHE_L2_PURGE_ADDR_TIMEOUT) + { + return ALT_E_TMO; + } + ++i; + } + + dprintf("DEBUG[cache][l2]: L2 Purge PA time = %d for %d segment(s)\n", i, seg); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length) +{ + // Verify preconditions: + // - length is non-zero + // - address and length are on the cache boundaries + if (length == 0) + { + return ALT_E_BAD_ARG; + } + if (((uintptr_t)paddress & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + if ((length & (ALT_CACHE_LINE_SIZE - 1)) != 0) + { + return ALT_E_BAD_ARG; + } + + return alt_cache_l2_purge_helper((uintptr_t)paddress, length); +} + +ALT_STATUS_CODE alt_cache_l2_purge_all(void) +{ + // Clean and invalidate by way, all ways. + // For more information, see L2C-310, section 3.3.10. + + alt_write_word(ALT_MPUL2_CLEAN_INV_WAY_ADDR, alt_cache_l2_waymask); + + int i = 0; + + while (alt_read_word(ALT_MPUL2_CLEAN_INV_WAY_ADDR)) + { + // Background operation still in progress. + + if (i == ALT_CACHE_L2_PURGE_ALL_TIMEOUT) + { + return ALT_E_TMO; + } + ++i; + } + + dprintf("DEBUG[cache][l2]: L2 Purge All time = %d.\n", i); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt) +{ + // Validate the interrupt mask + if ((interrupt & ALT_CACHE_L2_INTERRUPT_ALL) == 0) + { + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_MPUL2_INT_MASK_ADDR, interrupt); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt) +{ + // Validate the interrupt mask + if ((interrupt & ALT_CACHE_L2_INTERRUPT_ALL) == 0) + { + return ALT_E_BAD_ARG; + } + + alt_clrbits_word(ALT_MPUL2_INT_MASK_ADDR, interrupt); + return ALT_E_SUCCESS; +} + +uint32_t alt_cache_l2_int_status_get(void) +{ + return alt_read_word(ALT_MPUL2_INT_MASK_STATUS_ADDR); +} + +ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt) +{ + // Validate the interrupt mask + if ((interrupt & ALT_CACHE_L2_INTERRUPT_ALL) == 0) + { + return ALT_E_BAD_ARG; + } + + alt_write_word(ALT_MPUL2_INT_CLEAR_ADDR, interrupt); + return ALT_E_SUCCESS; +} + +///// + +__attribute__((weak)) ALT_STATUS_CODE alt_int_dist_pending_clear(ALT_INT_INTERRUPT_t int_id) +{ + return ALT_E_SUCCESS; +} + +inline static uint32_t get_current_cpu_num(void) +{ + uint32_t affinity; + + // Use the MPIDR. This is only available at PL1 or higher. + // See ARMv7, section B4.1.106. + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, affinity, c0, c0, 5"); +#else + __asm("MRC p15, 0, %0, c0, c0, 5" : "=r" (affinity)); +#endif + + return affinity & 0xFF; +} + +ALT_STATUS_CODE alt_cache_l2_ecc_start(void * block, size_t size) +{ + uint32_t way_size = (8 * 1024) << ALT_MPUL2_AUX_CONTROL_WAYSIZE_VALUE_GET(alt_read_word(ALT_MPUL2_AUX_CONTROL_ADDR)); + + // Add 32 KiB to the scrubbing size to account for effects of the L1 on scrubbing. + uint32_t scrub_way_size = way_size + (32 * 1024); + + if (size < scrub_way_size) + { + return ALT_E_ERROR; + } + + if (alt_cache_l2_is_enabled() == false) + { + return ALT_E_ERROR; + } + + ///// + + bool l1_icache = false; + bool l1_prefetch = false; + bool l2_prefetch = false; + + if (alt_cache_l1_instruction_is_enabled() == true) + { + l1_icache = true; + alt_cache_l1_instruction_disable(); + } + + if (alt_cache_l1_prefetch_is_enabled() == true) + { + l1_prefetch = true; + alt_cache_l1_prefetch_disable(); + } + + if (alt_cache_l2_prefetch_is_enabled() == true) + { + l2_prefetch = true; + alt_cache_l2_prefetch_disable(); + } + + // inline'ed alt_cache_l2_disable(); // This will invalidate all L2 entries + alt_cache_l2_purge_all(); + alt_write_word(ALT_MPUL2_CONTROL_ADDR, 0); + + // Enable "Full line of zero" feature of the L2C. + // See L2C-310, section 2.5.5, "Full line of zero write". + alt_setbits_word(ALT_MPUL2_AUX_CONTROL_ADDR, ALT_MPUL2_AUX_CONTROL_FULLLINEOFZERO_EN_SET_MSK); + + // ECC should be enabled before L2 is enabled. (NPP MPU, section 4.3, item 1) + alt_write_word(ALT_SYSMGR_ECC_L2_ADDR, ALT_SYSMGR_ECC_L2_EN_SET_MSK); + + // inline'ed alt_cache_l2_enable(); + // No need to invalidate all; the previous L2 disable should have purged everything. + alt_write_word(ALT_MPUL2_CONTROL_ADDR, ALT_MPUL2_CONTROL_EN_SET_MSK); + + // Enable "Full line of zero" feature of the A9. + // See Cortex-A9 TRM, section 4.3.10. + actlr_write_helper(actlr_read_helper() | ALT_CPU_ACTLR_WRITEFULLLINEZEROS_SET_MSK); + + ///// + + uint32_t cpu_affinity = get_current_cpu_num(); + + // Loop through all ways for the lock by master configuration. + int way_count = (alt_cache_l2_waymask == 0x0000ffff) ? 16 : 8; + + for (int way_lock = 0; way_lock < way_count; ++way_lock) + { + // Lock the current way for Data and Instruction. + alt_write_word(ALT_MPUL2_D_LOCKDOWNx_ADDR(cpu_affinity), ~(1 << way_lock) & alt_cache_l2_waymask); + alt_write_word(ALT_MPUL2_I_LOCKDOWNx_ADDR(cpu_affinity), ~(1 << way_lock) & alt_cache_l2_waymask); + + // Invalidate All. This will ensure that scrubbing RAM contents does not exist in a different way. + alt_cache_l2_invalidate_all(); + + // Loop through all words in the block + register uint32_t * block2 = block; + for (register int i = 0; i < (scrub_way_size / sizeof(*block2)); i++) + { + *block2 = 0; + ++block2; + } + + // Don't put the DSB inside the loop. It will disallow the [full line of zero] optimization. + __asm("dsb"); + } + + // Unlock the way lock by master for the current CPU. + alt_write_word(ALT_MPUL2_D_LOCKDOWNx_ADDR(cpu_affinity), 0); + alt_write_word(ALT_MPUL2_I_LOCKDOWNx_ADDR(cpu_affinity), 0); + + if (l1_icache) + { + alt_cache_l1_instruction_enable(); + } + + if (l1_prefetch) + { + alt_cache_l1_prefetch_enable(); + } + + if (l2_prefetch) + { + alt_cache_l2_prefetch_enable(); + } + + alt_int_dist_pending_clear(ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ); + alt_int_dist_pending_clear(ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ); + alt_int_dist_pending_clear(ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ); + + return ALT_E_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_clock_manager.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_clock_manager.c new file mode 100644 index 000000000..0e1db8234 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_clock_manager.c @@ -0,0 +1,5556 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include +#include +#include + +#include "socal/hps.h" +#include "socal/socal.h" +#include "socal/alt_sysmgr.h" +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "alt_mpu_registers.h" + +#define UINT12_MAX (4096) + +#define printf( ... ) + +/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ +/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Useful Structures ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ +/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ + + + /* General structure used to hold parameters of various clock entities, */ +typedef struct ALT_CLK_PARAMS_s +{ + alt_freq_t freqcur; // current frequency of the clock + alt_freq_t freqmin; // minimum allowed frequency for this clock + alt_freq_t freqmax; // maximum allowed frequency for this clock + uint32_t guardband : 7; // guardband percentage (0-100) if this clock + // is a PLL, ignored otherwise + uint32_t active : 1; // current state of activity of this clock +} ALT_CLK_PARAMS_t; + + +typedef struct ALT_EXT_CLK_PARAMBLOK_s +{ + ALT_CLK_PARAMS_t clkosc1; // ALT_CLK_OSC1 + ALT_CLK_PARAMS_t clkosc2; // ALT_CLK_OSC2 + ALT_CLK_PARAMS_t periph; // ALT_CLK_F2H_PERIPH_REF + ALT_CLK_PARAMS_t sdram; // ALT_CLK_F2H_SDRAM_REF +} ALT_EXT_CLK_PARAMBLOK_t; + + + /* Initializes the External Clock Frequency Limits block */ + /* The first field is the current external clock frequency, and can be set by */ + /* alt_clk_ext_clk_freq_set(), the second and third fields are the minimum and */ + /* maximum frequencies, the fourth field is ignored, and the fifth field */ + /* contains the current activity state of the clock, 1=active, 0=inactive. */ + /* Values taken from Section 2.3 and Section 2.7.1 of the HHP HPS-Clocking */ + /* NPP specification. */ +static ALT_EXT_CLK_PARAMBLOK_t alt_ext_clk_paramblok = +{ + { 25000000, 10000000, 50000000, 0, 1 }, + { 25000000, 10000000, 50000000, 0, 1 }, + { 0, 10000000, 50000000, 0, 1 }, + { 0, 10000000, 50000000, 0, 1 } +}; + + + /* PLL frequency limits */ +typedef struct ALT_PLL_CLK_PARAMBLOK_s +{ + ALT_CLK_PARAMS_t MainPLL_600; // Main PLL values for 600 MHz SoC + ALT_CLK_PARAMS_t PeriphPLL_600; // Peripheral PLL values for 600 MHz SoC + ALT_CLK_PARAMS_t SDRAMPLL_600; // SDRAM PLL values for 600 MHz SoC + ALT_CLK_PARAMS_t MainPLL_800; // Main PLL values for 800 MHz SoC + ALT_CLK_PARAMS_t PeriphPLL_800; // Peripheral PLL values for 800 MHz SoC + ALT_CLK_PARAMS_t SDRAMPLL_800; // SDRAM PLL values for 800 MHz SoC +} ALT_PLL_CLK_PARAMBLOK_t; + + + /* Initializes the PLL frequency limits block */ + /* The first field is the current frequency, the second and third fields */ + /* are the design limits of the PLLs as listed in Section 3.2.1.2 of the */ + /* HHP HPS-Clocking NPP document. The fourth field of each line is the */ + /* guardband percentage, and the fifth field of each line is the current */ + /* state of the PLL, 1=active, 0=inactive. */ +#define ALT_ORIGINAL_GUARDBAND_VAL 20 +#define ALT_GUARDBAND_LIMIT 20 + +static ALT_PLL_CLK_PARAMBLOK_t alt_pll_clk_paramblok = +{ + { 0, 320000000, 1200000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 900000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 800000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 }, + { 0, 320000000, 1600000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 }, + { 0, 320000000, 1250000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 }, + { 0, 320000000, 1066000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 } +}; + + + /* PLL counter frequency limits */ +typedef struct ALT_PLL_CNTR_FREQMAX_s +{ + alt_freq_t MainPLL_C0; // Main PLL Counter 0 parameter block + alt_freq_t MainPLL_C1; // Main PLL Counter 1 parameter block + alt_freq_t MainPLL_C2; // Main PLL Counter 2 parameter block + alt_freq_t MainPLL_C3; // Main PLL Counter 3 parameter block + alt_freq_t MainPLL_C4; // Main PLL Counter 4 parameter block + alt_freq_t MainPLL_C5; // Main PLL Counter 5 parameter block + alt_freq_t PeriphPLL_C0; // Peripheral PLL Counter 0 parameter block + alt_freq_t PeriphPLL_C1; // Peripheral PLL Counter 1 parameter block + alt_freq_t PeriphPLL_C2; // Peripheral PLL Counter 2 parameter block + alt_freq_t PeriphPLL_C3; // Peripheral PLL Counter 3 parameter block + alt_freq_t PeriphPLL_C4; // Peripheral PLL Counter 4 parameter block + alt_freq_t PeriphPLL_C5; // Peripheral PLL Counter 5 parameter block + alt_freq_t SDRAMPLL_C0; // SDRAM PLL Counter 0 parameter block + alt_freq_t SDRAMPLL_C1; // SDRAM PLL Counter 1 parameter block + alt_freq_t SDRAMPLL_C2; // SDRAM PLL Counter 2 parameter block + alt_freq_t SDRAMPLL_C5; // SDRAM PLL Counter 5 parameter block +} ALT_PLL_CNTR_FREQMAX_t; + +// +// The following pll max frequency array statically defined must be recalculated each time +// when powering up, by calling alt_clk_clkmgr_init() +// +// for 14.1 uboot preloader, the following values are calculated dynamically. +// +// Arrial 5 +// alt_pll_cntr_maxfreq.MainPLL_C0 = 1050000000 +// alt_pll_cntr_maxfreq.MainPLL_C1 = 350000000 +// alt_pll_cntr_maxfreq.MainPLL_C2 = 262500000 +// alt_pll_cntr_maxfreq.MainPLL_C3 = 350000000 +// alt_pll_cntr_maxfreq.MainPLL_C4 = 2050781 +// alt_pll_cntr_maxfreq.MainPLL_C5 = 116666666 +// alt_pll_cntr_maxfreq.PeriphPLL_C0 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C1 = 250000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C2 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C3 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C4 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C5 = 1953125 +// alt_pll_cntr_maxfreq.SDRAMPLL_C0 = 533333333 +// alt_pll_cntr_maxfreq.SDRAMPLL_C1 = 1066666666 +// alt_pll_cntr_maxfreq.SDRAMPLL_C2 = 533333333 +// alt_pll_cntr_maxfreq.SDRAMPLL_C5 = 177777777 + +// Cyclone V +// alt_pll_cntr_maxfreq.MainPLL_C0 = 925000000 +// alt_pll_cntr_maxfreq.MainPLL_C1 = 370000000 +// alt_pll_cntr_maxfreq.MainPLL_C2 = 462500000 +// alt_pll_cntr_maxfreq.MainPLL_C3 = 370000000 +// alt_pll_cntr_maxfreq.MainPLL_C4 = 3613281 +// alt_pll_cntr_maxfreq.MainPLL_C5 = 123333333 +// alt_pll_cntr_maxfreq.PeriphPLL_C0 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C1 = 250000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C2 = 1953125 +// alt_pll_cntr_maxfreq.PeriphPLL_C3 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C4 = 200000000 +// alt_pll_cntr_maxfreq.PeriphPLL_C5 = 1953125 +// alt_pll_cntr_maxfreq.SDRAMPLL_C0 = 400000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C1 = 800000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C2 = 400000000 +// alt_pll_cntr_maxfreq.SDRAMPLL_C5 = 133333333 + + +/* Initializes the PLL Counter output maximum frequency block */ +static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = +{ + 800000000, /* Main PLL Outputs */ + 400000000, + 400000000, + 432000000, + 250000000, + 125000000, + 250000000, /* Peripheral PLL Outputs */ + 250000000, + 432000000, + 250000000, + 200000000, + 100000000, /* SDRAM PLL Outputs */ + 533000000, + 1066000000, + 533000000, + 200000000 +}; + + + + /* Maximum multiply, divide, and counter divisor values for each PLL */ +#define ALT_CLK_PLL_MULT_MAX 4095 +#define ALT_CLK_PLL_DIV_MAX 63 +#define ALT_CLK_PLL_CNTR_MAX 511 + + + /* Definitions for the reset request and reset acknowledge bits */ + /* for each of the output counters for each of the PLLS */ +#define ALT_CLK_PLL_RST_BIT_C0 0x00000001 +#define ALT_CLK_PLL_RST_BIT_C1 0x00000002 +#define ALT_CLK_PLL_RST_BIT_C2 0x00000004 +#define ALT_CLK_PLL_RST_BIT_C3 0x00000008 +#define ALT_CLK_PLL_RST_BIT_C4 0x00000010 +#define ALT_CLK_PLL_RST_BIT_C5 0x00000020 + + + /* These are the bits that deal with PLL lock and this macro */ + /* defines a mask to test for bits outside of these */ +#define ALT_CLK_MGR_PLL_LOCK_BITS (ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK \ + & ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK \ + & ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK \ + & ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK \ + & ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK \ + & ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK) + + +// Undocumented register which determines clock dividers for main PLL C0, C1, and C2. These should be considered RO. +#define ALT_CLKMGR_ALTERA_OFST 0xe0 +#define ALT_CLKMGR_ALTERA_MPUCLK_OFST 0x0 +#define ALT_CLKMGR_ALTERA_MAINCLK_OFST 0x4 +#define ALT_CLKMGR_ALTERA_DBGATCLK_OFST 0x8 +#define ALT_CLKMGR_ALTERA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_ALTERA_OFST)) +#define ALT_CLKMGR_ALTERA_MPUCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_MPUCLK_OFST)) +#define ALT_CLKMGR_ALTERA_MAINCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_MAINCLK_OFST)) +#define ALT_CLKMGR_ALTERA_DBGATCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_DBGATCLK_OFST)) +#define ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +#define ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +#define ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) + +/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ +/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Utility functions ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ +/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ + + +/****************************************************************************************/ +/* alt_clk_mgr_wait() introduces a delay, not very exact, but very light in */ +/* implementation. Depending upon the optinization level, it will wait at least the */ +/* number of clock cycles specified in the cnt parameter, sometimes many more. The */ +/* reg parameter is set to a register or a memory location that was recently used (so */ +/* as to avoid accidently evicting a register and a recently-used cache line in favor */ +/* of one whose values are not actually needed.). The cnt parameter sets the number of */ +/* repeated volatile memory reads and so sets a minimum time delay measured in */ +/* mpu_clk cycles. If mpu_clk = osc1 clock (as in bypass mode), then this gives a */ +/* minimum osc1 clock cycle delay. */ +/****************************************************************************************/ + +inline static void alt_clk_mgr_wait(void* reg, uint32_t cnt) +{ + for (; cnt ; cnt--) + { + (void) alt_read_word(reg); + } +} + + /* Wait time constants */ + /* These values came from Section 4.9.4 of the HHP HPS-Clocking NPP document */ +#define ALT_SW_MANAGED_CLK_WAIT_CTRDIV 30 /* 30 or more MPU clock cycles */ +#define ALT_SW_MANAGED_CLK_WAIT_HWCTRDIV 40 +#define ALT_SW_MANAGED_CLK_WAIT_BYPASS 30 +#define ALT_SW_MANAGED_CLK_WAIT_SAFEREQ 30 +#define ALT_SW_MANAGED_CLK_WAIT_SAFEEXIT 30 +#define ALT_SW_MANAGED_CLK_WAIT_NANDCLK 8 /* 8 or more MPU clock cycles */ + + +#define ALT_BYPASS_TIMEOUT_CNT 50 + // arbitrary number until i find more info +#define ALT_TIMEOUT_PHASE_SYNC 300 + // how many loops to wait for the SDRAM clock to come around + // to zero and allow for writing a new divisor ratio to it + +ALT_STATUS_CODE alt_clk_plls_settle_wait(void) +{ + int32_t i = ALT_BYPASS_TIMEOUT_CNT; + bool nofini; + + do + { + nofini = alt_read_word(ALT_CLKMGR_STAT_ADDR) & ALT_CLKMGR_STAT_BUSY_SET_MSK; + } while (nofini && i--); + // wait until clocks finish transitioning and become stable again + return (i > 0) ? ALT_E_SUCCESS : ALT_E_ERROR; +} + +static ALT_STATUS_CODE alt_clk_pll_lock_wait(ALT_CLK_t pll, uint32_t timeout) +{ + uint32_t locked_mask = 0; + + if (pll == ALT_CLK_MAIN_PLL) { locked_mask = ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK; } + else if (pll == ALT_CLK_PERIPHERAL_PLL) { locked_mask = ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK; } + else if (pll == ALT_CLK_SDRAM_PLL) { locked_mask = ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK; } + else + { + return ALT_E_BAD_ARG; + } + + do + { + uint32_t int_status = alt_read_word(ALT_CLKMGR_INTER_ADDR); + if (int_status & locked_mask) + { + return ALT_E_SUCCESS; + } + + } while (timeout--); + + return ALT_E_TMO; +} + + /* Useful utility macro for checking if two values */ + /* are within a certain percentage of each other */ +#define alt_within_delta(ref, neu, prcnt) (((((neu) * 100)/(ref)) < (100 + (prcnt))) \ + && ((((neu) * 100)/(ref)) > (100 - (prcnt)))) + + + /* Flags to include or omit code sections */ +// There are four cases where there is a small possibility of producing clock +// glitches. Code has been added from an abundance of caution to prevent +// these glitches. If further testing shows that this extra code is not necessary +// under any conditions, it may be easily eliminated by clearing these flags. + +#define ALT_PREVENT_GLITCH_BYP true +// for PLL entering or leaving bypass +#define ALT_PREVENT_GLITCH_EXSAFE true +// for PLL exiting safe mode +#define ALT_PREVENT_GLITCH_CNTRRST true +// resets counter phase +#define ALT_PREVENT_GLITCH_CHGC1 true +// for changing Main PLL C1 counter + + + +/****************************************************************************************/ +/* Bare-bones utility function used to make the somewhat complex writes to the PLL */ +/* counter registers (the clock dividers) easier. No parameter-checking or */ +/* error-checking, this is a static to this file and invisible to Doxygen. */ +/****************************************************************************************/ + +static void alt_clk_pllcounter_write(void* vcoaddr, void* stataddr, void* cntraddr, + uint32_t val, uint32_t msk, uint32_t shift) +{ +#if ALT_PREVENT_GLITCH_CNTRRST + // this is here from an abundance of caution and it may not be necessary + // to put the counter in reset for this write + volatile uint32_t temp; + + alt_setbits_word(vcoaddr, msk << shift); // put the counter in reset + do + { + temp = alt_read_word(stataddr); + } while (!(temp & msk)); + + alt_write_word(cntraddr, val); + alt_clrbits_word(vcoaddr, msk << shift); // release counter reset + +#else // should we find out that resetting the counters as above is unnecessary + alt_write_word(cntraddr, val); +#endif +} + + +/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ +/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Main Functions ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ +/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ + + +/****************************************************************************************/ +/* alt_clk_lock_status_clear() clears assertions of one or more of the PLL lock status */ +/* conditions. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) +{ + if (lock_stat_mask & ( ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK + & ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK + & ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK + & ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK) + ) + { + return ALT_E_BAD_ARG; + } + else + { + alt_setbits_word(ALT_CLKMGR_INTER_ADDR, lock_stat_mask); + return ALT_E_SUCCESS; + } +} + + +/****************************************************************************************/ +/* alt_clk_lock_status_get() returns the value of the PLL lock status conditions. */ +/****************************************************************************************/ + +uint32_t alt_clk_lock_status_get(void) +{ + return alt_read_word(ALT_CLKMGR_INTER_ADDR) & ( ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK + | ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK + | ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK + | ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK + | ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK ); +} + + +/****************************************************************************************/ +/* alt_clk_pll_is_locked() returns ALT_E_TRUE if the designated PLL is currently */ +/* locked and ALT_E_FALSE if not. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll) +{ + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + + if (pll == ALT_CLK_MAIN_PLL) + { + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK) + ? ALT_E_TRUE : ALT_E_FALSE; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK) + ? ALT_E_TRUE : ALT_E_FALSE; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK) + ? ALT_E_TRUE : ALT_E_FALSE; + } + return status; +} + + +/****************************************************************************************/ +/* alt_clk_safe_mode_clear() clears the safe mode status of the Clock Manager following */ +/* a reset. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_clk_safe_mode_clear(void) +{ + ALT_STATUS_CODE status = ALT_E_ERROR; +#if ALT_PREVENT_GLITCH_EXSAFE + uint32_t temp; + + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & + (ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK)); + // gate off l4MP and L4SP clocks (no matter their source) + + alt_setbits_word(ALT_CLKMGR_CTL_ADDR, ALT_CLKMGR_CTL_SAFEMOD_SET_MSK); + // clear safe mode bit + status = alt_clk_plls_settle_wait(); + alt_replbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, + ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK, + temp); + // gate l4MP and L4SP clocks back on if they were on previously + +#else + alt_setbits_word(ALT_CLKMGR_CTL_ADDR, ALT_CLKMGR_CTL_SAFEMOD_SET_MSK); + // clear safe mode bit + status = alt_clk_plls_settle_wait(); + +#endif + return status; +} + + +/****************************************************************************************/ +/* alt_clk_is_in_safe_mode() returns whether the specified safe mode clock domain is in */ +/* safe mode or not. */ +/****************************************************************************************/ + +bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain) +{ + bool ret = false; + uint32_t temp; + + if (clk_domain == ALT_CLK_DOMAIN_NORMAL) + { + ret = alt_read_word(ALT_CLKMGR_CTL_ADDR) & ALT_CLKMGR_CTL_SAFEMOD_SET_MSK; + // is the main clock domain in safe mode? + } + else if (clk_domain == ALT_CLK_DOMAIN_DEBUG) + { + temp = alt_read_word(ALT_CLKMGR_DBCTL_ADDR); + if (temp & ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK) + { + ret = true; // is the debug clock domain in safe mode? + } + else if (temp & ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK) + { + ret = alt_read_word(ALT_CLKMGR_CTL_ADDR) & ALT_CLKMGR_CTL_SAFEMOD_SET_MSK; + // is the debug clock domain following the main clock domain + // AND is the main clock domain in safe mode? + } + } + return ret; +} + +/****************************************************************************************/ +/* alt_clk_pll_bypass_disable() disables bypass mode for the specified PLL, removing */ +/* it from bypass mode and allowing it to provide the output of the PLL to drive the */ +/* six main clocks. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll) +{ + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + uint32_t temp; +#if ALT_PREVENT_GLITCH_BYP + uint32_t temp1; + bool restore_0 = false; + bool restore_1 = false; +#endif + + // this function should only be called after the selected PLL is locked + if (alt_clk_pll_is_locked(pll) == ALT_E_TRUE) + { + if (pll == ALT_CLK_MAIN_PLL) + { +#if ALT_PREVENT_GLITCH_BYP + // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing + // bypass state, then gate clock back on. FogBugz #63778 + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) + { + restore_0 = true; + } + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) + { + restore_1 = true; + } + temp = temp1; + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } +#endif + + // assert outresetall of main PLL + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp | ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK); + + // deassert outresetall of main PLL + alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp & ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK); + + alt_clk_plls_settle_wait(); + + // remove bypass + alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); + status = alt_clk_plls_settle_wait(); + +#if ALT_PREVENT_GLITCH_BYP + if (restore_0 || restore_1) + { + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + // wait a bit more before reenabling the L4MP and L4SP clocks + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); + } +#endif + } + + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { +#if ALT_PREVENT_GLITCH_BYP + // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing + // bypass state, then gate clock back on. FogBugz #63778 + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK)) + { + restore_0 = true; + } + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK)) + { + restore_1 = true; + } + temp = temp1; + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } +#endif + + // assert outresetall of Peripheral PLL + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp | ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK); + alt_clk_plls_settle_wait(); + + // deassert outresetall of main PLL + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp & ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK); + + // remove bypass - don't think that there's any need to touch the bypass clock source + alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_PERPLL_SET_MSK); + status = alt_clk_plls_settle_wait(); + +#if ALT_PREVENT_GLITCH_BYP + if (restore_0 || restore_1) + { + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + // wait a bit more before reenabling the L4MP and L4SP clocks + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); + } +#endif + } + + else if (pll == ALT_CLK_SDRAM_PLL) + { + // assert outresetall of SDRAM PLL + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK); + + // deassert outresetall of main PLL + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp & ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK); + alt_clk_plls_settle_wait(); + + // remove bypass - don't think that there's any need to touch the bypass clock source + alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK); + status = alt_clk_plls_settle_wait(); + } + } + else + { + status = ALT_E_ERROR; + } + + return status; +} + + +/****************************************************************************************/ +/* alt_clk_pll_bypass_enable() enable bypass mode for the specified PLL. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux) +{ + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + uint32_t temp; +#ifdef ALT_PREVENT_GLITCH_BYP + uint32_t temp1; + bool restore_0 = false; + bool restore_1 = false; +#endif + + if (pll == ALT_CLK_MAIN_PLL) + { + if (!use_input_mux) + { +#ifdef ALT_PREVENT_GLITCH_BYP + // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing + // bypass state, then gate clock back on. FogBugz #63778 + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) + { + restore_0 = true; + } + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) + { + restore_1 = true; + } + temp = temp1; + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } + + alt_setbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); + // no input mux select on main PLL + + status = alt_clk_plls_settle_wait(); + // wait before reenabling the L4MP and L4SP clocks + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } + +#else + alt_setbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK); + // no input mux select on main PLL + status = alt_clk_plls_settle_wait(); + +#endif + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_BAD_ARG; + } + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { +#ifdef ALT_PREVENT_GLITCH_BYP + // if L4MP or L4SP source is set to Peripheral PLL C1, gate it off before changing + // bypass state, then gate clock back on. FogBugz #63778 + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK)) + { + restore_0 = true; + } + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK)) + { + restore_1 = true; + } + temp = temp1; + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } + + temp = alt_read_word(ALT_CLKMGR_BYPASS_ADDR) & + (ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK & ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK); + temp |= (use_input_mux) ? ALT_CLKMGR_BYPASS_PERPLL_SET_MSK | + ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK : ALT_CLKMGR_BYPASS_PERPLL_SET_MSK; + // set bypass bit and optionally the source select bit + + alt_write_word(ALT_CLKMGR_BYPASS_ADDR, temp); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + // wait a bit before reenabling the L4MP and L4SP clocks + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } + +#else + temp = alt_read_word(ALT_CLKMGR_BYPASS_ADDR) & + (ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK & ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK); + temp |= (use_input_mux) ? ALT_CLKMGR_BYPASS_PERPLL_SET_MSK | + ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK : ALT_CLKMGR_BYPASS_PERPLL_SET_MSK; + // set bypass bit and optionally the source select bit +#endif + status = ALT_E_SUCCESS; + } + + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_BYPASS_ADDR) & + (ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK & ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK); + temp |= (use_input_mux) ? ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK | + ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK : ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK; + // set bypass bit and optionally the source select bit + alt_write_word(ALT_CLKMGR_BYPASS_ADDR, temp); + status = ALT_E_SUCCESS; + } + return status; +} + + +/****************************************************************************************/ +/* alt_clk_pll_is_bypassed() returns whether the specified PLL is in bypass or not. */ +/* Bypass is a special state where the PLL VCO and the C0-C5 counters are bypassed */ +/* and not in the circuit. Either the Osc1 clock input or the input chosen by the */ +/* input mux may be selected to be operational in the bypass state. All changes to */ +/* the PLL VCO must be made in bypass mode to avoid the potential of producing clock */ +/* glitches which may affect downstream clock dividers and peripherals. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll) +{ + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + + if (pll == ALT_CLK_MAIN_PLL) + { + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + || ALT_CLKMGR_BYPASS_MAINPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + || ALT_CLKMGR_BYPASS_PERPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR)) + || ALT_CLKMGR_BYPASS_SDRPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + } + return status; +} + + +/****************************************************************************************/ +/* alt_clk_pll_source_get() returns the current input of the specified PLL. */ +/****************************************************************************************/ + +ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) +{ + ALT_CLK_t ret = ALT_CLK_UNKNOWN; + uint32_t temp; + + + if (pll == ALT_CLK_MAIN_PLL) + { + ret = ALT_CLK_IN_PIN_OSC1; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + // three possible clock sources for the peripheral PLL + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) + { + ret = ALT_CLK_IN_PIN_OSC1; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + ret = ALT_CLK_IN_PIN_OSC2; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + // three possible clock sources for the SDRAM PLL + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + ret = ALT_CLK_IN_PIN_OSC1; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + ret = ALT_CLK_IN_PIN_OSC2; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + ret = ALT_CLK_F2H_SDRAM_REF; + } + } + return ret; +} + +// +// alt_clk_clock_disable() disables the specified clock. Once the clock is disabled, +// its clock signal does not propagate to its clocked elements. +// +ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + switch (clk) + { + // For PLLs, put them in bypass mode. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = alt_clk_pll_bypass_enable(clk, false); + break; + + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); + break; + case ALT_CLK_L3_MP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); + break; + case ALT_CLK_L4_MP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + break; + case ALT_CLK_L4_SP: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + break; + case ALT_CLK_DBG_AT: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); + break; + case ALT_CLK_DBG: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); + break; + case ALT_CLK_DBG_TRACE: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); + break; + case ALT_CLK_DBG_TIMER: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); + break; + case ALT_CLK_CFG: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER0: + alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); + break; + + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); + break; + case ALT_CLK_EMAC1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); + break; + case ALT_CLK_USB_MP: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); + break; + case ALT_CLK_SPI_M: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); + break; + case ALT_CLK_CAN0: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); + break; + case ALT_CLK_CAN1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); + break; + case ALT_CLK_GPIO_DB: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER1: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); + break; + case ALT_CLK_SDMMC: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + break; + case ALT_CLK_NAND_X: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_clk off before nand_x_clk. + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + break; + case ALT_CLK_NAND: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + break; + case ALT_CLK_QSPI: + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + break; + + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_2X_DQS: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_DQ: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER2: + alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); + break; + + default: + status = ALT_E_BAD_ARG; + break; + } + + return status; +} + + +// +// alt_clk_clock_enable() enables the specified clock. Once the clock is enabled, its +// clock signal propagates to its elements. +// +ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + switch (clk) + { + // For PLLs, take them out of bypass mode. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = alt_clk_pll_bypass_disable(clk); + break; + + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK); + break; + case ALT_CLK_L3_MP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK); + break; + case ALT_CLK_L4_MP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + break; + case ALT_CLK_L4_SP: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + break; + case ALT_CLK_DBG_AT: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK); + break; + case ALT_CLK_DBG: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK); + break; + case ALT_CLK_DBG_TRACE: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK); + break; + case ALT_CLK_DBG_TIMER: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK); + break; + case ALT_CLK_CFG: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER0: + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK); + break; + + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK); + break; + case ALT_CLK_EMAC1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK); + break; + case ALT_CLK_USB_MP: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK); + break; + case ALT_CLK_SPI_M: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK); + break; + case ALT_CLK_CAN0: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK); + break; + case ALT_CLK_CAN1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK); + break; + case ALT_CLK_GPIO_DB: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER1: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK); + break; + case ALT_CLK_SDMMC: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + break; + case ALT_CLK_NAND_X: + // implementation detail - should ALK_CLK_NAND be gated off here before enabling ALT_CLK_NAND_X? + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + // implementation detail - should this wait be enforced here? + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + break; + case ALT_CLK_NAND: + // enabling ALT_CLK_NAND always implies enabling ALT_CLK_NAND_X first + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_x_clk on at least 8 MCU clocks before nand_clk + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + break; + case ALT_CLK_QSPI: + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + break; + + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_2X_DQS: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK); + break; + case ALT_CLK_DDR_DQ: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK); + break; + case ALT_CLK_H2F_USER2: + alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK); + break; + + default: + status = ALT_E_BAD_ARG; + break; + } + + return status; +} + +// +// alt_clk_is_enabled() returns whether the specified clock is enabled or not. +// +ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk) +{ + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + + switch (clk) + { + // For PLLs, this function checks if the PLL is bypassed or not. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_PERIPHERAL_PLL: + case ALT_CLK_SDRAM_PLL: + status = (alt_clk_pll_is_bypassed(clk) != ALT_E_TRUE); + break; + + // These clocks are not gated, so must return a ALT_E_BAD_ARG type error. + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_MPU: + case ALT_CLK_MPU_L2_RAM: + case ALT_CLK_MPU_PERIPH: + case ALT_CLK_L3_MAIN: + case ALT_CLK_L3_SP: + case ALT_CLK_DBG_BASE: + case ALT_CLK_MAIN_QSPI: + case ALT_CLK_MAIN_NAND_SDMMC: + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_SDRAM_PLL_C5: + status = ALT_E_BAD_ARG; + break; + + // Clocks that originate at the Main PLL. + case ALT_CLK_L4_MAIN: + status = (ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L3_MP: + status = (ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L4_MP: + status = (ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_L4_SP: + status = (ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_AT: + status = (ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG: + status = (ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_TRACE: + status = (ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DBG_TIMER: + status = (ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CFG: + status = (ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER0: + status = (ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + + // Clocks that originate at the Peripheral PLL. + case ALT_CLK_EMAC0: + status = (ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_EMAC1: + status = (ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_USB_MP: + status = (ALT_CLKMGR_PERPLL_EN_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_SPI_M: + status = (ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CAN0: + status = (ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_CAN1: + status = (ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_GPIO_DB: + status = (ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER1: + status = (ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + + // Clocks that may originate at the Main PLL, the Peripheral PLL, or the FPGA. + case ALT_CLK_SDMMC: + status = (ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_NAND_X: + status = (ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_NAND: + status = (ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_QSPI: + status = (ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + + // Clocks that originate at the SDRAM PLL. + case ALT_CLK_DDR_DQS: + status = (ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DDR_2X_DQS: + status = (ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_DDR_DQ: + status = (ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + case ALT_CLK_H2F_USER2: + status = (ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR))) + ? ALT_E_TRUE : ALT_E_FALSE; + break; + + default: + status = ALT_E_BAD_ARG; + break; + + } + + return status; +} + +// +// alt_clk_source_get() gets the input reference clock source selection value for the +// specified clock or PLL. +// +ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk) +{ + ALT_CLK_t ret = ALT_CLK_UNKNOWN; + uint32_t temp; + + switch (clk) + { + // Potential external clock sources. + // these clock entities are their own source + case ALT_CLK_IN_PIN_OSC1: + case ALT_CLK_IN_PIN_OSC2: + case ALT_CLK_F2H_PERIPH_REF: + case ALT_CLK_F2H_SDRAM_REF: + case ALT_CLK_IN_PIN_JTAG: + case ALT_CLK_IN_PIN_ULPI0: + case ALT_CLK_IN_PIN_ULPI1: + case ALT_CLK_IN_PIN_EMAC0_RX: + case ALT_CLK_IN_PIN_EMAC1_RX: + ret = clk; + break; + + // Phase-Locked Loops. + case ALT_CLK_MAIN_PLL: + case ALT_CLK_OSC1: + ret = ALT_CLK_IN_PIN_OSC1; + break; + case ALT_CLK_PERIPHERAL_PLL: + ret = alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL); + break; + case ALT_CLK_SDRAM_PLL: + ret = alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL); + break; + + // Main Clock Group. + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + // check bypass, return either osc1 or PLL ID + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL; + break; + + case ALT_CLK_MPU_PERIPH: + case ALT_CLK_MPU_L2_RAM: + case ALT_CLK_MPU: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C0; + break; + + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + case ALT_CLK_L3_MP: + case ALT_CLK_L3_SP: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + break; + + case ALT_CLK_L4_MP: + // read the state of the L4_mp source bit + if ((ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) + == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + } + else + { + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + } + break; + + case ALT_CLK_L4_SP: + // read the state of the source bit + if ((ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR))) + == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1; + } + else + { + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + } + break; + + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_AT: + case ALT_CLK_DBG_TRACE: + case ALT_CLK_DBG_TIMER: + case ALT_CLK_DBG: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C2; + break; + case ALT_CLK_MAIN_QSPI: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C3; + break; + case ALT_CLK_MAIN_NAND_SDMMC: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C4; + break; + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C5; + break; + + // Peripherals Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + // if the clock comes from periph_base_clk + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL; + break; + + case ALT_CLK_EMAC0: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C0; + break; + + case ALT_CLK_EMAC1: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C1; + break; + + case ALT_CLK_USB_MP: + case ALT_CLK_SPI_M: + case ALT_CLK_CAN0: + case ALT_CLK_CAN1: + case ALT_CLK_GPIO_DB: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4; + break; + + case ALT_CLK_H2F_USER1: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C5; + break; + + case ALT_CLK_SDMMC: + temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; + } + break; + + case ALT_CLK_NAND_X: + case ALT_CLK_NAND: + temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C3; + } + break; + + case ALT_CLK_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) + { + ret = ALT_CLK_F2H_PERIPH_REF; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ? + ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C3; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C2; + } + break; + + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_SDRAM_PLL_C3: + case ALT_CLK_SDRAM_PLL_C4: + case ALT_CLK_SDRAM_PLL_C5: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL; + break; + case ALT_CLK_DDR_DQS: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C0; + break; + case ALT_CLK_DDR_2X_DQS: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C1; + break; + case ALT_CLK_DDR_DQ: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C2; + break; + case ALT_CLK_H2F_USER2: + ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ? + alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) : ALT_CLK_SDRAM_PLL_C5; + break; + + // Clock Output Pins + case ALT_CLK_OUT_PIN_EMAC0_TX: + case ALT_CLK_OUT_PIN_EMAC1_TX: + case ALT_CLK_OUT_PIN_SDMMC: + case ALT_CLK_OUT_PIN_I2C0_SCL: + case ALT_CLK_OUT_PIN_I2C1_SCL: + case ALT_CLK_OUT_PIN_I2C2_SCL: + case ALT_CLK_OUT_PIN_I2C3_SCL: + case ALT_CLK_OUT_PIN_SPIM0: + case ALT_CLK_OUT_PIN_SPIM1: + case ALT_CLK_OUT_PIN_QSPI: + ret = ALT_CLK_UNKNOWN; + break; + + default: + ret = ALT_CLK_UNKNOWN; + break; + } + + return ret; +} + +// +// alt_clk_source_set() sets the specified clock's input reference clock source +// selection to the specified input. It does not handle gating the specified clock +// off and back on, those are covered in other functions in this API, but it does +// verify that the clock is off before changing the divider or PLL. Note that the PLL +// must have regained phase-lock before being the bypass is disabled. +// +ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; + + if (ALT_CLK_MAIN_PLL == clk) + { + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) + { + // ret = ALT_E_SUCCESS; + } + else + { + status = ALT_E_BAD_ARG; + } + } + else if (ALT_CLK_PERIPHERAL_PLL == clk) + { + // the PLL must be bypassed before getting here + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + temp &= ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; + + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) + { + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); + } + else if (ref_clk == ALT_CLK_IN_PIN_OSC2) + { + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); + } + else if (ref_clk == ALT_CLK_F2H_PERIPH_REF) + { + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); + } + else + { + status = ALT_E_INV_OPTION; + } + } + else if (ALT_CLK_SDRAM_PLL == clk) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + temp &= ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; + + if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1)) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); + } + else if (ref_clk == ALT_CLK_IN_PIN_OSC2) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); + } + else if (ref_clk == ALT_CLK_F2H_SDRAM_REF) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); + } + else + { + status = ALT_E_INV_OPTION; + } + } + else if ( ALT_CLK_L4_MP == clk) + { + // clock is gated off + if (ref_clk == ALT_CLK_MAIN_PLL_C1) + { + alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK); + } + else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4) + { + alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK); + } + else + { + status = ALT_E_INV_OPTION; + } + } + else if ( ALT_CLK_L4_SP == clk) + { + if (ref_clk == ALT_CLK_MAIN_PLL_C1) + { + alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK); + } + else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4) + { + alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK); + } + else + { + status = ALT_E_INV_OPTION; + } + } + else if (ALT_CLK_SDMMC == clk) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp &= ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK; + + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) + { + temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK); + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); + } + else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC)) + { + temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK); + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); + } + else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3) + { + temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); + } + else + { + status = ALT_E_INV_OPTION; + } + } + else if ((ALT_CLK_NAND_X == clk) || ( ALT_CLK_NAND == clk)) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp &= ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK; + + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) + { + temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK); + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); + } + else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC)) + { + temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK); + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); + } + else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3) + { + temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); + } + else + { + status = ALT_E_INV_OPTION; + } + } + else if (ALT_CLK_QSPI == clk) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp &= ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK; + + if (ref_clk == ALT_CLK_F2H_PERIPH_REF) + { + temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK); + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); + } + else if ((ref_clk == ALT_CLK_MAIN_PLL_C3) || (ref_clk == ALT_CLK_MAIN_QSPI)) + { + temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK); + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); + } + else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C2) + { + temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK); + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp); + } + else + { + status = ALT_E_INV_OPTION; + } + } + + return status; +} + +// +// alt_clk_ext_clk_freq_set() specifies the frequency of the external clock source as +// a measure of Hz. This value is stored in a static array and used for calculations. +// The supplied frequency should be within the Fmin and Fmax values allowed for the +// external clock source. +// +ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk, alt_freq_t freq) +{ + ALT_STATUS_CODE status = ALT_E_BAD_ARG; + + if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1)) // two names for one input + { + if ((freq >= alt_ext_clk_paramblok.clkosc1.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc1.freqmax)) + { + alt_ext_clk_paramblok.clkosc1.freqcur = freq; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; + } + } + else if (clk == ALT_CLK_IN_PIN_OSC2) // the other clock input pin + { + if ((freq >= alt_ext_clk_paramblok.clkosc2.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc2.freqmax)) + { + alt_ext_clk_paramblok.clkosc2.freqcur = freq; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; + } + } + else if (clk == ALT_CLK_F2H_PERIPH_REF) // clock from the FPGA + { + if ((freq >= alt_ext_clk_paramblok.periph.freqmin) && (freq <= alt_ext_clk_paramblok.periph.freqmax)) + { + alt_ext_clk_paramblok.periph.freqcur = freq; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; + } + } + else if (clk == ALT_CLK_F2H_SDRAM_REF) // clock from the FPGA SDRAM + { + if ((freq >= alt_ext_clk_paramblok.sdram.freqmin) && (freq <= alt_ext_clk_paramblok.sdram.freqmax)) + { + alt_ext_clk_paramblok.sdram.freqcur = freq; + status = ALT_E_SUCCESS; + } + else + { + status = ALT_E_ARG_RANGE; + } + } + else + { + status = ALT_E_BAD_ARG; + } + + return status; +} + + +// +// alt_clk_ext_clk_freq_get returns the frequency of the external clock source as +// a measure of Hz. This value is stored in a static array. +// +alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk) +{ + uint32_t ret = 0; + + if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1)) // two names for one input + { + ret = alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (clk == ALT_CLK_IN_PIN_OSC2) + { + ret = alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (clk == ALT_CLK_F2H_PERIPH_REF) // clock from the FPGA + { + ret = alt_ext_clk_paramblok.periph.freqcur; + } + else if (clk == ALT_CLK_F2H_SDRAM_REF) // clock from the FPGA + { + ret = alt_ext_clk_paramblok.sdram.freqcur; + } + return ret; +} + + +// +// alt_clk_pll_cfg_get() returns the current PLL configuration. +// +ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, ALT_CLK_PLL_CFG_t * pll_cfg) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // return value + uint32_t temp; // temp variable + + if (pll_cfg == NULL) + { + ret = ALT_E_BAD_ARG; + return ret; + } + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; + pll_cfg->mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + pll_cfg->div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); + + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)); + // C0 - mpu_clk + + pll_cfg->cntrs[1] = ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)); + // C1 - main_clk + + pll_cfg->cntrs[2] = ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)); + // C2 - dbg_base_clk + + pll_cfg->cntrs[3] = ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR)); + // C3 - main_qspi_clk + + pll_cfg->cntrs[4] = ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR)); + // C4 - main_nand_sdmmc_clk + + pll_cfg->cntrs[5] = ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR)); + // C5 - cfg_s2f_user0_clk aka cfg_h2f_user0_clk + + // The Main PLL C0-C5 outputs have no phase shift capabilities : + pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = + pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + if (temp <= 2) + { + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) + { + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + pll_cfg->ref_clk = ALT_CLK_F2H_PERIPH_REF; + } + + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + pll_cfg->mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + pll_cfg->div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); + + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR)); + // C0 - emac0_clk + + pll_cfg->cntrs[1] = ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR)); + // C1 - emac1_clk + + pll_cfg->cntrs[2] = ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR)); + // C2 - periph_qspi_clk + + pll_cfg->cntrs[3] = ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR)); + // C3 - periph_nand_sdmmc_clk + + pll_cfg->cntrs[4] = ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR)); + // C4 - periph_base_clk + + pll_cfg->cntrs[5] = ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR)); + // C5 - s2f_user1_clk + + // The Peripheral PLL C0-C5 outputs have no phase shift capabilities : + pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] = + pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0; + ret = ALT_E_SUCCESS; + } + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + if (temp <= 2) + { + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + pll_cfg->ref_clk = ALT_CLK_F2H_SDRAM_REF; + } + + pll_cfg->mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + pll_cfg->div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + + // Get the C0-C5 divider values: + pll_cfg->cntrs[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); + pll_cfg->pshift[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR)); + // C0 - ddr_dqs_clk + + pll_cfg->cntrs[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + pll_cfg->pshift[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR)); + // C1 - ddr_2x_dqs_clk + + pll_cfg->cntrs[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + pll_cfg->pshift[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR)); + // C2 - ddr_dq_clk + + pll_cfg->cntrs[3] = pll_cfg->cntrs[4] = pll_cfg->pshift[3] = pll_cfg->pshift[4] = 0; + // C3 & C4 outputs don't exist on the SDRAM PLL + + pll_cfg->cntrs[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + pll_cfg->pshift[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR)); + // C5 - s2f_user2_clk or h2f_user2_clk + + ret = ALT_E_SUCCESS; + } + } + + return ret; +} + + +// +// alt_clk_pll_cfg_set() sets the PLL configuration using the configuration parameters +// specified in pll_cfg. +// +ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, const ALT_CLK_PLL_CFG_t * pll_cfg) +{ + if (pll_cfg == NULL) + { + return ALT_E_BAD_ARG; + } + + if (alt_clk_pll_is_bypassed(pll) != ALT_E_TRUE) // safe to write the PLL registers? + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE ret = ALT_E_ERROR; + uint32_t temp; + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = (ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK) + & alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + temp |= ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(pll_cfg->mult) | + ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(pll_cfg->div); + + alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp); + alt_write_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR, pll_cfg->cntrs[0]); + alt_write_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR, pll_cfg->cntrs[1]); + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, pll_cfg->cntrs[2]); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, pll_cfg->cntrs[3]); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, pll_cfg->cntrs[4]); + alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, pll_cfg->cntrs[5]); + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK + & ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK; + temp &= alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + temp |= ALT_CLKMGR_PERPLL_VCO_NUMER_SET(pll_cfg->mult) + | ALT_CLKMGR_PERPLL_VCO_DENOM_SET(pll_cfg->div); + + if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) + { + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1); + } + else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) + { + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2); + } + else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) + { + temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF); + } + else + { + return ret; + } + + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, pll_cfg->cntrs[0]); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, pll_cfg->cntrs[1]); + alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, pll_cfg->cntrs[2]); + alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, pll_cfg->cntrs[3]); + alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, pll_cfg->cntrs[4]); + alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, pll_cfg->cntrs[5]); + ret = ALT_E_SUCCESS; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + // write the SDRAM PLL VCO Counter ----------------------------- + temp = ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK + & ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK; // make a mask + temp &= alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + temp |= ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(pll_cfg->mult) + | ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(pll_cfg->div) + | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK; + // setting this bit aligns the output phase of the counters and prevents + // glitches and too-short clock periods when restarting. + // this bit is cleared at the end of this routine + + if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1)) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1); + } + else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2); + } + else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF) + { + temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF); + } + else + { + return ret; + } + + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp); + + // write the SDRAM PLL C0 Divide Counter ----------------------------- + temp = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(pll_cfg->cntrs[0]) + | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(pll_cfg->pshift[0]); + + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + + // write the SDRAM PLL C1 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(pll_cfg->cntrs[1]) + | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(pll_cfg->pshift[1]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB); + } + + // write the SDRAM PLL C2 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(pll_cfg->cntrs[2]) + | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(pll_cfg->pshift[2]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB); + } + + // write the SDRAM PLL C5 Divide Counter ----------------------------- + if (ret == ALT_E_SUCCESS) + { + temp = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(pll_cfg->cntrs[2]) + | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(pll_cfg->pshift[2]); + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, temp, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB); + } + + if (ret == ALT_E_SUCCESS) + { + alt_clrbits_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK); + // allow the phase multiplexer and output counter to leave reset + } + } + + return ret; +} + + +// +// alt_clk_pll_vco_cfg_get() returns the current PLL VCO frequency configuration. +// +ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, uint32_t * mult, uint32_t * div) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; + + if ( (mult == NULL) || (div == NULL) ) + { + return ALT_E_BAD_ARG; + } + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + *mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp) + 1; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + *mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp) + 1; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + *mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp) + 1; + *div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp) + 1; + } + else + { + status = ALT_E_ERROR; + } + + return status; +} + + +/****************************************************************************************/ +/* This enum enumerates a set of possible change methods that are available for use by */ +/* alt_clk_pll_vco_cfg_set() to change VCO parameter settings. */ +/****************************************************************************************/ + +typedef enum ALT_CLK_PLL_VCO_CHG_METHOD_e +{ + ALT_VCO_CHG_NONE_VALID = 0, /* No valid method to change PLL + * VCO was found */ + ALT_VCO_CHG_NOCHANGE = 0x00000001, /* Proposed new VCO values are the + * same as the old values */ + ALT_VCO_CHG_NUM = 0x00000002, /* Can change the VCO multiplier + * alone */ + ALT_VCO_CHG_NUM_BYP = 0x00000004, /* A VCO multiplier-only change will + * require putting the PLL in bypass */ + ALT_VCO_CHG_DENOM = 0x00000008, /* Can change the VCO divider + * alone */ + ALT_VCO_CHG_DENOM_BYP = 0x00000010, /* A VCO divider-only change will + * require putting the PLL in bypass */ + ALT_VCO_CHG_NUM_DENOM = 0x00000020, /* Can change the clock multiplier + * first. then the clock divider */ + ALT_VCO_CHG_NUM_DENOM_BYP = 0x00000040, /* Changing the clock multiplier first. + * then the clock divider will + * require putting the PLL in bypass */ + ALT_VCO_CHG_DENOM_NUM = 0x00000080, /* Can change the clock divider first. + * then the clock multiplier */ + ALT_VCO_CHG_DENOM_NUM_BYP = 0x00000100 /* Changing the clock divider first. + * then the clock multiplier will + * require putting the PLL in bypass */ +} ALT_CLK_PLL_VCO_CHG_METHOD_t; + + + +/****************************************************************************************/ +/* alt_clk_pll_vco_chg_methods_get() determines which possible methods to change the */ +/* VCO are allowed within the limits set by the maximum PLL multiplier and divider */ +/* values and by the upper and lower frequency limits of the PLL, and also determines */ +/* whether each of these changes can be made without the PLL losing lock, which */ +/* requires the PLL to be bypassed before making changes, and removed from bypass state */ +/* afterwards. */ +/****************************************************************************************/ + + +#define ALT_CLK_PLL_VCO_CHG_METHOD_TEST_MODE false + // used for testing writes to the PLL VCOs + + + +static ALT_CLK_PLL_VCO_CHG_METHOD_t alt_clk_pll_vco_chg_methods_get(ALT_CLK_t pll, + uint32_t mult, uint32_t div ) +{ +#if ALT_CLK_PLL_VCO_CHG_METHOD_TEST_MODE + + // used for testing + return ALT_VCO_CHG_NOCHANGE; + +#else + + // check PLL max value limits + if ( (mult == 0) || (mult > ALT_CLK_PLL_MULT_MAX) + || (div == 0) || (div > ALT_CLK_PLL_DIV_MAX) + ) + { + return ALT_VCO_CHG_NONE_VALID; + } + + ALT_CLK_PLL_VCO_CHG_METHOD_t ret = ALT_VCO_CHG_NONE_VALID; + uint32_t temp; + uint32_t numer; + uint32_t denom; + uint32_t freqmax; + uint32_t freqmin; + uint32_t inputfreq; + uint32_t guardband; + bool numerchg = false; + bool denomchg = false; + bool within_gb; + + // gather data values according to PLL + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + + numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.MainPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.MainPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.MainPLL_800.guardband; + + inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; + } + + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + + numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.PeriphPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.PeriphPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.PeriphPLL_800.guardband; + + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) + { + inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + inputfreq = alt_ext_clk_paramblok.periph.freqcur; + } + else + { + return ret; + } + } + + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + + numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); + + freqmax = alt_pll_clk_paramblok.SDRAMPLL_800.freqmax; + freqmin = alt_pll_clk_paramblok.SDRAMPLL_800.freqmin; + guardband = alt_pll_clk_paramblok.SDRAMPLL_800.guardband; + + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + inputfreq = alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + inputfreq = alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + inputfreq = alt_ext_clk_paramblok.sdram.freqcur; + } + else + { + return ret; + } + } + else + { + return ret; + } + + temp = mult * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) // are the final values within frequency limits? + { + numer++; + denom++; + numerchg = (mult != numer); + denomchg = (div != denom); + + if (!numerchg && !denomchg) + { + ret = ALT_VCO_CHG_NOCHANGE; + } + else if (numerchg && !denomchg) + { + within_gb = alt_within_delta(numer, mult, guardband); + // check if change is within the guardband limits + temp = mult * (inputfreq / denom); + if ((temp <= freqmax) && (temp >= freqmin)) + { + ret = ALT_VCO_CHG_NUM; + if (!within_gb) ret |= ALT_VCO_CHG_NUM_BYP; + } + } + else if (!numerchg && denomchg) + { + within_gb = alt_within_delta(denom, div, guardband); + temp = numer * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) + { + ret = ALT_VCO_CHG_DENOM; + if (!within_gb) + { + ret |= ALT_VCO_CHG_DENOM_BYP; + } + } + } + else //numerchg && denomchg + { + within_gb = alt_within_delta(numer, mult, guardband); + temp = mult * (inputfreq / denom); + if ((temp <= freqmax) && (temp >= freqmin)) + { + ret = ALT_VCO_CHG_NUM_DENOM; + if (!within_gb) + { + ret |= ALT_VCO_CHG_NUM_DENOM_BYP; + } + } + within_gb = alt_within_delta(denom, div, guardband); + temp = numer * (inputfreq / div); + if ((temp <= freqmax) && (temp >= freqmin)) + { + ret = ALT_VCO_CHG_DENOM_NUM; + if (!within_gb) + { + ret |= ALT_VCO_CHG_DENOM_NUM_BYP; + } + } + } + } + + return ret; +#endif +} + + +/****************************************************************************************/ +/* alt_clk_pll_vco_cfg_set() sets the PLL VCO frequency configuration using the */ +/* supplied multiplier and divider arguments. alt_clk_pll_vco_chg_methods_get() */ +/* determines which methods are allowed by the limits set by the maximum multiplier */ +/* and divider values and by the upper and lower frequency limits of the PLL, and also */ +/* determines whether these changes can be made without requiring the PLL to be */ +/* bypassed. alt_clk_pll_vco_cfg_set() then carries out the actions required to effect */ +/* the method chosen to change the VCO settings. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll, uint32_t mult, uint32_t div) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; + ALT_CLK_PLL_VCO_CHG_METHOD_t method; + bool byp = false; + void *vaddr; + uint32_t numermask, denommask; + uint32_t numershift, denomshift; + + + method = alt_clk_pll_vco_chg_methods_get(pll, mult, div); + + if (method == ALT_VCO_CHG_NONE_VALID) + { + ret = ALT_E_BAD_CLK; + } + else if (method == ALT_VCO_CHG_NOCHANGE) + { + ret = ALT_E_INV_OPTION; + } + else + { + if (pll == ALT_CLK_MAIN_PLL) + { + vaddr = ALT_CLKMGR_MAINPLL_VCO_ADDR; + numermask = ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK; + denommask = ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK; + numershift = ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB; + denomshift = ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + vaddr = ALT_CLKMGR_PERPLL_VCO_ADDR; + numermask = ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK; + denommask = ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK; + numershift = ALT_CLKMGR_PERPLL_VCO_NUMER_LSB; + denomshift = ALT_CLKMGR_PERPLL_VCO_DENOM_LSB; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + vaddr = ALT_CLKMGR_SDRPLL_VCO_ADDR; + numermask = ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK; + denommask = ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK; + numershift = ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB; + denomshift = ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB; + } + else { return ALT_E_BAD_ARG; } + + mult--; + div--; + + if (method & ALT_VCO_CHG_NUM) + { + if (method & ALT_VCO_CHG_NUM_BYP) + { + alt_clk_pll_bypass_enable(pll, 0); + byp = true; + alt_clk_mgr_wait(vaddr, ALT_SW_MANAGED_CLK_WAIT_BYPASS); + } + alt_replbits_word(vaddr, numermask, mult << numershift); + } + + else if (method & ALT_VCO_CHG_DENOM) + { + if (method & ALT_VCO_CHG_DENOM_BYP) + { + alt_clk_pll_bypass_enable(pll, 0); + byp = true; + } + alt_replbits_word(vaddr, denommask, div << denomshift); + } + + else if (method & ALT_VCO_CHG_NUM_DENOM) + { + if (method & ALT_VCO_CHG_NUM_DENOM_BYP) + { + alt_clk_pll_bypass_enable(pll, 0); + byp = true; + } + alt_replbits_word(vaddr, numermask, mult << numershift); + if (!byp) // if PLL is not bypassed + { + ret = alt_clk_pll_lock_wait(ALT_CLK_MAIN_PLL, 1000); + // verify PLL is still locked or wait for it to lock again + } + alt_replbits_word(vaddr, denommask, div << denomshift); + } + + else if (method & ALT_VCO_CHG_DENOM_NUM) + { + if (method & ALT_VCO_CHG_DENOM_NUM_BYP) + { + alt_clk_pll_bypass_enable(pll, 0); + byp = true; + } + alt_replbits_word(vaddr, numermask, mult << numershift); + if (!byp) // if PLL is not bypassed + { + ret = alt_clk_pll_lock_wait(ALT_CLK_MAIN_PLL, 1000); + // verify PLL is still locked or wait for it to lock again + } + alt_replbits_word(vaddr, denommask, div << denomshift); + } + + ret = alt_clk_pll_lock_wait(ALT_CLK_MAIN_PLL, 1000); + // verify PLL is still locked or wait for it to lock again + if (byp) + { + alt_clk_pll_bypass_disable(pll); + alt_clk_mgr_wait(vaddr, ALT_SW_MANAGED_CLK_WAIT_BYPASS); + // wait for PLL to come out of bypass mode completely + } + } + return ret; +} + + +// +// alt_clk_pll_vco_freq_get() gets the VCO frequency of the specified PLL. +// Note that since there is at present no known way for software to obtain the speed +// bin of the SoC or MPU that it is running on, the function below only deals with the +// 800 MHz part. This may need to be revised in the future. +// +ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, alt_freq_t * freq) +{ + uint64_t temp1 = 0; + uint32_t temp; + uint32_t numer; + uint32_t denom; + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + + if (freq == NULL) + { + return ret; + } + + if (pll == ALT_CLK_MAIN_PLL) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + numer = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp); + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; + temp1 *= (numer + 1); + temp1 /= (denom + 1); + + if (temp1 <= UINT32_MAX) + { + temp = (alt_freq_t) temp1; + alt_pll_clk_paramblok.MainPLL_800.freqcur = temp; + // store this value in the parameter block table + *freq = temp; + // should NOT check value against PLL frequency limits + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + numer = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp); + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(temp); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + } + + if (temp1 != 0) + { + temp1 *= (numer + 1); + temp1 /= (denom + 1); + if (temp1 <= UINT32_MAX) + { + temp = (alt_freq_t) temp1; + alt_pll_clk_paramblok.PeriphPLL_800.freqcur = temp; + // store this value in the parameter block table + + *freq = temp; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } // this returns ALT_BAD_ARG if the source isn't known + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + numer = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(temp); + denom = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(temp); + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(temp); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc1.freqcur; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.clkosc2.freqcur; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + temp1 = (uint64_t) alt_ext_clk_paramblok.sdram.freqcur; + } + + if (temp1 != 0) + { + temp1 *= (numer + 1); + temp1 /= (denom + 1); + if (temp1 <= UINT32_MAX) + { + temp = (alt_freq_t) temp1; + alt_pll_clk_paramblok.SDRAMPLL_800.freqcur = temp; + // store this value in the parameter block table + + *freq = temp; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } + } // which returns ALT_BAD_ARG if the source isn't known + + return ret; +} + +// +// Returns the current guard band range in effect for the PLL. +// +uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll) +{ + uint32_t ret = 0; + + if (pll == ALT_CLK_MAIN_PLL) + { + ret = alt_pll_clk_paramblok.MainPLL_800.guardband; + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + ret = alt_pll_clk_paramblok.PeriphPLL_800.guardband; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + ret = alt_pll_clk_paramblok.SDRAMPLL_800.guardband; + } + return ret; +} + +// +// clk_mgr_pll_guard_band_set() changes the guard band from its current value to permit +// a more lenient or stringent policy to be in effect for the implementation of the +// functions configuring PLL VCO frequency. +// +ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll, uint32_t guard_band) +{ + if ( (guard_band > UINT12_MAX) || (guard_band <= 0) + || (guard_band > ALT_GUARDBAND_LIMIT) + ) + { + return ALT_E_ARG_RANGE; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (pll == ALT_CLK_MAIN_PLL) + { + alt_pll_clk_paramblok.MainPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.MainPLL_600.guardband = guard_band; + // ??? Don't know how to check the MPU speed bin yet, so only 800 MHz struct is used + } + else if (pll == ALT_CLK_PERIPHERAL_PLL) + { + alt_pll_clk_paramblok.PeriphPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.PeriphPLL_600.guardband = guard_band; + } + else if (pll == ALT_CLK_SDRAM_PLL) + { + alt_pll_clk_paramblok.SDRAMPLL_800.guardband = guard_band; + //alt_pll_clk_paramblok.SDRAMPLL_600.guardband = guard_band; + } + else + { + status = ALT_E_ERROR; + } + + return status; +} + +// +// alt_clk_divider_get() gets configured divider value for the specified clock. +// +ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, uint32_t * div) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t temp; + + if (div == NULL) + { + return ALT_E_BAD_ARG; + } + + switch (clk) + { + // Main PLL outputs + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MPU: + *div = (ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)) + 1); + break; + + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + *div = (ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)) + 1); + break; + + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_TIMER: + *div = (ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR)) + 1) * + (ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_DBGATCLK_ADDR)) + 1); + break; + + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_QSPI: + *div = (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR))) + 1; + break; + + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_NAND_SDMMC: + *div = (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR))) + 1; + break; + + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + *div = (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR))) + 1; + break; + + ///// + + // Peripheral PLL outputs + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_EMAC0: + *div = (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR))) + 1; + break; + + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_EMAC1: + *div = (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR))) + 1; + break; + + case ALT_CLK_PERIPHERAL_PLL_C2: + *div = (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR))) + 1; + break; + + case ALT_CLK_PERIPHERAL_PLL_C3: + *div = (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR))) + 1; + break; + + case ALT_CLK_PERIPHERAL_PLL_C4: + *div = (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR))) + 1; + break; + + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_H2F_USER1: + *div = (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR))) + 1; + break; + + ///// + + // SDRAM PLL outputs + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + *div = (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR))) + 1; + break; + + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + *div = (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR))) + 1; + break; + + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + *div = (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR))) + 1; + break; + + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + *div = (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR))) + 1; + break; + + ///// + + // Other clock dividers + case ALT_CLK_L3_MP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2) + { + *div = temp + 1; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_L3_SP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2) + { + *div = temp + 1; + } + else + { + status = ALT_E_ERROR; + } + // note that this value does not include the additional effect + // of the L3_MP divider that is upchain from this one + break; + + case ALT_CLK_L4_MP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_L4_SP: + temp = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_DBG_AT: + temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_DBG: + temp = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + // note that this value does not include the value of the upstream dbg_at_clk divder + break; + + case ALT_CLK_DBG_TRACE: + temp = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR)); + if (temp <= ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_USB_MP: + temp = ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_SPI_M: + temp = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_CAN0: + temp = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_CAN1: + temp = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR)); + if (temp <= ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16) + { + *div = 1 << temp; + } + else + { + status = ALT_E_ERROR; + } + break; + + case ALT_CLK_GPIO_DB: + temp = ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR)); + *div = temp + 1; + break; + + case ALT_CLK_MPU_PERIPH: + *div = 4; // set by hardware + break; + + case ALT_CLK_MPU_L2_RAM: + *div = 2; // set by hardware + break; + + case ALT_CLK_NAND: + *div = 4; // set by hardware + break; + + default: + status = ALT_E_BAD_ARG; + break; + } + + return status; +} + +///// + +#define ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE false + // used for testing writes to the the full range of counters without + // regard to the usual output frequency upper and lower limits + + +static ALT_STATUS_CODE alt_clk_within_freq_limits(ALT_CLK_t clk, uint32_t div) +{ +#if ALT_CLK_WITHIN_FREQ_LIMITS_TEST_MODE + return ALT_E_TRUE; +#else + + if (div == 0) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t numer = 0; + uint32_t hilimit; + uint32_t lolimit; + + switch (clk) + { + // Counters of the Main PLL + case ALT_CLK_MAIN_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C0; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C1; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C2; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C3: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C3; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C4: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C4; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + case ALT_CLK_MAIN_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.MainPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &numer); + break; + + // Counters of the Peripheral PLL + case ALT_CLK_PERIPHERAL_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C0; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C1; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C2; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C3; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C4; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.PeriphPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &numer); + break; + + // Counters of the SDRAM PLL + case ALT_CLK_SDRAM_PLL_C0: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C0; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C1: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C1; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C2: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C2; + lolimit = 0; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + case ALT_CLK_SDRAM_PLL_C5: + hilimit = alt_pll_cntr_maxfreq.SDRAMPLL_C5; + lolimit = alt_ext_clk_paramblok.clkosc1.freqcur; + status = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &numer); + break; + + default: + status = ALT_E_BAD_ARG; + break; + } + + if (status == ALT_E_SUCCESS) + { + numer = numer / div; + if ((numer <= hilimit) && (numer >= lolimit)) + { + status = ALT_E_TRUE; + } + else + { + status = ALT_E_FALSE; + } + } + + return status; +#endif +} + +static bool alt_clkmgr_is_val_modulo_n(uint32_t div, uint32_t mod) +{ + if (mod == 1) + { + return true; + } + else if (mod == 2) + { + return (div & 0x1) == 0; + } + else if (mod == 4) + { + return (div & 0x3) == 0; + } + else + { + return (div % mod) == 0; + } +} + +// +// alt_clk_divider_set() sets the divider value for the specified clock. +// +// See pages 38, 44, 45, and 46 of the HPS-Clocking NPP for a map of the +// HPS clocking architecture and hierarchy of connections. +// +ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk, uint32_t div) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + volatile uint32_t temp, temp1; + uint32_t wrval = UINT32_MAX; // value to be written + bool restore_0 = false; + bool restore_1 = false; + bool restore_2 = false; + + switch (clk) + { + // Main PLL outputs + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MPU: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR)) + 1); + + if ( (div <= ((ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C0, div) == ALT_E_TRUE) ) + { + wrval = (div / prediv) - 1; + + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. + alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, wrval); + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + } + break; + + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_L3_MAIN: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR)) + 1); + + if ( (div <= ((ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C1, div) == ALT_E_TRUE) ) + { + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. + + wrval = (div / prediv) - 1; + +#if ALT_PREVENT_GLITCH_CHGC1 + // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing + // bypass state, then gate clock back on. FogBugz #63778 + temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))) + { + restore_0 = true; + } + if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))) + { + restore_1 = true; + } + temp = temp1; + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); } + + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, wrval); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + // wait a bit before reenabling the L4MP and L4SP clocks + if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); } +#else + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, wrval); +#endif + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + } + break; + + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_DBG_BASE: + { + uint32_t prediv = (ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_DBGATCLK_ADDR)) + 1); + + if ( (div <= ((ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK + 1) * prediv)) + && alt_clkmgr_is_val_modulo_n(div, prediv) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C2, div) == ALT_E_TRUE) ) + { + wrval = (div / prediv) - 1; + // HW managed clock, change by writing to the external counter, no need to gate clock + // or match phase or wait for transistion time. No other field in the register to mask off either. + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, wrval); + + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + } + break; + + case ALT_CLK_MAIN_PLL_C3: + // The rest of the PLL outputs do not have external counters, but + // their internal counters are programmable rather than fixed + if ( (div <= (ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C3, div) == ALT_E_TRUE) ) + { + // if the main_qspi_clk input is selected for the qspi_clk + if (ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)) == + ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + restore_0 = (temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; + if (restore_0) // AND if the QSPI clock is currently enabled + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); + // gate off the QSPI clock + } + + wrval = div - 1; + // the rest are software-managed clocks and require a reset sequence to write to + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // if the QSPI clock was gated on (enabled) before, return it to that state + } + ret = ALT_E_SUCCESS; + } + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_NAND_SDMMC: + if ( (div <= (ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C4, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + + // do we need to gate off the SDMMC clock ? + if (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + if (temp1 & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK) { restore_0 = true; } + } + + // do we need to gate off the NAND clock and/or the NANDX clock? + if (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) + { + if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK) { restore_1 = true; } + if (temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK) { restore_2 = true; } + } + + temp = temp1; + if (restore_1 && restore_2) + { + temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + // gate nand_clk off at least 8 MPU clock cycles before before nand_x_clk + } + + if (restore_0 || restore_1) + { + if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; } + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // gate off sdmmc_clk and/or nand_x_clk + } + + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C4, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + + if (restore_0 || restore_1) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); + // if the NANDX and/or SDMMC clock was gated on (enabled) before, return it to that state + if (restore_1 && restore_2) + { + // wait at least 8 clock cycles to turn the nand_clk on + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); + } + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_MAIN_PLL_C5: + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + if ( (div <= (ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_MAIN_PLL_C5, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + restore_0 = ((temp & ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK) || + (temp & ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK)); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & (ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK & + ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK)); // clear both + } + + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + ///// + + // Peripheral PLL outputs + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_EMAC0: + if ( (div <= (ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C0, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK; + + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK); + } + + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C0, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_EMAC1: + if ( (div <= (ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C1, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK; + + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK); + } + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C1, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C2: + if ( (div <= (ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C2, div) == ALT_E_TRUE) ) + { + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + // if qspi source is set to Peripheral PLL C2 + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + // and if qspi_clk is enabled + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK); + // gate it off + } + } + + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + // if the clock was gated on (enabled) before, return it to that state + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C3: + if ( (div <= (ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C3, div) == ALT_E_TRUE) ) + { + // first, are the clock MUX input selections currently set to use the clock we want to change? + temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + restore_0 = (ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(temp) == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK); + restore_1 = restore_2 = (ALT_CLKMGR_PERPLL_SRC_NAND_GET(temp) == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK); + + // now AND those with the current state of the three gate enables + // to get the clocks which must be gated off and then back on + temp1 = temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = restore_0 && (temp & ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK); + restore_1 = restore_1 && (temp & ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK); + restore_2 = restore_2 && (temp & ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK); + + // gate off the clocks that depend on the clock divider that we want to change + if (restore_2) { temp &= ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK; } + if (restore_0) { temp &= ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK; } + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + + // the NAND clock must be gated off before the NANDX clock, + if (restore_1) + { + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK); + temp &= ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK; + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + + // NAND clock and NAND_X clock cannot be written together, must be a set sequence with a delay + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK); + if (restore_2) + { + // the NANDX clock must be gated on before the NAND clock. + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK ); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C4: + if ( (div <= (ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C4, div) == ALT_E_TRUE) ) + { + // look at the L4 set of clock gates first + temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + restore_0 = (ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL); + restore_1 = (ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(temp1) == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL); + temp1 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = restore_0 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK); + restore_1 = restore_1 && (temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK); + + // if the l4_sp and l4_mp clocks are not set to use the periph_base_clk + // from the Peripheral PLL C4 clock divider output, or if they are + // not currently gated on, don't change their gates + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; } + if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; } + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + + // now look at the C4 direct set of clock gates + // first, create a mask of the C4 direct set of clock gate enables + temp = ( ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK + | ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK ); + + // gate off all the C4 Direct set of clocks + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1 & ~temp); + + // change the clock divider ratio - the reason we're here + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C4, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + + // gate the affected clocks that were on before back on - both sets of gates + temp = (restore_0) ? ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK : 0; + if (restore_1) { temp |= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK; } + alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp1); + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_PERIPHERAL_PLL_C5: + case ALT_CLK_H2F_USER1: + if ( (div <= (ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_PERIPHERAL_PLL_C5, div) == ALT_E_TRUE) ) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + restore_0 = temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK; + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK); + } + + // now write the new divisor ratio + wrval = div - 1; + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + if (restore_0) { alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + ///// + + // SDRAM PLL outputs + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C0, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK); + restore_0 = true; + } + + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C0, + ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C1, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK); + restore_0 = true; + } + + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C1, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + if ( (div <= (ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C2, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK); + restore_0 = true; + } + + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + if ( (div <= (ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK + 1)) + && (alt_clk_within_freq_limits(ALT_CLK_SDRAM_PLL_C5, div) == ALT_E_TRUE) ) + { + wrval = div - 1; + temp = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + if (temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp & ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK); + restore_0 = true; + } + + alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, + ALT_CLKMGR_SDRPLL_STAT_ADDR, + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C5, + ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + ///// + + // Other clock dividers + case ALT_CLK_L3_MP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_L3_SP: + // note that the L3MP divider is upstream from the L3SP divider + // and any changes to the former will affect the output of both + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2; } + + if (wrval != UINT32_MAX) + { + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB); + // no clock gate to close and reopen + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV ); + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_L4_MP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); // which has the enable bit set + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_L4_SP: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_DBG_AT: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_DBG: + if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK, + wrval << (ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB - 1)); + // account for the fact that the divisor ratios are 2x the value + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_DBG_TRACE: + if (div == 1) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + if (temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp & ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK, + wrval << ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_USB_MP: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_SPI_M: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_CAN0: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_CAN1: + if (div == 1) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1; } + else if (div == 2) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2; } + else if (div == 4) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4; } + else if (div == 8) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8; } + else if (div == 16) { wrval = ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16; } + + if (wrval != UINT32_MAX) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK); + restore_0 = true; + } + alt_replbits_word(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_DIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_GPIO_DB: // GPIO debounce clock + if (div <= ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK) + { + temp = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + if (temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK) + { + // if clock is currently on, gate it off + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp & ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK); + restore_0 = true; + } + wrval = div - 1; + alt_replbits_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK, + wrval << ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB); + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, temp); + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + break; + + case ALT_CLK_MAIN_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + // get the QSPI clock source + restore_0 = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR) & ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK; + // and the current enable state + wrval = div - 1; + + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { // if the main_qspi_clk (Main PLL C3 Ouput) input is selected + if (div <= ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK) + { + if (restore_0) + { + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + } // gate off the QSPI clock + + alt_clk_pllcounter_write(ALT_CLKMGR_MAINPLL_VCO_ADDR, + ALT_CLKMGR_MAINPLL_STAT_ADDR, + ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C3, + ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + // if the QSPI clock was gated on (enabled) before, return it to that state + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + if (div <= ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK) + { + if (restore_0) + { + alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + } // gate off the QSPI clock + + alt_clk_pllcounter_write(ALT_CLKMGR_PERPLL_VCO_ADDR, + ALT_CLKMGR_PERPLL_STAT_ADDR, + ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, + wrval, + ALT_CLK_PLL_RST_BIT_C2, + ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB); + + alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV); + if (restore_0) + { + alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK); + // if the QSPI clock was gated on (enabled) before, return it to that state + } + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ARG_RANGE; + } + } + break; + + ///// + + default: + ret = ALT_E_BAD_ARG; + break; + } + + return ret; +} + +// +// alt_clk_freq_get() returns the output frequency of the specified clock. +// +ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, alt_freq_t* freq) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + uint32_t temp = 0; + uint64_t numer = 0; + uint64_t denom = 1; + + if (freq == NULL) + { + return ret; + } + + switch (clk) + { + // External Inputs + case ALT_CLK_IN_PIN_OSC1: + case ALT_CLK_OSC1: + numer = alt_ext_clk_paramblok.clkosc1.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_IN_PIN_OSC2: + numer = alt_ext_clk_paramblok.clkosc2.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_F2H_PERIPH_REF: + numer = alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + case ALT_CLK_F2H_SDRAM_REF: + numer = alt_ext_clk_paramblok.sdram.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + break; + + ///// + + // PLLs + case ALT_CLK_MAIN_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) + { + temp = alt_ext_clk_paramblok.clkosc1.freqcur; + ret = ALT_E_SUCCESS; + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; + + case ALT_CLK_PERIPHERAL_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) + { + temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1) + { + temp = alt_ext_clk_paramblok.clkosc1.freqcur; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2) + { + temp = alt_ext_clk_paramblok.clkosc2.freqcur; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF) + { + temp = alt_ext_clk_paramblok.periph.freqcur; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; + + case ALT_CLK_SDRAM_PLL: + if (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) + { + temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR)); + if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1) + { + temp = alt_ext_clk_paramblok.clkosc1.freqcur; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2) + { + temp = alt_ext_clk_paramblok.clkosc2.freqcur; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF) + { + temp = alt_ext_clk_paramblok.sdram.freqcur; + ret = ALT_E_SUCCESS; + } + else + { + ret = ALT_E_ERROR; + } + } + else + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + } + numer = (uint64_t) temp; + // denom = 1 by default + break; + + ///// + + // Main Clock Group + case ALT_CLK_MAIN_PLL_C0: + case ALT_CLK_MAIN_PLL_C1: + case ALT_CLK_MAIN_PLL_C2: + case ALT_CLK_MAIN_PLL_C3: + case ALT_CLK_MAIN_PLL_C4: + case ALT_CLK_MAIN_PLL_C5: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(clk, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_MPU: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_MPU_PERIPH: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MPU_PERIPH, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_MPU_L2_RAM: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C0, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MPU_L2_RAM, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_L4_MAIN: + case ALT_CLK_L3_MAIN: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_L3_MP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_L3_SP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_MP, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = denom * (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_L3_SP, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_L4_MP: + ret = alt_clk_divider_get(ALT_CLK_L4_MP, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + temp = ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + denom = denom * (uint64_t) temp; // no real harm if temp is garbage data + } + } + else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + denom = denom * (uint64_t) temp; + } + } + } + break; + + case ALT_CLK_L4_SP: + ret = alt_clk_divider_get(ALT_CLK_L4_SP, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + temp = ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)); + if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C1, &temp); + denom = denom * (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL) // periph_base_clk + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + denom = denom * (uint64_t) temp; + } + } + } + break; + + case ALT_CLK_DBG_BASE: + case ALT_CLK_DBG_TIMER: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_DBG_AT: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_DBG: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_AT, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = denom * (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_DBG_TRACE: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C2, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_DBG_TRACE, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_MAIN_QSPI: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_MAIN_NAND_SDMMC: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_CFG: + case ALT_CLK_H2F_USER0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; + + ///// + + // Peripheral Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + case ALT_CLK_PERIPHERAL_PLL_C1: + case ALT_CLK_PERIPHERAL_PLL_C2: + case ALT_CLK_PERIPHERAL_PLL_C3: + case ALT_CLK_PERIPHERAL_PLL_C4: + case ALT_CLK_PERIPHERAL_PLL_C5: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(clk, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_EMAC0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_EMAC1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_USB_MP: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_USB_MP, &temp); + denom = denom * (uint64_t) temp; + } + } + break; + + case ALT_CLK_SPI_M: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SPI_M, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_CAN0: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_CAN0, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_CAN1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_CAN1, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_GPIO_DB: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C4, &temp); + } + if (ret == ALT_E_SUCCESS) + { + denom = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_GPIO_DB, &temp); + denom = denom * (uint64_t) temp; + } + break; + + case ALT_CLK_H2F_USER1: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; + + /* Clocks That Can Switch Between Different Clock Groups */ + case ALT_CLK_SDMMC: + temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); + denom = (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; + + case ALT_CLK_NAND: + denom = 4; + // the absence of a break statement here is not a mistake + case ALT_CLK_NAND_X: + temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 or 4 by default; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C4, &temp); + denom = denom * (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C3, &temp); + denom = denom * (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; + + case ALT_CLK_QSPI: + temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR)); + if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK) + { + numer = (uint64_t) alt_ext_clk_paramblok.periph.freqcur; + // denom = 1 by default; + ret = ALT_E_SUCCESS; + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_MAIN_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_MAIN_PLL_C3, &temp); + denom = (uint64_t) temp; + } + } + else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK) + { + ret = alt_clk_pll_vco_freq_get(ALT_CLK_PERIPHERAL_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_PERIPHERAL_PLL_C2, &temp); + denom = (uint64_t) temp; + } + } + else + { + ret = ALT_E_ERROR; + } + break; + + ///// + + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + case ALT_CLK_DDR_DQS: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C0, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C1: + case ALT_CLK_DDR_2X_DQS: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C1, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C2: + case ALT_CLK_DDR_DQ: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C2, &temp); + denom = (uint64_t) temp; + } + break; + + case ALT_CLK_SDRAM_PLL_C5: + case ALT_CLK_H2F_USER2: + ret = alt_clk_pll_vco_freq_get(ALT_CLK_SDRAM_PLL, &temp); + if (ret == ALT_E_SUCCESS) + { + numer = (uint64_t) temp; + ret = alt_clk_divider_get(ALT_CLK_SDRAM_PLL_C5, &temp); + denom = (uint64_t) temp; + } + break; + + default: + ret = ALT_E_BAD_ARG; + break; + + } // end of switch-case construct + + if (ret == ALT_E_SUCCESS) + { + // will not get here if none of above cases match + if (denom > 0) + { + numer /= denom; + if (numer <= UINT32_MAX) + { + *freq = (uint32_t) numer; + } + else + { + ret = ALT_E_ERROR; + } + } + else + { + ret = ALT_E_ERROR; + } + } + + return ret; +} + +// +// alt_clk_irq_disable() disables one or more of the lock status conditions as +// contributors to the clkmgr_IRQ interrupt signal state. +// +ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) +{ + if (!(lock_stat_mask & ALT_CLK_MGR_PLL_LOCK_BITS)) + { + alt_clrbits_word(ALT_CLKMGR_INTREN_ADDR, lock_stat_mask); + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + +// +// alt_clk_irq_enable() enables one or more of the lock status conditions as +// contributors to the clkmgr_IRQ interrupt signal state. +// +ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask) +{ + if (!(lock_stat_mask & ALT_CLK_MGR_PLL_LOCK_BITS)) + { + alt_setbits_word(ALT_CLKMGR_INTREN_ADDR, lock_stat_mask); + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + +///// + +// +// alt_clk_group_cfg_raw_get() gets the raw configuration state of the designated +// clock group. +// +ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, + ALT_CLK_GROUP_RAW_CFG_t * clk_group_raw_cfg) +{ + clk_group_raw_cfg->verid = alt_read_word(ALT_SYSMGR_SILICONID1_ADDR); + clk_group_raw_cfg->siliid2 = alt_read_word(ALT_SYSMGR_SILICONID2_ADDR); + clk_group_raw_cfg->clkgrpsel = clk_group; + + if (clk_group == ALT_MAIN_PLL_CLK_GRP) + { + // Main PLL VCO register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR); + + // Main PLL Misc register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.misc = alt_read_word(ALT_CLKMGR_MAINPLL_MISC_ADDR); + + // Main PLL C0-C5 Counter registers + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mpuclk = alt_read_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations + + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgatclk = alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainqspiclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainnandsdmmcclk = alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR); + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.cfgs2fuser0clk = alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR); + + // Main PLL Enable register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.en = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR); + + // Main PLL Maindiv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.maindiv = alt_read_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR); + + // Main PLL Debugdiv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgdiv = alt_read_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR); + + // Main PLL Tracediv register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.tracediv = alt_read_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR); + + // Main PLL L4 Source register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.l4src = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR); + + // Main PLL Status register + clk_group_raw_cfg->clkgrp.mainpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_MAINPLL_STAT_ADDR); + // clkgrp.mainpllgrp.stat.outresetack is defined in the ALT_CLKMGR_MAINPLL_STAT_s declaration + // as a const but alt_indwrite_word() overrides that restriction. + + // padding ... + clk_group_raw_cfg->clkgrp.mainpllgrp.raw._pad_0x38_0x40[0] = 0; + clk_group_raw_cfg->clkgrp.mainpllgrp.raw._pad_0x38_0x40[1] = 0; + + return ALT_E_SUCCESS; + } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) + { + // Peripheral PLL VCO register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR); + + // Peripheral PLL Misc register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.misc = alt_read_word(ALT_CLKMGR_PERPLL_MISC_ADDR); + + // Peripheral PLL C0-C5 Counters + clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac0clk = alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations + + clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac1clk = alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.perqspiclk = alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.pernandsdmmcclk = alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.perbaseclk = alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR); + clk_group_raw_cfg->clkgrp.perpllgrp.raw.s2fuser1clk = alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR); + + // Peripheral PLL Enable register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.en = alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR); + + // Peripheral PLL Divider register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.div = alt_read_word(ALT_CLKMGR_PERPLL_DIV_ADDR); + + // Peripheral PLL GPIO Divider register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.gpiodiv = alt_read_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR); + + // Peripheral PLL Source register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.src = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR); + + // Peripheral PLL Status register + clk_group_raw_cfg->clkgrp.perpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_PERPLL_STAT_ADDR); + + // padding ... + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[0] = 0; + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[1] = 0; + clk_group_raw_cfg->clkgrp.perpllgrp.raw._pad_0x34_0x40[2] = 0; + + return ALT_E_SUCCESS; + } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + { + // SDRAM PLL VCO register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.vco = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR); + + // SDRAM PLL Control register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ctrl = alt_read_word(ALT_CLKMGR_SDRPLL_CTL_ADDR); + + // SDRAM PLL C0-C2 & C5 Counters + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqsclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR); + // doing these as 32-bit reads and writes avoids unnecessary masking operations + + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddr2xdqsclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqclk = alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR); + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.s2fuser2clk = alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR); + + // SDRAM PLL Enable register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.en = alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR); + + // SDRAM PLL Status register + clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.stat = alt_read_word(ALT_CLKMGR_SDRPLL_STAT_ADDR); + + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + +// +// alt_clk_group_cfg_raw_set() sets the clock group configuration. +// +ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t * clk_group_raw_cfg) +{ + // test for matching silicon ID, but not for matching silicon revision number + if (ALT_SYSMGR_SILICONID1_ID_GET(alt_read_word(ALT_SYSMGR_SILICONID1_ADDR)) != + ALT_SYSMGR_SILICONID1_ID_GET(clk_group_raw_cfg->verid)) + { + return ALT_E_BAD_VERSION; + } + + // get the PLL ID + ALT_CLK_GRP_t clk_group = clk_group_raw_cfg->clkgrpsel; + ALT_CLK_t pll; + + if (clk_group == ALT_MAIN_PLL_CLK_GRP) { pll = ALT_CLK_MAIN_PLL; } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) { pll = ALT_CLK_PERIPHERAL_PLL; } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) { pll = ALT_CLK_SDRAM_PLL; } + else + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // if the PLL isn't in bypass mode, put it in bypass mode + bool byp = false; + if (alt_clk_pll_is_bypassed(pll) == ALT_E_FALSE) + { + status = alt_clk_pll_bypass_enable(pll, false); + if (status != ALT_E_SUCCESS) + { + return status; + } + + byp = true; + } + + // now write the values in the ALT_CLK_GROUP_RAW_CFG_t structure to the registers + if (clk_group == ALT_MAIN_PLL_CLK_GRP) + { + // Main PLL VCO register + alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.vco & + ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now + + // Main PLL Misc register + alt_write_word(ALT_CLKMGR_MAINPLL_MISC_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.misc); + + // Main PLL C0-C5 Counter registers + alt_write_word(ALT_CLKMGR_MAINPLL_MPUCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mpuclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainclk); + alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgatclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainqspiclk); + alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.mainnandsdmmcclk); + alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.cfgs2fuser0clk); + + // Main PLL Counter Enable register + alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.en); + + // Main PLL Maindiv register + alt_write_word(ALT_CLKMGR_MAINPLL_MAINDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.maindiv); + + // Main PLL Debugdiv register + alt_write_word(ALT_CLKMGR_MAINPLL_DBGDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.dbgdiv); + + // Main PLL Tracediv register + alt_write_word(ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.tracediv); + + // Main PLL L4 Source register + alt_write_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, clk_group_raw_cfg->clkgrp.mainpllgrp.raw.l4src); + } + else if (clk_group == ALT_PERIPH_PLL_CLK_GRP) + { + // Peripheral PLL VCO register + alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.vco & + ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now + + // Peripheral PLL Misc register + alt_write_word(ALT_CLKMGR_PERPLL_MISC_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.misc); + + // Peripheral PLL C0-C5 Counters + alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac0clk); + alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.emac1clk); + alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.perqspiclk); + alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.pernandsdmmcclk); + alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.perbaseclk); + alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.s2fuser1clk); + + // Peripheral PLL Counter Enable register + alt_write_word(ALT_CLKMGR_PERPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.en); + + // Peripheral PLL Divider register + alt_write_word(ALT_CLKMGR_PERPLL_DIV_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.div); + + // Peripheral PLL GPIO Divider register + alt_write_word(ALT_CLKMGR_PERPLL_GPIODIV_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.gpiodiv); + + // Peripheral PLL Source register + alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, clk_group_raw_cfg->clkgrp.perpllgrp.raw.src); + } + else if (clk_group == ALT_SDRAM_PLL_CLK_GRP) + { + // SDRAM PLL VCO register + alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.vco & + ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK); + // the outreset and outresetall bits were probably clear when the + // state was saved, but make sure they're clear now + + // SDRAM PLL Control register + alt_write_word(ALT_CLKMGR_SDRPLL_CTL_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ctrl); + + // SDRAM PLL C0-C2 & C5 Counters + alt_write_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqsclk); + alt_write_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddr2xdqsclk); + alt_write_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.ddrdqclk); + alt_write_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.s2fuser2clk); + + // SDRAM PLL Counter Enable register + alt_write_word(ALT_CLKMGR_SDRPLL_EN_ADDR, clk_group_raw_cfg->clkgrp.sdrpllgrp.raw.en); + } + + // if PLL was not bypassed before, restore that state + if (byp) + { + status = alt_clk_pll_bypass_disable(pll); + } + + return status; +} + +// +// alt_clk_id_to_string() converts a clock ID to a text string. +// +ALT_STATUS_CODE alt_clk_id_to_string(ALT_CLK_t clk_id, char * output, size_t size) +{ + char * name = NULL; + + switch (clk_id) + { + case ALT_CLK_IN_PIN_OSC1: + name = "IN_PIN_OSC1"; + break; + case ALT_CLK_IN_PIN_OSC2: + name = "IN_PIN_OSC2"; + break; + + // FPGA Clock Sources External to HPS + case ALT_CLK_F2H_PERIPH_REF: + name = "F2H_PERIPH_REF"; + break; + case ALT_CLK_F2H_SDRAM_REF: + name = "F2H_SDRAM_REF"; + break; + + // Other Clock Sources External to HPS + case ALT_CLK_IN_PIN_JTAG: + name = "IN_PIN_JTAG"; + break; + case ALT_CLK_IN_PIN_ULPI0: + name = "IN_PIN_ULPI0"; + break; + case ALT_CLK_IN_PIN_ULPI1: + name = "IN_PIN_ULPI1"; + break; + case ALT_CLK_IN_PIN_EMAC0_RX: + name = "IN_PIN_EMAC0_RX"; + break; + case ALT_CLK_IN_PIN_EMAC1_RX: + name = "IN_PIN_EMAC1_RX"; + break; + + // PLLs + case ALT_CLK_MAIN_PLL: + name = "MAIN_PLL"; + break; + case ALT_CLK_PERIPHERAL_PLL: + name = "PERIPHERAL_PLL"; + break; + case ALT_CLK_SDRAM_PLL: + name = "SDRAM_PLL"; + break; + + // OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived + // directly from the osc_clk_1_HPS pin + case ALT_CLK_OSC1: + name = "OSC1"; + break; + + // Main Clock Group - The following clocks are derived from the Main PLL. + case ALT_CLK_MAIN_PLL_C0: + name = "MAIN_PLL_C0"; + break; + case ALT_CLK_MAIN_PLL_C1: + name = "MAIN_PLL_C1"; + break; + case ALT_CLK_MAIN_PLL_C2: + name = "MAIN_PLL_C2"; + break; + case ALT_CLK_MAIN_PLL_C3: + name = "MAIN_PLL_C3"; + break; + case ALT_CLK_MAIN_PLL_C4: + name = "MAIN_PLL_C4"; + break; + case ALT_CLK_MAIN_PLL_C5: + name = "MAIN_PLL_C5"; + break; + case ALT_CLK_MPU: + name = "MPU"; + break; + case ALT_CLK_MPU_L2_RAM: + name = "MPU_L2_RAM"; + break; + case ALT_CLK_MPU_PERIPH: + name = "MPU_PERIPH"; + break; + case ALT_CLK_L3_MAIN: + name = "L3_MAIN"; + break; + case ALT_CLK_L3_MP: + name = "L3_MP"; + break; + case ALT_CLK_L3_SP: + name = "L3_SP"; + break; + case ALT_CLK_L4_MAIN: + name = "L4_MAIN"; + break; + case ALT_CLK_L4_MP: + name = "L4_MP"; + break; + case ALT_CLK_L4_SP: + name = "L4_SP"; + break; + case ALT_CLK_DBG_BASE: + name = "DBG_BASE"; + break; + case ALT_CLK_DBG_AT: + name = "DBG_AT"; + break; + case ALT_CLK_DBG_TRACE: + name = "DBG_TRACE"; + break; + case ALT_CLK_DBG_TIMER: + name = "DBG_TIMER"; + break; + case ALT_CLK_DBG: + name = "DBG"; + break; + case ALT_CLK_MAIN_QSPI: + name = "MAIN_QSPI"; + break; + case ALT_CLK_MAIN_NAND_SDMMC: + name = "MAIN_NAND_SDMMC"; + break; + case ALT_CLK_CFG: + name = "CFG"; + break; + case ALT_CLK_H2F_USER0: + name = "H2F_USER0"; + break; + + // Peripherals Clock Group - The following clocks are derived from the Peripheral PLL. + case ALT_CLK_PERIPHERAL_PLL_C0: + name = "PERIPHERAL_PLL_C0"; + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + name = "PERIPHERAL_PLL_C1"; + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + name = "PERIPHERAL_PLL_C2"; + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + name = "PERIPHERAL_PLL_C3"; + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + name = "PERIPHERAL_PLL_C4"; + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + name = "PERIPHERAL_PLL_C5"; + break; + case ALT_CLK_USB_MP: + name = "USB_MP"; + break; + case ALT_CLK_SPI_M: + name = "SPI_M"; + break; + case ALT_CLK_QSPI: + name = "QSPI"; + break; + case ALT_CLK_NAND_X: + name = "NAND_X"; + break; + case ALT_CLK_NAND: + name = "NAND"; + break; + case ALT_CLK_SDMMC: + name = "SDMMC"; + break; + case ALT_CLK_EMAC0: + name = "EMAC0"; + break; + case ALT_CLK_EMAC1: + name = "EMAC1"; + break; + case ALT_CLK_CAN0: + name = "CAN0"; + break; + case ALT_CLK_CAN1: + name = "CAN1"; + break; + case ALT_CLK_GPIO_DB: + name = "GPIO_DB"; + break; + case ALT_CLK_H2F_USER1: + name = "H2F_USER1"; + break; + + // SDRAM Clock Group - The following clocks are derived from the SDRAM PLL. + case ALT_CLK_SDRAM_PLL_C0: + name = "SDRAM_PLL_C0"; + break; + case ALT_CLK_SDRAM_PLL_C1: + name = "SDRAM_PLL_C1"; + break; + case ALT_CLK_SDRAM_PLL_C2: + name = "SDRAM_PLL_C2"; + break; + case ALT_CLK_SDRAM_PLL_C3: + name = "SDRAM_PLL_C3"; + break; + case ALT_CLK_SDRAM_PLL_C4: + name = "SDRAM_PLL_C4"; + break; + case ALT_CLK_SDRAM_PLL_C5: + name = "SDRAM_PLL_C5"; + break; + case ALT_CLK_DDR_DQS: + name = "DDR_DQS"; + break; + case ALT_CLK_DDR_2X_DQS: + name = "DDR_2X_DQS"; + break; + case ALT_CLK_DDR_DQ: + name = "DDR_DQ"; + break; + case ALT_CLK_H2F_USER2: + name = "H2F_USER2"; + break; + + // Clock Output Pins + case ALT_CLK_OUT_PIN_EMAC0_TX: + name = "OUT_PIN_EMAC0_TX"; + break; + case ALT_CLK_OUT_PIN_EMAC1_TX: + name = "OUT_PIN_EMAC1_TX"; + break; + case ALT_CLK_OUT_PIN_SDMMC: + name = "OUT_PIN_SDMMC"; + break; + case ALT_CLK_OUT_PIN_I2C0_SCL: + name = "OUT_PIN_I2C0_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C1_SCL: + name = "OUT_PIN_I2C1_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C2_SCL: + name = "OUT_PIN_I2C2_SCL"; + break; + case ALT_CLK_OUT_PIN_I2C3_SCL: + name = "OUT_PIN_I2C3_SCL"; + break; + case ALT_CLK_OUT_PIN_SPIM0: + name = "OUT_PIN_SPIM0"; + break; + case ALT_CLK_OUT_PIN_SPIM1: + name = "OUT_PIN_SPIM1"; + break; + case ALT_CLK_OUT_PIN_QSPI: + name = "OUT_PIN_QSPI"; + break; + case ALT_CLK_UNKNOWN: + name = "UNKNOWN"; + break; + + // do *not* put a 'default' statement here. Then the compiler will throw + // an error if another clock id enum is added if the corresponding + // string is not added to this function. + } + + if (name != NULL) + { + snprintf(output, size, "ALT_CLK_%s", name); + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + + +// +// alt_clk_pll_cntr_maxfreq_recalc() recalculate the maxmum frequency of the specified clock. +// +ALT_STATUS_CODE alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_t clk, ALT_PLL_CNTR_FREQMAX_t * maxfreq) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; + alt_freq_t freq; + + ret = alt_clk_freq_get(clk, &freq); + + if (ret == ALT_E_SUCCESS) + { + + switch (clk) + { + // Main Clock Group + case ALT_CLK_MAIN_PLL_C0: + maxfreq->MainPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C1: + maxfreq->MainPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C2: + maxfreq->MainPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C3: + maxfreq->MainPLL_C3 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C3 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C4: + maxfreq->MainPLL_C4 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C4 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_MAIN_PLL_C5: + maxfreq->MainPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.MainPLL_C5 = %10d\n", (unsigned int)freq); + break; + + // Peripheral Clock Group + case ALT_CLK_PERIPHERAL_PLL_C0: + maxfreq->PeriphPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C1: + maxfreq->PeriphPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C2: + maxfreq->PeriphPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C3: + maxfreq->PeriphPLL_C3 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C3 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C4: + maxfreq->PeriphPLL_C4 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C4 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_PERIPHERAL_PLL_C5: + maxfreq->PeriphPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.PeriphPLL_C5 = %10d\n", (unsigned int)freq); + break; + + // SDRAM Clock Group + case ALT_CLK_SDRAM_PLL_C0: + maxfreq->SDRAMPLL_C0 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C0 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C1: + maxfreq->SDRAMPLL_C1 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C1 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C2: + maxfreq->SDRAMPLL_C2 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C2 = %10d\n", (unsigned int)freq); + break; + case ALT_CLK_SDRAM_PLL_C5: + maxfreq->SDRAMPLL_C5 = freq; + printf("alt_pll_cntr_maxfreq.SDRAMPLL_C5 = %10d\n", (unsigned int)freq); + break; + default: + ret = ALT_E_BAD_ARG; + printf("bad max frequency parameter\n"); + break; + } // end of switch-case construct + } + + return ret; +} + +// +// u-boot preloader actually initialize clock manager circuitry +// +// alt_clk_clkmgr_init() attempt to fix the pll counter max frequencies, since +// thses frequencies are not known in advance until u-boot programmed clock manager. +// +ALT_STATUS_CODE alt_clk_clkmgr_init(void) +{ + ALT_STATUS_CODE ret = ALT_E_SUCCESS; + ALT_STATUS_CODE status ; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C3,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C4,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_MAIN_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C3,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C4,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_PERIPHERAL_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C0,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C1,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C2,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + status = alt_clk_pll_cntr_maxfreq_recalc(ALT_CLK_SDRAM_PLL_C5,&alt_pll_cntr_maxfreq ); + if (status != ALT_E_SUCCESS) ret = ALT_E_ERROR; + + + return ret; +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_dma.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_dma.c new file mode 100644 index 000000000..d0ae4392a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_dma.c @@ -0,0 +1,3749 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include "alt_dma.h" +#include "socal/socal.h" +#include "socal/hps.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_sysmgr.h" + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT +#include "alt_16550_uart.h" +#include "socal/alt_uart.h" +#endif + +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT +#include "socal/alt_qspi.h" +#endif + +///// + +#ifndef MIN +#define MIN(a, b) ((a) > (b) ? (b) : (a)) +#endif // MIN + +#ifndef ARRAY_COUNT +#define ARRAY_COUNT(array) (sizeof(array) / sizeof(array[0])) +#endif + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +// +// SoCAL stand in for DMA Controller registers +// +// The base can be one of the following: +// - ALT_DMANONSECURE_ADDR +// - ALT_DMASECURE_ADDR +// +// Macros which have a channel parameter does no validation. +// + +// DMA Manager Status Register +#define ALT_DMA_DSR_OFST 0x0 +#define ALT_DMA_DSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DSR_OFST)) +#define ALT_DMA_DSR_DMASTATUS_SET_MSK 0x0000000f +#define ALT_DMA_DSR_DMASTATUS_GET(value) ((value) & 0x0000000f) + +// DMA Program Counter Register +#define ALT_DMA_DPC_OFST 0x4 +#define ALT_DMA_DPC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DPC_OFST)) + +// Interrupt Enable Register +#define ALT_DMA_INTEN_OFST 0x20 +#define ALT_DMA_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTEN_OFST)) + +// Event-Interrupt Raw Status Register +#define ALT_DMA_INT_EVENT_RIS_OFST 0x24 +#define ALT_DMA_INT_EVENT_RIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INT_EVENT_RIS_OFST)) + +// Interrupt Status Register +#define ALT_DMA_INTMIS_OFST 0x28 +#define ALT_DMA_INTMIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTMIS_OFST)) + +// Interrupt Clear Register +#define ALT_DMA_INTCLR_OFST 0x2c +#define ALT_DMA_INTCLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_INTCLR_OFST)) + +// Fault Status DMA Manager Register +#define ALT_DMA_FSRD_OFST 0x30 +#define ALT_DMA_FSRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRD_OFST)) + +// Fault Status DMA Channel Register +#define ALT_DMA_FSRC_OFST 0x34 +#define ALT_DMA_FSRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRC_OFST)) + +// Fault Type DMA Manager Register +#define ALT_DMA_FTRD_OFST 0x38 +#define ALT_DMA_FTRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FSRD_OFST)) + +// Fault Type DMA Channel Registers +#define ALT_DMA_FTRx_OFST(channel) (0x40 + 0x4 * (channel)) +#define ALT_DMA_FTRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_FTRx_OFST(channel))) + +// Channel Status Registers +#define ALT_DMA_CSRx_OFST(channel) (0x100 + 0x8 * (channel)) +#define ALT_DMA_CSRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CSRx_OFST(channel))) +#define ALT_DMA_CSRx_CHANNELSTATUS_SET_MSK 0x0000000f +#define ALT_DMA_CSRx_CHANNELSTATUS_GET(value) ((value) & 0x0000000f) + +// Channel Program Counter Registers +#define ALT_DMA_CPCx_OFST(channel) (0x104 + 0x8 * (channel)) +#define ALT_DMA_CPCx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CPCx_OFST(channel))) + +// Source Address Registers +#define ALT_DMA_SARx_OFST(channel) (0x400 + 0x20 * (channel)) +#define ALT_DMA_SARx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_SARx_OFST(channel))) + +// Destination Address Registers +#define ALT_DMA_DARx_OFST(channel) (0x404 + 0x20 * (channel)) +#define ALT_DMA_DARx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DARx_OFST(channel))) + +// Channel Control Registers +#define ALT_DMA_CCRx_OFST(channel) (0x408 + 0x20 * (channel)) +#define ALT_DMA_CCRx_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CCRx_OFST(channel))) + +// Loop Counter 0 Registers +#define ALT_DMA_LC0_x_OFST(channel) (0x40c + 0x20 * (channel)) +#define ALT_DMA_LC0_x_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_LC0_x_OFST(channel))) + +// Loop Counter 1 Registers +#define ALT_DMA_LC1_x_OFST(channel) (0x410 + 0x20 * (channel)) +#define ALT_DMA_LC1_x_ADDR(base, channel) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_LC1_x_OFST(channel))) + +// Debug Status Register +#define ALT_DMA_DBGSTATUS_OFST 0xd00 +#define ALT_DMA_DBGSTATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGSTATUS_OFST)) + +// Debug Command Register +#define ALT_DMA_DBGCMD_OFST 0xd04 +#define ALT_DMA_DBGCMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGCMD_OFST)) + +// Debug Instruction-0 Register +#define ALT_DMA_DBGINST0_OFST 0xd08 +#define ALT_DMA_DBGINST0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGINST0_OFST)) +#define ALT_DMA_DBGINST0_CHANNELNUMBER_SET(value) (((value) & 0x7) << 8) +#define ALT_DMA_DBGINST0_DEBUGTHREAD_SET(value) ((value) & 0x1) +#define ALT_DMA_DBGINST0_DEBUGTHREAD_E_MANAGER 0 +#define ALT_DMA_DBGINST0_DEBUGTHREAD_E_CHANNEL 1 +#define ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(value) (((value) & 0xff) << 16) +#define ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(value) (((value) & 0xff) << 24) + +// Debug Instruction-1 Register +#define ALT_DMA_DBGINST1_OFST 0xd0c +#define ALT_DMA_DBGINST1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_DBGINST1_OFST)) + +// Configuration Registers 0 - 4 +#define ALT_DMA_CR0_OFST 0xe00 +#define ALT_DMA_CR1_OFST 0xe04 +#define ALT_DMA_CR2_OFST 0xe08 +#define ALT_DMA_CR3_OFST 0xe0c +#define ALT_DMA_CR4_OFST 0xe10 +#define ALT_DMA_CR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR0_OFST)) +#define ALT_DMA_CR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR1_OFST)) +#define ALT_DMA_CR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR2_OFST)) +#define ALT_DMA_CR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR3_OFST)) +#define ALT_DMA_CR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CR4_OFST)) + +// DMA Configuration Register +#define ALT_DMA_CRD_OFST 0xe14 +#define ALT_DMA_CRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_CRD_OFST)) + +// Watchdog Register +#define ALT_DMA_WD_OFST 0xe80 +#define ALT_DMA_WD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_DMA_WD_OFST)) + +///// + +// +// Internal Data structures +// + +// This flag marks the channel as being allocated. +#define ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED (1 << 0) + +typedef struct ALT_DMA_CHANNEL_INFO_s +{ + uint8_t flag; +} +ALT_DMA_CHANNEL_INFO_t; + +static ALT_DMA_CHANNEL_INFO_t channel_info_array[8]; + +///// + +ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg) +{ + // Initialize the channel information array + for (int i = 0; i < 8; ++i) + { + channel_info_array[i].flag = 0; + } + + // Update the System Manager DMA configuration items + + uint32_t dmactrl = 0; + + // Handle FPGA / CAN muxing + for (int i = 0; i < 4; ++i) + { + // The default is FPGA. + switch (dma_cfg->periph_mux[i]) + { + case ALT_DMA_PERIPH_MUX_DEFAULT: + case ALT_DMA_PERIPH_MUX_FPGA: + break; + case ALT_DMA_PERIPH_MUX_CAN: + dmactrl |= (ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK << i); + break; + default: + return ALT_E_ERROR; + } + } + + // Handle Manager security + // Default is Secure state. + switch (dma_cfg->manager_sec) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + break; + case ALT_DMA_SECURITY_NONSECURE: + dmactrl |= ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK; + break; + default: + return ALT_E_ERROR; + } + + // Handle IRQ security + for (int i = 0; i < ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH; ++i) + { + // Default is Secure state. + switch (dma_cfg->irq_sec[i]) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + break; + case ALT_DMA_SECURITY_NONSECURE: + dmactrl |= (1 << (i + ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB)); + break; + default: + return ALT_E_ERROR; + } + } + + alt_write_word(ALT_SYSMGR_DMA_CTL_ADDR, dmactrl); + + // Update the System Manager DMA peripheral security items + + uint32_t dmapersecurity = 0; + + for (int i = 0; i < 32; ++i) + { + // Default is Secure state. + switch (dma_cfg->periph_sec[i]) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + break; + case ALT_DMA_SECURITY_NONSECURE: + dmapersecurity |= (1 << i); + break; + default: + return ALT_E_ERROR; + } + } + + alt_write_word(ALT_SYSMGR_DMA_PERSECURITY_ADDR, dmapersecurity); + + // Take DMA out of reset. + + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_DMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_uninit(void) +{ + // DMAKILL all channel and free all allocated channels. + for (int i = 0; i < 8; ++i) + { + if (channel_info_array[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED) + { + alt_dma_channel_kill((ALT_DMA_CHANNEL_t)i); + alt_dma_channel_free((ALT_DMA_CHANNEL_t)i); + } + } + + // Put DMA into reset. + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_DMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is unallocated + + if (channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED) + { + return ALT_E_ERROR; + } + + // Mark channel as allocated + + channel_info_array[channel].flag |= ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated) +{ + // Sweep channel array for unallocated channel + + for (int i = 0; i < 8; ++i) + { + if (!(channel_info_array[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + // Allocate that free channel. + + ALT_STATUS_CODE status = alt_dma_channel_alloc((ALT_DMA_CHANNEL_t)i); + if (status == ALT_E_SUCCESS) + { + *allocated = (ALT_DMA_CHANNEL_t)i; + } + return status; + } + } + + // No free channels found. + + return ALT_E_ERROR; +} + +ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is allocated + + if (!(channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + return ALT_E_ERROR; + } + + // Verify channel is stopped + + ALT_DMA_CHANNEL_STATE_t state; + ALT_STATUS_CODE status = alt_dma_channel_state_get(channel, &state); + if (status != ALT_E_SUCCESS) + { + return status; + } + if (state != ALT_DMA_CHANNEL_STATE_STOPPED) + { + return ALT_E_ERROR; + } + + // Mark channel as unallocated. + + channel_info_array[channel].flag &= ~ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel, ALT_DMA_PROGRAM_t * pgm) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is allocated + + if (!(channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + return ALT_E_ERROR; + } + + // Verify channel is stopped + + ALT_DMA_CHANNEL_STATE_t state; + ALT_STATUS_CODE status = alt_dma_channel_state_get(channel, &state); + if (status != ALT_E_SUCCESS) + { + return status; + } + if (state != ALT_DMA_CHANNEL_STATE_STOPPED) + { + return ALT_E_ERROR; + } + + // Validate the program + + if (alt_dma_program_validate(pgm) != ALT_E_SUCCESS) + { + return ALT_E_ERROR; + } + + // + // Execute the program + // + + // Get the start address + + uint32_t start = (uint32_t) &pgm->program[pgm->buffer_start]; + + dprintf("DMA[exec]: pgm->program = %p.\n", pgm->program); + dprintf("DMA[exec]: start = %p.\n", (void *)start); + + // Configure DBGINST0 and DBGINST1 to execute DMAGO targetting the requested channel. + + // For information on APB Interface, see PL330, section 2.5.1. + // For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21. + // For information on DMAGO, see PL330, section 4.3.5. + + alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR), + ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0xa0) | + ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(channel)); + + alt_write_word(ALT_DMA_DBGINST1_ADDR(ALT_DMASECURE_ADDR), start); + + // Execute the instruction held in DBGINST{0,1} + + // For information on DBGCMD, see PL330, section 3.3.19. + + alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify channel is allocated + + if (!(channel_info_array[channel].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED)) + { + return ALT_E_ERROR; + } + + // NOTE: Don't worry about the current channel state. Just issue DMAKILL + // instruction. The channel state cannot move from from Stopped back to + // Killing. + + // Configure DBGINST0 to execute DMAKILL on the requested channel thread. + // DMAKILL is short enough not to use DBGINST1 register. + + // For information on APB Interface, see PL330, section 2.5.1. + // For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21. + // For information on DMAKILL, see PL330, section 4.3.6. + + alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR), + ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0x1) | + ALT_DMA_DBGINST0_CHANNELNUMBER_SET(channel) | + ALT_DMA_DBGINST0_DEBUGTHREAD_SET(ALT_DMA_DBGINST0_DEBUGTHREAD_E_CHANNEL)); + + // Execute the instruction held in DBGINST0 + + // For information on DBGCMD, see PL330, section 3.3.19. + + alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0); + + // Wait for channel to move to KILLING or STOPPED state. Do not wait for + // the STOPPED only. If the AXI transaction hangs permanently, it can be + // waiting indefinately. + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + ALT_DMA_CHANNEL_STATE_t current; + uint32_t i = 20000; + + while (--i) + { + status = alt_dma_channel_state_get(channel, ¤t); + if (status != ALT_E_SUCCESS) + { + break; + } + if ( (current == ALT_DMA_CHANNEL_STATE_KILLING) + || (current == ALT_DMA_CHANNEL_STATE_STOPPED)) + { + break; + } + } + + if (i == 0) + { + status = ALT_E_TMO; + } + + return status; +} + +ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_REG_t reg, uint32_t * val) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on SAR, see PL330, section 3.3.13. + // For information on DAR, see PL330, section 3.3.14. + // For information on CCR, see PL330, section 3.3.15. + + switch (reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + *val = alt_read_word(ALT_DMA_SARx_ADDR(ALT_DMASECURE_ADDR, channel)); + break; + case ALT_DMA_PROGRAM_REG_DAR: + *val = alt_read_word(ALT_DMA_DARx_ADDR(ALT_DMASECURE_ADDR, channel)); + break; + case ALT_DMA_PROGRAM_REG_CCR: + *val = alt_read_word(ALT_DMA_CCRx_ADDR(ALT_DMASECURE_ADDR, channel)); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num) +{ + // Validate evt_num + + switch (evt_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // Issue the DMASEV on the DMA manager thread. + // DMASEV is short enough not to use DBGINST1 register. + + // For information on APB Interface, see PL330, section 2.5.1. + // For information on DBGINSTx, see PL330, section 3.3.20 - 3.3.21. + // For information on DMASEV, see PL330, section 4.3.15. + + alt_write_word(ALT_DMA_DBGINST0_ADDR(ALT_DMASECURE_ADDR), + ALT_DMA_DBGINST0_INSTRUCTIONBYTE0_SET(0x34) | // opcode for DMASEV + ALT_DMA_DBGINST0_INSTRUCTIONBYTE1_SET(evt_num << 3) | + ALT_DMA_DBGINST0_DEBUGTHREAD_SET(ALT_DMA_DBGINST0_DEBUGTHREAD_E_MANAGER) + ); + + // Execute the instruction held in DBGINST0 + + // For information on DBGCMD, see PL330, section 3.3.19. + + alt_write_word(ALT_DMA_DBGCMD_ADDR(ALT_DMASECURE_ADDR), 0); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state) +{ + // For information on DSR, see PL330, section 3.3.1. + + uint32_t raw_state = alt_read_word(ALT_DMA_DSR_ADDR(ALT_DMASECURE_ADDR)); + + *state = (ALT_DMA_MANAGER_STATE_t)ALT_DMA_DSR_DMASTATUS_GET(raw_state); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_STATE_t * state) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on CSR, see PL330, section 3.3.11. + + uint32_t raw_state = alt_read_word(ALT_DMA_CSRx_ADDR(ALT_DMASECURE_ADDR, channel)); + + *state = (ALT_DMA_CHANNEL_STATE_t)ALT_DMA_CSRx_CHANNELSTATUS_GET(raw_state); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_manager_fault_status_get(ALT_DMA_MANAGER_FAULT_t * fault) +{ + // For information on FTRD, see PL330, section 3.3.9. + + *fault = (ALT_DMA_MANAGER_FAULT_t)alt_read_word(ALT_DMA_FTRD_ADDR(ALT_DMASECURE_ADDR)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_channel_fault_status_get(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_FAULT_t * fault) +{ + // Validate channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on FTR, see PL330, section 3.3.10. + + *fault = (ALT_DMA_CHANNEL_FAULT_t)alt_read_word(ALT_DMA_FTRx_ADDR(ALT_DMASECURE_ADDR, channel)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num, + ALT_DMA_EVENT_SELECT_t opt) +{ + // Validate evt_num + switch (evt_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INTEN, see PL330, section 3.3.3. + + switch (opt) + { + case ALT_DMA_EVENT_SELECT_SEND_EVT: + alt_clrbits_word(ALT_DMA_INTEN_ADDR(ALT_DMASECURE_ADDR), 1 << evt_num); + break; + case ALT_DMA_EVENT_SELECT_SIG_IRQ: + alt_setbits_word(ALT_DMA_INTEN_ADDR(ALT_DMASECURE_ADDR), 1 << evt_num); + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_event_int_status_get_raw(ALT_DMA_EVENT_t evt_num) +{ + // Validate evt_num + switch (evt_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INT_EVENT_RIS, see PL330, section 3.3.4. + + uint32_t status_raw = alt_read_word(ALT_DMA_INT_EVENT_RIS_ADDR(ALT_DMASECURE_ADDR)); + + if (status_raw & (1 << evt_num)) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +ALT_STATUS_CODE alt_dma_int_status_get(ALT_DMA_EVENT_t irq_num) +{ + // Validate evt_num + switch (irq_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INTMIS, see PL330, section 3.3.5. + + uint32_t int_status = alt_read_word(ALT_DMA_INTMIS_ADDR(ALT_DMASECURE_ADDR)); + + if (int_status & (1 << irq_num)) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +ALT_STATUS_CODE alt_dma_int_clear(ALT_DMA_EVENT_t irq_num) +{ + // Validate evt_num + switch (irq_num) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // For information on INTCLR, see PL330, section 3.3.6. + + alt_write_word(ALT_DMA_INTCLR_ADDR(ALT_DMASECURE_ADDR), 1 << irq_num); + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_dma_memory_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst, + const void * src, + size_t size, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the size is zero, and no event is requested, just return success. + if ((size == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (size != 0) + { + uintptr_t udst = (uintptr_t)dst; + uintptr_t usrc = (uintptr_t)src; + + dprintf("DMA[M->M]: dst = %p.\n", dst); + dprintf("DMA[M->M]: src = %p.\n", src); + dprintf("DMA[M->M]: size = 0x%x.\n", size); + + // Detect if memory regions overshoots the address space. + + if (udst + size - 1 < udst) + { + return ALT_E_BAD_ARG; + } + if (usrc + size - 1 < usrc) + { + return ALT_E_BAD_ARG; + } + + // Detect if memory regions overlaps. + + if (udst > usrc) + { + if (usrc + size - 1 > udst) + { + return ALT_E_BAD_ARG; + } + } + else + { + if (udst + size - 1 > usrc) + { + return ALT_E_BAD_ARG; + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, usrc); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, udst); + } + + size_t sizeleft = size; + + // + // The algorithm uses the strategy described in PL330 B.3.1. + // It is extended for 2-byte and 1-byte unaligned cases. + // + + // First see how many byte(s) we need to transfer to get src to be 8 byte aligned + if (usrc & 0x7) + { + uint32_t aligncount = MIN(8 - (usrc & 0x7), sizeleft); + sizeleft -= aligncount; + + dprintf("DMA[M->M]: Total pre-alignment 1-byte burst size tranfer(s): %lu.\n", aligncount); + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SBx (Source burst length of [aligncount] transfers) + // - DBx (Destination burst length of [aligncount] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ((aligncount - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((aligncount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + // This is the number of 8-byte bursts + uint32_t burstcount = sizeleft >> 3; + + bool correction = (burstcount != 0); + + // Update the size left to transfer + sizeleft &= 0x7; + + dprintf("DMA[M->M]: Total Main 8-byte burst size transfer(s): %lu.\n", burstcount); + dprintf("DMA[M->M]: Total Main 1-byte burst size transfer(s): %u.\n", sizeleft); + + // Determine how many 16 length bursts can be done + + if (burstcount >> 4) + { + uint32_t length16burstcount = burstcount >> 4; + burstcount &= 0xf; + + dprintf("DMA[M->M]: Number of 16 burst length 8-byte transfer(s): %lu.\n", length16burstcount); + dprintf("DMA[M->M]: Number of remaining 8-byte transfer(s): %lu.\n", burstcount); + + // Program in the following parameters: + // - SS64 (Source burst size of 8-byte) + // - DS64 (Destination burst size of 8-byte) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SS64 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (length16burstcount > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(length16burstcount, 256); + length16burstcount -= loopcount; + + dprintf("DMA[M->M]: Looping %lux 16 burst length 8-byte transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [burstcount] 8-byte transfer(s) + // remaining. [burstcount] should be less than 16. + + // Do one more burst with a SB / DB of length [burstcount]. + + if (burstcount) + { + // Program in the following parameters: + // - SS64 (Source burst size of 8-byte) + // - DS64 (Destination burst size of 8-byte) + // - SBx (Source burst length of [burstlength] transfers) + // - DBx (Destination burst length of [burstlength] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ((burstcount - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SS64 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((burstcount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + // This is where the last DMAMOV CCR and DMAST is done if an + // alignment correction required. + + if ( (correction == true) + && ((usrc & 0x7) != (udst & 0x7)) // If src and dst are mod-8 congruent, no correction is needed. + ) + { + if (status == ALT_E_SUCCESS) + { + // Determine what type of correction. + + // Set the source parameters to match that of the destination + // parameters. This way the SAR is increment in the same fashion as + // DAR. This will allow the non 8-byte transfers to copy correctly. + + uint32_t ccr; + + if ((usrc & 0x3) == (udst & 0x3)) + { + dprintf("DMA[M->M]: Single correction 4-byte burst size tranfer.\n"); + + // Program in the following parameters: + // - SS32 (Source burst size of 4-byte) + // - DS32 (Destination burst size of 4-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - All other options default. + + ccr = ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ); + } + else if ((usrc & 0x1) == (udst & 0x1)) + { + dprintf("DMA[M->M]: Single correction 2-byte burst size tranfer.\n"); + + // Program in the following parameters: + // - SS16 (Source burst size of 2-byte) + // - DS16 (Destination burst size of 2-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - All other options default. + + ccr = ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS16 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS16 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ); + } + else + { + dprintf("DMA[M->M]: Single correction 1-byte burst size tranfer.\n"); + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - All other options default. + + ccr = ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ); + } + + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ccr); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + // At this point, there should be 0 - 7 1-byte transfers remaining. + + if (sizeleft) + { + dprintf("DMA[M->M]: Total post 1-byte burst size tranfer(s): %u.\n", sizeleft); + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SBx (Source burst length of [sizeleft] transfers) + // - DBx (Destination burst length of [sizeleft] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ((sizeleft - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((sizeleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } // if (size != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->M]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_zero_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * buf, + size_t size, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the size is zero, and no event is requested, just return success. + if ((size == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (size != 0) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)buf); + } + + dprintf("DMA[Z->M]: buf = %p.\n", buf); + dprintf("DMA[Z->M]: size = 0x%x.\n", size); + + size_t sizeleft = size; + + // First see how many byte(s) we need to transfer to get dst to be 8 byte aligned. + if ((uint32_t)buf & 0x7) + { + uint32_t aligncount = MIN(8 - ((uint32_t)buf & 0x7), sizeleft); + sizeleft -= aligncount; + + dprintf("DMA[Z->M]: Total pre-alignment 1-byte burst size tranfer(s): %lu.\n", aligncount); + + // Program in the following parameters: + // - DS8 (Destination burst size of 1-byte) + // - DBx (Destination burst length of [aligncount] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((aligncount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + } + + // This is the number of 8-byte bursts left + uint32_t burstcount = sizeleft >> 3; + + // Update the size left to transfer + sizeleft &= 0x7; + + dprintf("DMA[Z->M]: Total Main 8-byte burst size transfer(s): %lu.\n", burstcount); + dprintf("DMA[Z->M]: Total Main 1-byte burst size transfer(s): %u.\n", sizeleft); + + // Determine how many 16 length bursts can be done + if (burstcount >> 4) + { + uint32_t length16burstcount = burstcount >> 4; + burstcount &= 0xf; + + dprintf("DMA[Z->M]: Number of 16 burst length 8-byte transfer(s): %lu.\n", length16burstcount); + dprintf("DMA[Z->M]: Number of remaining 8-byte transfer(s): %lu.\n", burstcount); + + // Program in the following parameters: + // - DS64 (Destination burst size of 8-byte) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (length16burstcount > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(length16burstcount, 256); + length16burstcount -= loopcount; + + dprintf("DMA[Z->M]: Looping %lux 16 burst length 8-byte transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [burstcount] 8-byte transfer(s) + // remaining. [burstcount] should be less than 16. + + // Do one more burst with a SB / DB of length [burstcount]. + + if (burstcount) + { + // Program in the following parameters: + // - DS64 (Destination burst size of 8-byte) + // - DBx (Destination burst length of [burstlength] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((burstcount - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS64 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + } + + // At this point, there should be 0 - 7 1-byte transfers remaining. + + if (sizeleft) + { + dprintf("DMA[Z->M]: Total post 1-byte burst size tranfer(s): %u.\n", sizeleft); + + // Program in the following parameters: + // - DS8 (Destination burst size of 1-byte) + // - DBx (Destination burst length of [sizeleft] transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB_DEFAULT + | ALT_DMA_CCR_OPT_SS_DEFAULT + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((sizeleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMASTZ(program); + } + } + } // if (size != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[Z->M]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_memory_to_register(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst_reg, + const void * src_buf, + size_t count, + uint32_t register_width_bits, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the count is zero, and no event is requested, just return success. + if ((count == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (count != 0) + { + // Verify valid register_width_bits and construct the CCR SS and DS parameters. + uint32_t ccr_ss_ds_mask = 0; + + if (status == ALT_E_SUCCESS) + { + switch (register_width_bits) + { + case 8: + // Program in the following parameters: + // - SS8 (Source burst size of 8 bits) + // - DS8 (Destination burst size of 8 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_DS8; + break; + case 16: + // Program in the following parameters: + // - SS16 (Source burst size of 16 bits) + // - DS16 (Destination burst size of 16 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS16 | ALT_DMA_CCR_OPT_DS16; + break; + case 32: + // Program in the following parameters: + // - SS32 (Source burst size of 32 bits) + // - DS32 (Destination burst size of 32 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS32 | ALT_DMA_CCR_OPT_DS32; + break; + case 64: + // Program in the following parameters: + // - SS64 (Source burst size of 64 bits) + // - DS64 (Destination burst size of 64 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS64 | ALT_DMA_CCR_OPT_DS64; + break; + default: + status = ALT_E_BAD_ARG; + break; + } + } + + // Verify that the dst_reg and src_buf are aligned to the register width + if (status == ALT_E_SUCCESS) + { + if (((uintptr_t)dst_reg & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else if (((uintptr_t)src_buf & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else + { + dprintf("DMA[M->R]: dst_reg = %p.\n", dst_reg); + dprintf("DMA[M->R]: src_buf = %p.\n", src_buf); + dprintf("DMA[M->R]: count = 0x%x.\n", count); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, (uint32_t)src_buf); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)dst_reg); + } + + // This is the remaining count left to process. + uint32_t countleft = count; + + // See how many 16-length bursts we can use + if (countleft >> 4) + { + // Program in the following parameters: + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - DAF (Destination address fixed) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + uint32_t length16burst = countleft >> 4; + countleft &= 0xf; + + dprintf("DMA[M->R]: Number of 16 burst length transfer(s): %lu.\n", length16burst); + dprintf("DMA[M->R]: Number of remaining transfer(s): %lu.\n", countleft); + + // See how many 256x 16-length bursts we can use + if (length16burst >> 8) + { + uint32_t loop256length16burst = length16burst >> 8; + length16burst &= ((1 << 8) - 1); + + dprintf("DMA[M->R]: Number of 256-looped 16 burst length transfer(s): %lu.\n", loop256length16burst); + dprintf("DMA[M->R]: Number of remaining 16 burst length transfer(s): %lu.\n", length16burst); + + while (loop256length16burst > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(loop256length16burst, 256); + loop256length16burst -= loopcount; + + dprintf("DMA[M->R]: Looping %lux super loop transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // The super loop above ensures that the length16burst is below 256. + if (length16burst > 0) + { + uint32_t loopcount = length16burst; + length16burst = 0; + + dprintf("DMA[M->R]: Looping %lux 16 burst length transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [countleft] transfer(s) remaining. + // [countleft] should be less than 16. + + if (countleft) + { + // Program in the following parameters: + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - DAF (Destination address fixed) + // - SBx (Source burst length of [countleft] transfer(s)) + // - DBx (Destination burst length of [countleft] transfer(s)) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->R]: Tail end %lux transfer(s).\n", countleft); + + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ((countleft - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((countleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (count != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->R]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->R]: DMAEND program.\n"); + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_register_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst_buf, + const void * src_reg, + size_t count, + uint32_t register_width_bits, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the count is zero, and no event is requested, just return success. + if ((count == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_init(program); + } + + if (count != 0) + { + // Verify valid register_width_bits and construct the CCR SS and DS parameters. + uint32_t ccr_ss_ds_mask = 0; + + if (status == ALT_E_SUCCESS) + { + switch (register_width_bits) + { + case 8: + // Program in the following parameters: + // - SS8 (Source burst size of 8 bits) + // - DS8 (Destination burst size of 8 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_DS8; + break; + case 16: + // Program in the following parameters: + // - SS16 (Source burst size of 16 bits) + // - DS16 (Destination burst size of 16 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS16 | ALT_DMA_CCR_OPT_DS16; + break; + case 32: + // Program in the following parameters: + // - SS32 (Source burst size of 32 bits) + // - DS32 (Destination burst size of 32 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS32 | ALT_DMA_CCR_OPT_DS32; + break; + case 64: + // Program in the following parameters: + // - SS64 (Source burst size of 64 bits) + // - DS64 (Destination burst size of 64 bits) + ccr_ss_ds_mask = ALT_DMA_CCR_OPT_SS64 | ALT_DMA_CCR_OPT_DS64; + break; + default: + dprintf("DMA[R->M]: Invalid register width.\n"); + status = ALT_E_BAD_ARG; + break; + } + } + + // Verify that the dst_buf and src_reg are aligned to the register width + if (status == ALT_E_SUCCESS) + { + if (((uintptr_t)dst_buf & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else if (((uintptr_t)src_reg & ((register_width_bits >> 3) - 1)) != 0) + { + status = ALT_E_BAD_ARG; + } + else + { + dprintf("DMA[R->M]: dst_reg = %p.\n", dst_buf); + dprintf("DMA[R->M]: src_buf = %p.\n", src_reg); + dprintf("DMA[R->M]: count = 0x%x.\n", count); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, (uint32_t)src_reg); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)dst_buf); + } + + // This is the remaining count left to process. + uint32_t countleft = count; + + // See how many 16-length bursts we can use + if (countleft >> 4) + { + uint32_t length16burst = countleft >> 4; + countleft &= 0xf; + + dprintf("DMA[R->M]: Number of 16 burst length transfer(s): %lu.\n", length16burst); + dprintf("DMA[R->M]: Number of remaining transfer(s): %lu.\n", countleft); + + // + // The algorithm uses the strategy described in PL330 B.2.3. + // Not sure if registers will accept burst transfers so read the register in its own transfer. + // + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // See how many 256x 16-length bursts we can do + if (length16burst >> 8) + { + uint32_t loop256length16burst = length16burst >> 8; + length16burst &= ((1 << 8) - 1); + + dprintf("DMA[R->M]: Number of 256-looped 16 burst length transfer(s): %lu.\n", loop256length16burst); + dprintf("DMA[R->M]: Number of remaining 16 burst length transfer(s): %lu.\n", length16burst); + + while (loop256length16burst > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(loop256length16burst, 256); + loop256length16burst -= loopcount; + + dprintf("DMA[R->M]: Looping %lux super loop transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // The super loop above ensures that the length16burst is below 256. + if (length16burst > 0) + { + uint32_t loopcount = length16burst; + length16burst = 0; + + dprintf("DMA[R->M]: Looping %lux 16 burst length transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + + // At this point, we should have [countleft] transfer(s) remaining. + // [countleft] should be less than 16. + + if (countleft) + { + dprintf("DMA[R->M]: Tail end %lux transfer(s).\n", countleft); + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SSx (Source burst size of [ccr_ss_ds_mask]) + // - DSx (Destination burst size of [ccr_ss_ds_mask]) + // - SBx (Source burst length of [countleft] transfer(s)) + // - DBx (Destination burst length of [countleft] transfer(s)) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ccr_ss_ds_mask + | ((countleft - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ((countleft - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (count != 0) + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[R->M]: Adding event ...\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + return alt_dma_channel_exec(channel, program); +} + +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT +static ALT_STATUS_CODE alt_dma_memory_to_qspi(ALT_DMA_PROGRAM_t * program, + const char * src, + size_t size) +{ + if ((uintptr_t)src & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, + (uint32_t)ALT_QSPIDATA_ADDR); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, + (uint32_t)src); + } + + ///// + + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + uint32_t qspi_single_size_log2 = ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(dmaper); + uint32_t qspi_burst_size_log2 = ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(dmaper); + uint32_t qspi_single_size = 1 << qspi_single_size_log2; + uint32_t qspi_burst_size = 1 << qspi_burst_size_log2; + + dprintf("DMA[M->P][QSPI]: QSPI Single = %lu; Burst = %lu.\n", qspi_single_size, qspi_burst_size); + + // Because single transfers are equal or smaller than burst (and in the + // smaller case, it is always a clean multiple), only the single size + // check is needed for transfer composability. + if (size & (qspi_single_size - 1)) + { + dprintf("DMA[M->P][QSPI]: QSPI DMA size configuration not suitable for transfer request.\n"); + return ALT_E_ERROR; + } + + ///// + + if ((uintptr_t)src & 0x7) + { + // Source address is not 8-byte aligned. Do 1x 32-bit transfer to get it 8-byte aligned. + + dprintf("DMA[M->P][QSPI]: Creating 1x 4-byte aligning transfer.\n"); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAI + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + size -= sizeof(uint32_t); + } + + uint32_t qspi_single_count = 0; + uint32_t qspi_burst_count = size >> qspi_burst_size_log2; + + // Use QSPI burst transfers if: + // - QSPI bursts are larger than QSPI singles [AND] + // - Size is large enough that at least 1 burst will be used. + + if ( (qspi_burst_size_log2 > qspi_single_size_log2) + && (qspi_burst_count != 0) + ) + { + // qspi_burst_count = size >> qspi_burst_size_log2; + qspi_single_count = (size & (qspi_burst_size - 1)) >> qspi_single_size_log2; + + dprintf("DMA[M->P][QSPI][B]: Burst size = %lu bytes, count = %lu.\n", qspi_burst_size, qspi_burst_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t src_size_log2 = MIN(3, qspi_burst_size_log2); + + uint32_t src_length = 0; + uint32_t src_multiple = 0; + + if ((qspi_burst_size >> src_size_log2) <= 16) + { + src_length = qspi_burst_size >> src_size_log2; + src_multiple = 1; + } + else + { + src_length = 16; + src_multiple = (qspi_burst_size >> src_size_log2) >> 4; // divide by 16 + + if (src_multiple == 0) + { + dprintf("DEBUG[QSPI][B]: src_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t dst_length = 1; // dst_length is always 1 because the address is fixed. + uint32_t dst_multiple = qspi_burst_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[M->P][QSPI][B]: dst_size = %u bits, dst_length = %u, dst_multiple = %lu.\n", + 32, 1, dst_multiple); + dprintf("DMA[M->P][QSPI][B]: src_size = %u bits, src_length = %lu, src_multiple = %lu.\n", + (1 << src_size_log2) * 8, src_length, src_multiple); + + ///// + + // Program in the following parameters: + // - SAI (Source address increment) + // - SSx (Source burst size of [1 << src_size_log2]-bytes) + // - SBx (Source burst length of [src_length] transfer(s)) + // - DAF (Destination address fixed) + // - DS32 (Destination burst size of 4-bytes) + // - DB1 (Destination burst length of 1 transfer) + // - All other parameters default + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAI + | (src_size_log2 << 1) // SS + | ((src_length - 1) << 4) // SB + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // NOTE: We do not do the 256x bursts for M->P case because we only + // write up to 256 B at a time. + + while (qspi_burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_burst_count, 256); + qspi_burst_count -= loopcount; + + dprintf("DMA[M->P][QSPI][B]: Creating %lu burst-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + else + { + qspi_single_count = size >> qspi_single_size_log2; + } + + // Assemble the single portion of the DMA program. + if (qspi_single_count) + { + dprintf("DMA[M->P][QSPI][S]: Single size = %lu bytes, count = %lu.\n", qspi_single_size, qspi_single_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t src_size_log2 = MIN(3, qspi_single_size_log2); + + uint32_t src_length = 0; + uint32_t src_multiple = 0; + + if ((qspi_single_size >> src_size_log2) <= 16) + { + src_length = qspi_single_size >> src_size_log2; + src_multiple = 1; + } + else + { + src_length = 16; + src_multiple = (qspi_single_size >> src_size_log2) >> 4; // divide by 16 + + if (src_multiple == 0) + { + dprintf("DEBUG[QSPI][S]: src_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t dst_length = 1; // dst_length is always 1 becaus the address is fixed. + uint32_t dst_multiple = qspi_single_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[M->P][QSPI][S]: dst_size = %u bits, dst_length = %u, dst_multiple = %lu.\n", + 32, 1, dst_multiple); + dprintf("DMA[M->P][QSPI][S]: src_size = %u bits, src_length = %lu, src_multiple = %lu.\n", + (1 <P case because we only + // write up to 256 B at a time. + + while (qspi_single_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_single_count, 256); + qspi_single_count -= loopcount; + + dprintf("DMA[M->P][QSPI][S]: Creating %lu single-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_TX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (qspi_single_count != 0) + + return status; +} + +static ALT_STATUS_CODE alt_dma_qspi_to_memory(ALT_DMA_PROGRAM_t * program, + char * dst, + size_t size) +{ + if ((uintptr_t)dst & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, + (uint32_t)dst); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, + (uint32_t)ALT_QSPIDATA_ADDR); + } + + ///// + + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + uint32_t qspi_single_size_log2 = ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(dmaper); + uint32_t qspi_burst_size_log2 = ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(dmaper); + uint32_t qspi_single_size = 1 << qspi_single_size_log2; + uint32_t qspi_burst_size = 1 << qspi_burst_size_log2; + + dprintf("DMA[P->M][QSPI]: QSPI Single = %lu; Burst = %lu.\n", qspi_single_size, qspi_burst_size); + + // Because single transfers are equal or smaller than burst (and in the + // smaller case, it is always a clean multiple), only the single size + // check is needed for transfer composability. + if (size & (qspi_single_size - 1)) + { + dprintf("DMA[P->M][QSPI]: QSPI DMA size configuration not suitable for transfer request.\n"); + return ALT_E_ERROR; + } + + ///// + + if ((uintptr_t)dst & 0x7) + { + // Destination address is not 8-byte aligned. Do 1x 32-bit transfer to get it 8-byte aligned. + + dprintf("DMA[P->M][QSPI]: Creating 1x 4-byte aligning transfer.\n"); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAI + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + size -= sizeof(uint32_t); + } + + uint32_t qspi_single_count = 0; + uint32_t qspi_burst_count = size >> qspi_burst_size_log2; + + // Use QSPI burst transfers if: + // - QSPI bursts are larger than QSPI singles [AND] + // - Size is large enough that at least 1 burst will be used. + + if ( (qspi_burst_size_log2 > qspi_single_size_log2) + && (qspi_burst_count != 0) + ) + { + // qspi_burst_count = size >> qspi_burst_size_log2; + qspi_single_count = (size & (qspi_burst_size - 1)) >> qspi_single_size_log2; + + dprintf("DMA[P->M][QSPI][B]: Burst size = %lu bytes, count = %lu.\n", qspi_burst_size, qspi_burst_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t dst_size_log2 = MIN(3, qspi_burst_size_log2); + + uint32_t dst_length = 0; + uint32_t dst_multiple = 0; + + if ((qspi_burst_size >> dst_size_log2) <= 16) + { + dst_length = qspi_burst_size >> dst_size_log2; + dst_multiple = 1; + } + else + { + dst_length = 16; + dst_multiple = (qspi_burst_size >> dst_size_log2) >> 4; // divide by 16 + + if (dst_multiple == 0) + { + dprintf("DEBUG[QSPI][B]: dst_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t src_length = 1; // src_length is always 1 because the address is fixed. + uint32_t src_multiple = qspi_burst_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[P->M][QSPI][B]: dst_size = %u bits, dst_length = %lu, dst_multiple = %lu.\n", + (1 << dst_size_log2) * 8, dst_length, dst_multiple); + dprintf("DMA[P->M][QSPI][B]: src_size = %u bits, src_length = %u, src_multiple = %lu.\n", + 32, 1, src_multiple); + + ///// + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SS32 (Source burst size of 4-bytes) + // - SB1 (Source burst length of 1 transfer) + // - DAI (Destination address increment) + // - DSx (Destination burst size of [1 << dst_size_log2]-bytes]) + // - DBx (Destination burst length of [dst_length] transfer(s)) + // - All other parameters default + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAI + | (dst_size_log2 << 15) // DS + | ((dst_length - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // See how many 256x bursts we can construct. This will allow for extremely large requests. + + if (qspi_burst_count >> 8) + { + uint32_t qspi_burst256_count = qspi_burst_count >> 8; + qspi_burst_count &= (1 << 8) - 1; + + while (qspi_burst256_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_burst256_count, 256); + qspi_burst256_count -= loopcount; + + dprintf("DMA[P->M][QSPI][B]: Creating %lu 256x burst-type transfer(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + // Inner loop { + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Outer loop + } + } + + while (qspi_burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_burst_count, 256); + qspi_burst_count -= loopcount; + + dprintf("DMA[P->M][QSPI][B]: Creating %lu burst-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + } + else + { + qspi_single_count = size >> qspi_single_size_log2; + } + + // Assemble the single portion of the DMA program. + if (qspi_single_count) + { + dprintf("DMA[P->M][QSPI][S]: Single size = %lu bytes, count = %lu.\n", qspi_single_size, qspi_single_count); + + // 1 << 3 => 8 bytes => 64 bits, which is the width of the AXI bus. + uint32_t dst_size_log2 = MIN(3, qspi_single_size_log2); + + uint32_t dst_length = 0; + uint32_t dst_multiple = 0; + + if ((qspi_single_size >> dst_size_log2) <= 16) + { + dst_length = qspi_single_size >> dst_size_log2; + dst_multiple = 1; + } + else + { + dst_length = 16; + dst_multiple = (qspi_single_size >> dst_size_log2) >> 4; // divide by 16 + + if (dst_multiple == 0) + { + dprintf("DEBUG[QSPI][S]: dst_multiple is 0.\n"); + status = ALT_E_ERROR; + } + } + + // uint32_t src_length = 1; // src_length is always 1 because the address is fixed. + uint32_t src_multiple = qspi_single_size >> 2; // divide by sizeof(uint32_t) + + dprintf("DMA[P->M][QSPI][S]: dst_size = %u bits, dst_length = %lu, dst_multiple = %lu.\n", + (1 << dst_size_log2) * 8, dst_length, dst_multiple); + dprintf("DMA[P->M][QSPI][S]: src_size = %u bits, src_length = %u, src_multiple = %lu.\n", + 32, 1, src_multiple); + + ///// + + // Program in the following parameters: + // - SAF (Source address fixed) + // - SS32 (Source burst size of 4-bytes) + // - SB1 (Source burst length of 1 transfer) + // - DAI (Destination address increment) + // - DSx (Destination burst size of [1 << dst_size_log2]-bytes]) + // - DBx (Destination burst length of [dst_length] transfer(s)) + // - All other parameters default + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DAI + | (dst_size_log2 << 15) // DS + | ((dst_length - 1) << 18) // DB + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + // See how many 256x bursts we can construct. This will allow for extremely large requests. + + if (qspi_single_count >> 8) + { + uint32_t qspi_single256_count = qspi_single_count >> 8; + qspi_single_count &= (1 << 8) - 1; + + while (qspi_single256_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_single256_count, 256); + qspi_single256_count -= loopcount; + + dprintf("DMA[P->M][QSPI][S]: Creating %lu 256x single-type transfer(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + // Inner loop { + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, 256); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + + // } Outer loop + } + } + + while (qspi_single_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(qspi_single_count, 256); + qspi_single_count -= loopcount; + + dprintf("DMA[P->M][QSPI][S]: Creating %lu single-type transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, ALT_DMA_PERIPH_QSPI_FLASH_RX, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + for (uint32_t j = 0; j < src_multiple; ++j) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + for (uint32_t k = 0; k < dst_multiple; ++k) + { + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_NONE); + } + } + + } // if (qspi_single_count != 0) + + return status; +} +#endif // ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT +static ALT_STATUS_CODE alt_dma_memory_to_16550_single(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - DAF (Destination address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + uint32_t sizeleft = size; + + while (sizeleft > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(sizeleft, 256); + sizeleft -= loopcount; + + dprintf("DMA[M->P][16550][S]: Creating %lu transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_memory_to_16550_burst(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t burst_size, + size_t burst_count) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - DAF (Source address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DAF + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(burst_count, 256); + burst_count -= loopcount; + + dprintf("DMA[M->P][16550][B]: Creating outer %lu inner loop(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // Inner loop { + + // Loop [burst_size / 16] times. The burst_size was trimmed to the + // nearest multiple of 16 by the caller. Each burst does 16 transfers + // hence the need for the divide. + + dprintf("DMA[M->P][16550][B]: Creating inner %u transfer(s).\n", burst_size >> 4); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, burst_size >> 4); // divide by 16. + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Outer loop + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_memory_to_16550(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + ALT_16550_HANDLE_t * handle, + const void * src, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, + (uint32_t)ALT_UART_RBR_THR_DLL_ADDR(handle->location)); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, + (uint32_t)src); + } + + // Determine if FIFOs are enabled from the FCR cache + + if (ALT_UART_FCR_FIFOE_GET(handle->fcr) != 0) + { + dprintf("DMA[M->P][16550]: FIFOs enabled.\n"); + + // + // FIFOs are enabled. + // + + uint32_t tx_size; + uint32_t burst_size; + ALT_16550_FIFO_TRIGGER_TX_t trig_tx; + + // Get the TX FIFO Size + // Use the register interface to avoid coupling the 16550 and DMA. + tx_size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + + // Get the TX FIFO Trigger Level from the FCR cache + trig_tx = (ALT_16550_FIFO_TRIGGER_TX_t)ALT_UART_FCR_TET_GET(handle->fcr); + + switch (trig_tx) + { + case ALT_16550_FIFO_TRIGGER_TX_EMPTY: + burst_size = tx_size; + break; + case ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY: + burst_size = tx_size - 2; + break; + case ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL: + burst_size = 3 * (tx_size >> 2); + break; + case ALT_16550_FIFO_TRIGGER_TX_HALF_FULL: + burst_size = tx_size >> 1; + break; + default: + // This case should never happen. + return ALT_E_ERROR; + } + + if (burst_size < 16) + { + // There's no point bursting 1 byte at a time per notify, so just do single transfers. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_single(program, + periph, + size); + } + } + else + { + uint32_t sizeleft = size; + + // Now trip the burst size to a multiple of 16. + // This will optimize the bursting in the fewest possible commands. + dprintf("DMA[M->P][16550]: Untrimmed burst size = %lu.\n", burst_size); + burst_size &= ~0xf; + dprintf("DMA[M->P][16550]: Trimmed burst size = %lu.\n", burst_size); + + // Determine how many burst transfers can be done + uint32_t burst_count = 0; + + burst_count = sizeleft / burst_size; + sizeleft -= burst_count * burst_size; + + if (burst_count == 0) + { + // Do the transfer + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_single(program, + periph, + sizeleft); + } + } + else + { + // Do the burst transfers + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_burst(program, + periph, + burst_size, + burst_count); + } + + // Program the DMA engine to transfer the non-burstable items in single tranfers + if (status == ALT_E_SUCCESS) + { + status = alt_dma_memory_to_16550_single(program, + periph, + sizeleft); + } + + } // else if (burst_count == 0) + } + } + else + { + dprintf("DMA[M->P][16550]: FIFOs disabled.\n"); + + // + // FIFOs are disabled. + // + + status = alt_dma_memory_to_16550_single(program, + periph, + size); + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_16550_to_memory_single(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB1 (Source burst length of 1 transfer) + // - DB1 (Destination burst length of 1 transfer) + // - SAF (Source address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + uint32_t sizeleft = size; + + while (sizeleft > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(sizeleft, 256); + sizeleft -= loopcount; + + dprintf("DMA[P->M][16550][S]: Creating %lu transfer(s).\n", loopcount); + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_SINGLE); + } + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_16550_to_memory_burst(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + size_t burst_size, + size_t burst_count) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Program in the following parameters: + // - SS8 (Source burst size of 1-byte) + // - DS8 (Destination burst size of 1-byte) + // - SB16 (Source burst length of 16 transfers) + // - DB16 (Destination burst length of 16 transfers) + // - SAF (Source address fixed) + // - All other options default. + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB16 + | ALT_DMA_CCR_OPT_SS8 + | ALT_DMA_CCR_OPT_SAF + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB16 + | ALT_DMA_CCR_OPT_DS8 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES_DEFAULT + ) + ); + } + + while (burst_count > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t loopcount = MIN(burst_count, 256); + burst_count -= loopcount; + + dprintf("DMA[P->M][16550][B]: Creating outer %lu inner loop(s).\n", loopcount); + + // Outer loop { + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALP(program, loopcount); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAFLUSHP(program, periph); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAWFP(program, periph, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // Inner loop { + + // Loop [burst_size / 16] times. The burst_size was trimmed to the + // nearest multiple of 16 by the caller. Each burst does 16 transfers + // hence the need for the divide. + + dprintf("DMA[P->M][16550][B]: Creating inner %u transfer(s).\n", burst_size >> 4); + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALP(program, burst_size >> 4); // divide by 16. + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALD(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAST(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Inner loop + + if ((status == ALT_E_SUCCESS) && (loopcount > 1)) + { + status = alt_dma_program_DMALPEND(program, ALT_DMA_PROGRAM_INST_MOD_BURST); + } + + // } Outer loop + } + + return status; +} + +static ALT_STATUS_CODE alt_dma_16550_to_memory(ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t periph, + ALT_16550_HANDLE_t * handle, + void * dst, + size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_DAR, (uint32_t)dst); + } + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAMOV(program, ALT_DMA_PROGRAM_REG_SAR, (uint32_t)ALT_UART_RBR_THR_DLL_ADDR(handle->location)); + } + + // Determine if FIFOs are enabled from the FCR cache + + if (ALT_UART_FCR_FIFOE_GET(handle->fcr) != 0) + { + dprintf("DMA[P->M][16550]: FIFOs enabled.\n"); + + // + // FIFOs are enabled. + // + + uint32_t rx_size; + uint32_t burst_size; + ALT_16550_FIFO_TRIGGER_RX_t trig_rx; + + // Get the RX FIFO Size + // Use the register interface to avoid coupling the 16550 and DMA. + rx_size = ALT_UART_CPR_FIFO_MOD_GET(alt_read_word(ALT_UART_CPR_ADDR(handle->location))) << 4; + + // Get the RX FIFO Trigger Level from the FCR cache + trig_rx = (ALT_16550_FIFO_TRIGGER_RX_t)ALT_UART_FCR_RT_GET(handle->fcr); + + switch (trig_rx) + { + case ALT_16550_FIFO_TRIGGER_RX_ANY: + burst_size = 1; + break; + case ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL: + burst_size = rx_size >> 2; // divide by 4 + break; + case ALT_16550_FIFO_TRIGGER_RX_HALF_FULL: + burst_size = rx_size >> 1; // divide by 2 + break; + case ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL: + burst_size = rx_size - 2; + break; + default: + // This case should never happen. + return ALT_E_ERROR; + } + + if (burst_size < 16) + { + // There's no point bursting 1 byte at a time per notify, so just do single transfers. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_single(program, + periph, + size); + } + } + else + { + uint32_t sizeleft = size; + + // Now trim the burst size to a multiple of 16. + // This will optimize the bursting in the fewest possible commands. + dprintf("DMA[P->M][16550]: Untrimmed burst size = %lu.\n", burst_size); + burst_size &= ~0xf; + dprintf("DMA[P->M][16550]: Trimmed burst size = %lu.\n", burst_size); + + // Determine how many burst transfers can be done + uint32_t burst_count = 0; + + burst_count = sizeleft / burst_size; + sizeleft -= burst_count * burst_size; + + if (burst_count == 0) + { + // Do the transfer. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_single(program, + periph, + sizeleft); + } + } + else + { + // Do the burst transfers + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_burst(program, + periph, + burst_size, + burst_count); + } + + // Program the DMA engine to transfer the non-burstable items in single transfers. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_16550_to_memory_single(program, + periph, + sizeleft); + } + + } // if (burst_count == 0) + } + } + else + { + dprintf("DMA[P->M][16550]: FIFOs disabled.\n"); + + // + // FIFOs are disabled. + // + + status = alt_dma_16550_to_memory_single(program, + periph, + size); + } + + return status; +} +#endif // ALT_DMA_PERIPH_PROVISION_16550_SUPPORT + +ALT_STATUS_CODE alt_dma_memory_to_periph(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + ALT_DMA_PERIPH_t dstp, + const void * src, + size_t size, + void * periph_info, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if ((size == 0) && (send_evt == false)) + { + return status; + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->P]: Init Program.\n"); + status = alt_dma_program_init(program); + } + + if ((status == ALT_E_SUCCESS) && (size != 0)) + { + switch (dstp) + { +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT + case ALT_DMA_PERIPH_QSPI_FLASH_TX: + status = alt_dma_memory_to_qspi(program, src, size); + break; +#endif + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT + case ALT_DMA_PERIPH_UART0_TX: + case ALT_DMA_PERIPH_UART1_TX: + status = alt_dma_memory_to_16550(program, dstp, + (ALT_16550_HANDLE_t *)periph_info, src, size); + break; +#endif + + case ALT_DMA_PERIPH_FPGA_0: + case ALT_DMA_PERIPH_FPGA_1: + case ALT_DMA_PERIPH_FPGA_2: + case ALT_DMA_PERIPH_FPGA_3: + case ALT_DMA_PERIPH_FPGA_4: + case ALT_DMA_PERIPH_FPGA_5: + case ALT_DMA_PERIPH_FPGA_6: + case ALT_DMA_PERIPH_FPGA_7: + case ALT_DMA_PERIPH_I2C0_TX: + case ALT_DMA_PERIPH_I2C1_TX: + case ALT_DMA_PERIPH_I2C2_TX: + case ALT_DMA_PERIPH_I2C3_TX: + case ALT_DMA_PERIPH_SPI0_MASTER_TX: + case ALT_DMA_PERIPH_SPI0_SLAVE_TX: + case ALT_DMA_PERIPH_SPI1_MASTER_TX: + case ALT_DMA_PERIPH_SPI1_SLAVE_TX: + + default: + status = ALT_E_BAD_ARG; + break; + } + } + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[M->P]: Adding event.\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + + return alt_dma_channel_exec(channel, program); +} + +ALT_STATUS_CODE alt_dma_periph_to_memory(ALT_DMA_CHANNEL_t channel, + ALT_DMA_PROGRAM_t * program, + void * dst, + ALT_DMA_PERIPH_t srcp, + size_t size, + void * periph_info, + bool send_evt, + ALT_DMA_EVENT_t evt) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if ((size == 0) && (send_evt == false)) + { + return ALT_E_SUCCESS; + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[P->M]: Init Program.\n"); + status = alt_dma_program_init(program); + } + + if ((status == ALT_E_SUCCESS) && (size != 0)) + { + switch (srcp) + { +#if ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT + case ALT_DMA_PERIPH_QSPI_FLASH_RX: + status = alt_dma_qspi_to_memory(program, dst, size); + break; +#endif + +#if ALT_DMA_PERIPH_PROVISION_16550_SUPPORT + case ALT_DMA_PERIPH_UART0_RX: + case ALT_DMA_PERIPH_UART1_RX: + status = alt_dma_16550_to_memory(program, srcp, + (ALT_16550_HANDLE_t *)periph_info, dst, size); + break; +#endif + + case ALT_DMA_PERIPH_FPGA_0: + case ALT_DMA_PERIPH_FPGA_1: + case ALT_DMA_PERIPH_FPGA_2: + case ALT_DMA_PERIPH_FPGA_3: + case ALT_DMA_PERIPH_FPGA_4: + case ALT_DMA_PERIPH_FPGA_5: + case ALT_DMA_PERIPH_FPGA_6: + case ALT_DMA_PERIPH_FPGA_7: + case ALT_DMA_PERIPH_I2C0_RX: + case ALT_DMA_PERIPH_I2C1_RX: + case ALT_DMA_PERIPH_I2C2_RX: + case ALT_DMA_PERIPH_I2C3_RX: + case ALT_DMA_PERIPH_SPI0_MASTER_RX: + case ALT_DMA_PERIPH_SPI0_SLAVE_RX: + case ALT_DMA_PERIPH_SPI1_MASTER_RX: + case ALT_DMA_PERIPH_SPI1_SLAVE_RX: + + default: + status = ALT_E_BAD_ARG; + break; + } + } + + // Send event if requested. + if (send_evt) + { + if (status == ALT_E_SUCCESS) + { + dprintf("DMA[P->M]: Adding event.\n"); + status = alt_dma_program_DMASEV(program, evt); + } + } + + // Now that everything is done, end the program. + if (status == ALT_E_SUCCESS) + { + status = alt_dma_program_DMAEND(program); + } + + // If there was a problem assembling the program, clean up the buffer and exit. + if (status != ALT_E_SUCCESS) + { + // Do not report the status for the clear operation. A failure should be + // reported regardless of if the clear is successful. + alt_dma_program_clear(program); + return status; + } + + // Execute the program on the given channel. + + return alt_dma_channel_exec(channel, program); +} + +///// + +static bool alt_dma_is_init(void) +{ + uint32_t permodrst = alt_read_word(ALT_RSTMGR_PERMODRST_ADDR); + + if (permodrst & ALT_RSTMGR_PERMODRST_DMA_SET_MSK) + { + return false; + } + else + { + return true; + } +} + +ALT_STATUS_CODE alt_dma_ecc_start(void * block, size_t size) +{ + if (alt_dma_is_init() == false) + { + return ALT_E_ERROR; + } + + if ((uintptr_t)block & (sizeof(uint64_t) - 1)) + { + return ALT_E_ERROR; + } + + // Verify that all channels are either unallocated or allocated and idle. + + for (int i = 0; i < ARRAY_COUNT(channel_info_array); ++i) + { + if (channel_info_array[i].flag & ALT_DMA_CHANNEL_INFO_FLAG_ALLOCED) + { + ALT_DMA_CHANNEL_STATE_t state; + alt_dma_channel_state_get((ALT_DMA_CHANNEL_t)i, &state); + + if (state != ALT_DMA_CHANNEL_STATE_STOPPED) + { + dprintf("DMA[ECC]: Error: Channel %d state is non-stopped (%d).\n", i, (int)state); + return ALT_E_ERROR; + } + } + } + + ///// + + // Enable ECC for DMA RAM + + dprintf("DEBUG[DMA][ECC]: Enable ECC in SysMgr.\n"); + alt_write_word(ALT_SYSMGR_ECC_DMA_ADDR, ALT_SYSMGR_ECC_DMA_EN_SET_MSK); + + // Clear any pending spurious DMA ECC interrupts. + + dprintf("DEBUG[DMA][ECC]: Clear any pending spurious ECC status in SysMgr.\n"); + alt_write_word(ALT_SYSMGR_ECC_DMA_ADDR, + ALT_SYSMGR_ECC_DMA_EN_SET_MSK + | ALT_SYSMGR_ECC_DMA_SERR_SET_MSK + | ALT_SYSMGR_ECC_DMA_DERR_SET_MSK); + + return ALT_E_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_dma_program.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_dma_program.c new file mode 100644 index 000000000..3b4e670b9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_dma_program.c @@ -0,0 +1,1064 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_dma_program.h" +#include "alt_cache.h" +#include + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +// +// The following section describes how the bits are used in the "flag" field: +// + +// [17:16] Which loop registers (LOOP0, LOOP1) are currently being used by a +// partially assembled program. LOOP0 is always used before LOOP1. LOOP1 is +// always ended before LOOP0. +#define ALT_DMA_PROGRAM_FLAG_LOOP0 (1UL << 16) +#define ALT_DMA_PROGRAM_FLAG_LOOP1 (1UL << 17) +#define ALT_DMA_PROGRAM_FLAG_LOOP_ALL (ALT_DMA_PROGRAM_FLAG_LOOP0 | ALT_DMA_PROGRAM_FLAG_LOOP1) + +// [18] Flag that marks LOOP0 as a forever loop. Said another way, LOOP0 is +// being used to execute the DMALPFE directive. +#define ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE (1UL << 18) +// [19] Flag that marks LOOP1 as a forever loop. Said another way, LOOP1 is +// being used to execute the DMALPFE directive. +#define ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE (1UL << 19) + +// [24] Flag that the first SAR has been programmed. The SAR field is valid and +// is the offset from the start of the buffer where SAR is located. +#define ALT_DMA_PROGRAM_FLAG_SAR (1UL << 24) +// [25] Flag that the first DAR has been programmed. The DAR field is valid and +// is the offset from the start of the buffer where DAR is located. +#define ALT_DMA_PROGRAM_FLAG_DAR (1UL << 25) + +// [31] Flag that marks the last assembled instruction as DMAEND. +#define ALT_DMA_PROGRAM_FLAG_ENDED (1UL << 31) + +///// + +ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm) +{ + // Clear the variables that matter. + pgm->flag = 0; + pgm->code_size = 0; + + // Calculate the cache aligned start location of the buffer. + size_t buffer = (size_t)pgm->program; + size_t offset = ((buffer + ALT_DMA_PROGRAM_CACHE_LINE_SIZE - 1) & ~(ALT_DMA_PROGRAM_CACHE_LINE_SIZE - 1)) - buffer; + + // It is safe to cast to uint16_t because the extra offset can only be up to + // (ALT_DMA_PROGRAM_CACHE_LINE_SIZE - 1) or 31, which is within range of the + // uint16_t. + pgm->buffer_start = (uint16_t)offset; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm) +{ + // Clear the variables that matter + pgm->flag = 0; + pgm->code_size = 0; + + return ALT_E_SUCCESS; +} + +__attribute__((weak)) ALT_STATUS_CODE alt_cache_system_clean(void * address, size_t length) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm) +{ + // Verify that at least one instruction is in the buffer + if (pgm->code_size == 0) + { + return ALT_E_ERROR; + } + + // Verify all loops are completed. + if (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + return ALT_E_ERROR; + } + + // Verify last item is DMAEND + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_ENDED)) + { + return ALT_E_ERROR; + } + + // Sync the DMA program to RAM. + void * vaddr = (void *)((uintptr_t)(pgm->program + pgm->buffer_start) & ~(ALT_CACHE_LINE_SIZE - 1)); + size_t length = (pgm->code_size + ALT_CACHE_LINE_SIZE) & ~(ALT_CACHE_LINE_SIZE - 1); + + dprintf("DEBUG[DMAP]: Program (real) @ %p, length = 0x%x.\n", pgm->program + pgm->buffer_start, pgm->code_size); + dprintf("DEBUG[DMAP]: Clean: addr = %p, length = 0x%x.\n", vaddr, length); + + return alt_cache_system_clean(vaddr, length); +} + +ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, + uint32_t current, uint32_t * progress) +{ + // Pointer to where the register is initialized in the program buffer. + uint8_t * buffer = NULL; + + switch (reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_SAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->sar; + break; + + case ALT_DMA_PROGRAM_REG_DAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_DAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->dar; + break; + + default: + return ALT_E_BAD_ARG; + } + + uint32_t initial = + (buffer[3] << 24) | + (buffer[2] << 16) | + (buffer[1] << 8) | + (buffer[0] << 0); + + *progress = current - initial; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, uint32_t val) +{ + uint8_t * buffer = NULL; + + switch (reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_SAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->sar; + break; + + case ALT_DMA_PROGRAM_REG_DAR: + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_DAR)) + { + return ALT_E_BAD_ARG; + } + buffer = pgm->program + pgm->buffer_start + pgm->dar; + break; + + default: + return ALT_E_BAD_ARG; + } + + buffer[0] = (uint8_t)((val >> 0) & 0xff); + buffer[1] = (uint8_t)((val >> 8) & 0xff); + buffer[2] = (uint8_t)((val >> 16) & 0xff); + buffer[3] = (uint8_t)((val >> 24) & 0xff); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val) +{ + // For information on DMAADDH, see PL330, section 4.3.1. + + // Check for sufficient space in buffer + if ((pgm->code_size + 3) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid register; construct instruction modifier. + uint8_t ra_mask = 0; + switch (addr_reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + ra_mask = 0x0; + break; + case ALT_DMA_PROGRAM_REG_DAR: + ra_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAADDH + buffer[0] = 0x54 | ra_mask; + buffer[1] = (uint8_t)(val & 0xff); + buffer[2] = (uint8_t)(val >> 8); + + // Update the code size. + pgm->code_size += 3; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val) +{ + // For information on DMAADNH, see PL330, section 4.3.2. + + // Check for sufficient space in buffer + if ((pgm->code_size + 3) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid register; construct instruction modifier. + uint8_t ra_mask = 0; + switch (addr_reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + ra_mask = 0x0; + break; + case ALT_DMA_PROGRAM_REG_DAR: + ra_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAADNH + buffer[0] = 0x5c | ra_mask; + buffer[1] = (uint8_t)(val & 0xff); + buffer[2] = (uint8_t)(val >> 8); + + // Update the code size. + pgm->code_size += 3; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMAEND, see PL330, section 4.3.3. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAEND + buffer[0] = 0x00; + + // Update the code size. + pgm->code_size += 1; + + // Mark program as ended. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_ENDED; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph) +{ + // For information on DMAFLUSHP, see PL330, section 4.3.4. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAFLUSHP + buffer[0] = 0x35; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_CHANNEL_t channel, uint32_t val, + ALT_DMA_SECURITY_t sec) +{ + // For information on DMAGO, see PL330, section 4.3.5. + + // Check for sufficient space in buffer + if ((pgm->code_size + 6) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify channel + switch (channel) + { + case ALT_DMA_CHANNEL_0: + case ALT_DMA_CHANNEL_1: + case ALT_DMA_CHANNEL_2: + case ALT_DMA_CHANNEL_3: + case ALT_DMA_CHANNEL_4: + case ALT_DMA_CHANNEL_5: + case ALT_DMA_CHANNEL_6: + case ALT_DMA_CHANNEL_7: + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify security; construct ns mask value + uint8_t ns_mask = 0; + switch (sec) + { + case ALT_DMA_SECURITY_DEFAULT: + case ALT_DMA_SECURITY_SECURE: + ns_mask = 0x0; + break; + case ALT_DMA_SECURITY_NONSECURE: + ns_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAGO + buffer[0] = 0xa0 | ns_mask; + buffer[1] = (uint8_t)channel; + buffer[2] = (uint8_t)((val >> 0) & 0xff); + buffer[3] = (uint8_t)((val >> 8) & 0xff); + buffer[4] = (uint8_t)((val >> 16) & 0xff); + buffer[5] = (uint8_t)((val >> 24) & 0xff); + + // Update the code size. + pgm->code_size += 6; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMAKILL, see PL330, section 4.3.6. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAKILL + buffer[0] = 0x01; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMALD, see PL330, section 4.3.7. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs, x mask value. + uint8_t bsx_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_NONE: + bsx_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsx_mask = 0x1; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsx_mask = 0x3; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALD + buffer[0] = 0x04 | bsx_mask; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph) +{ + // For information on DMALDP, see PL330, section 4.3.8. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs mask value. + uint8_t bs_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bs_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bs_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALDP + buffer[0] = 0x25 | bs_mask; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, + uint32_t iterations) +{ + // For information on DMALP, see PL330, section 4.3.9. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify iterations in range + if ((iterations == 0) || (iterations > 256)) + { + return ALT_E_BAD_ARG; + } + + // Find suitable LOOPx register to use; construct lc mask value. + uint8_t lc_mask = 0; + switch (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + case 0: // No LOOPx in use. Use LOOP0. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP0; + pgm->loop0 = pgm->code_size + 2; // This is the first instruction after the DMALP + lc_mask = 0x0; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP0: // LOOP0 in use. Use LOOP1. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP1; + pgm->loop1 = pgm->code_size + 2; // This is the first instruction after the DMALP + lc_mask = 0x2; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP_ALL: // All LOOPx in use. Report error. + return ALT_E_BAD_OPERATION; + + default: // Catastrophic error !!! + return ALT_E_ERROR; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALP + buffer[0] = 0x20 | lc_mask; + buffer[1] = (uint8_t)(iterations - 1); + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMALPEND, see PL330, section 4.3.10. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs, x mask value. + uint8_t bsx_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_NONE: + bsx_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsx_mask = 0x1; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsx_mask = 0x3; + break; + default: + return ALT_E_BAD_ARG; + } + + // Determine the loop to end, if it is a forever loop; construct lc mask, nf mask, and backwards jump value. + uint8_t lc_mask = 0; + uint8_t nf_mask = 0; + uint16_t backwards_jump = 0; + switch (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + case ALT_DMA_PROGRAM_FLAG_LOOP0: // LOOP0 in use. End LOOP0. + + backwards_jump = pgm->code_size - pgm->loop0; + + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP0; + pgm->loop0 = 0; + + lc_mask = 0x0; + + if (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE) + { + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE; + } + else + { + nf_mask = 0x10; + } + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP_ALL: // All LOOPx in use. End LOOP1. + + backwards_jump = pgm->code_size - pgm->loop1; + + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP1; + pgm->loop1 = 0; + + lc_mask = 0x4; + + if (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE) + { + pgm->flag &= ~ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE; + } + else + { + nf_mask = 0x10; + } + break; + + case 0: // No LOOPx in use. Report error! + return ALT_E_BAD_OPERATION; + + default: // Catastrophic error !!! + return ALT_E_ERROR; + } + + // Verify that the jump size is suitable + if (backwards_jump > 255) + { + return ALT_E_ARG_RANGE; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMALPEND + buffer[0] = 0x28 | nf_mask | lc_mask | bsx_mask; + buffer[1] = (uint8_t)(backwards_jump); + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMALPFE, see PL330, section 4.3.11. + + // Find suitable LOOPx register to use; + switch (pgm->flag & ALT_DMA_PROGRAM_FLAG_LOOP_ALL) + { + case 0: // No LOOPx in use. Use LOOP0. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP0; + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP0_IS_FE; + pgm->loop0 = pgm->code_size; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP0: // LOOP0 in use. Use LOOP1. + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP1; + pgm->flag |= ALT_DMA_PROGRAM_FLAG_LOOP1_IS_FE; + pgm->loop1 = pgm->code_size; + break; + + case ALT_DMA_PROGRAM_FLAG_LOOP_ALL: // All LOOPx in use. Report error. + return ALT_E_BAD_OPERATION; + + default: // Catastrophic error !!! + return ALT_E_ERROR; + } + + // Nothing to assemble. + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val) +{ + // For information on DMAMOV, see PL330, section 4.3.12. + + // Check for sufficient space in buffer + if ((pgm->code_size + 6) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify channel register; construct rd mask value + uint8_t rd_mask = 0; + switch (chan_reg) + { + case ALT_DMA_PROGRAM_REG_SAR: + rd_mask = 0; + // If SAR has not been set before, mark the location of where SAR is in the buffer. + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_SAR)) + { + pgm->flag |= ALT_DMA_PROGRAM_FLAG_SAR; + pgm->sar = pgm->code_size + 2; + } + break; + + case ALT_DMA_PROGRAM_REG_CCR: + rd_mask = 1; + break; + + case ALT_DMA_PROGRAM_REG_DAR: + rd_mask = 2; + // If DAR has not been set before, mark the location of where DAR is in the buffer. + if (!(pgm->flag & ALT_DMA_PROGRAM_FLAG_DAR)) + { + pgm->flag |= ALT_DMA_PROGRAM_FLAG_DAR; + pgm->dar = pgm->code_size + 2; + } + break; + + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAMOV + buffer[0] = 0xbc;; + buffer[1] = rd_mask; + buffer[2] = (uint8_t)((val >> 0) & 0xff); + buffer[3] = (uint8_t)((val >> 8) & 0xff); + buffer[4] = (uint8_t)((val >> 16) & 0xff); + buffer[5] = (uint8_t)((val >> 24) & 0xff); + + // Update the code size. + pgm->code_size += 6; + + return ALT_E_SUCCESS; + +} + +ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMANOP, see PL330, section 4.3.13. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMANOP + buffer[0] = 0x18; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMARMB, see PL330, section 4.3.14. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMARMB + buffer[0] = 0x12; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt) +{ + // For information on DMA, see PL330, section 4.3.15. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Validate evt selection + switch (evt) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMASEV + buffer[0] = 0x34; + buffer[1] = (uint8_t)(evt) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMAST, see PL330, section 4.3.16. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs, x mask value. + uint8_t bsx_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_NONE: + bsx_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsx_mask = 0x1; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsx_mask = 0x3; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAST + buffer[0] = 0x08 | bsx_mask; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph) +{ + // For information on DMASTP, see PL330, section 4.3.17. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify instruction modifier; construct bs mask value. + uint8_t bs_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bs_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bs_mask = 0x2; + break; + default: + return ALT_E_BAD_ARG; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMASTP + buffer[0] = 0x29 | bs_mask; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMASTZ, see PL330, section 4.3.18. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMASTZ + buffer[0] = 0x0c; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt, bool invalid) +{ + // For information on DMAWFE, see PL330, section 4.3.19. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Validate evt selection + switch (evt) + { + case ALT_DMA_EVENT_0: + case ALT_DMA_EVENT_1: + case ALT_DMA_EVENT_2: + case ALT_DMA_EVENT_3: + case ALT_DMA_EVENT_4: + case ALT_DMA_EVENT_5: + case ALT_DMA_EVENT_6: + case ALT_DMA_EVENT_7: + case ALT_DMA_EVENT_ABORT: + break; + default: + return ALT_E_BAD_ARG; + } + + // Construct i mask value + uint8_t i_mask = 0; + if (invalid) + { + i_mask = 0x2; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAWFE + buffer[0] = 0x36; + buffer[1] = ((uint8_t)(evt) << 3) | i_mask; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod) +{ + // For information on DMAWFP, see PL330, section 4.3.20. + + // Check for sufficient space in buffer + if ((pgm->code_size + 2) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Verify valid peripheral identifier. + if (periph > ((1 << 5) - 1)) + { + return ALT_E_BAD_ARG; + } + + // Verify instruction modifier; construct bs, p mask value. + uint8_t bsp_mask = 0; + switch (mod) + { + case ALT_DMA_PROGRAM_INST_MOD_SINGLE: + bsp_mask = 0x0; + break; + case ALT_DMA_PROGRAM_INST_MOD_BURST: + bsp_mask = 0x2; + break; + case ALT_DMA_PROGRAM_INST_MOD_PERIPH: + bsp_mask = 0x1; + break; + default: + return ALT_E_BAD_ARG; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAWFP + buffer[0] = 0x30 | bsp_mask; + buffer[1] = (uint8_t)(periph) << 3; + + // Update the code size. + pgm->code_size += 2; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm) +{ + // For information on DMAWMB, see PL330, section 4.3.21. + + // Check for sufficient space in buffer + if ((pgm->code_size + 1) > ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE) + { + return ALT_E_BUF_OVF; + } + + // Buffer of where to assemble the instruction. + uint8_t * buffer = pgm->program + pgm->buffer_start + pgm->code_size; + + // Assemble DMAWMB + buffer[0] = 0x13; + + // Update the code size. + pgm->code_size += 1; + + return ALT_E_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_ecc.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_ecc.c new file mode 100644 index 000000000..f170bc456 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_ecc.c @@ -0,0 +1,875 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include "alt_ecc.h" +#include "socal/alt_sysmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +#ifndef ALT_MMU_SMALL_PAGE_SIZE +#define ALT_MMU_SMALL_PAGE_SIZE (4 * 1024) +#endif + +// +// This block of memory is scratch space used to scrub any ECC protected memory. It +// is the size of the largest block of memory required aligned to the strictest +// alignment. +// - L2 Data : Up to size of L2 way + size of L1 => 64 KiB + 32 KiB. Must be +// aligned to MMU small page boundary to be properly pageable. (largest RAM, +// strictest alignment) +// - OCRAM : Size of OCRAM => 64 KiB. +// - DMA : 0B. +// - QSPI : 2 KiB. +// +static char block[(64 + 32) * 1024] __attribute__ ((aligned (ALT_MMU_SMALL_PAGE_SIZE))); + +__attribute__((weak)) ALT_STATUS_CODE alt_cache_l2_ecc_start(void * block, size_t size) +{ + return ALT_E_SUCCESS; +} + +static ALT_STATUS_CODE alt_ocram_ecc_start(void * block, size_t size); + +__attribute__((weak)) ALT_STATUS_CODE alt_dma_ecc_start(void * block, size_t size) +{ + return ALT_E_SUCCESS; +} + +__attribute__((weak)) ALT_STATUS_CODE alt_qspi_ecc_start(void * block, size_t size) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_ecc_start(const ALT_ECC_RAM_ENUM_t ram_block) +{ + void * ecc_addr; + uint32_t ecc_bits; + + switch (ram_block) + { + case ALT_ECC_RAM_L2_DATA: + return alt_cache_l2_ecc_start(block, sizeof(block)); + + case ALT_ECC_RAM_OCRAM: + return alt_ocram_ecc_start(block, sizeof(block)); + + case ALT_ECC_RAM_USB0: + ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_USB0_EN_SET_MSK; + break; + case ALT_ECC_RAM_USB1: + ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_USB1_EN_SET_MSK; + break; + case ALT_ECC_RAM_EMAC0: + ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK; + break; + case ALT_ECC_RAM_EMAC1: + ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK; + break; + case ALT_ECC_RAM_DMA: + return alt_dma_ecc_start(block, sizeof(block)); + + case ALT_ECC_RAM_CAN0: + ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_CAN0_EN_SET_MSK; + break; + case ALT_ECC_RAM_CAN1: + ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_CAN1_EN_SET_MSK; + break; + case ALT_ECC_RAM_NAND: + ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR; + ecc_bits = ALT_SYSMGR_ECC_NAND_EN_SET_MSK; + break; + case ALT_ECC_RAM_QSPI: + return alt_qspi_ecc_start(block, sizeof(block)); + + case ALT_ECC_RAM_SDMMC: + ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR; + ecc_bits = ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK; + break; + default: + return ALT_E_ERROR; + } + + alt_setbits_word(ecc_addr, ecc_bits); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_ecc_stop(const ALT_ECC_RAM_ENUM_t ram_block) +{ + void * ecc_addr; + uint32_t ecc_bits; + + switch (ram_block) + { + case ALT_ECC_RAM_L2_DATA: + ecc_addr = ALT_SYSMGR_ECC_L2_ADDR; + ecc_bits = ALT_SYSMGR_ECC_L2_EN_SET_MSK; + break; + case ALT_ECC_RAM_OCRAM: + ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR; + ecc_bits = ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK; + break; + case ALT_ECC_RAM_USB0: + ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_USB0_EN_SET_MSK; + break; + case ALT_ECC_RAM_USB1: + ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_USB1_EN_SET_MSK; + break; + case ALT_ECC_RAM_EMAC0: + ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK; + break; + case ALT_ECC_RAM_EMAC1: + ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK; + break; + case ALT_ECC_RAM_DMA: + ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR; + ecc_bits = ALT_SYSMGR_ECC_DMA_EN_SET_MSK; + break; + case ALT_ECC_RAM_CAN0: + ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_CAN0_EN_SET_MSK; + break; + case ALT_ECC_RAM_CAN1: + ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_CAN1_EN_SET_MSK; + break; + case ALT_ECC_RAM_NAND: + ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR; + ecc_bits = ALT_SYSMGR_ECC_NAND_EN_SET_MSK; + break; + case ALT_ECC_RAM_QSPI: + ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR; + ecc_bits = ALT_SYSMGR_ECC_QSPI_EN_SET_MSK; + break; + case ALT_ECC_RAM_SDMMC: + ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR; + ecc_bits = ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK; + break; + default: + return ALT_E_ERROR; + } + + alt_clrbits_word(ecc_addr, ecc_bits); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_ecc_is_enabled(const ALT_ECC_RAM_ENUM_t ram_block) +{ + void * ecc_addr; + uint32_t ecc_bits; + + switch (ram_block) + { + case ALT_ECC_RAM_L2_DATA: + ecc_addr = ALT_SYSMGR_ECC_L2_ADDR; + ecc_bits = ALT_SYSMGR_ECC_L2_EN_SET_MSK; + break; + case ALT_ECC_RAM_OCRAM: + ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR; + ecc_bits = ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK; + break; + case ALT_ECC_RAM_USB0: + ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_USB0_EN_SET_MSK; + break; + case ALT_ECC_RAM_USB1: + ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_USB1_EN_SET_MSK; + break; + case ALT_ECC_RAM_EMAC0: + ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK; + break; + case ALT_ECC_RAM_EMAC1: + ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK; + break; + case ALT_ECC_RAM_DMA: + ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR; + ecc_bits = ALT_SYSMGR_ECC_DMA_EN_SET_MSK; + break; + case ALT_ECC_RAM_CAN0: + ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_CAN0_EN_SET_MSK; + break; + case ALT_ECC_RAM_CAN1: + ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_CAN1_EN_SET_MSK; + break; + case ALT_ECC_RAM_NAND: + ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR; + ecc_bits = ALT_SYSMGR_ECC_NAND_EN_SET_MSK; + break; + case ALT_ECC_RAM_QSPI: + ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR; + ecc_bits = ALT_SYSMGR_ECC_QSPI_EN_SET_MSK; + break; + case ALT_ECC_RAM_SDMMC: + ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR; + ecc_bits = ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK; + break; + default: + return ALT_E_ERROR; + } + + if (alt_read_word(ecc_addr) & ecc_bits) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +///// + +ALT_STATUS_CODE alt_ecc_status_get(const ALT_ECC_RAM_ENUM_t ram_block, + uint32_t *status) +{ + uint32_t ecc_bits; + uint32_t ecc_mask = 0; + + switch (ram_block) + { +// case ALT_ECC_RAM_L2_DATA: + + case ALT_ECC_RAM_OCRAM: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_OCRAM_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_OCRAM_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_OCRAM_DERR; + } + break; + + case ALT_ECC_RAM_USB0: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_USB0_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_USB0_SERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_USB0_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_USB0_DERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_USB0_DERR; + } + break; + + case ALT_ECC_RAM_USB1: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_USB1_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_USB1_SERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_USB1_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_USB1_DERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_USB1_DERR; + } + break; + + case ALT_ECC_RAM_EMAC0: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_EMAC0_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_EMAC0_TX_FIFO_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_EMAC0_TX_FIFO_DERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_EMAC0_RX_FIFO_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_EMAC0_RX_FIFO_DERR; + } + break; + + case ALT_ECC_RAM_EMAC1: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_EMAC1_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_EMAC1_TX_FIFO_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_EMAC1_TX_FIFO_DERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_EMAC1_RX_FIFO_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_EMAC1_RX_FIFO_DERR; + } + break; + + case ALT_ECC_RAM_DMA: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_DMA_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_DMA_SERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_DMA_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_DMA_DERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_DMA_DERR; + } + break; + + case ALT_ECC_RAM_CAN0: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_CAN0_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_CAN0_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_CAN0_DERR; + } + break; + + case ALT_ECC_RAM_CAN1: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_CAN1_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_CAN1_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_CAN1_DERR; + } + break; + + case ALT_ECC_RAM_NAND: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_NAND_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_NAND_BUFFER_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_NAND_BUFFER_DERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_NAND_WR_FIFO_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_NAND_WR_FIFO_DERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_NAND_RD_FIFO_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_NAND_RD_FIFO_DERR; + } + break; + + case ALT_ECC_RAM_QSPI: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_QSPI_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_QSPI_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_QSPI_DERR; + } + break; + + case ALT_ECC_RAM_SDMMC: + ecc_bits = alt_read_word(ALT_SYSMGR_ECC_SDMMC_ADDR); + if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_A_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_A_DERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_B_SERR; + } + if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK) + { + ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_B_DERR; + } + break; + + default: + return ALT_E_ERROR; + } + + *status = ecc_mask; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_ecc_status_clear(const ALT_ECC_RAM_ENUM_t ram_block, + const uint32_t ecc_mask) +{ + void * ecc_addr; + uint32_t ecc_bits = 0; + + switch (ram_block) + { +// case ALT_ECC_RAM_L2_DATA: + + case ALT_ECC_RAM_OCRAM: + ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_OCRAM_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_OCRAM_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK; + } + break; + + case ALT_ECC_RAM_USB0: + ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_USB0_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_USB0_SERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_USB0_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_USB0_DERR_SET_MSK; + } + break; + + case ALT_ECC_RAM_USB1: + ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_USB1_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_USB1_SERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_USB1_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_USB1_DERR_SET_MSK; + } + break; + + case ALT_ECC_RAM_EMAC0: + ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_EMAC0_TX_FIFO_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_EMAC0_TX_FIFO_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_EMAC0_RX_FIFO_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_EMAC0_RX_FIFO_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK; + } + break; + + case ALT_ECC_RAM_EMAC1: + ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_EMAC1_TX_FIFO_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_EMAC1_TX_FIFO_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_EMAC1_RX_FIFO_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_EMAC1_RX_FIFO_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK; + } + break; + + case ALT_ECC_RAM_DMA: + ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_DMA_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_DMA_SERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_DMA_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_DMA_DERR_SET_MSK; + } + break; + + case ALT_ECC_RAM_CAN0: + ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_CAN0_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_CAN0_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK; + } + break; + + case ALT_ECC_RAM_CAN1: + ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_CAN1_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_CAN1_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK; + } + break; + + case ALT_ECC_RAM_NAND: + ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_NAND_BUFFER_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_NAND_BUFFER_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_NAND_WR_FIFO_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_NAND_WR_FIFO_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_NAND_RD_FIFO_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_NAND_RD_FIFO_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK; + } + break; + + case ALT_ECC_RAM_QSPI: + ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_QSPI_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_QSPI_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK; + } + break; + + case ALT_ECC_RAM_SDMMC: + ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR; + + if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_A_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_A_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_B_SERR) + { + ecc_bits |= ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK; + } + if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_B_DERR) + { + ecc_bits |= ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK; + } + break; + + default: + return ALT_E_ERROR; + } + + // Bit 1 is always ECC enable. + // Be sure not to clear other conditions that may be active but not requested to be cleared. + alt_write_word(ecc_addr, (alt_read_word(ecc_addr) & (1 << 0)) | ecc_bits); + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_ecc_serr_inject(const ALT_ECC_RAM_ENUM_t ram_block) +{ + void * ecc_addr; + uint32_t ecc_bits; + + switch (ram_block) + { + case ALT_ECC_RAM_L2_DATA: + ecc_addr = ALT_SYSMGR_ECC_L2_ADDR; + ecc_bits = ALT_SYSMGR_ECC_L2_INJS_SET_MSK; + break; + case ALT_ECC_RAM_OCRAM: + ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR; + ecc_bits = ALT_SYSMGR_ECC_OCRAM_INJS_SET_MSK; + break; + case ALT_ECC_RAM_USB0: + ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_USB0_INJS_SET_MSK; + break; + case ALT_ECC_RAM_USB1: + ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_USB1_INJS_SET_MSK; + break; + case ALT_ECC_RAM_EMAC0: + ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK + | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK; + break; + case ALT_ECC_RAM_EMAC1: + ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET_MSK + | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET_MSK; + break; + case ALT_ECC_RAM_DMA: + ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR; + ecc_bits = ALT_SYSMGR_ECC_DMA_INJS_SET_MSK; + break; + case ALT_ECC_RAM_CAN0: + ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_CAN0_INJS_SET_MSK; + break; + case ALT_ECC_RAM_CAN1: + ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_CAN1_INJS_SET_MSK; + break; + case ALT_ECC_RAM_NAND: + ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR; + ecc_bits = ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK + | ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK + | ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK; + break; + case ALT_ECC_RAM_QSPI: + ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR; + ecc_bits = ALT_SYSMGR_ECC_QSPI_INJS_SET_MSK; + break; + case ALT_ECC_RAM_SDMMC: + ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR; + ecc_bits = ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET_MSK + | ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET_MSK; + break; + default: + return ALT_E_ERROR; + } + + uint32_t reg = alt_read_word(ecc_addr); + alt_write_word(ecc_addr, reg | ecc_bits); + alt_write_word(ecc_addr, reg); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_ecc_derr_inject(const ALT_ECC_RAM_ENUM_t ram_block) +{ + void * ecc_addr; + uint32_t ecc_bits; + + switch (ram_block) + { + case ALT_ECC_RAM_L2_DATA: + ecc_addr = ALT_SYSMGR_ECC_L2_ADDR; + ecc_bits = ALT_SYSMGR_ECC_L2_INJD_SET_MSK; + break; + case ALT_ECC_RAM_OCRAM: + ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR; + ecc_bits = ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK; + break; + case ALT_ECC_RAM_USB0: + ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_USB0_INJD_SET_MSK; + break; + case ALT_ECC_RAM_USB1: + ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_USB1_INJD_SET_MSK; + break; + case ALT_ECC_RAM_EMAC0: + ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK + | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK; + break; + case ALT_ECC_RAM_EMAC1: + ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK + | ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK; + break; + case ALT_ECC_RAM_DMA: + ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR; + ecc_bits = ALT_SYSMGR_ECC_DMA_INJD_SET_MSK; + break; + case ALT_ECC_RAM_CAN0: + ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR; + ecc_bits = ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK; + break; + case ALT_ECC_RAM_CAN1: + ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR; + ecc_bits = ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK; + break; + case ALT_ECC_RAM_NAND: + ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR; + ecc_bits = ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK + | ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK + | ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK; + break; + case ALT_ECC_RAM_QSPI: + ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR; + ecc_bits = ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK; + break; + case ALT_ECC_RAM_SDMMC: + ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR; + ecc_bits = ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK + | ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK; + break; + default: + return ALT_E_ERROR; + } + + uint32_t reg = alt_read_word(ecc_addr); + alt_write_word(ecc_addr, reg | ecc_bits); + alt_write_word(ecc_addr, reg); + + return ALT_E_SUCCESS; +} + +///// + +static ALT_STATUS_CODE alt_ocram_ecc_start(void * block, size_t size) +{ + // CASE 163685: Overflow in ALT_OCRAM_UB_ADDR. + // const uint32_t ocram_size = ((uint32_t)ALT_OCRAM_UB_ADDR - (uint32_t)ALT_OCRAM_LB_ADDR) + 1; + const uint32_t ocram_size = ((uint32_t)0xffffffff - (uint32_t)ALT_OCRAM_LB_ADDR) + 1; + dprintf("DEBUG[ECC][OCRAM]: OCRAM Size = 0x%lx.\n", ocram_size); + + // Verify buffer is large enough to contain the entire contents of OCRAM. + if (size < ocram_size) + { + return ALT_E_ERROR; + } + + // Verify buffer is word aligned. + if ((uintptr_t)block & (sizeof(uint32_t) - 1)) + { + return ALT_E_ERROR; + } + + // Read the contents of OCRAM into the provided buffer + + uint32_t * block_iter = block; + uint32_t * ocram_iter = ALT_OCRAM_ADDR; + uint32_t size_counter = ocram_size; + + while (size_counter) + { + *block_iter = alt_read_word(ocram_iter); + ++block_iter; + ++ocram_iter; + size_counter -= sizeof(*ocram_iter); + } + + // Enable ECC + + alt_setbits_word(ALT_SYSMGR_ECC_OCRAM_ADDR, ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK); + + // Write back contents of OCRAM from buffer to OCRAM + + block_iter = block; + ocram_iter = ALT_OCRAM_ADDR; + size_counter = ocram_size; + + while (size_counter) + { + alt_write_word(ocram_iter, *block_iter); + ++block_iter; + ++ocram_iter; + size_counter -= sizeof(*ocram_iter); + } + + // Clear any pending spurious interrupts + + alt_write_word(ALT_SYSMGR_ECC_OCRAM_ADDR, + ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK + | ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK + | ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK); + + return ALT_E_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_fpga_manager.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_fpga_manager.c new file mode 100644 index 000000000..791012e55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_fpga_manager.c @@ -0,0 +1,1042 @@ + +/****************************************************************************** +* +* alt_fpga_manager.c - API for the Altera SoC FPGA manager. +* +******************************************************************************/ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "alt_fpga_manager.h" +#include "socal/socal.h" +#include "socal/hps.h" +#include "socal/alt_fpgamgr.h" +#include +#include +#include "hwlib.h" + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, __VA_ARGS__) + + +// This is the timeout used when waiting for a state change in the FPGA monitor. +#define _ALT_FPGA_TMO_STATE 2048 + +// This is the timeout used when waiting for the DCLK countdown to complete. +// The time to wait a constant + DCLK * multiplier. +#define _ALT_FPGA_TMO_DCLK_CONST 2048 +#define _ALT_FPGA_TMO_DCLK_MUL 2 + +#define _ALT_FPGA_TMO_CONFIG 8192 + +// This define is used to control whether to use the Configuration with DCLK steps +#ifndef _ALT_FPGA_USE_DCLK +#define _ALT_FPGA_USE_DCLK 0 +#endif + +///// + +// This is used in the FGPA reconfiguration streaming interface. Because FPGA +// images are commonly stored on disk, the chunk size is that of the disk size. +// We cannot choose too large a chunk size because the stack size is fairly +// small. +#define DISK_SECTOR_SIZE 512 +#define ISTREAM_CHUNK_SIZE DISK_SECTOR_SIZE + +///// + +// +// FPGA Data Type identifier enum +// +typedef enum FPGA_DATA_TYPE_e +{ + FPGA_DATA_FULL = 1, + FPGA_DATA_ISTREAM = 2 +} FPGA_DATA_TYPE_t; + +// +// FPGA Data, for Full Stream or IStream configuration +// +typedef struct FPGA_DATA_s +{ + FPGA_DATA_TYPE_t type; + + union + { + // For FPGA_DATA_FULL + struct + { + const void * buffer; + size_t length; + } full; + + // FPGA_DATA_ISTREAM + struct + { + alt_fpga_istream_t stream; + void * data; + } istream; + } mode; + +#if ALT_FPGA_ENABLE_DMA_SUPPORT + bool use_dma; + ALT_DMA_CHANNEL_t dma_channel; +#endif + +} FPGA_DATA_t; + +#if ALT_FPGA_ENABLE_DMA_SUPPORT +static ALT_STATUS_CODE alt_dma_channel_wait_for_state(ALT_DMA_CHANNEL_t channel, + ALT_DMA_CHANNEL_STATE_t state, + uint32_t count) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + ALT_DMA_CHANNEL_STATE_t current; + + uint32_t i = count; + while (--i) + { + status = alt_dma_channel_state_get(channel, ¤t); + if (status != ALT_E_SUCCESS) + { + break; + } + if (current == state) + { + break; + } + } + + if (i == 0) + { + dprintf("FPGA[AXI]: Timeout [count=%u] waiting for DMA state [%d]. Last state was [%d]", + (unsigned)count, + (int)state, (int)current); + status = ALT_E_TMO; + } + + return status; +} +#endif + +// +// Helper function which handles writing data to the AXI bus. +// +static ALT_STATUS_CODE alt_fpga_internal_writeaxi(const char * cfg_buf, uint32_t cfg_buf_len +#if ALT_FPGA_ENABLE_DMA_SUPPORT + , + bool use_dma, ALT_DMA_CHANNEL_t dma_channel +#endif + ) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + +#if ALT_FPGA_ENABLE_DMA_SUPPORT + // Use DMA if requested. + if (use_dma) + { + ALT_DMA_PROGRAM_t program; + + if (status == ALT_E_SUCCESS) + { + dprintf("FPGA[AXI]: DMA mem-to-reg ...\n"); + status = alt_dma_memory_to_register(dma_channel, &program, + ALT_FPGAMGRDATA_ADDR, + cfg_buf, + cfg_buf_len >> 2, // we need the number uint32_t's + 32, + false, ALT_DMA_EVENT_0); + } + if (status == ALT_E_SUCCESS) + { + dprintf("FPGA[AXI]: Wait for channel to stop\n"); + + // NOTE: Polling this register is much better than polling the + // FPGA status register. Thus ensure the DMA is complete here. + status = alt_dma_channel_wait_for_state(dma_channel, ALT_DMA_CHANNEL_STATE_STOPPED, cfg_buf_len); + } + } + else +#endif + { + dprintf("FPGA[AXI]: PIO memcpy() ...\n"); + + size_t i = 0; + + // Write out as many complete 32-bit chunks. + const uint32_t * buffer_32 = (const uint32_t *) cfg_buf; + while (cfg_buf_len >= sizeof(uint32_t)) + { + alt_write_word(ALT_FPGAMGRDATA_ADDR, buffer_32[i++]); + cfg_buf_len -= sizeof(uint32_t); + } + } + + // Write out remaining non 32-bit chunks. + if ((status == ALT_E_SUCCESS) && (cfg_buf_len & 0x3)) + { + dprintf("FPGA[AXI]: Copy non-aligned data ...\n"); + + const uint32_t * buffer_32 = (const uint32_t *) (cfg_buf + (cfg_buf_len & ~0x3)); + + switch (cfg_buf_len & 0x3) + { + case 3: + alt_write_word(ALT_FPGAMGRDATA_ADDR, *buffer_32 & 0x00ffffff); + break; + case 2: + alt_write_word(ALT_FPGAMGRDATA_ADDR, *buffer_32 & 0x0000ffff); + break; + case 1: + alt_write_word(ALT_FPGAMGRDATA_ADDR, *buffer_32 & 0x000000ff); + break; + default: + // This will never happen. + break; + } + } + + return status; +} + +///// + +// +// Helper function which sets the DCLKCNT, waits for DCLKSTAT to report the +// count completed, and clear the complete status. +// Returns: +// - ALT_E_SUCCESS if the FPGA DCLKSTAT reports that the DCLK count is done. +// - ALT_E_TMO if the number of polling cycles exceeds the timeout value. +// +static ALT_STATUS_CODE dclk_set_and_wait_clear(uint32_t count, uint32_t timeout) +{ + ALT_STATUS_CODE status = ALT_E_TMO; + + // Clear any existing DONE status. This can happen if a previous call to + // this function returned timeout. The counter would complete later on but + // never be cleared. + if (alt_read_word(ALT_FPGAMGR_DCLKSTAT_ADDR)) + { + alt_write_word(ALT_FPGAMGR_DCLKSTAT_ADDR, ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE); + } + + // Issue the DCLK count. + alt_write_word(ALT_FPGAMGR_DCLKCNT_ADDR, count); + + // Poll DCLKSTAT to see if it completed in the timeout period specified. + do + { + dprintf("."); + + uint32_t done = alt_read_word(ALT_FPGAMGR_DCLKSTAT_ADDR); + + if (done == ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE) + { + // Now that it is done, clear the DONE status. + alt_write_word(ALT_FPGAMGR_DCLKSTAT_ADDR, ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE); + + status = ALT_E_SUCCESS; + break; + } + } + while (timeout--); + + dprintf("\n"); + + return status; +} + +// +// Helper function which waits for the FPGA to enter the specified state. +// Returns: +// - ALT_E_SUCCESS if successful +// - ALT_E_TMO if the number of polling cycles exceeds the timeout value. +// +static ALT_STATUS_CODE wait_for_fpga_state(ALT_FPGA_STATE_t state, uint32_t timeout) +{ + ALT_STATUS_CODE status = ALT_E_TMO; + + // Poll on the state to see if it matches the requested state within the + // timeout period specified. + do + { + dprintf("."); + + ALT_FPGA_STATE_t current = alt_fpga_state_get(); + + if (current == state) + { + status = ALT_E_SUCCESS; + break; + } + } + while (timeout--); + + dprintf("\n"); + + return status; +} + +// +// Waits for the FPGA CB monitor to report the FPGA configuration status by +// polling that both CONF_DONE and nSTATUS or neither flags are set. +// +// Returns: +// - ALT_E_SUCCESS if CB monitor reports configuration successful. +// - ALT_E_FPGA_CFG if CB monitor reports configuration failure. +// - ALT_E_FPGA_CRC if CB monitor reports a CRC error. +// - ALT_E_TMO if CONF_DONE and nSTATUS fails to "settle" in the number +// of polling cycles specified by the timeout value. +// +static ALT_STATUS_CODE wait_for_config_done(uint32_t timeout) +{ + ALT_STATUS_CODE retval = ALT_E_TMO; + + // Poll on the CONF_DONE and nSTATUS both being set within the timeout + // period specified. + do + { + dprintf("."); + + uint32_t status = alt_fpga_mon_status_get(); + + // Detect CRC problems with the FGPA configuration + if (status & ALT_FPGA_MON_CRC_ERROR) + { + retval = ALT_E_FPGA_CRC; + break; + } + + bool conf_done = (status & ALT_FPGA_MON_CONF_DONE) != 0; + bool nstatus = (status & ALT_FPGA_MON_nSTATUS) != 0; + + if (conf_done == nstatus) + { + if (conf_done) + { + retval = ALT_E_SUCCESS; + } + else + { + retval = ALT_E_FPGA_CFG; + } + break; + } + } + while (timeout--); + + dprintf("\n"); + + return retval; +} + +///// + +ALT_STATUS_CODE alt_fpga_init(void) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_fpga_uninit(void) +{ + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_fpga_control_enable(void) +{ + // Simply set CTRL.EN to allow HPS to control the FPGA control block. + alt_setbits_word(ALT_FPGAMGR_CTL_ADDR, ALT_FPGAMGR_CTL_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_fpga_control_disable(void) +{ + // Simply clear CTRL.EN to allow HPS to control the FPGA control block. + alt_clrbits_word(ALT_FPGAMGR_CTL_ADDR, ALT_FPGAMGR_CTL_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +bool alt_fpga_control_is_enabled(void) +{ + // Check if CTRL.EN is set or not. + if ((alt_read_word(ALT_FPGAMGR_CTL_ADDR) & ALT_FPGAMGR_CTL_EN_SET_MSK) != 0) + { + return true; + } + else + { + return false; + } +} + +ALT_FPGA_STATE_t alt_fpga_state_get(void) +{ + // Detect FPGA power status. + // NOTE: Do not use alt_fpga_state_get() to look for ALT_FPGA_STATE_PWR_OFF. + // This is a bit of a misnomer in that the ALT_FPGA_STATE_PWR_OFF really means + // FPGA is powered off or idle (which happens just out of being reset by the + // reset manager). + if ((alt_fpga_mon_status_get() & ALT_FPGA_MON_FPGA_POWER_ON) == 0) + { + return ALT_FPGA_STATE_POWER_OFF; + } + + // The fpgamgrreg::stat::mode bits maps to the FPGA state enum. + return (ALT_FPGA_STATE_t) ALT_FPGAMGR_STAT_MOD_GET(alt_read_word(ALT_FPGAMGR_STAT_ADDR)); +} + +uint32_t alt_fpga_mon_status_get(void) +{ + return alt_read_word(ALT_FPGAMGR_MON_GPIO_EXT_PORTA_ADDR) & ((1 << 12) - 1); +} + +ALT_STATUS_CODE alt_fgpa_reset_assert(void) +{ + // Verify that HPS has control of the FPGA control block. + if (alt_fpga_control_is_enabled() != true) + { + return ALT_E_FPGA_NO_SOC_CTRL; + } + + // Detect FPGA power status. + if (alt_fpga_state_get() == ALT_FPGA_STATE_POWER_OFF) + { + return ALT_E_FPGA_PWR_OFF; + } + + // Set the nCONFIGPULL to put the FPGA into reset. + alt_setbits_word(ALT_FPGAMGR_CTL_ADDR, ALT_FPGAMGR_CTL_NCFGPULL_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_fgpa_reset_deassert(void) +{ + // Verify that HPS has control of the FPGA control block. + if (alt_fpga_control_is_enabled() != true) + { + return ALT_E_FPGA_NO_SOC_CTRL; + } + + // Detect FPGA power status. + if (alt_fpga_state_get() == ALT_FPGA_STATE_POWER_OFF) + { + return ALT_E_FPGA_PWR_OFF; + } + + // Clear the nCONFIGPULL to release the FPGA from reset. + alt_clrbits_word(ALT_FPGAMGR_CTL_ADDR, ALT_FPGAMGR_CTL_NCFGPULL_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_FPGA_CFG_MODE_t alt_fpga_cfg_mode_get(void) +{ + uint32_t msel = ALT_FPGAMGR_STAT_MSEL_GET(alt_read_word(ALT_FPGAMGR_STAT_ADDR)); + + switch (msel) + { + case ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_NOAES_NODC: // SoCAL: 0x0 + case ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AES_NODC: // SoCAL: 0x1 + case ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AESOPT_DC: // SoCAL: 0x2 + case ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_NOAES_NODC: // SoCAL: 0x4 + case ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AES_NODC: // SoCAL: 0x5 + case ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AESOPT_DC: // SoCAL: 0x6 + case ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_NOAES_NODC: // SoCAL: 0x8 + case ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AES_NODC: // SoCAL: 0x9 + case ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AESOPT_DC: // SoCAL: 0xa + case ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_NOAES_NODC: // SoCAL: 0xc + case ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AES_NODC: // SoCAL: 0xd + case ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AESOPT_DC: // SoCAL: 0xe + // The definitions for the various msel's match up with the hardware + // definitions, so just cast it to the enum type. + return (ALT_FPGA_CFG_MODE_t) msel; + default: + return ALT_FPGA_CFG_MODE_UNKNOWN; + } +} + +ALT_STATUS_CODE alt_fpga_cfg_mode_set(ALT_FPGA_CFG_MODE_t cfg_mode) +{ + // This function will always return ERROR. See header for reasons. + return ALT_E_ERROR; +} + +// +// This function handles writing data to the FPGA data register and ensuring +// the image was programmed correctly. +// +static ALT_STATUS_CODE alt_fpga_internal_configure_idata(FPGA_DATA_t * fpga_data) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Step 9: + // - Write configuration image to AXI DATA register in 4 byte chunks. + + dprintf("FPGA: === Step 9 ===\n"); + + // This is the largest configuration image possible for the largest Arria 5 + // SoC device with some generous padding added. Given that the Arria 5 SoC + // is larger than the Cyclone 5 SoC, this value will also be sufficient for + // the Cyclone 5 SoC device. + + // From the A5 datasheet, it is 186 Mb => ~ 23 MiB. Thus cap the max + // configuration data size to 32 MiB. Anything larger will cause an error + // to be reported to the user. This will also terminate the IStream + // interface should the stream never end. + + uint32_t data_limit = 32 * 1024 * 1024; + + if (fpga_data->type == FPGA_DATA_FULL) + { + if (fpga_data->mode.full.length > data_limit) + { + status = ALT_E_FPGA_CFG; + } + else + { + status = alt_fpga_internal_writeaxi(fpga_data->mode.full.buffer, fpga_data->mode.full.length +#if ALT_FPGA_ENABLE_DMA_SUPPORT + , + fpga_data->use_dma, fpga_data->dma_channel +#endif + ); + } + } + else + { + char buffer[ISTREAM_CHUNK_SIZE]; + int32_t cb_status = 0; // Callback status + + do + { + cb_status = fpga_data->mode.istream.stream(buffer, sizeof(buffer), fpga_data->mode.istream.data); + + if (cb_status > sizeof(buffer)) + { + // Callback data overflows buffer space. + status = ALT_E_FPGA_CFG_STM; + } + else if (cb_status < 0) + { + // A problem occurred when streaming data from the source. + status = ALT_E_FPGA_CFG_STM; + } + else if (cb_status == 0) + { + // End of IStream data. + break; + } + else if (cb_status > data_limit) + { + // Limit hit for the largest permissible data stream. + status = ALT_E_FPGA_CFG_STM; + } + else + { + // Copy in configuration data. + status = alt_fpga_internal_writeaxi(buffer, cb_status +#if ALT_FPGA_ENABLE_DMA_SUPPORT + , + fpga_data->use_dma, fpga_data->dma_channel +#endif + ); + + data_limit -= cb_status; + } + + if (status != ALT_E_SUCCESS) + { + break; + } + + } while (cb_status > 0); + } + + if (status != ALT_E_SUCCESS) + { + dprintf("FPGA: Error in step 9: Problem streaming or writing out AXI data.\n"); + return status; + } + + // Step 10: + // - Observe CONF_DONE and nSTATUS (active low) + // - if CONF_DONE = 1 and nSTATUS = 1, configuration was successful + // - if CONF_DONE = 0 and nSTATUS = 0, configuration failed + + dprintf("FPGA: === Step 10 ===\n"); + + status = wait_for_config_done(_ALT_FPGA_TMO_CONFIG); + + if (status != ALT_E_SUCCESS) + { + if (status == ALT_E_FPGA_CRC) + { + dprintf("FPGA: Error in step 10: CRC error detected.\n"); + return ALT_E_FPGA_CRC; + } + else if (status == ALT_E_TMO) + { + dprintf("FPGA: Error in step 10: Timeout waiting for CONF_DONE + nSTATUS.\n"); + return ALT_E_FPGA_CFG; + } + else + { + dprintf("FPGA: Error in step 10: Configuration error CONF_DONE, nSTATUS = 0.\n"); + return ALT_E_FPGA_CFG; + } + } + + return ALT_E_SUCCESS; +} + +// +// Helper function which does handles the common steps for Full Buffer or +// IStream FPGA configuration. +// +static ALT_STATUS_CODE alt_fpga_internal_configure(FPGA_DATA_t * fpga_data) +{ + // Verify preconditions. + // This is a minor difference from the configure instructions given by the NPP. + + // Verify that HPS has control of the FPGA control block. + if (alt_fpga_control_is_enabled() != true) + { + return ALT_E_FPGA_NO_SOC_CTRL; + } + + // Detect FPGA power status. + if (alt_fpga_state_get() == ALT_FPGA_STATE_POWER_OFF) + { + return ALT_E_FPGA_PWR_OFF; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + dprintf("FPGA: Configure() !!!\n"); + + // The FPGA CTRL register cache + uint32_t ctrl_reg; + + ctrl_reg = alt_read_word(ALT_FPGAMGR_CTL_ADDR); + + // Step 1: + // - Set CTRL.CFGWDTH, CTRL.CDRATIO to match cfg mode + // - Set CTRL.NCE to 0 + + dprintf("FPGA: === Step 1 ===\n"); + + int cfgwidth = 0; + int cdratio = 0; + + switch (alt_fpga_cfg_mode_get()) + { + case ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC: + cfgwidth = 16; + cdratio = 1; + break; + case ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC: + cfgwidth = 16; + cdratio = 2; + break; + case ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC: + cfgwidth = 16; + cdratio = 4; + break; + case ALT_FPGA_CFG_MODE_PP16_SLOW_NOAES_NODC: + cfgwidth = 16; + cdratio = 1; + break; + case ALT_FPGA_CFG_MODE_PP16_SLOW_AES_NODC: + cfgwidth = 16; + cdratio = 2; + break; + case ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC: + cfgwidth = 16; + cdratio = 4; + break; + case ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC: + cfgwidth = 32; + cdratio = 1; + break; + case ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC: + cfgwidth = 32; + cdratio = 4; + break; + case ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC: + cfgwidth = 32; + cdratio = 8; + break; + case ALT_FPGA_CFG_MODE_PP32_SLOW_NOAES_NODC: + cfgwidth = 32; + cdratio = 1; + break; + case ALT_FPGA_CFG_MODE_PP32_SLOW_AES_NODC: + cfgwidth = 32; + cdratio = 4; + break; + case ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC: + cfgwidth = 32; + cdratio = 8; + break; + default: + return ALT_E_ERROR; + } + + dprintf("FPGA: CDRATIO = %x\n", cdratio); + dprintf("FPGA: CFGWIDTH = %s\n", cfgwidth == 16 ? "16" : "32"); + + // Adjust CTRL for the CDRATIO + ctrl_reg &= ALT_FPGAMGR_CTL_CDRATIO_CLR_MSK; + switch (cdratio) + { + case 1: + ctrl_reg |= ALT_FPGAMGR_CTL_CDRATIO_SET(ALT_FPGAMGR_CTL_CDRATIO_E_X1); + break; + case 2: // Unused; included for completeness. + ctrl_reg |= ALT_FPGAMGR_CTL_CDRATIO_SET(ALT_FPGAMGR_CTL_CDRATIO_E_X2); + break; + case 4: + ctrl_reg |= ALT_FPGAMGR_CTL_CDRATIO_SET(ALT_FPGAMGR_CTL_CDRATIO_E_X4); + break; + case 8: + ctrl_reg |= ALT_FPGAMGR_CTL_CDRATIO_SET(ALT_FPGAMGR_CTL_CDRATIO_E_X8); + break; + default: + return ALT_E_ERROR; + } + + // Adjust CTRL for CFGWIDTH + switch (cfgwidth) + { + case 16: + ctrl_reg &= ALT_FPGAMGR_CTL_CFGWDTH_CLR_MSK; + break; + case 32: + ctrl_reg |= ALT_FPGAMGR_CTL_CFGWDTH_SET_MSK; + break; + default: + return ALT_E_ERROR; + } + + // Set NCE to 0. + ctrl_reg &= ALT_FPGAMGR_CTL_NCE_CLR_MSK; + + alt_write_word(ALT_FPGAMGR_CTL_ADDR, ctrl_reg); + + // Step 2: + // - Set CTRL.EN to 1 + + dprintf("FPGA: === Step 2 (skipped due to precondition) ===\n"); + + // Step 3: + // - Set CTRL.NCONFIGPULL to 1 to put FPGA in reset + + dprintf("FPGA: === Step 3 ===\n"); + + ctrl_reg |= ALT_FPGAMGR_CTL_NCFGPULL_SET_MSK; + alt_write_word(ALT_FPGAMGR_CTL_ADDR, ctrl_reg); + + // Step 4: + // - Wait for STATUS.MODE to report FPGA is in reset phase + + dprintf("FPGA: === Step 4 ===\n"); + + status = wait_for_fpga_state(ALT_FPGA_STATE_RESET, _ALT_FPGA_TMO_STATE); + // Handle any error conditions after reset has been unasserted. + + // Step 5: + // - Set CONTROL.NCONFIGPULL to 0 to release FPGA from reset + + dprintf("FPGA: === Step 5 ===\n"); + + ctrl_reg &= ALT_FPGAMGR_CTL_NCFGPULL_CLR_MSK; + alt_write_word(ALT_FPGAMGR_CTL_ADDR, ctrl_reg); + + if (status != ALT_E_SUCCESS) + { + // This is a failure from Step 4. + dprintf("FPGA: Error in step 4: Wait for RESET timeout.\n"); + return ALT_E_FPGA_CFG; + } + + // Step 6: + // - Wait for STATUS.MODE to report FPGA is in configuration phase + + dprintf("FPGA: === Step 6 ===\n"); + + status = wait_for_fpga_state(ALT_FPGA_STATE_CFG, _ALT_FPGA_TMO_STATE); + + if (status != ALT_E_SUCCESS) + { + dprintf("FPGA: Error in step 6: Wait for CFG timeout.\n"); + return ALT_E_FPGA_CFG; + } + + // Step 7: + // - Clear nSTATUS interrupt in CB Monitor + + dprintf("FPGA: === Step 7 ===\n"); + + alt_write_word(ALT_FPGAMGR_MON_GPIO_PORTA_EOI_ADDR, + ALT_MON_GPIO_PORTA_EOI_NS_SET(ALT_MON_GPIO_PORTA_EOI_NS_E_CLR)); + + // Step 8: + // - Set CTRL.AXICFGEN to 1 to enable config data on AXI slave bus + + dprintf("FPGA: === Step 8 ===\n"); + + ctrl_reg |= ALT_FPGAMGR_CTL_AXICFGEN_SET_MSK; + alt_write_word(ALT_FPGAMGR_CTL_ADDR, ctrl_reg); + + ///// + + // + // Helper function to handle steps 9 - 10. + // + + ALT_STATUS_CODE data_status; + data_status = alt_fpga_internal_configure_idata(fpga_data); + + ///// + + // Step 11: + // - Set CTRL.AXICFGEN to 0 to disable config data on AXI slave bus + + dprintf("FPGA: === Step 11 ===\n"); + + ctrl_reg &= ALT_FPGAMGR_CTL_AXICFGEN_CLR_MSK; + alt_write_word(ALT_FPGAMGR_CTL_ADDR, ctrl_reg); + + // Step 12: + // - Write 4 to DCLKCNT + // - Wait for STATUS.DCNTDONE = 1 + // - Clear W1C bit in STATUS.DCNTDONE + + dprintf("FPGA: === Step 12 ===\n"); + + status = dclk_set_and_wait_clear(4, _ALT_FPGA_TMO_DCLK_CONST + 4 * _ALT_FPGA_TMO_DCLK_MUL); + if (status != ALT_E_SUCCESS) + { + dprintf("FPGA: Error in step 12: Wait for dclk(4) timeout.\n"); + + // The error here is probably a result of an error in the FPGA data. + if (data_status != ALT_E_SUCCESS) + { + return data_status; + } + else + { + return ALT_E_FPGA_CFG; + } + } + +#if _ALT_FPGA_USE_DCLK + + // Extra steps for Configuration with DCLK for Initialization Phase (4.2.1.2) + + // Step 14 (using 4.2.1.2 steps), 15 (using 4.2.1.2 steps) + // - Write 0x5000 to DCLKCNT + // - Poll until STATUS.DCNTDONE = 1, write 1 to clear + + dprintf("FPGA: === Step 14 (4.2.1.2) ===\n"); + dprintf("FPGA: === Step 15 (4.2.1.2) ===\n"); + + status = dclk_set_and_wait_clear(0x5000, _ALT_FPGA_TMO_DCLK_CONST + 0x5000 * _ALT_FPGA_TMO_DCLK_MUL); + if (status == ALT_E_TMO) + { + dprintf("FPGA: Error in step 15 (4.2.1.2): Wait for dclk(0x5000) timeout.\n"); + + // The error here is probably a result of an error in the FPGA data. + if (data_status != ALT_E_SUCCESS) + { + return data_status; + } + else + { + return ALT_E_FPGA_CFG; + } + } + +#endif + + // Step 13: + // - Wait for STATUS.MODE to report USER MODE + + dprintf("FPGA: === Step 13 ===\n"); + + status = wait_for_fpga_state(ALT_FPGA_STATE_USER_MODE, _ALT_FPGA_TMO_STATE); + if (status == ALT_E_TMO) + { + dprintf("FPGA: Error in step 13: Wait for state = USER_MODE timeout.\n"); + + // The error here is probably a result of an error in the FPGA data. + if (data_status != ALT_E_SUCCESS) + { + return data_status; + } + else + { + return ALT_E_FPGA_CFG; + } + } + + // Step 14: + // - Set CTRL.EN to 0 + + dprintf("FPGA: === Step 14 (skipped due to precondition) ===\n"); + + // Return data_status. status is used for the setup of the FPGA parameters + // and should be successful. Any errors in programming the FPGA is + // returned in data_status. + return data_status; +} + +ALT_STATUS_CODE alt_fpga_configure(const void* cfg_buf, + size_t cfg_buf_len) +{ + FPGA_DATA_t fpga_data; + fpga_data.type = FPGA_DATA_FULL; + fpga_data.mode.full.buffer = cfg_buf; + fpga_data.mode.full.length = cfg_buf_len; +#if ALT_FPGA_ENABLE_DMA_SUPPORT + fpga_data.use_dma = false; +#endif + + return alt_fpga_internal_configure(&fpga_data); +} + +#if ALT_FPGA_ENABLE_DMA_SUPPORT +ALT_STATUS_CODE alt_fpga_configure_dma(const void* cfg_buf, + size_t cfg_buf_len, + ALT_DMA_CHANNEL_t dma_channel) +{ + FPGA_DATA_t fpga_data; + fpga_data.type = FPGA_DATA_FULL; + fpga_data.mode.full.buffer = cfg_buf; + fpga_data.mode.full.length = cfg_buf_len; + fpga_data.use_dma = true; + fpga_data.dma_channel = dma_channel; + + return alt_fpga_internal_configure(&fpga_data); +} +#endif + +ALT_STATUS_CODE alt_fpga_istream_configure(alt_fpga_istream_t cfg_stream, + void * user_data) +{ + FPGA_DATA_t fpga_data; + fpga_data.type = FPGA_DATA_ISTREAM; + fpga_data.mode.istream.stream = cfg_stream; + fpga_data.mode.istream.data = user_data; +#if ALT_FPGA_ENABLE_DMA_SUPPORT + fpga_data.use_dma = false; +#endif + + return alt_fpga_internal_configure(&fpga_data); +} + +#if ALT_FPGA_ENABLE_DMA_SUPPORT +ALT_STATUS_CODE alt_fpga_istream_configure_dma(alt_fpga_istream_t cfg_stream, + void * user_data, + ALT_DMA_CHANNEL_t dma_channel) +{ + FPGA_DATA_t fpga_data; + fpga_data.type = FPGA_DATA_ISTREAM; + fpga_data.mode.istream.stream = cfg_stream; + fpga_data.mode.istream.data = user_data; + fpga_data.use_dma = true; + fpga_data.dma_channel = dma_channel; + + return alt_fpga_internal_configure(&fpga_data); +} +#endif + +uint32_t alt_fpga_gpi_read(uint32_t mask) +{ + if (mask == 0) + { + return 0; + } + + return alt_read_word(ALT_FPGAMGR_GPI_ADDR) & mask; +} + +ALT_STATUS_CODE alt_fpga_gpo_write(uint32_t mask, uint32_t value) +{ + if (mask == 0) + { + return ALT_E_SUCCESS; + } + + alt_write_word(ALT_FPGAMGR_GPO_ADDR, (alt_read_word(ALT_FPGAMGR_GPO_ADDR) & ~mask) | (value & mask)); + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_fpga_man_irq_disable(ALT_FPGA_MON_STATUS_t mon_stat_mask) +{ + // Ensure only bits 11:0 are set. + if (mon_stat_mask & ~((1 << 12) - 1)) + { + return ALT_E_BAD_ARG; + } + + uint32_t current = alt_read_word(ALT_FPGAMGR_MON_GPIO_INTEN_ADDR); + current &= ~((uint32_t)mon_stat_mask) & ((1 << 12) - 1); + alt_write_word(ALT_FPGAMGR_MON_GPIO_INTEN_ADDR, current); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_fpga_man_irq_enable(ALT_FPGA_MON_STATUS_t mon_stat_mask) +{ + // Ensure only bits 11:0 are set. + if (mon_stat_mask & ~((1 << 12) - 1)) + { + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_FPGAMGR_MON_GPIO_INTEN_ADDR, mon_stat_mask); + + return ALT_E_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_generalpurpose_io.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_generalpurpose_io.c new file mode 100644 index 000000000..454cf99b3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_generalpurpose_io.c @@ -0,0 +1,777 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include +#include + +#include "socal/hps.h" +#include "socal/socal.h" +#include "socal/alt_gpio.h" +#include "socal/alt_rstmgr.h" +#include "hwlib.h" +#include "alt_generalpurpose_io.h" + + +/****************************************************************************************/ +/******************************* Useful local definitions *******************************/ +/****************************************************************************************/ + +#define ALT_GPIO_EOPA ALT_GPIO_1BIT_28 +#define ALT_GPIO_EOPB ALT_GPIO_1BIT_57 +#define ALT_GPIO_EOPC ALT_HLGPI_15 +#define ALT_GPIO_BITMASK 0x1FFFFFFF + + // expands the zero or one bit to the 29-bit GPIO word +#define ALT_GPIO_ALLORNONE(tst) ((uint32_t) ((tst == 0) ? 0 : ALT_GPIO_BITMASK)) + + +/****************************************************************************************/ +/* alt_gpio_init() initializes the GPIO modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_init(void) +{ + // put GPIO modules into system manager reset if not already there + alt_gpio_uninit(); + // release GPIO modules from system reset (w/ two-instruction delay) + alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, 0); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_uninit() uninitializes the GPIO modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_uninit(void) +{ + // put all GPIO modules into system manager reset + alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK | + ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, + ALT_GPIO_BITMASK); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_port_datadir_set() sets the specified GPIO data bits to use the data */ +/* direction(s) specified. 0 = input (default). 1 = output. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config) +{ + volatile uint32_t *addr; + + if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; } + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_SWPORTA_DDR_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DDR_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DDR_ADDR; } + else { return ALT_E_BAD_ARG; } + + alt_replbits_word(addr, mask, config); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_port_datadir_get() returns the data direction configuration of selected */ +/* bits of the designated GPIO module. */ +/****************************************************************************************/ + +uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_SWPORTA_DDR_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DDR_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DDR_ADDR; } + else { return 0; } + + return alt_read_word(addr) & mask; +} + + +/****************************************************************************************/ +/* alt_gpio_port_data_write() sets the GPIO data outputs of the specified GPIO module */ +/* to a one or zero. Actual outputs are only set if the data direction for that bit(s) */ +/* has previously been set to configure them as output(s). */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t val) +{ + volatile uint32_t *addr; + + if ((mask & ~ALT_GPIO_BITMASK) || (val & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; } + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_SWPORTA_DR_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DR_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DR_ADDR; } + else { return ALT_E_BAD_ARG; } + + alt_replbits_word(addr, mask, val); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_port_data_read() returns the value of the data inputs of the specified */ +/* GPIO module. Data direction for these bits must have been previously set to inputs. */ +/****************************************************************************************/ + +#if (!ALT_GPIO_DATAREAD_TEST_MODE) + /* This is the production code version. For software unit testing, set the */ + /* ALT_GPIO_DATAREAD_TEST_MODE flag to true in the makefile, which will compile */ + /* the GPIO test software version of alt_gpio_port_data_read() instead. */ + +uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_EXT_PORTA_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_EXT_PORTA_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_EXT_PORTA_ADDR; } + else { return 0; } + + return alt_read_word(addr) & mask; +} +#endif + + +/****************************************************************************************/ +/* alt_gpio_port_int_type_set() sets selected signals of the specified GPIO port to */ +/* be either level-sensitive ( =0) or edge-triggered ( =1). */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config) +{ + volatile uint32_t *addr; + + if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; } + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTTYPE_LEVEL_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTTYPE_LEVEL_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTTYPE_LEVEL_ADDR; } + else { return ALT_E_BAD_ARG; } + + alt_replbits_word(addr, mask, config); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_port_int_type_get() returns the interrupt configuration (edge-triggered or */ +/* level-triggered) for the specified signals of the specified GPIO module. */ +/****************************************************************************************/ + +uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTTYPE_LEVEL_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTTYPE_LEVEL_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTTYPE_LEVEL_ADDR; } + else { return 0; } + + return alt_read_word(addr) & mask; +} + + +/****************************************************************************************/ +/* alt_gpio_port_int_pol_set() sets the interrupt polarity of the signals of the */ +/* specified GPIO register (when used as inputs) to active-high ( =0) or active-low */ +/* ( =1). */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config) +{ + volatile uint32_t *addr; + + if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; } + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INT_POL_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INT_POL_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INT_POL_ADDR; } + else { return ALT_E_BAD_ARG; } + + alt_replbits_word(addr, mask, config); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_port_int_pol_get() returns the active-high or active-low polarity */ +/* configuration for the possible interrupt sources of the specified GPIO module. */ +/* 0 = The interrupt polarity for this bit is set to active-low mode. 1 = The */ +/* interrupt polarity for this bit is set to active-highmode. */ +/****************************************************************************************/ + +uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INT_POL_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INT_POL_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INT_POL_ADDR; } + else { return 0; } + + return alt_read_word(addr) & mask; +} + + +/****************************************************************************************/ +/* alt_gpio_port_debounce_set() sets the debounce configuration for input signals of */ +/* the specified GPIO module. 0 - Debounce is not selected for this signal (default). */ +/* 1 - Debounce is selected for this signal. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config) +{ + volatile uint32_t *addr; + + if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; } + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_DEBOUNCE_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_DEBOUNCE_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_DEBOUNCE_ADDR; } + else { return ALT_E_BAD_ARG; } + + alt_replbits_word(addr, mask, config); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_port_debounce_get() returns the debounce configuration for the input */ +/* signals of the specified GPIO register. 0 - Debounce is not selected for this */ +/* signal. 1 - Debounce is selected for this signal. */ +/****************************************************************************************/ + +uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_DEBOUNCE_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_DEBOUNCE_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_DEBOUNCE_ADDR; } + else { return 0; } + + return alt_read_word(addr) & mask; +} + + +/****************************************************************************************/ +/* alt_gpio_port_sync_set() sets the synchronization configuration for the signals of */ +/* the specified GPIO register. This allows for synchronizing level-sensitive */ +/* interrupts to the internal clock signal. This is a port-wide option that controls */ +/* all level-sensitive interrupt signals of that GPIO port. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, uint32_t config) +{ + volatile uint32_t *addr; + + config = (config != 0) ? 1 : 0; + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_LS_SYNC_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_LS_SYNC_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_LS_SYNC_ADDR; } + else { return ALT_E_BAD_ARG; } + + alt_write_word(addr, config); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_port_sync_get() returns the synchronization configuration for the signals */ +/* of the specified GPIO register. This allows for synchronizing level-sensitive */ +/* interrupts to the internal clock signal. This is a port-wide option that controls */ +/* all level-sensitive interrupt signals of that GPIO port. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_LS_SYNC_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_LS_SYNC_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_LS_SYNC_ADDR; } + else { return ALT_E_BAD_ARG; } // error + + return (alt_read_word(addr) != 0) ? ALT_E_TRUE : ALT_E_FALSE; +} + + +/****************************************************************************************/ +/* alt_gpio_port_config() configures a group of GPIO signals with the same parameters. */ +/* Allows for configuring all parameters of a given port at one time. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, + ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc, + uint32_t data) +{ + ALT_STATUS_CODE ret; + + // set all affected GPIO bits to inputs + ret = alt_gpio_port_datadir_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(ALT_GPIO_PIN_INPUT)); + // the ALT_GPIO_ALLORNONE() macro expands the zero or one bit to the 29-bit GPIO word + + // set trigger type + if (ret == ALT_E_SUCCESS) + { + ret = alt_gpio_port_int_type_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(type)); + } + + // set polarity + if (ret == ALT_E_SUCCESS) + { + alt_gpio_port_int_pol_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(pol)); + } + + // set debounce + if (ret == ALT_E_SUCCESS) + { + alt_gpio_port_debounce_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(debounc)); + } + + // set data output(s) + if (ret == ALT_E_SUCCESS) + { + alt_gpio_port_data_write(gpio_pid, mask, ALT_GPIO_ALLORNONE(data)); + } + + if (ret == ALT_E_SUCCESS) + { + // set data direction of one or more bits to select output + ret = alt_gpio_port_datadir_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(dir)); + } + + return ret; +} + + +/****************************************************************************************/ +/* Enables the specified GPIO data register interrupts. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config) +{ + volatile uint32_t *addr; + + if (config & ~ALT_GPIO_BITMASK) { return ALT_E_ERROR; } + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTEN_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; } + else { return ALT_E_BAD_ARG; } + + alt_replbits_word(addr, config, UINT32_MAX); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* Disables the specified GPIO data module interrupts. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config) +{ + volatile uint32_t *addr; + + if (config & ~ALT_GPIO_BITMASK) { return ALT_E_ERROR; } + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTEN_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; } + else { return ALT_E_BAD_ARG; } + + alt_replbits_word(addr, config, 0); + return ALT_E_SUCCESS; +} + + + +/****************************************************************************************/ +/* Get the current state of the specified GPIO port interrupts enables. */ +/****************************************************************************************/ + +uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTEN_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; } + else { return 0; } + + return alt_read_word(addr); +} + + +/****************************************************************************************/ +/* Masks or unmasks selected interrupt source bits of the data register of the */ +/* specified GPIO module. Uses a second bit mask to determine which signals may be */ +/* changed by this call. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t val) +{ + volatile uint32_t *addr; + + if ((mask & ~ALT_GPIO_BITMASK) || (val & ~ALT_GPIO_BITMASK)) { return ALT_E_ERROR; } + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTMSK_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTMSK_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTMSK_ADDR; } + else { return ALT_E_BAD_ARG; } // argument error + + alt_replbits_word(addr, mask, val); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* Returns the interrupt source mask of the specified GPIO module. */ +/****************************************************************************************/ + +uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTMSK_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTMSK_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTMSK_ADDR; } + else { return 0; } // error + + return alt_read_word(addr); +} + + +/****************************************************************************************/ +/* alt_gpio_port_int_status_get() returns the interrupt pending status of all signals */ +/* of the specified GPIO register. */ +/****************************************************************************************/ + +uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTSTAT_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTSTAT_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTSTAT_ADDR; } + else { return 0; } // error + + return alt_read_word(addr); +} + + +/****************************************************************************************/ +/* Clear the interrupt pending status of selected signals of the specified GPIO */ +/* register. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid, + uint32_t clrmask) +{ + volatile uint32_t *addr; + + if (clrmask & ~ALT_GPIO_BITMASK) { return ALT_E_ERROR; } + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_INTSTAT_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTSTAT_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTSTAT_ADDR; } + else { return ALT_E_BAD_ARG; } // argument error + + alt_write_word(addr, clrmask); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpio_port_idcode_get() returns the ID code of the specified GPIO module. */ +/****************************************************************************************/ + +uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_ID_CODE_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_ID_CODE_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_ID_CODE_ADDR; } + else { return 0; } + + return alt_read_word(addr); +} + + +/****************************************************************************************/ +/* alt_gpio_port_ver_get() returns the version code of the specified GPIO module. */ +/****************************************************************************************/ + +uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid) +{ + volatile uint32_t *addr; + + if (gpio_pid == ALT_GPIO_PORTA) { addr = ALT_GPIO0_VER_ID_CODE_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_VER_ID_CODE_ADDR; } + else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_VER_ID_CODE_ADDR; } + else { return 0; } + + return alt_read_word(addr); +} + + +/****************************************************************************************/ +/* alt_gpio_bit_config() configures one bit (signal) of the GPIO ports. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num, + ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, + ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce, + ALT_GPIO_PIN_DATA_t data) +{ + ALT_GPIO_PORT_t pid; + uint32_t mask; + + pid = alt_gpio_bit_to_pid(signal_num); + mask = 0x1 << alt_gpio_bit_to_port_pin(signal_num); + return alt_gpio_port_config(pid, mask, dir, type, pol, debounce, data); +} + + +/****************************************************************************************/ +/* Returns the configuration parameters of a given GPIO bit. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num, + ALT_GPIO_CONFIG_RECORD_t *config) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; + ALT_GPIO_PORT_t pid; + uint32_t mask, shift; + + if ((config != NULL) && (signal_num != ALT_END_OF_GPIO_SIGNALS) && (signal_num <= ALT_LAST_VALID_GPIO_BIT)) + { + pid = alt_gpio_bit_to_pid(signal_num); + shift = alt_gpio_bit_to_port_pin(signal_num); + if ((pid != ALT_GPIO_PORT_UNKNOWN) && (shift <= ALT_GPIO_BIT_MAX)) + { + config->signal_number = signal_num; + mask = 0x00000001 << shift; + config->direction = (alt_gpio_port_datadir_get(pid, mask) == 0) ? ALT_GPIO_PIN_INPUT : ALT_GPIO_PIN_OUTPUT; + config->type = (alt_gpio_port_int_type_get(pid, mask) == 0) ? ALT_GPIO_PIN_LEVEL_TRIG_INT : ALT_GPIO_PIN_EDGE_TRIG_INT; + + // save the following data whatever the state of config->direction + config->polarity = (alt_gpio_port_int_pol_get(pid, mask) == 0) ? ALT_GPIO_PIN_ACTIVE_LOW : ALT_GPIO_PIN_ACTIVE_HIGH; + config->debounce = (alt_gpio_port_debounce_get(pid, mask) == 0) ? ALT_GPIO_PIN_NODEBOUNCE : ALT_GPIO_PIN_DEBOUNCE; + config->data = (alt_gpio_port_data_read(pid, mask) == 0) ? ALT_GPIO_PIN_DATAZERO : ALT_GPIO_PIN_DATAONE; + ret = ALT_E_SUCCESS; + } + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpio_group_config() configures a list of GPIO bits. The GPIO bits do not have */ +/* to be configured the same, as was the case for the mask version of this function, */ +/* alt_gpio_port_config(). Each bit may be configured differently and bits may be */ +/* listed in any order. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, uint32_t len) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; + + if (config_array != NULL) + { + if (config_array->signal_number == ALT_END_OF_GPIO_SIGNALS) { ret = ALT_E_SUCCESS; } + // catches the condition where the pointers are good, but the + // first index is the escape character - which isn't an error + else + { + for (; (len-- > 0) && (config_array->signal_number != ALT_END_OF_GPIO_SIGNALS) && (config_array != NULL); config_array++) + { + ret = alt_gpio_bit_config(config_array->signal_number, + config_array->direction, config_array->type, config_array->polarity, + config_array->debounce, config_array->data); + if ((config_array->direction == ALT_GPIO_PIN_OUTPUT) && (ret == ALT_E_SUCCESS)) + { + // if the pin is set to be an output, set it to the correct value + alt_gpio_port_data_write(alt_gpio_bit_to_pid(config_array->signal_number), + 0x1 << alt_gpio_bit_to_port_pin(config_array->signal_number), + ALT_GPIO_ALLORNONE(config_array->data)); + // ret should retain the value returned by alt_gpio_bit_config() above + // and should not be changed by the alt_gpio_port_data_write() call. + } + if (((ret != ALT_E_SUCCESS) && (config_array->signal_number <= ALT_LAST_VALID_GPIO_BIT)) + || ((ret == ALT_E_SUCCESS) && (config_array->signal_number > ALT_LAST_VALID_GPIO_BIT))) + { + ret = ALT_E_ERROR; + break; + } + } + } + } + return ret; +} + + +/****************************************************************************************/ +/* Returns a list of the pin signal indices and the associated configuration settings */ +/* (data direction, interrupt type, polarity, debounce, and synchronization) of that */ +/* list of signals. Only the signal indices in the first field of each configuration */ +/* record need be filled in. This function will fill in all the other fields of the */ +/* configuration record, returning all configuration parameters in the array. A signal */ +/* number index in the array equal to ALT_END_OF_GPIO_SIGNALS (-1) also terminates the */ +/* function. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array, + uint32_t len) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; + + if ((config_array != NULL) && (config_array->signal_number == ALT_END_OF_GPIO_SIGNALS)) + { + ret = ALT_E_SUCCESS; + } + else + { + for ( ; (len > 0) && (config_array != NULL) && (config_array->signal_number != ALT_END_OF_GPIO_SIGNALS) + && (config_array->signal_number <= ALT_LAST_VALID_GPIO_BIT); len--) + { + ret = alt_gpio_bitconfig_get(config_array->signal_number, config_array); + config_array++; + if (ret != ALT_E_SUCCESS) { break; } + } + } + return ret; +} + +/****************************************************************************************/ +/* Another way to return a configuration list. The difference between this version and */ +/* alt_gpio_group_config_get() is that this version follows a separate list of signal */ +/* indices instead of having the signal list provided in the first field of the */ +/* configuration records in the array. This function will fill in the fields of the */ +/* configuration record, returning all configuration parameters in the array. A signal */ +/* number index in the array equal to ALT_END_OF_GPIO_SIGNALS (-1) also terminates */ +/* operation. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array, + ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; + + if ((config_array != NULL) && (pinid_array != NULL) && (*pinid_array == ALT_END_OF_GPIO_SIGNALS)) + { + ret = ALT_E_SUCCESS; + // catches the condition where the pointers are good, but the + // first index is the escape character - which isn't an error + } + else + { + for ( ;(len > 0) && (pinid_array != NULL) && (*pinid_array != ALT_END_OF_GPIO_SIGNALS) && (config_array != NULL); len--) + { + ret = alt_gpio_bitconfig_get(*pinid_array, config_array); + config_array++; + pinid_array++; + if (ret != ALT_E_SUCCESS) { break; } + } + } + return ret; +} + + +/****************************************************************************************/ +/* A useful utility function. Extracts the GPIO port ID from the supplied GPIO Signal */ +/* Index Number. */ +/****************************************************************************************/ + +ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num) +{ + ALT_GPIO_PORT_t pid = ALT_GPIO_PORT_UNKNOWN; + + if (pin_num <= ALT_GPIO_EOPA) { pid = ALT_GPIO_PORTA; } + else if (pin_num <= ALT_GPIO_EOPB) { pid = ALT_GPIO_PORTB; } + else if (pin_num <= ALT_GPIO_EOPC) { pid = ALT_GPIO_PORTC; } + return pid; +} + + +/****************************************************************************************/ +/* A useful utility function. Extracts the GPIO signal (pin) mask from the supplied */ +/* GPIO Signal Index Number. */ +/****************************************************************************************/ + +ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num) +{ + if (pin_num <= ALT_GPIO_EOPA) {} + else if (pin_num <= ALT_GPIO_EOPB) { pin_num -= (ALT_GPIO_EOPA + 1); } + else if (pin_num <= ALT_GPIO_EOPC) { pin_num -= (ALT_GPIO_EOPB + 1); } + else { return ALT_END_OF_GPIO_PORT_SIGNALS; } + return (ALT_GPIO_PORTBIT_t) pin_num; +} + + +/****************************************************************************************/ +/* A useful utility function. Extracts the GPIO Signal Index Number from the supplied */ +/* GPIO port ID and signal mask. If passed a bitmask composed of more than one signal, */ +/* the signal number of the lowest bitmask presented is returned. */ +/****************************************************************************************/ + +ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid, + uint32_t bitmask) +{ + uint32_t i; + + for (i=0; i <= ALT_GPIO_BITNUM_MAX ;i++) + { + if (bitmask & 0x00000001) + { + if (pid == ALT_GPIO_PORTA) {} + else if (pid == ALT_GPIO_PORTB) { i += ALT_GPIO_EOPA + 1; } + else if (pid == ALT_GPIO_PORTC) { i += ALT_GPIO_EOPB + 1; } + else { return ALT_END_OF_GPIO_SIGNALS; } + return (ALT_GPIO_1BIT_t) i; + } + bitmask >>= 1; + } + return ALT_END_OF_GPIO_SIGNALS; +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_globaltmr.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_globaltmr.c new file mode 100644 index 000000000..015bbfe1c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_globaltmr.c @@ -0,0 +1,557 @@ + +/****************************************************************************** +* +* alt_globaltmr.c - API for the Altera SoC FPGA global timer. +* +******************************************************************************/ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + + + +#include +#include +#include +#include "socal/hps.h" +#include "socal/socal.h" +#include "hwlib.h" +#include "alt_mpu_registers.h" +#include "alt_globaltmr.h" +#include "alt_clock_manager.h" // for getting clock bus frequency + + + +/************************************************************************************************************/ + +/************************************************************************************************************/ +/* The global timer is common to both ARM CPUs and also to the FPGA fabric.There is no good way to know what + effect halting the global timer might have on the other ARM CPU. It was decided that once the global + timer was started, there should not be a way included in this API to halt it. It is possible to achieve + much of the same effect by disabling the global timer comparison functionality instead. The global timer + has hardware that can automatically add the count value to the current value of the global timer when + the timer reaches the comparison value. +*/ +/************************************************************************************************************/ + + + +/************************************************************************************************************* + * alt_globaltmr_is_running() is an internal function, not published in the API. + * It checks and returns the state of the enable bit of the global timer but doesn't check the comparison + * mode bit. +*************************************************************************************************************/ + +bool alt_globaltmr_is_running(void) +{ + return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & GLOBALTMR_ENABLE_BIT; +} + + +/****************************************************************************************/ +/* alt_globaltmr_uninit() uninitializes the global timer modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_uninit(void) +{ + alt_clrbits_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, + GLOBALTMR_COMP_ENABLE_BIT | GLOBALTMR_INT_ENABLE_BIT | + GLOBALTMR_AUTOINC_ENABLE_BIT); + // do NOT clear the global timer enable bit or prescaler setting + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_LO_REG_OFFSET, 0); + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_HI_REG_OFFSET, 0); + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_AUTOINC_REG_OFFSET, 0); + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_INT_STAT_REG_OFFSET, GLOBALTMR_INT_STATUS_BIT); + /* clear any interrupts by writing one to sticky bit */ + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_globaltmr_init() initializes the global timer module */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_init(void) +{ + alt_globaltmr_uninit(); + alt_setbits_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, GLOBALTMR_ENABLE_BIT); + return ALT_E_SUCCESS; +} + +/************************************************************************************************************* + * alt_globaltmr_stop() doesn't actually stop the global timer, instead it stops the virtual representation + * of the global timer as a typical countdown timer. The timer will no longer compare the global timer value + * to the global timer compare value, will not auto-increment the comparator value, and will not set the + * interrupt. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_stop(void) +{ + uint32_t regdata; // value to read & write + + regdata = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET); + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, regdata & ~GLOBALTMR_COMP_ENABLE_BIT); + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_start() sets the comparison mode of the global timer, allowing it to be used as a typical + * countdown timer. If auto-increment mode is enabled, it will operate as a free-running timer. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_start(void) +{ + uint32_t regdata; // value to read & write + + regdata = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET); + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, regdata | (GLOBALTMR_COMP_ENABLE_BIT | GLOBALTMR_ENABLE_BIT)); + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_get() returns the current value of the 64-bit global timer as two unsigned 32-bit quantities. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_get(uint32_t* highword, uint32_t* loword) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; + uint32_t hi, lo, temp; // temporary variables + uint32_t cnt = 3; // Timeout counter, do 3 tries + + if ((highword == NULL) || (loword == NULL)) { ret = ALT_E_BAD_ARG; } + else + { + hi = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_HI_REG_OFFSET); + do { + temp = hi; + lo = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_LO_REG_OFFSET); + hi = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_HI_REG_OFFSET); + } while ((temp != hi) && (cnt--)); // has the high-order word read the same twice yet? + // note that if the first condition is true, cnt is neither tested nor decremented + + if (cnt) { + *highword = hi; + *loword = lo; + ret = ALT_E_SUCCESS; + } + } + return ret; +} + + +/************************************************************************************************************* + * alt_globaltmr_get64() returns the current value of the global timer as an unsigned 64-bit quantity. +*************************************************************************************************************/ + +uint64_t alt_globaltmr_get64(void) +{ + + uint64_t ret = 0; // zero a very unlikely value for this timer + uint32_t hi, lo, temp; // temporary variables + uint32_t cnt = 3; // Timeout counter, do 3 tries + + hi = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_HI_REG_OFFSET); + do { + temp = hi; + lo = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_LO_REG_OFFSET); + hi = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_HI_REG_OFFSET); + } while ((temp != hi) && (cnt--)); // has the high-order word read the same twice yet? + // note that if the first condition is true, cnt is neither tested nor decremented + + if (cnt) + { + ret = (uint64_t) hi; + ret = (ret << (sizeof(uint32_t)*8)) | lo; + } + return ret; +} + + +/************************************************************************************************************* + * alt_globaltmr_counter_get_low32() returns the least-significant 32 bits of the current global timer value. +*************************************************************************************************************/ + +uint32_t alt_globaltmr_counter_get_low32(void) +{ + return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_LO_REG_OFFSET); + +} + + +/************************************************************************************************************* + * alt_globaltmr_counter_get_hi32() returns the most-significant 32 bits of the current global timer value. +*************************************************************************************************************/ + +uint32_t alt_globaltmr_counter_get_hi32(void) +{ + return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CNTR_HI_REG_OFFSET); +} + + +/************************************************************************************************************* + * alt_globaltmr_comp_set() writes the 64-bit comparator register with two 32-bit words. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_comp_set(uint32_t highword, uint32_t loword) +{ + bool was_comping = false; + ALT_STATUS_CODE ret = ALT_E_ERROR; + + if (alt_globaltmr_is_comp_mode()) // necessary to prevent a spurious interrupt + { + was_comping = true; + ret = alt_globaltmr_comp_mode_stop(); + if (ret != ALT_E_SUCCESS) { return ret; } + } + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_LO_REG_OFFSET, loword); + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_HI_REG_OFFSET, highword); + ret = ALT_E_SUCCESS; + + if (was_comping) { ret = alt_globaltmr_comp_mode_start(); } + // If global timer was in comparison mode before, re-enable it before returning + return ret; +} + + +/************************************************************************************************************* + * alt_globaltmr_comp_set64() writes the 64-bit comparator register with the supplied 64-bit value. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_comp_set64(uint64_t compval) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; + bool was_comping = false; + + if (alt_globaltmr_is_comp_mode()) + { + was_comping = true; + ret = alt_globaltmr_comp_mode_stop(); + if (ret != ALT_E_SUCCESS) { return ret; } + } + + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_LO_REG_OFFSET, (uint32_t) (compval & UINT32_MAX)); + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_COMP_HI_REG_OFFSET, + (uint32_t) ((compval >> (sizeof(uint32_t)*8)) & UINT32_MAX)); + ret = ALT_E_SUCCESS; + + if (was_comping) { ret = alt_globaltmr_comp_mode_start(); } + // If global timer was in comparison mode before, re-enable it + return ret; +} + + +/************************************************************************************************************* + * alt_globaltmr_comp_get() returns the 64 bits of the current global timer comparator value via two + * uint32_t pointers. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_comp_get(uint32_t *hiword, uint32_t *loword) +{ + if ((hiword == NULL) || (loword == NULL)) {return ALT_E_ERROR; } + *loword = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_COMP_LO_REG_OFFSET); + *hiword = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_COMP_HI_REG_OFFSET); + /* no need to read these multiple times since the register is not expected to change mid-read */ + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_comp_get64() returns all 64 bits of the current global timer comparator value. +*************************************************************************************************************/ + +uint64_t alt_globaltmr_comp_get64(void) +{ + uint64_t ret; + + ret = ((uint64_t) alt_read_word(GLOBALTMR_BASE + GLOBALTMR_COMP_HI_REG_OFFSET)) << (sizeof(uint32_t)*8); + ret = ret | ((uint64_t) alt_read_word(GLOBALTMR_BASE + GLOBALTMR_COMP_LO_REG_OFFSET)); + return ret; +} + + +/************************************************************************************************************* + * alt_globaltmr_remain_get64() returns a 64-bit quantity that represents the difference between the + * current comparator value and the current global timer value. If the comparator register was updated by + * the autoincrement circuitry (and the global timer has not subsequently crossed over the comparator + * value a second time), this difference will always be expressable in 32 bits. If the user has manually + * set the comparator value, however, this may not be true and more than 32 bits may be required to express + * the difference. +*************************************************************************************************************/ + +#define alt_globaltmr_remain_get64() (alt_globaltmr_comp_get64() - alt_globaltmr_get64()) + + + +/************************************************************************************************************* + * alt_globaltmr_remain_get() returns a 32-bit quantity that represents the difference between the + * current comparator value and the current global timer value. If the comparator register was updated by + * the autoincrement circuitry (and the global timer has not subsequently crossed over the comparator + * value a second time), this difference will always be expressable in 32 bits. If the user has manually + * set the comparator value, however, this may not be true and more than 32 bits may be required to express + * the difference. +*************************************************************************************************************/ + +uint32_t alt_globaltmr_remain_get(void) +{ + return (uint32_t) (alt_globaltmr_comp_get64() - alt_globaltmr_get64()); +} + + +/************************************************************************************************************* + * alt_globaltmr_comp_mode_start() sets the comparison enable bit of the global timer, enabling + * comparison mode operation. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_comp_mode_start(void) +{ + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, + alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) | GLOBALTMR_COMP_ENABLE_BIT); + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_comp_mode_stop() clears the comparison enable bit of the global timer, disabling + * comparison mode operation. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_comp_mode_stop(void) +{ + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, + alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & ~GLOBALTMR_COMP_ENABLE_BIT); + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_is_comp_mode() checks and returns the state of the comparison enable bit of the global timer. +*************************************************************************************************************/ + +bool alt_globaltmr_is_comp_mode(void) +{ + return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & GLOBALTMR_COMP_ENABLE_BIT; +} + + +/************************************************************************************************************* + * alt_globaltmr_prescaler_get() returns the value of the prescaler setting of the global timer, which is one + * less than the actual counter divisor. Valid output = 0-255. +*************************************************************************************************************/ + +uint32_t alt_globaltmr_prescaler_get(void) +{ + return (alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & GLOBALTMR_PS_MASK) >> GLOBALTMR_PS_SHIFT; +} + + +/************************************************************************************************************* + * alt_globaltmr_prescaler_set() sets the prescaler value of the global timer, which is one + * less than the actual counter divisor. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_prescaler_set(uint32_t val) +{ + // It is not defined in the ARM global timer spec if the prescaler can be rewritten while + //the global timer is counting or not. This is how we find out: + uint32_t regdata; + + if (val > UINT8_MAX) return ALT_E_BAD_ARG; + regdata = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & ~GLOBALTMR_PS_MASK; + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, regdata | (val << GLOBALTMR_PS_SHIFT)); + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_autoinc_set() safely writes a value to the auto-increment register of the global timer. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_autoinc_set(uint32_t inc) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; + bool was_comping = false; + + if (alt_globaltmr_is_comp_mode()) + { + was_comping = true; + ret = alt_globaltmr_comp_mode_stop(); + // if timer is currently in comparison mode, disable comparison mode + if (ret != ALT_E_SUCCESS) { return ret; } + } + + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_AUTOINC_REG_OFFSET, inc); + ret = ALT_E_SUCCESS; + + if (was_comping) { ret = alt_globaltmr_comp_mode_start(); } + // If global timer was in comparison mode before, re-enable it + return ret; +} + + +/************************************************************************************************************* + * alt_globaltmr_autoinc_get() returns the value of the auto-increment register of the global timer. +*************************************************************************************************************/ + +uint32_t alt_globaltmr_autoinc_get(void) +{ + return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_AUTOINC_REG_OFFSET); +} + + +/************************************************************************************************************* + * alt_globaltmr_autoinc_mode_start() sets the auto-increment enable bit of the global timer, putting it into + * auto-increment or periodic timer mode. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_autoinc_mode_start(void) +{ + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, + alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) | GLOBALTMR_AUTOINC_ENABLE_BIT); + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_autoinc_mode_stop() clears the auto-increment enable bit of the global timer, putting it into + * one-shot timer mode. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_autoinc_mode_stop(void) +{ + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, + alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & ~GLOBALTMR_AUTOINC_ENABLE_BIT); + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_is_autoinc_mode() checks and returns the state of the auto-increment enable bit of the global + * timer. +*************************************************************************************************************/ + +bool alt_globaltmr_is_autoinc_mode(void) +{ + return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & GLOBALTMR_AUTOINC_ENABLE_BIT; +} + + +/************************************************************************************************************* + * alt_globaltmr_maxcounter_get() returns the maximum possible auto-increment value of the global timer. +*************************************************************************************************************/ + +uint32_t alt_globaltmr_maxcounter_get(void) +{ + return GLOBALTMR_MAX; +} + + +/************************************************************************************************************* + * alt_globaltmr_int_disable() clears the interrupt enable bit of the global timer. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_int_disable(void) +{ + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, + alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & ~GLOBALTMR_INT_ENABLE_BIT); + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_int_enable() sets the interrupt enable bit of the global timer, allowing the timer to throw an + * interrupt when the global timer value is greater than the comparator value. If the global timer has not + * yet been started, it tries to start it first. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_int_enable(void) +{ + if (!alt_globaltmr_is_running()) // Is gbl timer running? + { + if ( alt_globaltmr_start() != ALT_E_SUCCESS) { return ALT_E_ERROR; } + } + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET, + alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) | GLOBALTMR_INT_ENABLE_BIT); + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_int_is_enabled() checks and returns the state of the interrupt bit of the global timer. +*************************************************************************************************************/ + +bool alt_globaltmr_int_is_enabled(void) +{ + return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_CTRL_REG_OFFSET) & GLOBALTMR_INT_ENABLE_BIT; +} + + +/************************************************************************************************************* + * alt_globaltmr_int_clear_pending() clears the status of the interrupt pending bit of the global timer. +*************************************************************************************************************/ + +ALT_STATUS_CODE alt_globaltmr_int_clear_pending(void) +{ + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_INT_STAT_REG_OFFSET, GLOBALTMR_INT_STATUS_BIT); + /* clear interrupt sticky bit by writing one to it */ + return ALT_E_SUCCESS; +} + + +/************************************************************************************************************* + * alt_globaltmr_int_is_pending() checks and returns the status of the interrupt pending bit of the global + * timer. +*************************************************************************************************************/ + +bool alt_globaltmr_int_is_pending(void) +{ + return alt_read_word(GLOBALTMR_BASE + GLOBALTMR_INT_STAT_REG_OFFSET) & GLOBALTMR_INT_STATUS_BIT; +} + + +/************************************************************************************************************* + * alt_globaltmr_int_if_pending_clear() checks and returns the status of the interrupt pending bit of the global + * timer. If the interrupt pending bit is set, this function also clears it. +*************************************************************************************************************/ + +bool alt_globaltmr_int_if_pending_clear(void) +{ + bool ret; + + ret = alt_read_word(GLOBALTMR_BASE + GLOBALTMR_INT_STAT_REG_OFFSET) & GLOBALTMR_INT_STATUS_BIT; + if (ret) + { + alt_write_word(GLOBALTMR_BASE + GLOBALTMR_INT_STAT_REG_OFFSET, GLOBALTMR_INT_STATUS_BIT); + } //clear int by writing to sticky bit + + return ret; +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_i2c.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_i2c.c new file mode 100644 index 000000000..028eaf260 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_i2c.c @@ -0,0 +1,2004 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_i2c.h" +#include "alt_reset_manager.h" +#include + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + +///// + +// Timeout for reset manager +#define ALT_I2C_RESET_TMO_INIT 8192 +// Timeout for disable device +#define ALT_I2C_MAX_T_POLL_COUNT 8192 +// Timeout for waiting interrupt +#define ALT_I2C_TMO_WAITER 2500000 + +// Min frequency during standard speed +#define ALT_I2C_SS_MIN_SPEED 8000 +// Max frequency during standard speed +#define ALT_I2C_SS_MAX_SPEED 100000 +// Min frequency during fast speed +#define ALT_I2C_FS_MIN_SPEED 100000 +// Max frequency during fast speed +#define ALT_I2C_FS_MAX_SPEED 400000 +// Default spike suppression limit during standard speed +#define ALT_I2C_SS_DEFAULT_SPKLEN 11 +// Default spike suppression limit during fast speed +#define ALT_I2C_FS_DEFAULT_SPKLEN 4 + +// Diff between SCL LCNT and SCL HCNT +#define ALT_I2C_DIFF_LCNT_HCNT 70 + +// Reserved address from 0x00 to 0x07 +#define ALT_I2C_SLV_RESERVE_ADDR_S_1 0x00 +#define ALT_I2C_SLV_RESERVE_ADDR_F_1 0x07 +// Reserved address from 0x78 to 0x7F +#define ALT_I2C_SLV_RESERVE_ADDR_S_2 0x78 +#define ALT_I2C_SLV_RESERVE_ADDR_F_2 0x7F + +static ALT_STATUS_CODE alt_i2c_is_enabled_helper(ALT_I2C_DEV_t * i2c_dev); + +// +// Check whether i2c space is correct. +// +static ALT_STATUS_CODE alt_i2c_checking(ALT_I2C_DEV_t * i2c_dev) +{ + if ( (i2c_dev->location != (void *)ALT_I2C_I2C0) + && (i2c_dev->location != (void *)ALT_I2C_I2C1) + && (i2c_dev->location != (void *)ALT_I2C_I2C2) + && (i2c_dev->location != (void *)ALT_I2C_I2C3)) + { + // Incorrect device + return ALT_E_FALSE; + } + + // Reset i2c module + return ALT_E_TRUE; +} + +static ALT_STATUS_CODE alt_i2c_rstmgr_set(ALT_I2C_DEV_t * i2c_dev) +{ + uint32_t rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + + // Assert the appropriate I2C module reset signal via the Reset Manager Peripheral Reset register. + switch ((ALT_I2C_CTLR_t)i2c_dev->location) + { + case ALT_I2C_I2C0: + rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + break; + case ALT_I2C_I2C1: + rst_mask = ALT_RSTMGR_PERMODRST_I2C1_SET_MSK; + break; + case ALT_I2C_I2C2: + rst_mask = ALT_RSTMGR_PERMODRST_I2C2_SET_MSK; + break; + case ALT_I2C_I2C3: + rst_mask = ALT_RSTMGR_PERMODRST_I2C3_SET_MSK; + break; + default: + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + return ALT_E_SUCCESS; +} + +// +// Reset i2c module by reset manager +// +static ALT_STATUS_CODE alt_i2c_rstmgr_strobe(ALT_I2C_DEV_t * i2c_dev) +{ + uint32_t rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + + // Assert the appropriate I2C module reset signal via the Reset Manager Peripheral Reset register. + switch ((ALT_I2C_CTLR_t)i2c_dev->location) + { + case ALT_I2C_I2C0: + rst_mask = ALT_RSTMGR_PERMODRST_I2C0_SET_MSK; + break; + case ALT_I2C_I2C1: + rst_mask = ALT_RSTMGR_PERMODRST_I2C1_SET_MSK; + break; + case ALT_I2C_I2C2: + rst_mask = ALT_RSTMGR_PERMODRST_I2C2_SET_MSK; + break; + case ALT_I2C_I2C3: + rst_mask = ALT_RSTMGR_PERMODRST_I2C3_SET_MSK; + break; + default: + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + volatile uint32_t timeout = ALT_I2C_RESET_TMO_INIT; + + // Wait while i2c modure is reseting + while (--timeout) + ; + + // Deassert the appropriate I2C module reset signal via the Reset Manager Peripheral Reset register. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + return ALT_E_SUCCESS; +} + +// +// Initialize the specified I2C controller instance for use and return a device +// handle referencing it. +// +ALT_STATUS_CODE alt_i2c_init(const ALT_I2C_CTLR_t i2c, + ALT_I2C_DEV_t * i2c_dev) +{ + // Save i2c start address to the instance + i2c_dev->location = (void *)i2c; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_clk_is_enabled(ALT_CLK_L4_SP) != ALT_E_TRUE) + { + return ALT_E_BAD_CLK; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_clk_freq_get(ALT_CLK_L4_SP, &i2c_dev->clock_freq); + } + + // Reset i2c module + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_reset(i2c_dev); + } + + return status; +} + +// +// Reset i2c module +// +ALT_STATUS_CODE alt_i2c_reset(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + // Reset i2c module by reset manager + alt_i2c_rstmgr_strobe(i2c_dev); + + // Set optimal parameters for all i2c devices on the bus + ALT_I2C_MASTER_CONFIG_t cfg; + cfg.addr_mode = ALT_I2C_ADDR_MODE_7_BIT; + cfg.speed_mode = ALT_I2C_SPEED_STANDARD; + cfg.fs_spklen = ALT_I2C_SS_DEFAULT_SPKLEN; + cfg.restart_enable = ALT_E_TRUE; + cfg.ss_scl_lcnt = cfg.fs_scl_lcnt = 0x2FB; + cfg.ss_scl_hcnt = cfg.fs_scl_hcnt = 0x341; + + alt_i2c_master_config_set(i2c_dev, &cfg); + + // Active master mode + alt_i2c_op_mode_set(i2c_dev, ALT_I2C_MODE_MASTER); + + // Reset the last target address cache. + i2c_dev->last_target = 0xffffffff; + + // Clear interrupts mask and clear interrupt status. + // Interrupts are unmasked by default. + alt_i2c_int_disable(i2c_dev, ALT_I2C_STATUS_INT_ALL); + alt_i2c_int_clear(i2c_dev, ALT_I2C_STATUS_INT_ALL); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Uninitialize the I2C controller referenced by the i2c_dev handle. +// +ALT_STATUS_CODE alt_i2c_uninit(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Disable i2c controller + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_disable(i2c_dev); + } + + // Reset i2c module by reset manager + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_rstmgr_set(i2c_dev); + } + + return status; +} + +// +// Enables the I2C controller. +// +ALT_STATUS_CODE alt_i2c_enable(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // Enable DMA by default. + alt_write_word(ALT_I2C_DMA_CR_ADDR(i2c_dev->location), + ALT_I2C_DMA_CR_TDMAE_SET_MSK | ALT_I2C_DMA_CR_RDMAE_SET_MSK); + + alt_setbits_word(ALT_I2C_EN_ADDR(i2c_dev->location), ALT_I2C_EN_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +// +// Disables the I2C controller +// +ALT_STATUS_CODE alt_i2c_disable(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // If i2c controller is enabled, return with sucess + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_SUCCESS; + } + + // Else clear enable bit of i2c_enable register + alt_clrbits_word(ALT_I2C_EN_ADDR(i2c_dev->location), ALT_I2C_EN_EN_SET_MSK); + + uint32_t timeout = ALT_I2C_MAX_T_POLL_COUNT; + + // Wait to complete all transfer operations or timeout + while (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE) + { + // If controller still are active, return timeout error + if (--timeout == 0) + { + return ALT_E_TMO; + } + } + + // Clear interrupt status + alt_i2c_int_clear(i2c_dev, ALT_I2C_STATUS_INT_ALL); + + return ALT_E_SUCCESS; +} + +// +// Check whether i2c controller is enable +// +static ALT_STATUS_CODE alt_i2c_is_enabled_helper(ALT_I2C_DEV_t * i2c_dev) +{ + if (ALT_I2C_EN_STAT_IC_EN_GET(alt_read_word(ALT_I2C_EN_STAT_ADDR(i2c_dev->location)))) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +ALT_STATUS_CODE alt_i2c_is_enabled(ALT_I2C_DEV_t * i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + return alt_i2c_is_enabled_helper(i2c_dev); +} + +// +// Get config parameters from appropriate registers for master mode. +// +ALT_STATUS_CODE alt_i2c_master_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register = alt_read_word(ALT_I2C_CON_ADDR(i2c_dev->location)); + uint32_t tar_register = alt_read_word(ALT_I2C_TAR_ADDR(i2c_dev->location)); + uint32_t spkl_register = alt_read_word(ALT_I2C_FS_SPKLEN_ADDR(i2c_dev->location)); + + cfg->speed_mode = (ALT_I2C_SPEED_t)ALT_I2C_CON_SPEED_GET(cfg_register); + cfg->fs_spklen = ALT_I2C_FS_SPKLEN_SPKLEN_GET(spkl_register); + cfg->restart_enable = ALT_I2C_CON_IC_RESTART_EN_GET(cfg_register); + cfg->addr_mode = (ALT_I2C_ADDR_MODE_t)ALT_I2C_TAR_IC_10BITADDR_MST_GET(tar_register); + + cfg->ss_scl_lcnt = alt_read_word(ALT_I2C_SS_SCL_LCNT_ADDR(i2c_dev->location)); + cfg->ss_scl_hcnt = alt_read_word(ALT_I2C_SS_SCL_HCNT_ADDR(i2c_dev->location)); + cfg->fs_scl_lcnt = alt_read_word(ALT_I2C_FS_SCL_LCNT_ADDR(i2c_dev->location)); + cfg->fs_scl_hcnt = alt_read_word(ALT_I2C_FS_SCL_HCNT_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +// +// Set config parameters to appropriate registers for master mode. +// +ALT_STATUS_CODE alt_i2c_master_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->speed_mode != ALT_I2C_SPEED_STANDARD) + && (cfg->speed_mode != ALT_I2C_SPEED_FAST)) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->addr_mode != ALT_I2C_ADDR_MODE_7_BIT) + && (cfg->addr_mode != ALT_I2C_ADDR_MODE_10_BIT)) + { + return ALT_E_ARG_RANGE; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + // Set config parameters to appropriate registers + + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_SPEED_SET_MSK | ALT_I2C_CON_IC_RESTART_EN_SET_MSK, + ALT_I2C_CON_SPEED_SET(cfg->speed_mode) | ALT_I2C_CON_IC_RESTART_EN_SET(cfg->restart_enable)); + + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK, + ALT_I2C_TAR_IC_10BITADDR_MST_SET(cfg->addr_mode)); + + alt_replbits_word(ALT_I2C_FS_SPKLEN_ADDR(i2c_dev->location), + ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK, + ALT_I2C_FS_SPKLEN_SPKLEN_SET(cfg->fs_spklen)); + + alt_replbits_word(ALT_I2C_SS_SCL_LCNT_ADDR(i2c_dev->location), + ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK, + ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(cfg->ss_scl_lcnt)); + alt_replbits_word(ALT_I2C_SS_SCL_HCNT_ADDR(i2c_dev->location), + ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK, + ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(cfg->ss_scl_hcnt)); + alt_replbits_word(ALT_I2C_FS_SCL_LCNT_ADDR(i2c_dev->location), + ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK, + ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(cfg->fs_scl_lcnt)); + alt_replbits_word(ALT_I2C_FS_SCL_HCNT_ADDR(i2c_dev->location), + ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK, + ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(cfg->fs_scl_hcnt)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Return bus speed by configuration of i2c controller for master mode. +// +ALT_STATUS_CODE alt_i2c_master_config_speed_get(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t * speed_in_hz) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t scl_lcnt = (cfg->speed_mode == ALT_I2C_SPEED_STANDARD) ? cfg->ss_scl_lcnt : cfg->fs_scl_lcnt; + + if (scl_lcnt == 0) + { + return ALT_E_BAD_ARG; + } + + *speed_in_hz = i2c_dev->clock_freq / (scl_lcnt << 1); + + return ALT_E_SUCCESS; +} + +// +// Fill struct with configuration of i2c controller for master mode by bus speed +// +ALT_STATUS_CODE alt_i2c_master_config_speed_set(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t speed_in_hz) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // If speed is not standard or fast return range error + if ((speed_in_hz > ALT_I2C_FS_MAX_SPEED) || (speed_in_hz < ALT_I2C_SS_MIN_SPEED)) + { + return ALT_E_ARG_RANGE; + } + + if (speed_in_hz > ALT_I2C_FS_MIN_SPEED) + { + cfg->speed_mode = ALT_I2C_SPEED_FAST; + cfg->fs_spklen = ALT_I2C_FS_DEFAULT_SPKLEN; + } + else + { + cfg->speed_mode = ALT_I2C_SPEED_STANDARD; + cfg->fs_spklen = ALT_I2C_SS_DEFAULT_SPKLEN; + } + + // = / 2 * + uint32_t scl_lcnt = i2c_dev->clock_freq / (speed_in_hz << 1); + + cfg->ss_scl_lcnt = cfg->fs_scl_lcnt = scl_lcnt; + // hcount = + 70 + cfg->ss_scl_hcnt = cfg->fs_scl_hcnt = scl_lcnt - ALT_I2C_DIFF_LCNT_HCNT; + + // lcount = / 2 * + + return ALT_E_SUCCESS; +} + +// +// Get config parameters from appropriate registers for slave mode. +// +ALT_STATUS_CODE alt_i2c_slave_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_SLAVE_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register = alt_read_word(ALT_I2C_CON_ADDR(i2c_dev->location)); + uint32_t sar_register = alt_read_word(ALT_I2C_SAR_ADDR(i2c_dev->location)); + uint32_t nack_register = alt_read_word(ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(i2c_dev->location)); + + cfg->addr_mode = (ALT_I2C_ADDR_MODE_t)ALT_I2C_CON_IC_10BITADDR_SLV_GET(cfg_register); + cfg->addr = ALT_I2C_SAR_IC_SAR_GET(sar_register); + cfg->nack_enable = ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(nack_register); + + return ALT_E_SUCCESS; +} + +// +// Set config parameters to appropriate registers for slave mode. +// +ALT_STATUS_CODE alt_i2c_slave_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_SLAVE_CONFIG_t* cfg) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->addr_mode != ALT_I2C_ADDR_MODE_7_BIT) + && (cfg->addr_mode != ALT_I2C_ADDR_MODE_10_BIT)) + { + return ALT_E_BAD_ARG; + } + + if ( (cfg->addr > ALT_I2C_SAR_IC_SAR_SET_MSK) + || (cfg->addr < ALT_I2C_SLV_RESERVE_ADDR_F_1) + || ((cfg->addr > ALT_I2C_SLV_RESERVE_ADDR_S_2) && (cfg->addr < ALT_I2C_SLV_RESERVE_ADDR_F_2)) + ) + { + return ALT_E_ARG_RANGE; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK, + ALT_I2C_CON_IC_10BITADDR_SLV_SET(cfg->addr_mode)); + + alt_replbits_word(ALT_I2C_SAR_ADDR(i2c_dev->location), + ALT_I2C_SAR_IC_SAR_SET_MSK, + ALT_I2C_SAR_IC_SAR_SET(cfg->addr)); + alt_replbits_word(ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(i2c_dev->location), + ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK, + ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(cfg->nack_enable)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Get hold time (use during slave mode) +// +ALT_STATUS_CODE alt_i2c_sda_hold_time_get(ALT_I2C_DEV_t *i2c_dev, + uint16_t *hold_time) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t sda_register = alt_read_word(ALT_I2C_SDA_HOLD_ADDR(i2c_dev->location)); + *hold_time = ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(sda_register); + + return ALT_E_SUCCESS; +} + +// +// Set hold time (use during slave mode) +// +ALT_STATUS_CODE alt_i2c_sda_hold_time_set(ALT_I2C_DEV_t *i2c_dev, + const uint16_t hold_time) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_SDA_HOLD_ADDR(i2c_dev->location), + ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK, + ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(hold_time)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Gets the current operational mode of the I2C controller. +// +ALT_STATUS_CODE alt_i2c_op_mode_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MODE_t* mode) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register = alt_read_word(ALT_I2C_CON_ADDR(i2c_dev->location)); + uint32_t mst_mod_stat = ALT_I2C_CON_MST_MOD_GET(cfg_register); + uint32_t slv_mod_stat = ALT_I2C_CON_IC_SLV_DIS_GET(cfg_register); + + // Return error if master and slave modes enable or disable at the same time + if ( (mst_mod_stat == ALT_I2C_CON_MST_MOD_E_EN && slv_mod_stat == ALT_I2C_CON_IC_SLV_DIS_E_EN) + || (mst_mod_stat == ALT_I2C_CON_MST_MOD_E_DIS && slv_mod_stat == ALT_I2C_CON_IC_SLV_DIS_E_DIS)) + { + return ALT_E_ERROR; + } + + *mode = (ALT_I2C_MODE_t)mst_mod_stat; + + return ALT_E_SUCCESS; +} + +// +// Sets the operational mode of the I2C controller. +// +ALT_STATUS_CODE alt_i2c_op_mode_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MODE_t mode) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( (mode != ALT_I2C_MODE_MASTER) + && (mode != ALT_I2C_MODE_SLAVE)) + { + return ALT_E_ARG_RANGE; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + if (mode == ALT_I2C_MODE_MASTER) + { + // Enable master, disable slave + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_IC_SLV_DIS_SET_MSK | ALT_I2C_CON_MST_MOD_SET_MSK, + ALT_I2C_CON_IC_SLV_DIS_SET(ALT_I2C_CON_IC_SLV_DIS_E_DIS) | ALT_I2C_CON_MST_MOD_SET(ALT_I2C_CON_MST_MOD_E_EN)); + } + else if (mode == ALT_I2C_MODE_SLAVE) + { + // Enable slave, disable master + alt_replbits_word(ALT_I2C_CON_ADDR(i2c_dev->location), + ALT_I2C_CON_IC_SLV_DIS_SET_MSK | ALT_I2C_CON_MST_MOD_SET_MSK, + ALT_I2C_CON_IC_SLV_DIS_SET(ALT_I2C_CON_IC_SLV_DIS_E_EN) | ALT_I2C_CON_MST_MOD_SET(ALT_I2C_CON_MST_MOD_E_DIS)); + } + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Returns ALT_E_TRUE if the I2C controller is busy +// +ALT_STATUS_CODE alt_i2c_is_busy(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if ( ALT_I2C_STAT_ACTIVITY_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location)))) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// This function reads a single data byte from the receive FIFO. +// +ALT_STATUS_CODE alt_i2c_read(ALT_I2C_DEV_t *i2c_dev, uint8_t *value) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + *value = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + + return ALT_E_SUCCESS; +} + +// +// This function writes a single data byte to the transmit FIFO. +// +ALT_STATUS_CODE alt_i2c_write(ALT_I2C_DEV_t *i2c_dev, const uint8_t value) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(value)); + + return ALT_E_SUCCESS; +} + +// +// This function acts in the role of a slave-receiver by receiving a single data +// byte from the I2C bus in response to a write command from the master. +// +ALT_STATUS_CODE alt_i2c_slave_receive(ALT_I2C_DEV_t * i2c_dev, + uint8_t * data) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + // alt_i2c_read(). + *data = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + + return ALT_E_SUCCESS; +} + +// +// This function acts in the role of a slave-transmitter by transmitting a single +// data byte to the I2C bus in response to a read request from the master. +// +ALT_STATUS_CODE alt_i2c_slave_transmit(ALT_I2C_DEV_t *i2c_dev, + const uint8_t data) +{ + // Send bulk of data with one value + return alt_i2c_slave_bulk_transmit(i2c_dev, &data, 1); +} + +// +// This function acts in the role of a slave-transmitter by transmitting data in +// bulk to the I2C bus in response to a series of read requests from a master. +// +ALT_STATUS_CODE alt_i2c_slave_bulk_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + const char * buffer = data; + for (size_t i = 0; i < size; ++i) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(*buffer) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + + ++buffer; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_master_target_get(ALT_I2C_DEV_t * i2c_dev, uint32_t * target_addr) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *target_addr = i2c_dev->last_target; + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_master_target_set(ALT_I2C_DEV_t * i2c_dev, uint32_t target_addr) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Wait until the TX FIFO flushes. This is needed because TAR can only be + // updated under specific conditions. + + if (target_addr != i2c_dev->last_target) + { + uint32_t timeout = 10000; + + while (alt_i2c_tx_fifo_is_empty(i2c_dev) == ALT_E_FALSE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + + // Update target address + if (status == ALT_E_SUCCESS) + { + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_IC_TAR_SET_MSK, + ALT_I2C_TAR_IC_TAR_SET(target_addr)); + + i2c_dev->last_target = target_addr; + } + } + + return status; +} + +// +// Write bulk of data or read requests to tx fifo +// +static ALT_STATUS_CODE alt_i2c_master_transmit_helper(ALT_I2C_DEV_t * i2c_dev, + const uint8_t * buffer, + size_t size, + bool issue_restart, + bool issue_stop) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // If the rested size is 1, the restart and stop may need to be sent in the + // same frame. + if (size == 1) + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_issue_write(i2c_dev, + *buffer, + issue_restart, + issue_stop); + + ++buffer; + --size; + } + } + else + { + // First byte + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_issue_write(i2c_dev, + *buffer, + issue_restart, + false); + + ++buffer; + --size; + } + + ///// + + // Middle byte(s) + + if (status == ALT_E_SUCCESS) + { + uint32_t timeout = size * 10000; + + while (size > 1) + { + uint32_t level = 0; + status = alt_i2c_tx_fifo_level_get(i2c_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t space = ALT_I2C_TX_FIFO_NUM_ENTRIES - level; + if (space == 0) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + + continue; + } + + // Subtract 1 because the last byte may need to issue_stop + space = MIN(space, size - 1); + + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(*buffer) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + + ++buffer; + } + + size -= space; + } + } + + ///// + + // Last byte + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_issue_write(i2c_dev, + *buffer, + false, + issue_stop); + + ++buffer; + --size; + } + } + + return status; +} + +// +// This function acts in the role of a master-transmitter by issuing a write +// command and transmitting data to the I2C bus. +// +ALT_STATUS_CODE alt_i2c_master_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_transmit_helper(i2c_dev, + data, + size, + issue_restart, + issue_stop); + } + + // Need reset for set i2c bus in idle state + if (status == ALT_E_TMO) + { + alt_i2c_reset(i2c_dev); + } + + return status; +} + +ALT_STATUS_CODE alt_i2c_master_receive_helper(ALT_I2C_DEV_t *i2c_dev, + uint8_t * buffer, + size_t size, + bool issue_restart, + bool issue_stop) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t issue_left = size; + uint32_t data_left = size; + + uint32_t timeout = size * 10000; + + // Wait for space in the TX FIFO to send the first read request. + // This is needed because the issue restart need to be set. + + if (issue_restart == true) + { + if (status == ALT_E_SUCCESS) + { + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + } + + // Now send the first request. + + if (status == ALT_E_SUCCESS) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + --issue_left; + } + } + + // For the rest of the data ... + + while (data_left > 0) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + // Top up the TX FIFO with read issues + // Special consideration must be made for the last read issue, as it may be necessary to "issue_stop". + + if (issue_left > 0) + { + uint32_t level = 0; + status = alt_i2c_tx_fifo_level_get(i2c_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t space = ALT_I2C_TX_FIFO_NUM_ENTRIES - level; + + if (issue_left == 1) + { + if (space > 0) + { + space = 1; + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + } + } + else + { + // Send up to issue_left - 1, as the last issue has special considerations. + space = MIN(issue_left - 1, space); + + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(false) + | ALT_I2C_DATA_CMD_RESTART_SET(false)); + } + } + + issue_left -= space; + } + + // Read out the resulting received data as they come in. + + if (data_left > 0) + { + uint32_t level = 0; + status = alt_i2c_rx_fifo_level_get(i2c_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + if (level == 0) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + + level = MIN(data_left, level); + + for (uint32_t i = 0; i < level; ++i) + { + // alt_i2c_read(i2c_dev, &value); + *buffer = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + ++buffer; + } + + data_left -= level; + } + } + + + return status; +} + +// +// This function acts in the role of a master-receiver by receiving one or more +// data bytes transmitted from a slave in response to read requests issued from +// this master. +// +ALT_STATUS_CODE alt_i2c_master_receive(ALT_I2C_DEV_t *i2c_dev, + void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // This I2C controller requires that a read issue be performed for each byte requested. + // Read issue takes space in the TX FIFO, which may asynchronously handling a previous request. + + if (size == 1) + { + uint32_t timeout = 10000; + + // Wait for space in the TX FIFO to send the read request. + + if (status == ALT_E_SUCCESS) + { + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + } + + // Issue the read request in the TX FIFO. + + if (status == ALT_E_SUCCESS) + { + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + } + + // Wait for data to become available in the RX FIFO. + + if (status == ALT_E_SUCCESS) + { + while (alt_i2c_rx_fifo_is_empty(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + } + + // Read the RX FIFO. + + if (status == ALT_E_SUCCESS) + { + uint8_t * buffer = data; + *buffer = (uint8_t)(ALT_I2C_DATA_CMD_DAT_GET(alt_read_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location)))); + } + } + else if (size <= 64) + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + data, + size, + issue_restart, + issue_stop); + } + } + else + { + uint8_t * buffer = data; + size_t size_left = size; + + // Send the first ALT_I2C_RX_FIFO_NUM_ENTRIES items + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + buffer, + ALT_I2C_RX_FIFO_NUM_ENTRIES, + issue_restart, + false); + } + + buffer += ALT_I2C_RX_FIFO_NUM_ENTRIES; + size_left -= ALT_I2C_RX_FIFO_NUM_ENTRIES; + + while (size_left > 0) + { + if (size_left > ALT_I2C_RX_FIFO_NUM_ENTRIES) + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + buffer, + ALT_I2C_RX_FIFO_NUM_ENTRIES, + false, + false); + } + + buffer += ALT_I2C_RX_FIFO_NUM_ENTRIES; + size_left -= ALT_I2C_RX_FIFO_NUM_ENTRIES; + } + else + { + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_receive_helper(i2c_dev, + buffer, + size_left, + false, + issue_stop); + } + + size_left = 0; + } + + if (status != ALT_E_SUCCESS) + { + break; + } + } + } + + // Need reset for set i2c bus in idle state + if (status == ALT_E_TMO) + { + alt_i2c_reset(i2c_dev); + } + + return status; +} + +// +// This function causes the I2C controller master to send data to the bus. +// +ALT_STATUS_CODE alt_i2c_issue_write(ALT_I2C_DEV_t *i2c_dev, + const uint8_t value, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + // Wait until there is a FIFO spot + uint32_t timeout = 10000; + + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + return ALT_E_TMO; + } + } + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_DAT_SET(value) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + return ALT_E_SUCCESS; +} + +// +// This function causes the I2C controller master to issue a READ request on the bus. +// +ALT_STATUS_CODE alt_i2c_issue_read(ALT_I2C_DEV_t *i2c_dev, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + // Wait until there is a FIFO spot + uint32_t timeout = 10000; + + while (alt_i2c_tx_fifo_is_full(i2c_dev) == ALT_E_TRUE) + { + if (--timeout == 0) + { + return ALT_E_TMO; + } + } + + alt_write_word(ALT_I2C_DATA_CMD_ADDR(i2c_dev->location), + ALT_I2C_DATA_CMD_CMD_SET(ALT_I2C_DATA_CMD_CMD_E_RD) + | ALT_I2C_DATA_CMD_STOP_SET(issue_stop) + | ALT_I2C_DATA_CMD_RESTART_SET(issue_restart)); + + return ALT_E_SUCCESS; +} + +// +// This function acts in the role of a master-transmitter by issuing a general +// call command to all devices connected to the I2C bus. +// +ALT_STATUS_CODE alt_i2c_master_general_call(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_target_set(i2c_dev, 0); + } + + // General call is a transmit in master mode (target address are not used during it) + if (status == ALT_E_SUCCESS) + { + status = alt_i2c_master_transmit(i2c_dev, data, size, issue_restart, issue_stop); + } + + return status; +} + +///// + +ALT_STATUS_CODE alt_i2c_general_call_ack_disable(ALT_I2C_DEV_t *i2c_dev) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_SPECIAL_SET_MSK | ALT_I2C_TAR_GC_OR_START_SET_MSK, + ALT_I2C_TAR_SPECIAL_SET(ALT_I2C_TAR_SPECIAL_E_STARTBYTE) | ALT_I2C_TAR_GC_OR_START_SET(ALT_I2C_TAR_GC_OR_START_E_STARTBYTE)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Enables the I2C controller to respond with an ACK when it receives a General +// Call address. +// +ALT_STATUS_CODE alt_i2c_general_call_ack_enable(ALT_I2C_DEV_t *i2c_dev) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_TAR_ADDR(i2c_dev->location), + ALT_I2C_TAR_SPECIAL_SET_MSK | ALT_I2C_TAR_GC_OR_START_SET_MSK, + ALT_I2C_TAR_SPECIAL_SET(ALT_I2C_TAR_SPECIAL_E_GENCALL) | ALT_I2C_TAR_GC_OR_START_SET(ALT_I2C_TAR_GC_OR_START_E_GENCALL)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Returns ALT_E_TRUE if the I2C controller is enabled to respond to General Call +// addresses. +// +ALT_STATUS_CODE alt_i2c_general_call_ack_is_enabled(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + uint32_t tar_register = alt_read_word(ALT_I2C_TAR_ADDR(i2c_dev->location)); + + if ( (ALT_I2C_TAR_SPECIAL_GET(tar_register) == ALT_I2C_TAR_SPECIAL_E_GENCALL) + && (ALT_I2C_TAR_GC_OR_START_GET(tar_register) == ALT_I2C_TAR_GC_OR_START_E_GENCALL) + ) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns the current I2C controller interrupt status conditions. +// +ALT_STATUS_CODE alt_i2c_int_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *status = alt_read_word(ALT_I2C_INTR_STAT_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +// +// Returns the I2C controller raw interrupt status conditions irrespective of +// the interrupt status condition enablement state. +// +ALT_STATUS_CODE alt_i2c_int_raw_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *status = alt_read_word(ALT_I2C_RAW_INTR_STAT_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +// +// Clears the specified I2C controller interrupt status conditions identified +// in the mask. +// +ALT_STATUS_CODE alt_i2c_int_clear(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (mask == ALT_I2C_STATUS_INT_ALL) + { + alt_read_word(ALT_I2C_CLR_INTR_ADDR(i2c_dev->location)); + return ALT_E_SUCCESS; + } + + // For different status clear different register + + if (mask & ALT_I2C_STATUS_RX_UNDER) + { + alt_read_word(ALT_I2C_CLR_RX_UNDER_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_RX_OVER) + { + alt_read_word(ALT_I2C_CLR_RX_OVER_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_TX_OVER) + { + alt_read_word(ALT_I2C_CLR_TX_OVER_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_RD_REQ) + { + alt_read_word(ALT_I2C_CLR_RD_REQ_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_TX_ABORT) + { + alt_read_word(ALT_I2C_CLR_TX_ABRT_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_RX_DONE) + { + alt_read_word(ALT_I2C_CLR_RX_DONE_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_ACTIVITY) + { + alt_read_word(ALT_I2C_CLR_ACTIVITY_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_STOP_DET) + { + alt_read_word(ALT_I2C_CLR_STOP_DET_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_START_DET) + { + alt_read_word(ALT_I2C_CLR_START_DET_ADDR(i2c_dev->location)); + } + if (mask & ALT_I2C_STATUS_INT_CALL) + { + alt_read_word(ALT_I2C_CLR_GEN_CALL_ADDR(i2c_dev->location)); + } + + return ALT_E_SUCCESS; +} + +// +// Disable the specified I2C controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_i2c_int_disable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + alt_clrbits_word(ALT_I2C_INTR_MSK_ADDR(i2c_dev->location), mask); + + return ALT_E_SUCCESS; +} + +// +// Enable the specified I2C controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_i2c_int_enable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_I2C_INTR_MSK_ADDR(i2c_dev->location), mask); + + return ALT_E_SUCCESS; +} + +///// + +// +// Gets the cause of I2C transmission abort. +// +ALT_STATUS_CODE alt_i2c_tx_abort_cause_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_TX_ABORT_CAUSE_t *cause) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *cause = (ALT_I2C_TX_ABORT_CAUSE_t)alt_read_word(ALT_I2C_TX_ABRT_SRC_ADDR(i2c_dev->location)); + + return ALT_E_SUCCESS; +} + +///// + +// +// Returns ALT_E_TRUE when the receive FIFO is empty. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_RFNE_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_RFNE_E_EMPTY) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns ALT_E_TRUE when the receive FIFO is completely full. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_RFF_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_RFF_E_FULL) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns the number of valid entries in the receive FIFO. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *num_entries = ALT_I2C_RXFLR_RXFLR_GET(alt_read_word(ALT_I2C_RXFLR_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Gets the current receive FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_RX_TL_RX_TL_GET(alt_read_word(ALT_I2C_RX_TL_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Sets the current receive FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_RX_TL_ADDR(i2c_dev->location), + ALT_I2C_RX_TL_RX_TL_SET_MSK, + ALT_I2C_RX_TL_RX_TL_SET(threshold)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +// +// Returns ALT_E_TRUE when the transmit FIFO is empty. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_TFE_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_TFE_E_EMPTY) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns ALT_E_TRUE when the transmit FIFO is completely full. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (ALT_I2C_STAT_TFNF_GET(alt_read_word(ALT_I2C_STAT_ADDR(i2c_dev->location))) == ALT_I2C_STAT_TFNF_E_FULL) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns the number of valid entries in the transmit FIFO. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *num_entries = ALT_I2C_TXFLR_TXFLR_GET(alt_read_word(ALT_I2C_TXFLR_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Sets the current transmit FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_TX_TL_TX_TL_GET(alt_read_word(ALT_I2C_TX_TL_ADDR(i2c_dev->location))); + + return ALT_E_SUCCESS; +} + +// +// Sets the current transmit FIFO threshold level value. +// +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + bool already_enabled = (alt_i2c_is_enabled_helper(i2c_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_i2c_disable(i2c_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_I2C_TX_TL_ADDR(i2c_dev->location), + ALT_I2C_TX_TL_TX_TL_SET_MSK, + ALT_I2C_TX_TL_TX_TL_SET(threshold)); + + if (already_enabled) + { + // Re-enable controller + status = alt_i2c_enable(i2c_dev); + } + + return status; +} + +///// + +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_DMA_RDLR_DMARDL_GET(alt_read_word(ALT_I2C_DMA_RDLR_ADDR(i2c_dev->location))); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (threshold > ALT_I2C_DMA_RDLR_DMARDL_SET_MSK) + { + return ALT_E_ARG_RANGE; + } + + alt_write_word(ALT_I2C_DMA_RDLR_ADDR(i2c_dev->location), threshold); + return ALT_E_SUCCESS; + +} + +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + *threshold = ALT_I2C_DMA_TDLR_DMATDL_GET(alt_read_word(ALT_I2C_DMA_TDLR_ADDR(i2c_dev->location))); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold) +{ + if (alt_i2c_checking(i2c_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (threshold > ALT_I2C_DMA_TDLR_DMATDL_SET_MSK) + { + return ALT_E_ARG_RANGE; + } + + alt_write_word(ALT_I2C_DMA_TDLR_ADDR(i2c_dev->location), threshold); + return ALT_E_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_interrupt.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_interrupt.c new file mode 100644 index 000000000..a998f97fb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_interrupt.c @@ -0,0 +1,1228 @@ +/****************************************************************************** +* +* alt_interrupt.c - API for the Altera SoC FPGA interrupts +* +******************************************************************************/ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "alt_interrupt.h" +#include "socal/socal.h" +#include "hwlib.h" + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, __VA_ARGS__) + +///// + +// Interrupt attribute(s) flags + +typedef enum INT_FLAG_e +{ + INT_FLAG_IMPLEMENTED = 0x01 +} +INT_FLAG_t; + +static uint8_t alt_int_flag[ALT_INT_PROVISION_INT_COUNT]; + +///// + +// IRQ Stack + +#if ALT_INT_PROVISION_STACK_SUPPORT + +static char __attribute__ ((aligned (16))) alt_int_stack_irq_block[ALT_INT_PROVISION_CPU_COUNT][ALT_INT_PROVISION_STACK_SIZE]; + +#ifdef __ARMCC_VERSION +// ARMCC specific helper function to fixup the IRQ stack. +// This is implemented in alt_interrupt_armcc.s. +extern void alt_int_fixup_irq_stack(uint32_t stack_irq); +#else +static void alt_int_fixup_irq_stack(uint32_t stack_irq) +{ + // 1. Save the current SP + // 2. Switch to the IRQ context + // 3. Point SP to the stack IRQ block provided + // 4. Switch back to SYS context + // 5. Restore the saved "current" SP + + // Mode_USR 0x10 + // Mode_FIQ 0x11 + // Mode_IRQ 0x12 + // Mode_SVC 0x13 + // Mode_MON 0x16 + // Mode_ABT 0x17 + // Mode_UNDEF 0x1B + // Mode_SYS 0x1F + + // I_Bit 0x80 @ when I bit is set, IRQ is disabled + // F_Bit 0x40 @ when F bit is set, FIQ is disabled + // NS_BIT 0x1 @ when NS bit is set, core in non-secure + + // r4 being used for stack_sys. + // Consider adding "lr" to the list of mangled registers. This way GCC will push/pop {lr} for us. + __asm( + "push {lr}\n" + "mov r4, sp\n" + "msr CPSR_c, #(0x12 | 0x80 | 0x40)\n" + "mov sp, %0\n" + "msr CPSR_c, #(0x1F | 0x80 | 0x40)\n" + "mov sp, r4\n" + "pop {lr}\n" + + : : "r" (stack_irq) : "sp", "r4" + ); +} +#endif + +#endif // #if ALT_INT_PROVISION_STACK_SUPPORT + +///// + +// Interrupt dispatch information +// See Cortex-A9 MPCore TRM, section 1.3. +// SGI (16) + PPI (16) + SPI count (224) = total number of interrupts. +typedef struct INT_DISPATCH_s +{ + alt_int_callback_t callback; + void * context; +} +INT_DISPATCH_t; + +static INT_DISPATCH_t alt_int_dispatch[ALT_INT_PROVISION_INT_COUNT]; + +///// + +// Distributer interface base address +static uint32_t alt_int_base_dist; +// CPU interface base address +static uint32_t alt_int_base_cpu; + +///// + +// Number of CPU(s) in system +static uint32_t alt_int_count_cpu; +// Number of interrupts in system, rounded up to nearest 32 +static uint32_t alt_int_count_int; + +///// + +inline static uint32_t get_periphbase(void) +{ + uint32_t periphbase; + + // Read the Peripheral Base Address. + // See: Cortex-A9 TRM, section 4.3.24. + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 4, periphbase, c15, c0, 0"); +#else + __asm("MRC p15, 4, %0, c15, c0, 0" : "=r" (periphbase)); +#endif + + return periphbase; +} + +#if ALT_INT_PROVISION_VECTOR_SUPPORT +inline static void set_sctlr_vbit(bool value) +{ + // See ARMv7, section B4.1.130. + + uint32_t sctlr; + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, sctlr, c1, c0, 0"); +#else + __asm("MRC p15, 0, %0, c1, c0, 0" : "=r" (sctlr)); +#endif + + if (value) + { + sctlr |= 1 << 13; + } + else + { + sctlr &= ~(1 << 13); + } + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, sctlr, c1, c0, 0"); +#else + __asm("MCR p15, 0, %0, c1, c0, 0" : : "r" (sctlr)); +#endif + +} +#endif + +inline static uint32_t get_current_cpu_num(void) +{ + uint32_t affinity; + + // Use the MPIDR. This is only available at PL1 or higher. + // See ARMv7, section B4.1.106. + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, affinity, c0, c0, 5"); +#else + __asm ("MRC p15, 0, %0, c0, c0, 5" : "=r" (affinity)); +#endif + + return affinity & 0xFF; +} + +///// + +ALT_STATUS_CODE alt_int_global_init() +{ + // Cache the distributor and CPU base addresses + // See: Cortex-A9 MPCore TRM, section 1.5. + { + uint32_t periphbase = get_periphbase(); + alt_int_base_dist = periphbase + 0x1000; + alt_int_base_cpu = periphbase + 0x0100; + } + + // Discover CPU and interrupt count + // See GIC 1.0, section 4.3.2. + { + uint32_t icdictr = alt_read_word(alt_int_base_dist + 0x4); + alt_int_count_cpu = ((icdictr >> 5) & 0x7) + 1; + alt_int_count_int = ((icdictr & 0x1F) + 1) << 5; + } + + // Initialize the callback and context array + // Initialize interrupt flags array + for (int i = 0; i < ALT_INT_PROVISION_INT_COUNT; ++i) + { + alt_int_dispatch[i].callback = 0; + alt_int_dispatch[i].context = 0; + + alt_int_flag[i] = 0; + } + + // Discover all interrupts that are implemented in hardware. + // See GIC 1.0, section 3.1.2. + for (int i = 0; i < (ALT_INT_PROVISION_INT_COUNT / 32); ++i) + { + // Set the whole bank to be enabled. + alt_write_word(alt_int_base_dist + 0x100 + i * sizeof(uint32_t), 0xffffffff); // icdisern + + // Read it back to see which bits stick. + uint32_t value = alt_read_word(alt_int_base_dist + 0x100 + i * sizeof(uint32_t)); // icdisern + for (int j = 0; j < 32; ++j) + { + if (((1 << j) & value) != 0) + { + alt_int_flag[i * 32 + j] |= INT_FLAG_IMPLEMENTED; + } + } + + // Clear the whole bank to be disabled. + alt_write_word(alt_int_base_dist + 0x180 + i * sizeof(uint32_t), 0xffffffff); // icdicern + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_global_uninit() +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_global_enable() +{ + // See GIC 1.0, section 4.3.1. + // See Cortex-A9 MPCore TRM, section 3.3.1. + + alt_setbits_word(alt_int_base_dist + 0x0, 0x1); // icddcr + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_global_disable() +{ + // See GIC 1.0, section 4.3.1. + // See Cortex-A9 MPCore TRM, section 3.3.1. + + alt_clrbits_word(alt_int_base_dist + 0x0, 0x1); // icddcr + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_global_enable_ns() +{ + // See Cortex-A9 MPCore TRM, section 3.3.1. + + alt_setbits_word(alt_int_base_dist + 0x0, 0x2); // icddcr + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_global_disable_ns() +{ + // See Cortex-A9 MPCore TRM, section 3.3.1. + + alt_clrbits_word(alt_int_base_dist + 0x0, 0x2); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_global_enable_all() +{ + // See Cortex-A9 MPCore TRM, section 3.3.1. + + alt_setbits_word(alt_int_base_dist + 0x0, 0x3); // icddcr + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_global_disable_all() +{ + // See Cortex-A9 MPCore TRM, section 3.3.1. + + alt_clrbits_word(alt_int_base_dist + 0x0, 0x3); // icddcr + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_int_dist_secure_enable(ALT_INT_INTERRUPT_t int_id) +{ + // See GIC 1.0, section 4.3.4. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + return ALT_E_BAD_ARG; + } + else + { + uint32_t regoffset = int_id >> 5; + uint32_t regbitshift = int_id & 0x1F; + + alt_clrbits_word(alt_int_base_dist + 0x80 + regoffset * sizeof(uint32_t), 1 << regbitshift); // icdisrn + + return ALT_E_SUCCESS; + } +} + +ALT_STATUS_CODE alt_int_dist_secure_disable(ALT_INT_INTERRUPT_t int_id) +{ + // See GIC 1.0, section 4.3.4. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + return ALT_E_BAD_ARG; + } + else + { + uint32_t regoffset = int_id >> 5; + uint32_t regbitshift = int_id & 0x1F; + + alt_setbits_word(alt_int_base_dist + 0x80 + regoffset * sizeof(uint32_t), 1 << regbitshift); // icdisrn + + return ALT_E_SUCCESS; + } +} + +ALT_STATUS_CODE alt_int_dist_is_secure(ALT_INT_INTERRUPT_t int_id) +{ + // See GIC 1.0, section 4.3.4. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + // Because interrupts are by default after reset secure, return the + // default security state. + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + // Because interrupts are by default after reset secure, return the + // default security state. + return ALT_E_TRUE; + } + else + { + uint32_t regoffset = int_id >> 5; + uint32_t regbitshift = int_id & 0x1F; + + uint32_t icdisrn = alt_read_word(alt_int_base_dist + 0x80 + regoffset * sizeof(uint32_t)); + + if ((icdisrn & (1 << regbitshift)) == 0) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } + } +} + +ALT_STATUS_CODE alt_int_dist_enable(ALT_INT_INTERRUPT_t int_id) +{ + // See GIC 1.0, section 4.3.5. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + return ALT_E_BAD_ARG; + } + else + { + uint32_t regoffset = int_id >> 5; + uint32_t regbitshift = int_id & 0x1F; + + alt_write_word(alt_int_base_dist + 0x100 + regoffset * sizeof(uint32_t), 1 << regbitshift); // icdisern + + return ALT_E_SUCCESS; + } +} + +ALT_STATUS_CODE alt_int_dist_disable(ALT_INT_INTERRUPT_t int_id) +{ + // See GIC 1.0, section 4.3.6. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + return ALT_E_BAD_ARG; + } + else + { + uint32_t regoffset = int_id >> 5; + uint32_t regbitshift = int_id & 0x1F; + + alt_write_word(alt_int_base_dist + 0x180 + regoffset * sizeof(uint32_t), 1 << regbitshift); // icdicern + + return ALT_E_SUCCESS; + } +} + +ALT_STATUS_CODE alt_int_dist_is_enabled(ALT_INT_INTERRUPT_t int_id) +{ + // See GIC 1.0, section 4.3.5. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + // Interrupts on the GIC is disabled by default, so report disabled. + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + // Interrupts on the GIC is disabled by default, so report disabled. + return ALT_E_FALSE; + } + else + { + uint32_t regoffset = int_id >> 5; + uint32_t regbitshift = int_id & 0x1F; + + uint32_t icdisern = alt_read_word(alt_int_base_dist + 0x100 + regoffset * sizeof(uint32_t)); + + if ((icdisern & (1 << regbitshift)) != 0) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } + } +} + +ALT_STATUS_CODE alt_int_dist_pending_set(ALT_INT_INTERRUPT_t int_id) +{ + // See GIC 1.0, section 4.3.7. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + return ALT_E_BAD_ARG; + } + else if ((uint32_t)int_id < 16) + { + return ALT_E_BAD_ARG; + } + else + { + uint32_t regoffset = int_id >> 5; + uint32_t regbitshift = int_id & 0x1F; + + alt_write_word(alt_int_base_dist + 0x200 + regoffset * sizeof(uint32_t), 1 << regbitshift); // icdisprn + + return ALT_E_SUCCESS; + } +} + +ALT_STATUS_CODE alt_int_dist_pending_clear(ALT_INT_INTERRUPT_t int_id) +{ + // See GIC 1.0, section 4.3.8. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + return ALT_E_BAD_ARG; + } + else if ((uint32_t)int_id < 16) + { + return ALT_E_BAD_ARG; + } + else + { + uint32_t regoffset = int_id >> 5; + uint32_t regbitshift = int_id & 0x1F; + + alt_write_word(alt_int_base_dist + 0x280 + regoffset * sizeof(uint32_t), 1 << regbitshift); // icdicprn + + return ALT_E_SUCCESS; + } +} + +ALT_STATUS_CODE alt_int_dist_is_pending(ALT_INT_INTERRUPT_t int_id) +{ + // See GIC 1.0, section 4.3.7. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + // Interrupts on the GIC is not pending by default, so report false. + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + // Interrupts on the GIC is not pending by default, so report false. + return ALT_E_FALSE; + } + else + { + uint32_t regoffset = int_id >> 5; + uint32_t regbitshift = int_id & 0x1F; + + uint32_t icdisprn = alt_read_word(alt_int_base_dist + 0x200 + regoffset * sizeof(uint32_t)); + + if ((icdisprn & (1 << regbitshift)) != 0) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } + } +} + +ALT_STATUS_CODE alt_int_dist_is_active(ALT_INT_INTERRUPT_t int_id) +{ + // See GIC 1.0, section 4.3.9. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + // Interrupts on the GIC is not active by default, so report false. + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + // Interrupts on the GIC is not active by default, so report false. + return ALT_E_FALSE; + } + else + { + uint32_t regoffset = int_id >> 5; + uint32_t regbitshift = int_id & 0x1F; + + uint32_t icdabrn = alt_read_word(alt_int_base_dist + 0x300 + regoffset * sizeof(uint32_t)); + + if ((icdabrn & (1 << regbitshift)) != 0) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } + } +} + +ALT_STATUS_CODE alt_int_dist_priority_get(ALT_INT_INTERRUPT_t int_id, + uint32_t * priority) +{ + // See GIC 1.0, section 4.3.10. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + // Interrupts on the GIC have a default priority of 0. + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + // Interrupts on the GIC have a default priority of 0. + *priority = 0; + return ALT_E_SUCCESS; + } + else + { + uint32_t regoffset = int_id; + + uint8_t icdiprn = alt_read_byte(alt_int_base_dist + 0x400 + regoffset * sizeof(uint8_t)); + + *priority = icdiprn; + return ALT_E_SUCCESS; + } +} + +ALT_STATUS_CODE alt_int_dist_priority_set(ALT_INT_INTERRUPT_t int_id, + uint32_t priority) +{ + // See GIC 1.0, section 4.3.10. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + return ALT_E_BAD_ARG; + } + else if (priority < 256) + { + uint32_t regoffset = int_id; + + alt_write_byte(alt_int_base_dist + 0x400 + regoffset * sizeof(uint8_t), (uint8_t)priority); // icdiprn + + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + +ALT_STATUS_CODE alt_int_dist_target_get(ALT_INT_INTERRUPT_t int_id, + alt_int_cpu_target_t * target) +{ + // See GIC 1.0, section 4.3.11. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + *target = 0; + return ALT_E_SUCCESS; + } + else + { + uint32_t regoffset = int_id; + + uint8_t icdiptr = alt_read_byte(alt_int_base_dist + 0x800 + regoffset * sizeof(uint8_t)); + + *target = icdiptr; + return ALT_E_SUCCESS; + } +} + +ALT_STATUS_CODE alt_int_dist_target_set(ALT_INT_INTERRUPT_t int_id, + alt_int_cpu_target_t target) +{ + // See GIC 1.0, section 4.3.11. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + return ALT_E_BAD_ARG; + } + else if (target >= (1 << alt_int_count_cpu)) + { + if (target == (1 << get_current_cpu_num())) + { + return ALT_E_SUCCESS; + } + return ALT_E_BAD_ARG; + } + else if (int_id < 32) + { + return ALT_E_BAD_ARG; + } + else + { + uint32_t regoffset = int_id; + + alt_write_byte(alt_int_base_dist + 0x800 + regoffset * sizeof(uint8_t), target); // icdiptr + + return ALT_E_SUCCESS; + } +} + +ALT_STATUS_CODE alt_int_dist_trigger_get(ALT_INT_INTERRUPT_t int_id, + ALT_INT_TRIGGER_t * trigger) +{ + // See GIC 1.0, section 4.3.12. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + *trigger = ALT_INT_TRIGGER_NA; + return ALT_E_SUCCESS; + } + else if (int_id < 16) + { + *trigger = ALT_INT_TRIGGER_SOFTWARE; + return ALT_E_SUCCESS; + } + else + { + uint32_t regoffset = int_id >> 4; + uint32_t regbitshift = ((int_id & 0x0F) * 2) + 1; + + uint32_t icdicfrn = alt_read_word(alt_int_base_dist + 0xC00 + regoffset * sizeof(uint32_t)); + + if ((icdicfrn & (1 << regbitshift)) == 0) + { + *trigger = ALT_INT_TRIGGER_LEVEL; + } + else + { + *trigger = ALT_INT_TRIGGER_EDGE; + } + + return ALT_E_SUCCESS; + } +} + +ALT_STATUS_CODE alt_int_dist_trigger_set(ALT_INT_INTERRUPT_t int_id, + ALT_INT_TRIGGER_t trigger_type) +{ + // See GIC 1.0, section 4.3.12. + + if ((uint32_t)int_id >= ALT_INT_PROVISION_INT_COUNT) + { + return ALT_E_BAD_ARG; + } + else if ((alt_int_flag[int_id] & INT_FLAG_IMPLEMENTED) == 0) + { + return ALT_E_BAD_ARG; + } + else if (int_id < 16) + { + if ( (trigger_type == ALT_INT_TRIGGER_AUTODETECT) + || (trigger_type == ALT_INT_TRIGGER_SOFTWARE)) + { + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } + } + else + { + uint32_t regoffset = int_id >> 4; + uint32_t regbitshift = ((int_id & 0x0F) * 2) + 1; + + if (trigger_type == ALT_INT_TRIGGER_AUTODETECT) + { + if (int_id <= 32) { trigger_type = ALT_INT_TRIGGER_EDGE; } // PPI + else if (int_id <= 40) { trigger_type = ALT_INT_TRIGGER_EDGE; } // CPU0_PARITYFAIL + else if (int_id <= 47) { trigger_type = ALT_INT_TRIGGER_LEVEL; } // CPU0_DEFLAGS + else if (int_id <= 56) { trigger_type = ALT_INT_TRIGGER_EDGE; } // CPU1_PARITYFAIL + else if (int_id <= 63) { trigger_type = ALT_INT_TRIGGER_LEVEL; } // CPU1_DEFLAGS + else if (int_id <= 66) { trigger_type = ALT_INT_TRIGGER_EDGE; } // SCU + else if (int_id <= 69) { trigger_type = ALT_INT_TRIGGER_EDGE; } // L2_ECC + else if (int_id <= 70) { trigger_type = ALT_INT_TRIGGER_LEVEL; } // L2 (other) + else if (int_id <= 71) { trigger_type = ALT_INT_TRIGGER_LEVEL; } // DDR + else if (int_id <= 135) { /* do nothing */ } // FPGA, !!! + else { trigger_type = ALT_INT_TRIGGER_LEVEL; } // everything else + } + + switch (trigger_type) + { + case ALT_INT_TRIGGER_LEVEL: + alt_clrbits_word(alt_int_base_dist + 0xC00 + regoffset * sizeof(uint32_t), 1 << regbitshift); // icdicfrn + break; + case ALT_INT_TRIGGER_EDGE: + alt_setbits_word(alt_int_base_dist + 0xC00 + regoffset * sizeof(uint32_t), 1 << regbitshift); // icdicfrn + break; + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; + } +} + +///// + +ALT_STATUS_CODE alt_int_sgi_trigger(ALT_INT_INTERRUPT_t int_id, + ALT_INT_SGI_TARGET_t target_filter, + alt_int_cpu_target_t target_list, + bool secure_only) +{ + // See GIC 1.0, section 4.3.13. + + if (target_list >= (1 << alt_int_count_cpu)) + { + return ALT_E_BAD_ARG; + } + else if ((uint32_t)int_id < 16) + { + uint32_t filterbits; + uint32_t sattmask = 0; + + switch (target_filter) + { + case ALT_INT_SGI_TARGET_LIST: + filterbits = 0x0 << 24; + break; + case ALT_INT_SGI_TARGET_ALL_EXCL_SENDER: + filterbits = 0x1 << 24; + break; + case ALT_INT_SGI_TARGET_SENDER_ONLY: + filterbits = 0x2 << 24; + break; + default: + return ALT_E_BAD_ARG; + } + + if (!secure_only) + { + sattmask = 1 << 15; + } + + alt_write_word(alt_int_base_dist + 0xF00, int_id | sattmask | (target_list << 16) | filterbits); // icdsgir + + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + +///// + +ALT_STATUS_CODE alt_int_cpu_init() +{ + uint32_t cpu_num = get_current_cpu_num(); + + if (cpu_num >= ALT_INT_PROVISION_CPU_COUNT) + { + return ALT_E_ERROR; + } + + // Setup the IRQ stack + +#if ALT_INT_PROVISION_STACK_SUPPORT + + // The ARM stack lowers in address as it is being used. 16 is the alignment + // of the block. + uint32_t stack_irq = (uint32_t) &alt_int_stack_irq_block[cpu_num][sizeof(alt_int_stack_irq_block[0]) - 16]; + + alt_int_fixup_irq_stack(stack_irq); + +#endif // #if ALT_INT_PROVISION_STACK_SUPPORT + + // Setup the Vector Interrupt Table + +#if ALT_INT_PROVISION_VECTOR_SUPPORT + + // Set the vector interrupt table (VBAR) to use __cs3_interrupt_vector and + // set SCTLR.V to always be 0. + + // For SCTLR.V information, See ARMv7, section B4.1.130. + // For VBAR information, See ARMv7, section B4.1.156. + + set_sctlr_vbit(false); + +#ifdef __ARMCC_VERSION + extern char alt_interrupt_vector; + uint32_t vector_table = (uint32_t)&alt_interrupt_vector; + __asm("MCR p15, 0, vector_table, c12, c0, 0"); +#else + extern char __cs3_interrupt_vector; + uint32_t vector_table = (uint32_t)&__cs3_interrupt_vector; + __asm("MCR p15, 0, %0, c12, c0, 0" : : "r" (vector_table)); +#endif + +#endif // #if ALT_INT_PROVISION_VECTOR_SUPPORT + + // Setup the priority mask and binary point defaults. + // This will allow all interrupts to have sufficient priority to be + // forwarded to the CPUs. + + ALT_STATUS_CODE status; + + status = alt_int_cpu_priority_mask_set(0xff); + if (status != ALT_E_SUCCESS) + { + return status; + } + status = alt_int_cpu_binary_point_set(0); + if (status != ALT_E_SUCCESS) + { + return status; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_cpu_uninit() +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_cpu_enable() +{ + // See GIC 1.0, section 4.4.1. + + alt_setbits_word(alt_int_base_cpu + 0x0, 0x1); // iccicr + + // Unmask IRQ interrupts from current processor. + +#ifdef __ARMCC_VERSION + __enable_irq(); +#else + __asm("CPSIE i"); +#endif + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_cpu_disable() +{ + // See GIC 1.0, section 4.4.1. + + alt_clrbits_word(alt_int_base_cpu + 0x0, 0x1); // iccicr + + // Mask IRQ interrupts from current processor. + +#ifdef __ARMCC_VERSION + __disable_irq(); +#else + __asm("CPSID i"); +#endif + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_cpu_enable_ns() +{ + // See GIC 1.0, section 4.4.1. + + alt_setbits_word(alt_int_base_cpu + 0x0, 0x2); // iccicr + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_cpu_disable_ns() +{ + // See GIC 1.0, section 4.4.1. + + alt_clrbits_word(alt_int_base_cpu + 0x0, 0x2); // iccicr + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_cpu_enable_all() +{ + // See GIC 1.0, section 4.4.1. + + alt_setbits_word(alt_int_base_cpu + 0x0, 0x3); // iccicr + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_cpu_disable_all() +{ + // See GIC 1.0, section 4.4.1. + + alt_clrbits_word(alt_int_base_cpu + 0x0, 0x3); // iccicr + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_cpu_config_get(bool* use_secure_binary_point, + bool* use_FIQ_for_secure_interrupts, + bool* allow_secure_ack_all_interrupts) +{ + // See GIC 1.0, section 4.4.1. + + uint32_t iccicr = alt_read_word(alt_int_base_cpu + 0x0); + + if (use_secure_binary_point) + { + *use_secure_binary_point = (iccicr & (1 << 4)) != 0; + } + if (use_FIQ_for_secure_interrupts) + { + *use_FIQ_for_secure_interrupts = (iccicr & (1 << 3)) != 0; + } + if (allow_secure_ack_all_interrupts) + { + *allow_secure_ack_all_interrupts = (iccicr & (1 << 2)) != 0; + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_int_cpu_config_set(bool use_secure_binary_point, + bool use_FIQ_for_secure_interrupts, + bool allow_secure_ack_all_interrupts) +{ + // See GIC 1.0, section 4.4.1. + + uint32_t iccicr = alt_read_word(alt_int_base_cpu + 0x0); + + if (use_secure_binary_point) + { + iccicr |= 1 << 4; + } + else + { + iccicr &= ~(1 << 4); + } + + if (use_FIQ_for_secure_interrupts) + { + iccicr |= 1 << 3; + } + else + { + iccicr &= ~(1 << 3); + } + + if (allow_secure_ack_all_interrupts) + { + iccicr |= 1 << 2; + } + else + { + iccicr &= ~(1 << 2); + } + + alt_write_word(alt_int_base_cpu + 0x0, iccicr); + + return ALT_E_SUCCESS; +} + +uint32_t alt_int_cpu_priority_mask_get() +{ + // See GIC 1.0, section 4.4.2. + + uint32_t iccpmr = alt_read_word(alt_int_base_cpu + 0x4); + + return iccpmr; +} + +ALT_STATUS_CODE alt_int_cpu_priority_mask_set(uint32_t priority_mask) +{ + // See GIC 1.0, section 4.4.2. + + if (priority_mask < 256) + { + alt_write_word(alt_int_base_cpu + 0x4, priority_mask); // iccpmr + + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + +uint32_t alt_int_cpu_binary_point_get() +{ + // See GIC 1.0, section 4.4.3. + + uint32_t iccbpr = alt_read_word(alt_int_base_cpu + 0x8); + + return iccbpr; +} + +ALT_STATUS_CODE alt_int_cpu_binary_point_set(uint32_t binary_point) +{ + // See GIC 1.0, section 4.4.3. + + if (binary_point < 8) + { + alt_write_word(alt_int_base_cpu + 0x8, binary_point); // iccbpr + + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + +uint32_t alt_int_cpu_binary_point_get_ns() +{ + // See GIC 1.0, section 4.4.7. + + uint32_t iccabpr = alt_read_word(alt_int_base_cpu + 0x1C); + + return iccabpr; +} + +ALT_STATUS_CODE alt_int_cpu_binary_point_set_ns(uint32_t binary_point) +{ + // See GIC 1.0, section 4.4.7. + + if (binary_point < 8) + { + alt_write_word(alt_int_base_cpu + 0x1C, binary_point); // iccabpr + + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + +///// + +ALT_STATUS_CODE alt_int_isr_register(ALT_INT_INTERRUPT_t int_id, + alt_int_callback_t callback, + void * context) +{ + if ((uint32_t)int_id < ALT_INT_PROVISION_INT_COUNT) + { + alt_int_dispatch[int_id].callback = callback; + alt_int_dispatch[int_id].context = context; + + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + +ALT_STATUS_CODE alt_int_isr_unregister(ALT_INT_INTERRUPT_t int_id) +{ + if ((uint32_t)int_id < ALT_INT_PROVISION_INT_COUNT) + { + alt_int_dispatch[int_id].callback = 0; + alt_int_dispatch[int_id].context = 0; + + return ALT_E_SUCCESS; + } + else + { + return ALT_E_BAD_ARG; + } +} + +///// + +uint32_t alt_int_util_cpu_count(void) +{ + return alt_int_count_cpu; +} + +uint32_t alt_int_util_int_count(void) +{ + return alt_int_count_int; +} + +alt_int_cpu_target_t alt_int_util_cpu_current(void) +{ + return 1 << get_current_cpu_num(); +} + +///// + +#if ALT_INT_PROVISION_VECTOR_SUPPORT + +#ifdef __ARMCC_VERSION +void __irq alt_int_handler_irq(void) +#else +void __attribute__ ((interrupt)) __cs3_isr_irq(void) +#endif + +#else // #if ALT_INT_PROVISION_VECTOR_SUPPORT + +void alt_int_handler_irq(void) + +#endif // #if ALT_INT_PROVISION_VECTOR_SUPPORT +{ + // See GIC 1.0, sections 4.4.4, 4.4.5. + + uint32_t icciar = alt_read_word(alt_int_base_cpu + 0xC); + + uint32_t ackintid = ALT_INT_ICCIAR_ACKINTID_GET(icciar); + + if (ackintid < ALT_INT_PROVISION_INT_COUNT) + { + if (alt_int_dispatch[ackintid].callback) + { + alt_int_dispatch[ackintid].callback(icciar, alt_int_dispatch[ackintid].context); + } + } + else + { + // Report error. + dprintf("INT[ISR]: Unhandled interrupt ID = 0x%lx.\n", ackintid); + } + + alt_write_word(alt_int_base_cpu + 0x10, icciar); // icceoir +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_interrupt_armcc.s b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_interrupt_armcc.s new file mode 100644 index 000000000..fdf1f981e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_interrupt_armcc.s @@ -0,0 +1,121 @@ +;***************************************************************************** +;* +;* Copyright 2013 Altera Corporation. All Rights Reserved. +;* +;* Redistribution and use in source and binary forms, with or without +;* modification, are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* +;* 3. The name of the author may not be used to endorse or promote products +;* derived from this software without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +;* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +;* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +;* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +;* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;*****************************************************************************/ + +;; This is a small stub vector put in front of the ARMCC image to support +;; interrupts. + + PRESERVE8 + AREA VECTORS, CODE, READONLY + + ENTRY + + EXPORT alt_interrupt_vector + IMPORT __main + EXPORT alt_int_handler_irq [WEAK] + +alt_interrupt_vector + +Vectors + LDR PC, alt_reset_addr + LDR PC, alt_undef_addr + LDR PC, alt_svc_addr + LDR PC, alt_prefetch_addr + LDR PC, alt_abort_addr + LDR PC, alt_reserved_addr + LDR PC, alt_irq_addr + LDR PC, alt_fiq_addr + +alt_reset_addr DCD alt_int_handler_reset +alt_undef_addr DCD alt_int_handler_undef +alt_svc_addr DCD alt_int_handler_svc +alt_prefetch_addr DCD alt_int_handler_prefetch +alt_abort_addr DCD alt_int_handler_abort +alt_reserved_addr DCD alt_int_handler_reserve +alt_irq_addr DCD alt_int_handler_irq +alt_fiq_addr DCD alt_int_handler_fiq + +alt_int_handler_reset + B alt_premain +alt_int_handler_undef + B alt_int_handler_undef +alt_int_handler_svc + B alt_int_handler_svc +alt_int_handler_prefetch + B alt_int_handler_prefetch +alt_int_handler_abort + B alt_int_handler_abort +alt_int_handler_reserve + B alt_int_handler_reserve +alt_int_handler_irq + B alt_int_handler_irq +alt_int_handler_fiq + B alt_int_handler_fiq + +;===== + + AREA ALT_INTERRUPT_ARMCC, CODE, READONLY + +alt_premain FUNCTION + +; Enable VFP / NEON. + MRC p15, 0, r0, c1, c0, 2 ; Read CP Access register + ORR r0, r0, #0x00f00000 ; Enable full access to NEON/VFP (Coprocessors 10 and 11) + MCR p15, 0, r0, c1, c0, 2 ; Write CP Access register + ISB + MOV r0, #0x40000000 ; Switch on the VFP and NEON hardware + VMSR fpexc, r0 ; Set EN bit in FPEXC + + B __main + + ENDFUNC + +;===== + + AREA ALT_INTERRUPT_ARMCC, CODE, READONLY + + EXPORT alt_int_fixup_irq_stack + +; void alt_int_fixup_irq_stack(uint32_t stack_irq); + ; This is the same implementation of GNU but for ARMCC. +alt_int_fixup_irq_stack FUNCTION + ; r4: stack_sys + + PUSH {lr} + MOV r4, sp + MSR CPSR_c, #(0x12 :OR: 0x80 :OR: 0x40) + MOV sp, r0 + MSR CPSR_c, #(0x1F :OR: 0x80 :OR: 0x40) + MOV sp, r4 + POP {lr} + BX lr + + ENDFUNC + + END diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_mmu.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_mmu.c new file mode 100644 index 000000000..329c16671 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_mmu.c @@ -0,0 +1,1356 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_mmu.h" +#include +#include + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) + +///// + +// Generates the bitmask given the MSB and LSB of a register field. +// NOTE: This is problematic for the BITMASK(31, 0) case. +#define BITMASK(msb, lsb) (((1 << ((msb) - (lsb) + 1)) - 1) << (lsb)) +// Calculates the array count statically +#define ARRAY_COUNT(array) (sizeof(array) / sizeof(array[0])) +// Minimum +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +// Index into the pagetable given the virtual address. This is bits va[19:12] >> 12. +#define ALT_MMU_PAGE_TABLE_INDEX(va) (((uintptr_t)(va) >> 12) & 0xff) + +///// + +// This is the number of 1 MiB sections in the TTB1 table. +#define ALT_MMU_TTB1_SECTION_COUNT 4096 + +///// + +// System Control Register +#define ALT_CPU_SCTLR_C_SET_MSK (1 << 2) +#define ALT_CPU_SCTLR_M_SET_MSK (1 << 0) + +#define ALT_CPU_CONTEXTIDR_PROCID_SET_MSK (0xffffff << 8) +#define ALT_CPU_CONTEXTIDR_ASID_SET_MSK (0x0000ff << 0) + +// Translation Table Base Register 0 (Process Specific; Changes on context switch) + +// (31 to 14 - (TTBCR.N)) +#define ALT_CPU_TTBR0_TTB0BASEADDR_SET_MSK(ttbcr_n) BITMASK(31, 14 - (ttbcr_n)) +#define ALT_CPU_TTBR0_IRGN_0_SET_MSK (1 << 6) +#define ALT_CPU_TTBR0_NOS_SET_MSK (1 << 5) +#define ALT_CPU_TTBR0_RGN_SET_MSK (3 << 3) +#define ALT_CPU_TTBR0_IMP_SET_MSK (1 << 2) +#define ALT_CPU_TTBR0_S_SET_MSK (1 << 1) +#define ALT_CPU_TTBR0_IRGN_1_SET_MSK (1 << 0) + +#define ALT_CPU_TTBR0_RGN_NC (0 << 3) // RGN[1:0] = 00 +#define ALT_CPU_TTBR0_RGN_WBA (1 << 3) // RGN[1:0] = 01 +#define ALT_CPU_TTBR0_RGN_WT (2 << 3) // RGN[1:0] = 10 +#define ALT_CPU_TTBR0_RGN_WB (3 << 3) // RGN[1:0] = 11 + +// NOTE: IRGN bits are reversed. TTBR0[6] is IRGN[0]; TTBR[0] is IRGN[1]. +#define ALT_CPU_TTBR0_IRGN_NC (0 << 0 | 0 << 6) // IRGN[1:0] = 00 +#define ALT_CPU_TTBR0_IRGN_WBA (0 << 0 | 1 << 6) // IRGN[1:0] = 01 +#define ALT_CPU_TTBR0_IRGN_WT (1 << 0 | 0 << 6) // IRGN[1:0] = 10 +#define ALT_CPU_TTBR0_IRGN_WB (1 << 0 | 1 << 6) // IRGN[1:0] = 11 + +// Translation Table Base Register 1 (OS and IO specific; Static) +#define ALT_CPU_TTBR1_TTB1BASEADDR_SET_MSK (0x3ffffUL << 14) +#define ALT_CPU_TTBR1_IRGN_0_SET_MSK (1 << 6) +#define ALT_CPU_TTBR1_NOS_SET_MSK (1 << 5) +#define ALT_CPU_TTBR1_RGN_SET_MSK (3 << 3) +#define ALT_CPU_TTBR1_IMP_SET_MSK (1 << 2) +#define ALT_CPU_TTBR1_S_SET_MSK (1 << 1) +#define ALT_CPU_TTBR1_IRGN_1_SET_MSK (1 << 0) + +// Translation Table Base Control Register +#define ALT_CPU_TTBCR_PD1_SET_MSK (1 << 5) +#define ALT_CPU_TTBCR_PD0_SET_MSK (1 << 4) +#define ALT_CPU_TTBCR_N_SET_MSK (7 << 0) +#define ALT_CPU_TTBCR_N_VALUE_GET(value) (((value) << 0) & ALT_CPU_TTBCR_N_SET_MSK) + +///// + +static inline __attribute__((always_inline)) uint32_t sctlr_get_helper(void) +{ + // Read from SCTLR using CP15. + // See ARMv7-A,R, section B4.1.30. + + uint32_t sctlr; + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, sctlr, c1, c0, 0"); +#else + __asm("MRC p15, 0, %0, c1, c0, 0" : "=r" (sctlr)); +#endif + + return sctlr; +} + +static inline __attribute__((always_inline)) void sctlr_set_helper(uint32_t sctlr) +{ + // Write to SCTLR using CP15. + // See ARMv7-A,R, section B4.1.30. + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, sctlr, c1, c0, 0"); +#else + __asm("MCR p15, 0, %0, c1, c0, 0" : : "r" (sctlr)); +#endif +} + +/* +__attribute__((always_inline)) uint32_t contextidr_get_helper(void) +{ + // Read from CONTEXTIDR using CP15. + // See ARMv7-A,R, section B4.1.36. + + uint32_t contextidr; + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, contextidr, c13, c0, 1"); +#else + __asm("MRC p15, 0, %0, c13, c0, 1" : "=r" (contextidr)); +#endif + + return contextidr; +} +*/ + +static inline __attribute__((always_inline)) void contextidr_set_helper(uint32_t contextidr) +{ + // Write to CONTEXTIDR using CP15. + // See ARMv7-A,R, section B4.1.36. + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, contextidr, c13, c0, 1"); +#else + __asm("MCR p15, 0, %0, c13, c0, 1" : : "r" (contextidr)); +#endif +} + +/* +__attribute__((always_inline)) uint32_t dacr_get_helper(void) +{ + // Read from DACR using CP15. + // See ARMv7-A,R, section B4.1.43. + + uint32_t dacr; + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, dacr, c3, c0, 0"); +#else + __asm("MRC p15, 0, %0, c3, c0, 0" : "=r" (dacr)); +#endif + + return dacr; +} +*/ + +static inline __attribute__((always_inline)) void dacr_set_helper(uint32_t dacr) +{ + // Write to DACR using CP15. + // See ARMv7-A,R, section B4.1.43. + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, dacr, c3, c0, 0"); +#else + __asm("MCR p15, 0, %0, c3, c0, 0" : : "r" (dacr)); +#endif +} + +static inline __attribute__((always_inline)) uint32_t ttbcr_get_helper(void) +{ + // Read from TTBCR using CP15. + // See ARMv7-A,R, section B4.1.153. + + uint32_t ttbcr; + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, ttbcr, c2, c0, 2"); +#else + __asm("MRC p15, 0, %0 , c2, c0, 2" : "=r" (ttbcr)); +#endif + + return ttbcr; +} + +static inline __attribute__((always_inline)) void ttbcr_set_helper(uint32_t ttbcr) +{ + // Write to TTBCR using CP15. + // See ARMv7-A,R, section B4.1.153. + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, ttbcr, c2, c0, 2"); +#else + __asm("MCR p15, 0, %0, c2, c0, 2" : : "r" (ttbcr)); +#endif +} + +static inline __attribute__((always_inline)) uint32_t ttbr0_get_helper(void) +{ + // Read the TTBR0 using CP15. + // See ARMv7-A,R, section B4.1.154. + + uint32_t ttbr0; + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, ttbr0, c2, c0, 0"); +#else + __asm("MRC p15, 0, %0, c2, c0, 0" : "=r" (ttbr0)); +#endif + + return ttbr0; +} + +static inline __attribute__((always_inline)) void ttbr0_set_helper(uint32_t ttbr0) +{ + // Write to TTBR0 using CP15. + // See ARMv7-A,R, section B4.1.154. + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, ttbr0, c2, c0, 0"); +#else + __asm("MCR p15, 0, %0, c2, c0, 0" : : "r" (ttbr0)); +#endif +} + +static inline __attribute__((always_inline)) uint32_t ttbr1_get_helper(void) +{ + // Read the TTBR1 using CP15. + // See ARMv7-A,R, section B4.1.155. + + uint32_t ttbr1; + +#ifdef __ARMCC_VERSION + __asm("MRC p15, 0, ttbr1, c2, c0, 1"); +#else + __asm("MRC p15, 0, %0, c2, c0, 1" : "=r" (ttbr1)); +#endif + + return ttbr1; +} + +static inline __attribute__((always_inline)) void ttbr1_set_helper(uint32_t ttbr1) +{ + // Write to TTBR1 using CP15. + // See ARMv7-A,R, section B4.1.155. + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, ttbr1, c2, c0, 1"); +#else + __asm("MCR p15, 0, %0, c2, c0, 1" : : "r" (ttbr1)); +#endif +} + +///// + +ALT_STATUS_CODE alt_mmu_init(void) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_uninit(void) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_ttb1_init(uint32_t* ttb1) +{ + uint32_t ttbcr = ttbcr_get_helper(); + uint32_t ttbcr_n = ALT_CPU_TTBCR_N_VALUE_GET(ttbcr); + + // Verify ttb1 buffer alignment. + if ((uintptr_t)ttb1 & ~ALT_CPU_TTBR0_TTB0BASEADDR_SET_MSK(ttbcr_n)) + { + // addr must align to 2^(14 - TTBCR.N) bytes. + return ALT_E_BAD_ARG; + } + + // The TTB1 size really depends on TTBCR.N value and if it will be used for + // TTBR0 or TTBR1. The documentation just states that it should be 16 KiB. + // See ARMv7-A,R, section B3.5.4. + + memset(ttb1, 0, ALT_MMU_TTB1_SIZE); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_ttb1_desc_set(uint32_t* ttb1, + const void* va, + const uint32_t desc) +{ + bool supersection = 0; + + // Validate the [va] parameter alignment based on the entry [desc] is describing. + // - Fault, Page Table, or section: 1 MiB. + // - Supersection: 16 MiB + // - Other: error. + + switch (ALT_MMU_TTB1_TYPE_GET(desc)) + { + case ALT_MMU_TTB1_TYPE_SET(0x2): // Section or Supersection sans Physical Address Extension + // Check bit 18, which determines if it is a regular or super variant + if (desc & (1 << 18)) + { + // Mark that we are describing a supersection. + supersection = true; + + // Supersection: Check for 16 MiB alignment + if ((uintptr_t)va & (ALT_MMU_SUPERSECTION_SIZE - 1)) + { + return ALT_E_BAD_ARG; + } + break; + } + else + { + // Section, fall through. + } + case ALT_MMU_TTB1_TYPE_SET(0x0): // Fault + case ALT_MMU_TTB1_TYPE_SET(0x1): // Page Table + // Section, Fault, or Page Table: check for 1 MiB alignment + if ((uintptr_t)va & (ALT_MMU_SECTION_SIZE - 1)) + { + return ALT_E_BAD_ARG; + } + break; + case ALT_MMU_TTB1_TYPE_SET(0x3): // Supersection with Physical Address Extension + // The SoCFPGA does not support PAE. + return ALT_E_BAD_ARG; + } + + // The [va] looks good! Add entry into the TTB1. + + // TTB1 is indexed by va[31-N:20]. This function assumes N = 0. + uint32_t index = (uintptr_t)va >> 20; + + if (supersection == false) + { + ttb1[index] = desc; + } + else + { + // Supersection needs the entry to be repeated 16x. + for (int i = 0; i < 16; ++i) + { + ttb1[index + i] = desc; + } + + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_ttb2_desc_set(const uint32_t* ttb1, + const void* va, + const uint32_t desc) +{ + bool largepage = false; + + // Validate the [va] parameter alignment based on the entry [desc] is describing. + // - Fault, Small Page: 4 KiB + // - Large Page: 64 KiB + + switch (ALT_MMU_TTB2_TYPE_GET(desc)) + { + case ALT_MMU_TTB2_TYPE_SET(0x0): // Fault + case ALT_MMU_TTB2_TYPE_SET(0x2): // Small Page, XN = 0 + case ALT_MMU_TTB2_TYPE_SET(0x3): // Small Page, XN = 1 + if ((uintptr_t)va & (ALT_MMU_SMALL_PAGE_SIZE - 1)) + { + return ALT_E_BAD_ARG; + } + break; + case ALT_MMU_TTB2_TYPE_SET(0x1): // Large Page + if ((uintptr_t)va & (ALT_MMU_LARGE_PAGE_SIZE - 1)) + { + return ALT_E_BAD_ARG; + } + largepage = true; + break; + } + + // The [va] looks good! Add entry into TTB1->TTB2. + + // Locate the TTB1 entry + uint32_t ttb1_desc = ttb1[(uintptr_t)va >> 20]; + + // Verify that [ttb1_desc] is a pagetable. + if (ALT_MMU_TTB1_TYPE_GET(ttb1_desc) != ALT_MMU_TTB1_TYPE_SET(0x1)) + { + return ALT_E_BAD_ARG; + } + + // Locate TTB2 given [ttb1_desc] + uint32_t * ttb2 = (uint32_t *)(ttb1_desc & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK); + + // TTB2 is indexed by va[19:12]. + uint32_t index = ALT_MMU_PAGE_TABLE_INDEX(va); + if (largepage == false) + { + ttb2[index] = desc; + } + else + { + // Large page needs the entry to be repeated 16x. + for (int i = 0; i < 16; ++i) + { + ttb2[index + i] = desc; + } + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_disable(void) +{ + uint32_t sctlr = sctlr_get_helper(); + if (sctlr & ALT_CPU_SCTLR_C_SET_MSK) + { + dprintf("WARN[MMU]: Data cache still active.\n"); + } + sctlr &= ~ALT_CPU_SCTLR_M_SET_MSK; + sctlr_set_helper(sctlr); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_enable(void) +{ + alt_mmu_tlb_invalidate(); + + uint32_t sctlr = sctlr_get_helper(); + sctlr |= ALT_CPU_SCTLR_M_SET_MSK; + sctlr_set_helper(sctlr); + + return ALT_E_SUCCESS; +} + +void * alt_mmu_TTBR0_get(void) +{ + uint32_t ttbcr = ttbcr_get_helper(); + uint32_t ttbcr_n = ALT_CPU_TTBCR_N_VALUE_GET(ttbcr); + uint32_t ttbr0 = ttbr0_get_helper(); + + return (void *)(ALT_CPU_TTBR0_TTB0BASEADDR_SET_MSK(ttbcr_n) & ttbr0); +} + +ALT_STATUS_CODE alt_mmu_TTBR0_set(const void* addr) +{ + uint32_t ttbcr = ttbcr_get_helper(); + uint32_t ttbcr_n = ALT_CPU_TTBCR_N_VALUE_GET(ttbcr); + + if ((uintptr_t)addr & ~ALT_CPU_TTBR0_TTB0BASEADDR_SET_MSK(ttbcr_n)) + { + // addr must align to 2^(14 - TTBCR.N) bytes. + return ALT_E_BAD_ARG; + } + + // The Translation table must reside in Normal Memory, so pick the most + // performant attributes. + uint32_t ttbr0 = ALT_CPU_TTBR0_RGN_WBA // Translation table is WBA for outer cacheability + | ALT_CPU_TTBR0_IRGN_WBA; // Translation table is WBA for inner cacheability + ttbr0 &= ~ALT_CPU_TTBR0_TTB0BASEADDR_SET_MSK(ttbcr_n); + ttbr0 |= (uint32_t)addr; + + ttbr0_set_helper(ttbr0); + + return ALT_E_SUCCESS; +} + +void * alt_mmu_TTBR1_get(void) +{ + uint32_t ttbr1 = ttbr1_get_helper(); + + return (void *)(ALT_CPU_TTBR1_TTB1BASEADDR_SET_MSK & ttbr1); +} + +ALT_STATUS_CODE alt_mmu_TTBR1_set(const void* addr) +{ + if ((uintptr_t)addr & ~ALT_CPU_TTBR1_TTB1BASEADDR_SET_MSK) + { + // addr must align to 16 KiB. + return ALT_E_BAD_ARG; + } + + uint32_t ttbr1 = ttbr1_get_helper(); + ttbr1 &= ~ALT_CPU_TTBR1_TTB1BASEADDR_SET_MSK; + ttbr1 |= (uint32_t)addr; + + ttbr1_set_helper(ttbr1); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_TTBCR_set(const bool enable_ttbr0_walk, + const bool enable_ttbr1_walk, + const uint32_t base_addr_width) +{ + uint32_t ttbcr = 0; + + if (!enable_ttbr0_walk) + { + ttbcr |= ALT_CPU_TTBCR_PD0_SET_MSK; + } + + if (!enable_ttbr1_walk) + { + ttbcr |= ALT_CPU_TTBCR_PD1_SET_MSK; + } + + if (base_addr_width > 7) + { + return ALT_E_BAD_ARG; + } + + ttbcr |= base_addr_width; + + ttbcr_set_helper(ttbcr); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_DACR_set(const ALT_MMU_DAP_t domain_ap[], + const size_t num_elem) +{ + if (num_elem > 16) + { + return ALT_E_BAD_ARG; + } + + uint32_t dacr = 0; + + for (int i = 0; i < num_elem; ++i) + { + ALT_MMU_DAP_t ap = domain_ap[i]; + + switch (ap) + { + case ALT_MMU_DAP_NO_ACCESS: + case ALT_MMU_DAP_CLIENT: + case ALT_MMU_DAP_MANAGER: + dacr |= ap << (i * 2); + break; + default: + case ALT_MMU_DAP_RESERVED: + return ALT_E_BAD_ARG; + } + } + + dacr_set_helper(dacr); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_CONTEXTIDR_set(const uint32_t procid, const uint32_t asid) +{ + if (procid > 0x00ffffff) + { + return ALT_E_BAD_ARG; + } + + if (asid > 0xff) + { + return ALT_E_BAD_ARG; + } + + uint32_t contextidr = (procid << 8) | (asid << 0); + + contextidr_set_helper(contextidr); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_tlb_invalidate(void) +{ + // Issue TLBIALL (TLB Invalidate All) + // See ARMv7-A,R, section B4.1.135. + + uint32_t dummy = 0; + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, dummy, c8, c3, 0"); +#else + __asm("MCR p15, 0, %0, c8, c3, 0" : : "r" (dummy)); +#endif + + // Ensure all TLB maintenance operations complete before returning. + __asm("dsb"); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_tlb_invalidate_is(void) +{ + // Issue TLBIALLIS (TLB Invalidate All, Inner Shareable) + // See ARMv7-A,R, section B4.1.138. + + uint32_t dummy = 0; + +#ifdef __ARMCC_VERSION + __asm("MCR p15, 0, dummy, c8, c7, 0"); +#else + __asm("MCR p15, 0, %0, c8, c7, 0" : : "r" (dummy)); +#endif + + // Ensure all TLB maintenance operations complete before returning. + __asm("dsb"); + + return ALT_E_SUCCESS; +} + +///// + +// The #define value for PAGETABLE is designed to make the security check efficient. +#define ALT_VREGION_1MIB (2) /* 2 */ +#define ALT_VREGION_PAGETABLE_S ((int)ALT_MMU_TTB_NS_SECURE) /* 0 */ +#define ALT_VREGION_PAGETABLE_NS ((int)ALT_MMU_TTB_NS_NON_SECURE) /* 1 */ + +static ALT_STATUS_CODE alt_vregion_mark_pagetable(char * vregion, ALT_MMU_TTB_NS_t security) +{ + if (*vregion == ALT_VREGION_1MIB) + { + *vregion = (int)security; + } + else if (*vregion != (int)security) + { + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +static size_t alt_mmu_va_space_storage_required_internal(const ALT_MMU_MEM_REGION_t* mem_regions, + const size_t num_mem_regions, + char * vregion) +{ + for (int i = 0; i < ALT_MMU_TTB1_SECTION_COUNT; ++i) + { + vregion[i] = ALT_VREGION_1MIB; + } + + // For each region entry, mark the TTB1 as either fault, section, pagetable. + // The total space required is the space required for the TTB1 (16 KiB) + pagetables * (1 KiB) + + for (int i = 0; i < num_mem_regions; ++i) + { + uintptr_t va = (uintptr_t)mem_regions[i].va; + uintptr_t pa = (uintptr_t)mem_regions[i].pa; + uint32_t size = mem_regions[i].size; + ALT_MMU_TTB_NS_t security = mem_regions[i].security; + + // Verify [va] aligns to 4 KiB + if (va & (ALT_MMU_SMALL_PAGE_SIZE - 1)) + { + return 0; + } + + // Verify [pa] aligns to 4 KiB + if (pa & (ALT_MMU_SMALL_PAGE_SIZE - 1)) + { + return 0; + } + + // Verify [size] aligns to 4 KiB + if (size & (ALT_MMU_SMALL_PAGE_SIZE - 1)) + { + return 0; + } + + // Mark the regions at the start of an unaligned 1 MiB as pagetable. + // Align the [va] to 1 MiB and subtract that from the [size] left to describe. + if (va & (ALT_MMU_SECTION_SIZE - 1)) + { + // Pagetables must be either S or NS. If the pagetable was + // previously marked as something different, the regions described + // will not be implementable. + if (alt_vregion_mark_pagetable(&vregion[va >> 20], + security) != ALT_E_SUCCESS) + { + return 0; + } + + uint32_t segment = MIN(ALT_MMU_SECTION_SIZE - (va & (ALT_MMU_SECTION_SIZE - 1)), size); + va += segment; + pa += segment; + size -= segment; + } + + // Skip each 1 MiB aligned segment of size 1 MiB. These regions require + // pagetable if the PA is not 1 MiB aligned. + + // [pa] is not used after this point. + + if (pa & (ALT_MMU_SECTION_SIZE - 1)) + { + // PA is not 1 MiB aligned. Everything must use pagetables. + + while (size >= ALT_MMU_SECTION_SIZE) + { + // Pagetables must be either S or NS. If the pagetable was + // previously marked as something different, the regions described + // will not be implementable. + if (alt_vregion_mark_pagetable(&vregion[va >> 20], + security) != ALT_E_SUCCESS) + { + return 0; + } + + va += ALT_MMU_SECTION_SIZE; + // pa += ALT_MMU_SECTION_SIZE; + size -= ALT_MMU_SECTION_SIZE; + } + } + else + { + // PA is 1 MiB aligned. Sections or supersections can be used. + + while (size >= ALT_MMU_SECTION_SIZE) + { + va += ALT_MMU_SECTION_SIZE; + // pa += ALT_MMU_SECTION_SIZE; + size -= ALT_MMU_SECTION_SIZE; + } + } + + // The remainder should be a 1 MiB aligned segment of less than 1 MiB. Mark that region as pagetable. + if (size) + { + // Pagetables must be either S or NS. If the pagetable was + // previously marked as something different, the regions described + // will not be implementable. + if (alt_vregion_mark_pagetable(&vregion[va >> 20], + security) != ALT_E_SUCCESS) + { + return 0; + } + } + } + + // Calculate the size as 16 KiB (TTB1) + 1 KiB * (TTB2 or the number of pagetables) + size_t reqsize = ALT_MMU_TTB1_SIZE; + + for (int i = 0; i < ALT_MMU_TTB1_SECTION_COUNT; ++i) + { + if (vregion[i] != ALT_VREGION_1MIB) + { + reqsize += ALT_MMU_TTB2_SIZE; + } + } + + return reqsize; +} + +size_t alt_mmu_va_space_storage_required(const ALT_MMU_MEM_REGION_t* mem_regions, + const size_t num_mem_regions) +{ + char vregion[ALT_MMU_TTB1_SECTION_COUNT]; + + return alt_mmu_va_space_storage_required_internal(mem_regions, + num_mem_regions, + vregion); +} + +/* +static inline uint32_t alt_mmu_va_space_gen_fault(void) +{ + return 0; +} +*/ + +static inline uint32_t alt_mmu_va_space_gen_pagetable(uintptr_t pagetable, + const ALT_MMU_MEM_REGION_t * mem) +{ + if (mem->attributes == ALT_MMU_ATTR_FAULT) + { + return 0; + } + + return + ALT_MMU_TTB1_TYPE_SET(0x1) + | ALT_MMU_TTB1_PAGE_TBL_NS_SET(mem->security) + | ALT_MMU_TTB1_PAGE_TBL_DOMAIN_SET(0) + | ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_SET(pagetable >> 10); +} + +static inline uint32_t alt_mmu_va_space_gen_section(uintptr_t pa, + const ALT_MMU_MEM_REGION_t * mem) +{ + if (mem->attributes == ALT_MMU_ATTR_FAULT) + { + return 0; + } + + int tex = (mem->attributes >> 4) & 0x7; + int c = (mem->attributes >> 1) & 0x1; + int b = (mem->attributes >> 0) & 0x1; + + return + ALT_MMU_TTB1_TYPE_SET(0x2) + | ALT_MMU_TTB1_SECTION_B_SET(b) + | ALT_MMU_TTB1_SECTION_C_SET(c) + | ALT_MMU_TTB1_SECTION_XN_SET(mem->execute) + | ALT_MMU_TTB1_SECTION_DOMAIN_SET(0) + | ALT_MMU_TTB1_SECTION_AP_SET(mem->access) + | ALT_MMU_TTB1_SECTION_TEX_SET(tex) + | ALT_MMU_TTB1_SECTION_S_SET(mem->shareable) + | ALT_MMU_TTB1_SECTION_NG_SET(0) + | ALT_MMU_TTB1_SECTION_NS_SET(mem->security) + | ALT_MMU_TTB1_SECTION_BASE_ADDR_SET(pa >> 20); +} + +static inline uint32_t alt_mmu_va_space_gen_supersection(uintptr_t pa, + const ALT_MMU_MEM_REGION_t * mem) +{ + if (mem->attributes == ALT_MMU_ATTR_FAULT) + { + return 0; + } + + int tex = (mem->attributes >> 4) & 0x7; + int c = (mem->attributes >> 1) & 0x1; + int b = (mem->attributes >> 0) & 0x1; + + return + ALT_MMU_TTB1_TYPE_SET(0x2) | (1 << 18) // bit 18 marks section as being super. + | ALT_MMU_TTB1_SUPERSECTION_B_SET(b) + | ALT_MMU_TTB1_SUPERSECTION_C_SET(c) + | ALT_MMU_TTB1_SUPERSECTION_XN_SET(mem->execute) + | ALT_MMU_TTB1_SUPERSECTION_DOMAIN_SET(0) + | ALT_MMU_TTB1_SUPERSECTION_AP_SET(mem->access) + | ALT_MMU_TTB1_SUPERSECTION_TEX_SET(tex) + | ALT_MMU_TTB1_SUPERSECTION_S_SET(mem->shareable) + | ALT_MMU_TTB1_SUPERSECTION_NG_SET(0) + | ALT_MMU_TTB1_SUPERSECTION_NS_SET(mem->security) + | ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_SET(pa >> 24); +} + +static inline uint32_t alt_mmu_va_space_gen_smallpage(uintptr_t pa, + const ALT_MMU_MEM_REGION_t * mem) +{ + if (mem->attributes == ALT_MMU_ATTR_FAULT) + { + return 0; + } + + int tex = (mem->attributes >> 4) & 0x7; + int c = (mem->attributes >> 1) & 0x1; + int b = (mem->attributes >> 0) & 0x1; + + // NS bit (mem->security) is ignored as it is set in TTB1. + + return + ALT_MMU_TTB2_TYPE_SET(0x2) + | ALT_MMU_TTB2_SMALL_PAGE_XN_SET(mem->execute) + | ALT_MMU_TTB2_SMALL_PAGE_B_SET(b) + | ALT_MMU_TTB2_SMALL_PAGE_C_SET(c) + | ALT_MMU_TTB2_SMALL_PAGE_AP_SET(mem->access) + | ALT_MMU_TTB2_SMALL_PAGE_TEX_SET(tex) + | ALT_MMU_TTB2_SMALL_PAGE_S_SET(mem->shareable) + | ALT_MMU_TTB2_SMALL_PAGE_NG_SET(0) + | ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_SET(pa >> 12); +} + +static inline uint32_t alt_mmu_va_space_gen_largepage(uintptr_t pa, + const ALT_MMU_MEM_REGION_t * mem) +{ + if (mem->attributes == ALT_MMU_ATTR_FAULT) + { + return 0; + } + + int tex = (mem->attributes >> 4) & 0x7; + int c = (mem->attributes >> 1) & 0x1; + int b = (mem->attributes >> 0) & 0x1; + + // NS bit (mem->security) is ignored as it is set in TTB1. + + return + ALT_MMU_TTB2_TYPE_SET(0x1) + | ALT_MMU_TTB2_LARGE_PAGE_B_SET(b) + | ALT_MMU_TTB2_LARGE_PAGE_C_SET(c) + | ALT_MMU_TTB2_LARGE_PAGE_AP_SET(mem->access) + | ALT_MMU_TTB2_LARGE_PAGE_S_SET(mem->shareable) + | ALT_MMU_TTB2_LARGE_PAGE_NG_SET(0) + | ALT_MMU_TTB2_LARGE_PAGE_TEX_SET(tex) + | ALT_MMU_TTB2_LARGE_PAGE_XN_SET(mem->execute) + | ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_SET(pa >> 16); +} + +static ALT_STATUS_CODE alt_mmu_ttb2_init(uint32_t * ttb2) +{ + // For TTB2 (page tables), the page table base address in TTB1 is + // bits[31:10]. Thus it must be 2^10 byte aligned or 1 KiB. + // Source: ARMv7-A,R, section B3.5.1. + + if ((uintptr_t)ttb2 & ((1 << 10) - 1)) + { + return ALT_E_BAD_ARG; + } + + memset(ttb2, 0, ALT_MMU_TTB2_SIZE); + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_mmu_va_space_create(uint32_t** ttb1, + const ALT_MMU_MEM_REGION_t* mem_regions, + const size_t num_mem_regions, + alt_mmu_ttb_alloc_t ttb_alloc, + void * ttb_alloc_context) +{ + char vregion[ALT_MMU_TTB1_SECTION_COUNT]; + + size_t reqsize = alt_mmu_va_space_storage_required_internal(mem_regions, + num_mem_regions, + vregion); + if (reqsize == 0) + { + return ALT_E_ERROR; + } + + char * memory = ttb_alloc(reqsize, ttb_alloc_context); + size_t allocated = 0; + + // Verify allocation + + if (memory == NULL) + { + return ALT_E_ERROR; + } + + // Verify alignment + + // For TTBR0, the translation table must be aligned to 2^x bytes, where + // x = (14 - TTBCR.N). Because VA space sets TTBCR.N = 0, x = 14, and the + // table must be aligned to 2^14 or 16 KiB. + // Source: ARMv7-A,R, section B4.1.154. + + // For TTB2 (page tables), the page table base address in TTB1 is + // bits[31:10]. Thus it must be 2^10 byte aligned or 1 KiB. + // Source: ARMv7-A,R, section B3.5.1. + + // The stricter of the two alignment is 16 KiB. + + if ((uintptr_t)memory & ((1 << 14) - 1)) + { + return ALT_E_BAD_ARG; + } + + // "allocate" space for the TTB1. + if (allocated + ALT_MMU_TTB1_SIZE > reqsize) + { + return ALT_E_ERROR; + } + *ttb1 = (uint32_t *)memory; + allocated += ALT_MMU_TTB1_SIZE; + + if (alt_mmu_ttb1_init(*ttb1) != ALT_E_SUCCESS) + { + return ALT_E_ERROR; + } + + // "allocate" space for each pagetable in [vregion] + for (int i = 0; i < ALT_MMU_TTB1_SECTION_COUNT; ++i) + { + if (vregion[i] != ALT_VREGION_1MIB) + { + if (allocated + ALT_MMU_TTB2_SIZE > reqsize) + { + return ALT_E_ERROR; + } + uint32_t * pagetable = (uint32_t *)(memory + allocated); + allocated += ALT_MMU_TTB2_SIZE; + alt_mmu_ttb2_init(pagetable); + + ALT_MMU_MEM_REGION_t mem_region; + mem_region.attributes = ALT_MMU_ATTR_STRONG; // Any non-FAULT will work. + mem_region.security = (ALT_MMU_TTB_NS_t)vregion[i]; + uint32_t desc = alt_mmu_va_space_gen_pagetable((uintptr_t)pagetable, &mem_region); + + (*ttb1)[i] = desc; + } + } + + // The allocated size should match the requested size. If not, this means + // that the regions descriptor changed between calling + // alt_mmu_va_space_storage_required() and alt_mmu_va_space_create(). + if (reqsize != allocated) + { + return ALT_E_ERROR; + } + + // Iterate through all region descriptors + + for (size_t i = 0; i < num_mem_regions; ++i) + { + uintptr_t va = (uintptr_t)mem_regions[i].va; + uintptr_t pa = (uintptr_t)mem_regions[i].pa; + uint32_t size = mem_regions[i].size; + + // Determine the va/pa relative alignment: 4 KiB, 64 KiB, 1 MiB, 16 MiB + + uint32_t alignopt[] = + { + ALT_MMU_SUPERSECTION_SIZE, + ALT_MMU_SECTION_SIZE, + ALT_MMU_LARGE_PAGE_SIZE + }; + + // Relative alignment of [va] and [pa]. + int relalign = ALT_MMU_SMALL_PAGE_SIZE; + + for (int j = 0; j < ARRAY_COUNT(alignopt); ++j) + { + if ( (va & (alignopt[j] - 1)) == + (pa & (alignopt[j] - 1)) ) + { + relalign = alignopt[j]; + break; + } + } + + // Page the 1 MiB unaligned segment of [va]. Areas requiring page tables + // should already have those page tables created previously in this + // function. + if (va & (ALT_MMU_SECTION_SIZE - 1)) + { + // This is the size of the memory segment after paging which will cause the [va] to align to a 1 MiB, + // or up to the size of the region being processed, whichever is smaller. + uint32_t segsize = MIN(ALT_MMU_SECTION_SIZE - (va & (ALT_MMU_SECTION_SIZE - 1)), size); + + if (relalign >= ALT_MMU_LARGE_PAGE_SIZE) + { + // Because of the 64 KiB relative alignment, try to use large pages. + + // Use small pages until [va] is 64KiB aligned. + while (((va & (ALT_MMU_LARGE_PAGE_SIZE - 1)) != 0) && (segsize >= ALT_MMU_SMALL_PAGE_SIZE)) + { + uint32_t desc = alt_mmu_va_space_gen_smallpage(pa, &mem_regions[i]); + + uint32_t * pagetable = (uint32_t *)((*ttb1)[va >> 20] & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK); + uint32_t ptindex = ALT_MMU_PAGE_TABLE_INDEX(va); + + // Detect if an existing non-fault region has already been created. + // We cannot detect if a fault region is requested and a region description is already a fault, + // which it is by default. + if (pagetable[ptindex] != 0) + { + return ALT_E_ERROR; + } + + pagetable[ptindex] = desc; + + va += ALT_MMU_SMALL_PAGE_SIZE; + pa += ALT_MMU_SMALL_PAGE_SIZE; + segsize -= ALT_MMU_SMALL_PAGE_SIZE; + size -= ALT_MMU_SMALL_PAGE_SIZE; + } + + // Use large pages for the rest of the 64 KiB aligned areas. + while (segsize >= ALT_MMU_LARGE_PAGE_SIZE) + { + uint32_t desc = alt_mmu_va_space_gen_largepage(pa, &mem_regions[i]); + + uint32_t * pagetable = (uint32_t *)((*ttb1)[va >> 20] & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK); + uint32_t ptindex = ALT_MMU_PAGE_TABLE_INDEX(va); + + for (int j = 0; j < 16; ++j) + { + if (pagetable[ptindex + j] != 0) + { + return ALT_E_ERROR; + } + + pagetable[ptindex + j] = desc; + } + + va += ALT_MMU_LARGE_PAGE_SIZE; + pa += ALT_MMU_LARGE_PAGE_SIZE; + segsize -= ALT_MMU_LARGE_PAGE_SIZE; + size -= ALT_MMU_LARGE_PAGE_SIZE; + } + + // There is a chance that the segment is so small that it does cause the progress to align to the 1 MiB. + // If this is the case, page out the rest of segsize using small pages, and the remaining size to be 0. + while (segsize >= ALT_MMU_SMALL_PAGE_SIZE) + { + uint32_t desc = alt_mmu_va_space_gen_smallpage(pa, &mem_regions[i]); + + uint32_t * pagetable = (uint32_t *)((*ttb1)[va >> 20] & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK); + uint32_t ptindex = ALT_MMU_PAGE_TABLE_INDEX(va); + + if (pagetable[ptindex] != 0) + { + return ALT_E_ERROR; + } + + pagetable[ptindex] = desc; + + va += ALT_MMU_SMALL_PAGE_SIZE; + pa += ALT_MMU_SMALL_PAGE_SIZE; + segsize -= ALT_MMU_SMALL_PAGE_SIZE; + size -= ALT_MMU_SMALL_PAGE_SIZE; + } + } + else + { + // No large pages possible, Use small pages only. + while (segsize >= ALT_MMU_SMALL_PAGE_SIZE) + { + uint32_t desc = alt_mmu_va_space_gen_smallpage(pa, &mem_regions[i]); + + uint32_t * pagetable = (uint32_t *)((*ttb1)[va >> 20] & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK); + uint32_t ptindex = ALT_MMU_PAGE_TABLE_INDEX(va); + + if (pagetable[ptindex] != 0) + { + return ALT_E_ERROR; + } + + pagetable[ptindex] = desc; + + va += ALT_MMU_SMALL_PAGE_SIZE; + pa += ALT_MMU_SMALL_PAGE_SIZE; + segsize -= ALT_MMU_SMALL_PAGE_SIZE; + size -= ALT_MMU_SMALL_PAGE_SIZE; + } + } + } + + // Page each the larger 1 MiB aligned, 1 MiB sized segments. + + // If [va] and [pa] are relatively 16 MiB aligned and the size remaining + // to be described is greater than 16 MiB, use supersections. + + // If [va] and [pa] are relatively 1 MiB aligned and the size remaining + // to be described is greater than 1 MiB, use sections. + + // Otherwise use pagetables for everything remaining. + + if ( (relalign >= ALT_MMU_SUPERSECTION_SIZE) + && (size >= ALT_MMU_SUPERSECTION_SIZE)) + { + // Attempt to use supersections. This may not always be possible. + + // Use regular sections for the areas before supersections that does not align to 16 MiB + while (((va & (ALT_MMU_SUPERSECTION_SIZE - 1)) != 0) && (size >= ALT_MMU_SECTION_SIZE)) + { + uint32_t desc = alt_mmu_va_space_gen_section(pa, &mem_regions[i]); + + if ((*ttb1)[va >> 20] != 0) + { + return ALT_E_ERROR; + } + + (*ttb1)[va >> 20] = desc; + + va += ALT_MMU_SECTION_SIZE; + pa += ALT_MMU_SECTION_SIZE; + size -= ALT_MMU_SECTION_SIZE; + } + + // Use supersections for the 16 MiB aligned areas + while (size >= ALT_MMU_SUPERSECTION_SIZE) + { + uint32_t desc = alt_mmu_va_space_gen_supersection(pa, &mem_regions[i]); + + for (int j = 0; j < 16; ++j) + { + if ((*ttb1)[(va >> 20) + j] != 0) + { + return ALT_E_ERROR; + } + + (*ttb1)[(va >> 20) + j] = desc; + } + + va += ALT_MMU_SUPERSECTION_SIZE; + pa += ALT_MMU_SUPERSECTION_SIZE; + size -= ALT_MMU_SUPERSECTION_SIZE; + } + + // Use regular sections for the areas after supersections that does not align to 16 MiB. + while (size >= ALT_MMU_SECTION_SIZE) + { + uint32_t desc = alt_mmu_va_space_gen_section(pa, &mem_regions[i]); + + if ((*ttb1)[va >> 20] != 0) + { + return ALT_E_ERROR; + } + + (*ttb1)[va >> 20] = desc; + + va += ALT_MMU_SECTION_SIZE; + pa += ALT_MMU_SECTION_SIZE; + size -= ALT_MMU_SECTION_SIZE; + } + } + else if ( (relalign >= ALT_MMU_SECTION_SIZE) + && (size >= ALT_MMU_SECTION_SIZE)) + { + // No supersection possible. Use regular sections only. + + while (size >= ALT_MMU_SECTION_SIZE) + { + uint32_t desc = alt_mmu_va_space_gen_section(pa, &mem_regions[i]); + + if ((*ttb1)[va >> 20] != 0) + { + return ALT_E_ERROR; + } + + (*ttb1)[va >> 20] = desc; + + va += ALT_MMU_SECTION_SIZE; + pa += ALT_MMU_SECTION_SIZE; + size -= ALT_MMU_SECTION_SIZE; + } + } + + // The remainder should be [va] 1 MiB aligned segment not able to use + // sections or supersections. Mark that region as pagetable. + + // Use large pages if it is suitable. + if ((relalign >= ALT_MMU_LARGE_PAGE_SIZE) && (size >= ALT_MMU_LARGE_PAGE_SIZE)) + { + while (size >= ALT_MMU_LARGE_PAGE_SIZE) + { + uint32_t desc = alt_mmu_va_space_gen_largepage(pa, &mem_regions[i]); + + uint32_t * pagetable = (uint32_t *)((*ttb1)[va >> 20] & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK); + uint32_t ptindex = ALT_MMU_PAGE_TABLE_INDEX(va); + + for (int j = 0; j < 16; ++j) + { + if (pagetable[ptindex + j] != 0) + { + return ALT_E_ERROR; + } + + pagetable[ptindex + j] = desc; + } + + va += ALT_MMU_LARGE_PAGE_SIZE; + pa += ALT_MMU_LARGE_PAGE_SIZE; + size -= ALT_MMU_LARGE_PAGE_SIZE; + } + } + + while (size >= ALT_MMU_SMALL_PAGE_SIZE) + { + uint32_t desc = alt_mmu_va_space_gen_smallpage(pa, &mem_regions[i]); + + uint32_t * pagetable = (uint32_t *)((*ttb1)[va >> 20] & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK); + uint32_t ptindex = ALT_MMU_PAGE_TABLE_INDEX(va); + + if (pagetable[ptindex] != 0) + { + return ALT_E_ERROR; + } + + pagetable[ptindex] = desc; + + va += ALT_MMU_SMALL_PAGE_SIZE; + pa += ALT_MMU_SMALL_PAGE_SIZE; + size -= ALT_MMU_SMALL_PAGE_SIZE; + } + + } // for (size_t i = 0; i < num_mem_regions; ++i) + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_mmu_va_space_enable(const uint32_t * ttb1) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Set TTBCR to use N=0 + if (status == ALT_E_SUCCESS) + { + status = alt_mmu_TTBCR_set(true, + true, + 0); + if (status != ALT_E_SUCCESS) + { + dprintf("DEBUG[MMU:VA]: Failure on line %d.\n", __LINE__); + } + } + + // Set TTBR0 to use ttb1 + + if (status == ALT_E_SUCCESS) + { + status = alt_mmu_TTBR0_set(ttb1); + if (status != ALT_E_SUCCESS) + { + dprintf("DEBUG[MMU:VA]: Failure on line %d.\n", __LINE__); + } + } + + // Configure DACRs to be client domain. + + if (status == ALT_E_SUCCESS) + { + ALT_MMU_DAP_t domain_ap[16]; + for (int i = 0; i < 16; ++i) + { + domain_ap[i] = ALT_MMU_DAP_CLIENT; + } + + status = alt_mmu_DACR_set(domain_ap, 16); + if (status != ALT_E_SUCCESS) + { + dprintf("DEBUG[MMU:VA]: Failure on line %d.\n", __LINE__); + } + } + + // Enable MMU (implicitly invalidates TLBs) + + if (status == ALT_E_SUCCESS) + { + status = alt_mmu_enable(); + if (status != ALT_E_SUCCESS) + { + dprintf("DEBUG[MMU:VA]: Failure on line %d.\n", __LINE__); + } + } + + return status; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_nand.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_nand.c new file mode 100644 index 000000000..ad5c57c42 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_nand.c @@ -0,0 +1,932 @@ +/****************************************************************************** +* +* alt_nand.c - API for the Altera SoC FPGA NAND device. +* +******************************************************************************/ + +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "alt_nand_flash.h" +#include "socal/alt_nand.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_sysmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" +#include "alt_nand_private.h" +//#include "denali_flash_regs.h" +#include +#include +#include + +static int s_nand_is_interrupt_enabled = false; +static uint32_t g_nand_interrup_status_register_poll_counter_limit; +static nand_interrupt_handler_t s_nand_interrupt_handler = NULL; +uint32_t alt_nand_number_blocks_of_plane_get(void); + +static __inline uint32_t alt_nand_compose_map01_cmd_addr(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr); +static __inline uint32_t alt_nand_get_interrupt_status_register_addr(const uint32_t bank); +static __inline uint32_t alt_nand_get_interrupt_enable_register_addr(const uint32_t bank); +static __inline uint32_t alt_nand_get_device_reset_register_bank(const uint32_t bank); + +uint32_t nand_read_register(const uint32_t offset); + +static uint32_t real_table[ALT_HHP_NAND_NUM_OF_BLOCK_TOTAL/32]; +alt_nand_bad_block_table_t nand_bad_block_table = real_table; + +ALT_NAND_MGR_t nand_io = +{ + (ALT_NAND_CFG_raw_t*)ALT_NAND_CFG_ADDR, + (ALT_NAND_PARAM_raw_t*)ALT_NAND_PARAM_ADDR, + (ALT_NAND_STAT_raw_t*)ALT_NAND_STAT_ADDR, + (ALT_NAND_ECC_raw_t*)ALT_NAND_ECC_ADDR, + (ALT_NAND_DMA_raw_t*)ALT_NAND_DMA_ADDR, + (uint32_t *)ALT_NANDDATA_ADDR, /*control_address */ + ALT_CAST(uint32_t *, (ALT_CAST(char *, (ALT_NANDDATA_ADDR)) + 0x10)) +}; + +ALT_NAND_MGR_t * nand = &nand_io; + +FLASH_CHARACTERIZATION_t memory = +{ + /*manufacturer id */ ALT_HHP_NAND_MANUFACTURER_ID, + /*device_id */ ALT_HHP_NAND_DEVICE_ID, + /*device_param_0 */ 0, + /*device_param_1 */ 0, + /*device_param_2 */ 0, + /*page_size */ ALT_HHP_NAND_PAGE_SIZE, + /*spare_size */ ALT_HHP_NAND_SPARE_SIZE, + /*revision */ ALT_HHP_NAND_REVISION, + /*onfi_device_feature */ 0, + /*onfi_optional_commands */ 0, + /*onfi_timing_mode */ 0, + /*onfi_pgm_cache_timing_mode */ 0, + /*onfi_compliant */ 1, + /*onfi_device_no_of_luns */ 0, + /*onfi_device_no_of_blocks_per_lun */ 0, + /*features */ 0, + + /*number_of_planes */ ALT_HHP_NAND_NUMBER_OF_PLANES, + /*pages_per_block */ ALT_HHP_NAND_PAGES_PER_BLOCK, + /*device_width */ ALT_HHP_NAND_DEVICE_WIDTH, + /*block_size */ ALT_HHP_NAND_PAGES_PER_BLOCK * ALT_HHP_NAND_PAGE_SIZE, + /*spare_area_skip_bytes */ ALT_HHP_NAND_SPARE_SKIP, + /*first block of next plane */ ALT_HHP_NAND_FIRST_BLOCK_OF_NEXT_PLANE, + /*page_size_in_32 */ ALT_HHP_NAND_PAGE_SIZE / sizeof(uint32_t), + /*block_shift */ ALT_HHP_NAND_BLOCK_SHIFT, + /*dma_burst_length */ 0, + /*ecc_correct */ ALT_HHP_NAND_ECC_CORRECT, +}; + +FLASH_CHARACTERIZATION_t * flash = &memory; + +ALT_STATUS_CODE alt_nand_flash_init(const bool load_block0_page0, + const bool page_size_512, + alt_nand_flash_custom_init_t custom_init, + void *user_arg) +{ + ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg); + ALT_NAND_PARAM_raw_t * param = (ALT_NAND_PARAM_raw_t *)(nand->param); + ALT_STATUS_CODE ret = ALT_E_SUCCESS; + uint32_t x; + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_NAND_SET_MSK); + alt_nand_set_sysmgr_bootstrap_value( ALT_NAND_BOOTSTRAP_INHIBIT_INIT_DISABLE, + load_block0_page0, + page_size_512, + ALT_NAND_BOOTSTRAP_TWO_ROW_ADDR_CYCLES_DISABLE + ); + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_NAND_SET_MSK); + + g_nand_interrup_status_register_poll_counter_limit = (uint32_t)(-1); + + ret = (*custom_init)(user_arg); + if (ret == ALT_E_RESERVED) // no custom initialization being done + { + alt_nand_reset_bank(0); + } + + // Read flash device characterization + flash->manufacturer_id = alt_read_word(¶m->manufacturer_id); + flash->device_id = alt_read_word(¶m->device_id); + flash->device_param_0 = alt_read_word(¶m->device_param_0); + flash->device_param_1 = alt_read_word(¶m->device_param_1); + flash->device_param_2 = alt_read_word(¶m->device_param_2); + flash->page_size = alt_read_word(&cfg->device_main_area_size); + flash->spare_size = alt_read_word(&cfg->device_spare_area_size); + flash->revision = alt_read_word(¶m->revision); + flash->onfi_device_features = alt_read_word(¶m->onfi_device_features); + flash->onfi_optional_commands = alt_read_word(¶m->onfi_optional_commands); + flash->onfi_timing_mode = alt_read_word(¶m->onfi_timing_mode); + flash->onfi_pgm_cache_timing_mode = alt_read_word(¶m->onfi_pgm_cache_timing_mode); + flash->onfi_compliant = alt_read_word(¶m->onfi_device_no_of_luns) >> 8; + flash->onfi_device_no_of_luns = alt_read_word(¶m->onfi_device_no_of_luns) & 0xff; + x = alt_read_word(¶m->onfi_device_no_of_blocks_per_lun_l); + flash->onfi_device_no_of_blocks_per_lun = (alt_read_word(¶m->onfi_device_no_of_blocks_per_lun_u) << 16) + x; + flash->features = alt_read_word(¶m->features); + x = alt_read_word(&cfg->number_of_planes); + switch (x) + { + case 0: + flash->number_of_planes = 1; + break; + case 1: + flash->number_of_planes = 2; + break; + case 3: + flash->number_of_planes = 4; + break; + case 7: + flash->number_of_planes = 4; + break; + default: + flash->number_of_planes = 1; + break; + } + flash->pages_per_block = alt_read_word(&cfg->pages_per_block); + + // Device Width register content should automatically update SystemManager:NandGrp:BootStrap:page512 or page512x16 bit + flash->device_width = alt_read_word(&cfg->device_width); + + // Set the skip bytes and then read back the result. + alt_write_word(&cfg->spare_area_skip_bytes, flash->spare_area_skip_bytes); + flash->spare_area_skip_bytes = alt_read_word(&cfg->spare_area_skip_bytes); + flash->block_size = flash->pages_per_block * flash->page_size; + + flash->first_block_of_next_plane = alt_read_word(&cfg->first_block_of_next_plane); + // Set flash config based on read config + flash->page_size_32 = flash->page_size / sizeof(uint32_t); + + flash->page_shift = ffs32(flash->page_size); + flash->block_shift = ffs32(flash->pages_per_block); + + alt_nand_rb_pin_mode_clear(ALT_NAND_CFG_RB_PIN_END_BANK0_SET_MSK); + alt_nand_flash_ecc_disable(); + alt_write_word(&cfg->first_block_of_next_plane,alt_nand_number_blocks_of_plane_get()); + flash->first_block_of_next_plane = alt_read_word(&cfg->first_block_of_next_plane); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_nand_flash_uninit(void) +{ + alt_nand_flash_ecc_disable(); + alt_nand_dma_set_enabled( false ); + return ALT_E_SUCCESS; +} + +#define ALT_NAND_INVALID_FLASH_ADDR 0xffffffff + +uint32_t alt_nand_block_address_get(const uint32_t addr) +{ + return addr >> (flash->block_shift + flash->page_shift); +} + +uint32_t alt_nand_page_address_get(const uint32_t addr) +{ + return addr >> flash->page_shift & ((1 << flash->block_shift) - 1); +} + +uint32_t alt_nand_flash_addr_compose(const uint32_t block_num, + const uint32_t page_num) +{ + return (block_num << (flash->block_shift + flash->page_shift)) + (page_num << flash->page_shift); +} + +ALT_STATUS_CODE alt_nand_flash_block_erase(const uint32_t block_addr, + alt_nand_callback_t completion_callback, + void *completion_arg) +{ + int32_t ret = ALT_E_SUCCESS; + int32_t res = -1; + uint32_t bank = alt_nand_bank_get(); + const uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr( bank ); + const uint32_t addr = alt_nand_compose_map10_cmd_addr( bank, block_addr, 0 ); + + alt_write_word(interrup_status_register, ALT_HHP_UINT32_MASK ); + + alt_nand_write_indirect( addr, ALT_HHP_NAND_10_OP_ERASE_BLOCK ); + + res = alt_nand_poll_for_interrupt_status_register(interrup_status_register, + ALT_NAND_INT_STATUS_TIME_OUT | + ALT_NAND_INT_STATUS_ERASE_COMP | + ALT_NAND_INT_STATUS_ERASE_FAIL); + + if (!(res & ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET_MSK)) + { + //printf("FAIL: erasing not complete. (%08lX, %ld)\n", res, block_addr); + ret = ALT_E_ERROR; + } + + return ret; +} + +ALT_STATUS_CODE alt_nand_flash_page_read(const uint32_t page_addr, + const uint32_t num_pages, + void *dest, + const uint32_t dest_size) +{ + // currently only one page + uint32_t bank = alt_nand_bank_get(); + uint32_t page = alt_nand_page_address_get(page_addr); + uint32_t block = alt_nand_block_address_get(page_addr); + + return alt_nand_full_page_read_with_map10( bank, block, page, (uint32_t *)dest); +} + +ALT_STATUS_CODE alt_nand_flash_page_write(const uint32_t page_addr, + const uint32_t num_pages, + const void *src, + const uint32_t src_size) +{ + // currently only one page + uint32_t bank = alt_nand_bank_get(); + uint32_t page = alt_nand_page_address_get(page_addr); + uint32_t block = alt_nand_block_address_get(page_addr); + + return alt_nand_full_page_write_with_map10( bank, block, page, (uint32_t *)src); +} + +ALT_STATUS_CODE alt_nand_flash_page_dma_read(const uint32_t page_addr, + const uint32_t num_pages, + void *dest, + const uint32_t dest_size, + alt_nand_callback_t completion_callback, + void *completion_arg) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t mem_addr = page_addr; + uint32_t dest_addr = (uint32_t)dest; + uint32_t buff_size = dest_size; + + uint32_t bank = alt_nand_bank_get(); + uint32_t page; + uint32_t block; + + for (int i = 0; (i < num_pages) && (buff_size >= flash->page_size); i++) { + + page = alt_nand_page_address_get(mem_addr); + block = alt_nand_block_address_get(mem_addr); + + status = alt_nand_dma_page_read(bank, block, page, dest_addr); + if (status == ALT_E_SUCCESS) + { + mem_addr += flash->page_size; + dest_addr += flash->page_size; + buff_size -= flash->page_size; + } + else + break; + } + + if (status == ALT_E_SUCCESS) + { + (*completion_callback)(status, completion_arg); + } + + return status; +} + +ALT_STATUS_CODE alt_nand_flash_page_dma_write(const uint32_t page_addr, + const uint32_t num_pages, + const void *src, + const uint32_t src_size, + alt_nand_callback_t completion_callback, + void *completion_arg) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t mem_addr = page_addr; + uint32_t src_addr = (uint32_t)src; + uint32_t buff_size = src_size; + + uint32_t bank = alt_nand_bank_get(); + uint32_t page; + uint32_t block; + + for (int i = 0; (i < num_pages) && (buff_size >= flash->page_size); i++) { + + page = alt_nand_page_address_get(mem_addr); + block = alt_nand_block_address_get(mem_addr); + + status = alt_nand_dma_page_write(bank, block, page, src_addr); + if (status == ALT_E_SUCCESS) + { + mem_addr += flash->page_size; + src_addr += flash->page_size; + buff_size -= flash->page_size; + } + else + break; + } + + if (status == ALT_E_SUCCESS) + { + (*completion_callback)(status, completion_arg); + } + + return status; +} + +ALT_STATUS_CODE alt_nand_flash_ecc_enable(const ALT_NAND_ECC_CORRECTION_t ecc_correction) +{ + ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg); + alt_setbits_word(&cfg->ecc_enable, ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_nand_flash_ecc_disable(void) +{ + ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg); + alt_clrbits_word(&cfg->ecc_enable, ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_nand_flash_ecc_status_get(ALT_NAND_FLASH_ECC_STATUS_t *ecc_status) +{ + ALT_NAND_ECC_raw_t * ecc = (ALT_NAND_ECC_raw_t *)(nand->ecc); + uint32_t status; + + status = alt_read_word(&ecc->ECCCorInfo_b01); + ecc_status->corrected_errors[0] = (status & ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB; + ecc_status->corrected_errors[1] = (status & ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB; + ecc_status->uncorrected_error[0] = (status & ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB; + ecc_status->uncorrected_error[1] = (status & ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB; + status = alt_read_word(&ecc->ECCCorInfo_b23); + ecc_status->corrected_errors[2] = (status & ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB; + ecc_status->corrected_errors[3] = (status & ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB; + ecc_status->uncorrected_error[2] = (status & ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB; + ecc_status->uncorrected_error[3] = (status & ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB; + return ALT_E_SUCCESS; +} + +uint32_t alt_nand_int_status_get(void) +{ + uint32_t bank = alt_nand_bank_get(); + uint32_t reg = alt_nand_get_interrupt_status_register_addr(bank); + return alt_read_word(reg); +} + +ALT_STATUS_CODE alt_nand_int_clear(const uint32_t mask) +{ + uint32_t bank = alt_nand_bank_get(); + uint32_t reg = alt_nand_get_interrupt_status_register_addr(bank); + alt_setbits_word(reg, mask); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_nand_int_disable(const uint32_t mask) +{ + uint32_t bank = alt_nand_bank_get(); + uint32_t reg = alt_nand_get_interrupt_enable_register_addr(bank); + alt_clrbits_word(reg, mask); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_nand_int_enable(const uint32_t mask) +{ + uint32_t bank = alt_nand_bank_get(); + uint32_t reg = alt_nand_get_interrupt_enable_register_addr(bank); + alt_setbits_word(reg, mask); + return ALT_E_SUCCESS; +} + +uint32_t alt_nand_num_planes_get(void) +{ + return flash->number_of_planes; +} + +uint32_t alt_nand_number_blocks_of_plane_get(void) +{ + return (flash->onfi_device_no_of_blocks_per_lun / flash->number_of_planes); +} + +uint32_t alt_nand_first_block_of_next_plane(void) +{ + return flash->first_block_of_next_plane; +} + +uint32_t alt_nand_num_blocks_get(void) +{ + return (alt_nand_num_planes_get() * alt_nand_number_blocks_of_plane_get()) ; +} + +uint32_t alt_nand_num_pages_per_block_get(void) +{ + return flash->pages_per_block; +} + +uint32_t alt_nand_sector_size_get(void) +{ + return ALT_HHP_NAND_SECTOR_SIZE; +} + +uint32_t alt_nand_spare_size_get(void) +{ + return flash->spare_size; +} + +bool alt_nand_block_is_bad(const uint32_t block_addr) +{ + return false; +} + +ALT_STATUS_CODE alt_nand_bad_block_table_get(alt_nand_bad_block_table_t bad_block_table, + const uint32_t bad_block_table_len) +{ + alt_nand_callback_t dma_callback = &alt_nand_dma_page_callback; + uint32_t completion_arg = 0; + uint32_t total_blocks = (flash->onfi_device_no_of_luns * flash->onfi_device_no_of_blocks_per_lun); + uint32_t addr = (total_blocks - 1) << (flash->block_shift + flash->page_shift); // highest block is reseved for bad block table + uint32_t buff[ALT_HHP_NAND_PAGE_SIZE]; + + alt_nand_flash_page_dma_read( addr, 1, buff, sizeof(buff), dma_callback, &completion_arg); + for (int i = 0; i cfg); + alt_setbits_word(&cfg->rb_pin_enabled, mask); +} + +void alt_nand_rb_pin_mode_clear(uint32_t mask) +{ + ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg); + alt_clrbits_word(&cfg->rb_pin_enabled, mask); +} + +void alt_nand_reset_bank(uint32_t bank) +{ + ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg); + + uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr(bank); + uint32_t device_reset_bank = alt_nand_get_device_reset_register_bank(bank); + + + // Write on clear of all interrupt status + alt_write_word(interrup_status_register, ALT_HHP_UINT32_MASK); + + // Controller sends a RESET command to device + alt_setbits_word(&cfg->device_reset, device_reset_bank); + + alt_nand_poll_for_interrupt_status_register(interrup_status_register, ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET_MSK); + + // Write on clear of all interrupt status + alt_write_word(interrup_status_register, ALT_HHP_UINT32_MASK); +} + + + +/* + * Count the consecutive zero bits (trailing) on the right in parallel + * + * Some bit fiddleing stuff. + * From... http://graphics.stanford.edu/~seander/bithacks.html + */ +uint32_t ffs32(uint32_t v) +{ + uint32_t r = 0; + do + { + if(v == 0) + break; + + if(v & 0xFFFF0000){v >>= 16;r |= 16;} + if(v & 0x0000FF00){v >>= 8;r |= 8;} + if(v & 0x000000F0){v >>= 4;r |= 4;} + if(v & 0x0000000C){v >>= 2;r |= 2;} + if(v & 0x00000002){ ;r |= 1;} + } while(0); + + return(r); +} + +uint32_t alt_nand_poll_for_interrupt_status_register(uint32_t interrup_status_register, uint32_t interrup_status_mask ) +{ + uint32_t ret; + uint32_t i = 0; + + if ( !s_nand_is_interrupt_enabled ) + { + ret = alt_read_word( interrup_status_register ); + while( !( ret & (interrup_status_mask | ALT_NAND_INT_STATUS_UNSUP_CMD ) ) ) + { + ret = alt_read_word( interrup_status_register ); + //printf("->interrupt status reg = %08lX\n", ret); + if ( ++i == g_nand_interrup_status_register_poll_counter_limit ) + { + break; + } + } + + if ( ret & ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK ) + { + //printf( "Warning: Unsupported CMD interrupt INTR_STATUS_UNSUP_CMD is raised!!!!\n" ); + } + } + else + { + ret = s_nand_interrupt_handler( interrup_status_register, interrup_status_mask ); + } + + return ret; +} + + +int32_t alt_nand_full_page_read_with_map10(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t *buffer ) +{ + int32_t ret = ALT_E_SUCCESS; + int32_t res = -1; + const uint32_t PAGES_TO_READ = 1; // NOTE: Only 2 bits wide + const uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr( bank ); + const uint32_t addr = alt_nand_compose_map10_cmd_addr( bank, block_addr, page_addr ); + + alt_write_word( interrup_status_register, ALT_HHP_UINT32_MASK ); + + // Sets up a pipeline read-ahead of for a read (0x2001) + alt_nand_write_indirect( addr, ALT_HHP_NAND_10_OP_READ_PIPE | PAGES_TO_READ ); + res = alt_nand_poll_for_interrupt_status_register( interrup_status_register, + ALT_NAND_INT_STATUS_TIME_OUT | + ALT_NAND_INT_STATUS_LOAD_COMP ); + + if((res & ALT_NAND_INT_STATUS_LOAD_COMP) != 0) + { + alt_nand_full_page_read_with_map10_post_read_with_map01( bank, block_addr, page_addr, buffer); + } + else + { + //printf("FAIL: Timeout loading NAND page. (%08lX,%ld,%ld)\n", res, bank, page_addr); + ret = ALT_E_ERROR; + } + + return ret; +} + +uint32_t alt_nand_get_device_reset_register_bank(const uint32_t bank) +{ + uint32_t ret=0; + + switch( bank ) + { + case 0: + ret = ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK; + break; + + case 1: + ret = ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK; + break; + + case 2: + ret = ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK; + break; + + case 3: + ret = ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK; + break; + + default: + // info_assert(0, "Do not support more than 4 banks"); + break; + } + + return ret; +} + +uint32_t alt_nand_get_interrupt_status_register_addr(const uint32_t bank) +{ + ALT_NAND_STAT_raw_t * stat = (ALT_NAND_STAT_raw_t *)(nand->stat); + uint32_t ret=0; + + switch( bank ) + { + case 0: + ret = (uint32_t)(&stat->intr_status0); + break; + + case 1: + ret = (uint32_t)(&stat->intr_status1); + break; + + case 2: + ret = (uint32_t)(&stat->intr_status2); + break; + + case 3: + ret = (uint32_t)(&stat->intr_status3); + break; + + default: + // info_assert(0, "Do not support more than 4 banks"); + break; + } + + return ret; +} + +uint32_t alt_nand_get_interrupt_enable_register_addr(uint32_t bank) +{ + uint32_t interrup_enable_register=0; + + ALT_NAND_STAT_raw_t * stat = (ALT_NAND_STAT_raw_t *)(nand->stat); + + switch( bank ) + { + case 0: + interrup_enable_register = (uint32_t)(&stat->intr_en0); + //printf("interrupt status register: %08lX \n", interrup_enable_register); + break; + + case 1: + interrup_enable_register = (uint32_t)(&stat->intr_en1); + break; + + case 2: + interrup_enable_register = (uint32_t)(&stat->intr_en2); + break; + + case 3: + interrup_enable_register = (uint32_t)(&stat->intr_en3); + break; + + default: + // info_assert(0, "Do not support more than 4 banks"); + break; + } + + return interrup_enable_register; +} + +uint32_t alt_nand_compose_map01_cmd_addr(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr) +{ + const uint32_t BANK_MASK = 0x3; + const uint32_t BLOCK_ADDR_MASK = (1 << (23 - flash->block_shift + 1)) - 1; + const uint32_t PAGE_ADDR_MASK = (1 << flash->block_shift) - 1; + + const uint32_t ret = ALT_HHP_NAND_MODE_01 | + ((bank & BANK_MASK) << ALT_HHP_NAND_ADDR_MAP_BANK_SEL_LSB_INDEX) | + ((block_addr & BLOCK_ADDR_MASK) << flash->block_shift) | + (page_addr & PAGE_ADDR_MASK); + + return ret; +} + +uint32_t alt_nand_compose_map10_cmd_addr(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr) +{ + const uint32_t BANK_MASK = 0x3; + const uint32_t BLOCK_ADDR_MASK = (1 << (23 - flash->block_shift + 1)) - 1; + const uint32_t PAGE_ADDR_MASK = (1 << flash->block_shift) - 1; + + const uint32_t ret = ALT_HHP_NAND_MODE_10 | + ((bank & BANK_MASK) << ALT_HHP_NAND_ADDR_MAP_BANK_SEL_LSB_INDEX) | + ((block_addr & BLOCK_ADDR_MASK) << flash->block_shift) | + (page_addr & PAGE_ADDR_MASK); + + return ret; +} + +void alt_nand_write_indirect(const uint32_t address, const uint32_t value) +{ + alt_write_word(nand->ctrl_addr, address); + alt_write_word(nand->data_addr, value); +} + +uint32_t alt_nand_read_indirect(const uint32_t address) +{ + alt_write_word(nand->ctrl_addr, address); + return alt_read_word(nand->data_addr); +} + +void alt_nand_full_page_read_with_map10_post_read_with_map01(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t *buffer) +{ + const uint32_t addr = alt_nand_compose_map01_cmd_addr( bank, block_addr, page_addr ); + uint32_t *cur = buffer; + uint32_t i; + + for( i = 0; i < flash->page_size_32; ++i ) + { + *cur++ = alt_nand_read_indirect( addr ); + } +} + +int32_t alt_nand_full_page_write_with_map10(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t *buffer) +{ + int32_t ret = 0; + int32_t res = -1; + const uint32_t PAGES_TO_READ = 1; // NOTE: Only 2 bits wide + const uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr( bank ); + const uint32_t addr = alt_nand_compose_map10_cmd_addr( bank, block_addr, page_addr ); + + alt_write_word( interrup_status_register, ALT_HHP_UINT32_MASK ); + + // Sets up a pipeline read-ahead of “01” pages.“W” = 0 for a read (0x2001) + alt_nand_write_indirect( addr, ALT_HHP_NAND_10_OP_WRITE_PIPE | PAGES_TO_READ ); + +// +// don't forget this one, it is a hardware bug +// + for (int i = 0; i < 10000; i++) ; + + // Temporarily disable status check as RTL doesn't seem to raise any flag. + // But, it works. + //res = alt_nand_poll_for_interrupt_status_register( interrup_status_register, INTR_STATUS0__TIME_OUT | INTR_STATUS0__PIPE_CPYBCK_CMD_COMP ); + res = ALT_NAND_INT_STATUS_PIPE_CPYBCK_CMD_COMP; + if((res & ALT_NAND_INT_STATUS_PIPE_CPYBCK_CMD_COMP) != 0) + { + alt_nand_full_page_write_with_map10_post_write_with_map01( bank, block_addr, page_addr, buffer ); + } + else + { + //printf("FAIL: Timeout loading NAND page. (%08lX,%ld,%ld)\n", res, bank, page_addr); + ret = 1; + } + + return ret; +} + +void alt_nand_full_page_write_with_map10_post_write_with_map01(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t *buffer) +{ + const uint32_t addr = alt_nand_compose_map01_cmd_addr( bank, block_addr, page_addr ); + const uint32_t *cur = buffer; + uint32_t i; + + for( i = 0; i < flash->page_size_32; ++i ) + { + alt_nand_write_indirect( addr, *cur++ ); + } +} + + +void alt_nand_set_sysmgr_bootstrap_value( uint32_t bootstrp_inhibit_init, + uint32_t bootstrp_inhibit_b0p0_load, + uint32_t bootstrp_512b_device, + uint32_t bootstrp_two_row_addr_cycles) +{ + uint32_t settings = ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(bootstrp_inhibit_init) | + ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(bootstrp_512b_device) | + ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(bootstrp_inhibit_b0p0_load) | + ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(bootstrp_two_row_addr_cycles); + + alt_write_word(ALT_SYSMGR_NAND_BOOTSTRAP_ADDR, settings); +} + + +uint32_t alt_nand_bank_get(void) +{ + // on SOC, only bank 0 of physical memory is connected + return ALT_NAND_FLASH_MEM_BANK_0; +} + + +int32_t alt_nand_dma_page_write( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t mem_addr ) +{ + int32_t ret = 0; + uint32_t res; + const uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr( bank ); + + alt_write_word( interrup_status_register, ALT_HHP_UINT32_MASK ); + + alt_nand_dma_set_enabled( true ); + + alt_nand_dma_write_cmd_structure( bank, block_addr, page_addr, 1, mem_addr, false, 64); + + res = alt_nand_poll_for_interrupt_status_register( interrup_status_register, + ALT_NAND_INT_STATUS_DMA_CMD_COMP | + ALT_NAND_INT_STATUS_PROGRAM_FAIL | + ALT_NAND_INT_STATUS_LOCKED_BLK ); + // 10.8. Order of interrupt status bits assertion 8. + + if ( !(res & ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK) ) + { + //printf( "Error: DMA command is incomplete: 0x%lx\n", res ); + ret = res; + } + + alt_nand_dma_set_enabled( false ); + + return ret; +} + +int32_t alt_nand_dma_page_read( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t mem_addr ) +{ + int32_t ret = 0; + uint32_t res; + const uint32_t interrup_status_register = alt_nand_get_interrupt_status_register_addr( bank ); + + alt_write_word( interrup_status_register, ALT_HHP_UINT32_MASK ); + + alt_nand_dma_set_enabled( true ); + + alt_nand_dma_write_cmd_structure( bank, block_addr, page_addr, 1, mem_addr, true, 64 ); + + res = alt_nand_poll_for_interrupt_status_register( interrup_status_register, + ALT_NAND_INT_STATUS_DMA_CMD_COMP | + ALT_NAND_INT_STATUS_ECC_UNCOR_ERR); + // 10.8. Order of interrupt status bits assertion 9. + + if ( !(res & ALT_NAND_INT_STATUS_DMA_CMD_COMP) ) + { + //printf( "Error: DMA command is incomplete: 0x%lx\n", res ); + ret = res; + } + + alt_nand_dma_set_enabled( false ); + + return ret; +} + +void alt_nand_dma_set_enabled( int32_t is_enabled ) +{ + ALT_NAND_DMA_raw_t * dma = (ALT_NAND_DMA_raw_t *)(nand->dma); + alt_write_word(&dma->dma_enable, ( is_enabled ? ALT_NAND_DMA_DMA_EN_FLAG_SET_MSK : 0 ) ); + alt_read_word( &dma->dma_enable); +} + +void alt_nand_dma_write_cmd_structure( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t page_count, uint64_t mem_addr, int32_t is_read_op, const uint32_t burst_len ) +{ + const uint32_t MODE_BANK_MASK = 0xFF000000; + uint32_t addr = alt_nand_compose_map10_cmd_addr( bank, block_addr, page_addr ); + + // Transaction 1 + // Table 7.2. Address Encoding + // Table 7.3. Data + alt_nand_write_indirect( addr, 0x2000 | (is_read_op ? 0x0 : 0x100) | page_count); + + // Transaction 2 + // Table 7.4. Address Encoding + // Table 7.5. Data + addr &= MODE_BANK_MASK; + addr |= ((uint16_t)(mem_addr >> 16) << 8); + alt_nand_write_indirect( addr, 0x2200 ); + + // Transaction 3 + // Table 7.6. Address Encoding + // Table 7.7. Data + addr &= MODE_BANK_MASK; + addr |= ((uint16_t)mem_addr << 8); + alt_nand_write_indirect( addr, 0x2300 ); + + // Transaction 4 + // Table 7.8. Address Encoding + // Table 7.9. Data + addr &= MODE_BANK_MASK; + addr |= 0x10000 | burst_len << 8; // Enable INTR_STATUS__DMA_CMD_COMP always. + alt_nand_write_indirect( addr, 0x2400); +} + + +ALT_STATUS_CODE alt_nand_flash_init_manual(void *user_arg) +{ + //printf("Entered Custom Init Routine for NAND.\n"); + return ALT_E_RESERVED; +} + +void alt_nand_erase_block_callback(ALT_STATUS_CODE status, void *callback_arg) +{ + //printf("NAND Block Erase Callback is successful.\n"); + return; +} + +void alt_nand_dma_page_callback(ALT_STATUS_CODE status, void *callback_arg) +{ + //printf("NAND DMA read Callback is successful.\n"); + return; +} + +uint32_t nand_read_register(const uint32_t offset) +{ + return alt_read_word(&nand->cfg + offset); +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_qspi.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_qspi.c new file mode 100644 index 000000000..7c5f331fa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_qspi.c @@ -0,0 +1,2619 @@ +/****************************************************************************** +* +* alt_qspi.c - API for the Altera SoC FPGA QSPI device. +* +******************************************************************************/ + +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include +#include +#include +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "alt_qspi.h" +#include "alt_qspi_private.h" +#include "socal/alt_qspi.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_sysmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" + +///// + +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +#define dprintf(...) +// #define dprintf printf + +///// + +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + +// qspi_clk operating frequency range. +#define ALT_QSPI_CLK_FREQ_MIN ((alt_freq_t)0) +#define ALT_QSPI_CLK_FREQ_MAX ((alt_freq_t)432000000) + +// The set of all valid QSPI controller interrupt status mask values. +#define ALT_QSPI_INT_STATUS_ALL ( \ + ALT_QSPI_INT_STATUS_MODE_FAIL | \ + ALT_QSPI_INT_STATUS_UFL | \ + ALT_QSPI_INT_STATUS_IDAC_OP_COMPLETE | \ + ALT_QSPI_INT_STATUS_IDAC_OP_REJECT | \ + ALT_QSPI_INT_STATUS_WR_PROT_VIOL | \ + ALT_QSPI_INT_STATUS_ILL_AHB_ACCESS | \ + ALT_QSPI_INT_STATUS_IDAC_WTRMK_TRIG | \ + ALT_QSPI_INT_STATUS_RX_OVF | \ + ALT_QSPI_INT_STATUS_TX_FIFO_NOT_FULL | \ + ALT_QSPI_INT_STATUS_TX_FIFO_FULL | \ + ALT_QSPI_INT_STATUS_RX_FIFO_NOT_EMPTY | \ + ALT_QSPI_INT_STATUS_RX_FIFO_FULL | \ + ALT_QSPI_INT_STATUS_IDAC_RD_FULL \ + ) + +static uint32_t qspi_device_size = 0; + +///// + +static ALT_STATUS_CODE alt_qspi_device_status(uint32_t * status) +{ + // Read flag status register through STIG + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_RDSR, 0, 1, status, 10000); +} + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +static ALT_STATUS_CODE alt_qspi_N25Q_device_flag(uint32_t * flagsr) +{ + if (qspi_device_size < 0x4000000) + { + return ALT_E_SUCCESS; + } + + // Read flag status register through STIG + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_RDFLGSR, 0, 1, flagsr, 10000); +} + +// NOTE: This must be called after QSPI has been enabled. Communications with +// the device will not happen until QSPI is enabled. +static inline ALT_STATUS_CODE alt_qspi_N25Q_enable(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Reset the volatile memory on the N25Q + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_RESET_EN, 0, 10000); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_RESET_MEM, 0, 10000); + } + + ///// + + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_DEV_INST_CONFIG_t cfg = + { + .op_code = ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO, + .inst_type = ALT_QSPI_MODE_SINGLE, // RDID does not support QUAD. + .addr_xfer_type = ALT_QSPI_MODE_QUAD, + .data_xfer_type = ALT_QSPI_MODE_QUAD, + .dummy_cycles = 10 + }; + + status = alt_qspi_device_read_config_set(&cfg); + } + +/* + // CASE 157096: Investigate using QUAD for writes. + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_DEV_INST_CONFIG_t cfg = + { + .op_code = ALT_QSPI_STIG_OPCODE_PP, + .inst_type = ALT_QSPI_MODE_SINGLE, + .addr_xfer_type = ALT_QSPI_MODE_QUAD, + .data_xfer_type = ALT_QSPI_MODE_QUAD, + .dummy_cycles = 0 + }; + + status = alt_qspi_device_write_config_set(&cfg); + } +*/ + + return status; +} + +static ALT_STATUS_CODE alt_qspi_N25Q_flag_wait_for_program(uint32_t timeout) +{ + // The flag status register is only available on the 512 Mib and 1 Gib + // (64 MiB and 128 MiB) Micron parts. + if (qspi_device_size < 0x4000000) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t time_out = timeout; + uint32_t stat = 0; + bool infinite = (timeout == ALT_QSPI_TIMEOUT_INFINITE); + + do + { + status = alt_qspi_device_status(&stat); + if (status != ALT_E_SUCCESS) + { + break; + } + if (!ALT_QSPI_STIG_SR_BUSY_GET(stat)) + { + break; + } + } + while (time_out-- || infinite); + + if (time_out == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + uint32_t flagsr = 0; + + do + { + status = alt_qspi_N25Q_device_flag(&flagsr); + if (status != ALT_E_SUCCESS) + { + break; + } + if (ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(flagsr)) + { + break; + } + } + while (timeout-- || infinite); + + if (timeout == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + if (ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(flagsr)) + { + status = ALT_E_ERROR; + } + } + } + return status; +} + +static ALT_STATUS_CODE alt_qspi_N25Q_flag_wait_for_erase(uint32_t timeout) +{ + // The flag status register is only available on the 512 Mib and 1 Gib + // (64 MiB and 128 MiB) Micron parts. + if (qspi_device_size < 0x4000000) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t time_out = timeout; + uint32_t stat = 0; + bool infinite = (timeout == ALT_QSPI_TIMEOUT_INFINITE); + + do + { + status = alt_qspi_device_status(&stat); + if (status != ALT_E_SUCCESS) + { + break; + } + if (!ALT_QSPI_STIG_SR_BUSY_GET(stat)) + { + break; + } + } + while (time_out-- || infinite); + + if (time_out == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + + uint32_t flagsr = 0; + + do + { + status = alt_qspi_N25Q_device_flag(&flagsr); + if (status != ALT_E_SUCCESS) + { + break; + } + if (ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(flagsr)) + { + break; + } + } + while (timeout-- || infinite); + + if (timeout == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + if (status == ALT_E_SUCCESS) + { + if (ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(flagsr)) + { + status = ALT_E_ERROR; + } + } + } + + return status; +} +#endif + +// +// A helper function which converts a ns interval into a delay interval for a given MHz. +// The +999 is there to round up the result. +// +static inline int alt_qspi_ns_to_multiplier(int ns, int mhz) +{ + return ((ns * mhz) + 999) / 1000; +} + +ALT_STATUS_CODE alt_qspi_init(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + alt_freq_t qspi_clk_freq = 0; + + // Validate QSPI module input clocks. + // - pclk - l4_mp_clk + // - hclk - l4_mp_clk + // - ref_clk - qspi_clk + + // Check and validate the QSPI ref_clk which is connected to the HPS qspi_clk. + if (status == ALT_E_SUCCESS) + { + if (alt_clk_is_enabled(ALT_CLK_QSPI) != ALT_E_TRUE) + { + status = ALT_E_BAD_CLK; + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_clk_freq_get(ALT_CLK_QSPI, &qspi_clk_freq); + if (status == ALT_E_SUCCESS) + { + if (qspi_clk_freq > ALT_QSPI_CLK_FREQ_MAX) + { + return ALT_E_BAD_CLK; + } + } + } + + int qspi_clk_mhz = qspi_clk_freq / 1000000; + + ///// + + // Take QSPI controller out of reset. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_QSPI_SET_MSK); + + ///// + + // Configure the device timing + + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_TIMING_CONFIG_t timing_cfg = + { + .clk_phase = (ALT_QSPI_CLK_PHASE_t)ALT_QSPI_CFG_SELCLKPHASE_RESET, + .clk_pol = (ALT_QSPI_CLK_POLARITY_t)ALT_QSPI_CFG_SELCLKPOL_RESET, + .cs_da = alt_qspi_ns_to_multiplier(ALT_QSPI_TSHSL_NS_DEF, qspi_clk_mhz), + .cs_dads = alt_qspi_ns_to_multiplier(ALT_QSPI_TSD2D_NS_DEF, qspi_clk_mhz), + .cs_eot = alt_qspi_ns_to_multiplier(ALT_QSPI_TCHSH_NS_DEF, qspi_clk_mhz), + .cs_sot = alt_qspi_ns_to_multiplier(ALT_QSPI_TSLCH_NS_DEF, qspi_clk_mhz), + .rd_datacap = 1 + }; + + dprintf("DEBUG[QSPI]: cs_da = %" PRIu32 ".\n", timing_cfg.cs_da); + dprintf("DEBUG[QSPI]: cs_dads = %" PRIu32 ".\n", timing_cfg.cs_dads); + dprintf("DEBUG[QSPI]: cs_eot = %" PRIu32 ".\n", timing_cfg.cs_eot); + dprintf("DEBUG[QSPI]: cs_sot = %" PRIu32 ".\n", timing_cfg.cs_sot); + + status = alt_qspi_timing_config_set(&timing_cfg); + } + + ///// + + // Configure the remap address register, no remap + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_ahb_remap_address_set(0); + } + + // Configure the interrupt mask register, disabled all first + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_int_disable(ALT_QSPI_INT_STATUS_ALL); + } + + // Configure the baud rate divisor + // CASE 157095: Investigate using 108 MHz, and tweaking the rd_datacap param. + + if (status == ALT_E_SUCCESS) + { + uint32_t device_sclk_mhz = 54; + uint32_t div_actual = (qspi_clk_mhz + (device_sclk_mhz - 1)) / device_sclk_mhz; + dprintf("DEBUG[QSPI]: div_actual = %" PRIu32 ".\n", div_actual); + + ALT_QSPI_BAUD_DIV_t div_bits = (ALT_QSPI_BAUD_DIV_t)(((div_actual + 1) / 2) - 1); + status = alt_qspi_baud_rate_div_set(div_bits); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_uninit(void) +{ + // Put QSPI controller into reset. + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_QSPI_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_disable(void) +{ + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_enable(void) +{ + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_EN_SET_MSK); + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + ///// + + // Device specific configuration + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_enable(); + } +#endif + + uint32_t rdid = 0; + + // Query device capabilities + // This requires QSPI to be enabled. + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_rdid(&rdid); + } + + if (status == ALT_E_SUCCESS) + { + // NOTE: The size code seems to be a form of BCD (binary coded decimal). + // The first nibble is the 10's digit and the second nibble is the 1's + // digit in the number of bytes. + + // Capacity ID samples: + // 0x15 : 16 Mb => 2 MiB => 1 << 21 ; BCD=15 + // 0x16 : 32 Mb => 4 MiB => 1 << 22 ; BCD=16 + // 0x17 : 64 Mb => 8 MiB => 1 << 23 ; BCD=17 + // 0x18 : 128 Mb => 16 MiB => 1 << 24 ; BCD=18 + // 0x19 : 256 Mb => 32 MiB => 1 << 25 ; BCD=19 + // 0x1a + // 0x1b + // 0x1c + // 0x1d + // 0x1e + // 0x1f + // 0x20 : 512 Mb => 64 MiB => 1 << 26 ; BCD=20 + // 0x21 : 1024 Mb => 128 MiB => 1 << 27 ; BCD=21 + + int cap_code = ALT_QSPI_STIG_RDID_CAPACITYID_GET(rdid); + + if ( ((cap_code >> 4) > 0x9) || ((cap_code & 0xf) > 0x9)) + { + // If a non-valid BCD value is detected at the top or bottom nibble, chances + // are that the chip has a problem. + + dprintf("DEBUG[QSPI]: Invalid CapacityID encountered: 0x%02x.\n", cap_code); + status = ALT_E_ERROR; + } + else + { + int cap_decoded = ((cap_code >> 4) * 10) + (cap_code & 0xf); + + qspi_device_size = 1 << (cap_decoded + 6); + + dprintf("DEBUG[QSPI]: Device size = 0x%" PRIx32 ".\n", qspi_device_size); + } + } + + // Configure the device size and address bytes + + if (status == ALT_E_SUCCESS) + { + ALT_QSPI_DEV_SIZE_CONFIG_t size_cfg = + { + .block_size = ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET, // 0x10 => 2^16 = 64 KiB + .page_size = ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET, // 0x100 => 256 B + .addr_size = ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET, // 0x2 => 3 bytes or 0x00ffffff mask. + .lower_wrprot_block = 0, + .upper_wrprot_block = (qspi_device_size - 1) >> 16, + .wrprot_enable = ALT_QSPI_WRPROT_EN_RESET + }; + + status = alt_qspi_device_size_config_set(&size_cfg); + } + + ///// + + // Configure the DMA parameters + + // This will allow DMA to work well without much intervention by users. + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_dma_config_set(4, 32); + } + + ///// + + return status; +} + +///// + +uint32_t alt_qspi_int_status_get(void) +{ + // Read and return the value of the QSPI controller Interrupt Status + // Register (irqstat). + return alt_read_word(ALT_QSPI_IRQSTAT_ADDR); +} + +ALT_STATUS_CODE alt_qspi_int_clear(const uint32_t mask) +{ + // Check that the [mask] contains valid interrupt status conditions values. + if ((ALT_QSPI_INT_STATUS_ALL & mask) == 0) + { + return ALT_E_BAD_ARG; + } + + // Write 1's to clear the desired interrupt status condition(s). + alt_write_word(ALT_QSPI_IRQSTAT_ADDR, mask); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_int_disable(const uint32_t mask) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Check that the [mask] contains valid interrupt status conditions values. + if ((ALT_QSPI_INT_STATUS_ALL & mask) == 0) + { + return ALT_E_BAD_ARG; + } + + // Write 0's to disable the desired interrupt status condition(s). + alt_clrbits_word(ALT_QSPI_IRQMSK_ADDR, mask); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_int_enable(const uint32_t mask) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Check that the [mask] contains valid interrupt status conditions values. + if ((ALT_QSPI_INT_STATUS_ALL & mask) == 0) + { + return ALT_E_BAD_ARG; + } + + // Write 1's to enable the desired interrupt status condition(s). + alt_setbits_word(ALT_QSPI_IRQMSK_ADDR, mask); + + return ALT_E_SUCCESS; +} + +///// + +bool alt_qspi_is_idle(void) +{ + // If the idle field of the QSPI configuration register is 1 then the serial + // interface and QSPI pipeline is idle. + return ALT_QSPI_CFG_IDLE_GET(alt_read_word(ALT_QSPI_CFG_ADDR)) == 1; +} + +///// + +static ALT_STATUS_CODE alt_qspi_indirect_write_start_bank(uint32_t dst, size_t length); + +static ALT_STATUS_CODE alt_qspi_indirect_page_bound_write_helper(uint32_t dst, const char * src, size_t length) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_write_start_bank(dst, length); + } + + if (status == ALT_E_SUCCESS) + { + uint32_t write_count = 0; + uint32_t write_capacity = ALT_QSPI_SRAM_FIFO_ENTRY_COUNT - alt_qspi_sram_partition_get(); + + while (write_count < length) + { + uint32_t space = write_capacity - alt_qspi_indirect_write_fill_level(); + space = MIN(space, (length - write_count)/ sizeof(uint32_t)); + + const uint32_t * data = (const uint32_t *)(src + write_count); + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_QSPIDATA_ADDR, *data++); + } + + write_count += space * sizeof(uint32_t); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_write_finish(); + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_indirect_subsector_aligned_write_helper(const char * data, uint32_t subsec_addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + for (int i = 0; i < ALT_QSPI_SUBSECTOR_SIZE / ALT_QSPI_PAGE_SIZE; i++) + { + int offset = i * ALT_QSPI_PAGE_SIZE; + + status = alt_qspi_indirect_page_bound_write_helper(subsec_addr + offset, data + offset, ALT_QSPI_PAGE_SIZE); + if (status != ALT_E_SUCCESS) + { + break; + } + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_indirect_read_start_bank(uint32_t src, size_t size); + +// +// This helper function reads a segment of data, which is limited to 1 bank +// (24 bits of addressing). +// +static ALT_STATUS_CODE alt_qspi_read_bank(char * dst, uint32_t src, size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_read_start_bank(src, size); + } + + if (status == ALT_E_SUCCESS) + { + uint32_t read_count = 0; + + while (!alt_qspi_indirect_read_is_complete()) + { + uint32_t level = alt_qspi_indirect_read_fill_level(); +// level = MIN(level, (size - read_count) / sizeof(uint32_t)); + + uint32_t * data = (uint32_t *)(dst + read_count); + for (uint32_t i = 0; i < level; ++i) + { + *data++ = alt_read_word(ALT_QSPIDATA_ADDR); + } + + read_count += level * sizeof(uint32_t); + } + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_read_finish(); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_read(void * dst, uint32_t src, size_t size) +{ + if (src >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (src + size - 1 >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + if ((uintptr_t)dst & 0x3) + { + return ALT_E_ERROR; + } + + if (src & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // + // bank_count : The number of bank(s) affected, including partial banks. + // bank_addr : The aligned address of the first affected bank, including partial bank(s). + // bank_ofst : The offset of the bank to read. Only used when reading the first bank. + // + uint32_t bank_count = ((src + size - 1) >> 24) - (src >> 24) + 1; + uint32_t bank_addr = src & ALT_QSPI_BANK_ADDR_MSK; + uint32_t bank_ofst = src & (ALT_QSPI_BANK_SIZE - 1); + + char * data = (char *)dst; + + uint32_t copy_length = MIN(size, ALT_QSPI_BANK_SIZE - bank_ofst); + + dprintf("DEBUG[QSPI]: read(): bulk: mem_addr = %p; flash_addr = 0x%" PRIx32 ".\n", data, src); + dprintf("DEBUG[QSPI]: read(): bulk: bank_count = 0x%" PRIx32 ", bank_ofst = 0x%" PRIx32 ".\n", bank_count, bank_ofst); + + for (uint32_t i = 0; i < bank_count; ++i) + { + dprintf("DEBUG[QSPI]: read(): bank 0x%" PRIx32 "; copy_length = 0x%" PRIx32 ".\n", bank_addr >> 24, copy_length); + + status = alt_qspi_device_bank_select(bank_addr >> 24); + if (status != ALT_E_SUCCESS) + { + break; + } + + status = alt_qspi_read_bank(dst, bank_ofst, copy_length); + if (status != ALT_E_SUCCESS) + { + break; + } + + bank_addr += ALT_QSPI_BANK_SIZE; + data += copy_length; + size -= copy_length; + + copy_length = MIN(size, ALT_QSPI_BANK_SIZE); + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_write_bank(uint32_t dst, const char * src, size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + ///// + + uint32_t page_ofst = dst & (ALT_QSPI_PAGE_SIZE - 1); + uint32_t write_size = MIN(size, ALT_QSPI_PAGE_SIZE - page_ofst); + + while (size) + { + dprintf("DEBUG[QSPI]: write(): flash dst = 0x%" PRIx32 ", mem src = %p, write size = 0x%" PRIx32 ", size left = 0x%x.\n", dst, src, write_size, size); + + status = alt_qspi_indirect_page_bound_write_helper(dst, src, write_size); + if (status != ALT_E_SUCCESS) + { + break; + } + + dst += write_size; + src += write_size; + size -= write_size; + + write_size = MIN(size, ALT_QSPI_PAGE_SIZE); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_write(uint32_t dst, const void * src, size_t size) +{ + if (dst >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (dst + size - 1 >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + if ((uintptr_t)src & 0x3) + { + return ALT_E_ERROR; + } + + if (dst & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t bank_count = ((dst + size - 1) >> 24) - (dst >> 24) + 1; + uint32_t bank_addr = dst & ALT_QSPI_BANK_ADDR_MSK; + uint32_t bank_ofst = dst & (ALT_QSPI_BANK_SIZE - 1); + + const char * data = src; + + uint32_t copy_length = MIN(size, ALT_QSPI_BANK_SIZE - bank_ofst); + + dprintf("DEBUG[QSPI]: write(): bulk: flash_addr = 0x%" PRIx32 "; mem_addr = %p.\n", dst, data); + dprintf("DEBUG[QSPI]: write(): bulk: bank_count = 0x%" PRIx32 ", bank_ofst = 0x%" PRIx32 ".\n", bank_count, bank_ofst); + + for (uint32_t i = 0; i < bank_count; ++i) + { + dprintf("DEBUG[QSPI]: write(): bank 0x%" PRIx32 "; copy_length = 0x%" PRIx32 ".\n", bank_addr >> 24, copy_length); + + status = alt_qspi_device_bank_select(bank_addr >> 24); + if (status != ALT_E_SUCCESS) + { + break; + } + + status = alt_qspi_write_bank(bank_ofst, data, copy_length); + if (status != ALT_E_SUCCESS) + { + break; + } + + bank_addr += ALT_QSPI_BANK_SIZE; + data += copy_length; + size -= copy_length; + + copy_length = MIN(size, ALT_QSPI_BANK_SIZE); + } + + return status; +} + +static ALT_STATUS_CODE alt_qspi_erase_subsector_bank(uint32_t addr); + +static ALT_STATUS_CODE alt_qspi_replace_bank(uint32_t dst, const char * src, size_t size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // + // subsec_count : The total number of affected subsector(s), + // including partial subsector(s). + // subsec_addr : The aligned address of the next affected subsector, + // including partial subsector(s). + // subsec_partial_head : The number of subsector unaligned data to be + // written out at the start of the flash write + // request. This data ends at the end of the subsector + // or earlier depending on the number of data to be + // written. + // subsec_partial_tail : The number of subsector unaligned data to be + // written out at the end of the flash write request. + // This data starts at the start of the subsector. If + // only a single subsector is written (partial or + // full), this value will be zero. + // + + uint32_t subsec_count = ((dst + size - 1) >> 12) - (dst >> 12) + 1; + uint32_t subsec_addr = dst & ALT_QSPI_SUBSECTOR_ADDR_MSK; + + uint32_t subsec_partial_head = MIN(ALT_QSPI_SUBSECTOR_SIZE - (dst & (ALT_QSPI_SUBSECTOR_SIZE - 1)), size) & (ALT_QSPI_SUBSECTOR_SIZE - 1); + uint32_t subsec_partial_tail = (size - subsec_partial_head) & (ALT_QSPI_SUBSECTOR_SIZE - 1); + + dprintf("DEBUG[QSPI]: replace(): report: dst = 0x%" PRIx32 "; size = 0x%x.\n", + dst, size); + dprintf("DEBUG[QSPI]: replace(): report: subsec_count = 0x%" PRIx32 "; subsec_addr = 0x%" PRIx32 ".\n", + subsec_count, subsec_addr); + dprintf("DEBUG[QSPI]: replace(): report: partial_head = 0x%" PRIx32 "; partial_tail = 0x%" PRIx32 ".\n", + subsec_partial_head, subsec_partial_tail); + + // Write the first subsector, partial case. + + if (subsec_partial_head) + { + // The write request is not aligned to a subsector so we must do the + // Read-Modify-Write cycle to preserve the existing data at the head of + // the subsector not affected by the write. + + char subsec_buf[ALT_QSPI_SUBSECTOR_SIZE]; + + uint32_t subsec_ofst = dst & ~ALT_QSPI_SUBSECTOR_ADDR_MSK; + + // - Read the subsector into buffer + // - Erase that subsector + // - Copy in the user data into buffer + // - Write out buffer to subsector + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_read_bank(subsec_buf, subsec_addr, subsec_ofst); + } + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(subsec_addr); + } + if (status == ALT_E_SUCCESS) + { + memcpy(subsec_buf + subsec_ofst, src, subsec_partial_head); + status = alt_qspi_indirect_subsector_aligned_write_helper(subsec_buf, subsec_addr); + } + + // Do some bookkeeping on the user buffer information + src += subsec_partial_head; + size -= subsec_partial_head; + + // Do some bookkeeping on the subsector tracking + subsec_count--; + subsec_addr += ALT_QSPI_SUBSECTOR_SIZE; + + dprintf("DEBUG[QSPI]: replace(): partial head: subsec_ofst = 0x%" PRIx32 "; size left = 0x%x; status = %" PRIi32 ".\n", + subsec_ofst, size, status); + } + + // If there is a partial tail, then take 1 off the subsec_count. This way + // the following loop will write out all the complete subsectors. The tail + // will be written out afterwards. + + if (subsec_partial_tail) + { + subsec_count--; + } + + // Write the aligned subsectors following any partial subsectors. + + for (uint32_t i = 0; i < subsec_count; ++i) + { + // - Erase subsector + // - Write out buffer to subsector + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(subsec_addr); + } + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_indirect_subsector_aligned_write_helper(src, subsec_addr); + } + + src += ALT_QSPI_SUBSECTOR_SIZE; + size -= ALT_QSPI_SUBSECTOR_SIZE; + + // Don't modify subsec_count as it's being used by the loop. + subsec_addr += ALT_QSPI_SUBSECTOR_SIZE; + + dprintf("DEBUG[QSPI]: replace(): subsec aligned: size left = 0x%x, status = %" PRIi32 ".\n", + size, status); + } + + // Write the last subsector, partial case. + + if (subsec_partial_tail) + { + // The write request is not aligned to a subsector so we must do the + // Read-Modify-Write cycle to preserve the existing data at the end of + // the subsector not affected by the write. + + char subsec_buf[ALT_QSPI_SUBSECTOR_SIZE]; + + // - Read the subsector into buffer + // - Erase that subsector + // - Copy in the user data into buffer + // - Write out buffer to subsector + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_read_bank(subsec_buf + subsec_partial_tail, + subsec_addr + subsec_partial_tail, + ALT_QSPI_SUBSECTOR_SIZE - subsec_partial_tail); + } + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(subsec_addr); + } + if (status == ALT_E_SUCCESS) + { + memcpy(subsec_buf, src, subsec_partial_tail); + status = alt_qspi_indirect_subsector_aligned_write_helper(subsec_buf, subsec_addr); + } + + src += subsec_partial_tail; + size -= subsec_partial_tail; + + dprintf("DEBUG[QSPI]: replace(): partial tail: size left = 0x%x, status = %" PRIi32 ".\n", + size, status); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size) +{ + if (dst >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (dst + size - 1 >= qspi_device_size) + { + return ALT_E_ERROR; + } + + if (size == 0) + { + return ALT_E_SUCCESS; + } + + if ((uintptr_t)src & 0x3) + { + return ALT_E_ERROR; + } + + if (dst & 0x3) + { + return ALT_E_ERROR; + } + + if (size & 0x3) + { + return ALT_E_ERROR; + } + + ///// + + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t bank_count = ((dst + size - 1) >> 24) - (dst >> 24) + 1; + uint32_t bank_addr = dst & ALT_QSPI_BANK_ADDR_MSK; + uint32_t bank_ofst = dst & (ALT_QSPI_BANK_SIZE - 1); + + const char * data = (const char *)src; + + uint32_t copy_length = MIN(size, ALT_QSPI_BANK_SIZE - bank_ofst); + + dprintf("DEBUG[QSPI]: replace(): bulk: flash_addr = 0x%" PRIx32 "; mem_addr = %p.\n", dst, data); + dprintf("DEBUG[QSPI]: replace(): bulk: bank_count = 0x%" PRIx32 ", bank_ofst = 0x%" PRIx32 ".\n", bank_count, bank_ofst); + + for (uint32_t i = 0; i < bank_count; ++i) + { + dprintf("DEBUG[QSPI]: replace(): bank 0x%" PRIx32 "; copy_length = 0x%" PRIx32 ".\n", bank_addr >> 24, copy_length); + + status = alt_qspi_device_bank_select(bank_addr >> 24); + if (status != ALT_E_SUCCESS) + { + break; + } + + status = alt_qspi_replace_bank(bank_ofst, data, copy_length); + if (status != ALT_E_SUCCESS) + { + break; + } + + bank_addr += ALT_QSPI_BANK_SIZE; + data += copy_length; + size -= copy_length; + + copy_length = MIN(size, ALT_QSPI_BANK_SIZE); + } + + return status; +} + +///// + +ALT_QSPI_BAUD_DIV_t alt_qspi_baud_rate_div_get(void) +{ + uint32_t baud_rate_div = ALT_QSPI_CFG_BAUDDIV_GET(alt_read_word(ALT_QSPI_CFG_ADDR)); + return (ALT_QSPI_BAUD_DIV_t) baud_rate_div; +} + +ALT_STATUS_CODE alt_qspi_baud_rate_div_set(const ALT_QSPI_BAUD_DIV_t baud_rate_div) +{ + if (0xf < (uint32_t)baud_rate_div) + { + // Invalid baud rate divisor value. + return ALT_E_BAD_ARG; + } + + // Set the Master Mode Baud Rate Divisor Field of the QSPI Configuration Register. + alt_replbits_word(ALT_QSPI_CFG_ADDR, + ALT_QSPI_CFG_BAUDDIV_SET_MSK, + ALT_QSPI_CFG_BAUDDIV_SET(baud_rate_div)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_chip_select_config_get(uint32_t* cs, + ALT_QSPI_CS_MODE_t* cs_mode) +{ + uint32_t cfg = alt_read_word(ALT_QSPI_CFG_ADDR); + + *cs = ALT_QSPI_CFG_PERCSLINES_GET(cfg); + *cs_mode = (ALT_QSPI_CS_MODE_t) ALT_QSPI_CFG_PERSELDEC_GET(cfg); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_chip_select_config_set(const uint32_t cs, + const ALT_QSPI_CS_MODE_t cs_mode) +{ + // chip select cs: + // four bit value, bit 0 = cs0, bit 1 = cs1, bit 2 = cs2, bit 3 = cs3 + // since cs is low true, the value of each bit should be zero if enable the cs. + // + // also allows multiple cs line enabled together. + + if (cs > ((1 << ALT_QSPI_CFG_PERCSLINES_WIDTH) - 1)) + { + // [cs] not within possible 4 bit chip select line value range. + return ALT_E_ARG_RANGE; + } + + if ((cs_mode != ALT_QSPI_CS_MODE_SINGLE_SELECT) && (cs_mode != ALT_QSPI_CS_MODE_DECODE)) + { + return ALT_E_INV_OPTION; + } + + // Update the Peripheral Chip Select Lines and Peripheral Select Decode + // Fields of the QSPI Configuration Register value with the chip select + // options. + uint32_t cfg = alt_read_word(ALT_QSPI_CFG_ADDR); + cfg &= ALT_QSPI_CFG_PERCSLINES_CLR_MSK & ALT_QSPI_CFG_PERSELDEC_CLR_MSK; + cfg |= ALT_QSPI_CFG_PERCSLINES_SET(cs) | ALT_QSPI_CFG_PERSELDEC_SET(cs_mode); + alt_write_word(ALT_QSPI_CFG_ADDR, cfg); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_mode_bit_disable(void) +{ + // Clear the Mode Bit Enable Field of the Device Read Instruction Register + // to disable mode bits from being sent after the address bytes. + alt_clrbits_word(ALT_QSPI_DEVRD_ADDR, ALT_QSPI_DEVRD_ENMODBITS_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_mode_bit_enable(void) +{ + // Set the Mode Bit Enable Field of the Device Read Instruction Register + // to enable mode bits to be sent after the address bytes. + alt_setbits_word(ALT_QSPI_DEVRD_ADDR, ALT_QSPI_DEVRD_ENMODBITS_SET_MSK); + + return ALT_E_SUCCESS; +} + +uint32_t alt_qspi_mode_bit_config_get(void) +{ + // Return the 8 bit value from the Mode Field of the Mode Bit Configuration + // Register. + return ALT_QSPI_MODBIT_MOD_GET(alt_read_word(ALT_QSPI_MODBIT_ADDR)); +} + +ALT_STATUS_CODE alt_qspi_mode_bit_config_set(const uint32_t mode_bits) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + if (mode_bits > ((1 << ALT_QSPI_MODBIT_MOD_WIDTH) - 1)) + { + // 'mode_bits' not within possible 8 bit mode value range. + return ALT_E_ARG_RANGE; + } + + // Set the 8 bit value in the Mode Field of the Mode Bit Configuration + // Register. + alt_replbits_word(ALT_QSPI_MODBIT_ADDR, + ALT_QSPI_MODBIT_MOD_SET_MSK, + ALT_QSPI_MODBIT_MOD_SET(mode_bits)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_size_config_get(ALT_QSPI_DEV_SIZE_CONFIG_t * cfg) +{ + // Although not required, it is recommended that the write protect feature + // be enabled prior to enabling the QSPI controller. This will block any AHB + // writes from taking effect. This also means the write protection registers + // (Lower Write Protection, Upper Write Protection, and Write Protection) + // should be setup and the number of bytes per device block in the device + // size configuration register should be setup prior to enabling the QSPI + // controller. + + // Read Device Size Register and get the Number of Bytes per Block, Number + // of Bytes per Device, and Number of Address Bytes Fields. + + uint32_t devsz = alt_read_word(ALT_QSPI_DEVSZ_ADDR); + + cfg->block_size = ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(devsz); + cfg->page_size = ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(devsz); + cfg->addr_size = ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(devsz); + + // Read Lower Write Protection, Upper Write Protection, and Write Protection + // Registers. + + cfg->lower_wrprot_block = ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(alt_read_word(ALT_QSPI_LOWWRPROT_ADDR)); + cfg->upper_wrprot_block = ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(alt_read_word(ALT_QSPI_UPPWRPROT_ADDR)); + cfg->wrprot_enable = ALT_QSPI_WRPROT_EN_GET(alt_read_word(ALT_QSPI_WRPROT_ADDR)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_size_config_set(const ALT_QSPI_DEV_SIZE_CONFIG_t * cfg) +{ + if (cfg->block_size > ((1 << ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + if (cfg->page_size > ((1 << ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + if (cfg->addr_size > ((1 << ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + if (cfg->lower_wrprot_block > cfg->upper_wrprot_block) + { + // Null write protection regions are not allowed. + return ALT_E_ARG_RANGE; + } + + ///// + + uint32_t value = ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(cfg->block_size) | + ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(cfg->page_size) | + ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(cfg->addr_size); + + alt_write_word(ALT_QSPI_DEVSZ_ADDR, value); + + if (cfg->wrprot_enable) + { + alt_write_word(ALT_QSPI_LOWWRPROT_ADDR, cfg->lower_wrprot_block); + alt_write_word(ALT_QSPI_UPPWRPROT_ADDR, cfg->upper_wrprot_block); + } + + // Read Upper Write Protection Register - uppwrprot. + // Set the Write Protection Enable Bit Field of the Write Protection + // Register accordingly. + if (cfg->wrprot_enable) + { + alt_setbits_word(ALT_QSPI_WRPROT_ADDR, ALT_QSPI_WRPROT_EN_SET(1)); + } + else + { + alt_clrbits_word(ALT_QSPI_WRPROT_ADDR, ALT_QSPI_WRPROT_EN_SET(1)); + } + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_read_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + // Read the Device Read Instruction Register - devrd. + uint32_t devrd = alt_read_word(ALT_QSPI_DEVRD_ADDR); + + cfg->op_code = ALT_QSPI_DEVRD_RDOPCODE_GET(devrd); + cfg->inst_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_INSTWIDTH_GET(devrd); + cfg->addr_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_ADDRWIDTH_GET(devrd); + cfg->data_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_DATAWIDTH_GET(devrd); + cfg->dummy_cycles = ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(devrd); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_read_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Validate input + + if (cfg->op_code > ((1 << ALT_QSPI_DEVRD_RDOPCODE_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + switch (cfg->inst_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->addr_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->data_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + if (cfg->dummy_cycles > ((1 << ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + ///// + + // Read the Device Read Instruction Register - devrd. + uint32_t devrd = alt_read_word(ALT_QSPI_DEVRD_ADDR); + + devrd &= ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK & + ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK & + ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK & + ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK & + ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK; + + devrd |= ALT_QSPI_DEVRD_RDOPCODE_SET(cfg->op_code) | + ALT_QSPI_DEVRD_INSTWIDTH_SET(cfg->inst_type) | + ALT_QSPI_DEVRD_ADDRWIDTH_SET(cfg->addr_xfer_type) | + ALT_QSPI_DEVRD_DATAWIDTH_SET(cfg->data_xfer_type) | + ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(cfg->dummy_cycles); + + alt_write_word(ALT_QSPI_DEVRD_ADDR, devrd); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_write_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + // Device Write Instruction Register - devwr. + uint32_t devwr = alt_read_word(ALT_QSPI_DEVWR_ADDR); + + cfg->op_code = ALT_QSPI_DEVWR_WROPCODE_GET(devwr); + // The Instruction Type field in the Device READ Instruction Register only appears + // once and applies to both READ and WRITE opertions. it is not included in the + // Device WRITE Instruction Register. + cfg->inst_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVRD_INSTWIDTH_GET(alt_read_word(ALT_QSPI_DEVRD_ADDR)); + cfg->addr_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVWR_ADDRWIDTH_GET(devwr); + cfg->data_xfer_type = (ALT_QSPI_MODE_t) ALT_QSPI_DEVWR_DATAWIDTH_GET(devwr); + cfg->dummy_cycles = ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(devwr); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_device_write_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Validate input + + if (cfg->op_code > ((1 << ALT_QSPI_DEVWR_WROPCODE_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + switch (cfg->inst_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->addr_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->data_xfer_type) + { + case ALT_QSPI_MODE_SINGLE: + case ALT_QSPI_MODE_DUAL: + case ALT_QSPI_MODE_QUAD: + break; + default: + return ALT_E_BAD_ARG; + } + + if (cfg->dummy_cycles > ((1 << ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + ///// + + // Read the Device Write Instruction Register - devwr. + uint32_t devwr = alt_read_word(ALT_QSPI_DEVWR_ADDR); + + devwr &= ALT_QSPI_DEVWR_WROPCODE_CLR_MSK & + ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK & + ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK & + ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK; + + devwr |= ALT_QSPI_DEVWR_WROPCODE_SET(cfg->op_code) | + ALT_QSPI_DEVWR_ADDRWIDTH_SET(cfg->addr_xfer_type) | + ALT_QSPI_DEVWR_DATAWIDTH_SET(cfg->data_xfer_type) | + ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(cfg->dummy_cycles); + + alt_write_word(ALT_QSPI_DEVWR_ADDR, devwr); + + // The Instruction Type field in the Device READ Instruction Register only appears + // once and applies to both READ and WRITE operations - it is not included in the + // Device WRITE Instruction Register. Therefore, modify the Instruction Type + // Field in the Device Read Register. + alt_replbits_word(ALT_QSPI_DEVRD_ADDR, + ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK, + ALT_QSPI_DEVRD_INSTWIDTH_SET((uint32_t) cfg->inst_type)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_timing_config_get(ALT_QSPI_TIMING_CONFIG_t * cfg) +{ + // QSPI Configuration Register - cfg + uint32_t cfgreg = alt_read_word(ALT_QSPI_CFG_ADDR); + cfg->clk_phase = (ALT_QSPI_CLK_PHASE_t) ALT_QSPI_CFG_SELCLKPHASE_GET(cfgreg); + cfg->clk_pol = (ALT_QSPI_CLK_POLARITY_t) ALT_QSPI_CFG_SELCLKPOL_GET(cfgreg); + + // QSPI Device Delay Register + uint32_t delayreg = alt_read_word(ALT_QSPI_DELAY_ADDR); + cfg->cs_sot = ALT_QSPI_DELAY_INIT_GET(delayreg); + cfg->cs_eot = ALT_QSPI_DELAY_AFTER_GET(delayreg); + cfg->cs_dads = ALT_QSPI_DELAY_BTWN_GET(delayreg); + cfg->cs_da = ALT_QSPI_DELAY_NSS_GET(delayreg); + + // Read Data Capture Register + cfg->rd_datacap = ALT_QSPI_RDDATACAP_DELAY_GET(alt_read_word(ALT_QSPI_RDDATACAP_ADDR)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_timing_config_set(const ALT_QSPI_TIMING_CONFIG_t * cfg) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Validate parameter(s) + + switch (cfg->clk_phase) + { + case ALT_QSPI_CLK_PHASE_ACTIVE: + case ALT_QSPI_CLK_PHASE_INACTIVE: + break; + default: + return ALT_E_BAD_ARG; + } + + switch (cfg->clk_pol) + { + case ALT_QSPI_CLK_POLARITY_LOW: + case ALT_QSPI_CLK_POLARITY_HIGH: + break; + default: + return ALT_E_BAD_ARG; + } + + if (cfg->cs_da > ((1 << ALT_QSPI_DELAY_NSS_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + if (cfg->cs_dads > ((1 << ALT_QSPI_DELAY_BTWN_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + if (cfg->cs_eot > ((1 << ALT_QSPI_DELAY_AFTER_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + if (cfg->cs_sot > ((1 << ALT_QSPI_DELAY_INIT_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + if (cfg->rd_datacap > ((1 << ALT_QSPI_RDDATACAP_DELAY_WIDTH) - 1)) + { + return ALT_E_BAD_ARG; + } + + ///// + + // QSPI Configuration Register - cfg + uint32_t cfgreg = alt_read_word(ALT_QSPI_CFG_ADDR); + cfgreg &= ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK & + ALT_QSPI_CFG_SELCLKPOL_CLR_MSK; + cfgreg |= ALT_QSPI_CFG_SELCLKPHASE_SET(cfg->clk_phase) | + ALT_QSPI_CFG_SELCLKPOL_SET(cfg->clk_pol); + alt_write_word(ALT_QSPI_CFG_ADDR, cfgreg); + + // QSPI Device Delay Register + uint32_t delayreg = ALT_QSPI_DELAY_INIT_SET(cfg->cs_sot) | + ALT_QSPI_DELAY_AFTER_SET(cfg->cs_eot) | + ALT_QSPI_DELAY_BTWN_SET(cfg->cs_dads) | + ALT_QSPI_DELAY_NSS_SET(cfg->cs_da); + alt_write_word(ALT_QSPI_DELAY_ADDR, delayreg); + + // Read Data Capture Register + + alt_write_word(ALT_QSPI_RDDATACAP_ADDR, + ALT_QSPI_RDDATACAP_BYP_SET(1) | + ALT_QSPI_RDDATACAP_DELAY_SET(cfg->rd_datacap)); + + return ALT_E_SUCCESS; +} + +///// + +ALT_STATUS_CODE alt_qspi_direct_disable(void) +{ + // Clear (set to 0) the Enable Direct Access Controller Field of the QSPI + // Configuration Register to disable the Direct Access Controller. + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDIRACC_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_direct_enable(void) +{ + // Set (set to 1) the Enable Direct Access Controller Field of the QSPI + // Configuration Register to enable the Direct Access Controller. + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDIRACC_SET_MSK); + + return ALT_E_SUCCESS; +} + +uint32_t alt_qspi_ahb_remap_address_get(void) +{ + // Read and return the value of the Remap Address Register. + return ALT_QSPI_REMAPADDR_VALUE_GET(alt_read_word(ALT_QSPI_REMAPADDR_ADDR)); +} + +ALT_STATUS_CODE alt_qspi_ahb_remap_address_set(const uint32_t ahb_remap_addr) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + // Read and return the value of the Remap Address Register. + alt_setbits_word(ALT_QSPI_REMAPADDR_ADDR, ALT_QSPI_REMAPADDR_VALUE_SET(ahb_remap_addr)); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_ahb_address_remap_disable(void) +{ + // Clear (set to 0) the Enable AHB Address Remapping Field of the QSPI + // Configuration Register to disable AHB address remapping. + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENAHBREMAP_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_ahb_address_remap_enable(void) +{ + // Set (set to 1) the Enable AHB Address Remapping Field of the QSPI + // Configuration Register to enable AHB address remapping. + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENAHBREMAP_SET_MSK); + + return ALT_E_SUCCESS; +} + +///// + +static ALT_STATUS_CODE alt_qspi_indirect_read_start_bank(uint32_t flash_addr, + size_t num_bytes) +{ + alt_write_word(ALT_QSPI_INDRDSTADDR_ADDR, flash_addr); + alt_write_word(ALT_QSPI_INDRDCNT_ADDR, num_bytes); + alt_write_word(ALT_QSPI_INDRD_ADDR, ALT_QSPI_INDRD_START_SET_MSK | + ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_indirect_read_start(const uint32_t flash_addr, + const size_t num_bytes) +{ + // flash_addr and num_bytes restriction is to prevent possible unaligned + // exceptions. + + if (flash_addr & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes == 0) + { + // Do not report this as a success. If a indirect read was not + // previously completed, it may be cleared already, at which point + // alt_qspi_indirect_read_is_complete() will never report true. + return ALT_E_ERROR; + } + + if (flash_addr > qspi_device_size) + { + return ALT_E_ERROR; + } + + if (flash_addr + num_bytes > qspi_device_size) + { + return ALT_E_ERROR; + } + + // Verify request does not cross bank boundary. + // This limitation is due to the 3-byte addressing limitation. + if ((flash_addr & ALT_QSPI_BANK_ADDR_MSK) != ((flash_addr + num_bytes - 1) & ALT_QSPI_BANK_ADDR_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status; + status = alt_qspi_device_bank_select(flash_addr >> 24); + if (status != ALT_E_SUCCESS) + { + return status; + } + + ///// + + return alt_qspi_indirect_read_start_bank(flash_addr, + num_bytes); + +} + +ALT_STATUS_CODE alt_qspi_indirect_read_finish(void) +{ + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_indirect_read_cancel(void) +{ + // An indirect operation may be cancelled at any time by setting Indirect + // Transfer Control Register bit [1]. + alt_write_word(ALT_QSPI_INDRD_ADDR, ALT_QSPI_INDRD_CANCEL_SET_MSK); + + return ALT_E_SUCCESS; +} + +uint32_t alt_qspi_indirect_read_fill_level(void) +{ + // Return the SRAM Fill Level (Indirect Read Partition) Field of the SRAM + // Fill Register to get the SRAM Fill Level for the Indirect Read Partition + // in units of SRAM Words (4 bytes). + return ALT_QSPI_SRAMFILL_INDRDPART_GET(alt_read_word(ALT_QSPI_SRAMFILL_ADDR)); +} + +uint32_t alt_qspi_indirect_read_watermark_get(void) +{ + // Return the Watermark value in the Indirect Read Transfer Watermark Register. + return alt_read_word(ALT_QSPI_INDRDWATER_ADDR); +} + +ALT_STATUS_CODE alt_qspi_indirect_read_watermark_set(const uint32_t watermark) +{ + // Verify that there is not already a read in progress. + if (ALT_QSPI_INDRD_RD_STAT_GET(alt_read_word(ALT_QSPI_INDRD_ADDR))) + { + return ALT_E_ERROR; + } + + // Set the Watermark value in the Indirect Read Transfer Watermark Register. + alt_write_word(ALT_QSPI_INDRDWATER_ADDR, watermark); + + return ALT_E_SUCCESS; +} + +bool alt_qspi_indirect_read_is_complete(void) +{ + // The value of the Indirect Completion Status Field of the Indirect Read + // Transfer Control Register is set by hardware when an indirect read + // operation has completed. + return (alt_read_word(ALT_QSPI_INDRD_ADDR) & ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK) != 0; +} + +static ALT_STATUS_CODE alt_qspi_indirect_write_start_bank(uint32_t flash_addr, + size_t num_bytes) +{ + alt_write_word(ALT_QSPI_INDWRSTADDR_ADDR, flash_addr); + alt_write_word(ALT_QSPI_INDWRCNT_ADDR, num_bytes); + alt_write_word(ALT_QSPI_INDWR_ADDR, ALT_QSPI_INDWR_START_SET_MSK | + ALT_QSPI_INDWR_INDDONE_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_indirect_write_start(const uint32_t flash_addr, + const size_t num_bytes) +{ + // flash_addr and num_bytes restriction is to prevent possible unaligned + // exceptions. + + if (flash_addr & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes & 0x3) + { + return ALT_E_ERROR; + } + + if (num_bytes == 0) + { + // Do not report this as a success. If a indirect write was not + // previously completed, it may be cleared already, at which point + // alt_qspi_indirect_write_is_complete() will never report true. + return ALT_E_ERROR; + } + + if (num_bytes > 256) + { + // The Micron part can only write up to 256 bytes at a time. + return ALT_E_ERROR; + } + + if (flash_addr > qspi_device_size) + { + return ALT_E_ERROR; + } + + if (flash_addr + num_bytes > qspi_device_size) + { + return ALT_E_ERROR; + } + +/* + // Verify request does not cross bank boundary. + // This limitation is due to the 3-byte addressing limitation. + if ((flash_addr & ALT_QSPI_BANK_ADDR_MSK) != ((flash_addr + num_bytes - 1) & ALT_QSPI_BANK_ADDR_MSK)) + { + return ALT_E_ERROR; + } +*/ + // Verify request does not cross page boundary. + // This limitation is in place for the Micron part used. + if ((flash_addr & ALT_QSPI_PAGE_ADDR_MSK) != ((flash_addr + num_bytes - 1) & ALT_QSPI_PAGE_ADDR_MSK)) + { + return ALT_E_ERROR; + } + + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + status = alt_qspi_device_bank_select(flash_addr >> 24); + if (status != ALT_E_SUCCESS) + { + return status; + } + + ///// + + return alt_qspi_indirect_write_start_bank(flash_addr, + num_bytes); +} + +ALT_STATUS_CODE alt_qspi_indirect_write_finish(void) +{ +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + return alt_qspi_N25Q_flag_wait_for_program(ALT_QSPI_TIMEOUT_INFINITE); +#else + return ALT_E_SUCCESS; +#endif +} + +ALT_STATUS_CODE alt_qspi_indirect_write_cancel(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_program(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + + if (status == ALT_E_SUCCESS) + { + // An indirect operation may be cancelled at any time by setting Indirect + // Transfer Control Register bit [1]. + alt_write_word(ALT_QSPI_INDWR_ADDR, ALT_QSPI_INDWR_CANCEL_SET_MSK); + } + + return status; +} + +uint32_t alt_qspi_indirect_write_fill_level(void) +{ + // Return the SRAM Fill Level (Indirect Write Partition) Field of the SRAM + // Fill Register to get the SRAM Fill Level for the Indirect Write Partition + // in units of SRAM Words (4 bytes). + return ALT_QSPI_SRAMFILL_INDWRPART_GET(alt_read_word(ALT_QSPI_SRAMFILL_ADDR)); +} + +uint32_t alt_qspi_indirect_write_watermark_get(void) +{ + // Return the Watermark value in the Indirect Write Transfer Watermark Register. + return alt_read_word(ALT_QSPI_INDWRWATER_ADDR); +} + +ALT_STATUS_CODE alt_qspi_indirect_write_watermark_set(const uint32_t watermark) +{ + // Verify that there is not already a write in progress. + if (ALT_QSPI_INDWR_RDSTAT_GET(alt_read_word(ALT_QSPI_INDWR_ADDR))) + { + return ALT_E_ERROR; + } + + // Set the Watermark value in the Indirect Write Transfer Watermark Register. + alt_write_word(ALT_QSPI_INDWRWATER_ADDR, watermark); + + return ALT_E_SUCCESS; +} + +bool alt_qspi_indirect_write_is_complete(void) +{ + // The value of the Indirect Completion Status Field of the Indirect Write + // Transfer Control Register is set by hardware when an indirect write + // operation has completed. + return (alt_read_word(ALT_QSPI_INDWR_ADDR) & ALT_QSPI_INDWR_INDDONE_SET_MSK) != 0; +} + +///// + +uint32_t alt_qspi_sram_partition_get(void) +{ + // The number of locations allocated to indirect read is equal to the value + // of the SRAM partition register. See the documentation for this function + // regarding the + 1 in the IP documentation. This way the get() and set() + // will be symmetrical. + + return ALT_QSPI_SRAMPART_ADDR_GET(alt_read_word(ALT_QSPI_SRAMPART_ADDR)); +} + +ALT_STATUS_CODE alt_qspi_sram_partition_set(const uint32_t read_part_size) +{ + if (read_part_size > ((1 << ALT_QSPI_SRAMPART_ADDR_WIDTH) - 1)) + { + return ALT_E_ARG_RANGE; + } + + alt_replbits_word(ALT_QSPI_SRAMPART_ADDR, + ALT_QSPI_SRAMPART_ADDR_SET_MSK, + ALT_QSPI_SRAMPART_ADDR_SET(read_part_size)); + + return ALT_E_SUCCESS; +} + +///// + + +static ALT_STATUS_CODE alt_qspi_erase_subsector_bank(uint32_t addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE, 0, addr, 10000); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + + return status; +} + +ALT_STATUS_CODE alt_qspi_erase_subsector(const uint32_t addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(addr >> 24); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_erase_subsector_bank(addr); + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_erase_sector(const uint32_t addr) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(addr >> 24); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_SEC_ERASE, 0, addr, ALT_QSPI_TIMEOUT_INFINITE); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + + return status; +} + +ALT_STATUS_CODE alt_qspi_erase_chip(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (qspi_device_size >= (2 * ALT_QSPI_N25Q_DIE_SIZE)) + { + // NOTE: This path is specifically for 512 Mib and 1 Gib Micron N25Q + // chips only. + + dprintf("DEBUG[QSPI]: erase[chip]: FYI, wait time is ~800s for 128 MiB.\n"); + + uint32_t die_count = qspi_device_size / ALT_QSPI_N25Q_DIE_SIZE; + + for (int i = 0; i < die_count; ++i) + { + if (status != ALT_E_SUCCESS) + { + break; + } + + dprintf("DEBUG[QSPI]: Erase chip: die = %d, total = %" PRIu32 ".\n", i, die_count); + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(i * (ALT_QSPI_N25Q_DIE_SIZE / ALT_QSPI_BANK_SIZE)); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_DIE_ERASE, 0, + i * ALT_QSPI_N25Q_DIE_SIZE, + ALT_QSPI_TIMEOUT_INFINITE); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + } + } + else + { + // NOTE: Untested path. + + dprintf("DEBUG[QSPI]: Bulk erase.\n"); + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_bank_select(0); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + // If BULK_ERASE is like other ERASE, it needs the address command. + status = alt_qspi_stig_addr_cmd(ALT_QSPI_STIG_OPCODE_BULK_ERASE, 0, + 0, + ALT_QSPI_TIMEOUT_INFINITE); + } + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_N25Q_flag_wait_for_erase(ALT_QSPI_TIMEOUT_INFINITE); + } +#endif + } + + return status; +} + +///// + +ALT_STATUS_CODE alt_qspi_dma_disable(void) +{ + // Clear (set to 0) the Enable DMA Peripheral Interface Field of the QSPI + // Configuration Register to disable the DMA peripheral interface. + alt_clrbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_dma_enable(void) +{ + // Set (set to 1) the Enable DMA Peripheral Interface Field of the QSPI + // Configuration Register to enable the DMA peripheral interface. + alt_setbits_word(ALT_QSPI_CFG_ADDR, ALT_QSPI_CFG_ENDMA_SET_MSK); + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_dma_config_get(uint32_t * single_type_sz, + uint32_t * burst_type_sz) +{ + // Get the current value of the DMA Peripheral Register - dmaper + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + + // For both values, a programmed value of 0 represents a single byte. The + // actual number of bytes used is 2 ** (value in this register field). + *single_type_sz = 1 << ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(dmaper); + *burst_type_sz = 1 << ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(dmaper); + + return ALT_E_SUCCESS; +} + +// +// Returns true if [n] is a power of 2 value otherwise returns false. +// +static bool is_pow_2(uint32_t n) +{ + return ((n > 0) && ((n & (n - 1)) == 0)); +} + +// +// Return the log base 2 value of a number that is known to be a power of 2. +// +static uint32_t log2u(uint32_t value) +{ + uint32_t exp = 0; + while ((exp < 32) && (value != (1 << exp))) + { + ++exp; + } + return exp; +} + +ALT_STATUS_CODE alt_qspi_dma_config_set(const uint32_t single_type_sz, + const uint32_t burst_type_sz) +{ + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + if (single_type_sz < 4) + { + return ALT_E_ERROR; + } + + if (burst_type_sz < 4) + { + return ALT_E_ERROR; + } + + if (burst_type_sz < single_type_sz) + { + return ALT_E_ERROR; + } + + const uint32_t single_type_sz_max = 1 << ((1 << ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH) - 1); + const uint32_t burst_type_sz_max = 1 << ((1 << ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH) - 1); + + // Both parameter values must be a power of 2 between 1 and 32728. + if ( (single_type_sz > single_type_sz_max) || !is_pow_2(single_type_sz) + || (burst_type_sz > burst_type_sz_max) || !is_pow_2(burst_type_sz) + ) + { + return ALT_E_ARG_RANGE; + } + + // Get the current value of the DMA Peripheral Register - dmaper + uint32_t dmaper = alt_read_word(ALT_QSPI_DMAPER_ADDR); + dmaper &= ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK & + ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK; + dmaper |= ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(log2u(burst_type_sz)) | + ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(log2u(single_type_sz)); + alt_write_word(ALT_QSPI_DMAPER_ADDR, dmaper); + + return ALT_E_SUCCESS; +} + +///// + +// +// Private STIG and device commands +// + +static ALT_STATUS_CODE alt_qspi_stig_cmd_helper(uint32_t reg_value, uint32_t timeout) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + bool infinite = (timeout == ALT_QSPI_TIMEOUT_INFINITE); + + alt_write_word(ALT_QSPI_FLSHCMD_ADDR, reg_value); + alt_write_word(ALT_QSPI_FLSHCMD_ADDR, reg_value | ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE); + + do + { + reg_value = alt_read_word(ALT_QSPI_FLSHCMD_ADDR); + if (!(reg_value & ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK)) + { + break; + } + + } while (timeout-- || infinite); + + if (timeout == (uint32_t)-1 && !infinite) + { + status = ALT_E_TMO; + } + + return status; +} + +ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + uint32_t reg = ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + return alt_qspi_stig_cmd_helper(reg, timeout); +} + +ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, + uint32_t dummy, + uint32_t num_bytes, + uint32_t * output, + uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + // STIG read can only return up to 8 bytes. + if ((num_bytes > 8) || (num_bytes == 0)) + { + return ALT_E_BAD_ARG; + } + + uint32_t reg_value = + ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_ENRDDATA_SET(ALT_QSPI_FLSHCMD_ENRDDATA_E_EN) | + ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(num_bytes - 1) | + ALT_QSPI_FLSHCMD_ENCMDADDR_SET(ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD) | + ALT_QSPI_FLSHCMD_ENMODBIT_SET(ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD) | + ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(0) | + ALT_QSPI_FLSHCMD_ENWRDATA_SET(ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION) | + ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(0) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + status = alt_qspi_stig_cmd_helper(reg_value, timeout); + if (status != ALT_E_SUCCESS) + { + return status; + } + + output[0] = alt_read_word(ALT_QSPI_FLSHCMDRDDATALO_ADDR); + + if (num_bytes > 4) + { + output[1] = alt_read_word(ALT_QSPI_FLSHCMDRDDATAUP_ADDR); + } + + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, + uint32_t dummy, + uint32_t num_bytes, + const uint32_t * input, + uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + // STIG can only write up to 8 bytes. + if ((num_bytes > 8) || (num_bytes == 0)) + { + return ALT_E_BAD_ARG; + } + + uint32_t reg_value = + ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_ENRDDATA_SET(ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION) | + ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(0) | + ALT_QSPI_FLSHCMD_ENCMDADDR_SET(ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD) | + ALT_QSPI_FLSHCMD_ENMODBIT_SET(ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD) | + ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(0) | + ALT_QSPI_FLSHCMD_ENWRDATA_SET(ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES) | + ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(num_bytes - 1) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + alt_write_word(ALT_QSPI_FLSHCMDWRDATALO_ADDR, input[0]); + + if (num_bytes > 4) + { + alt_write_word(ALT_QSPI_FLSHCMDWRDATAUP_ADDR, input[1]); + } + + return alt_qspi_stig_cmd_helper(reg_value, timeout); +} + +ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, + uint32_t dummy, + uint32_t address, + uint32_t timeout) +{ + if (dummy > ((1 << ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH) - 1)) + { + return ALT_E_ERROR; + } + + uint32_t reg = ALT_QSPI_FLSHCMD_CMDOPCODE_SET(opcode) | + ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(dummy); + + reg |= ALT_QSPI_FLSHCMD_ENCMDADDR_SET(ALT_QSPI_FLSHCMD_ENCMDADDR_E_END); + reg |= ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3); + + alt_write_word(ALT_QSPI_FLSHCMDADDR_ADDR, address); + + return alt_qspi_stig_cmd_helper(reg, timeout); +} + +///// + +ALT_STATUS_CODE alt_qspi_device_wren(void) +{ + // Write enable through STIG (not required, auto send by controller during write) + return alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_WREN, 0, 10000); +} + +ALT_STATUS_CODE alt_qspi_device_wrdis(void) +{ + // Write disable through STIG (not required, auto send by controller during write) + return alt_qspi_stig_cmd(ALT_QSPI_STIG_OPCODE_WRDIS, 0, 10000); +} + +ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid) +{ + // Read flash device ID through STIG + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_RDID, 0, 4, rdid, 10000); +} + +ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param) +{ + // Read flash discovery parameters through STIG + + return alt_qspi_stig_rd_cmd(ALT_QSPI_STIG_OPCODE_DISCVR_PARAM, 8, 8, param, 10000); +} + +ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + dprintf("DEBUG[QSPI]: bank_select(): switching to bank 0x%" PRIu32 ".\n", bank); + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wren(); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_stig_wr_cmd(ALT_QSPI_STIG_OPCODE_WR_EXT_REG, 0, 1, &bank, 10000); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_qspi_device_wrdis(); + } + + return status; +} + +///// + +static bool alt_qspi_is_enabled(void) +{ + uint32_t cfg = alt_read_word(ALT_QSPI_CFG_ADDR); + + if (cfg & ALT_QSPI_CFG_EN_SET_MSK) + { + return true; + } + else + { + return false; + } +} + +ALT_STATUS_CODE alt_qspi_ecc_start(void * block, size_t size) +{ + if (size < (ALT_QSPI_PAGE_SIZE * 8)) + { + return ALT_E_ERROR; + } + + if (alt_qspi_is_enabled() == false) + { + return ALT_E_ERROR; + } + + if (alt_qspi_is_idle() == false) + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // 1. Configure SRAM Partition Register to 126 words for read, 2 words for write. + // 2. Enable ECC on QSPI RAM + // 3. Trigger an indirect read transfer that will fill up 126 words in FIFO by + // monitoring read FIFO fill level; Do not read out data through AHB. + // 4. Start AHB read and start indirect write operation to write back to the same + // device location, this will fill up and initilaize the write partition RAM. + // 5. To clear spurious interrupts, reset the QSPI controller. + + // Save the previous partition size + + uint32_t sram_orig = alt_qspi_sram_partition_get(); + dprintf("DEBUG[QSPI][ECC]: Save original SRAM as %" PRIu32 ".\n", sram_orig); + + // Step 1 + + uint32_t sram_fill = (1 << ALT_QSPI_SRAMPART_ADDR_WIDTH) - 2; + alt_qspi_sram_partition_set(sram_fill); + dprintf("DEBUG[QSPI][ECC]: Set new SRAM as %" PRIu32 ".\n", sram_fill); + + // Step 2 + + dprintf("DEBUG[QSPI][ECC]: Enable ECC in SysMgr.\n"); + alt_write_word(ALT_SYSMGR_ECC_QSPI_ADDR, ALT_SYSMGR_ECC_QSPI_EN_SET_MSK); + + // Step 3 + + // Issue a read ~ 2x larger than the read partition. We will read out 1 page, + // which will be used as the buffer to write back to QSPI. This way no data + // actually changes thus no erase will be needed. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Start indirect read PAGE * 8.\n"); + status = alt_qspi_indirect_read_start(0x0, ALT_QSPI_PAGE_SIZE * 8); + } + + // Read out 1 page for the write data + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Reading out 1 page ...\n"); + + uint32_t read_size = 0; + char * buffer = block; + while (read_size < ALT_QSPI_PAGE_SIZE) + { + uint32_t level = alt_qspi_indirect_read_fill_level(); + level = MIN(level, (ALT_QSPI_PAGE_SIZE - read_size) / sizeof(uint32_t)); + + uint32_t * data = (uint32_t *)(&buffer[read_size]); + for (uint32_t i = 0; i < level; ++i) + { + *data = alt_read_word(ALT_QSPIDATA_ADDR); + ++data; + } + + read_size += level * sizeof(uint32_t); + } + + if (read_size != ALT_QSPI_PAGE_SIZE) + { + status = ALT_E_ERROR; + } + } + + // Wait for read FIFO to report it is up to the specified fill level. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Waiting for read fill level ...\n"); + + uint32_t timeout = 10000; + + while (alt_qspi_indirect_read_fill_level() < sram_fill) + { + if (--timeout == 0) + { + dprintf("DEBUG[QSPI][ECC]: Waiting for read fill timeout !!!\n"); + status = ALT_E_TMO; + break; + } + } + } + + // Step 4 + + // Issue a write of 1 page of the same data from 0x0. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Start indirect write PAGE.\n"); + status = alt_qspi_indirect_write_start(0x0, ALT_QSPI_PAGE_SIZE); + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Writing in 1 page ...\n"); + + uint32_t write_size = 0; + char * buffer = block; + + while (write_size < ALT_QSPI_PAGE_SIZE) + { + uint32_t space = 2 - alt_qspi_indirect_write_fill_level(); + if (space == 0) + { + dprintf("DEBUG[QSPI][ECC]: Write FIFO filled at write_size = %" PRIu32 ".\n", write_size); + // Space = 0; which means all 2 positions in the write FIFO is filled, + // meaning it has been initialized with respect to ECC. + break; + } + + space = MIN(space, (ALT_QSPI_PAGE_SIZE - write_size) / sizeof(uint32_t)); + + uint32_t * data = (uint32_t *)(&buffer[write_size]); + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_QSPIDATA_ADDR, *data); + ++data; + } + + write_size += space * sizeof(uint32_t); + } + + if (write_size != ALT_QSPI_PAGE_SIZE) + { + dprintf("DEBUG[QSPI][ECC]: Cancel indirect write.\n"); + status = alt_qspi_indirect_write_cancel(); + } + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Finish indirect write.\n"); + status = alt_qspi_indirect_write_finish(); + } + + // Cancel the indirect read as it has initialized the read FIFO partition. + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Cancel indirect read.\n"); + status = alt_qspi_indirect_read_cancel(); + } + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Finish indirect read.\n"); + status = alt_qspi_indirect_read_finish(); + } + + // Step 5 + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Clear any pending spurious QSPI ECC interrupts.\n"); + + alt_write_word(ALT_SYSMGR_ECC_QSPI_ADDR, + ALT_SYSMGR_ECC_QSPI_EN_SET_MSK + | ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK + | ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK); + } + + ///// + + // Restore original partition + + if (status == ALT_E_SUCCESS) + { + dprintf("DEBUG[QSPI][ECC]: Restore original SRAM as %" PRIu32 ".\n", sram_orig); + status = alt_qspi_sram_partition_set(sram_orig); + } + + return status; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_reset_manager.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_reset_manager.c new file mode 100644 index 000000000..47303e42a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_reset_manager.c @@ -0,0 +1,135 @@ + +/****************************************************************************** +* +* alt_reset_manager.c - API for the Altera SoC FPGA reset manager. +* +******************************************************************************/ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "alt_reset_manager.h" +#include "socal/socal.h" +#include "socal/hps.h" +#include "socal/alt_rstmgr.h" + +///// + + +uint32_t alt_reset_event_get(void) +{ + return alt_read_word(ALT_RSTMGR_STAT_ADDR); +} + +ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask) +{ + alt_write_word(ALT_RSTMGR_STAT_ADDR, event_mask); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_reset_cold_reset(void) +{ + alt_write_word(ALT_RSTMGR_CTL_ADDR, ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK); + return ALT_E_SUCCESS; +} + +ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay, + uint32_t nRST_pin_clk_assertion, + bool sdram_refresh_enable, + bool fpga_mgr_handshake, + bool scan_mgr_handshake, + bool fpga_handshake, + bool etr_stall) +{ + // Cached register values + uint32_t ctrl_reg = ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK; + uint32_t counts_reg = 0; + + ///// + + // Validate warm_reset_delay is above 16 and below the field width + if ((warm_reset_delay < 16) || (warm_reset_delay >= (1 << ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH))) + { + return ALT_E_BAD_ARG; + } + + // Validate nRST_pin_clk_assertion delay is non-zero and below the field width + if (!nRST_pin_clk_assertion) + { + return ALT_E_ERROR; + } + if (nRST_pin_clk_assertion >= (1 << ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH)) + { + return ALT_E_BAD_ARG; + } + + // Update counts register with warm_reset_delay information + counts_reg |= ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(warm_reset_delay); + + // Update counts register with nRST_pin_clk_assertion information + counts_reg |= ALT_RSTMGR_COUNTS_NRSTCNT_SET(nRST_pin_clk_assertion); + + ///// + + // Update ctrl register with the specified option flags + + if (sdram_refresh_enable) + { + ctrl_reg |= ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK; + } + + if (fpga_mgr_handshake) + { + ctrl_reg |= ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK; + } + + if (scan_mgr_handshake) + { + ctrl_reg |= ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK; + } + + if (fpga_handshake) + { + ctrl_reg |= ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK; + } + + if (etr_stall) + { + ctrl_reg |= ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK; + } + + ///// + + // Commit registers to hardware + alt_write_word(ALT_RSTMGR_COUNTS_ADDR, counts_reg); + alt_write_word(ALT_RSTMGR_CTL_ADDR, ctrl_reg); + + return ALT_E_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_sdmmc.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_sdmmc.c new file mode 100644 index 000000000..3386dcc08 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_sdmmc.c @@ -0,0 +1,2529 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_sdmmc.h" +#include "alt_clock_manager.h" +#include "alt_reset_manager.h" +#include "socal/alt_sdmmc.h" +#include "socal/alt_rstmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" +#include + +///// + +//#define LOGGER +// NOTE: To enable debugging output, delete the next line and uncomment the +// line after. +//#define dprintf(...) +#define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) +#ifdef LOGGER +#endif + +///// + +#define MIN(a, b) ((a) > (b) ? (b) : (a)) +#define ARRAY_COUNT(array) (sizeof(array) / sizeof(array[0])) + +///// + +// Timeout for reset manager +#define ALT_SDMMC_RESET_TMO_INIT 8192 +// Timeout for disable device +#define ALT_SDMMC_MAX_T_POLL_COUNT 8192 +// Timeout for waiting event +#define ALT_SDMMC_TMO_WAITER 1000000 + +#define ALT_SDMMC_DMA_SEGMENT_SIZE 512 +#define ALT_SDMMC_DMA_DESC_COUNT 128 + +#define ALT_SDMMC_FSM_IDLE 0 +#define ALT_SDMMC_DMA_FSM_IDLE 0 + +#define ALT_SDMMC_CSD_MAX_R_BLK_MSK 0x000F0000 +#define ALT_SDMMC_CSD_MAX_W_BLK_MSK 0x03C00000 +#define ALT_SDMMC_CSD_PART_R_ALLOW_MSK 0x00008000 +#define ALT_SDMMC_CSD_PART_W_ALLOW_MSK 0x00200000 +#define ALT_SDMMC_CSD_SPEED_RATE_MSK 0x00000007 +#define ALT_SDMMC_CSD_SPEED_TIME_MSK 0x00000078 +#define ALT_SDMMC_CSD_MAX_R_BLK_GET(val) ((val & ALT_SDMMC_CSD_MAX_R_BLK_MSK) >> 16) +#define ALT_SDMMC_CSD_MAX_W_BLK_GET(val) ((val & ALT_SDMMC_CSD_MAX_W_BLK_MSK) >> 22) +#define ALT_SDMMC_CSD_PART_R_ALLOW_GET(val) ((val & ALT_SDMMC_CSD_PART_R_ALLOW_MSK) >> 15) +#define ALT_SDMMC_CSD_PART_W_ALLOW_GET(val) ((val & ALT_SDMMC_CSD_PART_W_ALLOW_MSK) >> 21) +#define ALT_SDMMC_CSD_SPEED_RATE_GET(val) ((val & ALT_SDMMC_CSD_SPEED_RATE_MSK) >> 0) +#define ALT_SDMMC_CSD_SPEED_TIME_GET(val) ((val & ALT_SDMMC_CSD_SPEED_TIME_MSK) >> 3) +typedef enum ALT_SDMMC_TMOD_e +{ + ALT_SDMMC_TMOD_READ = 0, + ALT_SDMMC_TMOD_WRITE = 1, +} ALT_SDMMC_TMOD_t; + +#ifdef LOGGER +uint32_t log_buffer[1000] = { 0 }; +uint32_t log_index = 0; + +#define D_ADD_VALUE(value)({if (log_index < 1000) log_buffer[log_index++] = value;}) +#endif + +static alt_freq_t clock_freq; + +// Default configurations of used commands +static ALT_SDMMC_CMD_CONFIG_t cmd_default_cfg[20] = +{ + { + .cmd_index = ALT_SDMMC_WRITE_MULTIPLE_BLOCK, + .send_auto_stop = true, + .response_expect = true, + .data_expected = 1, + .write_active = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_READ_MULTIPLE_BLOCK, + .send_auto_stop = true, + .response_expect = true, + .data_expected = 1, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SD_SEND_SCR, + .response_expect = true, + .data_expected = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_WRITE_BLOCK, + .response_expect = true, + .data_expected = true, + .write_active = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_READ_SINGLE_BLOCK, + .response_expect = true, + .data_expected = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_SET_BLOCKLEN, + .response_expect = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_SEL_DES_CARD, + .response_expect = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_APP_CMD, + .response_expect = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SD_SET_BUS_WIDTH, + .response_expect = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SD_SEND_OP_COND, + .response_expect = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_SEND_OP_COND, + .response_expect = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_IF_COND, + .response_expect = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_SET_RELATIVE_ADDR, + .response_expect = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_SEND_STATUS, + .response_expect = true, + .card_number = 0, + .use_hold_reg = true + }, + { + .cmd_index = ALT_SDMMC_ALL_SEND_CID, + .response_expect = true, + .response_length_long = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_SEND_CID, + .response_expect = true, + .response_length_long = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_SEND_CSD, + .response_expect = true, + .response_length_long = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_STOP_TRANSMISSION, + .stop_abort_cmd = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + }, + { + .cmd_index = ALT_SDMMC_GO_IDLE_STATE, + .send_initialization = true, + .card_number = 0, + .use_hold_reg = true, + .wait_prvdata_complete = true + } +}; + +static ALT_SDMMC_CMD_CONFIG_t cmd_clock_cfg = +{ + .update_clock_registers_only = true, + .wait_prvdata_complete = true +}; + +static uint32_t rca_number; /*!< Relative card address. */ +static ALT_SDMMC_DMA_BUF_DESC_t dma_descriptors[ALT_SDMMC_DMA_DESC_COUNT]; + /*!< Array of dma descriptors. */ +static ALT_SDMMC_DMA_BUF_DESC_t *dma_cur_descr; + /*!< Current decriptor. */ + +// +// Reset sdmmc module by reset manager without deassert +// +static ALT_STATUS_CODE alt_sdmmc_rstmgr_set(void) +{ + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK); + + return ALT_E_SUCCESS; +} + +// +// Assert reset sdmmc module by reset manager, wait, deasert +// +static ALT_STATUS_CODE alt_sdmmc_rstmgr_strobe(void) +{ + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK); + + volatile uint32_t timeout = ALT_SDMMC_RESET_TMO_INIT; + + // Wait while sdmmc module is reseting + while (timeout--) + ; + + // Deassert the appropriate sdmmc module reset signal via the Reset Manager Peripheral Reset register. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK); + + return ALT_E_SUCCESS; +} + +// +// Initialize descriptor chain for dma +// +static ALT_STATUS_CODE alt_sdmmc_desc_chain_init() +{ + ALT_SDMMC_DMA_BUF_DESC_t * dma_desc = dma_descriptors; + + // Initialising descriptor chain + for (uint32_t count = 0; count < ALT_SDMMC_DMA_DESC_COUNT; count++) + { + dma_desc[count].des0.fld.own = 0; + dma_desc[count].des0.fld.ch = 1; + dma_desc[count].des0.fld.er = 0; + dma_desc[count].des1.fld.bs1 = 0; + dma_desc[count].des2.fld.bap1 = 0; + + // Create chain description list + if (count == (ALT_SDMMC_DMA_DESC_COUNT - 1)) + { + // If it is latest element set pointer to the ring head. + dma_desc[count].des3.fld.bap2_or_next = (uint32_t) dma_desc; + } + else + { + // Set pointer to the next element in the ring + dma_desc[count].des3.fld.bap2_or_next = (uint32_t) (&dma_desc[count + 1]); + } + } + + dma_cur_descr = dma_desc; + + return ALT_E_SUCCESS; +} + +// +// Clear descriptors of chain for dma operations +// +static ALT_STATUS_CODE alt_sdmmc_desc_chain_clear() +{ + ALT_SDMMC_DMA_BUF_DESC_t * dma_desc = dma_descriptors; + + // Clean descriptions + for (uint32_t count = 0; count < ALT_SDMMC_DMA_DESC_COUNT; count++) + { + dma_desc[count].des0.fld.own = 0; + dma_desc[count].des0.fld.dic = 0; + dma_desc[count].des0.fld.ld = 0; + dma_desc[count].des0.fld.fs = 0; + dma_desc[count].des1.fld.bs1 = 0; + dma_desc[count].des2.fld.bap1 = 0; + } + + dma_cur_descr = dma_desc; + + return ALT_E_SUCCESS; +} + +// +// Initialize the specified sdmmc controller instance for use and return a device +// handle referencing it. +// +ALT_STATUS_CODE alt_sdmmc_init() +{ + if (alt_clk_is_enabled(ALT_CLK_SDMMC) != ALT_E_TRUE) + { + return ALT_E_BAD_CLK; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Query the SDMMC clock. + if (status == ALT_E_SUCCESS) + { + status = alt_clk_freq_get(ALT_CLK_SDMMC, &clock_freq); + } + + // Reset sdmmc module + if (status == ALT_E_SUCCESS) + { + status = alt_sdmmc_reset(); + } + + return status; +} + +// +//Reset the SD/MMC controller by stopping any data transfers in progress and +//putting the controller into reset and reinit it after reset complete. +// +ALT_STATUS_CODE alt_sdmmc_reset() +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + bool already_enabled = (alt_sdmmc_card_pwr_is_on() == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily power off the card + status = alt_sdmmc_card_pwr_off(); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + // Reset sdmmc module by reset manager + alt_sdmmc_rstmgr_strobe(); + + if (already_enabled) + { + // Re-enable card power + status = alt_sdmmc_card_pwr_on(); + } + + // Relative card address have not readed yet + rca_number = 0; + // Init description chain + alt_sdmmc_desc_chain_init(); + + if (status == ALT_E_SUCCESS) + { + //Enable default clock for working alt_sdmmc_command_send + alt_write_word(ALT_SDMMC_CLKENA_ADDR, ALT_SDMMC_CLKENA_CCLK_EN_SET(true)); + status = alt_sdmmc_command_send(ALT_SDMMC_CLK_INDEX, 0x0, NULL); + } + + return status; +} + +// +// Uninitialize the sdmmc controller referenced by the sdmmc_dev handle. +// +ALT_STATUS_CODE alt_sdmmc_uninit(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Clean descriptor chain + alt_sdmmc_desc_chain_clear(); + + // Card power off + if (status == ALT_E_SUCCESS) + { + status = alt_sdmmc_card_pwr_off(); + } + + // Reset sdmmc module by reset manager + if (status == ALT_E_SUCCESS) + { + status = alt_sdmmc_rstmgr_set(); + } + + return status; +} + +// +// Power on of the card. +// +ALT_STATUS_CODE alt_sdmmc_card_pwr_on(void) +{ + alt_setbits_word(ALT_SDMMC_PWREN_ADDR, + ALT_SDMMC_PWREN_POWER_EN_SET_MSK); + + return ALT_E_SUCCESS; +} + +// +//Power off of the card. +// +ALT_STATUS_CODE alt_sdmmc_card_pwr_off(void) +{ + //If sdmmc controller is enabled, return with sucess + if (alt_sdmmc_card_pwr_is_on() == ALT_E_FALSE) + { + return ALT_E_SUCCESS; + } + + //Else clear enable bit of sdmmc_enable register + alt_clrbits_word(ALT_SDMMC_PWREN_ADDR, + ALT_SDMMC_PWREN_POWER_EN_SET_MSK); + + // Clear interrupt status + alt_sdmmc_int_clear(ALT_SDMMC_INT_STATUS_ALL); + + // Relative card address have not readed yet + rca_number = 0; + // Reset state of card stack + return ALT_E_SUCCESS; +} + +// +// Check whether sdmmc controller is enable +// +bool alt_sdmmc_card_pwr_is_on(void) +{ + if (ALT_SDMMC_PWREN_POWER_EN_GET(alt_read_word(ALT_SDMMC_PWREN_ADDR)) == + ALT_SDMMC_PWREN_POWER_EN_E_ON) + { + return true; + } + else + { + return false; + } +} + +// +// Returns ALT_E_TRUE if the sdmmc controller is busy +// +static ALT_STATUS_CODE alt_sdmmc_is_busy(void) +{ + if (ALT_SDMMC_STAT_DATA_BUSY_GET(alt_read_word(ALT_SDMMC_STAT_ADDR)) == + ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns ALT_E_TRUE if the sdmmc and iddmac controller is in idle state +// +static ALT_STATUS_CODE alt_sdmmc_is_idle(void) +{ + uint32_t mmc_state = ALT_SDMMC_STAT_CMD_FSM_STATES_GET(alt_read_word(ALT_SDMMC_STAT_ADDR)); + + uint32_t dma_state = ALT_SDMMC_IDSTS_FSM_GET(alt_read_word(ALT_SDMMC_IDSTS_ADDR)); + + if ((mmc_state != ALT_SDMMC_FSM_IDLE) || (dma_state != ALT_SDMMC_DMA_FSM_IDLE)) + { +#ifdef LOGGER + dprintf("\nstate %x dma_state %x\n", (int)mmc_state, (int)dma_state); +#endif + return ALT_E_FALSE; + } + else + { + return ALT_E_TRUE; + } +} + +// +// Get config clock parameters +// +uint32_t alt_sdmmc_card_clk_div_get(void) +{ + return ALT_SDMMC_CLKDIV_CLK_DIVR0_GET(alt_read_word(ALT_SDMMC_CLKDIV_ADDR)); +} + +// +// Set config clock parameters (7.2.3 Clock Programming) +// +ALT_STATUS_CODE alt_sdmmc_card_clk_div_set(const uint32_t clk_div) +{ + if (alt_sdmmc_is_busy() == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + alt_write_word(ALT_SDMMC_CLKDIV_ADDR, ALT_SDMMC_CLKDIV_CLK_DIVR0_SET(clk_div)); + + return alt_sdmmc_command_send(ALT_SDMMC_CLK_INDEX, 0x0, NULL); +} + +uint32_t alt_sdmmc_card_speed_get(void) +{ + uint32_t clk_div = alt_sdmmc_card_clk_div_get(); + + uint32_t speed_bps = clock_freq / (2 * clk_div); + + return speed_bps; +} + +ALT_STATUS_CODE alt_sdmmc_card_speed_set(uint32_t xfer_speed) +{ + uint32_t clk_div = clock_freq / (2 * xfer_speed); + + return alt_sdmmc_card_clk_div_set(clk_div); +} + +ALT_STATUS_CODE alt_sdmmc_card_clk_disable(void) +{ + if (alt_sdmmc_is_busy() == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + alt_write_word(ALT_SDMMC_CLKENA_ADDR, ALT_SDMMC_CLKENA_CCLK_EN_SET(false)); + + return alt_sdmmc_command_send(ALT_SDMMC_CLK_INDEX, 0x0, NULL); +} + +// +// Enables the card clock (sdmmc_cclk_out). +// +ALT_STATUS_CODE alt_sdmmc_card_clk_enable(const bool use_low_pwr_mode) +{ + if (alt_sdmmc_is_busy() == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + // Enable clock + alt_write_word(ALT_SDMMC_CLKENA_ADDR, ALT_SDMMC_CLKENA_CCLK_EN_SET(true) + | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET(use_low_pwr_mode)); + + return alt_sdmmc_command_send(ALT_SDMMC_CLK_INDEX, 0x0, NULL); +} + +// +// Returns true if the card clock (sdmmc_cclk_out) is enabled otherwise returns +// +bool alt_sdmmc_card_clk_is_enabled(void) +{ + return ALT_SDMMC_CLKENA_CCLK_EN_GET(alt_read_word(ALT_SDMMC_CLKENA_ADDR)); +} + +// +// Get sdmmc bus width +// +static ALT_SDMMC_BUS_WIDTH_t alt_sdmmc_bus_width_get(void) +{ + uint32_t ctype_register = alt_read_word(ALT_SDMMC_CTYPE_ADDR); + + uint16_t card_width1 = ALT_SDMMC_CTYPE_CARD_WIDTH1_GET(ctype_register); + uint16_t card_width2 = ALT_SDMMC_CTYPE_CARD_WIDTH2_GET(ctype_register); + + if (card_width1 == ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT) + { + return ALT_SDMMC_BUS_WIDTH_8; + } + else if (card_width2 == ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT) + { + return ALT_SDMMC_BUS_WIDTH_4; + } + else + { + return ALT_SDMMC_BUS_WIDTH_1; + } +} + +// +// Set sdmmc bus width +// +static ALT_STATUS_CODE alt_sdmmc_bus_width_set(const ALT_SDMMC_BUS_WIDTH_t width) +{ + // Set config parameters to appropriate registers + switch (width) + { + case ALT_SDMMC_BUS_WIDTH_8: + alt_replbits_word(ALT_SDMMC_CTYPE_ADDR, + ALT_SDMMC_CTYPE_CARD_WIDTH1_SET_MSK, + ALT_SDMMC_CTYPE_CARD_WIDTH1_SET(ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT)); + break; + + case ALT_SDMMC_BUS_WIDTH_4: + alt_replbits_word(ALT_SDMMC_CTYPE_ADDR, + ALT_SDMMC_CTYPE_CARD_WIDTH1_SET_MSK, + ALT_SDMMC_CTYPE_CARD_WIDTH1_SET(ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT)); + alt_replbits_word(ALT_SDMMC_CTYPE_ADDR, + ALT_SDMMC_CTYPE_CARD_WIDTH2_SET_MSK, + ALT_SDMMC_CTYPE_CARD_WIDTH2_SET(ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT)); + break; + + case ALT_SDMMC_BUS_WIDTH_1: + alt_replbits_word(ALT_SDMMC_CTYPE_ADDR, + ALT_SDMMC_CTYPE_CARD_WIDTH1_SET_MSK, + ALT_SDMMC_CTYPE_CARD_WIDTH1_SET(ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT)); + alt_replbits_word(ALT_SDMMC_CTYPE_ADDR, + ALT_SDMMC_CTYPE_CARD_WIDTH2_SET_MSK, + ALT_SDMMC_CTYPE_CARD_WIDTH2_SET(ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT)); + break; + + default: + return ALT_E_BAD_ARG; + } + + return ALT_E_SUCCESS; +} + +// +// Get block size +// +inline static uint16_t alt_sdmmc_block_size_get(void) +{ + uint32_t blksiz_register = alt_read_word(ALT_SDMMC_BLKSIZ_ADDR); + return ALT_SDMMC_BLKSIZ_BLOCK_SIZE_GET(blksiz_register); +} + +// +// Set block size +// +inline static ALT_STATUS_CODE alt_sdmmc_block_size_set(uint16_t block_size) +{ + alt_replbits_word(ALT_SDMMC_BLKSIZ_ADDR, + ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET_MSK, + ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET(block_size)); + + return ALT_E_SUCCESS; +} + +// +// Set byte count +// +inline static ALT_STATUS_CODE alt_sdmmc_byte_count_set(uint32_t count) +{ + alt_replbits_word(ALT_SDMMC_BYTCNT_ADDR, + ALT_SDMMC_BYTCNT_BYTE_COUNT_SET_MSK, + ALT_SDMMC_BYTCNT_BYTE_COUNT_SET(count)); + + return ALT_E_SUCCESS; +} + +// +// Get sdmmc timeouts for command response and data sending +// +ALT_STATUS_CODE alt_sdmmc_card_misc_get(ALT_SDMMC_CARD_MISC_t *card_misc_cfg) +{ + uint32_t tmout_register = alt_read_word(ALT_SDMMC_TMOUT_ADDR); + + card_misc_cfg->response_timeout = ALT_SDMMC_TMOUT_RESPONSE_TMO_GET(tmout_register); + card_misc_cfg->data_timeout = ALT_SDMMC_TMOUT_DATA_TMO_GET(tmout_register); + + card_misc_cfg->card_width = alt_sdmmc_bus_width_get(); + card_misc_cfg->block_size = alt_sdmmc_block_size_get(); + + card_misc_cfg->debounce_count = ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_GET(alt_read_word(ALT_SDMMC_DEBNCE_ADDR)); + + return ALT_E_SUCCESS; +} + +// +//Set sdmmc timeouts for command response and data sending +// +ALT_STATUS_CODE alt_sdmmc_card_misc_set(const ALT_SDMMC_CARD_MISC_t *card_misc_cfg) +{ + uint32_t tmout_value = ALT_SDMMC_TMOUT_RESPONSE_TMO_SET(card_misc_cfg->response_timeout) + | ALT_SDMMC_TMOUT_DATA_TMO_SET(card_misc_cfg->data_timeout); + + alt_write_word(ALT_SDMMC_TMOUT_ADDR, tmout_value); + + alt_replbits_word(ALT_SDMMC_DEBNCE_ADDR, + ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET_MSK, + ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET(card_misc_cfg->debounce_count)); + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + status = alt_sdmmc_bus_width_set(card_misc_cfg->card_width); + } + + if (status == ALT_E_SUCCESS) + { + status = alt_sdmmc_block_size_set(card_misc_cfg->block_size); + } + + return status; +} + +// +// Starts the SD/MMC internal DMA transfer with the specified +// descriptor an bus mode transfer configuration. +// +ALT_STATUS_CODE alt_sdmmc_dma_start(ALT_SDMMC_DMA_BUF_DESC_t *buf_desc_list, + const uint32_t desc_skip_len, + const ALT_SDMMC_DMA_PBL_t burst_len, + const bool use_fixed_burst) +{ + uint32_t bmod_set_value = ALT_SDMMC_BMOD_PBL_SET(burst_len) + | ALT_SDMMC_BMOD_FB_SET(use_fixed_burst) + | ALT_SDMMC_BMOD_DSL_SET(desc_skip_len); + + uint32_t bmod_set_mask = ALT_SDMMC_BMOD_PBL_SET_MSK + | ALT_SDMMC_BMOD_FB_SET_MSK + | ALT_SDMMC_BMOD_DSL_SET_MSK; + + alt_replbits_word(ALT_SDMMC_BMOD_ADDR, bmod_set_mask, bmod_set_value); + + // Set start address of descriptor chain + alt_write_word(ALT_SDMMC_DBADDR_ADDR, (uint32_t)buf_desc_list); + + return ALT_E_SUCCESS; +} + +// +// Enables the sdmmc write protect. +// +bool alt_sdmmc_card_is_write_protected(void) +{ + alt_setbits_word(ALT_SDMMC_WRTPRT_ADDR, + ALT_SDMMC_WRTPRT_WR_PROTECT_SET_MSK); + + return ALT_E_SUCCESS; +} + +// +// FIFO reset +// +ALT_STATUS_CODE alt_sdmmc_fifo_reset(void) +{ + uint32_t timeout = ALT_SDMMC_MAX_T_POLL_COUNT; + + // Activate fifo reset + alt_setbits_word(ALT_SDMMC_CTL_ADDR, ALT_SDMMC_CTL_FIFO_RST_SET_MSK); + + // Wait to complete reset or timeout + while (ALT_SDMMC_CTL_FIFO_RST_GET(alt_read_word(ALT_SDMMC_CTL_ADDR)) + && --timeout) + ; + + // If fifo reset still are active, return timeout error + if (timeout == 0) + { + return ALT_E_TMO; + } + + return ALT_E_SUCCESS; +} + +// +// DMA reset +// +ALT_STATUS_CODE alt_sdmmc_dma_reset(void) +{ + uint32_t timeout = ALT_SDMMC_MAX_T_POLL_COUNT; + + //Activate dma reset + alt_setbits_word(ALT_SDMMC_CTL_ADDR, ALT_SDMMC_CTL_DMA_RST_SET_MSK); + + // Wait to complete reset or timeout + while (ALT_SDMMC_CTL_DMA_RST_GET(alt_read_word(ALT_SDMMC_CTL_ADDR)) + && --timeout) + ; + + // If dma reset still are active, return timeout error + if (timeout == 0) + { + return ALT_E_TMO; + } + + return ALT_E_SUCCESS; +} + + +// +// Returns ALT_E_TRUE if the sdmmc controller is present depend on cdata_in. +// +bool alt_sdmmc_card_is_detected(void) +{ + if (ALT_SDMMC_STAT_DATA_3_STAT_GET(alt_read_word(ALT_SDMMC_STAT_ADDR)) == + ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT) +// if (ALT_SDMMC_CDETECT_CARD_DETECT_N_GET(alt_read_word(ALT_SDMMC_CDETECT_ADDR)) +// == ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED) + { + return true; + } + else + { + return false; + } +} + +// +//Set command configuration +// +static ALT_STATUS_CODE alt_sdmmc_cmd_set(const ALT_SDMMC_CMD_INDEX_t cmd_index, + const ALT_SDMMC_CMD_CONFIG_t *cmd_cfg, + bool start_cmd) +{ + uint32_t cmd_register = ALT_SDMMC_CMD_CMD_INDEX_SET(cmd_index) + | ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(cmd_cfg->response_expect) + | ALT_SDMMC_CMD_RESPONSE_LEN_SET(cmd_cfg->response_length_long) + | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(cmd_cfg->check_response_crc) + | ALT_SDMMC_CMD_DATA_EXPECTED_SET(cmd_cfg->data_expected) + | ALT_SDMMC_CMD_RD_WR_SET(cmd_cfg->write_active) + | ALT_SDMMC_CMD_TFR_MOD_SET(cmd_cfg->stream_mode_active) + | ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(cmd_cfg->send_auto_stop) + | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(cmd_cfg->wait_prvdata_complete) + | ALT_SDMMC_CMD_STOP_ABT_CMD_SET(cmd_cfg->stop_abort_cmd) + | ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(cmd_cfg->send_initialization) + | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET(cmd_cfg->update_clock_registers_only) + | ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET(cmd_cfg->read_ceata_device) + | ALT_SDMMC_CMD_CCS_EXPECTED_SET(cmd_cfg->ccs_expected) + | ALT_SDMMC_CMD_EN_BOOT_SET(cmd_cfg->enable_boot) + | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(cmd_cfg->expect_boot_ack) + | ALT_SDMMC_CMD_DIS_BOOT_SET(cmd_cfg->disable_boot) + | ALT_SDMMC_CMD_BOOT_MOD_SET(cmd_cfg->boot_mode) + | ALT_SDMMC_CMD_VOLT_SWITCH_SET(cmd_cfg->volt_switch) + | ALT_SDMMC_CMD_USE_HOLD_REG_SET(cmd_cfg->use_hold_reg) + | ALT_SDMMC_CMD_START_CMD_SET(start_cmd); + + alt_write_word(ALT_SDMMC_CMD_ADDR, cmd_register); + +#ifdef LOGGER + dprintf("\ncommand = %X\n", (int)cmd_register); +#endif + + return ALT_E_SUCCESS; +} + +// +// Set command argument +// +inline static ALT_STATUS_CODE alt_sdmmc_cmd_arg_set(uint32_t cmdarg) +{ + alt_write_word(ALT_SDMMC_CMDARG_ADDR, cmdarg); + + return ALT_E_SUCCESS; +} + +// +// Get response previous command. +// +inline static ALT_STATUS_CODE alt_sdmmc_read_short_response(uint32_t *response) +{ + uint32_t resp0 = alt_read_word(ALT_SDMMC_RESP0_ADDR); + *response = (uint32_t)(ALT_SDMMC_RESP0_RESPONSE0_GET(resp0)); + + return ALT_E_SUCCESS; +} + +// +// Get long response of previous command. +// +ALT_STATUS_CODE alt_sdmmc_read_long_response(ALT_SDMMC_RESPONSE_t *response) +{ + uint32_t resp0 = alt_read_word(ALT_SDMMC_RESP0_ADDR); + uint32_t resp1 = alt_read_word(ALT_SDMMC_RESP1_ADDR); + uint32_t resp2 = alt_read_word(ALT_SDMMC_RESP2_ADDR); + uint32_t resp3 = alt_read_word(ALT_SDMMC_RESP3_ADDR); + + response->resp0 = (uint32_t)(ALT_SDMMC_RESP0_RESPONSE0_GET(resp0)); + response->resp1 = (uint32_t)(ALT_SDMMC_RESP1_RESPONSE1_GET(resp1)); + response->resp2 = (uint32_t)(ALT_SDMMC_RESP2_RESPONSE2_GET(resp2)); + response->resp3 = (uint32_t)(ALT_SDMMC_RESP3_RESPONSE3_GET(resp3)); + + return ALT_E_SUCCESS; +} + +// +//This function reads a single data byte from the receive FIFO. +// +ALT_STATUS_CODE alt_sdmmc_fifo_read(void *dest, const size_t size) +{ + uint32_t * dest_ptr = dest; + for (int counter = 0; counter < size / 4; counter++) + { + dest_ptr[counter] = (uint32_t)(ALT_SDMMC_DATA_VALUE_GET(alt_read_word(ALT_SDMMC_DATA_ADDR))); + } + + if (size & 0x3) + { + uint8_t * add_dest_ptr = (uint8_t*)dest + (size / 4); + uint32_t word_notfull = (uint32_t)(ALT_SDMMC_DATA_VALUE_GET(alt_read_word(ALT_SDMMC_DATA_ADDR))); + + for (int counter = 0; counter < (size & 0x3); counter++) + { + add_dest_ptr[counter] = (uint8_t)word_notfull; + word_notfull = word_notfull >> 8; + } + } + + return ALT_E_SUCCESS; +} + +// +// This function writes a single data byte to the transmit FIFO. +// +ALT_STATUS_CODE alt_sdmmc_fifo_write(const void *src, const size_t size) +{ + const uint32_t * src_ptr = src; + for (int counter = 0; counter < size / 4; counter++) + { + alt_write_word(ALT_SDMMC_DATA_ADDR, ALT_SDMMC_DATA_VALUE_SET(src_ptr[counter])); + } + + if (size & 0x3) + { + const uint8_t *add_src_ptr = (uint8_t*)src + (size / 4); + uint32_t word_notfull = 0; + + for (int counter = 0; counter < (size & 0x3); counter++) + { + word_notfull |= (uint32_t)add_src_ptr[counter] << (8 * counter); + } + + alt_write_word(ALT_SDMMC_DATA_ADDR, ALT_SDMMC_DATA_VALUE_SET(word_notfull)); + } + + return ALT_E_SUCCESS; +} + +// +// Returns the current sdmmc controller interrupt status conditions. +// +uint32_t alt_sdmmc_int_status_get(void) +{ + return alt_read_word(ALT_SDMMC_MINTSTS_ADDR); +} + +// +// Returns the sdmmc controller raw interrupt status conditions irrespective of +// the interrupt status condition enablement state. +// +uint32_t alt_sdmmc_int_mask_get(void) +{ + return alt_read_word(ALT_SDMMC_INTMSK_ADDR); +} + +// +// Clears the specified sdmmc controller interrupt status conditions identified +// in the mask. +// +ALT_STATUS_CODE alt_sdmmc_int_clear(const uint32_t mask) +{ + alt_write_word(ALT_SDMMC_RINTSTS_ADDR, mask); + + return ALT_E_SUCCESS; +} + +// +// Disable the specified sdmmc controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_sdmmc_int_disable(const uint32_t mask) +{ + alt_clrbits_word(ALT_SDMMC_INTMSK_ADDR, mask); + + return ALT_E_SUCCESS; +} + +// +// Enable the specified sdmmc controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_sdmmc_int_enable(const uint32_t mask) +{ + if (mask & 0x0001ffff) + { + alt_setbits_word(ALT_SDMMC_CTL_ADDR, + ALT_SDMMC_CTL_INT_EN_SET_MSK); + + alt_setbits_word(ALT_SDMMC_INTMSK_ADDR, mask); + } + return ALT_E_SUCCESS; +} + +// +//Returns true if SD/MMC controller FIFO has reached the receive watermark level +//otherwise returns false. +// +bool alt_sdmmc_fifo_is_rx_wtrmk_reached(void) +{ + if (ALT_SDMMC_STAT_FIFO_RX_WATERMARK_GET(alt_read_word(ALT_SDMMC_STAT_ADDR)) == + ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK) + { + return true; + } + else + { + return false; + } +} + +// +//Returns true if SD/MMC controller FIFO has reached the transmit watermark level +//otherwise returns false. +// +bool alt_sdmmc_fifo_is_tx_wtrmk_reached(void) +{ + if (ALT_SDMMC_STAT_FIFO_TX_WATERMARK_GET(alt_read_word(ALT_SDMMC_STAT_ADDR)) == + ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK) + { + return true; + } + else + { + return false; + } +} + +// +// Returns ALT_E_TRUE when the receive FIFO is empty. +// +bool alt_sdmmc_fifo_is_empty(void) +{ + if (ALT_SDMMC_STAT_FIFO_EMPTY_GET(alt_read_word(ALT_SDMMC_STAT_ADDR)) == + ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY) + { + return true; + } + else + { + return false; + } +} + +// +// Returns ALT_E_TRUE when the receive FIFO is completely full. +// +bool alt_sdmmc_fifo_is_full(void) +{ + if (ALT_SDMMC_STAT_FIFO_FULL_GET(alt_read_word(ALT_SDMMC_STAT_ADDR)) == + ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL) + { + return true; + } + else + { + return false; + } +} + +// +// Returns the number of valid entries in the receive FIFO. +// +int32_t alt_sdmmc_fifo_count(void) +{ + return (int32_t)ALT_SDMMC_STAT_FIFO_COUNT_GET(alt_read_word(ALT_SDMMC_STAT_ADDR)); +} + +// +// Gets the configured FIFO operational parameter values. +// +ALT_STATUS_CODE alt_sdmmc_fifo_param_get(uint32_t *rx_wtrmk, uint32_t *tx_wtrmk, ALT_SDMMC_MULT_TRANS_t *mult_trans_size) +{ + uint32_t fifoth = alt_read_word(ALT_SDMMC_FIFOTH_ADDR); + + *rx_wtrmk = ALT_SDMMC_FIFOTH_RX_WMARK_GET(fifoth); + *tx_wtrmk = ALT_SDMMC_FIFOTH_TX_WMARK_GET(fifoth); + *mult_trans_size = (ALT_SDMMC_MULT_TRANS_t)ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_GET(fifoth); + + return ALT_E_SUCCESS; +} + +// +// Sets the configured FIFO operational parameter values. +// +ALT_STATUS_CODE alt_sdmmc_fifo_param_set(uint32_t rx_wtrmk, uint32_t tx_wtrmk, ALT_SDMMC_MULT_TRANS_t mult_trans_size) +{ + uint32_t fifoth_set_mask = ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK + | ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK + | ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET_MSK; + + uint32_t fifoth_set_value = ALT_SDMMC_FIFOTH_RX_WMARK_SET(rx_wtrmk) + | ALT_SDMMC_FIFOTH_TX_WMARK_SET(tx_wtrmk) + | ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET(mult_trans_size); + + alt_replbits_word(ALT_SDMMC_FIFOTH_ADDR, + fifoth_set_mask, + fifoth_set_value); + + return ALT_E_SUCCESS; +} + +// +// Card reset +// +ALT_STATUS_CODE alt_sdmmc_card_reset(void) +{ + // Assert card reset + alt_setbits_word(ALT_SDMMC_RST_N_ADDR, + ALT_SDMMC_RST_N_CARD_RST_SET_MSK); + + volatile uint32_t timeout = ALT_SDMMC_RESET_TMO_INIT; + + // Wait while card reset + while (timeout--) + ; + + // Deassert the appropriate card reset. + alt_clrbits_word(ALT_SDMMC_RST_N_ADDR, + ALT_SDMMC_RST_N_CARD_RST_SET_MSK); + + return ALT_E_SUCCESS; +} + +// +// Enables the sdmmc Internal DMA Controller. +// +ALT_STATUS_CODE alt_sdmmc_dma_enable(void) +{ + alt_setbits_word(ALT_SDMMC_CTL_ADDR, + ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK); + alt_setbits_word(ALT_SDMMC_BMOD_ADDR, + ALT_SDMMC_BMOD_DE_SET_MSK); + + return ALT_E_SUCCESS; +} + +// +// Disables the sdmmc Internal DMA Controller +// +ALT_STATUS_CODE alt_sdmmc_dma_disable(void) +{ + alt_clrbits_word(ALT_SDMMC_CTL_ADDR, + ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK); + alt_clrbits_word(ALT_SDMMC_BMOD_ADDR, + ALT_SDMMC_BMOD_DE_SET_MSK); + + return ALT_E_SUCCESS; +} + +// +// Enables the sdmmc Internal DMA Controller. +// +ALT_STATUS_CODE alt_sdmmc_is_dma_enabled(void) +{ + if ( ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET(alt_read_word(ALT_SDMMC_CTL_ADDR)) + && ALT_SDMMC_BMOD_DE_GET(alt_read_word(ALT_SDMMC_BMOD_ADDR))) + { + return ALT_E_TRUE; + } + else + { + return ALT_E_FALSE; + } +} + +// +// Returns the current sdmmc controller interrupt IDMAC status conditions. +// +uint32_t alt_sdmmc_dma_int_status_get(void) +{ + return alt_read_word(ALT_SDMMC_IDSTS_ADDR); +} + +// +// Returns the SD/MMC internal DMA controller interrupt mask value which +// reflects the enabled internal DMA controller interrupt status conditions. +// +uint32_t alt_sdmmc_dma_int_mask_get(void) +{ + return alt_read_word(ALT_SDMMC_IDINTEN_ADDR); +} + +// +// Clears the specified sdmmc controller interrupt status IDMAC conditions identified +// in the mask. +// +ALT_STATUS_CODE alt_sdmmc_dma_int_clear(const uint32_t mask) +{ + alt_write_word(ALT_SDMMC_IDSTS_ADDR, mask); + + return ALT_E_SUCCESS; +} + +// +// Disable the specified sdmmc controller interrupt IDMAC status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_sdmmc_dma_int_disable(const uint32_t mask) +{ + alt_clrbits_word(ALT_SDMMC_IDINTEN_ADDR, mask); + + return ALT_E_SUCCESS; +} + +// +// Enable the specified sdmmc controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_sdmmc_dma_int_enable(const uint32_t mask) +{ + alt_setbits_word(ALT_SDMMC_IDINTEN_ADDR, mask); + + return ALT_E_SUCCESS; +} + +// +// Sets value into this register for the IDMAC FSM to resume normal descriptor fetch operation. +// +ALT_STATUS_CODE alt_sdmmc_poll_demand_set(const uint32_t value) +{ + alt_replbits_word(ALT_SDMMC_PLDMND_ADDR, + ALT_SDMMC_PLDMND_PD_SET_MSK, + ALT_SDMMC_PLDMND_PD_SET(value)); + + return ALT_E_SUCCESS; +} + +// +// Disable Card Read Threshold . +// +ALT_STATUS_CODE alt_sdmmc_card_rd_threshold_disable(void) +{ + alt_clrbits_word(ALT_SDMMC_CARDTHRCTL_ADDR, + ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK); + + return ALT_E_SUCCESS; +} + + +// +// Enable Card Read Threshold . +// +ALT_STATUS_CODE alt_sdmmc_card_rd_threshold_enable(const uint32_t threshold) +{ + alt_replbits_word(ALT_SDMMC_CARDTHRCTL_ADDR, + ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET_MSK + | ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK, + ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET(threshold) + | ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET(ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END)); + + return ALT_E_SUCCESS; +} + +// +// This function return ALT_E_ERROR if interrupt error was detected +// +static ALT_STATUS_CODE alt_sdmmc_error_status_detect(void) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t int_status = 0; + + // All sdmmc interrupt status caused by an error + uint32_t err = ( ALT_SDMMC_INT_STATUS_RE + | ALT_SDMMC_INT_STATUS_RCRC + | ALT_SDMMC_INT_STATUS_DCRC + | ALT_SDMMC_INT_STATUS_RTO + | ALT_SDMMC_INT_STATUS_DRTO + | ALT_SDMMC_INT_STATUS_FRUN + | ALT_SDMMC_INT_STATUS_HLE + | ALT_SDMMC_INT_STATUS_SBE + | ALT_SDMMC_INT_STATUS_EBE); + + int_status = alt_sdmmc_int_status_get(); + if (status != ALT_E_SUCCESS) + { + return status; + } + + // Checking on errors + if (int_status & err) + { + status = ALT_E_ERROR; + } + + return status; +} + +// +// Read/write all data from/to buffer +// +static ALT_STATUS_CODE alt_sdmmc_transfer_helper(uint32_t * buffer, + const size_t size, + ALT_SDMMC_TMOD_t transfer_mode) +{ +#ifdef LOGGER + dprintf("\nalt_sdmmc_transfer_helper\n"); +#endif + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t data_size = size; + bool read_freeze = false; + bool write_freeze = false; + + while (data_size > 0) + { +#ifdef LOGGER + dprintf("\ndata_size = %x\n", (int)data_size); + // Error handling +#endif + // Error checking + status = alt_sdmmc_error_status_detect(); + + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t timeout = ALT_SDMMC_TMO_WAITER; + + do + { + read_freeze =(transfer_mode == ALT_SDMMC_TMOD_READ) + && alt_sdmmc_fifo_is_empty() == true; + write_freeze = transfer_mode == ALT_SDMMC_TMOD_WRITE + && alt_sdmmc_fifo_is_full() == true; +#ifdef LOGGER + dprintf("\nread_freeze = %x write_freeze = %x\n", (int)read_freeze, (int)write_freeze); +#endif + if (--timeout == 0) + { + status = ALT_E_TMO; + return status; + } + } + while (read_freeze || write_freeze); + + uint32_t level = alt_sdmmc_fifo_count(); + +#ifdef LOGGER + dprintf("\nfifo level = %x\n", (int)level); +#endif + + // Top up the TX FIFO with read issues + + if (transfer_mode == ALT_SDMMC_TMOD_WRITE) + { + uint32_t free_space = ALT_SDMMC_FIFO_NUM_ENTRIES - level; + free_space = MIN(data_size / 4, free_space); + + for (uint32_t i = 0; i < free_space; i++) + { + alt_write_word(ALT_SDMMC_DATA_ADDR, *buffer); + ++buffer; + } + data_size -= free_space * 4; + } + + // Read out the resulting received data as they come in. + + if (transfer_mode == ALT_SDMMC_TMOD_READ) + { + level = MIN(data_size / 4, level); + + for (uint32_t i = 0; i < level; i++) + { + *buffer = ALT_SDMMC_DATA_VALUE_GET(alt_read_word(ALT_SDMMC_DATA_ADDR)); + ++buffer; + } + + data_size -= level * 4; + } + } + + return status; +} + +// +// Fill descriptors +// +static ALT_STATUS_CODE alt_sdmmc_dma_trans_helper(uint32_t * buffer, + size_t buf_len) +{ +#ifdef LOGGER + dprintf("\nalt_sdmmc_dma_trans_helper: buf_len = %d\n", + (int)buf_len); +#endif + ALT_STATUS_CODE status = ALT_E_SUCCESS; + //Pointer to current descriptor + ALT_SDMMC_DMA_BUF_DESC_t *cur_dma_desc = dma_cur_descr; + + uint32_t cur_buffer = (uint32_t)buffer; + uint32_t len_left = buf_len; + + while (len_left > 0) + { + //Error checking + status = alt_sdmmc_error_status_detect(); + if (status != ALT_E_SUCCESS) + { + status = ALT_E_ERROR; + break; + } + //If current descriptor is free then fill it + if (cur_dma_desc->des0.fld.own == 0) + { + int set_len = len_left > ALT_SDMMC_DMA_SEGMENT_SIZE ? ALT_SDMMC_DMA_SEGMENT_SIZE : len_left; + //Disable interrupt after it will be free + cur_dma_desc->des0.fld.dic = 1;//socfpga->dma_cur_pos % 4; + //Set If it is first part of buffer for transfer + cur_dma_desc->des0.fld.fs = (buf_len == len_left) ? 1 : 0; + //Set size of des2 + cur_dma_desc->des1.fld.bs1 = set_len; + //Set address of buffer in memory + cur_dma_desc->des2.fld.bap1 = cur_buffer; + +#ifdef LOGGER + dprintf("socfpga_setup_dma_add: des_adrdr %08X des2_paddr %08X des1_len %08X len_left %08X\n", + (int)cur_dma_desc, (int)cur_buffer, (int)set_len, (int)len_left); +#endif + + //Update address buffer and buffer len + cur_buffer += set_len; + len_left -= set_len; + //Set if it is last part of buffer + cur_dma_desc->des0.fld.ld = (len_left == 0) ? 1 : 0; + //Descriptor could be used + cur_dma_desc->des0.fld.own = 1; + //Currernt descriptor set sa next element + cur_dma_desc = (ALT_SDMMC_DMA_BUF_DESC_t *)cur_dma_desc->des3.fld.bap2_or_next; + } + + uint32_t idmac_status = alt_sdmmc_dma_int_status_get(); + + // If DMA status is as descriptor unavailable then resume transfer and clean interrupt status + if (idmac_status & ALT_SDMMC_DMA_INT_STATUS_DU) + { + alt_sdmmc_poll_demand_set(0xFFFF); + alt_sdmmc_dma_int_clear(ALT_SDMMC_DMA_INT_STATUS_ALL); + } + // If DMA status is another abnormal then break with error + else if (idmac_status & ALT_SDMMC_DMA_INT_STATUS_AI) + { + status = ALT_E_ERROR; + break; + } + + } + + return status; + +} + +// +// Waiter of data transfer complete +// +static ALT_STATUS_CODE alt_sdmmc_data_done_waiter(void) +{ + ALT_STATUS_CODE status = ALT_E_TMO; + uint32_t timeout = ALT_SDMMC_TMO_WAITER; + + while (--timeout) + { + uint32_t int_status; + int_status = alt_sdmmc_int_status_get(); + + // Error checking + if (alt_sdmmc_error_status_detect() != ALT_E_SUCCESS) + { + status = ALT_E_ERROR; + break; + } + + uint32_t idmac_status = alt_sdmmc_dma_int_status_get(); + + // If DMA status is abnormal then transfer complete with error + if (idmac_status & ALT_SDMMC_DMA_INT_STATUS_AI) + { + status = ALT_E_ERROR; + break; + } + // Data transfer over caused by complete transfer operation + if (int_status & ALT_SDMMC_INT_STATUS_DTO) + { + alt_sdmmc_int_clear(ALT_SDMMC_INT_STATUS_DTO); + status = ALT_E_SUCCESS; + break; + } + } + + timeout = ALT_SDMMC_TMO_WAITER; + while (!alt_sdmmc_is_idle() && timeout--) + ; + if (timeout == 0) + { + status = ALT_E_TMO; + } + + return status; +} + + +// +// Waiter of clock command complete +// +static ALT_STATUS_CODE alt_sdmmc_clock_waiter(void) +{ + ALT_STATUS_CODE status = ALT_E_TMO; + uint32_t timeout = ALT_SDMMC_TMO_WAITER; + + while (--timeout) + { + uint32_t cmd_register = alt_read_word(ALT_SDMMC_CMD_ADDR); + + // Error checking + if (alt_sdmmc_error_status_detect() != ALT_E_SUCCESS) + { + status = ALT_E_ERROR; + break; + } + + // Only for clock command detect complete operation by 0 in start_cmd bit of cmd register + if (ALT_SDMMC_CMD_START_CMD_GET(cmd_register) == ALT_SDMMC_CMD_START_CMD_E_NOSTART) + { + status = ALT_E_SUCCESS; + break; + } + } + return status; +} + +// +// Waiter of command complete +// +static ALT_STATUS_CODE alt_sdmmc_cmd_waiter(void) +{ + ALT_STATUS_CODE status = ALT_E_TMO; + uint32_t timeout = ALT_SDMMC_TMO_WAITER; + + while (--timeout) + { + uint32_t int_status; + int_status = alt_sdmmc_int_status_get(); + + // Error checking + if (alt_sdmmc_error_status_detect() != ALT_E_SUCCESS) + { + status = ALT_E_ERROR; + break; + } + + //Check command done + if (int_status & ALT_SDMMC_INT_STATUS_CMD) + { + alt_sdmmc_int_clear(ALT_SDMMC_INT_STATUS_CMD); + status = ALT_E_SUCCESS; + break; + } + } + return status; +} + +// +// Read SRC register from card and read supported bus width +// +static ALT_STATUS_CODE alt_sdmmc_card_scr_get(uint64_t *scr_reg) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; +#ifdef LOGGER + uint32_t response = 0; +#endif + + uint16_t prev_blk_size = 0; + // Save current block size and change it + prev_blk_size = alt_sdmmc_block_size_get(); + alt_sdmmc_block_size_set(8); + alt_sdmmc_byte_count_set(8); + + // Activate ACMD commands + status = alt_sdmmc_command_send(ALT_SDMMC_APP_CMD, rca_number, NULL); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_APP_CMD response = %x\n", (int)response); +#endif + + // Send request for read SRC register + status = alt_sdmmc_command_send(ALT_SD_SEND_SCR, 0x0, NULL); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SD_SEND_SCR responce = %x\n", (int)response); +#endif + + // Read SRC register + status = alt_sdmmc_transfer_helper((uint32_t*)scr_reg, 8, ALT_SDMMC_TMOD_READ); + if (status != ALT_E_SUCCESS) + { + return status; + } + + // Transfer complete + status = alt_sdmmc_data_done_waiter(); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + dprintf("\nALT_SD_SEND_SCR data = "); + uint8_t* scr_buf_8 = (uint8_t*)scr_reg; + for (int count = 0; count < 8; count++) + { + dprintf("%02x", scr_buf_8[count]); + } + dprintf("\n"); +#endif + + // Re-change block size + alt_sdmmc_block_size_set(prev_blk_size); + + return status; +} + +// +// Set sdmmc card width +// +ALT_STATUS_CODE alt_sdmmc_card_bus_width_set(const ALT_SDMMC_BUS_WIDTH_t width) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint64_t scr_reg; + + // Read SRC register + status = alt_sdmmc_card_scr_get(&scr_reg); + if (status != ALT_E_SUCCESS) + { + return status; + } + + uint8_t * scr_buf_8 = (uint8_t*)&scr_reg; + // Get supported bus width + uint32_t supported_bus_width = scr_buf_8[1] & 0xF; + +#ifdef LOGGER + dprintf("\nbus_width_supported = %02x\n", (int)supported_bus_width); +#endif + + if ((supported_bus_width & width) == 0) + { + return ALT_E_BAD_ARG; + } + + uint32_t set_width_arg; + switch (width) + { + case ALT_SDMMC_BUS_WIDTH_8: + set_width_arg = 0x3; + break; + case ALT_SDMMC_BUS_WIDTH_4: + set_width_arg = 0x2; + break; + case ALT_SDMMC_BUS_WIDTH_1: + set_width_arg = 0x0; + break; + default: + return ALT_E_BAD_ARG; + } + +#ifdef LOGGER + uint32_t response = 0; +#endif + + // Activate ACMD commands + status = alt_sdmmc_command_send(ALT_SDMMC_APP_CMD, rca_number, NULL); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_APP_CMD response = %x\n", (int)response); +#endif + + // Send new card bus width + status = alt_sdmmc_command_send(ALT_SD_SET_BUS_WIDTH, set_width_arg, NULL); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SD_SET_BUS_WIDTH responce = %x\n", (int)response); +#endif + + // Set new bus width in controller register + alt_sdmmc_bus_width_set(width); + + return status; +} + +// +// Set block size +// +ALT_STATUS_CODE alt_sdmmc_card_block_size_set(const uint16_t block_size) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Send new block size to card + status = alt_sdmmc_command_send(ALT_SDMMC_SET_BLOCKLEN, block_size, NULL); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + uint32_t response; + + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_SET_BLOCKLEN response = %x\n", (int)response); +#endif + + // Set new block size in controller register + alt_sdmmc_block_size_set(block_size); + + return status; +} + +// +// Enumerated Card Stack ident sdio io only +// +static ALT_STATUS_CODE alt_sdmmc_card_ident_io_only(ALT_SDMMC_CARD_INFO_t *card_info) +{ +#ifdef LOGGER + dprintf("\nalt_sdmmc_card_ident_io_only\n"); +#endif + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t int_status = 0; + uint32_t response = 0; + // Enumerated Card Stack p.2a - 2b + // Activates the card's initialization process. + status = alt_sdmmc_command_send(ALT_SDMMC_SEND_OP_COND, 0x0, &response); + if (status != ALT_E_SUCCESS) + { + int_status = alt_sdmmc_int_status_get(); + if (int_status & ALT_SDMMC_INT_STATUS_RTO) + { + return ALT_E_SUCCESS; + } + else + { + return status; + } + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_SEND_OP_COND_1 = %x\n", (int)response); +#endif + + // Enumerated Card Stack p.2c + status = alt_sdmmc_command_send(ALT_SDMMC_SEND_OP_COND, 0x100000, &response); + if (status != ALT_E_SUCCESS) + { + int_status = alt_sdmmc_int_status_get(); + if (int_status & ALT_SDMMC_INT_STATUS_RTO) + { + return ALT_E_SUCCESS; + } + else + { + return status; + } + } + +#ifdef LOGGER + dprintf("\nALT_SDMMC_SEND_OP_COND_2 response = %x\n", (int)response); +#endif + // Enumerated Card Stack p.2d + bool is_sdio_combo = response & (1 << 27); + card_info->card_type = (is_sdio_combo) + ? ALT_SDMMC_CARD_TYPE_NOTDETECT + : ALT_SDMMC_CARD_TYPE_SDIOIO; + + return ALT_E_SUCCESS; +} + +// +// Enumerated Card Stack ident sdhc type +// +static ALT_STATUS_CODE alt_sdmmc_card_ident_sdhc(ALT_SDMMC_CARD_INFO_t *card_info) +{ +#ifdef LOGGER + dprintf("\nalt_sdmmc_card_ident_sdhc\n"); +#endif + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t int_status = 0; + uint32_t response = 0; + // Resets all cards to Idle State + status = alt_sdmmc_command_send(ALT_SDMMC_GO_IDLE_STATE, 0x0, &response); + if (status != ALT_E_SUCCESS) + { + int_status = alt_sdmmc_int_status_get(); + if (int_status & ALT_SDMMC_INT_STATUS_RTO) + { + return ALT_E_SUCCESS; + } + else + { + return status; + } + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_GO_IDLE_STATE response = %x\n", (int)response); +#endif + + // Enumerated Card Stack p.3a + // For only SDC V2. Check voltage range. + status = alt_sdmmc_command_send(ALT_SDMMC_IF_COND, 0x1AA, &response); + if (status != ALT_E_SUCCESS) + { + int_status = alt_sdmmc_int_status_get(); + if (int_status & ALT_SDMMC_INT_STATUS_RTO) + { + return ALT_E_SUCCESS; + } + else + { + return status; + } + } + + alt_sdmmc_read_short_response(&response); +#ifdef LOGGER + dprintf("\nALT_SDMMC_IF_COND response = %x\n", (int)response); +#endif + + if (response != 0x1AA) + { + return ALT_E_ERROR; + } + + // Indicates to the card that the next command is an + // application specific command rather than a + // standard command + status = alt_sdmmc_command_send(ALT_SDMMC_APP_CMD, 0x0, &response); + if (status != ALT_E_SUCCESS) + { + int_status = alt_sdmmc_int_status_get(); + if (int_status & ALT_SDMMC_INT_STATUS_RTO) + { + return ALT_E_SUCCESS; + } + else + { + return status; + } + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_APP_CMD response = %x\n", (int)response); +#endif + + // Enumerated Card Stack p.3c + // Asks the accessed card to send its operating condition + // register (OCR) con tent in the response on the CMD + // line. + status = alt_sdmmc_command_send(ALT_SD_SEND_OP_COND, 0x40FF8000, &response); + if (status != ALT_E_SUCCESS) + { + int_status = alt_sdmmc_int_status_get(); + if (int_status & ALT_SDMMC_INT_STATUS_RTO) + { + return ALT_E_SUCCESS; + } + else + { + return status; + } + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SD_SEND_OP_COND responce = %x\n", (int)response); +#endif + + //Enumerated Card Stack p.3d + card_info->card_type = ALT_SDMMC_CARD_TYPE_SDHC; + + return status; +} + +// +//Enumerated Card Stack ident sd type +// +static ALT_STATUS_CODE alt_sdmmc_card_ident_sd(ALT_SDMMC_CARD_INFO_t *card_info) +{ +#ifdef LOGGER + dprintf("\nalt_sdmmc_card_ident_sd\n"); +#endif + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t int_status = 0; +#ifdef LOGGER + uint32_t response = 0; +#endif + // Enumerated Card Stack p.3e + // Indicates to the card that the next command is an + // application specific command rather than a + // standard command + status = alt_sdmmc_command_send(ALT_SDMMC_APP_CMD, 0x0, NULL); + if (status != ALT_E_SUCCESS) + { + int_status = alt_sdmmc_int_status_get(); + if (int_status & ALT_SDMMC_INT_STATUS_RTO) + { + return ALT_E_SUCCESS; + } + else + { + return status; + } + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_APP_CMD response = %x\n", (int)response); +#endif + + // Asks the accessed card to send its operating condition + // register (OCR) con tent in the response on the CMD + // line. + status = alt_sdmmc_command_send(ALT_SD_SEND_OP_COND, 0x00FF8000, NULL); + if (status != ALT_E_SUCCESS) + { + int_status = alt_sdmmc_int_status_get(); + if (int_status & ALT_SDMMC_INT_STATUS_RTO) + { + return ALT_E_SUCCESS; + } + else + { + return status; + } + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SD_SEND_OP_COND responce = %x\n", (int)response); +#endif + + // Enumerated Card Stack p.3f + card_info->card_type = ALT_SDMMC_CARD_TYPE_SD; + + return status; +} + +// +// Enumerated Card Stack enumarete sd cart type +// +static ALT_STATUS_CODE alt_sdmmc_card_enum_sd(ALT_SDMMC_CARD_INFO_t *card_info) +{ +#ifdef LOGGER + dprintf("\nalt_sdmmc_card_enum_sd\n"); +#endif + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t clk_div = clock_freq / (2 * 400000); + + status = alt_sdmmc_card_clk_div_set(clk_div); + if (status != ALT_E_SUCCESS) + { + return status; + } + status = alt_sdmmc_card_clk_enable(false); + if (status != ALT_E_SUCCESS) + { + return status; + } + + uint32_t response = 0; + // Resets all cards to Idle State + status = alt_sdmmc_command_send(ALT_SDMMC_GO_IDLE_STATE, 0x0, &response); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_GO_IDLE_STATE response = %x\n", (int)response); +#endif + // For only SDC V2. Check voltage range. + status = alt_sdmmc_command_send(ALT_SDMMC_IF_COND, 0x1AA, &response); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_IF_COND response = %x\n", (int)response); +#endif + +/* OCR Bit VDD Voltage Window + 0-3 Reserved + 4 1.6-1.7 + 5 1.7-1.8 + 6 1.8-1.9 + 7 1.9-2.0 + 8 2.0-2.1 + 9 2.1-2.2 + 10 2.2-2.3 + 11 2.3-2.4 + 12 2.4-2.5 + 13 2.5-2.6 + 14 2.6-2.7 + 15 2.7-2.8 + 16 2.8-2.9 + 17 2.9-3.0 + 18 3.0-3.1 + 19 3.1-3.2 + 20 3.2-3.3 + 21 3.3-3.4 + 22 3.4-3.5 + 23 3.5-3.6 + 24-29 Reserved + 30 High capacity card + 31 Card power up status bit (busy) +*/ + uint32_t ocr_reg = 0xFF8000; + + if (card_info->card_type == ALT_SDMMC_CARD_TYPE_SDHC) + { + ocr_reg |= (1 << 30); + } + + do + { + status = alt_sdmmc_command_send(ALT_SDMMC_APP_CMD, 0x0, &response); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_APP_CMD response = %x\n", (int)response); +#endif + + volatile uint32_t timeout = 1000000; + + // Wait while sdmmc module is reseting + while (timeout--) + ; + status = alt_sdmmc_command_send(ALT_SD_SEND_OP_COND, 0x40FF8000, &response); + if (status != ALT_E_SUCCESS) + { + return status; + } + + alt_sdmmc_read_short_response(&response); +#ifdef LOGGER + dprintf("\nALT_SD_SEND_OP_COND response = %x\n", (int)response); +#endif + } + while ((response & (1UL << 31)) == 0); + + //Asks any card to send their CID numbers on the CMD line. + //(Any card that is connected to the host will respond.) + status = alt_sdmmc_command_send(ALT_SDMMC_ALL_SEND_CID, 0x0, &response); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_ALL_SEND_CID response = %x\n", (int)response); +#endif + // Asks the card to publish a new relative address (RCA). + status = alt_sdmmc_command_send(ALT_SDMMC_SET_RELATIVE_ADDR, 0x0, &response); + if (status != ALT_E_SUCCESS) + { + return status; + } + + alt_sdmmc_read_short_response(&response); +#ifdef LOGGER + dprintf("\nALT_SDMMC_SET_RELATIVE_ADDR responce = %x\n", (int)response); +#endif + + uint32_t RCA_number = response & 0xFFFF0000; + rca_number = RCA_number; + + // Addressed card sends its card identification (CID) on the CMD line. + status = alt_sdmmc_command_send(ALT_SDMMC_SEND_CID, rca_number, &response); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_SEND_CID responce = %x\n", (int)response); +#endif + + // Addressed card sends its card-specific data (CSD) + // on the CMD line. + status = alt_sdmmc_command_send(ALT_SDMMC_SEND_CSD, rca_number, &response); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_SEND_CSD responce = %x\n", (int)response); +#endif + + ALT_SDMMC_RESPONSE_t response_long; + alt_sdmmc_read_long_response(&response_long); + static const uint32_t tran_speed_mul_x10[] = { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 }; + static const uint32_t freq_unit[] = { 100000, 1000000, 10000000, 100000000 }; +// card_info->max_r_blkln = pow(2, ALT_SDMMC_CSD_MAX_R_BLK_GET(response_long.resp2)); +// card_info->max_w_blkln = pow(2, ALT_SDMMC_CSD_MAX_W_BLK_GET(response_long.resp0)); + card_info->max_r_blkln = 1 << ALT_SDMMC_CSD_MAX_R_BLK_GET(response_long.resp2); + card_info->max_w_blkln = 1 << ALT_SDMMC_CSD_MAX_W_BLK_GET(response_long.resp0); + card_info->partial_r_allowed = ALT_SDMMC_CSD_PART_R_ALLOW_GET(response_long.resp2); + card_info->partial_w_allowed = ALT_SDMMC_CSD_PART_W_ALLOW_GET(response_long.resp0); + uint32_t rate_unit = ALT_SDMMC_CSD_SPEED_RATE_GET(response_long.resp3); + uint32_t time_val = ALT_SDMMC_CSD_SPEED_TIME_GET(response_long.resp3); + if ((time_val != 0) && (rate_unit <= 3)) + { + // uint32_t speed_rate = (rate_unit == 0) ? 100 : pow(10, rate_unit - 1) * 1000; + uint32_t speed_rate = freq_unit[rate_unit]; + card_info->xfer_speed = speed_rate * tran_speed_mul_x10[time_val] / 10; + } + else + { + return ALT_E_ERROR; + } + + // Command toggles a card between the Stand-by + // and Transfer states or between the Programming + // and Disconnect state + status = alt_sdmmc_command_send(ALT_SDMMC_SEL_DES_CARD, rca_number, &response); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_SEL_DES_CARD responce = %x\n", (int)response); +#endif + + // Addressed card sends its status register + status = alt_sdmmc_command_send(ALT_SDMMC_SEND_STATUS, rca_number, &response); + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + alt_sdmmc_read_short_response(&response); + dprintf("\nALT_SDMMC_SEND_STATUS responce = %x\n", (int)response); +#endif + + return status; +} + +// +// Enumerated Card Stack +// +ALT_STATUS_CODE alt_sdmmc_card_identify(ALT_SDMMC_CARD_INFO_t *card_info) +{ +#ifdef LOGGER + dprintf("\nalt_sdmmc_card_identify\n"); +#endif + ALT_STATUS_CODE status = ALT_E_SUCCESS; + card_info->card_type = ALT_SDMMC_CARD_TYPE_NOTDETECT; + + //Enumerated Card Stack p.1 + alt_sdmmc_bus_width_set(ALT_SDMMC_BUS_WIDTH_1); + + if (status == ALT_E_SUCCESS) + { + status = alt_sdmmc_card_ident_io_only(card_info); + // If card is identified as SDIO IO only or SDIO COMBO then prepare it + if (card_info->card_type != ALT_SDMMC_CARD_TYPE_NOTDETECT && status == ALT_E_SUCCESS) + { + return status; + } + } + if (status == ALT_E_SUCCESS) + { + status = alt_sdmmc_card_ident_sdhc(card_info); + if (card_info->card_type != ALT_SDMMC_CARD_TYPE_NOTDETECT && status == ALT_E_SUCCESS) + { + // If card is identified as SDHC then prepare it + status = alt_sdmmc_card_enum_sd(card_info); + return status; + } + } + if (status != ALT_E_SUCCESS) + { + status = alt_sdmmc_card_ident_sd(card_info); + if (card_info->card_type != ALT_SDMMC_CARD_TYPE_NOTDETECT && status == ALT_E_SUCCESS) + { + // If card is identified as SD card then prepare it + status = alt_sdmmc_card_enum_sd(card_info); + return status; + } + } + + return status; +} + +// +// Send the a command and command argument to the card and optionally return the +// command response. +// +ALT_STATUS_CODE alt_sdmmc_command_send(ALT_SDMMC_CMD_INDEX_t command, + uint32_t command_arg, uint32_t *response) +{ + const ALT_SDMMC_CMD_CONFIG_t * cmd_cfg = NULL; + + bool found = false; + + if (command == ALT_SDMMC_CLK_INDEX) + { + cmd_cfg = &cmd_clock_cfg; + found = true; + } + + for (uint32_t counter = 0; counter < ARRAY_COUNT(cmd_default_cfg); counter++) + { + if (found == true) + { + break; + } + if (cmd_default_cfg[counter].cmd_index == command) + { + cmd_cfg = &cmd_default_cfg[counter]; + found = true; + } + } + + if (found == false) + { + return ALT_E_BAD_ARG; + } + + if (cmd_cfg->wait_prvdata_complete) + { + uint32_t timeout = ALT_SDMMC_TMO_WAITER; + while (alt_sdmmc_is_busy() && timeout--) + ; + } + + // Create interrupt mask by command configurations + uint32_t int_mask = ALT_SDMMC_INT_STATUS_RE // Response error + | ALT_SDMMC_INT_STATUS_RTO // Response timeout + | ALT_SDMMC_INT_STATUS_CD // Card detect (CD) interrupt + | ALT_SDMMC_INT_STATUS_HLE // Hardware Locked Write Error + | ALT_SDMMC_INT_STATUS_CMD; // Command done (CD) interrupt + + if (cmd_cfg->data_expected == true) + { + int_mask |= ALT_SDMMC_INT_STATUS_DTO // Data transfer over + | ALT_SDMMC_INT_STATUS_RCRC // Response CRC error + | ALT_SDMMC_INT_STATUS_DCRC // Data CRC error + | ALT_SDMMC_INT_STATUS_HTO // Data starvation by host timeout + | ALT_SDMMC_INT_STATUS_FRUN // FIFO underrun/overrun error + | ALT_SDMMC_INT_STATUS_EBE; // End-bit error + + if (cmd_cfg->write_active == ALT_SDMMC_TMOD_WRITE) + { + int_mask |= ALT_SDMMC_INT_STATUS_TXDR // Transmit FIFO data request (TXDR) + | ALT_SDMMC_INT_STATUS_HLE; // Hardware locked write error (HLE) + } + else + { + int_mask |= ALT_SDMMC_INT_STATUS_RXDR // Receive FIFO data request (RXDR) + |ALT_SDMMC_INT_STATUS_SBE; // Start-bit error (SBE) + } + + } + + alt_sdmmc_int_disable(ALT_SDMMC_INT_STATUS_ALL); + // Reset all possible interrupts + alt_sdmmc_int_clear(ALT_SDMMC_INT_STATUS_ALL); + // Interrupts enable + alt_sdmmc_int_enable(int_mask); + // Setup the Argument Register and send CMD + alt_sdmmc_cmd_arg_set(command_arg); + + // Set command configuraions + alt_sdmmc_cmd_set(command, cmd_cfg, false); + // Send commnd + alt_sdmmc_cmd_set(command, cmd_cfg, true); + +#ifdef LOGGER + uint32_t state = (uint32_t)ALT_SDMMC_STAT_CMD_FSM_STATES_GET(alt_read_word(ALT_SDMMC_STAT_ADDR)); + + uint32_t dma_state = (uint32_t)ALT_SDMMC_IDSTS_FSM_GET(alt_read_word(ALT_SDMMC_IDSTS_ADDR)); + + dprintf("\nstate %x dma_state %x\n", (int)state, (int)dma_state); + dprintf("\nCMD = %d ARG = %x\n", (int)command, (int)command_arg); +#endif + + ALT_STATUS_CODE status = 0; + if (cmd_cfg->update_clock_registers_only == true) + { + //Wait for complete clock update command + status = alt_sdmmc_clock_waiter(); +#ifdef LOGGER + if (status == ALT_E_TMO) + { + dprintf("\nTIMEOUT\n"); + } +#endif + return status; + } + + //Wait for complete + if ( alt_sdmmc_is_dma_enabled() == ALT_E_FALSE + || cmd_cfg->data_expected == false) + { + status = alt_sdmmc_cmd_waiter(); + } +#ifdef LOGGER + if (status == ALT_E_TMO) + { + dprintf("\nTIMEOUT\n"); + } +#endif + if (status == ALT_E_SUCCESS) + { + alt_sdmmc_read_short_response(response); + } + + return status; +} + +static ALT_STATUS_CODE alt_sdmmc_transfer(uint32_t start_addr, + uint32_t buffer[], + const size_t buf_len, + ALT_SDMMC_TMOD_t transfer_mode) +{ + if (buf_len == 0) + { + return ALT_E_SUCCESS; + } + + if (!alt_sdmmc_is_idle()) + { + return ALT_E_ERROR; + } + + uint16_t block_size = alt_sdmmc_block_size_get(); + + if ( (start_addr % block_size != 0) + || (buf_len % block_size != 0)) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + // Number of block to transfer + uint32_t block_count = buf_len / block_size; + // New count of reading byte + uint32_t byte_count = block_count * block_size; + + // reset FIFO + status = alt_sdmmc_fifo_reset(); + if (status != ALT_E_SUCCESS) + { + return status; + } + + // reset DMA + status = alt_sdmmc_dma_reset(); + if (status != ALT_E_SUCCESS) + { + return status; + } + + alt_sdmmc_byte_count_set(byte_count); + alt_sdmmc_card_rd_threshold_enable(0x80); + + uint32_t cmd_index = 0; + if (buf_len == block_size) + { + cmd_index = (transfer_mode == ALT_SDMMC_TMOD_READ) + ? ALT_SDMMC_READ_SINGLE_BLOCK + : ALT_SDMMC_WRITE_BLOCK; + } + else + { + cmd_index = (transfer_mode == ALT_SDMMC_TMOD_READ) + ? ALT_SDMMC_READ_MULTIPLE_BLOCK + : ALT_SDMMC_WRITE_MULTIPLE_BLOCK; + } + + if (alt_sdmmc_is_dma_enabled()) + { + // Clean descriptor chain + alt_sdmmc_desc_chain_clear(); + + alt_sdmmc_dma_start(dma_cur_descr, 0x0, + ALT_SDMMC_DMA_PBL_1, false); + //Enable all dma interrupt status + alt_sdmmc_dma_int_enable(ALT_SDMMC_DMA_INT_STATUS_ALL); + } + if (status != ALT_E_SUCCESS) + { + return status; + } + +#ifdef LOGGER + dprintf("\nstart_addr = %d\n", (int)start_addr); +#endif + + //Send transfer command + status = alt_sdmmc_command_send((ALT_SDMMC_CMD_INDEX_t)cmd_index, start_addr / block_size, NULL); + if (status != ALT_E_SUCCESS) + { + return status; + } + + //Send or read data + if (alt_sdmmc_is_dma_enabled()) + { + //Fill descriptors + status = alt_sdmmc_dma_trans_helper(buffer, byte_count); + } + else + { + status = alt_sdmmc_transfer_helper(buffer, byte_count, transfer_mode); + } + + if (status != ALT_E_SUCCESS) + { + return status; + } + + //Wait for data transfer complete + status = alt_sdmmc_data_done_waiter(); + + return status; +} + +// +// This function performs SDMMC write. +// +ALT_STATUS_CODE alt_sdmmc_write(void *dest, void *src, const size_t size) +{ + return alt_sdmmc_transfer((uint32_t)dest, src, size, ALT_SDMMC_TMOD_WRITE); +} + +// +// This function performs SDMMC read. +// +ALT_STATUS_CODE alt_sdmmc_read(void *dest, void *src, const size_t size) +{ + return alt_sdmmc_transfer((uint32_t)src, dest, size, ALT_SDMMC_TMOD_READ); +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_spi.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_spi.c new file mode 100644 index 000000000..779987393 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_spi.c @@ -0,0 +1,2232 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ + +#include "alt_spi.h" +#include "alt_reset_manager.h" +#include "socal/alt_rstmgr.h" + +// Timeout for reset manager +#define ALT_SPI_RESET_TMO_INIT 8192 + +// Maximum value of SPI Clock Divider +#define ALT_SPI_MAX_CLK_DIV 65534 +// Minimum value of SPI Clock Divider +#define ALT_SPI_MIN_CLK_DIV 2 +// Timeout for waiting interrupt +#define ALT_SPI_TMO_WAITER 2500000 + +///// + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) + +///// + +// +// Check whether spi space is correct. +// +static ALT_STATUS_CODE alt_spi_checking(ALT_SPI_DEV_t * spi_dev) + +{ + if (!spi_dev) + { + //Incorrect pointer + return ALT_E_FALSE; + } + + if ( spi_dev->location != (void *)ALT_SPI_SPIS0 + && spi_dev->location != (void *)ALT_SPI_SPIS1 + && spi_dev->location != (void *)ALT_SPI_SPIM0 + && spi_dev->location != (void *)ALT_SPI_SPIM1) + { + // Incorrect device + return ALT_E_FALSE; + } + + + return ALT_E_TRUE; +} + +// +// Initialize the specified SPI controller instance for use and return a device +// handle referencing it. +// +ALT_STATUS_CODE alt_spi_init(const ALT_SPI_CTLR_t spi, + ALT_SPI_DEV_t * spi_dev) + +{ + if (!spi_dev || spi == 0) + { + return ALT_E_BAD_ARG; + } + + //Save spi start address to the instance + spi_dev->location = (void *)spi; + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_clk_is_enabled(ALT_CLK_SPI_M) != ALT_E_TRUE) + { + return ALT_E_BAD_CLK; + } + + // Define operation mode + if ( spi_dev->location == (void *)ALT_SPI_SPIM0 + || spi_dev->location == (void *)ALT_SPI_SPIM1) + { + spi_dev->op_mode = ALT_SPI_OP_MODE_MASTER; + } + else if ( spi_dev->location == (void *)ALT_SPI_SPIS0 + || spi_dev->location == (void *)ALT_SPI_SPIS1) + { + spi_dev->op_mode = ALT_SPI_OP_MODE_SLAVE; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (status == ALT_E_SUCCESS) + { + // Get spi clock frequence + status = alt_clk_freq_get(ALT_CLK_SPI_M, &spi_dev->clock_freq); + } + + // Reset spi module + if (status == ALT_E_SUCCESS) + { + status = alt_spi_reset(spi_dev); + } + + return status; +} + +// +// Reset spi module by reset manager +// +static ALT_STATUS_CODE alt_spi_rstmgr_set(ALT_SPI_DEV_t * spi_dev) +{ + uint32_t rst_mask = ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK; + + // Assert the appropriate SPI module reset signal via the Reset Manager Peripheral Reset register. + switch ((ALT_SPI_CTLR_t)spi_dev->location) + { + case ALT_SPI_SPIM0: + rst_mask = ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK; + break; + case ALT_SPI_SPIM1: + rst_mask = ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK; + break; + case ALT_SPI_SPIS0: + rst_mask = ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK; + break; + case ALT_SPI_SPIS1: + rst_mask = ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK; + break; + default: + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + return ALT_E_SUCCESS; +} + +// +// Reset spi module by reset manager +// +static ALT_STATUS_CODE alt_spi_rstmgr_strobe(ALT_SPI_DEV_t * spi_dev) +{ + uint32_t rst_mask = ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK; + + // Assert the appropriate SPI module reset signal via the Reset Manager Peripheral Reset register. + switch ((ALT_SPI_CTLR_t)spi_dev->location) + { + case ALT_SPI_SPIM0: + rst_mask = ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK; + break; + case ALT_SPI_SPIM1: + rst_mask = ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK; + break; + case ALT_SPI_SPIS0: + rst_mask = ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK; + break; + case ALT_SPI_SPIS1: + rst_mask = ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK; + break; + default: + return ALT_E_BAD_ARG; + } + + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + volatile uint32_t timeout = ALT_SPI_RESET_TMO_INIT; + + // Wait while spi modure is reseting + while (timeout--) + ; + + // Deassert the appropriate SPI module reset signal via the Reset Manager Peripheral Reset register. + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, rst_mask); + + return ALT_E_SUCCESS; +} + +// +// Reset spi module +// +ALT_STATUS_CODE alt_spi_reset(ALT_SPI_DEV_t * spi_dev) +{ + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + bool already_enabled = (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_spi_disable(spi_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + // Reset spi module by reset manager + alt_spi_rstmgr_strobe(spi_dev); + + // Reset the last target address cache. + spi_dev->last_slave_mask = 0xffffffff; + spi_dev->last_transfer_mode = (uint32_t)(-1); + + if (already_enabled) + { + // Re-enable controller + status = alt_spi_enable(spi_dev); + } + + return status; +} + + +// +// Uninitialize the SPI controller referenced by the spi_dev handle. +// +ALT_STATUS_CODE alt_spi_uninit(ALT_SPI_DEV_t * spi_dev) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // Disable spi controller + status = alt_spi_disable(spi_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + + // Reset spi module by reset manager + alt_spi_rstmgr_set(spi_dev); + + return status; +} + + +// +// Enables the SPI controller. +// +ALT_STATUS_CODE alt_spi_enable(ALT_SPI_DEV_t * spi_dev) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_setbits_word(ALT_SPIM_SPIENR_ADDR(spi_dev->location), + ALT_SPIM_SPIENR_SPI_EN_SET_MSK); + break; + case ALT_SPI_OP_MODE_SLAVE: + alt_setbits_word(ALT_SPIS_SPIENR_ADDR(spi_dev->location), + ALT_SPIS_SPIENR_SPI_EN_SET_MSK); + break; + } + + return ALT_E_SUCCESS; +} + +// +// Disables the SPI controller +// +ALT_STATUS_CODE alt_spi_disable(ALT_SPI_DEV_t * spi_dev) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // If spi controller is enabled, return with sucess + if (alt_spi_is_enabled(spi_dev) == ALT_E_FALSE) + { + return ALT_E_SUCCESS; + } + + // Else clear enable bit of spi_enable register + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_clrbits_word(ALT_SPIM_SPIENR_ADDR(spi_dev->location), + ALT_SPIM_SPIENR_SPI_EN_SET_MSK); + break; + case ALT_SPI_OP_MODE_SLAVE: + alt_clrbits_word(ALT_SPIS_SPIENR_ADDR(spi_dev->location), + ALT_SPIS_SPIENR_SPI_EN_SET_MSK); + break; + } + + // Clear interrapts mask and clear interrupt status + alt_spi_int_disable(spi_dev, ALT_SPI_STATUS_ALL); + alt_spi_int_clear(spi_dev, ALT_SPI_STATUS_ALL); + + return ALT_E_SUCCESS; +} + +// +// Check whether spi controller is enable +// +ALT_STATUS_CODE alt_spi_is_enabled(ALT_SPI_DEV_t * spi_dev) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE en_status = ALT_E_FALSE; + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + en_status = ALT_SPIM_SPIENR_SPI_EN_GET(alt_read_word(ALT_SPIM_SPIENR_ADDR(spi_dev->location))); + break; + case ALT_SPI_OP_MODE_SLAVE: + en_status = ALT_SPIS_SPIENR_SPI_EN_GET(alt_read_word(ALT_SPIS_SPIENR_ADDR(spi_dev->location))); + break; + } + return en_status; +} + +ALT_STATUS_CODE alt_spi_is_busy(ALT_SPI_DEV_t *spi_dev) + +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + if (ALT_SPIM_SR_BUSY_GET(alt_read_word(ALT_SPIM_SR_ADDR(spi_dev->location)))) + { + return ALT_E_TRUE; + } + break; + case ALT_SPI_OP_MODE_SLAVE: + if (ALT_SPIS_SR_BUSY_GET(alt_read_word(ALT_SPIS_SR_ADDR(spi_dev->location)))) + { + return ALT_E_TRUE; + } + break; + } + + return ALT_E_FALSE; +} + +// +// Get config parameters from appropriate registers. +// +ALT_STATUS_CODE alt_spi_config_get(ALT_SPI_DEV_t *spi_dev, + ALT_SPI_CONFIG_t* cfg) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !cfg) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register; + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + cfg_register = alt_read_word(ALT_SPIM_CTLR0_ADDR(spi_dev->location)); + + cfg->frame_size = (ALT_SPI_DFS_t)ALT_SPIM_CTLR0_DFS_GET(cfg_register); + cfg->frame_format = (ALT_SPI_FRF_t)ALT_SPIM_CTLR0_FRF_GET(cfg_register); + cfg->clk_phase = (ALT_SPI_SCPH_t)ALT_SPIM_CTLR0_SCPH_GET(cfg_register); + cfg->clk_polarity = (ALT_SPI_SCPOL_t)ALT_SPIM_CTLR0_SCPOL_GET(cfg_register); + cfg->transfer_mode = (ALT_SPI_TMOD_t)ALT_SPIM_CTLR0_TMOD_GET(cfg_register); + cfg->loopback_mode = (bool)ALT_SPIM_CTLR0_SRL_GET(cfg_register); + break; + case ALT_SPI_OP_MODE_SLAVE: + cfg_register = alt_read_word(ALT_SPIS_CTLR0_ADDR(spi_dev->location)); + + cfg->frame_size = (ALT_SPI_DFS_t)ALT_SPIS_CTLR0_DFS_GET(cfg_register); + cfg->frame_format = (ALT_SPI_FRF_t)ALT_SPIS_CTLR0_FRF_GET(cfg_register); + cfg->clk_phase = (ALT_SPI_SCPH_t)ALT_SPIS_CTLR0_SCPH_GET(cfg_register); + cfg->clk_polarity = (ALT_SPI_SCPOL_t)ALT_SPIS_CTLR0_SCPOL_GET(cfg_register); + cfg->transfer_mode = (ALT_SPI_TMOD_t)ALT_SPIS_CTLR0_TMOD_GET(cfg_register); + cfg->slave_output_enable = (bool)ALT_SPIS_CTLR0_SLV_OE_GET(cfg_register); + cfg->loopback_mode = (bool)ALT_SPIS_CTLR0_SRL_GET(cfg_register); + break; + } + return ALT_E_SUCCESS; +} + +// +// Set config parameters to appropriate registers. +// +ALT_STATUS_CODE alt_spi_config_set(ALT_SPI_DEV_t *spi_dev, + const ALT_SPI_CONFIG_t* cfg) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !cfg) + { + return ALT_E_BAD_ARG; + } + + if (cfg->frame_size < ALT_SPI_DFS_4BIT ||cfg->frame_size > ALT_SPI_DFS_16BIT + || cfg->frame_format > ALT_SPI_FRF_MICROWIRE || cfg->clk_polarity > ALT_SPI_SCPOL_INACTIVE_HIGH + || cfg->clk_phase > ALT_SPI_SCPH_TOGGLE_START) + { + return ALT_E_ARG_RANGE; + } + + // Set config parameters to appropriate registers + uint32_t cfg_register; + uint32_t cfg_mask; + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + cfg_register = ALT_SPIM_CTLR0_DFS_SET(cfg->frame_size) + | ALT_SPIM_CTLR0_FRF_SET(cfg->frame_format) + | ALT_SPIM_CTLR0_SCPH_SET(cfg->clk_phase) + | ALT_SPIM_CTLR0_SCPOL_SET(cfg->clk_polarity) + | ALT_SPIM_CTLR0_TMOD_SET(cfg->transfer_mode) + | ALT_SPIM_CTLR0_SRL_SET(cfg->loopback_mode); + + cfg_mask = ALT_SPIM_CTLR0_DFS_SET_MSK + | ALT_SPIM_CTLR0_FRF_SET_MSK + | ALT_SPIM_CTLR0_SCPH_SET_MSK + | ALT_SPIM_CTLR0_SCPOL_SET_MSK + | ALT_SPIM_CTLR0_TMOD_SET_MSK + | ALT_SPIM_CTLR0_SRL_SET_MSK; + + alt_replbits_word(ALT_SPIM_CTLR0_ADDR(spi_dev->location), cfg_mask, cfg_register); + break; + case ALT_SPI_OP_MODE_SLAVE: + + cfg_register = ALT_SPIS_CTLR0_DFS_SET(cfg->frame_size) + | ALT_SPIS_CTLR0_FRF_SET(cfg->frame_format) + | ALT_SPIS_CTLR0_SCPH_SET(cfg->clk_phase) + | ALT_SPIS_CTLR0_SCPOL_SET(cfg->clk_polarity) + | ALT_SPIS_CTLR0_TMOD_SET(cfg->transfer_mode) + | ALT_SPIS_CTLR0_SLV_OE_SET(cfg->slave_output_enable) + | ALT_SPIS_CTLR0_SRL_SET(cfg->loopback_mode); + + cfg_mask = ALT_SPIS_CTLR0_DFS_SET_MSK + | ALT_SPIS_CTLR0_FRF_SET_MSK + | ALT_SPIS_CTLR0_SCPH_SET_MSK + | ALT_SPIS_CTLR0_SCPOL_SET_MSK + | ALT_SPIS_CTLR0_TMOD_SET_MSK + | ALT_SPIS_CTLR0_SLV_OE_SET_MSK + | ALT_SPIS_CTLR0_SRL_SET_MSK; + + alt_replbits_word(ALT_SPIS_CTLR0_ADDR(spi_dev->location), cfg_mask, cfg_register); + break; + } + + spi_dev->last_transfer_mode = cfg->transfer_mode; + + return status; + +} + +// +// Get config parameters from appropriate registers for microwire mode. +// +ALT_STATUS_CODE alt_spi_mw_config_get(ALT_SPI_DEV_t *spi_dev, + ALT_SPI_MW_CONFIG_t* cfg) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !cfg) + { + return ALT_E_BAD_ARG; + } + + uint32_t cfg_register, mwcr_register; + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + cfg_register = alt_read_word(ALT_SPIM_CTLR0_ADDR(spi_dev->location)); + mwcr_register = alt_read_word(ALT_SPIM_MWCR_ADDR(spi_dev->location)); + + cfg->ctl_frame_size = ALT_SPIM_CTLR0_DFS_GET(cfg_register); + cfg->mode = (ALT_SPI_MW_MODE_t)ALT_SPIM_MWCR_MWMOD_GET(mwcr_register); + cfg->dir = (ALT_SPI_MW_DIR_t)ALT_SPIM_MWCR_MDD_GET(mwcr_register); + cfg->handshake_enabled = ALT_SPIM_MWCR_MHS_GET(mwcr_register); + break; + case ALT_SPI_OP_MODE_SLAVE: + cfg_register = alt_read_word(ALT_SPIS_CTLR0_ADDR(spi_dev->location)); + mwcr_register = alt_read_word(ALT_SPIS_MWCR_ADDR(spi_dev->location)); + + cfg->ctl_frame_size = ALT_SPIS_CTLR0_DFS_GET(cfg_register); + cfg->mode = (ALT_SPI_MW_MODE_t)ALT_SPIS_MWCR_MWMOD_GET(mwcr_register); + cfg->dir = (ALT_SPI_MW_DIR_t)ALT_SPIS_MWCR_MDD_GET(mwcr_register); + break; + } + return ALT_E_SUCCESS; +} + +// +// Set config parameters to appropriate registers for microwire mode. +// +ALT_STATUS_CODE alt_spi_mw_config_set(ALT_SPI_DEV_t *spi_dev, + const ALT_SPI_MW_CONFIG_t* cfg) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !cfg) + { + return ALT_E_BAD_ARG; + } + + if (cfg->ctl_frame_size > ALT_SPI_MW_CTL_FRAME_SIZE_MAX + || cfg->mode > ALT_SPI_MW_SEQUENTIAL || cfg->dir > ALT_SPI_MW_DIR_TX) + { + return ALT_E_ARG_RANGE; + } + + // Set config parameters to appropriate registers + uint32_t mwcr_register; + uint32_t mwcr_mask; + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + mwcr_register = ALT_SPIM_MWCR_MWMOD_SET(cfg->mode) + | ALT_SPIM_MWCR_MDD_SET(cfg->dir) + | ALT_SPIM_MWCR_MHS_SET(cfg->handshake_enabled); + + mwcr_mask = ALT_SPIM_MWCR_MWMOD_SET_MSK + | ALT_SPIM_MWCR_MDD_SET_MSK + | ALT_SPIM_MWCR_MHS_SET_MSK; + + alt_replbits_word(ALT_SPIM_MWCR_ADDR(spi_dev->location), mwcr_mask, mwcr_register); + alt_replbits_word(ALT_SPIM_CTLR0_ADDR(spi_dev->location), + ALT_SPIM_CTLR0_DFS_SET_MSK, + ALT_SPIM_CTLR0_DFS_SET(cfg->ctl_frame_size)); + break; + case ALT_SPI_OP_MODE_SLAVE: + mwcr_register = ALT_SPIS_MWCR_MWMOD_SET(cfg->mode) + | ALT_SPIS_MWCR_MDD_SET(cfg->dir); + + mwcr_mask = ALT_SPIS_MWCR_MWMOD_SET_MSK + | ALT_SPIS_MWCR_MDD_SET_MSK; + + alt_replbits_word(ALT_SPIS_MWCR_ADDR(spi_dev->location), mwcr_mask, mwcr_register); + alt_replbits_word(ALT_SPIS_CTLR0_ADDR(spi_dev->location), + ALT_SPIS_CTLR0_DFS_SET_MSK, + ALT_SPIS_CTLR0_DFS_SET(cfg->ctl_frame_size)); + break; + } + + return status; + +} + +// +// Disable the specified SPI controller slave select output lines.. +// +ALT_STATUS_CODE alt_spi_slave_select_disable(ALT_SPI_DEV_t *spi_dev, + const uint32_t mask) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (mask > ALT_SPI_SLAVE_MASK_ALL) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_clrbits_word(ALT_SPIM_SER_ADDR(spi_dev->location), mask); + break; + case ALT_SPI_OP_MODE_SLAVE: + status = ALT_E_ERROR; + break; + } + + return status; +} + +// +// Enable the specified SPI controller slave select output lines. +// +ALT_STATUS_CODE alt_spi_slave_select_enable(ALT_SPI_DEV_t *spi_dev, + const uint32_t mask) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (mask > ALT_SPI_SLAVE_MASK_ALL) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_setbits_word(ALT_SPIM_SER_ADDR(spi_dev->location), mask); + break; + case ALT_SPI_OP_MODE_SLAVE: + status = ALT_E_ERROR; + break; + } + + return status; +} + +// +// Get the configured baud rate divider value for the specified SPI controller +// +ALT_STATUS_CODE alt_spi_divider_get(ALT_SPI_DEV_t *spi_dev, uint32_t *div) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *div = ALT_SPIM_BAUDR_SCKDV_GET(alt_read_word(ALT_SPIM_BAUDR_ADDR(spi_dev->location))); + break; + case ALT_SPI_OP_MODE_SLAVE: + default: + return ALT_E_ERROR; + } + + return ALT_E_SUCCESS; +} + +// +// Set the baud rate divider to configure the generated sclk_out frequency +// +ALT_STATUS_CODE alt_spi_divider_set(ALT_SPI_DEV_t *spi_dev, const uint32_t div) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (spi_dev->op_mode != ALT_SPI_OP_MODE_MASTER) + { + return ALT_E_ERROR; + } + + if (div < ALT_SPI_MIN_CLK_DIV || div > ALT_SPI_MAX_CLK_DIV) + { + return ALT_E_BAD_ARG; + } + + ///// + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + bool already_enabled = (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE); + + if (already_enabled) + { + // Temporarily disable controller + status = alt_spi_disable(spi_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + alt_replbits_word(ALT_SPIM_BAUDR_ADDR(spi_dev->location), + ALT_SPIM_BAUDR_SCKDV_SET_MSK, + ALT_SPIM_BAUDR_SCKDV_SET(div)); + + if (already_enabled) + { + // Re-enable controller + status = alt_spi_enable(spi_dev); + } + + return status; +} + + +// +// Get the configured baud rate divider value for the specified SPI controller +// +ALT_STATUS_CODE alt_spi_baud_rate_get(ALT_SPI_DEV_t *spi_dev, uint32_t *div) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !div) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *div = ALT_SPIM_BAUDR_SCKDV_GET(alt_read_word(ALT_SPIM_BAUDR_ADDR(spi_dev->location))); + break; + case ALT_SPI_OP_MODE_SLAVE: + status = ALT_E_ERROR; + break; + } + + return status; +} + +// +// Set the baud rate divider to configure the generated sclk_out frequency +// +ALT_STATUS_CODE alt_spi_baud_rate_set(ALT_SPI_DEV_t *spi_dev, const uint32_t div) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE ) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + if(div < ALT_SPI_MIN_CLK_DIV || div > ALT_SPI_MAX_CLK_DIV) + { + status = ALT_E_BAD_ARG; + break; + } + alt_replbits_word(ALT_SPIM_BAUDR_ADDR(spi_dev->location), + ALT_SPIM_BAUDR_SCKDV_SET_MSK, + ALT_SPIM_BAUDR_SCKDV_SET(div)); + break; + case ALT_SPI_OP_MODE_SLAVE: + status = ALT_E_ERROR; + break; + } + + return status; + +} + +// +// Return bus speed by configuration of spi controller for master mode. +// +ALT_STATUS_CODE alt_spi_speed_get(ALT_SPI_DEV_t * spi_dev, + uint32_t * speed_in_hz) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + uint32_t div; + + status = alt_spi_divider_get(spi_dev, &div); + if (status != ALT_E_SUCCESS) + { + return status; + } + + if (div < ALT_SPI_MIN_CLK_DIV || div > ALT_SPI_MAX_CLK_DIV) + { + return ALT_E_BAD_ARG; + } + + // = / + *speed_in_hz = spi_dev->clock_freq / div; + + return ALT_E_SUCCESS; +} + +// +// Fill struct with configuration of spi controller for master mode by bus speed +// +ALT_STATUS_CODE alt_spi_speed_set(ALT_SPI_DEV_t * spi_dev, + uint32_t speed_in_hz) + +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // If speed is not standard or fast return range error + if (speed_in_hz > spi_dev->clock_freq || speed_in_hz == 0) + { + return ALT_E_ARG_RANGE; + } + + // = / + uint32_t div = spi_dev->clock_freq / speed_in_hz; + + return alt_spi_divider_set(spi_dev, div); +} + +// +// Fill struct with configuration of spi controller for master mode by bus speed +// +ALT_STATUS_CODE alt_spi_speed_to_divider(ALT_SPI_DEV_t * spi_dev, + uint32_t speed_in_hz, + uint32_t * div) + +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !div) + { + return ALT_E_BAD_ARG; + } + + // If speed is not standard or fast return range error + if (speed_in_hz > spi_dev->clock_freq || speed_in_hz == 0) + { + return ALT_E_ARG_RANGE; + } + + // = / + *div = spi_dev->clock_freq / speed_in_hz; + + return ALT_E_SUCCESS; +} + +// +// Return bus speed by configuration of spi controller for master mode. +// +ALT_STATUS_CODE alt_spi_divider_to_speed(ALT_SPI_DEV_t * spi_dev, + uint32_t * speed_in_hz, + const uint32_t * div) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !div) + { + return ALT_E_BAD_ARG; + } + + if (*div < ALT_SPI_MIN_CLK_DIV || *div > ALT_SPI_MAX_CLK_DIV) + { + return ALT_E_BAD_ARG; + } + + // = / + *speed_in_hz = spi_dev->clock_freq / *div; + + return ALT_E_SUCCESS; +} + +// +// Get the current number of data frames configured for the SPI controller. +// +ALT_STATUS_CODE alt_spi_num_data_frames_get(ALT_SPI_DEV_t *spi_dev, uint32_t *num_data_frames) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !num_data_frames) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *num_data_frames = ALT_SPIM_CTLR1_NDF_GET(alt_read_word(ALT_SPIM_CTLR1_ADDR(spi_dev->location))); + break; + case ALT_SPI_OP_MODE_SLAVE: + status = ALT_E_ERROR; + break; + } + + return status; +} + +// +// Set the number of data frames configured for the SPI controller. +// +ALT_STATUS_CODE alt_spi_num_data_frames_set(ALT_SPI_DEV_t *spi_dev, const uint32_t num_data_frames) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE ) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + if(num_data_frames & ALT_SPIM_CTLR1_NDF_CLR_MSK) + { + status = ALT_E_BAD_ARG; + break; + } + alt_replbits_word(ALT_SPIM_CTLR1_ADDR(spi_dev->location), + ALT_SPIM_CTLR1_NDF_SET_MSK, + ALT_SPIM_CTLR1_NDF_SET(num_data_frames)); + break; + case ALT_SPI_OP_MODE_SLAVE: + status = ALT_E_ERROR; + break; + } + + return status; + +} + +// +// Returns the current SPI controller interrupt status conditions. +// +ALT_STATUS_CODE alt_spi_int_status_get(ALT_SPI_DEV_t *spi_dev, + uint32_t *status) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !status) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *status = alt_read_word(ALT_SPIM_ISR_ADDR(spi_dev->location)); + break; + case ALT_SPI_OP_MODE_SLAVE: + *status = alt_read_word(ALT_SPIS_ISR_ADDR(spi_dev->location)); + break; + } + + return ALT_E_SUCCESS; +} + +// +// Returns the SPI controller raw interrupt status conditions irrespective of +// the interrupt status condition enablement state. +// +ALT_STATUS_CODE alt_spi_int_raw_status_get(ALT_SPI_DEV_t *spi_dev, + uint32_t *status) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !status) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *status = alt_read_word(ALT_SPIM_RISR_ADDR(spi_dev->location)); + break; + case ALT_SPI_OP_MODE_SLAVE: + *status = alt_read_word(ALT_SPIS_RISR_ADDR(spi_dev->location)); + break; + } + + return ALT_E_SUCCESS; +} + +// +// Clears the specified SPI controller interrupt status conditions identified +// in the mask (for slave mode). +// +static ALT_STATUS_CODE alt_spi_slave_int_clear(ALT_SPI_DEV_t *spi_dev, const uint32_t mask) +{ + if (mask == ALT_SPI_STATUS_ALL) + { + alt_read_word(ALT_SPIS_ICR_ADDR(spi_dev->location)); + return ALT_E_SUCCESS; + } + + // For different status clear different register + if (mask & ALT_SPI_STATUS_TXOI) + { + alt_read_word(ALT_SPIS_TXOICR_ADDR(spi_dev->location)); + } + if (mask & ALT_SPI_STATUS_RXOI) + { + alt_read_word(ALT_SPIS_RXOICR_ADDR(spi_dev->location)); + } + if (mask & ALT_SPI_STATUS_RXUI) + { + alt_read_word(ALT_SPIS_RXUICR_ADDR(spi_dev->location)); + } + + return ALT_E_SUCCESS; +} + +// +// Clears the specified SPI controller interrupt status conditions identified +// in the mask (for master mode). +// +static ALT_STATUS_CODE alt_spi_master_int_clear(ALT_SPI_DEV_t *spi_dev, const uint32_t mask) +{ + if (mask == ALT_SPI_STATUS_ALL) + { + alt_read_word(ALT_SPIM_ICR_ADDR(spi_dev->location)); + return ALT_E_SUCCESS; + } + + // For different status clear different register + if (mask & ALT_SPI_STATUS_TXOI) + { + alt_read_word(ALT_SPIM_TXOICR_ADDR(spi_dev->location)); + } + if (mask & ALT_SPI_STATUS_RXOI) + { + alt_read_word(ALT_SPIM_RXOICR_ADDR(spi_dev->location)); + } + if (mask & ALT_SPI_STATUS_RXUI) + { + alt_read_word(ALT_SPIM_RXUICR_ADDR(spi_dev->location)); + } + + return ALT_E_SUCCESS; +} + +// +// Clears the specified SPI controller interrupt status conditions identified +// in the mask. +// +ALT_STATUS_CODE alt_spi_int_clear(ALT_SPI_DEV_t *spi_dev, const uint32_t mask) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + status = alt_spi_master_int_clear(spi_dev, mask); + break; + case ALT_SPI_OP_MODE_SLAVE: + status = alt_spi_slave_int_clear(spi_dev, mask); + break; + } + return status; +} + +// +// Disable the specified SPI controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_spi_int_disable(ALT_SPI_DEV_t *spi_dev, const uint32_t mask) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_clrbits_word(ALT_SPIM_IMR_ADDR(spi_dev->location), mask); + break; + case ALT_SPI_OP_MODE_SLAVE: + alt_clrbits_word(ALT_SPIS_IMR_ADDR(spi_dev->location), mask); + break; + } + + return ALT_E_SUCCESS; +} + +// +// Enable the specified SPI controller interrupt status conditions identified in +// the mask. +// +ALT_STATUS_CODE alt_spi_int_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t mask) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_setbits_word(ALT_SPIM_IMR_ADDR(spi_dev->location), mask); + break; + case ALT_SPI_OP_MODE_SLAVE: + alt_setbits_word(ALT_SPIS_IMR_ADDR(spi_dev->location), mask); + break; + } + + return ALT_E_SUCCESS; +} + +// +// Returns ALT_E_TRUE when the receive FIFO is empty. +// +ALT_STATUS_CODE alt_spi_rx_fifo_is_empty(ALT_SPI_DEV_t *spi_dev) +{ + ALT_STATUS_CODE status = ALT_E_FALSE; + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + if (ALT_SPIM_SR_RFNE_GET(alt_read_word(ALT_SPIM_SR_ADDR(spi_dev->location))) == ALT_SPIM_SR_RFNE_E_EMPTY) + { + status = ALT_E_TRUE; + } + break; + case ALT_SPI_OP_MODE_SLAVE: + if (ALT_SPIS_SR_RFNE_GET(alt_read_word(ALT_SPIS_SR_ADDR(spi_dev->location))) == ALT_SPIS_SR_RFNE_E_EMPTY) + { + status = ALT_E_TRUE; + } + break; + } + return status; +} + +// +// Returns ALT_E_TRUE when the receive FIFO is completely full. +// +ALT_STATUS_CODE alt_spi_rx_fifo_is_full(ALT_SPI_DEV_t *spi_dev) +{ + ALT_STATUS_CODE status = ALT_E_FALSE; + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + if (ALT_SPIM_SR_RFF_GET(alt_read_word(ALT_SPIM_SR_ADDR(spi_dev->location))) == ALT_SPIM_SR_RFF_E_FULL) + { + status = ALT_E_TRUE; + } + break; + case ALT_SPI_OP_MODE_SLAVE: + if (ALT_SPIS_SR_RFF_GET(alt_read_word(ALT_SPIS_SR_ADDR(spi_dev->location))) == ALT_SPIS_SR_RFF_E_FULL) + { + status = ALT_E_TRUE; + } + break; + } + return status; +} + +// +// Returns the number of valid entries in the receive FIFO. +// +ALT_STATUS_CODE alt_spi_rx_fifo_level_get(ALT_SPI_DEV_t *spi_dev, + uint32_t *num_entries) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !num_entries) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *num_entries = ALT_SPIM_RXFLR_RXTFL_GET(alt_read_word(ALT_SPIM_RXFLR_ADDR(spi_dev->location))); + break; + case ALT_SPI_OP_MODE_SLAVE: + *num_entries = ALT_SPIS_RXFLR_RXTFL_GET(alt_read_word(ALT_SPIS_RXFLR_ADDR(spi_dev->location))); + break; + } + + return ALT_E_SUCCESS; + +} + +// +// Gets the current receive FIFO threshold level value. +// +ALT_STATUS_CODE alt_spi_rx_fifo_threshold_get(ALT_SPI_DEV_t *spi_dev, + uint8_t *threshold) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !threshold) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *threshold = ALT_SPIM_RXFTLR_RFT_GET(alt_read_word(ALT_SPIM_RXFTLR_ADDR(spi_dev->location))); + break; + case ALT_SPI_OP_MODE_SLAVE: + *threshold = ALT_SPIS_RXFTLR_RFT_GET(alt_read_word(ALT_SPIS_RXFTLR_ADDR(spi_dev->location))); + break; + } + + return ALT_E_SUCCESS; + +} + +// +// Sets the current receive FIFO threshold level value. +// +ALT_STATUS_CODE alt_spi_rx_fifo_threshold_set(ALT_SPI_DEV_t *spi_dev, + const uint8_t threshold) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_replbits_word(ALT_SPIM_RXFTLR_ADDR(spi_dev->location), + ALT_SPIM_RXFTLR_RFT_SET_MSK, + ALT_SPIM_RXFTLR_RFT_SET(threshold)); + + break; + case ALT_SPI_OP_MODE_SLAVE: + alt_replbits_word(ALT_SPIS_RXFTLR_ADDR(spi_dev->location), + ALT_SPIS_RXFTLR_RFT_SET_MSK, + ALT_SPIS_RXFTLR_RFT_SET(threshold)); + + break; + } + + return status; +} + +// +// Returns ALT_E_TRUE when the transmit FIFO is empty. +// +ALT_STATUS_CODE alt_spi_tx_fifo_is_empty(ALT_SPI_DEV_t *spi_dev) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + if (ALT_SPIM_SR_TFE_GET(alt_read_word(ALT_SPIM_SR_ADDR(spi_dev->location))) == ALT_SPIM_SR_TFE_E_EMPTY) + { + return ALT_E_TRUE; + } + break; + case ALT_SPI_OP_MODE_SLAVE: + if (ALT_SPIS_SR_TFE_GET(alt_read_word(ALT_SPIS_SR_ADDR(spi_dev->location))) == ALT_SPIS_SR_TFE_E_EMPTY) + { + return ALT_E_TRUE; + } + break; + } + + return ALT_E_FALSE; +} + +// +// Returns ALT_E_TRUE when the transmit FIFO is completely full. +// +ALT_STATUS_CODE alt_spi_tx_fifo_is_full(ALT_SPI_DEV_t *spi_dev) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + if (ALT_SPIM_SR_TFNF_GET(alt_read_word(ALT_SPIM_SR_ADDR(spi_dev->location))) == ALT_SPIM_SR_TFNF_E_FULL) + { + return ALT_E_TRUE; + } + break; + case ALT_SPI_OP_MODE_SLAVE: + if (ALT_SPIS_SR_TFNF_GET(alt_read_word(ALT_SPIS_SR_ADDR(spi_dev->location))) == ALT_SPIS_SR_TFNF_E_FULL) + { + return ALT_E_TRUE; + } + break; + } + + return ALT_E_FALSE; +} + +// +// Returns the number of valid entries in the transmit FIFO. +// +ALT_STATUS_CODE alt_spi_tx_fifo_level_get(ALT_SPI_DEV_t *spi_dev, + uint32_t *num_entries) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !num_entries) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *num_entries = ALT_SPIM_TXFLR_TXTFL_GET(alt_read_word(ALT_SPIM_TXFLR_ADDR(spi_dev->location))); + break; + case ALT_SPI_OP_MODE_SLAVE: + *num_entries = ALT_SPIS_TXFLR_TXTFL_GET(alt_read_word(ALT_SPIS_TXFLR_ADDR(spi_dev->location))); + break; + } + + return ALT_E_SUCCESS; + +} + + +// +// Sets the current transmit FIFO threshold level value. +// +ALT_STATUS_CODE alt_spi_tx_fifo_threshold_get(ALT_SPI_DEV_t *spi_dev, + uint8_t *threshold) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !threshold) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *threshold = ALT_SPIM_TXFTLR_TFT_GET(alt_read_word(ALT_SPIM_TXFTLR_ADDR(spi_dev->location))); + break; + case ALT_SPI_OP_MODE_SLAVE: + *threshold = ALT_SPIS_TXFTLR_TFT_GET(alt_read_word(ALT_SPIS_TXFTLR_ADDR(spi_dev->location))); + break; + } + + return ALT_E_SUCCESS; + +} + +// +// Sets the current transmit FIFO threshold level value. +// +ALT_STATUS_CODE alt_spi_tx_fifo_threshold_set(ALT_SPI_DEV_t *spi_dev, + const uint8_t threshold) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_replbits_word(ALT_SPIM_TXFTLR_ADDR(spi_dev->location), + ALT_SPIM_TXFTLR_TFT_SET_MSK, + ALT_SPIM_TXFTLR_TFT_SET(threshold)); + break; + case ALT_SPI_OP_MODE_SLAVE: + alt_replbits_word(ALT_SPIS_TXFTLR_ADDR(spi_dev->location), + ALT_SPIS_TXFTLR_TFT_SET_MSK, + ALT_SPIS_TXFTLR_TFT_SET(threshold)); + break; + } + + return status; +} + +// +// Get the configured Rx sample delay value. +// +ALT_STATUS_CODE alt_spi_rx_sample_delay_get(ALT_SPI_DEV_t *spi_dev, uint32_t *delay) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !delay) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *delay = ALT_SPIM_RX_SMPL_DLY_RSD_GET(alt_read_word(ALT_SPIM_RX_SMPL_DLY_ADDR(spi_dev->location))); + break; + case ALT_SPI_OP_MODE_SLAVE: + status = ALT_E_ERROR; + break; + } + + return status; +} + +// +// Set the configured Rx sample delay value. +// +ALT_STATUS_CODE alt_spi_rx_sample_delay_set(ALT_SPI_DEV_t *spi_dev, const uint32_t delay) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + if(delay & ALT_SPIM_RX_SMPL_DLY_RSD_CLR_MSK) + { + status = ALT_E_BAD_ARG; + break; + } + alt_replbits_word(ALT_SPIM_RX_SMPL_DLY_ADDR(spi_dev->location), + ALT_SPIM_RX_SMPL_DLY_RSD_SET_MSK, + ALT_SPIM_RX_SMPL_DLY_RSD_SET(delay)); + break; + case ALT_SPI_OP_MODE_SLAVE: + status = ALT_E_ERROR; + break; + } + + return status; +} + +// +// Disable the transmit (Tx) FIFO DMA channel. +// +ALT_STATUS_CODE alt_spi_dma_tx_disable(ALT_SPI_DEV_t *spi_dev) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // Else clear enable bit of spi_enable register + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_clrbits_word(ALT_SPIM_DMACR_ADDR(spi_dev->location), + ALT_SPIM_DMACR_TDMAE_SET_MSK); + break; + case ALT_SPI_OP_MODE_SLAVE: + alt_clrbits_word(ALT_SPIS_DMACR_ADDR(spi_dev->location), + ALT_SPIS_DMACR_TDMAE_SET_MSK); + break; + } + + return ALT_E_SUCCESS; +} + +// +// Enable and set the transmit data level for the transmit (Tx) FIFO DMA channel. +// +ALT_STATUS_CODE alt_spi_dma_tx_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t level) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_setbits_word(ALT_SPIM_DMACR_ADDR(spi_dev->location), + ALT_SPIM_DMACR_TDMAE_SET_MSK); + if(level & ALT_SPIM_DMATDLR_DMATDL_CLR_MSK) + { + status = ALT_E_BAD_ARG; + break; + } + alt_replbits_word(ALT_SPIM_DMATDLR_ADDR(spi_dev->location), + ALT_SPIM_DMATDLR_DMATDL_SET_MSK, + ALT_SPIM_DMATDLR_DMATDL_SET(level)); + break; + case ALT_SPI_OP_MODE_SLAVE: + if(level & ALT_SPIS_DMATDLR_DMATDL_CLR_MSK) + { + status = ALT_E_BAD_ARG; + break; + } + alt_setbits_word( ALT_SPIS_DMACR_ADDR(spi_dev->location), + ALT_SPIS_DMACR_TDMAE_SET_MSK); + alt_replbits_word(ALT_SPIS_DMATDLR_ADDR(spi_dev->location), + ALT_SPIS_DMATDLR_DMATDL_SET_MSK, + ALT_SPIS_DMATDLR_DMATDL_SET(level)); + break; + } + + return status; +} + +// +// Disable the receive (Rx) FIFO DMA channel. +// +ALT_STATUS_CODE alt_spi_dma_rx_disable(ALT_SPI_DEV_t *spi_dev) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + // Else clear enable bit of spi_enable register + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_clrbits_word(ALT_SPIM_DMACR_ADDR(spi_dev->location), + ALT_SPIM_DMACR_RDMAE_SET_MSK); + break; + case ALT_SPI_OP_MODE_SLAVE: + alt_clrbits_word(ALT_SPIS_DMACR_ADDR(spi_dev->location), + ALT_SPIS_DMACR_RDMAE_SET_MSK); + break; + } + + return ALT_E_SUCCESS; +} + +// +// Enable and set the receive data level for the receive (Rx) FIFO DMA channel. +// +ALT_STATUS_CODE alt_spi_dma_rx_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t level) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_setbits_word( ALT_SPIM_DMACR_ADDR(spi_dev->location), + ALT_SPIM_DMACR_RDMAE_SET_MSK); + if(level & ALT_SPIM_DMARDLR_DMARDL_CLR_MSK) + { + status = ALT_E_BAD_ARG; + break; + } + alt_replbits_word(ALT_SPIM_DMARDLR_ADDR(spi_dev->location), + ALT_SPIM_DMARDLR_DMARDL_SET_MSK, + ALT_SPIM_DMARDLR_DMARDL_SET(level)); + break; + case ALT_SPI_OP_MODE_SLAVE: + if(level & ALT_SPIS_DMARDLR_DMARDL_CLR_MSK) + { + status = ALT_E_BAD_ARG; + break; + } + alt_setbits_word( ALT_SPIS_DMACR_ADDR(spi_dev->location), + ALT_SPIS_DMACR_RDMAE_SET_MSK); + alt_replbits_word(ALT_SPIS_DMARDLR_ADDR(spi_dev->location), + ALT_SPIS_DMARDLR_DMARDL_SET_MSK, + ALT_SPIS_DMARDLR_DMARDL_SET(level)); + break; + } + + return status; +} + +// +// Reads a data frame from the receive (Rx) FIFO. +// +ALT_STATUS_CODE alt_spi_rx_fifo_deq(ALT_SPI_DEV_t *spi_dev, uint16_t *data) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE || !data) + { + return ALT_E_BAD_ARG; + } + + if (alt_spi_is_enabled(spi_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + *data = (ALT_SPIM_DR_DR_GET(alt_read_word(ALT_SPIM_DR_ADDR(spi_dev->location)))); + break; + case ALT_SPI_OP_MODE_SLAVE: + *data = (ALT_SPIS_DR_DR_GET(alt_read_word(ALT_SPIS_DR_ADDR(spi_dev->location)))); + break; + } + + return ALT_E_SUCCESS; +} + +// +// Writes a data frame to the transmit (Tx) FIFO for transmittal. +// +ALT_STATUS_CODE alt_spi_tx_fifo_enq(ALT_SPI_DEV_t *spi_dev, const uint16_t data) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (alt_spi_is_enabled(spi_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + switch (spi_dev->op_mode) + { + case ALT_SPI_OP_MODE_MASTER: + alt_write_word(ALT_SPIM_DR_ADDR(spi_dev->location), ALT_SPIM_DR_DR_SET(data)); + break; + case ALT_SPI_OP_MODE_SLAVE: + alt_write_word(ALT_SPIS_DR_ADDR(spi_dev->location), ALT_SPIS_DR_DR_SET(data)); + break; + } + + return ALT_E_SUCCESS; +} + +// +// This function writes a single data byte to the transmit FIFO. +// +static ALT_STATUS_CODE alt_spi_transmit_error_handler(ALT_SPI_DEV_t *spi_dev, ALT_STATUS_CODE *err_status) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t int_status = 0; + + status = alt_spi_int_raw_status_get(spi_dev, &int_status); + + if (status == ALT_E_TRUE && int_status != 0) + { + if(int_status + & (ALT_SPI_STATUS_TXOI + | ALT_SPI_STATUS_RXOI + | ALT_SPI_STATUS_RXUI)) + { + *err_status = ALT_E_BUF_OVF; + } + } + + return status; +} + +// +// Write or read bulk of data form master mode +// +static ALT_STATUS_CODE alt_spi_master_transfer_helper(ALT_SPI_DEV_t *spi_dev, + size_t data_send, + size_t data_recv, + const uint16_t * tx_buf, + uint16_t * rx_buf) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + const uint16_t * buffer_tx = tx_buf; + uint16_t * buffer_rx = rx_buf; + uint32_t timeout = MAX(data_send, data_recv) * 10000; + + while (data_send > 0 || data_recv > 0) + { + // Error handling + ALT_STATUS_CODE err_status = 0; + status = alt_spi_transmit_error_handler(spi_dev, &err_status); + + if (status != ALT_E_SUCCESS) + { + break; + } + + if (err_status != ALT_E_SUCCESS) + { + status = err_status; + break; + } + + // Top up the TX FIFO with sending data + + if (data_send > 0) + { + uint32_t level = 0; + status = alt_spi_tx_fifo_level_get(spi_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t space = ALT_SPI_TX_FIFO_NUM_ENTRIES - level; + + space = MIN(data_send, space); + + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_SPIM_DR_ADDR(spi_dev->location), ALT_SPIM_DR_DR_SET(*buffer_tx)); + ++buffer_tx; + } + + data_send -= space; + } + + // Read out the resulting received data as they come in. + + if (data_recv > 0) + { + uint32_t level = 0; + status = alt_spi_rx_fifo_level_get(spi_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + if (level == 0) + { + timeout--; + if (timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + + level = MIN(data_recv, level); + + for (uint32_t i = 0; i < level; ++i) + { + uint32_t data_read = alt_read_word(ALT_SPIM_DR_ADDR(spi_dev->location)); + *buffer_rx = (ALT_SPIM_DR_DR_GET(data_read)); + //printf("data %x\n", (unsigned int)data_read); + ++buffer_rx; + } + + data_recv -= level; + } + } + + return status; +} + +// +// This function performs a master SPI/SSP serial master transfer operations (use by all transfer functions). +// +static ALT_STATUS_CODE alt_spi_master_transfer(ALT_SPI_DEV_t *spi_dev, + const uint32_t slave_select, + const size_t num_frames, + const uint16_t * tx_buf, + uint16_t * rx_buf, + ALT_SPI_TMOD_t transfer_mode, + const uint8_t opcode, + const uint32_t eeprom_addr) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (spi_dev->op_mode == ALT_SPI_OP_MODE_SLAVE) + { + return ALT_E_ERROR; + } + + if (num_frames == 0) + { + return ALT_E_SUCCESS; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + if(alt_spi_is_busy(spi_dev) == ALT_E_TRUE) + { + return ALT_E_ERROR; + } + + // Checking necessity to update slave mask + if (slave_select != spi_dev->last_slave_mask) + { + status = alt_spi_disable(spi_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + // Update slave select mask + alt_spi_slave_select_disable(spi_dev, ALT_SPI_SLAVE_MASK_ALL); + status = alt_spi_slave_select_enable(spi_dev, slave_select); + if (status != ALT_E_SUCCESS) + { + return status; + } + + spi_dev->last_slave_mask = slave_select; + } + + // Checking necessity to update transfer mode + if (transfer_mode != spi_dev->last_transfer_mode) + { + status = alt_spi_disable(spi_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + // Update transfer mode + alt_replbits_word(ALT_SPIM_CTLR0_ADDR(spi_dev->location), + ALT_SPIM_CTLR0_TMOD_SET_MSK, + ALT_SPIM_CTLR0_TMOD_SET(transfer_mode)); + spi_dev->last_transfer_mode = transfer_mode; + } + + if (transfer_mode == ALT_SPI_TMOD_RX || transfer_mode == ALT_SPI_TMOD_EEPROM) + { + status = alt_spi_disable(spi_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + // Set number of data frames for read + status = alt_spi_num_data_frames_set(spi_dev, num_frames - 1); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + // Clear interrupt status and disable interrupt mask + alt_spi_int_clear(spi_dev, ALT_SPI_STATUS_ALL); + alt_spi_int_disable(spi_dev, ALT_SPI_STATUS_ALL); + + if (alt_spi_is_enabled(spi_dev) == ALT_E_FALSE) + { + status = alt_spi_enable(spi_dev); + if (status != ALT_E_SUCCESS) + { + return status; + } + } + + //Enable abort and TXFIFO empty interrupt status + alt_spi_int_enable(spi_dev, ALT_SPI_STATUS_RXOI | + ALT_SPI_STATUS_RXUI | + ALT_SPI_STATUS_TXOI); + + // This SPI controller requires that a read issue be performed for each byte requested. + // Read issue takes space in the TX FIFO, which may asynchronously handling a previous request. + + uint32_t data_send = 0; + uint32_t data_recv = 0; + + if (transfer_mode == ALT_SPI_TMOD_TX || transfer_mode == ALT_SPI_TMOD_TXRX) + { + data_send = num_frames; + } + + if (transfer_mode == ALT_SPI_TMOD_RX || + transfer_mode == ALT_SPI_TMOD_TXRX || + transfer_mode == ALT_SPI_TMOD_EEPROM) + { + data_recv = num_frames; + } + + if (transfer_mode == ALT_SPI_TMOD_EEPROM) + { + //Send opcode and eeprom address + alt_write_word(ALT_SPIM_DR_ADDR(spi_dev->location), ALT_SPIM_DR_DR_SET(opcode)); + alt_write_word(ALT_SPIM_DR_ADDR(spi_dev->location), ALT_SPIM_DR_DR_SET(((eeprom_addr & 0xFF00) >> 8))); + alt_write_word(ALT_SPIM_DR_ADDR(spi_dev->location), ALT_SPIM_DR_DR_SET(eeprom_addr & 0xFF)); + } + if (transfer_mode == ALT_SPI_TMOD_RX) + { + //Activate rx transfer + alt_spi_tx_fifo_enq(spi_dev, 0); + } + + // Write or read bulk of data + status = alt_spi_master_transfer_helper(spi_dev, + data_send, data_recv, + tx_buf, + rx_buf); + + // Need reset for set spi bus in idle state + if(status == ALT_E_TMO) + alt_spi_reset(spi_dev); + + // Mask all interrupts + alt_spi_int_disable(spi_dev, ALT_SPI_STATUS_ALL); + + return status; +} + +// +// This function performs a master SPI/SSP serial transmit and receive transfer. +// +ALT_STATUS_CODE alt_spi_master_tx_rx_transfer(ALT_SPI_DEV_t *spi_dev, + const uint32_t slave_select, + const size_t num_frames, + const uint16_t * tx_buf, + uint16_t * rx_buf) +{ + return alt_spi_master_transfer(spi_dev, + slave_select, + num_frames, + tx_buf, + rx_buf, + ALT_SPI_TMOD_TXRX, + 0, 0); +} + +// +// This function performs a master SPI/SSP serial transmit only transfer. +// +ALT_STATUS_CODE alt_spi_master_tx_transfer(ALT_SPI_DEV_t *spi_dev, + const uint32_t slave_select, + const size_t num_frames, + const uint16_t * tx_buf) +{ + return alt_spi_master_transfer(spi_dev, + slave_select, + num_frames, + tx_buf, NULL, + ALT_SPI_TMOD_TX, + 0, 0); +} + +// +// This function performs a master SPI/SSP serial receive only transfer. +// +ALT_STATUS_CODE alt_spi_master_rx_transfer(ALT_SPI_DEV_t *spi_dev, + const uint32_t slave_select, + const size_t num_frames, + uint16_t * rx_buf) +{ + return alt_spi_master_transfer(spi_dev, + slave_select, + num_frames, + NULL, + rx_buf, + ALT_SPI_TMOD_RX, + 0, 0); +} + +// +// This function performs a master SPI EEPROM read transfer. +// +ALT_STATUS_CODE alt_spi_master_eeprom_transfer(ALT_SPI_DEV_t *spi_dev, + const uint32_t slave_select, + const uint8_t opcode, + const uint16_t eeprom_addr, + const size_t num_frames, + uint16_t * rx_buf) +{ + return alt_spi_master_transfer(spi_dev, + slave_select, + num_frames, + NULL, + rx_buf, + ALT_SPI_TMOD_EEPROM, + opcode, + eeprom_addr); +} + +// +// Write or read bulk of data form slave mode +// +static ALT_STATUS_CODE alt_spi_slave_transfer_helper(ALT_SPI_DEV_t *spi_dev, + size_t data_send, + size_t data_recv, + const uint16_t * tx_buf, + uint16_t * rx_buf) +{ + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + const uint16_t * buffer_tx = tx_buf; + uint16_t * buffer_rx = rx_buf; + uint32_t timeout = MAX(data_send, data_recv) * 10000; + + while (data_send > 0 || data_recv > 0) + { + // Error handling + ALT_STATUS_CODE err_status = 0; + status = alt_spi_transmit_error_handler(spi_dev, &err_status); + + if (status != ALT_E_SUCCESS) + { + break; + } + + if (err_status != ALT_E_SUCCESS) + { + status = err_status; + break; + } + + // Read out the resulting received data as they come in. + + if (data_recv > 0) + { + uint32_t level = 0; + status = alt_spi_rx_fifo_level_get(spi_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + if (level == 0) + { + if (--timeout == 0) + { + status = ALT_E_TMO; + break; + } + } + + level = MIN(data_recv, level); + + for (uint32_t i = 0; i < level; ++i) + { + *buffer_rx = (ALT_SPIS_DR_DR_GET(alt_read_word(ALT_SPIS_DR_ADDR(spi_dev->location)))); + ++buffer_rx; + } + + data_recv -= level; + } + + // Top up the TX FIFO with sending data + + if (data_send > 0) + { + uint32_t level = 0; + status = alt_spi_tx_fifo_level_get(spi_dev, &level); + if (status != ALT_E_SUCCESS) + { + break; + } + + uint32_t space = ALT_SPI_TX_FIFO_NUM_ENTRIES - level; + + space = MIN(data_send, space); + + for (uint32_t i = 0; i < space; ++i) + { + alt_write_word(ALT_SPIS_DR_ADDR(spi_dev->location), ALT_SPIS_DR_DR_SET(*buffer_tx)); + ++buffer_tx; + } + + data_send -= space; + } + + } + + return status; +} +// +// This function performs a slave SPI/SSP serial slave transfer. +// +static ALT_STATUS_CODE alt_spi_slave_transfer(ALT_SPI_DEV_t *spi_dev, + const uint16_t * tx_buf, + uint16_t * rx_buf, + const size_t buf_len, + ALT_SPI_TMOD_t transfer_mode) +{ + if (alt_spi_checking(spi_dev) == ALT_E_FALSE) + { + return ALT_E_BAD_ARG; + } + + if (spi_dev->op_mode == ALT_SPI_OP_MODE_MASTER) + { + return ALT_E_ERROR; + } + + if (buf_len == 0) + { + return ALT_E_SUCCESS; + } + + if (alt_spi_is_enabled(spi_dev) == ALT_E_FALSE) + { + return ALT_E_ERROR; + } + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // Clear interrupt status and disable interrupt mask + alt_spi_int_clear( spi_dev,ALT_SPI_STATUS_ALL); + alt_spi_int_disable(spi_dev,ALT_SPI_STATUS_ALL); + // Enable abort and TXFIFO empty interrupt status + alt_spi_int_enable( spi_dev,ALT_SPI_STATUS_RXOI | + ALT_SPI_STATUS_RXUI | + ALT_SPI_STATUS_TXOI); + + // This SPI controller requires that a read issue be performed for each byte requested. + // Read issue takes space in the TX FIFO, which may asynchronously handling a previous request. + + uint32_t data_send = 0; + uint32_t data_recv = 0; + + if (transfer_mode == ALT_SPI_TMOD_TX || transfer_mode == ALT_SPI_TMOD_TXRX) + { + data_send = buf_len; + } + + if (transfer_mode == ALT_SPI_TMOD_RX || transfer_mode == ALT_SPI_TMOD_TXRX) + { + data_recv = buf_len; + } + + // Write or read bulk of data + status = alt_spi_slave_transfer_helper(spi_dev, + data_send, + data_recv, + tx_buf, + rx_buf); + + // Need reset for set spi bus in idle state + if(status == ALT_E_TMO) + alt_spi_reset(spi_dev); + + // Mask all interrupts + alt_spi_int_disable(spi_dev, ALT_SPI_STATUS_ALL); + + return status; + +} + +// +// This function performs a slave SPI/SSP serial transmit and receive transfer. +// +ALT_STATUS_CODE alt_spi_slave_tx_rx_transfer(ALT_SPI_DEV_t *spi_dev, + const uint16_t * tx_buf, + uint16_t * rx_buf, + const size_t buf_len) +{ + return alt_spi_slave_transfer(spi_dev, + tx_buf, + rx_buf, + buf_len, + ALT_SPI_TMOD_TXRX); +} + +// +// This function performs a slave SPI/SSP serial transmit only transfer. +// +ALT_STATUS_CODE alt_spi_slave_tx_transfer(ALT_SPI_DEV_t *spi_dev, + const uint16_t * tx_buf, + const size_t buf_len) +{ + alt_spi_int_disable(spi_dev, ALT_SPI_STATUS_RXFI); + return alt_spi_slave_transfer(spi_dev, + tx_buf, + NULL, + buf_len, + ALT_SPI_TMOD_TXRX); +} + +// +// This function performs a slave SPI/SSP serial receive only transfer. +// +ALT_STATUS_CODE alt_spi_slave_rx_transfer(ALT_SPI_DEV_t *spi_dev, + uint16_t * rx_buf, + const size_t buf_len) +{ + alt_spi_int_disable(spi_dev, ALT_SPI_STATUS_TXEI); + return alt_spi_slave_transfer(spi_dev, + NULL, + rx_buf, + buf_len, + ALT_SPI_TMOD_TXRX); +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_system_manager.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_system_manager.c new file mode 100644 index 000000000..5d2c32691 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_system_manager.c @@ -0,0 +1,265 @@ + +/****************************************************************************** +* +* alt_system_manager.c - API for the Altera SoC FPGA system manager +* +******************************************************************************/ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "alt_system_manager.h" +#include "socal/alt_sysmgr.h" +#include "socal/socal.h" +#include "socal/hps.h" + +///// + + +ALT_STATUS_CODE alt_fpga_interface_enable(ALT_FPGA_INTERFACE_t intfc) +{ + switch (intfc) + { + case ALT_FPGA_INTERFACE_GLOBAL: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_GBL_ADDR, + ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK); + + case ALT_FPGA_INTERFACE_RESET_REQ: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_JTAG_ENABLE: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_CONFIG_IO: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_BSCAN: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_TRACE: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_DBG_APB: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + 1 << 5); + + case ALT_FPGA_INTERFACE_STM: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_CTI: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_EMAC0: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK); + + case ALT_FPGA_INTERFACE_EMAC1: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK); + + case ALT_FPGA_INTERFACE_SPIM0: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + 1 << 0); + + case ALT_FPGA_INTERFACE_SPIM1: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + 1 << 1); + + case ALT_FPGA_INTERFACE_NAND: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + 1 << 4); + + case ALT_FPGA_INTERFACE_SDMMC: + return alt_setbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + 1 << 5); + + default: + return ALT_E_BAD_ARG; + } +} + +ALT_STATUS_CODE alt_fpga_interface_disable(ALT_FPGA_INTERFACE_t intfc) +{ + switch (intfc) + { + case ALT_FPGA_INTERFACE_GLOBAL: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_GBL_ADDR, + ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK); + + case ALT_FPGA_INTERFACE_RESET_REQ: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_JTAG_ENABLE: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_CONFIG_IO: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_BSCAN: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_TRACE: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_DBG_APB: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + 1 << 5); + + case ALT_FPGA_INTERFACE_STM: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_CTI: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR, + ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK); + + case ALT_FPGA_INTERFACE_EMAC0: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK); + + case ALT_FPGA_INTERFACE_EMAC1: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK); + + case ALT_FPGA_INTERFACE_SPIM0: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + 1 << 0); + + case ALT_FPGA_INTERFACE_SPIM1: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + 1 << 1); + + case ALT_FPGA_INTERFACE_NAND: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + 1 << 4); + + case ALT_FPGA_INTERFACE_SDMMC: + return alt_clrbits_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR, + 1 << 5); + + default: + return ALT_E_BAD_ARG; + } +} + +ALT_STATUS_CODE alt_fpga_interface_is_enabled(ALT_FPGA_INTERFACE_t intfc) +{ + switch (intfc) + { + case ALT_FPGA_INTERFACE_GLOBAL: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_GBL_ADDR) & + ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_RESET_REQ: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) & + ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_JTAG_ENABLE: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) & + ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_CONFIG_IO: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) & + ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_BSCAN: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) & + ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_TRACE: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) & + ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_DBG_APB: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) & + (1 << 5)) != 0) ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_STM: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) & + ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_CTI: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) & + ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_EMAC0: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) & + ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_EMAC1: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) & + ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_SPIM0: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) & + (1 << 0)) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_SPIM1: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) & + (1 << 1)) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_NAND: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) & + (1 << 4)) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + case ALT_FPGA_INTERFACE_SDMMC: + return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) & + (1 << 5)) != 0) + ? ALT_E_TRUE : ALT_E_FALSE; + + default: + return ALT_E_BAD_ARG; + } +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_timers.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_timers.c new file mode 100644 index 000000000..75fb5acfb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_timers.c @@ -0,0 +1,1340 @@ + +/****************************************************************************** +* +* alt_timers.c - API for the Altera SoC general purpose timers. +* +******************************************************************************/ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/****************************************************************************** +* +* The SoC FPGA has nine general purpose timers. Seven timers are available +* to each CPU. +* +* There are four types of timers available: +* - Four general-purpose countdown timers available to CPU0, CPU1, or the FPGA +* - Each CPU has a private GP countdown timer available only to itself +* - Each CPU has a watchdog timer that can work in GP timer countdown mode +* - One continuous-countup global timer with compare capabilities available to +* both CPUs and to the FPGA +* +* Each type has a somewhat different HW interface. This API presents the same +* external interface for each. +* +******************************************************************************/ + + +#include +#include +#include "socal/hps.h" +#include "socal/socal.h" +#include "socal/alt_tmr.h" +#include "socal/alt_rstmgr.h" +#include "hwlib.h" +#include "alt_mpu_registers.h" +#include "alt_timers.h" +#include "alt_clock_manager.h" // for getting clock bus frequency +#include "alt_watchdog.h" +#include "alt_globaltmr.h" + + +extern bool cpu_wdog_in_gpt_mode(void); +extern bool alt_globaltmr_is_running(void); +#define alt_globaltmr_remain_get64() (alt_globaltmr_comp_get64() - alt_globaltmr_get64()) + + +/****************************************************************************************/ +/* alt_gpt_all_tmr_uninit() uninitializes the general-purpose timer modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_all_tmr_uninit(void) +{ + // put the L4 general-purpose timer modules into system manager reset + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, + ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK | ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK + | ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK | ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK); + + // put the local ARM private timer into reset manually + alt_clrbits_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET, + CPU_PRIV_TMR_ENABLE | CPU_PRIV_TMR_INT_EN); + // reset load and counter registers + alt_write_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_LOAD_REG_OFFSET, 0); + // clear any pending interrupts + alt_write_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_INT_STATUS_REG_OFFSET, CPU_PRIV_TMR_INT_STATUS); + // now write zeros to the control register significant bitfields + alt_clrbits_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET, + (CPU_PRIV_TMR_ENABLE | CPU_PRIV_TMR_AUTO_RELOAD | CPU_PRIV_TMR_INT_EN + | CPU_PRIV_TMR_PS_MASK)); + + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpt_all_tmr_init() initializes the general-purpose timer modules */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_all_tmr_init(void) +{ + // put general-purpose timer modules into system manager reset if not already there + alt_gpt_all_tmr_uninit(); + // release general-purpose timer modules from system reset (w/ two-instruction delay) + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, + ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK | ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK + | ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK | ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK); + + // nothing to do for the local ARM private timer + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* alt_gpt_tmr_stop() stops the countdown or countup of the specified timer. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_tmr_stop(ALT_GPT_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // Return value + uint32_t regmask; // data mask + volatile uint32_t *regaddr; // register address + + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_stop(); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU, if it is in gpt mode + { + if (cpu_wdog_in_gpt_mode()) // Is local watchdog timer in general-purpose timer mode? + { + ret = alt_wdog_stop(ALT_WDOG_CPU); + } + } + else + { + if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + regaddr = (volatile uint32_t *) (CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET); + regmask = ~CPU_PRIV_TMR_ENABLE; + } + else if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK; + } + else { return ALT_E_BAD_ARG; } // none of the above + + alt_write_word(regaddr, alt_read_word(regaddr) & regmask); + ret = ALT_E_SUCCESS; + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_tmr_start() starts the countdown or countup of the specified timer. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_tmr_start(ALT_GPT_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // Return value + uint32_t regmask; // data mask + volatile uint32_t *regaddr; // register address + + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_start(); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU, if it is in gpt mode + { + if (cpu_wdog_in_gpt_mode()) // Is local watchdog timer in general-purpose timer mode? + { + ret = alt_wdog_start(ALT_WDOG_CPU); + } + } + else + { + if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + regaddr = (volatile uint32_t *) (CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET); + regmask = CPU_PRIV_TMR_ENABLE; + } + else if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK; + } + else { return ALT_E_BAD_ARG; } // none of the above + + alt_write_word(regaddr, alt_read_word(regaddr) | regmask); + ret = ALT_E_SUCCESS; + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_tmr_is_running() checks and returns the status of the specified timer, */ +/* i.e. whether running or not. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_tmr_is_running(ALT_GPT_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // Return value + uint32_t regdata; // temp value to read + uint32_t regmask; // data mask + volatile uint32_t *regaddr; // register address + + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = (alt_globaltmr_is_comp_mode() && alt_globaltmr_is_running()) + ? ALT_E_TRUE : ALT_E_FALSE; + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU + { + ret = (alt_wdog_tmr_is_enabled(ALT_WDOG_CPU)) ? ALT_E_TRUE : ALT_E_FALSE; + } + else + { + if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + regaddr = (volatile uint32_t *) (CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET); + regmask = CPU_PRIV_TMR_ENABLE; + } + else if (tmr_id == ALT_GPT_OSC1_TMR0) //Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) //Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK; + } + else if (tmr_id == ALT_GPT_SP_TMR0) //Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK; + } + else if (tmr_id == ALT_GPT_SP_TMR1) //Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1CTLREG_ADDR; + regmask = ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK; + } + else { return ALT_E_BAD_ARG; } // none of the above + + regdata = alt_read_word(regaddr); + ret = (regdata & regmask) ? ALT_E_TRUE : ALT_E_FALSE; + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_tmr_reset() just stops and restarts the specified timer, causing it to */ +/* reset and start its count over again. */ + /****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_tmr_reset(ALT_GPT_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_SUCCESS; + + if (alt_gpt_tmr_is_running(tmr_id)) { ret = alt_gpt_tmr_stop(tmr_id); } + // stop the timer + if (ret == ALT_E_SUCCESS) { ret = alt_gpt_tmr_start(tmr_id); } + // restart timer again from the beginning + if (ret == ALT_E_SUCCESS) { ret = alt_gpt_int_clear_pending(tmr_id); } + // clear out any pending interrupts for this timer + + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_counter_set() sets the value of the specified timer. If the timer is */ +/* currently running, it is stopped first. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_counter_set(ALT_GPT_TIMER_t tmr_id, uint32_t val) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // Return value + volatile uint32_t *regaddr; // register address + + + if (alt_gpt_tmr_is_running(tmr_id)) + { + alt_gpt_tmr_stop(tmr_id); // If timer is currently running, stop it + } + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_autoinc_set(val); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU, if it is in gpt mode + { + ret = alt_wdog_counter_set(ALT_WDOG_CPU, (ALT_WDOG_TIMEOUT_t) val); + } + else + { + if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + regaddr = (volatile uint32_t *) (CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_LOAD_REG_OFFSET); + } + else if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1LDCOUNT_ADDR; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1LDCOUNT_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1LDCOUNT_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1LDCOUNT_ADDR; + } + else { return ALT_E_BAD_ARG; } // none of the above + + alt_write_word(regaddr, val); + ret = ALT_E_SUCCESS; + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_counter_get() returns the current value of the specified timer, whether */ +/* running or not. Note that the global timer counts up and for the global timer, this */ +/* function does NOT return a value that indicates how long until the next interrupt. */ +/****************************************************************************************/ + + uint32_t alt_gpt_counter_get(ALT_GPT_TIMER_t tmr_id) +{ + uint32_t ret = 0; // value to return + volatile uint32_t *regaddr; // register address + + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_counter_get_low32(); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU + { + ret = alt_wdog_counter_get_current(ALT_WDOG_CPU); + } + else + { + if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + regaddr = (volatile uint32_t *) (CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CNTR_REG_OFFSET); + } + else if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1CURVAL_ADDR; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1CURVAL_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1CURVAL_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1CURVAL_ADDR; + } + else { return 0; } // none of the above + + ret = alt_read_word(regaddr); + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_curtime_get_kernl() is the basis of the next four functions. */ +/****************************************************************************************/ + +static uint32_t alt_gpt_curtime_get_kernl(ALT_GPT_TIMER_t tmr_id, uint32_t mult) +{ + uint64_t bigtime; // r2 & r3 + uint32_t time = 0; // value to return + ALT_CLK_t clk = ALT_CLK_UNKNOWN; + uint32_t pres, freq; + volatile uint32_t *regaddr; // register address + + + + pres = alt_gpt_prescaler_get(tmr_id); + if (pres <= UINT8_MAX) + { + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + bigtime = alt_globaltmr_remain_get64(); + clk = ALT_CLK_MPU_PERIPH; + } + else + { + if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU + { + time = alt_wdog_counter_get_current(ALT_WDOG_CPU); + clk = ALT_CLK_MPU_PERIPH; + } + else + { + if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + regaddr = (volatile uint32_t *) (CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CNTR_REG_OFFSET); + clk = ALT_CLK_MPU_PERIPH; + } + else if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1CURVAL_ADDR; + clk = ALT_CLK_OSC1; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1CURVAL_ADDR; + clk = ALT_CLK_OSC1; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1CURVAL_ADDR; + clk = ALT_CLK_L4_SP; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1CURVAL_ADDR; + clk = ALT_CLK_L4_SP; + } + else { return 0; } // none of the above + + time = alt_read_word(regaddr); + } + bigtime = (uint64_t) time; + } + + if (alt_clk_freq_get(clk, &freq) == ALT_E_SUCCESS) + { + bigtime *= (pres + 1); + // ARM can usually do a 32x64 bit multiply faster than a 64x64 bit multiply + bigtime *= mult; + bigtime /= freq; + // remaining count divided by cycles-per-second becomes seconds, + // milliseconds, microseconds, or nanoseconds remaining + time = (bigtime > UINT32_MAX) ? 0xFFFFFFFF : (uint32_t) bigtime; + } + } + return time; +} + + +/****************************************************************************************/ +/* alt_gpt_curtime_get() returns the current time until the specified timer counts */ +/* down to zero, measured in seconds. */ +/****************************************************************************************/ + +uint32_t alt_gpt_curtime_get(ALT_GPT_TIMER_t tmr_id) +{ + return alt_gpt_curtime_get_kernl(tmr_id, 1); +} + + +/****************************************************************************************/ +/* alt_gpt_curtime_get() returns the current time until the specified timer counts */ +/* down to zero, measured in milliseconds. */ +/****************************************************************************************/ + +uint32_t alt_gpt_curtime_millisecs_get(ALT_GPT_TIMER_t tmr_id) +{ + return alt_gpt_curtime_get_kernl(tmr_id, ALT_MILLISECS_IN_A_SEC); +} + + +/****************************************************************************************/ +/* alt_gpt_curtime_get() returns the current time until the specified timer counts */ +/* down to zero, measured in microseconds. */ +/****************************************************************************************/ + +uint32_t alt_gpt_curtime_microsecs_get(ALT_GPT_TIMER_t tmr_id) +{ + return alt_gpt_curtime_get_kernl(tmr_id, ALT_MICROSECS_IN_A_SEC); +} + + +/****************************************************************************************/ +/* alt_gpt_curtime_get() returns the current time until the specified timer counts */ +/* down to zero, measured in microseconds. */ +/****************************************************************************************/ + +uint32_t alt_gpt_curtime_nanosecs_get(ALT_GPT_TIMER_t tmr_id) +{ + return alt_gpt_curtime_get_kernl(tmr_id, ALT_NANOSECS_IN_A_SEC); +} + + +/****************************************************************************************/ +/* alt_gpt_counter_get() returns the value that the specified timer would reset to, */ +/* independent of the current value of the counter. */ +/****************************************************************************************/ + + uint32_t alt_gpt_reset_value_get(ALT_GPT_TIMER_t tmr_id) +{ + uint32_t ret = 0; // Return value + volatile uint32_t *regaddr; // register address + + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_autoinc_get(); // The equivalent of the reset value + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU + { + ret = alt_wdog_counter_get_init(ALT_WDOG_CPU); + } + else + { + if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + regaddr = (volatile uint32_t *) (CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_LOAD_REG_OFFSET); + } + else if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1LDCOUNT_ADDR; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1LDCOUNT_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1LDCOUNT_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1LDCOUNT_ADDR; + } + else { return ret;} // none of the above + + ret = alt_read_word(regaddr); + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_maxcounter_get() returns the maximum possible value that the specified timer */ +/* could be set to reset or restart to. */ +/****************************************************************************************/ + +uint32_t alt_gpt_maxcounter_get(ALT_GPT_TIMER_t tmr_id) +{ + uint32_t ret = 0; // Return value + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = GLOBALTMR_MAX; + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU, if it is in gpt mode + { + ret = alt_wdog_counter_get_max(ALT_WDOG_CPU); + } + else if ((tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + || (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + || (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + || (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + || (tmr_id == ALT_GPT_SP_TMR1)) // Timer 1 on the SP bus + { + ret = CPU_PRIV_TMR_MAX; + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_prescaler_set() sets the value of the prescaler field of the specified */ +/* timer, which is one less than the actual counter value. Valid input = 0-255 and any */ +/* larger value causes an error. It also throws an error if the timer is currently */ +/* running. */ +/****************************************************************************************/ + + ALT_STATUS_CODE alt_gpt_prescaler_set(ALT_GPT_TIMER_t tmr_id, uint32_t val) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // value to return + uint32_t regdata; + + if ((tmr_id == ALT_GPT_CPU_GLOBAL_TMR) && (val <= GLOBALTMR_PS_MAX)) // Global Timer + { + ret = alt_globaltmr_prescaler_set(val); + } + else if ((tmr_id == ALT_GPT_CPU_WDTGPT_TMR) && (val <= WDOG_PS_MAX)) + { // Local watchdog Timer for this CPU + ret = alt_wdog_core_prescaler_set(val); + } + else if ((tmr_id == ALT_GPT_CPU_PRIVATE_TMR) && (val <= CPU_PRIV_TMR_PS_MAX)) + { // Local Private Timer for this CPU + regdata = alt_read_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET); + regdata = (regdata & ~CPU_PRIV_TMR_PS_MASK) | (val << CPU_PRIV_TMR_PS_SHIFT); + // Replace existing bitfield + alt_write_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET, + regdata); + ret = ALT_E_SUCCESS; + } + else { ret = ALT_E_BAD_ARG; } // the other timers don't have a prescaler + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_prescaler_get() returns the value of the prescaler setting of the specified */ +/* timer, which is one less than the actual scaler value. Valid output = 0-255. */ +/****************************************************************************************/ + + uint32_t alt_gpt_prescaler_get(ALT_GPT_TIMER_t tmr_id) +{ + uint32_t ret = 0; // value to return + uint32_t regdata; // value to read + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_prescaler_get(); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) + { // Local watchdog Timer for this CPU, gpt mode doesn't matter + ret = alt_wdog_core_prescaler_get(); + } + else if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + regdata = alt_read_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET); + ret = (regdata & CPU_PRIV_TMR_PS_MASK) >> CPU_PRIV_TMR_PS_SHIFT; + } + return ret; // Returns zero for the other timers +} + + + /****************************************************************************************/ +/* alt_gpt_freq_get() returns the integer portion of the frequency that the */ +/* selected timer will rollover at, measured in Hertz. */ +/****************************************************************************************/ + +uint32_t alt_gpt_freq_get(ALT_GPT_TIMER_t tmr_id) +{ + uint32_t freq = 0; // return value + uint64_t divd, bigfreq; // math + ALT_CLK_t clk; // clock type + + + if ((tmr_id == ALT_GPT_CPU_GLOBAL_TMR) || (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) || (tmr_id == ALT_GPT_CPU_PRIVATE_TMR)) + { + clk = ALT_CLK_MPU_PERIPH; + } + /* Peripheral timers */ + else if ((tmr_id == ALT_GPT_OSC1_TMR0) || (tmr_id == ALT_GPT_OSC1_TMR1)) + { + clk = ALT_CLK_OSC1; + } + else if ((tmr_id == ALT_GPT_SP_TMR0) || (tmr_id == ALT_GPT_SP_TMR1)) + { + clk = ALT_CLK_L4_SP; + } + else { return freq; } + + if (alt_clk_freq_get(clk, &freq) == ALT_E_SUCCESS) + { + bigfreq = (uint64_t) freq; + divd = ((((uint64_t) alt_gpt_reset_value_get(tmr_id)) + 1) * + ((uint64_t) (alt_gpt_prescaler_get(tmr_id) + 1))); + // Convert the reset value to 64-bit before the addition to avoid a potential + // rollover to zero. But add one to the prescaler value before the conversion + // to 64-bit -- no potential for rollover and integer addition is faster + + bigfreq /= divd; + freq = (bigfreq > UINT32_MAX) ? 0 : (uint32_t) bigfreq; + } + else { freq = 0; } + return freq; +} + + +/****************************************************************************************/ +/* alt_gpt_time_get_kernl() is the root function of the next three functions */ +/* definitions. */ +/****************************************************************************************/ + +static uint32_t alt_gpt_time_get_kernl(ALT_GPT_TIMER_t tmr_id, uint32_t mult) +{ + uint32_t freq, time = 0; + uint64_t bigtime; + ALT_CLK_t clk; + + + if ((tmr_id == ALT_GPT_CPU_GLOBAL_TMR) || (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) || (tmr_id == ALT_GPT_CPU_PRIVATE_TMR)) + { + clk = ALT_CLK_MPU_PERIPH; + } + /* Peripheral timers */ + else if ((tmr_id == ALT_GPT_OSC1_TMR0) || (tmr_id == ALT_GPT_OSC1_TMR1)) + { + clk = ALT_CLK_OSC1; + } + else if ((tmr_id == ALT_GPT_SP_TMR0) || (tmr_id == ALT_GPT_SP_TMR1)) + { + clk = ALT_CLK_L4_SP; + } + else { return time; } + + if (alt_clk_freq_get(clk, &freq) == ALT_E_SUCCESS) + { + bigtime = ((((uint64_t) alt_gpt_reset_value_get(tmr_id)) + 1) * + ((uint64_t) (alt_gpt_prescaler_get(tmr_id) + 1))); + // Convert the reset value to 64-bit before the addition to avoid a potential + // rollover to zero. But add one to the prescaler value before the conversion + // to 64-bit -- no potential for rollover and integer addition is faster + + bigtime *= (uint64_t) mult; + bigtime /= (uint64_t) freq; + time = (bigtime > UINT32_MAX) ? 0xFFFFFFFF : (uint32_t) bigtime; + } + return time; +} + + +/****************************************************************************************/ +/* alt_gpt_time_get() returns the currently-selected timeout period of the selected */ +/* timer, measured in seconds. */ +/****************************************************************************************/ + +uint32_t alt_gpt_time_get(ALT_GPT_TIMER_t tmr_id) +{ + return alt_gpt_time_get_kernl(tmr_id, 1); +} + +/****************************************************************************************/ +/* alt_gpt_time_get() returns the currently-selected timeout period of the selected */ +/* timer, measured in milliseconds. */ +/****************************************************************************************/ + +uint32_t alt_gpt_time_millisecs_get(ALT_GPT_TIMER_t tmr_id) +{ + return alt_gpt_time_get_kernl(tmr_id, ALT_MILLISECS_IN_A_SEC); +} + + +/****************************************************************************************/ +/* alt_gpt_time_get() returns the currently-selected timeout period of the selected */ +/* timer, measured in microseconds. */ +/****************************************************************************************/ + +uint32_t alt_gpt_time_microsecs_get(ALT_GPT_TIMER_t tmr_id) +{ + return alt_gpt_time_get_kernl(tmr_id, ALT_MICROSECS_IN_A_SEC); +} + + +/****************************************************************************************/ +/* alt_gpt_maxtime_get_kernl() is the basis for the next two functions */ +/****************************************************************************************/ + +static uint32_t alt_gpt_maxtime_get_kernl(ALT_GPT_TIMER_t tmr_id, uint32_t mult) +{ + uint32_t time = 0; + uint32_t freq; + uint64_t bigtime; + ALT_CLK_t clk; + + + if ((tmr_id == ALT_GPT_CPU_GLOBAL_TMR) || (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) || (tmr_id == ALT_GPT_CPU_PRIVATE_TMR)) + { + clk = ALT_CLK_MPU_PERIPH; + } + /* Peripheral timers */ + else if ((tmr_id == ALT_GPT_OSC1_TMR0) || (tmr_id == ALT_GPT_OSC1_TMR1)) + { + clk = ALT_CLK_OSC1; + } + else if ((tmr_id == ALT_GPT_SP_TMR0) || (tmr_id == ALT_GPT_SP_TMR1)) + { + clk = ALT_CLK_L4_SP; + } + else { return time; } + + if (alt_clk_freq_get(clk, &freq) == ALT_E_SUCCESS) + { + bigtime = (((uint64_t) alt_gpt_maxcounter_get(tmr_id)) + 1) + * ((uint64_t) (alt_gpt_prescaler_get(tmr_id) + 1)); + bigtime *= (uint64_t) mult; //scale the output + bigtime /= (uint64_t) freq; + time = (bigtime > UINT32_MAX) ? 0xFFFFFFFF : (uint32_t) bigtime; + } + return time; +} + + +/****************************************************************************************/ +/* alt_gpt_maxtime_get() returns the maximum available timeout period of the selected */ +/* timer, measured in seconds. */ +/****************************************************************************************/ + +uint32_t alt_gpt_maxtime_get(ALT_GPT_TIMER_t tmr_id) +{ + return alt_gpt_maxtime_get_kernl(tmr_id, 1); +} + + +/****************************************************************************************/ +/* alt_gpt_maxtime_millisecs_get() returns the maximum available timeout period of the */ +/* selected timer, measured in milliseconds. */ +/****************************************************************************************/ + +uint32_t alt_gpt_maxtime_millisecs_get(ALT_GPT_TIMER_t tmr_id) +{ + return alt_gpt_maxtime_get_kernl(tmr_id, ALT_MILLISECS_IN_A_SEC); +} + + +/****************************************************************************************/ +/* alt_gpt_int_disable() disables the interrupt of the specified timer. It returns a */ +/* status code showing the result of the operation. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_int_disable(ALT_GPT_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // Return value + volatile uint32_t *regaddr; // register address + + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_int_disable(); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU, if it is in gpt mode + { + ret = alt_wdog_int_disable(ALT_WDOG_CPU); + } + else if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + alt_write_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET, + alt_read_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET) & ~CPU_PRIV_TMR_INT_EN); + ret = ALT_E_SUCCESS; + } + else + { + if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1CTLREG_ADDR; + + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1CTLREG_ADDR; + } + else { return ALT_E_BAD_ARG; } // none of the above + + alt_write_word(regaddr, alt_read_word(regaddr) | ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET_MSK); + ret = ALT_E_SUCCESS; + } + alt_gpt_int_clear_pending(tmr_id); // Clear any pending ints + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_int_enable() enables the interrupt of the specified timer. It returns a */ +/* status code showing the result of the operation. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_int_enable(ALT_GPT_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // Return value + volatile uint32_t *regaddr; // register address + + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_int_enable(); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU + { + if (cpu_wdog_in_gpt_mode()) // Is watchdog in general-purpose timer mode? + { + ret = alt_wdog_int_enable(ALT_WDOG_CPU); + } + } + else if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + alt_write_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET, + alt_read_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET) | CPU_PRIV_TMR_INT_EN); + ret = ALT_E_SUCCESS; + } + else + { + if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1CTLREG_ADDR; + } + else { return ALT_E_BAD_ARG; } // none of the above + + alt_write_word(regaddr, alt_read_word(regaddr) & ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_CLR_MSK); + ret = ALT_E_SUCCESS; + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_int_is_enabled() returns whether or not the interrupt of the specified */ +/* timer is enabled or not. */ +/****************************************************************************************/ + +bool alt_gpt_int_is_enabled(ALT_GPT_TIMER_t tmr_id) +{ + bool ret = false; // Return value + volatile uint32_t *regaddr; // register address + + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_int_is_enabled(); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU + { + if (cpu_wdog_in_gpt_mode()) // Is watchdog timer in gpt mode? + { + ret = alt_wdog_int_is_enabled(ALT_WDOG_CPU); + } + } + if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + ret = alt_read_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET) & CPU_PRIV_TMR_INT_EN; + } + else + { + if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1CTLREG_ADDR; + } + else { return ret; } // none of the above + + ret = (alt_read_word(regaddr) & ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET_MSK) ? false : true; + // this is inverted from the private timer above + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_int_clear_pending() clears the interrupt of the specified timer. */ +/****************************************************************************************/ + + +ALT_STATUS_CODE alt_gpt_int_clear_pending(ALT_GPT_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // Return status + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_int_clear_pending(); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU, if it is in gpt mode + { + if (cpu_wdog_in_gpt_mode()) // Is local watchdog timer in general-purpose timer mode? + { + ret = alt_wdog_int_clear(ALT_WDOG_CPU); + } + } + else + { + if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + alt_write_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_INT_STATUS_REG_OFFSET, CPU_PRIV_TMR_INT_STATUS); + // Clear interrupt status bit by writing 0x00000001 to register + } + else if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + (void) alt_read_word(ALT_OSC1TMR0_TMRSEOI_ADDR); + // Clear Osc1 Timer 0 interrupts by reading the timers EOI register + // adding the void cast tells armcc not to throw a error for this usage + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + (void) alt_read_word(ALT_OSC1TMR1_TMRSEOI_ADDR); + // Clear Osc1 Timer 1 interrupts by reading the timers EOI register + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + (void) alt_read_word(ALT_SPTMR0_TMRSEOI_ADDR); + // Clear SP Timer 0 interrupts by reading the timers EOI register + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + (void) alt_read_word(ALT_SPTMR1_TMRSEOI_ADDR); + // Clear SP Timer 1 interrupts by reading the timers EOI register + } + else { return ALT_E_BAD_ARG; } // none of the above + + ret = ALT_E_SUCCESS; + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_int_is_pending() returns whether or not the interrupt of the specified */ +/* timer is pending or not. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_int_is_pending(ALT_GPT_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_ERROR; // Return status + uint32_t regmask; // data mask + volatile uint32_t *regaddr; // register address + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_int_is_pending(); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU + { + if (cpu_wdog_in_gpt_mode()) + { + ret = alt_wdog_int_is_pending(ALT_WDOG_CPU); + } + } + else + { + if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + regaddr = (uint32_t *) (CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_INT_STATUS_REG_OFFSET); + regmask = CPU_PRIV_TMR_INT_STATUS; + } + else if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (uint32_t *) ALT_OSC1TMR0_TMR1INTSTAT_ADDR; + regmask = ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (uint32_t *) ALT_OSC1TMR1_TMR1INTSTAT_ADDR; + regmask = ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (uint32_t *) ALT_SPTMR0_TMR1INTSTAT_ADDR; + regmask = ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (uint32_t *) ALT_SPTMR1_TMR1INTSTAT_ADDR; + regmask = ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK; + } + else { return ALT_E_BAD_ARG; } // none of the above + + ret = (alt_read_word(regaddr) & regmask) ? ALT_E_TRUE : ALT_E_FALSE; + + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_int_if_pending_clear() clears the interrupt of the specified timer and also */ +/* returns whether it was pending before being cleared or not. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_int_if_pending_clear(ALT_GPT_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_FALSE; // Return status + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_int_if_pending_clear(); + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU + { + if (cpu_wdog_in_gpt_mode()) + { + ret = alt_wdog_int_if_pending_clear(ALT_WDOG_CPU); + } + else { ret = ALT_E_ERROR; } + } + else if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + if (alt_read_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_INT_STATUS_REG_OFFSET) & CPU_PRIV_TMR_INT_STATUS) // Faster to avoid the read if possible + { + alt_write_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_INT_STATUS_REG_OFFSET, CPU_PRIV_TMR_INT_STATUS); + // Clear interrupt status bit by writing 0x00000001 to register + ret = ALT_E_TRUE; + } + } + else + { + if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + if (alt_read_word(ALT_OSC1TMR0_TMR1INTSTAT_ADDR) & ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK) + { + (void) alt_read_word(ALT_OSC1TMR0_TMR1EOI_ADDR); + // Clear Osc1 Timer 0 interrupts by reading the timer1 EOI register + // adding the void cast tells armcc not to throw a error for this usage + ret = ALT_E_TRUE; + } + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + if (alt_read_word(ALT_OSC1TMR1_TMR1INTSTAT_ADDR) & ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK) + { + (void) alt_read_word(ALT_OSC1TMR1_TMR1EOI_ADDR); + // Clear Osc1 Timer 1 interrupts by reading the timer1 EOI register + ret = ALT_E_TRUE; + } + + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + if (alt_read_word(ALT_SPTMR0_TMR1INTSTAT_ADDR) & ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK) + { + (void) alt_read_word(ALT_SPTMR0_TMR1EOI_ADDR); + // Clear SP Timer 0 interrupts by reading the timer1 EOI register + ret = ALT_E_TRUE; + } + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + if (alt_read_word(ALT_SPTMR1_TMR1INTSTAT_ADDR) & ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK) + { + (void) alt_read_word(ALT_SPTMR1_TMR1EOI_ADDR); + // Clear SP Timer 1 interrupts by reading the timer1 EOI register + ret = ALT_E_TRUE; + } + } + else { ret = ALT_E_BAD_ARG; } // none of the above + } + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_mode_set() sets the reset mode (rollover or oneshot) of the specified timer. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_gpt_mode_set(ALT_GPT_TIMER_t tmr_id, ALT_GPT_RESTART_MODE_t mode) +{ + int32_t ret = ALT_E_ERROR; // Return value + uint32_t regdata; // value to read + volatile uint32_t *regaddr; // register address + + + if ((mode == ALT_GPT_RESTART_MODE_ONESHOT) || (mode == ALT_GPT_RESTART_MODE_PERIODIC)) + { + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + if (mode == ALT_GPT_RESTART_MODE_PERIODIC) + { + ret = alt_globaltmr_autoinc_mode_start(); + } + else + { + ret = alt_globaltmr_autoinc_mode_stop(); + } + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU + { + ret = alt_wdog_response_mode_set(ALT_WDOG_CPU, + (mode == ALT_GPT_RESTART_MODE_ONESHOT) ? ALT_WDOG_TIMER_MODE_ONESHOT : ALT_WDOG_TIMER_MODE_FREERUN); + } + else if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + regdata = alt_read_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET); + regdata = (mode == ALT_GPT_RESTART_MODE_PERIODIC) ? + regdata | CPU_PRIV_TMR_AUTO_RELOAD : regdata & ~CPU_PRIV_TMR_AUTO_RELOAD; + alt_write_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET, regdata); + ret = ALT_E_SUCCESS; + } + else + { + if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1CTLREG_ADDR; + } + else { return ALT_E_BAD_ARG; } // none of the above + + regdata = alt_read_word(regaddr); + regdata = (mode == ALT_GPT_RESTART_MODE_ONESHOT) ? + regdata & ALT_TMR_TMR1CTLREG_TMR1_MOD_CLR_MSK : + regdata | ALT_TMR_TMR1CTLREG_TMR1_MOD_SET_MSK; + // Peripheral timers are opposite polarity as the private timer + alt_write_word(regaddr, regdata); + ret = ALT_E_SUCCESS; + } + } + else { ret = ALT_E_BAD_ARG; } + + return ret; +} + + +/****************************************************************************************/ +/* alt_gpt_mode_get() returns the mode setting of the specified timer. */ +/****************************************************************************************/ + +int32_t alt_gpt_mode_get(ALT_GPT_TIMER_t tmr_id) +{ + int32_t ret = ALT_E_BAD_ARG; // Return value + volatile uint32_t *regaddr; // register address + + + if (tmr_id == ALT_GPT_CPU_GLOBAL_TMR) // Global Timer + { + ret = alt_globaltmr_is_autoinc_mode() ? ALT_GPT_RESTART_MODE_PERIODIC : ALT_GPT_RESTART_MODE_ONESHOT; + + } + else if (tmr_id == ALT_GPT_CPU_WDTGPT_TMR) // Local watchdog Timer for this CPU + { + ret = alt_wdog_response_mode_get(ALT_WDOG_CPU); + + ret = (ret == ALT_WDOG_TIMER_MODE_ONESHOT) ? ALT_GPT_RESTART_MODE_ONESHOT : + (ret == ALT_WDOG_TIMER_MODE_FREERUN) ? ALT_GPT_RESTART_MODE_PERIODIC : ALT_E_ERROR; + // enumeration conversion + } + else if (tmr_id == ALT_GPT_CPU_PRIVATE_TMR) // Local Private Timer for this CPU + { + ret = (alt_read_word(CPU_PRIVATE_TMR_BASE + CPU_PRIV_TMR_CTRL_REG_OFFSET) & CPU_PRIV_TMR_AUTO_RELOAD) + ? ALT_GPT_RESTART_MODE_PERIODIC : ALT_GPT_RESTART_MODE_ONESHOT; + } + else + { + if (tmr_id == ALT_GPT_OSC1_TMR0) // Timer 0 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR0_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_OSC1_TMR1) // Timer 1 on the OSC1 bus + { + regaddr = (volatile uint32_t *) ALT_OSC1TMR1_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR0) // Timer 0 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR0_TMR1CTLREG_ADDR; + } + else if (tmr_id == ALT_GPT_SP_TMR1) // Timer 1 on the SP bus + { + regaddr = (volatile uint32_t *) ALT_SPTMR1_TMR1CTLREG_ADDR; + } + else { return ret; } // none of the above + + ret = (alt_read_word(regaddr) & ALT_TMR_TMR1CTLREG_TMR1_MOD_SET_MSK) + ? ALT_GPT_RESTART_MODE_PERIODIC : ALT_GPT_RESTART_MODE_ONESHOT; + } + return ret; +} + + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_watchdog.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_watchdog.c new file mode 100644 index 000000000..10c600709 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/alt_watchdog.c @@ -0,0 +1,1101 @@ + +/****************************************************************************** +* +* alt_watchdog.c - API for the Altera SoC FPGA watchdog timers. +* +******************************************************************************/ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/****************************************************************************** +* +* The Altera SoC FPGA has six watchdog timers, two are local to the MPU +* themselves, and the other four are accessable to either MPU. +* +******************************************************************************/ + +#include +#include +#include "socal/hps.h" +#include "socal/socal.h" +#include "socal/alt_rstmgr.h" +#include "socal/alt_l4wd.h" +#include "socal/alt_tmr.h" +#include "hwlib.h" +#include "alt_mpu_registers.h" +#include "alt_watchdog.h" +#include "alt_clock_manager.h" + + + /* Useful constants and utilities */ + +bool cpu_wdog_in_gpt_mode(void) +{ + return !(alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET) & WDOG_WDT_MODE); +} + +static inline bool cpu_wdog_in_wdt_mode(void) +{ + return (alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET) & WDOG_WDT_MODE); +} + + +/* This value must be written to the Counter Restart Register of the + * peripheral watchdog timers to restart them. */ +#define WDOG_RESET_KEY 0x00000076 + +#define ALT_WDOG_RST_WIDTH 8 /* 8 or more MPU clock cycles */ + + +inline static void alt_wdog_wait(void* reg, uint32_t cnt) +{ + for (; cnt ; cnt--) + { + (void) alt_read_word(reg); + } +} + + +/****************************************************************************************/ +/* Initialize the watchdog timer module before use */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_init(void) +{ + // put watchdog timer modules into system manager reset if not already there + alt_wdog_uninit(); + // release L4 watchdog timer modules from system reset (w/ four instruction-cycle delay) + alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK | + ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK); + + // release *both* ARM watchdog timer modules from system reset (if in reset) + // does not put either one into watchdog timer mode + alt_clrbits_word(ALT_RSTMGR_MPUMODRST_ADDR, ALT_RSTMGR_MPUMODRST_WDS_SET_MSK); + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* Return the local ARM watchdog timer back to general-purpose timer mode */ +/****************************************************************************************/ + +void alt_ARM_wdog_gpt_mode_set(void) +{ + while (alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET) & WDOG_WDT_MODE) + { + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_DISABLE_REG_OFFSET, WDOG_DISABLE_VAL0); + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_DISABLE_REG_OFFSET, WDOG_DISABLE_VAL1); + } +} + + +/****************************************************************************************/ +/* Set the local ARM watchdog timer to watchdog timer mode */ +/****************************************************************************************/ + +void alt_ARM_wdog_wdog_mode_set(void) +{ + alt_setbits_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET, WDOG_WDT_MODE); +} + + +/****************************************************************************************/ +/* Uninitialize the watchdog timer module & return to reset state */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_uninit(void) +{ + // put L4 watchdog modules into system manager reset + alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, + ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK | ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK); + + // using the system manager bit to reset the ARM watchdog timer + // resets *both* ARM watchdog timers, which is often not advisable, + // so we reset the local ARM watchdog timer manually: + + // first, stop the ARM watchdog timer & disable interrupt + alt_clrbits_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET, WDOG_TMR_ENABLE | WDOG_INT_EN); + // reset load and counter registers + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_LOAD_REG_OFFSET, 0); + // clear any pending reset and interrupt status + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_RSTSTAT_REG_OFFSET, WDOG_RST_STAT_BIT); + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_INTSTAT_REG_OFFSET, WDOG_INT_STAT_BIT); + // return ARM watchdog timer to (initial) general-purpose timer mode + alt_ARM_wdog_gpt_mode_set(); + // now write zeros to the control register significant bitfields + // and then verify that all significant bitfields return zero + alt_clrbits_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET, + (WDOG_PS_MASK | WDOG_WDT_MODE | WDOG_INT_EN | WDOG_AUTO_RELOAD | WDOG_TMR_ENABLE)); + if (alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET) + & (WDOG_PS_MASK | WDOG_WDT_MODE | WDOG_INT_EN | WDOG_AUTO_RELOAD | WDOG_TMR_ENABLE)) + { + return ALT_E_ERROR; + } + return ALT_E_SUCCESS; + +} + + +/****************************************************************************************/ +/* Stops the specified watchdog timer. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_stop(ALT_WDOG_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; // return value + uint32_t config; // the current configuration + uint32_t loadreg; // current restart value + + + if (tmr_id == ALT_WDOG_CPU) + { + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET, + (alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET) & ~WDOG_TMR_ENABLE)); + ret = ALT_E_SUCCESS; + } + + // these timers can only be reset by using a system manager reset + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + config = alt_read_word(ALT_L4WD0_WDT_CR_ADDR); // read current timer mode + loadreg = alt_read_word(ALT_L4WD0_WDT_TORR_ADDR); // read timer restart values + alt_write_word(ALT_RSTMGR_PERMODRST_ADDR, + alt_read_word(ALT_RSTMGR_PERMODRST_ADDR) | ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK); + // assert reset & wait + alt_wdog_wait(ALT_RSTMGR_PERMODRST_ADDR, ALT_WDOG_RST_WIDTH); + alt_write_word(ALT_RSTMGR_PERMODRST_ADDR, + alt_read_word(ALT_RSTMGR_PERMODRST_ADDR) & ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK); + // release peripheral reset signal by clearing bit + alt_write_word(ALT_L4WD0_WDT_TORR_ADDR, loadreg); // restore timer restart value + alt_write_word(ALT_L4WD0_WDT_CR_ADDR, config & ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK); + // restore previous timer mode except timer isn't started + ret = ALT_E_SUCCESS; + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + config = alt_read_word(ALT_L4WD1_WDT_CR_ADDR); // read current timer mode + loadreg = alt_read_word(ALT_L4WD1_WDT_TORR_ADDR); // read timer restart values + alt_write_word(ALT_RSTMGR_PERMODRST_ADDR, + alt_read_word(ALT_RSTMGR_PERMODRST_ADDR) | ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK); + // assert reset & wait + alt_write_word(ALT_RSTMGR_PERMODRST_ADDR, + alt_read_word(ALT_RSTMGR_PERMODRST_ADDR) & ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK); + // release peripheral reset signal by clearing bit + alt_write_word(ALT_L4WD1_WDT_TORR_ADDR, loadreg); // restore timer restart value + alt_write_word(ALT_L4WD1_WDT_CR_ADDR, config & ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK); + // restore previous timer mode except timer isn't started + ret = ALT_E_SUCCESS; + } + return ret; +} + +/****************************************************************************************/ +/* Start the specified watchdog timer. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_start(ALT_WDOG_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; // return value + uint32_t regdata; // data + + + if (tmr_id == ALT_WDOG_CPU) + { + regdata = alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET); + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET, regdata | WDOG_TMR_ENABLE); + ret = ALT_E_SUCCESS; + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + regdata = alt_read_word(ALT_L4WD0_WDT_CR_ADDR); + alt_write_word(ALT_L4WD0_WDT_CR_ADDR, regdata | ALT_L4WD_CR_WDT_EN_SET_MSK); + ret = ALT_E_SUCCESS; + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + regdata = alt_read_word(ALT_L4WD1_WDT_CR_ADDR); + alt_write_word(ALT_L4WD1_WDT_CR_ADDR, regdata | ALT_L4WD_CR_WDT_EN_SET_MSK); + ret = ALT_E_SUCCESS; + } + return ret; +} + + +/****************************************************************************************/ +/* Returns whether the specified watchdog timer is currently running or not. */ +/****************************************************************************************/ + +bool alt_wdog_tmr_is_enabled(ALT_WDOG_TIMER_t tmr_id) +{ + bool ret = false; // return value + + + if (tmr_id == ALT_WDOG_CPU) + { + ret = alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET) & WDOG_TMR_ENABLE; + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + ret = alt_read_word(ALT_L4WD0_WDT_CR_ADDR) & ALT_L4WD_CR_WDT_EN_SET_MSK; + } + + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + ret = alt_read_word(ALT_L4WD1_WDT_CR_ADDR) & ALT_L4WD_CR_WDT_EN_SET_MSK; + } + return ret; +} + + +/****************************************************************************************/ +/* Reloads the counter countdown value and restarts the watchdog timer. User can reset */ +/* the timer at any time before timeout. Also known as kicking, petting, feeding, */ +/* waking, or walking the watchdog. Inherently clears the interrupt as well. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_reset(ALT_WDOG_TIMER_t tmr_id) +{ + uint32_t regdata; // data read + + + if (tmr_id == ALT_WDOG_CPU) + { + regdata = alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_LOAD_REG_OFFSET); + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_LOAD_REG_OFFSET, regdata); + // verify operation when we have hardware, + // the ARM documentation is somewhat vague here + + if (cpu_wdog_in_wdt_mode()) + { + alt_write_word((CPU_WDTGPT_TMR_BASE + WDOG_RSTSTAT_REG_OFFSET), WDOG_RST_STAT_BIT); + // depending on current mode, clear the reset bit or... + } + else + { + alt_write_word((CPU_WDTGPT_TMR_BASE + WDOG_INTSTAT_REG_OFFSET), WDOG_INT_STAT_BIT); + // ...clear the interrupt status bit by writing one to it + } + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + alt_write_word(ALT_L4WD0_WDT_CRR_ADDR, WDOG_RESET_KEY); + //restarts the counter, also clears the watchdog timer interrupt + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + alt_write_word(ALT_L4WD1_WDT_CRR_ADDR, WDOG_RESET_KEY); + //restarts the counter, also clears the watchdog timer interrupt + } + else {return ALT_E_BAD_ARG; } + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* Sets the countdown value of the specified timer. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_counter_set(ALT_WDOG_TIMER_t tmr_id, uint32_t val) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; // return value + uint32_t regdata; // returned data + + + if (tmr_id == ALT_WDOG_CPU) + { + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_LOAD_REG_OFFSET, val); + ret = ALT_E_SUCCESS; + // the ARM documentation is somewhat vague here, but it looks like it should be + // possible to rewrite this value while counter is running, and that it works in + // watchdog mode as well as timer mode. Verify operation when we have hardware. + } + else if (val <= ALT_WDOG_TIMEOUT2G) + { + if (tmr_id == ALT_WDOG0) + { + // set regular timeout value + regdata = alt_read_word(ALT_L4WD0_WDT_TORR_ADDR); + alt_write_word(ALT_L4WD0_WDT_TORR_ADDR, (regdata & ALT_L4WD_TORR_TOP_CLR_MSK) | val); + ret = ALT_E_SUCCESS; + } + else if (tmr_id == ALT_WDOG1) + { + // set regular timeout value + regdata = alt_read_word(ALT_L4WD1_WDT_TORR_ADDR); + alt_write_word(ALT_L4WD1_WDT_TORR_ADDR, (regdata & ALT_L4WD_TORR_TOP_CLR_MSK) | val); + ret = ALT_E_SUCCESS; + } + else if (tmr_id == ALT_WDOG0_INIT) + { + // set initial timeout value + regdata = alt_read_word(ALT_L4WD0_WDT_TORR_ADDR); + regdata = (regdata & ALT_L4WD_TORR_TOP_INIT_CLR_MSK) | + (val << ALT_L4WD_TORR_TOP_INIT_LSB); + alt_write_word(ALT_L4WD0_WDT_TORR_ADDR, regdata); + ret = ALT_E_SUCCESS; + } + else if (tmr_id == ALT_WDOG1_INIT) + { + // set initial timeout value + regdata = alt_read_word(ALT_L4WD1_WDT_TORR_ADDR); + regdata = (regdata & ALT_L4WD_TORR_TOP_INIT_CLR_MSK) | + (val << ALT_L4WD_TORR_TOP_INIT_LSB); + alt_write_word(ALT_L4WD1_WDT_TORR_ADDR, regdata); + ret = ALT_E_SUCCESS; + } + } + return ret; +} + + +/****************************************************************************************/ +/* Returns the current counter value of the specified timer. */ +/****************************************************************************************/ + +uint32_t alt_wdog_counter_get_current(ALT_WDOG_TIMER_t tmr_id) +{ + uint32_t ret = 0; // return value + + if (tmr_id == ALT_WDOG_CPU) + { + ret = alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CNTR_REG_OFFSET); + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + ret = alt_read_word(ALT_L4WD0_WDT_CCVR_ADDR); + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + ret = alt_read_word(ALT_L4WD1_WDT_CCVR_ADDR); + } + return ret; +} + + +/****************************************************************************************/ +/* Returns the current counter value of the specified timer, as measured in */ +/* milliseconds. For ALT_CPU_WATCHDOG, this includes the effects of the prescaler */ +/* setting. */ +/****************************************************************************************/ + +uint32_t alt_wdog_counter_get_curtime_millisecs(ALT_WDOG_TIMER_t tmr_id) +{ + uint32_t time = 0; // return value + uint64_t bigtime; // temp for math + alt_freq_t freq; // clock frequency + ALT_CLK_t clk; // clock ID + + if (tmr_id == ALT_WDOG_CPU) + { + clk = ALT_CLK_MPU_PERIPH; + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG1) || + (tmr_id == ALT_WDOG0_INIT) || (tmr_id == ALT_WDOG1_INIT)) + { + clk = ALT_CLK_OSC1; + } + else { return time; } + + if ((alt_clk_freq_get(clk, &freq) == ALT_E_SUCCESS) && (freq != 0)) + { // get clock frequency & test + time = alt_wdog_counter_get_current(tmr_id); // get current counter value + if (time != 0) + { + bigtime = (uint64_t) time; + // the current time period is not counted, only whole periods are counted + if (tmr_id == ALT_WDOG_CPU) + { + bigtime *= (uint64_t) (alt_wdog_core_prescaler_get() + 1); + } + bigtime *= ALT_MILLISECS_IN_A_SEC; + bigtime /= freq; // cycles-per-second becomes milliseconds-per-cycle + time = (bigtime > (uint64_t) UINT32_MAX) ? 0 : (uint32_t) bigtime; + } + } + return time; +} + + +// see the return value range calculations below at alt_wdog_counter_get_inittime_millisecs(). + +/****************************************************************************************/ +/* Returns the initial counter value of the specified timer as a 32-bit integer */ +/* value. This is the value that will be reloaded when the timer is reset or restarted. */ +/* For the timers where this value is set as an encoded powers-of-two between 15 and */ +/* 31, the value is converted into the equivalent binary value before returning it. For */ +/* ALT_CPU_WATCHDOG, the returned value does not include the effects of the prescaler */ +/* setting */ +/****************************************************************************************/ + +uint32_t alt_wdog_counter_get_init(ALT_WDOG_TIMER_t tmr_id) +{ + uint32_t ret = 0; // value to return + + if (tmr_id == ALT_WDOG_CPU) + { + ret = alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_LOAD_REG_OFFSET); + } + else if (tmr_id == ALT_WDOG0) + { + ret = ALT_L4WD_TORR_TOP_GET(alt_read_word(ALT_L4WD0_WDT_TORR_ADDR)); + ret = (ret > ALT_L4WD_TORR_TOP_E_TMO2G) ? 0 : ALT_TWO_TO_POW16 << ret; + } + else if (tmr_id == ALT_WDOG1) + { + ret = ALT_L4WD_TORR_TOP_GET(alt_read_word(ALT_L4WD1_WDT_TORR_ADDR)); + ret = (ret > ALT_L4WD_TORR_TOP_E_TMO2G) ? 0 : ALT_TWO_TO_POW16 << ret; + } + else if (tmr_id == ALT_WDOG0_INIT) + { + ret = ALT_L4WD_TORR_TOP_INIT_GET(alt_read_word(ALT_L4WD0_WDT_TORR_ADDR)); + ret = (ret > ALT_L4WD_TORR_TOP_INIT_E_TMO2G) ? 0 : ALT_TWO_TO_POW16 << ret; + } + else if (tmr_id == ALT_WDOG1_INIT) + { + ret = ALT_L4WD_TORR_TOP_INIT_GET(alt_read_word(ALT_L4WD1_WDT_TORR_ADDR)); + ret = (ret > ALT_L4WD_TORR_TOP_INIT_E_TMO2G) ? 0 : ALT_TWO_TO_POW16 << ret; + } + return ret; +} + + +/****************************************************************************************/ +/* Returns the initial value of the specified timer in nanoseconds. This is the */ +/* value that will be reloaded when the timer is reset or restarted. For */ +/* ALT_CPU_WATCHDOG, this includes the effects of the prescaler setting. This call */ +/* returns a more precise result than alt_wdog_counter_get_inittime_millisecs(), but */ +/* as an unsigned 64-bit integer. */ +/****************************************************************************************/ + +uint64_t alt_wdog_counter_get_inittime_nanosecs(ALT_WDOG_TIMER_t tmr_id) +{ + uint64_t time = 0; + alt_freq_t freq; + ALT_CLK_t clk; + + if (tmr_id == ALT_WDOG_CPU) + { + clk = ALT_CLK_MPU_PERIPH; + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG1) || + (tmr_id == ALT_WDOG0_INIT) || (tmr_id == ALT_WDOG1_INIT)) + { + clk = ALT_CLK_OSC1; + } + else { return time; } // zero always indicates an error for an init time + + if ((alt_clk_freq_get(clk, &freq) == ALT_E_SUCCESS) && (freq != 0)) + { // get clock frequency & test + time = (uint64_t) alt_wdog_counter_get_init(tmr_id); // get reset value + if (time != 0) + { + time += 1; + if (tmr_id == ALT_WDOG_CPU) + { + time *= (uint64_t) (alt_wdog_core_prescaler_get() + 1); + } + time *= ALT_NANOSECS_IN_A_SEC; + time /= freq; // cycles-per-second becomes nanoseconds per cycle + } + } + + return time; +} + + +/* For reviewers: + * minimum clock divider for ALT_CPU_WATCHDOG is 1 + * maximum clock divider for ALT_CPU_WATCHDOG is ((0xFFFF FFFF + 1) x (0x0000 0100) = 0x0000 0100 0000 0000) + * multiply that by the number of nanoseconds in a second (1,000,000,000) + * = 1,099,511,627,776,000,000,000 (0x9ACA 0000 0000 0000) + * so the countdown time with the slowest mpu_peripheral clock (2.5 MHz) = + * 400 nS to 439,804.6511104 seconds (0x0001 9000 0000 0000 nS) + * and with the fastest mpu_peripheral clock (200 MHz) = + * 5 nS to 5,497,558,138,880 nanoseconds ( 0x0000 0500 0000 0000 nS) + * + * minimum clock divider for peripheral watchdogs is 2**16 = (65,536 = 0x00010000) + * maximum clock divider for peripheral watchdogs is 2**31 = (2,147,483,648 = 0x8000 0000) + * multiply that by the number of nanoseconds in a second (1,000,000,000) = + * 4,096,000,000,000 (0x0000 03B9 ACA0 0000) to 2,147,483,648,000,000,000 (0x1DCD 6500 0000 0000) + * so the countdown time with the slowest l4_sp_clk (625 kHz) = + * 6,553,600 nS (0x0064 0000) to 3,435,973,836,800 nS (0x0000 0320 0000 0000 nS) + * and with the fastest l4_sp_clk (100 MHz) = + * 40,960 ns (0xA000) to 21,474,836,480 nS (0x0000 0005 0000 0000 nS) + */ + +/****************************************************************************************/ +/* Returns the initial value of the specified timer in milliseconds. This is the */ +/* value that will be reloaded when the timer is reset or restarted. For */ +/* ALT_CPU_WATCHDOG, this includes the effects of the prescaler setting. This call */ +/* returns a 32-bit unsigned integer, though is less precise than */ +/* alt_wdog_counter_get_inittime_nanosecs(). */ +/****************************************************************************************/ + +uint32_t alt_wdog_counter_get_inittime_millisecs(ALT_WDOG_TIMER_t tmr_id) +{ + uint32_t time = 0; + alt_freq_t freq; + ALT_CLK_t clk; + uint64_t bigtime; + + if (tmr_id == ALT_WDOG_CPU) + { + clk = ALT_CLK_MPU_PERIPH; + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG1) || + (tmr_id == ALT_WDOG0_INIT) || (tmr_id == ALT_WDOG1_INIT)) + { + clk = ALT_CLK_OSC1; + } + else { return time; } // must be an invalid tmr_id + + if ((alt_clk_freq_get(clk, &freq) == ALT_E_SUCCESS) && (freq != 0)) + { // get clock frequency & test + time = alt_wdog_counter_get_init(tmr_id); // get reset value + if (time != 0) + { + bigtime = ((uint64_t) time) + 1; + if (tmr_id == ALT_WDOG_CPU) // the only watchdog with a prescaler + { + bigtime *= (uint64_t) (alt_wdog_core_prescaler_get() + 1); + } + bigtime *= ALT_MILLISECS_IN_A_SEC; // scale value + bigtime /= freq; // cycles-per-second becomes milliseconds per cycle + time = (bigtime > (uint64_t) UINT32_MAX) ? 0 : (uint32_t) bigtime; + } + } + return time; +} + + +/* For reviewers: + * minimum clock divider for ALT_CPU_WATCHDOG is 1 + * maximum clock divider for ALT_CPU_WATCHDOG is ((0xFFFF FFFF + 1) x (0x0000 0100) = 0x0000 0100 0000 0000) + * multiply that by the number of milliseconds in a second (1,000) + * = 1,000 (0x3e8) to 1,099,511,627,776,000 (0x0003 E800 0000 0000) + * so the countdown time with the slowest mpu_peripheral clock (2.5 MHz) = + * 0 mS to 439,804.6511104 seconds (0x1A36 E2EB mS) + * and with the fastest mpu_peripheral clock (200 MHz) = + * 0 mS to 5,497.55813888 seconds ( 0x0053 E2D6 mS) + * + * minimum clock divider for peripheral watchdogs is 2**16 = (65,536 = 0x00010000) + * maximum clock divider for peripheral watchdogs is 2**31 = (2,147,483,648 = 0x8000 0000) + * multiply that by the number of milliseconds in a second (1,000) = + * 65,536,000 (0x3E8 0000) to 2,147,483,648,000 (0x01F4 0000 0000) + * so the countdown time with the slowest l4_sp_clk (625 kHz) = + * 104 mS (0x0068) to 3,435,973 mS (0x0034 6DC5 mS) + * and with the fastest l4_sp_clk (100 MHz) = 0 mS to 21,474 mS (0x0000 53E2 mS) + */ + +/****************************************************************************************/ +/* Sets the value of the CPU watchdog timer ALT_CPU_WATCHDOG prescaler. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_core_prescaler_set(uint32_t val) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; // return value + uint32_t regdata; + + if (val <= WDOG_PS_MAX) + { + if (alt_wdog_tmr_is_enabled(ALT_WDOG_CPU)) + { + ret = ALT_E_ERROR; + } + else + { + regdata = alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET); + alt_write_word((CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET), + (regdata & ~WDOG_PS_MASK) | (val << WDOG_PS_SHIFT)); + ret = ALT_E_SUCCESS; + } + } + return ret; +} + + +/****************************************************************************************/ +/* Returns the value of the prescaler of the CPU core watchdog timer. */ +/****************************************************************************************/ + +uint32_t alt_wdog_core_prescaler_get(void) +{ + return (alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET) & + WDOG_PS_MASK) >> WDOG_PS_SHIFT; +} + + +/****************************************************************************************/ +/* Returns the maximum possible counter value of the specified timer as a 32-bit value. */ +/* For the timers where this value is encoded (as powers-of-two between 15 and 31), the */ +/* encoded value is converted into the equivalent binary value before returning it. */ +/* This does not include the effects of the prescaler available for ALT_CPU_WATCHDOG. */ +/****************************************************************************************/ + +uint32_t alt_wdog_counter_get_max(ALT_WDOG_TIMER_t tmr_id) +{ + uint32_t ret = 0; // return value + + if (tmr_id == ALT_WDOG_CPU) + { + ret = WDOG_TMR_MAX; + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG1) + || (tmr_id == ALT_WDOG0_INIT) || (tmr_id == ALT_WDOG1_INIT)) + { + ret = ((uint32_t) ALT_TWO_TO_POW16) << ALT_WDOG_TIMEOUT2G; + } + + return ret; +} + + +/****************************************************************************************/ +/* Returns the maximum possible delay time of the specified timer specified in */ +/* nanoseconds. For ALT_CPU_WATCHDOG, this includes the prescaler setting. This call */ +/* returns a more precise reading of the counter than */ +/* alt_wdog_counter_get_max_millisecs(), though in an unsigned 64-bit integer. */ +/****************************************************************************************/ + +uint64_t alt_wdog_counter_get_max_nanosecs(ALT_WDOG_TIMER_t tmr_id) +{ + uint64_t time = 0; + alt_freq_t freq; + ALT_CLK_t clk; + + if (tmr_id == ALT_WDOG_CPU) + { + clk = ALT_CLK_MPU_PERIPH; + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG1) || + (tmr_id == ALT_WDOG0_INIT) || (tmr_id == ALT_WDOG1_INIT)) + { + clk = ALT_CLK_OSC1; + } + else { return time; } + + if ((alt_clk_freq_get(clk, &freq) == ALT_E_SUCCESS) && (freq != 0)) + { // get clock frequency & test + time = (uint64_t) alt_wdog_counter_get_max(tmr_id); // get maximum reset value + if (time != 0) + { + time += 1; + if (tmr_id == ALT_WDOG_CPU) + { + time *= (WDOG_PS_MAX + 1); // maximum prescaler + } + time *= ALT_NANOSECS_IN_A_SEC; + time /= freq; //cycles-per-second becomes nanoseconds-per-cycle + } + } + return time; +} + + + +/****************************************************************************************/ +/* Returns the maximum possible delay time of the specified timer specified in */ +/* milliseconds. For ALT_CPU_WATCHDOG, this includes the prescaler setting. This call */ +/* returns a 32-bit unsigned integer, though is less precise than */ +/* alt_wdog_counter_get_max_nanosecs(). */ +/****************************************************************************************/ + +uint32_t alt_wdog_counter_get_max_millisecs(ALT_WDOG_TIMER_t tmr_id) +{ + uint32_t time = 0; + alt_freq_t freq; + ALT_CLK_t clk; + uint64_t bigtime; + + if (tmr_id == ALT_WDOG_CPU) + { + clk = ALT_CLK_MPU_PERIPH; + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG1) || + (tmr_id == ALT_WDOG0_INIT) || (tmr_id == ALT_WDOG1_INIT)) + { + clk = ALT_CLK_OSC1; + } + else { return time; } + + if ((alt_clk_freq_get(clk, &freq) == ALT_E_SUCCESS) && (freq != 0)) + { // get clock frequency & test + time = alt_wdog_counter_get_max(tmr_id); // get reset value + if (time != 0) + { + bigtime = ((uint64_t) time) + 1; + if (tmr_id == ALT_WDOG_CPU) + { + bigtime *= (WDOG_PS_MAX + 1); // maximum prescaler + } + bigtime *= ALT_MILLISECS_IN_A_SEC; + bigtime /= freq; //cycles-per-second becomes milliseconds-per-cycle + time = (bigtime > (uint64_t) UINT32_MAX) ? 0 : (uint32_t) bigtime; + } + } + return time; +} + + +/****************************************************************************************/ +/* Disables the interrupt of the specified watchdog timer module. If the watchdog timer */ +/* is one of the watchdog timers that can be used in general-purpose mode, and if the */ +/* timer is in general-purpose timer mode, disable the interrupt. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_int_disable(ALT_WDOG_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; // return value + + if (tmr_id == ALT_WDOG_CPU) + { + if (cpu_wdog_in_wdt_mode()) + { + ret = ALT_E_ERROR; + } + else + { + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET, + (alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET) & ~WDOG_INT_EN)); + ret = ALT_E_SUCCESS; + } + } + // returns an error for the other four watchdog timers + // since their interrupts cannot be disabled + // (this could change in v13.1) + return ret; +} + + +/****************************************************************************************/ +/* Sets/enables the interrupt of the specified watchdog timer module. If the watchdog */ +/* timer is one of the watchdog timers that can be used in general-purpose mode, and */ +/* if the timer is in general-purpose timer mode, enable the interrupt. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_int_enable(ALT_WDOG_TIMER_t tmr_id) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; // return value + + if (tmr_id == ALT_WDOG_CPU) + { + if (cpu_wdog_in_wdt_mode()) + { + ret = ALT_E_ERROR; + } + else + { + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET, + (alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET) | WDOG_INT_EN)); + ret = ALT_E_SUCCESS; + } + } + return ret; + // other watchdog timers always have interrupt enabled if they are running +} + + +/****************************************************************************************/ +/* Returns the status of the interrupt of the specified watchdog timer module but does */ +/* not clear it. Return TRUE if the interrupt of the specified general purpose timer */ +/* module is pending and FALSE otherwise. */ +/****************************************************************************************/ + +bool alt_wdog_int_is_pending(ALT_WDOG_TIMER_t tmr_id) +{ + bool ret = false; //return value + + if ((tmr_id == ALT_WDOG_CPU) && cpu_wdog_in_gpt_mode()) + { + ret = alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_INTSTAT_REG_OFFSET) & WDOG_INT_STAT_BIT; + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + ret = alt_read_word(ALT_L4WD0_WDT_STAT_ADDR) & ALT_L4WD_STAT_WDT_STAT_SET_MSK; + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + ret = alt_read_word(ALT_L4WD1_WDT_STAT_ADDR) & ALT_L4WD_STAT_WDT_STAT_SET_MSK; + } + return ret; +} + + +/****************************************************************************************/ +/* Returns the state of the interrupt of the specified watchdog timer module. If the */ +/* watchdog timer is one of the watchdog timers that can be used in general-purpose */ +/* mode, and if the timer is in general-purpose timer mode, returns TRUE if the */ +/* interrupt of the specified general purpose timer module is enabled and FALSE if */ +/* disabled. If the timer is not in general-purpose timer mode, returns TRUE, as */ +/* watchdog interrupts are always enabled. */ +/****************************************************************************************/ + +bool alt_wdog_int_is_enabled(ALT_WDOG_TIMER_t tmr_id) +{ + bool ret = false; //return value + + if (tmr_id == ALT_WDOG_CPU) + { + ret = alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET) & + (WDOG_INT_EN | WDOG_WDT_MODE); + // if in watchdog mode OR if in general purpose timer mode + // AND the interrupt is enabled + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + ret = alt_read_word(ALT_L4WD0_WDT_CR_ADDR) & ALT_L4WD_CR_WDT_EN_SET_MSK; + // if these timers are running, their interrupt is enabled + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + ret = alt_read_word(ALT_L4WD1_WDT_CR_ADDR) & ALT_L4WD_CR_WDT_EN_SET_MSK; + // if these timers are running, their interrupt is enabled + } + return ret; +} + + +/****************************************************************************************/ +/* Clears the pending status of the interrupt of the specified watchdog timer module. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_int_clear(ALT_WDOG_TIMER_t tmr_id) +{ + + + if (tmr_id == ALT_WDOG_CPU) + { + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_INTSTAT_REG_OFFSET, WDOG_INT_STAT_BIT); + // clear int by writing to status bit + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + (void) alt_read_word(ALT_L4WD0_WDT_EOI_ADDR); + // clear int by reading from end-of-interrupt register + // adding the void cast tells armcc not to throw a error for this usage + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + (void) alt_read_word(ALT_L4WD1_WDT_EOI_ADDR); + // clear int by reading from end-of-interrupt register + } + else {return ALT_E_ERROR; } + return ALT_E_SUCCESS; +} + + +/****************************************************************************************/ +/* Returns the status of the interrupt of the specified watchdog timer module and also */ +/* clears it. Return TRUE if the interrupt of the specified general purpose timer */ +/* module is pending and FALSE otherwise. */ +/****************************************************************************************/ + +bool alt_wdog_int_if_pending_clear(ALT_WDOG_TIMER_t tmr_id) +{ + uint32_t ret = false; // value to return + + + if (tmr_id == ALT_WDOG_CPU) + { + ret = (alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_INTSTAT_REG_OFFSET) & WDOG_INT_STAT_BIT); + if (ret) + { + alt_write_word(CPU_WDTGPT_TMR_BASE + WDOG_INTSTAT_REG_OFFSET, WDOG_INT_STAT_BIT); + // clear int by writing to status bit + } + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + ret = alt_read_word(ALT_L4WD0_WDT_STAT_ADDR) & ALT_L4WD_STAT_WDT_STAT_SET_MSK; + if (ret) + { + (void) alt_read_word(ALT_L4WD0_WDT_EOI_ADDR); + // clear int by reading from end-of-interrupt register + // adding the void cast tells armcc not to throw a error for this usage + + } + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + ret = alt_read_word(ALT_L4WD1_WDT_STAT_ADDR) & ALT_L4WD_STAT_WDT_STAT_SET_MSK; + + if (ret) + { + (void) alt_read_word(ALT_L4WD1_WDT_EOI_ADDR); + // clear int by reading from end-of-interrupt register + } + } + + return ret; +} + + +/****************************************************************************************/ +/* Sets the timeout response mode of the specified watchdog timer. For ALT_WATCHDOG0, */ +/* ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, the options */ +/* are to generate a system reset or to generate an interrupt and then generate a */ +/* system reset if the interrupt is not cleared by the next time the watchdog timer */ +/* counter rolls over. For ALT_CPU_WATCHDOG, the options are to trigger an interrupt */ +/* request (with the result set in the interrupt manager) or a reset request (with the */ +/* result set in the reset manager) plus two more options available when it is used */ +/* as a general-purpose timer. */ +/****************************************************************************************/ + +ALT_STATUS_CODE alt_wdog_response_mode_set(ALT_WDOG_TIMER_t tmr_id, ALT_WDOG_RESET_TYPE_t type) +{ + ALT_STATUS_CODE ret = ALT_E_BAD_ARG; // return value + uint32_t regdata; // register data + + + if (tmr_id == ALT_WDOG_CPU) + { + regdata = alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET); + if (type == ALT_WDOG_TIMER_MODE_ONESHOT) + { + alt_write_word((CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET), regdata & ~WDOG_AUTO_RELOAD); + ret = ALT_E_SUCCESS; + } + else if (type == ALT_WDOG_TIMER_MODE_FREERUN) + { + alt_write_word((CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET), regdata | WDOG_AUTO_RELOAD); + ret = ALT_E_SUCCESS; + } + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + regdata = alt_read_word(ALT_L4WD0_WDT_CR_ADDR); + if (type == ALT_WDOG_WARM_RESET) + { + alt_write_word(ALT_L4WD0_WDT_CR_ADDR, regdata & ALT_L4WD_CR_RMOD_CLR_MSK); + ret = ALT_E_SUCCESS; + } + else if (type == ALT_WDOG_INT_THEN_RESET) + { + alt_write_word(ALT_L4WD0_WDT_CR_ADDR, regdata | ALT_L4WD_CR_RMOD_SET_MSK); + ret = ALT_E_SUCCESS; + } + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + regdata = alt_read_word(ALT_L4WD1_WDT_CR_ADDR); + if (type == ALT_WDOG_WARM_RESET) + { + alt_write_word(ALT_L4WD1_WDT_CR_ADDR, regdata & ALT_L4WD_CR_RMOD_CLR_MSK); + ret = ALT_E_SUCCESS; + } + else if (type == ALT_WDOG_INT_THEN_RESET) + { + alt_write_word(ALT_L4WD1_WDT_CR_ADDR, regdata | ALT_L4WD_CR_RMOD_SET_MSK); + ret = ALT_E_SUCCESS; + } + } + return ret; // rejects a bad tmr_id argument/type argument combination +} + + +/****************************************************************************************/ +/* Returns the response mode of the specified timer. */ +/****************************************************************************************/ + +int32_t alt_wdog_response_mode_get(ALT_WDOG_TIMER_t tmr_id) +{ + int32_t ret = ALT_E_BAD_ARG; // return value + uint32_t regdata; // read value + + + if (tmr_id == ALT_WDOG_CPU) + { + regdata = alt_read_word(CPU_WDTGPT_TMR_BASE + WDOG_CTRL_REG_OFFSET); + ret = (regdata & WDOG_AUTO_RELOAD) ? ALT_WDOG_TIMER_MODE_FREERUN : ALT_WDOG_TIMER_MODE_ONESHOT; + } + else if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + regdata = alt_read_word(ALT_L4WD0_WDT_CR_ADDR); + ret = (regdata & ALT_L4WD_CR_RMOD_SET_MSK) ? ALT_WDOG_INT_THEN_RESET : ALT_WDOG_WARM_RESET; + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + regdata = alt_read_word(ALT_L4WD1_WDT_CR_ADDR); + ret = (regdata & ALT_L4WD_CR_RMOD_SET_MSK) ? ALT_WDOG_INT_THEN_RESET : ALT_WDOG_WARM_RESET; + } + + return ret; +} + + + +/****************************************************************************************/ +/* Returns the component code of the watchdog timer module. Only valid for */ +/* ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL or ALT_WATCHDOG1_INITIAL. */ +/****************************************************************************************/ + +uint32_t alt_wdog_compcode_get(ALT_WDOG_TIMER_t tmr_id) +{ + uint32_t component = 0; // component code of the module + + if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + component = alt_read_word(ALT_L4WD0_WDT_COMP_TYPE_ADDR); + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + component = alt_read_word(ALT_L4WD1_WDT_COMP_TYPE_ADDR); + + } + return component; +} + + +/****************************************************************************************/ +/* Returns the version code of the watchdog timer module. Only valid for ALT_WATCHDOG0, */ +/* ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL or ALT_WATCHDOG1_INITIAL. */ +/****************************************************************************************/ + +uint32_t alt_wdog_ver_get(ALT_WDOG_TIMER_t tmr_id) +{ + uint32_t ver = 0; // revision code of the module + + if ((tmr_id == ALT_WDOG0) || (tmr_id == ALT_WDOG0_INIT)) + { + ver = alt_read_word(ALT_L4WD0_WDT_COMP_VER_ADDR); + } + else if ((tmr_id == ALT_WDOG1) || (tmr_id == ALT_WDOG1_INIT)) + { + ver = alt_read_word(ALT_L4WD1_WDT_COMP_VER_ADDR); + + } + return ver; +} + + +/****************************************************************************************/ + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_16550_uart.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_16550_uart.h new file mode 100644 index 000000000..64bb27b0f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_16550_uart.h @@ -0,0 +1,1555 @@ +/* + * Altera - SoC UART Manager + */ + +/***************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ALT_16550_UART_H__ +#define __ALT_16550_UART_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup UART UART Driver API + * + * This module defines the Universal Asynchronous Receiver/Transmitter (UART) + * API for accessing and using the UART resources. The API allows for general + * control of a 16550 compatible UART controller. + * + * This implementation can control the following UARTs: + * * SoCFPGA On-board UARTs + * * Altera 16550 Compatible Soft IP UART + * + * The following reference materials were used in the design of this API: + * * Synopsys® DesignWare DW_apb_uart Databook v3.10a + * + * @{ + */ + +/*! + * \addtogroup UART_BASIC UART Basic + * + * This group of APIs provides basic access to the UART to initialize, + * uninitialize, read, write, and reset the UART. + * + * @{ + */ + +/*! + * This type definition enumerates the list of UARTs available on the system. + */ +typedef enum ALT_16550_DEVICE_e +{ + /*! + * This option selects UART0 in the SoC FPGA. + */ + ALT_16550_DEVICE_SOCFPGA_UART0 = 0, + + /*! + * This option selects UART1 in the SoC FPGA. + */ + ALT_16550_DEVICE_SOCFPGA_UART1 = 1, + + /*! + * This option selects an Altera 16550 Compatible soft IP UART. The memory + * location of the device must be provided as part of the initialization. + */ + ALT_16550_DEVICE_ALTERA_16550_UART = 0x100 +} +ALT_16550_DEVICE_t; + +/*! + * This structure is used to represent a handle to a specific UART on the + * system. The internal members are undocumented and should be not altered + * outside of this API. + */ +typedef struct ALT_16550_HANDLE_s +{ + ALT_16550_DEVICE_t device; + void * location; + alt_freq_t clock_freq; + uint32_t data; + uint32_t fcr; +} +ALT_16550_HANDLE_t; + +/*! + * Performs the initialization steps needed by the UART. This should be the + * first API call made when accessing a particular UART + * + * The default UART setting is 8 databits, no parity, 1 stopbit, and 57600 + * baud. + * + * For the SoCFPGA UARTs, The ALT_CLK_L4_SP clock needs to be setup before + * initialization. + * + * \param device + * The UART device identifier. + * + * \param location + * The memory of the location for the given UART. For SoCFPGA + * UARTs, this parameter is ignored. + * + * \param clock_freq + * The clock frequency of the serial clock for the given UART. + * For SoCFPGA UARTs, this paramter is ignored. + * + * \param handle + * [out] A pointer to a handle that will represent the UART. This + * handle should subsequently be used when calling other UART + * APIs. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device identifier is invalid. + * \retval ALT_E_BAD_CLK The required clock is not yet setup. + */ +ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device, + void * location, + alt_freq_t clock_freq, + ALT_16550_HANDLE_t * handle); + +/*! + * Performs the uninitialization steps for the UART. This should be the last + * API call made to cleanup the UART. + * + * After calling this function, the handle will need to be initialized again + * before being used by calling alt_16550_init(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle); + +/*! + * Resets the UART to the default configuration. The UART will be reset and + * reinitialized. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle); + +/*! + * Starts the UART after all configuration has been completed. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Stops the UART. While UART configuration can be done while enabled, it is + * not recommended. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads a single character from the UART receiver buffer. This API should + * only be used when FIFOs are disabled. + * + * \param handle + * The UART device handle. + * + * \param item + * [out] Pointer to an output parameter that contains the in + * receiver buffer of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle, + char * item); + +/*! + * Writes a single character to the UART transmitter buffer. This API should + * only be used when FIFOs are disabled. + * + * \param handle + * The UART device handle. + * + * \param item + * The character to write to the transmitter buffer of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle, + char item); + +/*! + * @} + */ + +/*! + * \addtogroup UART_FIFO UART FIFO Interface + * + * This group of APIs provides access, configuration, and control of the UART + * FIFO. The FIFO allows the UART to buffer received data and data to be + * transmitted. + * + * @{ + */ + +/*! + * This type definition enumerates the receiver FIFO level conditions that + * will trigger the receiver FIFO to issue a receiver FIFO full event. + */ +typedef enum ALT_16550_FIFO_TRIGGER_RX_e +{ + /*! + * 1 or more character(s) in the receiver FIFO will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_RX_ANY = 0, + + /*! + * 25% or higher capacity usage in the receiver FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL = 1, + + /*! + * 50% or higher capacity usage in the receiver FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_HALF_FULL = 2, + + /*! + * 2 characters less than the receiver FIFO capacity will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL = 3 +} +ALT_16550_FIFO_TRIGGER_RX_t; + +/*! + * This type definition enumerates the transmitter FIFO level conditions that + * will trigger the transmitter FIFO to issue a transmitter FIFO empty event. + */ +typedef enum ALT_16550_FIFO_TRIGGER_TX_e +{ + /*! + * Transmitter FIFO being completely empty will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_TX_EMPTY = 0, + + /*! + * 2 or less character(s) in the transmitter FIFO will trigger an event. + */ + ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY = 1, + + /*! + * 25% or less capacity usage in the transmitter FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL = 2, + + /*! + * 50% or less capacity usage in the transmitter FIFO will trigger an + * event. + */ + ALT_16550_FIFO_TRIGGER_TX_HALF_FULL = 3 +} +ALT_16550_FIFO_TRIGGER_TX_t; + +/*! + * Enables FIFO on the UART. This will enable both the receiver FIFO and + * transmitter FIFO. Both FIFOs will be cleared. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Disables FIFOs on the UART. This will disable both the receiver FIFO and + * transmitter FIFO. Any data left in the FIFOs will be lost. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the given buffer from the receiver FIFO in the UART. + * + * The available characters in the FIFO can be determined by a few ways. Users + * can determine the number of items by calling alt_16550_fifo_level_get_rx(). + * + * Another way is by using the RX trigger and RX interrupt. First determine the + * RX FIFO size by calling alt_16550_fifo_size_get_rx(). Then set the desired + * trigger level by calling alt_16550_fifo_trigger_set_rx(). Calculate the + * triggering point by applying trigger description on the FIFO size. Enable RX + * interrupts by calling alt_16550_int_enable_rx(). When the RX interrupt fires + * due to the ALT_16550_INT_STATUS_RX_DATA condition, the calculated triggering + * point value can be used to determine the RX FIFO level. If the interrupt + * fires due to the ALT_16550_INT_STATUS_RX_TIMEOUT, the RX FIFO can be + * completely emptied by repeatedly polling the Line Status + * ALT_16550_LINE_STATUS_DR condition by calling alt_16550_line_status_get(). + * These steps are necessary if the UART does not implement FIFO level query + * functionality. As of 13.0sp1, this applies to the Altera 16550 Compatible + * Soft UART. + * + * Reading more data than that which is available can result in invalid data + * appearing like valid data. + * + * The FIFO must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param buffer + * [out] Pointer to a buffer where the specified count of + * characters from the receiver FIFO will be copied to. + * + * \param count + * The count of characters from the receiver FIFO to be copied. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle, + char * buffer, + size_t count); + +/*! + * Writes the given buffer to the transmitter FIFO in the UART. + * + * The available space in the FIFO can be determined by a few ways. Users can + * determine the number of items by calculating the FIFO capacity minus the + * FIFO level. This can be done by calling alt_16550_fifo_size_get_tx() and + * alt_16550_fifo_level_get_tx() respectively. + * + * Another way is by using the TX trigger and TX interrupt. First determine the + * TX FIFO size by calling alt_16550_fifo_size_get_tx(). The set the desired + * trigger level by calling alt_16550_fifo_trigger_set_tx(). Calculate the + * triggering point by applying the trigger description on the FIFO size. + * Enable TX interrupts by calling alt_16550_int_enable_tx(). When the TX + * interrupt fires, calculate the empty entries in the FIFO by subtracting the + * TX FIFO size and the calculated value. These steps are necessary if the UART + * does not implement FIFO level query functionality. As of 13.0sp1, this + * applies to the Altera 16550 Compatible Soft UART. + * + * Writing more data that there is space can result in data lost due to + * overflowing. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param buffer + * Pointer to a buffer from where the specified count of + * characters will be copied to the transmitter FIFO. + * + * \param count + * The count of characters from the given buffer to be copied. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle, + const char * buffer, + size_t count); + +/*! + * Clears the contents of the receiver FIFO. Any characters which were + * previously contained in that FIFO will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Clears the contents of the transmitter FIFO. Any characters which were + * previously contained in that FIFO will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Clears the contents of the receiver and transmitter FIFO. Any characters + * which were previously contained on those FIFOs will be discarded. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle); + +/*! + * Queries the size of the receiver FIFO. + * + * \param handle + * The UART device handle. + * + * \param size + * [out] Pointer to an output parameter that contains the size of + * the receiver FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * size); + +/*! + * Queries the size of the transmitter FIFO. + * + * \param handle + * The UART device handle. + * + * \param size + * [out] Pointer to an output parameter that contains the size of + * the transmitter FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * size); + +/*! + * Queries the current level of the receiver FIFO. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * For the Altera 16550 Compatible UART, it may not be possible to read the + * FIFO level and this function may always report 0. For more information on + * interacting with the FIFO in this situation, see documentation for + * alt_16550_fifo_read(). + * + * \param handle + * The UART device handle. + * + * \param level + * [out] Pointer to an output parameter that contains the level + * or number of characters in the receiver FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle, + uint32_t * level); + +/*! + * Queries the current level of the transmitter FIFO. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * For the Altera 16550 Compatible UART, it may not be possible to read the + * FIFO level and this function may always report 0. For more information on + * interacting with the FIFO in this situation, see documentation for + * alt_16550_fifo_write(). + * + * \param handle + * The UART device handle. + * + * \param level + * [out] Pointer to an output parameter that contains the level + * or number of characters in the transmitter FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle, + uint32_t * level); + +/*! + * Sets the receiver FIFO level which will trigger the receiver FIFO to issue + * receiver FIFO full event. For the list of available receiver FIFO trigger + * levels, see the documentation for ALT_16550_FIFO_TRIGGER_RX_t. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param trigger + * The level of the receiver FIFO which is needed to trigger a + * receiver FIFO full event. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_RX_t trigger); + +/*! + * Sets the transmitter FIFO level which will trigger the transmitter FIFO to + * transmitter FIFO empty event. For the list of available transmitter FIFO + * trigger levels, see the documentation for ALT_16550_FIFO_TRIGGER_TX_t. + * + * The FIFOs must first be enabled before calling this function by calling + * alt_16550_fifo_enable(). + * + * \param handle + * The UART device handle. + * + * \param trigger + * The level of the transmitter FIFO which is needed to trigger a + * transmitter FIFO empty event. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle, + ALT_16550_FIFO_TRIGGER_TX_t trigger); + +/*! + * @} + */ + +/*! + * \addtogroup UART_BAUD UART Baudrate Interface + * + * This group of APIs allows for the configuration of the UART's baudrate + * generation related functions. + * + * The UART baudrate is determined by dividing the ALT_CLK_L4_SP clock with + * the configured divisor. + * + * @{ + */ + +/*! + * This enumeration lists out the common baudrates used with modem and serial + * ports. Not every baudrate is available for the UART due to the limits of + * the serial clock frequency and divisor value. + */ +typedef enum ALT_16550_BAUDRATE_e +{ + ALT_16550_BAUDRATE_50 = 50, /*!< 50 bps baudrate. */ + ALT_16550_BAUDRATE_75 = 75, /*!< 75 bps baudrate. */ + ALT_16550_BAUDRATE_150 = 150, /*!< 150 bps baudrate. */ + ALT_16550_BAUDRATE_300 = 300, /*!< 300 bps baudrate. */ + ALT_16550_BAUDRATE_600 = 600, /*!< 600 bps baudrate. */ + ALT_16550_BAUDRATE_900 = 900, /*!< 900 bps baudrate. */ + ALT_16550_BAUDRATE_1200 = 1200, /*!< 1200 bps baudrate. */ + ALT_16550_BAUDRATE_1800 = 1800, /*!< 1800 bps baudrate. */ + ALT_16550_BAUDRATE_2400 = 2400, /*!< 2400 bps baudrate. */ + ALT_16550_BAUDRATE_3600 = 3600, /*!< 3600 bps baudrate. */ + ALT_16550_BAUDRATE_4800 = 4800, /*!< 4800 bps baudrate. */ + ALT_16550_BAUDRATE_7200 = 7200, /*!< 7200 bps baudrate. */ + ALT_16550_BAUDRATE_9600 = 9600, /*!< 9600 bps baudrate. */ + ALT_16550_BAUDRATE_14400 = 14400, /*!< 14400 bps baudrate. */ + ALT_16550_BAUDRATE_19200 = 19200, /*!< 19200 bps baudrate. */ + ALT_16550_BAUDRATE_28800 = 28800, /*!< 28800 bps baudrate. */ + ALT_16550_BAUDRATE_38400 = 38400, /*!< 38400 bps baudrate. */ + ALT_16550_BAUDRATE_57600 = 57600, /*!< 57600 bps baudrate. */ + ALT_16550_BAUDRATE_115200 = 115200 /*!< 115200 bps baudrate. */ +} +ALT_16550_BAUDRATE_t; + +/*! + * Gets the baudrate for the UART. + * + * This is done by calculating the baudrate from the divisor and the serial + * clock. The reported baudrate may not correspond exactly to the request + * baudrate. + * + * \param handle + * The UART device handle. + * + * \param baudrate + * [out] Pointer to an output paramter that contains the current + * baudrate of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle, + uint32_t * baudrate); + +/*! + * Sets the baudrate for the UART. This change will take effect when the UART + * moves from disabled to enabled. + * + * This is done by calculating the correct divisor using the request baudrate + * and the known serial clock. + * + * \param handle + * The UART device handle. + * + * \param baudrate + * The requested baudrate for the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + * \retval ALT_E_ARG_RANGE The given baudrate is not possible due to + * limitations of the baudrate divisor and/or + * serial clock. + */ +ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle, + uint32_t baudrate); + +/*! + * Gets the baudrate divisor for the UART. + * + * The baudrate is determined by the following formula: + * * Baudrate = (serial clock frequency) / (16 * divisor) + * + * \param handle + * The UART device handle. + * + * \param divisor + * [out] Pointer to an output parameter that contains the current + * divisor used for baudrate generation. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle, + uint32_t * divisor); + +/*! + * Sets the baudrate divisor for the UART. This change will take effect when + * the UART moves from disabled to enabled. + * + * The baudrate is determined by the following formula: + * * Baudrate = (serial clock frequency) / (16 * divisor) + * + * \param handle + * The UART device handle. + * + * \param divisor + * The specified divisor value to use for baudrate generation. + * Valid values are 1 - 65535. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART identifier is invalid or the + * specified divisor is not supported by the + * UART. + */ +ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle, + uint32_t divisor); + +/*! + * @} + */ + +/*! + * \addtogroup UART_INT UART Interrupt Interface + * + * This group of APIs provides access, configuration, and control of the + * UART interrupts. + * + * @{ + */ + +/*! + * This type definition enumerates the different interrupt conditions that can + * be generated by the UART controller. + * + * Interrupts are listed in highest to lowest priority order. + */ +typedef enum ALT_16550_INT_STATUS_e +{ + /*! + * This interrupt signals that a overrun, parity, or framing error + * occurred, or a break event occured. The interrupt is cleared by reading + * the line status by calling alt_16550_line_status_get() or by disabling + * line status interrupts by calling alt_16550_int_disable_line(). + */ + ALT_16550_INT_STATUS_LINE = 0x6, + + /*! + * This interrupt signals that some data is available to be read from the + * UART. The definition of some depends on whether FIFOs are enabled or + * not. + * + * If FIFOs are disabled, this interrupt signals that the receiver + * contains data. In this case, the interrupt is cleared by reading the + * data from the UART by calling alt_16550_read(). + * + * If FIFOs are enabled, this interrupt signals that the receiver FIFO + * level is above the receiver trigger level specified. In this case, the + * interrupt is cleared by reading a sufficiently large buffer from the + * receiver FIFO such that the FIFO is filled below the receiver trigger + * level specified by calling alt_16550_fifo_read() or by adjusting the + * receiver trigger level appropriately by calling + * alt_16550_fifo_trigger_set_rx(). + * + * In either case, this interrupt can also be cleared by disabling + * receiver interrupts by calling alt_16550_int_disable_rx(). + */ + ALT_16550_INT_STATUS_RX_DATA = 0x4, + + /*! + * This interrupt signals that data is available in the receiver FIFO and + * that there has been no activity with the receiver FIFO for the last 4 + * character frames. In essence, the receiver FIFO has temporarily settled + * thus it may be a good time to empty the receiver FIFO. This interrupt + * is only available if FIFOs are enabled. The interrupt is cleared by + * reading from the receiver FIFO by calling alt_16550_fifo_read() or by + * disabling receiver interrupts by calling alt_16550_int_disable_rx(). + */ + ALT_16550_INT_STATUS_RX_TIMEOUT = 0xC, + + /*! + * This interrupt signals that the transmitter is idling. The definition + * of idling depends on whether FIFOs are enabled or not. + * + * If FIFOs are disabled, this interrupt signals that the transmitter + * shift register is empty. In this case, the interrupt is cleared by + * writing data to the UART by calling alt_16550_write(). + * + * If FIFO are enabled, this interrupt signals that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * the interrupt is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * In either case, this interrupt can also be cleared by disabling + * transmitter interrupts by calling alt_16550_int_disable_tx(). + */ + ALT_16550_INT_STATUS_TX_IDLE = 0x2, + + /*! + * Modem status interrupt pending. The interrupt is cleared by reading the + * modem status by calling alt_16550_modem_status_get() or by disabling + * modem status interrupts by calling alt_16550_int_disable_modem(). + */ + ALT_16550_INT_STATUS_MODEM = 0x0, + + /*! + * No interrupts pending. + */ + ALT_16550_INT_STATUS_NONE = 0x1 +} +ALT_16550_INT_STATUS_t; + +/*! + * Enables the receiver FIFO to generate interrupts. Enabling this interrupt + * allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_RX_DATA + * * ALT_16550_INT_STATUS_RX_TIMEOUT + * + * This interrupt is disabled by default. + * + * The FIFOs must also be enabled for this interrupt to actually be generated. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the receiver FIFO from generating interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the transmitter FIFO to generate interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_TX_IDLE + * + * This interrupt is disabled by default. + * + * The FIFOs must also be enabled for this interrupt to actually be generated. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the transmitter FIFO from generating interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the receiver to generate line status interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_LINE + * + * This interrupt is disabled by default. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the receiver from generating line status interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle); + +/*! + * Enables the UART to generate modem status interrupts. Enabling this + * interrupt allows for the following interrupt signal(s): + * * ALT_16550_INT_STATUS_MODEM + * + * This interrupt is disabled by default. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle); + +/*! + * Disables the UART from generate modem status interrupts. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle); + +/*! + * Disables all interrupts on the UART. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle); + +/*! + * Queries the interrupt status of the UART. This returns the highest priority + * interrupt pending. The appropriate interrupts must be enabled for them be + * generated in the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * interrupt status of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_int_status_get(ALT_16550_HANDLE_t * handle, + ALT_16550_INT_STATUS_t * status); + +/*! + * @} + */ + +/*! + * \addtogroup UART_MODEM UART Modem Interface + * + * This group of APIs provides access, configuration, and control of the UART + * Modem interface. + * + * @{ + */ + +/*! + * This type definition enumerates the set of UART modem status conditions as + * register mask values. + */ +typedef enum ALT_16550_MODEM_STATUS_e +{ + /*! + * Data Carrier Detect. This status indicates that the carrier has been + * detected by the modem. It corresponds to an inverted dcd_n input. DCD + * is unasserted when dcd_n is logic 1 and asserted when dcd_n is logic 0. + */ + ALT_16550_MODEM_STATUS_DCD = 1 << 7, + + /*! + * Ring Indicator. This status indicates that the telephone ringing signal + * has been redeived by the modem. It corresponds to an inverted ri_n + * input. RI is unasserted when ri_n is logic 1 and asserted when ri_n is + * logic 0. + */ + ALT_16550_MODEM_STATUS_RI = 1 << 6, + + /*! + * Data Set Ready. This status indicates that the modem is ready to + * establish communications with the UART. It corresponds to an inverted + * dsr_n input. DSR is unasserted when dsr_n is logic 1 and asserted when + * dsr_n is logic 0. + */ + ALT_16550_MODEM_STATUS_DSR = 1 << 5, + + /*! + * Clear To Send. This status indicates the current state of the modem + * cts_n line. It corresponds to an inverted cts_n input. CTS is + * unasserted when cts_n is logic 1 and asserted when cts_n is logic 0. + */ + ALT_16550_MODEM_STATUS_CTS = 1 << 4, + + /*! + * Delta Data Carrier Detect. This status condition indicates that the + * Data Carrier Detect has changed since the last time the modem status + * was read. Reading the modem status clears this status. For more + * information about the Data Carrier Detect status, see + * ALT_16550_MODEM_STATUS_DCD. + */ + ALT_16550_MODEM_STATUS_DDCD = 1 << 3, + + /*! + * Trailing Edge of Ring Indicator. This status indicates that the Ring + * Indicator has changed from asserted to unasserted. Reading the modem + * status will clear this status. For more information about the Ring + * Indicator status, reference ALT_16550_MODEM_STATUS_RI. + */ + ALT_16550_MODEM_STATUS_TERI = 1 << 2, + + /*! + * Delta Data Set Ready. This status condition indicates that the Data Set + * Ready has changed since the last time the modem status was read. + * Reading the modem status will clear this status. For more information + * about the Data Set Ready status, see ALT_16550_MODEM_STATUS_DSR. + */ + ALT_16550_MODEM_STATUS_DDSR = 1 << 1, + + /*! + * Delta Clear To Send. This status condition indicates that the Clear To + * Send has changed since the last time the modem status was read. Reading + * the modem status will clear this status. For more information about the + * Clear To Send status, see ALT_16550_MODEM_STATUS_CTS. + */ + ALT_16550_MODEM_STATUS_DCTS = 1 << 0 +} +ALT_16550_MODEM_STATUS_t; + +/*! + * Enables automatic flow control in the UART modem. When in this mode, the + * rts_n is gated with the threshold trigger condition of the receiver FIFO. + * + * The Altera 16550 Compatible Soft IP UART may not have this option enabled. + * + * The FIFOs must be enabled for flow control to be used. + * + * The recommended bring up for flow control is as follows: + * * Enable automatic flow control by calling alt_16550_flowcontrol_enable(). + * This will allow both the receiver FIFO and user RTS to control the rts_n + * output. Because the user RTS is not enabled, the rts_n will be inactive + * high. + * * Enable RTS by calling alt_16550_modem_enable_rts(). This will give the + * receiver FIFO to have full control of the rts_n output. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Disables automatic flow control in the UART modem. + * + * The recommended bring down for flow control is as follows: + * * Disable RTS by calling alt_16550_modem_disable_rts(). This will disable + * generation of the rts_n ouput. + * * Disable automatic flow control by calling + * alt_16550_flowcontrol_disable(). + * + * The receiver FIFO will still be active after these steps. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Puts the UART in loopback mode. This is used for diagnostic and test + * purposes. + * + * The SoCFPGA UARTs does not support automatic flow control when in loopback + * mode. + * + * The Altera 16550 Compatible Soft IP UART implements this in 13.0sp1 and + * later. Setting this has no effect with 13.0. + * + * When in this mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are + * disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) + * are held inactive high externally and internally looped back to the inputs. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Takes the UART out of loopback mode. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the OUT1 output. OUT1 is inverted then driven out to out1_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle); + +/*! + * Unasserts the OUT1 output. OUT1 is inverted then driven out to out1_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the OUT2 output. OUT2 is inverted then driven out to out2_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle); + +/*! + * Unasserts the OUT2 output. OUT2 is inverted then driven out to out2_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the RTS (Request To Send) output. RTS is inverted then driven out + * to rts_n. RTS is used to inform the modem that the UART is ready to receive + * data. + * + * There are special considerations when the UART is in automatic flow control + * mode. See alt_16550_flowcontrol_enable() for more information. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle); + +/*! + * Deaserts the RTS (Request To Send) output. RTS is inverted then driven out + * to rts_n. + * + * There are special considerations when the UART is in automatic flow control + * mode. See alt_16550_flowcontrol_enable() for more information. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle); + +/*! + * Asserts the DTR (Data Terminal Ready) output. DTR is inverted then driven + * out to dtr_n. DTR is used to inform the modem that UART is ready to + * establish communications. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle); + +/*! + * Deasserts the DTR (Data Terminal Ready) output. DTR is inverted then driven + * out to dtr_n. + * + * There are special considerations when the UART is in loopback mode. See + * alt_16550_loopback_enable() for more information. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the modem status from the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * modem status of the UART as a register mask. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status); + +/*! + * @} + */ + +/*! + * \addtogroup UART_LINE UART Line Interface + * + * This group of APIs provides access, configuration, and control of the UART + * Line interface. + * + * @{ + */ + +/*! + * This type definition enumerates the supported databits per frame. + */ +typedef enum ALT_16550_DATABITS_e +{ + /*! + * This option selects 5 databits per frame. + */ + ALT_16550_DATABITS_5 = 0, + + /*! + * This option selects 6 databits per frame. + */ + ALT_16550_DATABITS_6 = 1, + + /*! + * This option selects 7 databits per frame. + */ + ALT_16550_DATABITS_7 = 2, + + /*! + * This option selects 8 databits per frame. + */ + ALT_16550_DATABITS_8 = 3 +} +ALT_16550_DATABITS_t; + +/*! + * This type definition enumerates the supported stopbits per frame. + */ +typedef enum ALT_16550_STOPBITS_e +{ + /*! + * This options specifies 1 stopbit per frame. + */ + ALT_16550_STOPBITS_1 = 0, + + /*! + * This options specifies 2 stopbits per frame. If the frame is + * configured with 5 databits, 1.5 stopbits is used instead. + */ + ALT_16550_STOPBITS_2 = 1 +} +ALT_16550_STOPBITS_t; + +/*! + * This type definition enumerates the possible parity to use per frame. + */ +typedef enum ALT_16550_PARITY_e +{ + /*! + * This option disables the parity error detection bit in the data frame. + */ + ALT_16550_PARITY_DISABLE = 0, + + /*! + * This option enables the odd parity error detection bit in the data + * frame. + */ + ALT_16550_PARITY_ODD = 1, + + /*! + * This option enables the even parity error detection bit in the data + * frame. + */ + ALT_16550_PARITY_EVEN = 2 +} +ALT_16550_PARITY_t; + +/*! + * This type definition enumerates the set of UART line status conditions as + * register mask values. + */ +typedef enum ALT_16550_LINE_STATUS_e +{ + /*! + * Receiver FIFO Error. This status indicates that one or more parity + * error, framing error, or break indication exists in the receiver FIFO. + * It is only set when FIFO is enabled. This status cleared when line + * status is read, the character with the issue is at the top of the FIFO, + * and when no other issues exist in the FIFO. + */ + ALT_16550_LINE_STATUS_RFE = 1 << 7, + + /*! + * Transmitter EMpTy (Empty). This status indicates that transmitter shift + * register is empty. If FIFOs are enabled, the status is set when the + * transmitter FIFO is also empty. This status is cleared when the + * transmitter shift registers is loaded by writing to the UART + * transmitter buffer or transmitter FIFO if FIFOs are enabled. This is + * done by calling alt_16550_write() and alt_16550_fifo_write() + * respectively. + */ + ALT_16550_LINE_STATUS_TEMT = 1 << 6, + + /*! + * Transmitter Holding Register Empty. This status indicates that the + * transmitter will run out of data soon. The definition of soon depends + * on whether the FIFOs are enabled. + * + * If FIFOs are disabled, this status indicates that the transmitter will + * run out of data to send after the current transmit shift register + * completes. In this case, this status is cleared when the data is + * written to the UART. This can be done by calling alt_16550_write(). + * + * If FIFOs are enabled, this status indicates that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * this status is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * \internal + * The implementation of the UART driver always ensures that IER[7] is + * set. This means that the UART always has Programmable THRE (Transmitter + * Holding Register Empty) Interrupt Mode Enable (PTIME) enabled. + * \endinternal + */ + ALT_16550_LINE_STATUS_THRE = 1 << 5, + + /*! + * Break Interrupt. This status indicates that a break interrupt sequence + * is detected in the incoming serial data. This happens when the the data + * is 0 for longer than a frame would normally be transmitted. The break + * interrupt status is cleared by reading the line status by calling + * alt_16550_line_status_get(). + * + * If FIFOs are enabled, this status will be set when the character with + * the break interrupt status is at the top of the receiver FIFO. + */ + ALT_16550_LINE_STATUS_BI = 1 << 4, + + /*! + * Framing Error. This status indicates that a framing error occurred in + * the receiver. This happens when the receiver detects a missing or + * incorrect number of stopbit(s). + * + * If FIFOs are enabled, this status will be set when the character with + * the framing error is at the top of the FIFO. When a framing error + * occurs, the UART attempts to resynchronize with the transmitting UART. + * This status is also set if break interrupt occurred. + */ + ALT_16550_LINE_STATUS_FE = 1 << 3, + + /*! + * Parity Error. This status indicates that a parity error occurred in the + * receiver. + * + * If FIFOs are enabled, this status will be set when the character with + * the parity error is at the top of the receiver FIFO. This status is + * also set if a break interrupt occurred. + */ + ALT_16550_LINE_STATUS_PE = 1 << 2, + + /*! + * Overrun Error. This status indicates that an overrun occurred in the + * receiver. + * + * If FIFOs are disabled, the arriving character will overwrite the + * existing character in the receiver. Any previously existing + * character(s) will be lost. + * + * If FIFOs are disabled, the arriving character will be discarded. The + * buffer will continue to contain the preexisting characters. + */ + ALT_16550_LINE_STATUS_OE = 1 << 1, + + /*! + * Data Ready. This status indicates that the receiver or receiver FIFO + * contains at least one character. + */ + ALT_16550_LINE_STATUS_DR = 1 << 0 +} +ALT_16550_LINE_STATUS_t; + +/*! + * Sets the configuration for a given character frame. + * + * \param handle + * The UART device handle. + * + * \param databits + * The number of databits for each character frame. + * + * \param parity + * The parity to use for each character frame. + * + * \param stopbits + * The number of stopbits for each character frame. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle, + ALT_16550_DATABITS_t databits, + ALT_16550_PARITY_t parity, + ALT_16550_STOPBITS_t stopbits); + +/*! + * Starts transmitting a break condition by transmitting a logic 0 state + * longer than a frame would normally be transmitted. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle); + +/*! + * Stops transmitting a break condition. + * + * \param handle + * The UART device handle. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle); + +/*! + * Reads the line status from the UART. + * + * \param handle + * The UART device handle. + * + * \param status + * [out] Pointer to an output parameter that contains the current + * line status of the UART. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given UART device handle is invalid. + */ +ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle, + uint32_t * status); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_16550_UART_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_address_space.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_address_space.h new file mode 100644 index 000000000..24b2cf629 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_address_space.h @@ -0,0 +1,825 @@ +/*! \file + * Altera - SoC FPGA Address Space Manager + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_ADDRESS_SPACE_H__ +#define __ALT_ADDRESS_SPACE_H__ + +#include +#include "hwlib.h" +#include "socal/hps.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +// ARM Level 2 Cache Controller L2C-310 Register Interface + +// Address Filtering Start Register +// The Address Filtering Start Register is a read and write register. +// Bits Field Description +// :-------|:--------------------------|:----------------------------------------- +// [31:20] | address_filtering_start | Address filtering start address for +// | | bits [31:20] of the filtering address. +// [19:1] | Reserved | SBZ/RAZ +// [0] | address_filtering_enable | 0 - address filtering disabled +// | | 1 - address filtering enabled. + +// Address Filtering Start Register Address +#define L2_CACHE_ADDR_FILTERING_START_OFST 0xC00 +#define L2_CACHE_ADDR_FILTERING_START_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST) +// Address Filtering Start Register - Start Value Mask +#define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000 +// Address Filtering Start Register - Reset Start Address Value (1 MB) +#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 +// Address Filtering Start Register - Enable Flag Mask +#define L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001 +// Address Filtering Start Register - Reset Enable Flag Value (Enabled) +#define L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1 + +// Address Filtering End Register +// The Address Filtering End Register is a read and write register. +// Bits Field Description +// :-------|:--------------------------|:----------------------------------------- +// [31:20] | address_filtering_end | Address filtering end address for bits +// | | [31:20] of the filtering address. +// [19:0] | Reserved | SBZ/RAZ + +// Address Filtering End Register Address +#define L2_CACHE_ADDR_FILTERING_END_OFST 0xC04 +#define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST) +// Address Filtering End Register - End Value Mask +#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000 +// Address Filtering End Register - Reset End Address Value (3 GiB) +#define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000 + +#ifndef __ASSEMBLY__ + +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR The Address Space Manager + * + * This module contains group APIs for managing the HPS address space. This + * module contains group APIs to manage: + * * Memory Map Control + * * Memory Coherence + * * Cache Managment + * * MMU Managment + * + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control + * + * This group API provides functions to map and remap selected address ranges + * into the accessible (visible) views of the MPU and non MPU address spaces. + * + * \b Caveats + * + * \b NOTE: Caution should be observed when remapping address 0 to different + * memory. The code performing the remapping operation should not be executing + * in the address range being remapped to different memory. + * + * For example, if address 0 is presently mapped to OCRAM and the code is + * preparing to remap address 0 to SDRAM, then the code must not be executing in + * the range 0 to 64 KB as this address space is about to be remapped to + * different memory. If the code performing the remap operation is executing + * from OCRAM then it needs to be executing from its permanently mapped OCRAM + * address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR). + * + * \b NOTE: The MPU address space view is controlled by two disparate hardware + * control interfaces: the L3 remap register and the L2 cache address filtering + * registers. To complicate matters, the L3 remap register is write-only which + * means not only that current remap register state cannot be read but also that + * a read-modify-write operation cannot be performed on the register. + * + * This should not present a problem in most use case scenarios except for the + * case where a current MPU address space mapping of 0 to SDRAM is being changed + * to to a mapping of 0 to Boot ROM or OCRAM. + * + * In this case, a two step process whereby the L3 remap register is first set + * to the new desired MPU address 0 mapping and then the L2 cache address + * filtering registers have their address ranges adjusted accordingly must be + * followed. An example follows: +\verbatim +// 1 MB reset default value for address filtering start +#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 +uint32_t addr_filt_start; +uint32_t addr_filt_end; + +// Perform L3 remap register programming first by setting the desired new MPU +// address space 0 mapping. Assume OCRAM for the example. +alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...); + +// Next, adjust the L2 cache address filtering range. Set the start address to +// the default reset value and retain the existing end address configuration. +alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end); +if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET) +{ + alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end); +} +\endverbatim + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the MPU address space attributes. + * + * The MPU address space consists of the ARM Cortex A9 processors and associated + * processor peripherals (cache, MMU). + */ +typedef enum ALT_ADDR_SPACE_MPU_ATTR_e +{ + ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM, /*!< Maps the Boot ROM to address + * 0x0 for the MPU L3 master. Note + * that the Boot ROM is also + * always mapped to address + * 0xfffd_0000 for the MPU L3 + * master independent of + * attribute. + */ + + ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address + * 0x0 for the MPU L3 master. Note + * that the On-chip RAM is also + * always mapped to address + * 0xffff_0000 for the MPU L3 + * master independent of this + * attribute. + */ +} ALT_ADDR_SPACE_MPU_ATTR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the non-MPU address space attributes. + * + * The non-MPU address space consists of the non-MPU L3 masters including the + * DMA controllers (standalone and those built into peripherals), the F2H AXI + * Bridge, and the DAP. + */ +typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e +{ + ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, /*!< Maps the SDRAM to address 0x0 + * for the non-MPU L3 masters. + */ + ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address + * 0x0 for the non-MPU L3 + * masters. Note that the On-chip + * RAM is also always mapped to + * address 0xffff_0000 for the + * non-MPU L3 masters independent + * of this attribute. + */ +} ALT_ADDR_SPACE_NONMPU_ATTR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the HPS to FPGA bridge accessiblity + * attributes. + */ +typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e +{ + ALT_ADDR_SPACE_H2F_INACCESSIBLE, /*!< The H2F AXI Bridge is not + * visible to L3 masters. Accesses + * to the associated address range + * return an AXI decode error to + * the master. + */ + ALT_ADDR_SPACE_H2F_ACCESSIBLE /*!< The H2F AXI Bridge is visible + * to L3 masters. + */ +} ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the Lightweight HPS to FPGA bridge + * accessiblity attributes. + */ +typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e +{ + ALT_ADDR_SPACE_LWH2F_INACCESSIBLE, /*!< The LWH2F AXI Bridge is not + * visible to L3 masters. Accesses + * to the associated address range + * return an AXI decode error to + * the master. + */ + ALT_ADDR_SPACE_LWH2F_ACCESSIBLE /*!< The LWH2F AXI Bridge is visible + * to L3 masters. + */ +} ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t; + +/******************************************************************************/ +/*! + * Configures the mapped and accessible (visible) address ranges for the HPS + * MPU, non-MPU, and Bridge address spaces. + * + * \param mpu_attr + * The MPU address space configuration attributes. + * + * \param nonmpu_attr + * The non-MPU address space configuration attributes. + * + * \param h2f_attr + * The H2F Bridge attribute mapping and accessibility attributes. + * + * \param lwh2f_attr + * The Lightweight H2F Bridge attribute mapping and accessibility + * attributes. + * + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_INV_OPTION One or more invalid attribute options were + * specified. + */ +ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, + ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr, + ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr, + ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr); + +/******************************************************************************/ +/*! + * Maps SDRAM to address 0x0 for the MPU address space view. + * + * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest + * 64KB of the boot region are accessible because the size of the Boot ROM and + * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to + * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to + * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not + * accessible to the MPU unless address 0 is remapped to SDRAM after reset. + * + * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access + * SDRAM. + * + * \internal + * The remap to address 0x0 is achieved by configuring the L2 cache Address + * Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM + * AXI (M1) master port by calling: + * + * alt_l2_addr_filter_cfg_set(0x0, ); + * + * See: ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical + * Reference Manual, Section 3.3.12 Address Filtering . + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter + * + * The L2 cache address filter controls where physical addresses within certain + * ranges of the MPU address space are directed. + * + * The L2 cache has master port connections to the L3 interconnect and the SDRAM + * controller. A programmable address filter controls which portions of the + * 32-bit physical address space use each master. + * + * When l2 address filtering is configured and enabled, a physical address will + * be redirected to one master or the other based upon the address filter + * configuration. + * + * If \b address_filter_start <= \e physical_address < \b address_filter_end: + * * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller) + * * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect) + * + * See: ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical + * Reference Manual, Section 3.3.12 Address Filtering for more information. + * @{ + */ + +/******************************************************************************/ +/*! + * Get the L2 cache address filtering configuration settings. + * + * \param addr_filt_start + * [out] An output parameter variable for the address filtering + * start address for the range of physical addresses redirected to + * the SDRAM AXI master port. The value returned is always a 1 MiB + * aligned address. + * + * \param addr_filt_end + * [out] An output parameter variable for the address filtering + * end address for the range of physical addresses redirected to + * the SDRAM AXI master port. The value returned is always a 1 MiB + * aligned address. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG An bad argument was passed. Either \e addr_filt_start + * or \e addr_filt_end or both are invalid addresses. + */ +ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start, + uint32_t* addr_filt_end); + +/******************************************************************************/ +/*! + * Set the L2 cache address filtering configuration settings. + * + * Address filtering start and end values must be 1 MiB aligned. + * + * \param addr_filt_start + * The address filtering start address for the range of physical + * addresses redirected to the SDRAM AXI master port. Only bits + * [31:20] of the address are valid. Any bits outside the range + * [31:20] are invalid and will cause an error status to be + * returned. + * + * \param addr_filt_end + * The address filtering end address for the range of physical + * addresses redirected to the SDRAM AXI master port. Only bits + * [31:20] of the address are valid. Any bits outside the range + * [31:20] are invalid and will cause an error status to be + * returned. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more address arguments do not satisfy the argument + * constraints. + */ +ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, + uint32_t addr_filt_end); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping + * + * This API provides management of the ACP ID Mapper that enables data coherent + * access to the MPU address space by external masters. The set of external + * masters include L3 master peripherals and FPGA soft IP. + * + * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA + * based soft IP - to maintain data coherency with the Cortex-A9 MPCore + * processors and the Snoop Control Unit (SCU). + * + * The ACP supports up to six masters. However, soft IP implemented in the FPGA + * fabric can have a larger number of masters that need to access the ACP. The + * ACP ID Mapper expands the number of masters able to access the ACP. The ACP + * ID Mapper is situated between the interconnect and the ACP of the MPU + * subsystem. It has the following characteristics: + * * Support for up to six concurrent ID mappings. + * * 1 GiB coherent window into 4 GiB MPU address space + * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU) + * and L2 cache. + * + * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller + * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input + * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output + * identifiers) required by the ACP slave port. + * + * The ACP ID Mapper supports the two ID mapping modes: + * * Dynamic Mapping - In this mode an input ID is automatically mapped to an + * available output ID. The dynamic mode is more flexible because the hardware + * handles the mapping. The hardware mapping allows an output ID to be used + * for more than one input ID. Output IDs are assigned to input IDs on a + * first-come, first-served basis. + * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs + * to output IDs. + * + * Out of the total of eight ACP output ID values, only six are available to the + * ACP ID Mapper for remapping. The first two output IDs (0 and 1) are + * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the + * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6 + * support fixed and dynamic modes of operation while output ID 7 supports + * dynamic mode only. + * + * The following table summarizes the usage of the 3-bit ouput ID values by the + * ACP ID Mapper and their settings at reset. + * + * Output ID | Usage | Reset State + * :-----------|:--------------------------------------------------|:------------ + * 0 | Reserved for Cortex-A9 cores. | - + * 1 | Reserved for Cortex-A9 cores. | - + * 2 | Assigned to Debug Access Port (DAP) input ID at | Fixed + * : | reset. After reset, can be reconfigured to either | DAP Master + * : | fixed or dynamic. |: + * 3 | Configurable fixed or dynamic mode. | Dynamic + * 4 | Configurable fixed or dynamic mode. | Dynamic + * 5 | Configurable fixed or dynamic mode. | Dynamic + * 6 | Configurable fixed or dynamic mode. | Dynamic + * 7 | Dynamic mode only. | Dynamic + * + * Where Output ID is the ACP ID Mapper output value that goes to the ACP. + * + * Additionally, for masters unable to drive the AXI user sideband signals of + * incoming transactions, the ACP ID Mapper allows control of the AXI user + * sideband signal values. Not all masters drive these signals, so the ACP ID + * Mapper makes it possible to drive the 5-bit user sideband signal with either + * a default value (in dynamic mode) or specific values (in fixed mode). + * + * The ACP ID Mapper can also control which 1 GiB coherent window into memory is + * accessed by masters of the L3 interconnect. Each fixed mapping can be + * assigned a different user sideband signal and memory window to allow specific + * settings for different masters. All dynamic mappings share a common user + * sideband signal and memory window setting. One important exception, however, + * is that the ACP ID mapper always allows user sideband signals from the + * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured + * user sideband value associated with the ID. + * + * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which + * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows + * transactions to be routed to different 1 GiB-sized memory views, called pages, + * in both dynamic and fixed modes. + * + * See: Chapter 6: Cortex-A9 Microprocessor Unit Subsystem in + * Volume 3: Hard Processor System Technical Reference Manual of the + * Arria V or Cyclone V Device Handbook for a complete discussion of + * the operation and restrictions on the ACP and the ACP ID Mapper. + * + * @{ + */ + +/******************************************************************************/ +/*! + * \name External Master ID Macros + * + * These macros define the HPS external master identifiers that are 12-bit input + * IDs to the ACP ID Mapper. Some of the masters have a range of identifier + * values assigned to them and are distinguished by taking a (var)\ + * argument. + * @{ + */ + +/*! Bit mask for the relevant 12 bits of an external master ID */ +#define ALT_ACP_ID_MAP_MASTER_ID_MASK 0xfff + +/*! Master ID for L2M0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var) (0x00000002 | (0x000007f8 & (var))) +/*! Master ID for DMA */ +#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var) (0x00000001 | (0x00000078 & (var))) +/*! Master ID for EMAC0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var) (0x00000801 | (0x00000878 & (var))) +/*! Master ID for EMAC1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var) (0x00000802 | (0x00000878 & (var))) +/*! Master ID for USB0 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB0 0x00000803 +/*! Master ID for USB1 */ +#define ALT_ACP_ID_MAP_MASTER_ID_USB1 0x00000806 +/*! Master ID for NAND controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var) (0x00000804 | (0x00000ff8 & (var))) +/*! Master ID for Embedded Trace Router (ETR) */ +#define ALT_ACP_ID_MAP_MASTER_ID_TMC 0x00000800 +/*! Master ID for Debug Access Port (DAP) */ +#define ALT_ACP_ID_MAP_MASTER_ID_DAP 0x00000004 +/*! Master ID for SD/MMC controller */ +#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC 0x00000805 +/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */ +#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var) (0x00000000 | (0x000007f8 & (var))) +/*! @} */ + +/******************************************************************************/ +/*! + * This type defines the enumerations 3-bit output ids to ACP ID mapper. + */ +typedef enum ALT_ACP_ID_OUTPUT_ID_e +{ + ALT_ACP_ID_OUT_FIXED_ID_2 = 2, /*!< Assigned to the input ID of the DAP at reset. + * After reset, can be either fixed or dynamic, + * programmed by software. + */ + ALT_ACP_ID_OUT_DYNAM_ID_3 = 3, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_4 = 4, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_5 = 5, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_6 = 6, /*!< Fixed or dynamic, programmed by software output id */ + ALT_ACP_ID_OUT_DYNAM_ID_7 = 7 /*!< Dynamic mapping only */ +} ALT_ACP_ID_OUTPUT_ID_t; + +/*! + * This type defines the enumerations used to specify the 1 GiB page view of the + * MPU address space used by an ACP ID mapping configuration. + */ +typedef enum ALT_ACP_ID_MAP_PAGE_e +{ + ALT_ACP_ID_MAP_PAGE_0 = 0, /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_1 = 1, /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */ + ALT_ACP_ID_MAP_PAGE_2 = 2, /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */ + ALT_ACP_ID_MAP_PAGE_3 = 3 /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */ +} ALT_ACP_ID_MAP_PAGE_t; + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for read transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating read transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates read + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure a fixed ACP ID mapping for write transactions originating from + * external masters identified by \e input_id. The \e input_id value is + * translated to the specified 3-bit \e output_id required by the ACP slave + * port. + * + * \param input_id + * The 12 bit external master ID originating write transactions + * targeted for ID translation. Valid argument range must be 0 <= + * \e output_id <= 4095. + * + * \param output_id + * The 3-bit output ID value the ACP ID Mapper translates write + * transactions identified by \e input_id to. This is the value + * propogated to the ACP slave port. Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e awuser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e input_id, and/or \e output_id + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e page argument is invalid. + */ +ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, + const uint32_t output_id, + const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for read + * transactions. The \e output_id value is available for dynamic assignment to + * external master read transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_read_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the designated 3-bit output ID as an available identifier resource + * for use by the dynamic ID mapping function of the ACP ID Mapper for write + * transactions. The \e output_id value is available for dynamic assignment to + * external master write transaction IDs that do not have an explicit fixed ID + * mapping. + * + * \param output_id + * The 3-bit output ID value designated as an available ID for use + * by the dynamic mapping function of the ACP ID Mapper. The \e + * ouput_id value is used exclusively for dynamic ID mapping until + * reconfigured as a fixed ID mapping by a call to + * alt_acp_id_map_fixed_write_set(). Valid argument values must be + * 0 <= \e output_id <= 7. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id); + +/******************************************************************************/ +/*! + * Configure the page and user read sideband signal options that are applied to + * all read transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param aruser + * The 5-bit AXI ARUSER read user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e aruser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t aruser); + +/******************************************************************************/ +/*! + * Configure the page and user write sideband signal options that are applied to + * all write transactions that have their input IDs dynamically mapped. + * + * \param page + * The MPU address space page view to use for the ACP window used + * by the dynamic ID tranlation mapping. + * + * \param awuser + * The 5-bit AXI AWUSER write user sideband signal value to use for + * masters unable to drive the AXI user sideband signals. Valid + * argument range is 0 <= \e aruser <= 31. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or + * more of the \e page and/or \e awuser + * arguments violates its range constraint. + * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master + * identifier. + */ +ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, + const uint32_t awuser); + +/******************************************************************************/ +/*! + * Return the current read transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param aruser + * [out] The 5-bit AXI ARUSER read user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* aruser); + +/******************************************************************************/ +/*! + * Return the current write transaction mapping configuration used by the ACP ID + * Mapper for the specified output ID. + * + * If \e output_id is configured as a fixed mapping then \b true is returned in + * the \e fixed output parameter and the translation mapping options configured + * for that \e output_id are returned in the other output parameters. + * + * If \e output_id is configured as a dynamic mapping then \b false is returned + * in the \e fixed output parameter and the translation mapping options + * configured for all dynamically remapped output IDs are returned in the other + * output parameters. + * + * \param output_id + * The output ID to return the mapping configuration for. 0 <= \e + * output_id <= 7. + * + * \param fixed + * [out] Set to \b true if the specified \e output_id is a fixed ID + * mapping configuration. Set to \b false if the mapping + * configuration is dynamic. + * + * \param input_id + * [out] The input ID of the external master that a fixed ID + * mapping is applied to for the \e output_id. If \e fixed is \b + * false then this output parameter is set to 0 and its value + * should be considered as not applicable. + * + * \param page + * [out] The MPU address space page view used by the mapping + * configuration. + * + * \param awuser + * [out] The 5-bit AXI AWUSER write user sideband signal value used + * by the mapping configuration when masters are unable to drive + * the AXI user sideband signals. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_RESERVED The argument value is reserved or unavailable. + * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e + * output_id argument violates its range constraint. + */ +ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, + bool* fixed, + uint32_t* input_id, + ALT_ACP_ID_MAP_PAGE_t* page, + uint32_t* awuser); + +/*! @} */ + +/*! @} */ + +#endif /* __ASSEMBLY__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_ADDRESS_SPACE_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_bridge_manager.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_bridge_manager.h new file mode 100644 index 000000000..c1750bd5e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_bridge_manager.h @@ -0,0 +1,269 @@ +/*! \file + * Altera - SoC FPGA FPGA/HPS Bridge Management + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_BRG_MGR_H__ +#define __ALT_BRG_MGR_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_BRIDGE The AXI Bridge Manager + * + * The functions in this group manage access, configuration, and control of the + * AXI bridges between the FPGA and HPS. + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the AXI bridge interfaces between the FPGA + * and HPS. + */ +typedef enum ALT_BRIDGE_e +{ + ALT_BRIDGE_F2H, /*!< FPGA-to-HPS AXI bridge providing a + * high-performance, statically configurable + * width interface that gives the FPGA the + * ability to: + * * master transactions to slaves in the HPS + * * have full visibility into the HPS address space + * * access the coherent memory interface (ACP) + * + * The width (32/64/128 bits) of this bridge + * is statically configurable at design time + * using \e Quartus. + */ + ALT_BRIDGE_H2F, /*!< HPS-to-FPGA AXI bridge providing a + * statically configurable width, + * high-performance master interface to the + * FPGA fabric. The bridge provides a 1GB + * address space and gives any master in the + * HPS system access to logic, peripherals, + * and memory implemented in the FPGA. + */ + ALT_BRIDGE_LWH2F /*!< Lightweight HPS-to-FPGA AXI bridge + * providing a secondary, fixed-width, smaller + * address space, lower-performance master + * interface to the FPGA fabric. The bridge + * provides a 2MB address space and gives any + * master in the HPS access to logic, + * peripherals, and memory implemented in the + * FPGA fabric. The bridge master exposed to + * the FPGA fabric has a fixed data width of + * 32 bits. + * + * The bridge provides clock crossing logic to + * allow the logic in the FPGA to run + * asynchronous to the HPS. The bridge + * simplifies the process of connecting the + * HPS to soft logic. Soft logic can even be + * designed to support only a subset of the + * full AXI protocol that the bridge + * supports. Use the lightweight HPS-to-FPGA + * bridge for high-latency, low-bandwidth + * traffic, such as memory-mapped register + * accesses of FPGA peripherals. This approach + * diverts traffic from the high-performance + * HPS-to-FPGA bridge, which can improve + * overall performance. + */ +} ALT_BRIDGE_t; + +/******************************************************************************/ +/*! + * Type definition for a callback function prototype used by the + * alt_bridge_init() bridge initialization function to determine whether the + * FPGA is ready to begin transactions across the bridge interface. + * + * The implementation of the callback function is user defined allowing the user + * to define a flexible signaling protocol for the FPGA to indicate its + * readiness to begin transactions across the initialized bridge interface. + * + * The range of values returned by the callback function may be extended per the + * user defined FPGA readiness signaling protocol but any return value other + * than ALT_E_SUCCESS will be interpreted by the alt_bridge_init() bridge + * initialization function as an indication that the FPGA is not ready to + * commence bridge interface transactions. + * + * \param user_arg + * This is a user defined parameter available to pass additional + * data that might be needed to support the user defined FPGA + * readiness signaling protocol. + * + * \retval ALT_E_SUCCESS The FPGA is ready to commence bridge interface + * transactions. + * \retval ALT_E_ERROR An error has occurred. The FPGA is not ready to + * commence bridge interface transactions. + * \retval ALT_E_TMO The FPGA failed to signal a ready to commence + * bridge interface transactions indication before + * the response timeout period expired. + */ +typedef ALT_STATUS_CODE (*alt_bridge_fpga_is_ready_t)(void* user_arg); + +/******************************************************************************/ +/*! + * Initialize the bridge for bus transactions by bringing up the interface in a + * safe, controlled sequence. + * + * The following actions are performed as part of the process of initializing + * the bridge interface for transactions: + * + * * Sets and holds bridge interface in reset. + * * Ensures that the bridge interface is ready by asserting that: + * - FPGA is powered and configured (i.e. in USER mode). + * - Bridge interface clock is ready and stable. + * - FPGA soft IP is ready for transactions across the bridge interface. + * * Releases bridge interface from reset. + * + * The mechanism used by alt_bridge_init() to determine whether the FPGA soft IP + * is ready to begin bus transactions across the interface is the user defined + * callback \e fpga_is_ready. + * + * \internal + * This process of software controlled bring-up of HPS/FPGA interfaces is + * detailed in Hammerhead-P HPS FPGA Interface NPP, Section 4 Software + * Bring-up/Tear-down. + * \endinternal + * + * \param bridge + * The bridge interface to initialize. + * + * \param fpga_is_ready + * A pointer to a user defined callback function to determine + * whether the FPGA is ready to commence bridge interface + * transactions. If NULL is passed, then bridge interface + * initialization proceeds without making a determination of + * whether the FPGA is ready to commence bridge interface + * transactions or not. + * + * \param user_arg + * A user defined argument value for passing support data to the \e + * fpga_is_ready callback function. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_bridge_init(ALT_BRIDGE_t bridge, + alt_bridge_fpga_is_ready_t fpga_is_ready, + void* user_arg); + +/******************************************************************************/ +/*! + * Type definition for a callback function prototype used by the + * alt_bridge_uninit() function to conduct a handshake protocol with the FPGA + * notifying it that the bridge interface is being taken down. + * + * The callback function implementation is user defined and allows the user to + * implement a flexible handshake notification protocol with the FPGA to allow + * an orderly interface shutdown prior to the bridge being taken down. + * + * The handshake protocol is user defined but normally consists of two parts: + * * The processor notifies the FPGA soft IP that the bridge interface is being + * taken down. The notification mechanism used to signal the FPGA is user + * defined. + * * The process waits for an acknowledgement response from the FPGA. + * + * The range of return values for the callback function may be extended per the + * user defined handshake notification protocol but any return value other than + * ALT_E_SUCCESS will be interpreted by the alt_bridge_uninit() function as an + * indication that the handshake protocol was unsuccessful. + * + * \param user_arg + * This is a user defined parameter available to pass additional + * data that might be needed to support the user defined handshake + * notification protocol. + * + * \retval ALT_E_SUCCESS The handshake notification protocol was successful. + * \retval ALT_E_ERROR An error has occurred. The handshake notification + * protocol was unsuccessful. + * \retval ALT_E_TMO The handshake notification protocol failed + * because a response timeout period expired. + */ +typedef ALT_STATUS_CODE (*alt_bridge_teardown_handshake_t)(void* user_arg); + +/******************************************************************************/ +/*! + * Uninitialize the bridge by tearing down the interface in a safe and + * controlled sequence. + * + * The process of taking down the bridge interface entails: + * * Optional: Conduct teardown handshake notification protocol + * - Bridge Manager informs FPGA that the bridge interface is being torn down. + * - Bridge Manager waits for FPGA response to notification. + * * Processor waits for the completion of outstanding transactions on the AXI + * bridge. Note, that HPS has no mechanism to track outstanding AXI transactions; + * this needs to be provided by the customer design. + * * Places and holds the bridge interface in reset. + * + * The mechanism used by alt_bridge_uninit() to initiate the handshake + * notification to the FPGA soft IP that the bridge interface is being taken + * down is the user defined \e handshake callback. + * + * \internal + * This function implements the software controlled tear-down procedure detailed + * in Hammerhead-P HPS FPGA Interface NPP, Section 4 Software + * Bring-up/Tear-down. + * \endinternal + * + * \param bridge + * The bridge interface to uninitialize. + * + * \param handshake + * A pointer to a user defined tear-down handshake protocol. If + * NULL is passed, then the bridge interface take down proceeds + * without conducting any handshake notification protocol. + * + * \param user_arg + * A user defined argument value for passing support data to the + * \e teardown_hs callback function. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_bridge_uninit(ALT_BRIDGE_t bridge, + alt_bridge_teardown_handshake_t handshake, + void* user_arg); + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_BRG_MGR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_cache.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_cache.h new file mode 100644 index 000000000..69310825e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_cache.h @@ -0,0 +1,964 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_CACHE_H__ +#define __ALT_CACHE_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup CACHE_MGR Cache Management API + * + * This module defines the cache management API for enabling and disabling L1 + * data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1 + * TLB cache, and L2 cache in the SoC. As well, many it allows users to perform + * cache maintenance operations on these caches. This includes the following + * operations: + * * Invalidate: Marks the cache line as being invalid, freeing up the space + * to cache other data. All APIs which enable caches invalidates the memory + * before being enabling the cache. + * * Clean: If the cache line is dirty, it synchronizes the cache line data + * with the upper level memory system and marks that line as clean. All APIs + * which disable caches cleans the memory before disabling the cache. + * * Purge: A term used in this API as a short form for clean and invalidate. + * This operation cleans and invalidates a cache line in that order, as a + * single command to the cache controller. + * + * The following reference materials were used in the design of this API: + * * ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition + * * Cortex™-A9 Technical Reference Manual + * * Cortex™-A9 MPCore Technical Reference Manual + * * CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference + * Manual + * + * @{ + */ + +/*! + * \addtogroup CACHE_SYS System Level Cache Management API + * + * This API group provides cache maintenance operations which affects multiple + * cache levels. + * + * The enable and disable functions enables and disables all caches in the + * system respectively. For caches shared by the CPU core(s), particularly the + * L2 cache, once that cache is enabled or disabled it will not be invalidated + * or cleaned again respectively. This allows the safe system-wide enable and + * disable to be used in single-core and multi-core scenarios. + * + * For cache maintenance operations, this API implements the procedures + * outlined in the L2C-310 Technical Reference Manual, section 3.3.10, + * subsection "System cache maintenance considerations". This allows for a + * convenient way to invalidate, clean, or clean and invalidate cache data from + * the L1 to L2 to L3 while avoiding any potential race conditions in + * mutli-core or multi-master scenarios. It assumes that the L1 and L2 cache is + * set in "non-exclusive" mode. This means a segment of data can reside in both + * the L1 and L2 simultaneously. This is the default mode for caches in the + * system. + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * @{ + */ + +/*! + * Enables support for a non-flat virtual memory. A flat virtual memory is + * where every virtual address matches exactly to the physical address, making + * the virtual to physical translation trivial. Adding support for non-flat + * adds some overhead for the VA to PA translation and error detection. + * + * To enable non-flat virtual memory support, defined + * ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY=1 in your Makefile when compiling + * HWLibs. + */ +#ifndef ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY +#define ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY (0) +#endif + +/*! + * This is the system wide cache line size, given in bytes. + */ +#define ALT_CACHE_LINE_SIZE 32 + +/*! + * Enables all caches and features which improve reliability and speed on all + * cache controllers visible to the current CPU core. This includes parity + * error detection. Cache controllers visible to multiple CPU cores, for + * example the L2, will first be checked to be disabled before being enabled. + * All necessary cache maintenance operations will be done automatically. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_system_enable(void); + +/*! + * Disables all cache controllers visible to the current CPU core. Cache + * controllers visible to multiple CPU cores, for example the L2, will first + * be checked to be enabled before being disabled. All necessary cache + * maintenance operations will be done automatically. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_system_disable(void); + +/*! + * Invalidates the specified contents of all cache levels visible to the + * current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L2 invalidate address(es) + * -# L2 cache sync + * -# L1 invalidate address(es) + * -# DSB instruction + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length); + +/*! + * Cleans the specified contents of all cache levels visible to the current + * CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L1 clean address(es) + * -# DSB instruction + * -# L2 clean address(es) + * -# L2 cache sync + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length); + +/*! + * Cleans and invalidates the specified contents of all cache levels visible + * to the current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * The following pseudocode outlines the operations carried out by this + * function: + * -# L1 clean address(es) + * -# DSB instruction + * -# L2 clean and invalidate address(es) + * -# L2 cache sync + * -# L1 invalidate address(es) + * -# DSB instruction + * + * The current implementation of the system cache APIs assumes that the MMU is + * configured with a flat memory mapping or that every virtual address matches + * perfectly with the physical address. This restriction may be lifted in a + * future release of the cache API implementation. + * + * \param vaddress + * The virtual address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length); + +/*! + * @} + */ + +/*! + * \addtogroup CACHE_L1 L1 Cache Management API + * + * This API group provides functions to interact with various components of the + * L1 cache on the SoCFPGA. This includes the following cache components: + * * Instruction Cache + * * Data Cache + * * Parity error detection + * * Dynamic branch prediction + * * Data prefetching + * + * The API within this group only affects the L1 cache on the current CPU. To + * interact the L1 cache on another CPU, the API must be called from that other + * CPU. + * + * With respect to bring-up, the L1 and L2 cache controller setups are fully + * independent. The L2 can be setup at any time, before or after the L1 is setup. + * \internal + * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". + * \endinternal + * + * @{ + */ + +/*! + * Enables all L1 caches and features on the current CPU core. This includes + * the instruction cache, data cache, parity error detection, branch target + * address cache, global history buffer, and data prefetching. All necessary + * maintenance tasks will be taken care of. + * + * This function should not be mixed with other L1 cache related functions + * which enable or disable caches individually. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_enable_all(void); + +/*! + * Disables all L1 caches and features on the current CPU core. This includes + * the instruction cache, data cache, parity error detection, branch target + * address cache, global history buffer, and data prefetching. All necessary + * maintenance tasks will be taken care of. + * + * This function should not be mixed with other L1 cache related functions + * which enable or disable caches individually. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_disable_all(void); + +/*! + * Enables the L1 instruction cache on the current CPU core. If the cache is + * already enabled, nothing is done. Otherwise the instruction cache is first + * invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_enable(void); + +/*! + * Disables the L1 instruction cache on the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_disable(void); + +/*! + * Returns \b true when the L1 instruction cache is enabled and \b false when + * it is disabled on the current CPU core. + * + * \retval true The L1 instruction cache is enabled. + * \retval false The L1 instruction cache is disabled. + */ +bool alt_cache_l1_instruction_is_enabled(void); + +/*! + * Invalidates the contents of the L1 instruction cache on the current CPU + * core. + * + * Normally this is done automatically as part of + * alt_cache_l1_instruction_enable(), but in certain circumstances it may be + * necessary to invalidate it manually. An example of this situation is when + * the address space is remapped and the processor executes instructions from + * the new memory area. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void); + +/*! + * Enables the L1 data cache on the current CPU core. + * + * If the cache is already enabled nothing is done. Otherwise the data cache is + * first invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_enable(void); + +/*! + * Disables the L1 data cache on the current CPU core. + * + * If the cache is already disabled nothing is done. Otherwise the data cache + * is first cleaned before being disabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_disable(void); + +/*! + * Returns \b true when the L1 data cache is enabled and \b false when it is + * disabled on the current CPU core. + * + * \retval true The L1 data cache is enabled. + * \retval false The L1 data cache is disabled. + */ +bool alt_cache_l1_data_is_enabled(void); + +/*! + * Invalidates the specified contents of the L1 data cache on the current CPU + * core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param vaddress + * The virtual address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length); + +/*! + * Invalidates the entire contents of the L1 data cache on the current CPU + * core. + * + * Normally this is done automatically as part of alt_cache_l1_data_enable(), + * but in certain circumstances it may be necessary to invalidate it manually. + * An example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void); + +/*! + * Cleans the specified contents of the L1 data cache on the current CPU core + * for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param vaddress + * The virtual address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length); + +/*! + * Cleans the entire L1 data cache for the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_clean_all(void); + +/*! + * Cleans and invalidates the specified contents of the L1 data cache on the + * current CPU core for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * Normally this is done automatically as part of alt_cache_l1_data_disable(), + * but in certain circumstances it may be necessary to purged it manually. + * An example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + * + * \param vaddress + * The virtual address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length); + +/*! + * Cleans and invalidates the entire L1 data cache for the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_data_purge_all(void); + +/*! + * Enables the parity error detection feature in the L1 caches on the current + * CPU core. + * + * Ideally parity should be enabled before any L1 caches are enabled. If the + * instruction, data, and / or dynamic branch predictor caches are already + * enabled, they will first be cleaned (if needed) and disabled before parity + * is enabled in hardware. Afterwards, the affected caches will be invalidated + * and enabled. + * + * Parity and TLB interaction deserves special attention. The TLB is considered + * to be a L1 cache but is enabled when the MMU, which is grouped in another + * API, is enabled. Due to the system-wide influence of the MMU, it cannot be + * disabled and enabled with impunity as the other L1 caches, which are + * designed to operate as transparently as possible. Thus parity error + * detection must be enabled before the L1 TLB cache, and by extension the MMU, + * is enabled. + * + * For a parity error to be reported, the appropriate CPU PARITYFAIL interrupt + * for the current CPU core must be enabled using the interrupt controller API. + * For CPU0, ALT_INT_INTERRUPT_CPU0_PARITYFAIL is asserted if any parity error + * is detected while the other PARITYFAIL interrupts are for parity errors in a + * specific memory. Refer to the interrupt controller API for more details + * about programming the interrupt controller. + * + * In the event of a parity error is detected, the appropriate CPU parity + * interrupt will be raised. CPU parity interrupts are all edge triggered and + * are cleared by acknowledging them in the interrupt controller API. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_parity_enable(void); + +/*! + * Disables parity error detection in the L1 caches. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_parity_disable(void); + +/*! + * Returns \b true when parity error detection is enabled and \b false when it + * is disabled on the current CPU core. + * + * \retval true Parity error detection for L1 caches is + * enabled. + * \retval false Parity error detection for L1 caches is + * disabled. + */ +bool alt_cache_l1_parity_is_enabled(void); + +/*! + * Enables the dynamic branch predictor features on the current CPU core. + * + * This operation enables both the Branch Target Address Cache (BTAC) and + * the Global History Buffer (GHB). Affected caches are automatically + * invalidated before use. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_enable(void); + +/*! + * Disables the dynamic branch predictor features on the current CPU core. + * + * This operation disables both the Branch Target Address Cache (BTAC) and + * the Global History Buffer (GHB). + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_disable(void); + +/*! + * Returns \b true when both the dynamic predictor features are enabled and + * \b false when they are disabled on the current CPU core. + * + * \retval true The L1 branch predictor caches are all enabled. + * \retval false Some or all L1 branch predictor caches are + * disabled. + */ +bool alt_cache_l1_branch_is_enabled(void); + +/*! + * Invalidates the dynamic branch predictor feature caches on the current CPU + * core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void); + +/*! + * Enables the L1 cache data prefetch feature on the current CPU core. + * + * This allows data to be prefetched into the data cache before it is to be + * used. For example in a loop the current iteration may want to preload the + * data which will be used in the next teration. This is done by using the PLD + * instructions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void); + +/*! + * Disables the L1 cache data prefetch feature on the current CPU core. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void); + +/*! + * Returns \b true if the L1 cache data prefetch feature is enabled and + * \b false if it is disabled on the current CPU core. + * + * \retval true The L1 data cache prefetch feature is enabled. + * \retval false The L1 data cache prefetch feature is disabled. + */ +bool alt_cache_l1_prefetch_is_enabled(void); + +/*! + * @} + */ + +/*! + * \addtogroup CACHE_L2 L2 Cache Management API + * + * This API group provides functions to interact with various features of the + * L2 cache on the SoCFPGA. This includes the following features: + * * L2 cache + * * Parity error detection + * * Data prefetching + * * Interrupt Management + * + * \internal + * Additional features that may be implemented in the future: + * * Lockdown + * * Event counter + * \endinternal + * + * The API within this group affects the L2 cache which is visible to all CPUs + * on the system. + * + * With respect to bring-up, the L1 and L2 cache controller setups are fully + * independent. The L2 can be setup at any time, before or after the L1 is setup. + * \internal + * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". + * \endinternal + * + * @{ + */ + +/*! + * Initializes the L2 cache controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_cache_l2_init(void); + +/*! + * Uninitializes the L2 cache controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_cache_l2_uninit(void); + +/*! + * Enables the L2 cache features for data and instruction prefetching. + * + * Prefetching can be enabled or disabled while the L2 cache is enabled. + * \internal + * Source: Use the Prefetch Control Register. + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void); + +/*! + * Disables the L2 cache features for data and instruction prefetching. + * + * Prefetching can be enabled or disabled while the L2 cache is enabled. + * \internal + * Source: Use the Prefetch Control Register. + * \endinternal + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void); + +/*! + * Returns \b true if either L2 cache data or instruction prefetch features are + * enabled and \b false if no prefetching features are enabled. + * + * \retval true The L2 data and instruction prefetch features + * are enabled. + * \retval false Some L2 data and instruction prefetch features + * are disabled. + */ +bool alt_cache_l2_prefetch_is_enabled(void); + +/*! + * Enables parity error detection in the L2 cache. + * + * Ideally parity should be enabled before the L2 cache is enabled. If the + * cache is already enabled, it will first be cleaned and disabled before + * parity is enabled in hardware. Afterwards, the cache will be invalidated and + * enabled. + * + * For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or + * ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is + * done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt + * must be enabled using the interrupt controller API. Refer to the interrupt + * controller API for more details about programming the interrupt controller. + * + * In the event of a parity error is detected, the appropriate L2 cache parity + * interrupt will be raised. To clear the parity interrupt(s), the appropriate + * L2 cache parity interrupt must be cleared by calling + * alt_cache_l2_int_status_clear(). + * + * For ECC support, refer to the ECC related API documentation for more + * information. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_parity_enable(void); + +/*! + * Disables parity error detection in the L2 cache. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_parity_disable(void); + +/*! + * Returns \b true when parity error detection is enabled and \b false when it + * is disabled. + * + * \retval true The L2 cache parity error detection feature is + * enabled. + * \retval false The L2 cache parity error detection feature is + * disabled. + */ +bool alt_cache_l2_parity_is_enabled(void); + +/*! + * Enables the L2 cache. + * + * If the L2 cache is already enabled, nothing is done. Otherwise the entire + * contents of the cache is first invalidated before being enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_enable(void); + +/*! + * Disables the L2 cache. + * + * If the L2 cache is already disabled, nothing is done. Otherwise the entire + * contents of the cache is first cleaned before being disabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_disable(void); + +/*! + * Returns \b true when the L2 cache is enabled and \b false when it is + * disabled. + * + * \retval true The L2 cache is enabled. + * \retval false The L2 cache is disabled. + */ +bool alt_cache_l2_is_enabled(void); + +/*! + * Flushes the L2 cache controller hardware buffers. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_sync(void); + +/*! + * Invalidates the specified contents of the L2 cache for the given memory + * segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be invalidated. + * + * \param length + * The length of the memory segment to be invalidated. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length); + +/*! + * Invalidates th entire contents of the L2 cache. + * + * Normally this is done automatically as part of alt_cache_l2_enable(), but + * in certain circumstances it may be necessary to invalidate it manually. An + * example of this situation is when the address space is remapped and the + * processor accesses memory from the new memory area. + + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_invalidate_all(void); + +/*! + * Cleans the specified contents of the L2 cache for the given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be cleaned. + * + * \param length + * The length of the memory segment to be cleaned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length); + +/*! + * Cleans the entire L2 cache. All L2 cache controller interrupts will be + * temporarily disabled while the clean operation is in progress and restored + * once the it is finished. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_clean_all(void); + +/*! + * Cleans and invalidates the specified contents of the L2 cache for the + * given memory segment. + * + * The memory segment address and length specified must align to the + * characteristics of the cache line. This means the address and length must be + * multiples of the cache line size. To determine the cache line size, use the + * \b ALT_CACHE_LINE_SIZE macro. + * + * \param paddress + * The physical address of the memory segment to be purged. + * + * \param length + * The length of the memory segment to be purged. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The memory segment is invalid. + */ +ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length); + +/*! + * Cleans and invalidates the entire L2 cache. All L2 cache controller + * interrupts will be temporarily disabled while the clean and invalidate + * operation is in progress and restored once the it is finished. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_TMO The memory operation timed out. + */ +ALT_STATUS_CODE alt_cache_l2_purge_all(void); + +/*! + * This type definition enumerates all the interrupt conditions that can be + * generated by the L2 cache controller as register mask values. + */ +enum ALT_CACHE_L2_INTERRUPT_e +{ + /*! Decode error received on the master ports from L3. */ + ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8, + + /*! Slave error received on the master ports from L3. */ + ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7, + + /*! Error on the L2 data RAM read. */ + ALT_CACHE_L2_INTERRUPT_ERRRD = 1 << 6, + + /*! Error on the L2 tag RAM read. */ + ALT_CACHE_L2_INTERRUPT_ERRRT = 1 << 5, + + /*! Error on the L2 data RAM write. */ + ALT_CACHE_L2_INTERRUPT_ERRWD = 1 << 4, + + /*! Error on the L2 tag RAM write. */ + ALT_CACHE_L2_INTERRUPT_ERRWT = 1 << 3, + + /*! Parity error on the L2 data RAM read. */ + ALT_CACHE_L2_INTERRUPT_PARRD = 1 << 2, + + /*! Parity error on the L2 tag RAM read. */ + ALT_CACHE_L2_INTERRUPT_PARRT = 1 << 1, + + /*! Event counter overflow or increment. */ + ALT_CACHE_L2_INTERRUPT_ECNTR = 1 << 0 +}; +typedef enum ALT_CACHE_L2_INTERRUPT_e ALT_CACHE_L2_INTERRUPT_t; + +/*! + * Enables the L2 cache controller interrupts for the specified set of + * condition(s). + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt); + +/*! + * Disables the L2 cache controller interrupts for the specified set of + * condition(s). + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt); + +/*! + * Gets the condition(s) causing the L2 cache controller to interrupt as a + * register mask. + * + * \returns A register mask of the currently asserted and enabled + * conditions resulting in an interrupt being generated. + */ +uint32_t alt_cache_l2_int_status_get(void); + +/*! + * Clears the specified conditon(s) causing the L2 cache controller to + * interrupt as a mask. Condition(s) specified which are not causing an + * interrupt or condition(s) specified which are not enabled are ignored. + * + * \param interrupt + * A register mask of the selected L2 cache controller + * interrupting conditions. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_CACHE_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_clock_group.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_clock_group.h new file mode 100644 index 000000000..ec4a7971f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_clock_group.h @@ -0,0 +1,114 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! + * \file + * + * Contains the definition of an opaque data structure that contains raw + * configuration information for a clock group. + */ + +#ifndef __ALT_CLK_GRP_H__ +#define __ALT_CLK_GRP_H__ + +#include "hwlib.h" +#include "socal/alt_clkmgr.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * This type definition enumerates the clock groups + */ +typedef enum ALT_CLK_GRP_e +{ + ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ + + ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ + + ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ + +} ALT_CLK_GRP_t; + +/*! + * This type definition defines an opaque data structure for holding the + * configuration settings for a complete clock group. + */ +typedef struct ALT_CLK_GROUP_RAW_CFG_s +{ + uint32_t verid; /*!< SoC FPGA version identifier. This field + * encapsulates the silicon identifier and + * version information associated with this + * clock group configuration. It is used to + * assert that this clock group configuration + * is valid for this device. */ + + uint32_t siliid2; /*!< Reserved register - reserved for future + * device IDs or capability flags. */ + + ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */ + + /*! + * This union holds the register values for configuration of the set of + * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator + * identifies the valid clock group union data member. + */ + union ALT_CLK_GROUP_RAW_CFG_u + { + /*! Clock group configuration for Main PLL group. */ + union + { + ALT_CLKMGR_MAINPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */ + } mainpllgrp; + + /*! Clock group configuration for Peripheral PLL group. */ + union + { + ALT_CLKMGR_PERPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */ + } perpllgrp; + + /*! Clock group configuration for SDRAM PLL group. */ + union + { + ALT_CLKMGR_SDRPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */ + } sdrpllgrp; + + } clkgrp; +} ALT_CLK_GROUP_RAW_CFG_t; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_CLK_GRP_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_clock_manager.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_clock_manager.h new file mode 100644 index 000000000..a72ba261a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_clock_manager.h @@ -0,0 +1,1434 @@ +/*! \file + * Contains definitions for the Altera Hardware Libraries Clock Manager + * Application Programming Interface + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_CLK_MGR_H__ +#define __ALT_CLK_MGR_H__ + +#include "hwlib.h" +#include "alt_clock_group.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! \addtogroup CLK_MGR The Clock Manager API + * + * This module defines the Clock Manager API for accessing, configuring, and + * controlling the HPS clock resources. + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition is an opaque type definition for clock frequency values + * in Hz. + */ +typedef uint32_t alt_freq_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the names of the clock and PLL resources + * managed by the Clock Manager. + */ +typedef enum ALT_CLK_e +{ + /* Clock Input Pins */ + ALT_CLK_IN_PIN_OSC1, + /*!< \b OSC_CLK_1_HPS + * External oscillator input: + * * Input Pin + * * Clock source to Main PLL + * * Clock source to SDRAM PLL + * and Peripheral PLL if selected via + * register write + * * Clock source for clock in safe mode + */ + + ALT_CLK_IN_PIN_OSC2, + /*!< \b OSC_CLK_2_HPS + * External Oscillator input: + * * Input Pin + * * Optional clock source to SDRAM PLL + * and Peripheral PLL if selected + * * Typically used for Ethernet + * reference clock + */ + + + /* FPGA Clock Sources External to HPS */ + ALT_CLK_F2H_PERIPH_REF, + /*2C 0 TX */ + ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I2C 0 RX */ + ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I2C 1 TX */ + ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I2C 1 RX */ + ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I2C 2 TX */ + ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I2C 2 RX */ + ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I2C 3 TX */ + ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I2C 3 RX */ + ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */ + ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */ + ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */ + ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */ + ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */ + ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */ + ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */ + ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */ + ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */ + ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */ + ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */ + ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */ + ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */ + ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */ + ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */ + ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */ +} +ALT_DMA_PERIPH_t; + +/*! + * This type enumerates the DMA security state options available. + */ +typedef enum ALT_DMA_SECURITY_e +{ + ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */ + ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */ + ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */ +} +ALT_DMA_SECURITY_t; + +/*! + * This type definition enumerates the DMA event-interrupt resources. + */ +typedef enum ALT_DMA_EVENT_e +{ + ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */ + ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */ + ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */ + ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */ + ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */ + ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */ + ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */ + ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */ + ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */ +} +ALT_DMA_EVENT_t; + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_COMMON_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_dma_program.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_dma_program.h new file mode 100644 index 000000000..66f86352b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_dma_program.h @@ -0,0 +1,951 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +#ifndef __ALT_DMA_PROGRAM_H__ +#define __ALT_DMA_PROGRAM_H__ + +#include "hwlib.h" +#include "alt_dma_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_DMA_PRG DMA Controller Programming API + * + * This API provides functions for dynamically defining and assembling microcode + * programs for execution on the DMA controller. + * + * The microcode program assembly API provides users with the ability to develop + * highly optimized and tailored algorithms for data transfer between SoC FPGA + * IP blocks and/or system memory. + * + * The same microcode program assembly facilities are also used to implement the + * functions found in the HWLIB Common DMA Operations functional API. + * + * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA + * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated + * from used specified system memory. Once a microcode program has been + * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA + * channel thread. The microcode program may be rerun on any DMA channel thread + * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t + * containing the program is maintained. + * + * @{ + */ + +/*! + * This preprocessor declares the DMA channel thread microcode instruction + * cache line width in bytes. It is recommended that the program buffers be + * sized to a multiple of the cache line size. This will allow for the most + * efficient microcode speed and space utilization. + */ +#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32) + +/*! + * This preprocessor declares the DMA channel thread microcode instruction + * cache line count. Thus the total size of the cache is the cache line size + * multipled by the cache line count. Programs larger than the cache size risk + * having a cache miss while executing. + */ +#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16) + +/*! + * This preprocessor definition determines the size of the program buffer + * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate + * size for most DMA microcode programs. If calls within this API are + * reporting out of memory response codes, consider increasing the provisioned + * program buffersize. + * + * To specify another DMA microcode program buffer size, redefine the macro + * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in + * your Makefile. It is recommended that the size be a multiple of the + * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for + * more information. The largest supported buffer size is 65536 bytes. + */ +#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE +#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT) +#endif + +/*! + * This type defines the structure used to assemble and contain a microcode + * program which can be executed by the DMA controller. The internal members + * are undocumented and should not be altered outside of this API. + */ +typedef struct ALT_DMA_PROGRAM_s +{ + uint32_t flag; + + uint16_t buffer_start; + uint16_t code_size; + + uint16_t loop0; + uint16_t loop1; + + uint16_t sar; + uint16_t dar; + + /* + * Add a little extra space so that regardless of where this structure + * sits in memory, a suitable start address can be aligned to the cache + * line stride while providing the requested buffer space. + */ + uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE + + ALT_DMA_PROGRAM_CACHE_LINE_SIZE]; +} +ALT_DMA_PROGRAM_t; + +/*! + * This type definition enumerates the DMA controller register names for use in + * microcode program definition. + */ +typedef enum ALT_DMA_PROGRAM_REG_e +{ + /*! Source Address Register */ + ALT_DMA_PROGRAM_REG_SAR = 0x0, + + /*! Destination Address Register */ + ALT_DMA_PROGRAM_REG_DAR = 0x2, + + /*! Channel Control Register */ + ALT_DMA_PROGRAM_REG_CCR = 0x1 +} +ALT_DMA_PROGRAM_REG_t; + +/*! + * This type definition enumerates the instruction modifier options available + * for use with selected DMA microcode instructions. + * + * The enumerations values are context dependent upon the instruction being + * modified. + * + * For the DMALD[S|B], DMALDP\, DMAST[S|B], and + * DMASTP\ microcode instructions, the enumeration + * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the S option modifier + * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the B + * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies + * that no modifier is present for instructions where use of [S|B] is + * optional. + * + * For the DMAWFP microcode instruction, the enumerations + * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or + * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding + * options \. + */ +typedef enum ALT_DMA_PROGRAM_INST_MOD_e +{ + /*! + * This DMA instruction modifier specifies that no special modifier is + * added to the instruction. + */ + ALT_DMA_PROGRAM_INST_MOD_NONE, + + /*! + * Depending on the DMA microcode instruction modified, this modifier + * specifies S case for a [S|B] or a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_SINGLE, + + /*! + * Depending on the DMA microcode instruction modified, this modifier + * specifies B case for a [S|B] or a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_BURST, + + /*! + * This DMA instruction modifier specifies a \ for a + * \. + */ + ALT_DMA_PROGRAM_INST_MOD_PERIPH +} +ALT_DMA_PROGRAM_INST_MOD_t; + +/*! + * This function initializes a system memory buffer for use as a DMA microcode + * program buffer. This should be the first API call made on the program + * buffer type. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function verifies that the DMA microcode program buffer is no longer + * in use and performs any needed uninitialization steps. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function clears the existing DMA microcode program in the given + * program buffer. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function validate that the given DMA microcode program buffer contains + * a well formed program. If caches are enabled, the program buffer contents + * will be cleaned to RAM. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \retval ALT_E_SUCCESS The given program is well formed. + * \retval ALT_E_ERROR The given program is not well formed. + * \retval ALT_E_TMO The cache operation timed out. + */ +ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm); + +/*! + * This function reports the number bytes incremented for the register + * specified. The purpose is to determine the progress of an ongoing DMA + * transfer. + * + * It is implemented by calculating the difference of the programmed SAR or DAR + * with the current channel SAR or DAR register value. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \param channel + * The channel that the program is running on. + * + * \param reg + * Register to change the value for. Valid for only + * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. + * + * \param current + * The current snapshot value of the register read from the DMA + * channel. + * + * \param progress + * [out] A pointer to a memory location that will be used to store + * the number of bytes transfered. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + * \retval ALT_E_BAD_ARG The specified channel is invalid, the specified + * register is invalid, or the DMAMOV for the + * specified register has not yet been assembled + * in the current program buffer. + */ +ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, + uint32_t current, uint32_t * progress); + +/*! + * This function updates a pre-existing DMAMOV value affecting the SAR or DAR + * registers. This allows for pre-assembled programs that can be used on + * different source and destination addresses. + * + * \param pgm + * A pointer to a DMA program buffer structure. + * + * \param reg + * Register to change the value for. Valid for only + * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. + * + * \param val + * The value to update to. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR Details about error status code. + * \retval ALT_E_BAD_ARG The specified register is invalid or the DMAMOV + * for the specified register has not yet been + * assembled in the current program buffer. + */ +ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t reg, uint32_t val); + +/*! + */ + +/*! + * Assembles a DMAADDH (Add Halfword) instruction into the microcode program + * buffer. This instruction uses 3 bytes of buffer space. + * + * \param pgm + * The DMA program buffer to contain the assembled instruction. + * + * \param addr_reg + * The channel address register (ALT_DMA_PROGRAM_REG_DAR or + * ALT_DMA_PROGRAM_REG_SAR) to add the value to. + * + * \param val + * The 16-bit unsigned value to add to the channel address + * register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAADDH , <16-bit immediate> +ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); + +/*! + * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode + * program buffer. This instruction uses 3 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param addr_reg + * The channel address register (ALT_DMA_PROGRAM_REG_DAR or + * ALT_DMA_PROGRAM_REG_SAR) to add the value to. + * + * \param val + * The 16-bit unsigned value to add to the channel address + * register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAADNH , <16-bit immediate> +ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); + +/*! + * Assembles a DMAEND (End) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAEND +ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode + * program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param periph + * The peripheral to flush. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid peripheral specified. + */ +// Assembler Syntax: DMAFLUSHP +ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMAGO (Go) instruction into the microcode program buffer. This + * instruction uses 6 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param channel + * The stopped channel to act upon. + * + * \param val + * The value to write to the channel program counter register. + * + * \param sec + * The security state for the operation. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel or security specified. + */ +// Assembler Syntax: DMAGO , <32-bit_immediate> [, ns] +ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_CHANNEL_t channel, uint32_t val, + ALT_DMA_SECURITY_t sec); + +/*! + * Assembles a DMAKILL (Kill) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAKILL +ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMALD (Load) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. + */ +// Assembler Syntax: DMALD[S|B] +ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMALDP (Load and notify Peripheral) instruction into the + * microcode program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \param periph + * The peripheral to notify. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral + * specified. + */ +// Assembler Syntax: DMALDP +ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMALP (Loop) instruction into the microcode program buffer. + * This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param iterations + * The number of iterations to run for. Valid values are 1 - 256. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid iterations specified. + * \retval ALT_E_BAD_OPERATION All loop registers are in use. + */ +// Assembler Syntax: DMALP [|] +ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, + uint32_t iterations); + +/*! + * Assembles a DMALPEND (Loop End) instruction into the microcode program + * buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the loop terminator. Only + * ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE + * and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. + * \retval ALT_E_ARG_RANGE Loop size is too large to be supported. + * \retval ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to + * the program buffer before adding this + * DMALPEND instruction. + */ +// Assembler Syntax: DMALPEND[S|B] +ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMALPFE (Loop Forever) instruction into the microcode program + * buffer. No instruction is added to the buffer but a previous DMALPEND to + * create an infinite loop. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMALPFE +ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAMOV (Move) instruction into the microcode program buffer. + * This instruction uses 6 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param chan_reg + * The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR, + * ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy + * the value to. + * + * \param val + * The value to write to the specified register. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid channel register specified. + */ +// Assembler Syntax: DMAMOV , <32-bit_immediate> +ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val); + +/*! + * Assembles a DMANOP (No Operation) instruction into the microcode program + * buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMANOP +ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode + * program buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMARMB +ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMASEV (Send Event) instruction into the microcode program + * buffer. This instruction uses 2 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param evt + * The event to send. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid event specified. + */ +// Assembler Syntax: DMASEV +ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt); + +/*! + * Assembles a DMAST (Store) instruction into the microcode program buffer. + * This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAST[S|B] +ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMASTP (Store and notify Peripheral) instruction into the + * microcode program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and + * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. + * + * \param periph + * The peripheral to notify. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral + * specified. + */ +// Assembler Syntax: DMASTP +ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); + +/*! + * Assembles a DMASTZ (Store Zero) instruction into the microcode program + * buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMASTZ +ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm); + +/*! + * Assembles a DMAWFE (Wait For Event) instruction into the microcode program + * buffer. This instruction uses 2 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param evt + * The event to wait for. + * + * \param invalid + * If invalid is set to true, the instruction will be configured + * to invalidate the instruction cache for the current DMA + * thread. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid event specified. + */ +// Assembler Syntax: DMAWFE [, invalid] +ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_EVENT_t evt, bool invalid); + +/*! + * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode + * program buffer. This instruction uses 2 bytes of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \param periph + * The peripheral to wait on. + * + * \param mod + * The program instruction modifier for the type of transfer. + * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE, + * ALT_DMA_PROGRAM_INST_MOD_BURST, or + * ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + * \retval ALT_E_BAD_ARG Invalid peripheral or instruction modifier + * specified. + */ +// Assembler Syntax: DMAWFP , +ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, + ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod); + +/*! + * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode + * program buffer. This instruction uses 1 byte of buffer space. + * + * \param pgm + * The DMA programm buffer to contain the assembled instruction. + * + * \retval ALT_E_SUCCESS Successful instruction assembly status. + * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. + */ +// Assembler Syntax: DMAWMB +ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm); + +/*! + * \addtogroup DMA_CCR Support for DMAMOV CCR + * + * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the + * dynamic microcode programming of the assembler directive: +\verbatim + +DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA] + [SP] [SC] + [DB<1-16>] [DS<8|16|32|64|128>] [DA] + [DP] [DC] + [ES<8|16|32|64|128>] + +\endverbatim +* with a DMAMOV instruction (see: alt_dma_program_DMAMOV()). +* +* For example the assembler directive: +\verbatim +DMAMOV CCR SB1 SS32 DB1 DS32 +\endverbatim +* would be dynamically programmed with the following API call: +\verbatim +alt_dma_program_DMAMOV( pgm, + ALT_DMA_PROGRAM_REG_CCR, + ( ALT_DMA_CCR_OPT_SB1 + | ALT_DMA_CCR_OPT_SS32 + | ALT_DMA_CCR_OPT_SA_DEFAULT + | ALT_DMA_CCR_OPT_SP_DEFAULT + | ALT_DMA_CCR_OPT_SC_DEFAULT + | ALT_DMA_CCR_OPT_DB1 + | ALT_DMA_CCR_OPT_DS32 + | ALT_DMA_CCR_OPT_DA_DEFAULT + | ALT_DMA_CCR_OPT_DP_DEFAULT + | ALT_DMA_CCR_OPT_DC_DEFAULT + | ALT_DMA_CCR_OPT_ES8 + ) + ); +\endverbatim +* +* Each CCR option category should be specified regardless of whether it +* specifies a custom value or the normal default value (i.e. an +* ALT_DMA_CCR_OPT_*_DEFAULT. +* +* @{ +*/ + +/* + * Source Address {Fixed,Incrementing} + */ +/*! Source Address Fixed address burst. */ +#define ALT_DMA_CCR_OPT_SAF (0 << 0) +/*! Source Address Incrementing address burst. */ +#define ALT_DMA_CCR_OPT_SAI (1 << 0) +/*! Source Address Default value. */ +#define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI + +/* + * Source burst Size (in bits) + */ +/*! Source burst Size of 8 bits. */ +#define ALT_DMA_CCR_OPT_SS8 (0 << 1) +/*! Source burst Size of 16 bits. */ +#define ALT_DMA_CCR_OPT_SS16 (1 << 1) +/*! Source burst Size of 32 bits. */ +#define ALT_DMA_CCR_OPT_SS32 (2 << 1) +/*! Source burst Size of 64 bits. */ +#define ALT_DMA_CCR_OPT_SS64 (3 << 1) +/*! Source burst Size of 128 bits. */ +#define ALT_DMA_CCR_OPT_SS128 (4 << 1) +/*! Source burst Size default bits. */ +#define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8 + +/* + * Source burst Length (in transfer(s)) + */ +/*! Source Burst length of 1 transfer. */ +#define ALT_DMA_CCR_OPT_SB1 (0x0 << 4) +/*! Source Burst length of 2 transfers. */ +#define ALT_DMA_CCR_OPT_SB2 (0x1 << 4) +/*! Source Burst length of 3 transfers. */ +#define ALT_DMA_CCR_OPT_SB3 (0x2 << 4) +/*! Source Burst length of 4 transfers. */ +#define ALT_DMA_CCR_OPT_SB4 (0x3 << 4) +/*! Source Burst length of 5 transfers. */ +#define ALT_DMA_CCR_OPT_SB5 (0x4 << 4) +/*! Source Burst length of 6 transfers. */ +#define ALT_DMA_CCR_OPT_SB6 (0x5 << 4) +/*! Source Burst length of 7 transfers. */ +#define ALT_DMA_CCR_OPT_SB7 (0x6 << 4) +/*! Source Burst length of 8 transfers. */ +#define ALT_DMA_CCR_OPT_SB8 (0x7 << 4) +/*! Source Burst length of 9 transfers. */ +#define ALT_DMA_CCR_OPT_SB9 (0x8 << 4) +/*! Source Burst length of 10 transfers. */ +#define ALT_DMA_CCR_OPT_SB10 (0x9 << 4) +/*! Source Burst length of 11 transfers. */ +#define ALT_DMA_CCR_OPT_SB11 (0xa << 4) +/*! Source Burst length of 12 transfers. */ +#define ALT_DMA_CCR_OPT_SB12 (0xb << 4) +/*! Source Burst length of 13 transfers. */ +#define ALT_DMA_CCR_OPT_SB13 (0xc << 4) +/*! Source Burst length of 14 transfers. */ +#define ALT_DMA_CCR_OPT_SB14 (0xd << 4) +/*! Source Burst length of 15 transfers. */ +#define ALT_DMA_CCR_OPT_SB15 (0xe << 4) +/*! Source Burst length of 16 transfers. */ +#define ALT_DMA_CCR_OPT_SB16 (0xf << 4) +/*! Source Burst length default transfers. */ +#define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1 + +/* + * Source Protection + */ +/*! Source Protection bits for AXI bus ARPROT[2:0]. */ +#define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8) +/*! Source Protection bits default value. */ +#define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0) + +/* + * Source cache + */ +/*! Source Cache bits for AXI bus ARCACHE[2:0]. */ +#define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11) +/*! Source Cache bits default value. */ +#define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0) + +/* + * Destination Address {Fixed,Incrementing} + */ +/*! Destination Address Fixed address burst. */ +#define ALT_DMA_CCR_OPT_DAF (0 << 14) +/*! Destination Address Incrementing address burst. */ +#define ALT_DMA_CCR_OPT_DAI (1 << 14) +/*! Destination Address Default value. */ +#define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI + +/* + * Destination burst Size (in bits) + */ +/*! Destination burst Size of 8 bits. */ +#define ALT_DMA_CCR_OPT_DS8 (0 << 15) +/*! Destination burst Size of 16 bits. */ +#define ALT_DMA_CCR_OPT_DS16 (1 << 15) +/*! Destination burst Size of 32 bits. */ +#define ALT_DMA_CCR_OPT_DS32 (2 << 15) +/*! Destination burst Size of 64 bits. */ +#define ALT_DMA_CCR_OPT_DS64 (3 << 15) +/*! Destination burst Size of 128 bits. */ +#define ALT_DMA_CCR_OPT_DS128 (4 << 15) +/*! Destination burst Size default bits. */ +#define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8 + +/* + * Destination Burst length (in transfer(s)) + */ +/*! Destination Burst length of 1 transfer. */ +#define ALT_DMA_CCR_OPT_DB1 (0x0 << 18) +/*! Destination Burst length of 2 transfers. */ +#define ALT_DMA_CCR_OPT_DB2 (0x1 << 18) +/*! Destination Burst length of 3 transfers. */ +#define ALT_DMA_CCR_OPT_DB3 (0x2 << 18) +/*! Destination Burst length of 4 transfers. */ +#define ALT_DMA_CCR_OPT_DB4 (0x3 << 18) +/*! Destination Burst length of 5 transfers. */ +#define ALT_DMA_CCR_OPT_DB5 (0x4 << 18) +/*! Destination Burst length of 6 transfers. */ +#define ALT_DMA_CCR_OPT_DB6 (0x5 << 18) +/*! Destination Burst length of 7 transfers. */ +#define ALT_DMA_CCR_OPT_DB7 (0x6 << 18) +/*! Destination Burst length of 8 transfers. */ +#define ALT_DMA_CCR_OPT_DB8 (0x7 << 18) +/*! Destination Burst length of 9 transfers. */ +#define ALT_DMA_CCR_OPT_DB9 (0x8 << 18) +/*! Destination Burst length of 10 transfers. */ +#define ALT_DMA_CCR_OPT_DB10 (0x9 << 18) +/*! Destination Burst length of 11 transfers. */ +#define ALT_DMA_CCR_OPT_DB11 (0xa << 18) +/*! Destination Burst length of 12 transfers. */ +#define ALT_DMA_CCR_OPT_DB12 (0xb << 18) +/*! Destination Burst length of 13 transfers. */ +#define ALT_DMA_CCR_OPT_DB13 (0xc << 18) +/*! Destination Burst length of 14 transfers. */ +#define ALT_DMA_CCR_OPT_DB14 (0xd << 18) +/*! Destination Burst length of 15 transfers. */ +#define ALT_DMA_CCR_OPT_DB15 (0xe << 18) +/*! Destination Burst length of 16 transfers. */ +#define ALT_DMA_CCR_OPT_DB16 (0xf << 18) +/*! Destination Burst length default transfers. */ +#define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1 + +/* + * Destination Protection + */ +/*! Destination Protection bits for AXI bus AWPROT[2:0]. */ +#define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22) +/*! Destination Protection bits default value. */ +#define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0) + +/* + * Destination Cache + */ +/*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */ +#define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25) +/*! Destination Cache bits default value. */ +#define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0) + +/* + * Endian Swap size (in bits) + */ +/*! Endian Swap: No swap, 8-bit data. */ +#define ALT_DMA_CCR_OPT_ES8 (0 << 28) +/*! Endian Swap: Swap bytes within 16-bit data. */ +#define ALT_DMA_CCR_OPT_ES16 (1 << 28) +/*! Endian Swap: Swap bytes within 32-bit data. */ +#define ALT_DMA_CCR_OPT_ES32 (2 << 28) +/*! Endian Swap: Swap bytes within 64-bit data. */ +#define ALT_DMA_CCR_OPT_ES64 (3 << 28) +/*! Endian Swap: Swap bytes within 128-bit data. */ +#define ALT_DMA_CCR_OPT_ES128 (4 << 28) +/*! Endian Swap: Default byte swap. */ +#define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8 + +/*! Default CCR register options for a DMAMOV CCR assembler directive. */ +#define ALT_DMA_CCR_OPT_DEFAULT \ + (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \ + ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \ + ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \ + ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \ + ALT_DMA_CCR_OPT_ES8) + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_PROGRAM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_ecc.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_ecc.h new file mode 100644 index 000000000..6e98aa326 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_ecc.h @@ -0,0 +1,445 @@ +/*! \file + * Altera - SoC FPGA ECC Management + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_ECC_H__ +#define __ALT_ECC_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_ECC Error Correcting Code (ECC) Management + * + * This module provides programmatic access and control of the Error-Correcting + * Code (ECC) protection features for the embedded RAM blocks in HPS peripherals. + * + * ECC protection can be enabled or disabled for each of the following HPS + * peripheral embedded RAM blocks: + * * L2 Cache Data RAM + * * On-chip RAM (OCRAM) + * * USB 2.0 OTG Controllers + * * Ethernet Media Access Controllers (EMAC) + * * CAN Controllers + * * NAND Flash Controller + * * Quad SPI (QSPI) Flash Controller + * * SD/MMC Controller + * * DMA Controller + * + * All ECC protected peripherals support detection of single bit, correctable + * errors and double bit, non-correctable errors. + * + * With the exception of L2 cache data RAM, each of the ECC protected memories + * generates single and double bit interrupts to the global interrupt controller + * (GIC) and sets error status condition bits in the System Manager. The L2 cache + * interrupt only generates single and double bit interrupts to the global + * interrupt controller (GIC) - no error status conditions are set in the System + * Manager. + * + * When ECC protection is enabled, RAM data should first be written before ever + * being read. Otherwise the ECC syndrome encoding bits for each memory location + * probably contain random uninitialized data that will result in spurious ECC + * errors. A utility function is provided to guarantee proper initialization is + * performed on a memory block once ECC is enabled. + * + * Fault injection capabilities for single, correctable errors and double, + * non-correctable errors are provided for test purposes. + * @{ + */ + +/******************************************************************************/ +/*! + * This type enumerates the ECC protected RAM blocks embedded in HPS peripherals. + */ +typedef enum ALT_ECC_RAM_ENUM_e +{ + ALT_ECC_RAM_L2_DATA, /*!< L2 Cache Data RAM */ + ALT_ECC_RAM_OCRAM, /*!< On-chip RAM */ + ALT_ECC_RAM_USB0, /*!< USB0 Controller RAM */ + ALT_ECC_RAM_USB1, /*!< USB1 Controller RAM */ + ALT_ECC_RAM_EMAC0, /*!< EMAC0 Receive/Transmit Data FIFO Buffer RAMs */ + ALT_ECC_RAM_EMAC1, /*!< EMAC1 Receive/Transmit Data FIFO Buffer RAMs */ + ALT_ECC_RAM_DMA, /*!< DMA Controller RAM */ + ALT_ECC_RAM_CAN0, /*!< CAN0 RAM */ + ALT_ECC_RAM_CAN1, /*!< CAN1 RAM */ + ALT_ECC_RAM_NAND, /*!< NAND Controller Buffer, Read FIFO, Write FIFO RAMs */ + ALT_ECC_RAM_QSPI, /*!< QSPI Controller RAM */ + ALT_ECC_RAM_SDMMC /*!< SD/MMC Controller Port A and Port B RAMs */ +} ALT_ECC_RAM_ENUM_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the ECC status conditions for each of the HPS + * embedded RAM blocks. + * + * The enumerations serve as masks for the ECC status conditions monitored + * in each of the individual embedded RAM blocks. If ECC protection is enabled on + * the selected RAM block, then a mask bit corresponding to the type of ECC error + * is set to 1 if the error occurs. + * + * Additionally, when any of these ECC error conditions occur, then an ECC interrupt + * signal is asserted. + * + * Interrupt sources are cleared by calling alt_ecc_status_clear(). The ECC + * interrupt sources are enabled automatically when ECC is started. + */ +typedef enum ALT_ECC_ERROR_STATUS_e +{ + + ALT_ECC_ERROR_L2_BYTE_WR = 0x1, /*!< L2 cache ECC protection bits are + * not valid because a cache write + * violated data width and/or + * alignment requirements. + * Interrupt: \b l2_ecc_byte_wr_IRQ + */ + ALT_ECC_ERROR_L2_SERR = 0x2, /*!< L2 Cache + * ECC single bit, correctable error status + * Interrupt: \b l2_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_L2_DERR = 0x4, /*!< L2 Cache + * ECC double bit, non-correctable error status + * Interrupt: \b l2_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_OCRAM_SERR = 0x1, /*!< On-chip RAM + * ECC single bit, correctable error status + * Interrupt: \b ram_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_OCRAM_DERR = 0x2, /*!< On-chip RAM + * ECC double bit, non-correctable error status + * Interrupt: \b ram_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_USB0_SERR = 0x1, /*!< USB0 Controller + * ECC single bit, correctable error status + * Interrupt: \b usb0_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_USB0_DERR = 0x2, /*!< USB0 Controller + * ECC double bit, non-correctable error status + * Interrupt: \b usb0_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_USB1_SERR = 0x1, /*!< USB1 Controller + * ECC single bit, correctable error status + * Interrupt: \b usb1_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_USB1_DERR = 0x2, /*!< USB1 Controller + * ECC double bit, non-correctable error status + * Interrupt: \b usb1_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_EMAC0_TX_FIFO_SERR = 0x1, /*!< EMAC0 Transmit Data FIFO Buffer + * ECC single bit, correctable error status + * Interrupt: \b emac0_tx_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_EMAC0_TX_FIFO_DERR = 0x2, /*!< EMAC0 Transmit Data FIFO Buffer + * ECC double bit, non-correctable error status + * Interrupt: \b emac0_tx_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_EMAC0_RX_FIFO_SERR = 0x4, /*!< EMAC0 Receive Data FIFO Buffer + * ECC single bit, correctable error status + * Interrupt: \b emac0_rx_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_EMAC0_RX_FIFO_DERR = 0x8, /*!< EMAC0 Receive Data FIFO Buffer + * ECC double bit, non-correctable error status + * Interrupt: \b emac0_rx_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_EMAC1_TX_FIFO_SERR = 0x1, /*!< EMAC1 Transmit Data FIFO Buffer + * ECC single bit, correctable error status + * Interrupt: \b emac1_tx_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_EMAC1_TX_FIFO_DERR = 0x2, /*!< EMAC1 Transmit Data FIFO Buffer + * ECC double bit, non-correctable error status + * Interrupt: \b emac1_tx_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_EMAC1_RX_FIFO_SERR = 0x4, /*!< EMAC1 Receive Data FIFO Buffer + * ECC single bit, correctable error status + * Interrupt: \b emac1_rx_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_EMAC1_RX_FIFO_DERR = 0x8, /*!< EMAC1 Receive Data FIFO Buffer + * ECC double bit, non-correctable error status + * Interrupt: \b emac1_rx_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_DMA_SERR = 0x1, /*!< DMA Controller + * ECC single bit, correctable error status + * Interrupt: \b dma_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_DMA_DERR = 0x2, /*!< DMA Controller + * ECC double bit, non-correctable error status + * Interrupt: \b dma_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_CAN0_SERR = 0x1, /*!< CAN0 Controller + * ECC single bit, correctable error status + * Interrupt: \b can0_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_CAN0_DERR = 0x2, /*!< CAN0 Controller + * ECC double bit, non-correctable error status + * Interrupt: \b can0_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_CAN1_SERR = 0x1, /*!< CAN1 Controller + * ECC single bit, correctable error status + * Interrupt: \b can1_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_CAN1_DERR = 0x2, /*!< CAN1 Controller + * ECC double bit, non-correctable error status + * Interrupt: \b can1_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_NAND_BUFFER_SERR = 0x1, /*!< NAND Controller Buffer RAM + * ECC single bit, correctable error status + * Interrupt: \b nande_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_NAND_BUFFER_DERR = 0x2, /*!< NAND Controller Buffer RAM + * ECC double bit, non-correctable error status + * Interrupt: \b nande_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_NAND_WR_FIFO_SERR = 0x4, /*!< NAND Controller Write FIFO + * ECC single bit, correctable error status + * Interrupt: \b nandw_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_NAND_WR_FIFO_DERR = 0x8, /*!< NAND Controller Write FIFO + * ECC double bit, non-correctable error status + * Interrupt: \b nandw_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_NAND_RD_FIFO_SERR = 0x10, /*!< NAND Controller Read FIFO + * ECC single bit, correctable error status + * Interrupt: \b nandr_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_NAND_RD_FIFO_DERR = 0x20, /*!< NAND Controller Read FIFO + * ECC double bit, non-correctable error status + * Interrupt: \b nandr_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_QSPI_SERR = 0x1, /*!< QSPI Controller + * ECC single bit, correctable error status + * Interrupt: \b qspi_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_QSPI_DERR = 0x2, /*!< QSPI Controller + * ECC double bit, non-correctable error status + * Interrupt: \b qspi_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_SDMMC_PORT_A_SERR = 0x1, /*!< SD/MMC Controller Port A + * ECC single bit, correctable error status + * Interrupt: \b sdmmc_porta_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_SDMMC_PORT_A_DERR = 0x2, /*!< SD/MMC Controller Port A + * ECC double bit, non-correctable error status + * Interrupt: \b sdmmc_porta_ecc_uncorrected_IRQ + */ + + ALT_ECC_ERROR_SDMMC_PORT_B_SERR = 0x4, /*!< SD/MMC Controller Port B + * ECC single bit, correctable error status + * Interrupt: \b sdmmc_portb_ecc_corrected_IRQ + */ + ALT_ECC_ERROR_SDMMC_PORT_B_DERR = 0x8 /*!< SD/MMC Controller Port B + * ECC double bit, non-correctable error status + * Interrupt: \b sdmmc_portb_ecc_uncorrected_IRQ + */ +} ALT_ECC_ERROR_STATUS_t; + +/******************************************************************************/ +/*! + * Initializes and starts ECC protection for the specified embedded RAM block. + * + * This function performs any necessary initialization on the embedded RAM block + * for the specified peripheral. The decision on whether to enable ECC protection + * for the peripheral embedded RAM block should be made before commencing normal + * operational use of the peripheral. Ideally, ECC protection for a peripheral + * should be enabled immediately after calling the peripheral's initialization + * function and calling the alt_ecc_init() function designating the applicable + * peripheral embedded RAM block. + * + * For example, the proper initialization sequence for enabling ECC for the QSPI + * controller embedded RAM block is: +\verbatim + alt_qspi_init(); // Initialize the QSPI controller + alt_qspi_enable(); // Enable the QSPI controller. + alt_ecc_start(ALT_ECC_RAM_QSPI); // Bring up ECC protection for QSPI. +\endverbatim + * + * There may be some spurious interrupts that occurs as part of the ECC bring + * up. However at the completion of the ECC bring up, there will be no ECC + * related interrupts pending. + * + * NOTE: The contents of the embedded RAM block are overwritten during + * initialization. This should not normally present a problem as the presumption + * is that this routine is called as part of the peripheral's initialization + * sequence. As well, any special RAM configurations may be overwritten as part + * of the initialization. Particularly, the L2 data RAM may alter the lockdown + * settings. + * + * \param ram_block + * The RAM block to initialize. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The \e ram_block argument is invalid. + */ +ALT_STATUS_CODE alt_ecc_start(const ALT_ECC_RAM_ENUM_t ram_block); + +/******************************************************************************/ +/*! + * Stops and Uninitializes ECC protection for the specified embedded RAM block. + * + * \param ram_block + * The RAM block to uninitialize. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The \e ram_block argument is invalid. + */ +ALT_STATUS_CODE alt_ecc_stop(const ALT_ECC_RAM_ENUM_t ram_block); + +/******************************************************************************/ +/*! + * Returns ALT_E_TRUE if the specified RAM block is enabled for ECC protection and + * ALT_E_FALSE otherwise. + * + * \param ram_block + * The RAM block to check for ECC protection enablement. + * + * \retval ALT_E_TRUE ECC protection is enabled. + * \retval ALT_E_FALSE ECC protection is not enabled. + * \retval ALT_E_BAD_ARG The \e ram_block argument is invalid. + */ +ALT_STATUS_CODE alt_ecc_is_enabled(const ALT_ECC_RAM_ENUM_t ram_block); + +/******************************************************************************/ +/*! + * Returns an ECC error status bit mask for the specified RAM block. + * + * The returned bit mask reflects the ECC status conditions for the specified RAM + * block. + * + * \param ram_block + * The RAM block to return the ECC error status mask for. + * + * \param status + * [out] An ECC status condition bit mask is returned indicating the + * single bit, correctable (SERR) and/or double bit, non-correctable + * error (DERR) conditions set for the specified RAM block. A set (1) + * bit indicates an error detection for the corresponding ECC error + * type mask. + * + * \retval ALT_E_TRUE ECC protection is enabled. + * \retval ALT_E_FALSE ECC protection is not enabled. + * \retval ALT_E_BAD_ARG The \e ram_block argument is invalid. + */ +ALT_STATUS_CODE alt_ecc_status_get(const ALT_ECC_RAM_ENUM_t ram_block, + uint32_t *status); + +/******************************************************************************/ +/*! + * Clears the selected ECC error conditions for the specified RAM block. + * + * A bit mask is returned containing indications of any single bit, correctable + * (SERR) and/or double bit, non-correctable error (DERR) occurrences for the + * specified RAM block. A 1 indicates an error detection of the corresponding + * error type mask position. + * + * \param ram_block + * The RAM block to clear the ECC error condition statuses for. + * + * \param ecc_mask + * A bit mask specification of the ECC error condition statuses (\ref + * ALT_ECC_ERROR_STATUS_t) to clear. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR An invalid \e ecc_mask was specified. + * \retval ALT_E_BAD_ARG Either the \e ram_block or \e ecc_mask argument + * is invalid. + */ +ALT_STATUS_CODE alt_ecc_status_clear(const ALT_ECC_RAM_ENUM_t ram_block, + const uint32_t ecc_mask); + +/******************************************************************************/ +/*! + * Injects a single bit, correctable error into the specified ECC protected RAM + * block for test purposes. This error will occur at the next write to the + * specified RAM block and will remain pending until such time. For RAM blocks + * which have mutliple RAM sub-blocks, all sub-blocks are injected. This + * affects the EMAC0, EMAC1, NAND, and SDMMC. + * + * ECC protection is required to be enabled on the RAM block. + * + * \param ram_block + * The RAM block to inject the ECC error into. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The \e ram_block argument is invalid. + * \retval ALT_E_BAD_OPERATION ECC is not enabled on the specified RAM + * block. + */ +ALT_STATUS_CODE alt_ecc_serr_inject(const ALT_ECC_RAM_ENUM_t ram_block); + +/******************************************************************************/ +/*! + * Injects a double bit, non-correctable error into the specified ECC protected + * RAM block for test purposes. This error will occur at the next write to the + * specified RAM block and will remain pending until such time. For RAM blocks + * which have mutliple RAM sub-blocks, all sub-blocks are injected. This + * affects the EMAC0, EMAC1, NAND, and SDMMC. + * + * ECC protection is required to be enabled on the RAM block. + * + * \param ram_block + * The RAM block to disable ECC protection for. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The \e ram_block argument is invalid. + * \retval ALT_E_BAD_OPERATION ECC is not enabled on the specified RAM + * block. + */ +ALT_STATUS_CODE alt_ecc_derr_inject(const ALT_ECC_RAM_ENUM_t ram_block); + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_ECC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_fpga_manager.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_fpga_manager.h new file mode 100644 index 000000000..75b83f556 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_fpga_manager.h @@ -0,0 +1,1052 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_FPGA_MGR_H__ +#define __ALT_FPGA_MGR_H__ + +#include "hwlib.h" +#include "alt_dma.h" +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup FPGA_MGR The FPGA Manager + * + * This module defines the FPGA Manager API for accessing, configuring, and + * controlling the FPGA fabric and the FPGA/HPS interface. + * + * @{ + */ + + +/*! + * This preprocessor definition determines if DMA support for FPGA programming + * is enabled or not. Enabling DMA support enables the following API: + * * alt_fpga_configure_dma() + * * alt_fpga_istream_configure_dma() + * + * To enable DMA support, define ALT_FPGA_ENABLE_DMA_SUPPORT=1 in the Makefile. + */ +#ifndef ALT_FPGA_ENABLE_DMA_SUPPORT +#define ALT_FPGA_ENABLE_DMA_SUPPORT (0) +#endif + +/*! + * Initializes the FPGA manager. This should be the first API called when using + * the FPGA manager API. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_fpga_init(void); + +/*! + * Uninitializes the FPGA manager + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_fpga_uninit(void); + +/*! + * \addtogroup FPGA_MGR_STATUS FPGA Manager Status and Control + * + * This group provides functions for controlling and determining status of the + * FPGA Manager. + * + * @{ + */ + +/*! + * Instructs the CPU core to acquire control of the FPGA control block. This + * must API must be called before any other API is issued. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Error acquiring control of the FPGA control + * block. This is likely due to another device + * on the system controlling the FPGA control + * block or a repeat call to this API without + * first being released. + */ +ALT_STATUS_CODE alt_fpga_control_enable(void); + +/*! + * Instructs the CPU core to release control of the FPGA control block. This + * API should be called after all FPGA related operations are completed. This + * will allow another device on the system to configure the FPGA. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Failure status. + */ +ALT_STATUS_CODE alt_fpga_control_disable(void); + +/*! + * Returns \b true if the HPS currently has control of the FPGA control block + * and \b false otherwise. + * + * \retval true HPS has control of the FPGA control block. + * \retval false HPS does not have control of the FPGA + * control block. + */ +bool alt_fpga_control_is_enabled(void); + +/*! + * This type definition enumerates the possible states the FPGA can be in at + * any one time. + */ +typedef enum ALT_FPGA_STATE_e +{ + /*! + * FPGA in Power Up Phase. This is the state of the FPGA just after + * powering up. + * + * \internal + * Register documentation calls it "PWR_OFF" which is really a misnomer as + * the FPGA is powered as evident from alt_fpga_mon_status_get() and + * looking at the ALT_FPGA_MON_FPGA_POWER_ON bit. + * \endinternal + */ + ALT_FPGA_STATE_POWER_UP = 0x0, + + /*! + * FPGA in Reset Phase. In this phase, the FPGA resets, clears the FPGA + * configuration RAM bits, tri-states all FPGA user I/O pins, pulls the + * nSTATUS and CONF_DONE pins low, and determines the configuration mode + * by reading the value of the MSEL pins. + */ + ALT_FPGA_STATE_RESET = 0x1, + + /*! + * FPGA in Configuration Phase. This state represents the phase when the + * configuration bitstream is loaded into the FPGA fabric. The + * configuration phase is complete after the FPGA has received all the + * configuration data. + */ + ALT_FPGA_STATE_CFG = 0x2, + + /*! + * FPGA in Initialization Phase. In this state the FPGA prepares to enter + * User Mode. In Configuration via PCI Express (CVP), this state indicates + * I/O configuration has completed. + */ + ALT_FPGA_STATE_INIT = 0x3, + + /*! + * FPGA in User Mode. In this state, the FPGA performs the function loaded + * during the configuration phase. The FPGA user I/O are functional as + * determined at design time. + */ + ALT_FPGA_STATE_USER_MODE = 0x4, + + /*! + * FPGA state has not yet been determined. This only occurs briefly after + * reset. + */ + ALT_FPGA_STATE_UNKNOWN = 0x5, + + /*! + * FPGA is powered off. + * + * \internal + * This is a software only state which is determined by + * alt_fpga_mon_status_get() and looking at the ALT_FPGA_MON_FPGA_POWER_ON + * bit. The hardware register sourced for ALT_FPGA_STATE_t is only 3 bits + * wide so this will never occur in hardware. + * \endinternal + */ + ALT_FPGA_STATE_POWER_OFF = 0xF + +} ALT_FPGA_STATE_t; + +/*! + * Returns the current operational state of the FPGA fabric. + * + * \returns The current operational state of the FPGA. + */ +ALT_FPGA_STATE_t alt_fpga_state_get(void); + +/*! + * This type definition enumerates the monitored status conditions for the FPGA + * Control Block (CB). + */ +typedef enum ALT_FPGA_MON_STATUS_e +{ + /*! + * 0 if the FPGA is in Reset Phase or if the FPGA detected an error during + * the Configuration Phase. + */ + ALT_FPGA_MON_nSTATUS = 0x0001, + + /*! + * 0 during the FPGA Reset Phase and 1 when the FPGA Configuration Phase is + * done. + */ + ALT_FPGA_MON_CONF_DONE = 0x0002, + + /*! + * 0 during the FPGA Configuration Phase and 1 when the FPGA Initialization + * Phase is done. + */ + ALT_FPGA_MON_INIT_DONE = 0x0004, + + /*! + * CRC error indicator. A 1 indicates that the FPGA detected a CRC error + * while in User Mode. + */ + ALT_FPGA_MON_CRC_ERROR = 0x0008, + + /*! + * Configuration via PCIe (CVP) Done indicator. A 1 indicates that CVP is + * done. + */ + ALT_FPGA_MON_CVP_CONF_DONE = 0x0010, + + /*! + * Partial Reconfiguration ready indicator. A 1 indicates that the FPGA is + * ready to receive partial reconfiguration or external scrubbing data. + */ + ALT_FPGA_MON_PR_READY = 0x0020, + + /*! + * Partial Reconfiguration error indicator. A 1 indicates that the FPGA + * detected an error during partial reconfiguration or external scrubbing. + */ + ALT_FPGA_MON_PR_ERROR = 0x0040, + + /*! + * Partial Reconfiguration done indicator. A 1 indicates partial + * reconfiguration or external scrubbing is done. + */ + ALT_FPGA_MON_PR_DONE = 0x0080, + + /*! + * Value of the nCONFIG pin. This can be pulled-down by the FPGA in this + * device or logic external to this device connected to the nCONFIG pin. + * See the description of the nCONFIG field in this register to understand + * when the FPGA in this device pulls-down the nCONFIG pin. Logic external + * to this device pulls-down the nCONFIG pin to put the FPGA into the Reset + * Phase. + */ + ALT_FPGA_MON_nCONFIG_PIN = 0x0100, + + /*! + * Value of the nSTATUS pin. This can be pulled-down by the FPGA in this + * device or logic external to this device connected to the nSTATUS pin. + * See the description of the nSTATUS field in this register to understand + * when the FPGA in this device pulls-down the nSTATUS pin. Logic external + * to this device pulls-down the nSTATUS pin during Configuration Phase or + * Initialization Phase if it detected an error. + */ + ALT_FPGA_MON_nSTATUS_PIN = 0x0200, + + /*! + * Value of the CONF_DONE pin. This can be pulled-down by the FPGA in this + * device or logic external to this device connected to the CONF_DONE pin. + * See the description of the CONF_DONE field in this register to + * understand when the FPGA in this device pulls-down the CONF_DONE pin. + * See FPGA documentation to determine how logic external to this device + * drives CONF_DONE. + */ + ALT_FPGA_MON_CONF_DONE_PIN = 0x0400, + + /*! + * FPGA powered on indicator. + */ + ALT_FPGA_MON_FPGA_POWER_ON = 0x0800, + +} ALT_FPGA_MON_STATUS_t; + +/*! + * Returns the FPGA Control Block monitor status conditions. + * + * This function returns the current value of the FPGA Control Block monitor + * status conditions. + * + * \returns The current values of the FPGA Control Block monitor status + * conditions as defined by the \ref ALT_FPGA_MON_STATUS_t mask + * bits. If the corresponding bit is set then the condition is + * asserted. + * + * \internal + * Use the Raw Interrupt Status Register \b hps::fpgamgrregs::mon::gpio_ext_porta + * to retrieve the monitor status conditions. + * \endinternal + */ +uint32_t alt_fpga_mon_status_get(void); + +/*! + * Assert and hold the FPGA in reset. + * + * This function asserts and holds the FPGA in reset. Any FPGA configuration is + * cleared. The FPGA must be reconfigured to resume operation. + * + * The FPGA is reset by the assertion of the nCONFIG signal. The signal remains + * asserted until alt_fgpa_reset_deassert() is called. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_FPGA_PWR_OFF FPGA is not powered on. + * \retval ALT_E_FPGA_NO_SOC_CTRL SoC software is not in control of the + * FPGA. Use alt_fpga_control_enable() to + * gain control. + */ +ALT_STATUS_CODE alt_fgpa_reset_assert(void); + +/*! + * Deassert and release the FPGA from reset. + * + * This function deasserts the FPGA from reset. The FPGA must be reconfigured to + * resume operation. + * + * The FPGA is reset by the deassertion of the nCONFIG signal. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_FPGA_PWR_OFF FPGA is not powered on. + * \retval ALT_E_FPGA_NO_SOC_CTRL SoC software is not in control of the + * FPGA. Use alt_fpga_control_enable() to + * gain control. + */ +ALT_STATUS_CODE alt_fgpa_reset_deassert(void); + +/*! + * @} + */ + +/*! + * \addtogroup FPGA_MGR_CFG FPGA Configuration + * + * This functional group provides the following services: + * * Determination of the FPGA configuration mode. + * * Software control for full configuration of the FPGA. + * * Software control for partial reconfiguration of the FPGA \e (Future). + * + * @{ + */ + +/*! + * This type definition enumerates the available modes for configuring the + * FPGA. + */ +typedef enum ALT_FPGA_CFG_MODE_e +{ + /*! + * 16-bit Passive Parallel with Fast Power on Reset Delay; No AES + * Encryption; No Data Compression. CDRATIO must be programmed to x1. + */ + ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC = 0x0, + + /*! + * 16-bit Passive Parallel with Fast Power on Reset Delay; With AES + * Encryption; No Data Compression. CDRATIO must be programmed to x4. + */ + ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC = 0x1, + + /*! + * 16-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; + * With Data Compression. CDRATIO must be programmed to x8. + */ + ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC = 0x2, + + /*! + * 16-bit Passive Parallel with Slow Power on Reset Delay; No AES + * Encryption; No Data Compression. CDRATIO must be programmed to x1. + */ + ALT_FPGA_CFG_MODE_PP16_SLOW_NOAES_NODC = 0x4, + + /*! + * 16-bit Passive Parallel with Slow Power on Reset Delay; With AES + * Encryption; No Data Compression. CDRATIO must be programmed to x4. + */ + ALT_FPGA_CFG_MODE_PP16_SLOW_AES_NODC = 0x5, + + /*! + * 16-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; + * With Data Compression. CDRATIO must be programmed to x8. + */ + ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC = 0x6, + + /*! + * 32-bit Passive Parallel with Fast Power on Reset Delay; No AES + * Encryption; No Data Compression. CDRATIO must be programmed to x1. + */ + ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC = 0x8, + + /*! + * 32-bit Passive Parallel with Fast Power on Reset Delay; With AES + * Encryption; No Data Compression. CDRATIO must be programmed to x4. + */ + ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC = 0x9, + + /*! + * 32-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; + * With Data Compression. CDRATIO must be programmed to x8. + */ + ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC = 0xa, + + /*! + * 32-bit Passive Parallel with Slow Power on Reset Delay; No AES + * Encryption; No Data Compression. CDRATIO must be programmed to x1. + */ + ALT_FPGA_CFG_MODE_PP32_SLOW_NOAES_NODC = 0xc, + + /*! + * 32-bit Passive Parallel with Slow Power on Reset Delay; With AES + * Encryption; No Data Compression. CDRATIO must be programmed to x4. + */ + ALT_FPGA_CFG_MODE_PP32_SLOW_AES_NODC = 0xd, + + /*! + * 32-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; + * With Data Compression. CDRATIO must be programmed to x8. + */ + ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC = 0xe, + + /*! + * Unknown FPGA Configuration Mode. + */ + ALT_FPGA_CFG_MODE_UNKNOWN = 0x20, + +} ALT_FPGA_CFG_MODE_t; + +/*! + * Gets the FPGA configuration mode currently in effect. + * + * Presently, the FPGA configuration mode is statically set by the external MSEL + * pin values and cannot be programmatically overridden by HPS software. + * + * \returns The current FPGA configuration mode as determined by the MSEL + * pin values. + */ +ALT_FPGA_CFG_MODE_t alt_fpga_cfg_mode_get(void); + +/*! + * Sets the FPGA configuration mode. + * + * Presently, the FPGA configuration mode is statically set by the external + * MSEL pin values and cannot be programmatically overridden by HPS software. + * This function should always return ALT_E_ERROR at least for Hammerhead-P. + * This may change with future SoCFPGA devices. + * + * \param cfg_mode + * The desired FPGA configuration mode. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Failed to set the FPGA configuration mode. + * + * \internal + * This should set the fpgamgrregs::stat::msel. The full configuration reads + * this to program the fpgamgrregs::ctrl with the appropriate parameters + * decoded from msel. + * \endinternal + */ +ALT_STATUS_CODE alt_fpga_cfg_mode_set(ALT_FPGA_CFG_MODE_t cfg_mode); + +/*! + * Type definition for the callback function prototype used by the FPGA Manager + * to read configuration bitstream data from a user defined input source + * stream. + * + * The purpose of this callback function declaration is to provide a prototype + * for a user defined method of sequentially reading FPGA configuration + * bitstream data from an arbitrary input source. Example input sources include + * a file resident on a file system, a network stream socket, or a fixed + * address block in flash memory. The only requirement on the input source is + * that it is capable of supplying consecutive blocks of data of the requested + * size from the FPGA configuration bitstream as demanded by the FPGA Manager. + * + * During FPGA configuration, the FPGA Manager periodically calls the user + * defined callback function to fetch the next \e buf_len consecutive + * configuration data bytes from the user defined input stream. The callback + * function fills the FPGA Manager supplied buffer \e buf with up to the next + * \e buf_len bytes of configuration bitsteam data as read from the input + * source stream. The callback function returns the number of configuration + * bytes read into \e buf or 0 upon reaching the end of the configuration + * bitstream data. + * + * If an error occurs on the configuration bitstream input source, then the + * callback function should return an error code value less than 0. + * + * \param buf + * A pointer to a buffer to fill with FPGA configuration bitstream + * data bytes. + * + * \param buf_len + * The length of the input buffer \e buf in bytes. The number of + * FPGA configuration bitstream data bytes copied into \e buf + * should not exceed \e buf_len. + * + * \param user_data + * A 32-bit data word for passing user defined data. The content + * of this parameter is user defined. The FPGA Manager merely + * forwards the \e user_data value when it invokes the callback. + * + * \retval >0 The number of bytes returned in buf. + * \retval =0 The end of the input stream has been reached. + * \retval <0 An error occurred on the input stream. + */ +typedef int32_t (*alt_fpga_istream_t)(void* buf, size_t buf_len, void* user_data); + +/*! + * \addtogroup FPGA_MGR_CFG_FULL FPGA Full Configuration + * + * These functions manage full configuration of the FPGA fabric from HPS + * software. + * + * @{ + */ + +/*! + * Perform a full configuration of the FPGA from the specified configuration + * bitstream located in addressable memory. + * + * Due to the nature of FPGA configuration, there may be intermittent and + * recoverable errors during the process. When the API returns ALT_E_FPGA_CFG, + * it is advisable to retry configuration up to 5 times. If the error still + * persists, there may be an unrecoverable configuration error or a problem + * with configuration image bitstream data. + * + * \internal + * Source: FPGA Manager NPP, section 4.2.1.3 "Error handling and corrupted + * configuration file" + * \endinternal + * + * \param cfg_buf + * A pointer to a buffer containing FPGA configuration bitstream + * data. + * + * \param cfg_buf_len + * The length of the configuration bitstream data in bytes. + * + * \retval ALT_E_SUCCESS FPGA configuration was successful. + * \retval ALT_E_FPGA_CFG FPGA configuration error detected. + * \retval ALT_E_FPGA_CRC FPGA CRC error detected. + * \retval ALT_E_FPGA_PWR_OFF FPGA is not powered on. + * \retval ALT_E_FPGA_NO_SOC_CTRL SoC software is not in control of the + * FPGA. Use alt_fpga_control_enable() to + * gain control. + */ +ALT_STATUS_CODE alt_fpga_configure(const void* cfg_buf, + size_t cfg_buf_len); + +#if ALT_FPGA_ENABLE_DMA_SUPPORT + +/*! + * Perform a full configuration of the FPGA from the specified configuration + * bitstream located in addressable memory using the DMA engine. Using DMA can + * have a large performance benefit in FPGA programming time. + * + * Due to the nature of FPGA configuration, there may be intermittent and + * recoverable errors during the process. When the API returns ALT_E_FPGA_CFG, + * it is advisable to retry configuration up to 5 times. If the error still + * persists, there may be an unrecoverable configuration error or a problem + * with configuration image bitstream data. + * + * \internal + * Source: FPGA Manager NPP, section 4.2.1.3 "Error handling and corrupted + * configuration file" + * \endinternal + * + * \param cfg_buf + * A pointer to a buffer containing FPGA configuration bitstream + * data. + * + * \param cfg_buf_len + * The length of the configuration bitstream data in bytes. + * + * \retval ALT_E_SUCCESS FPGA configuration was successful. + * \retval ALT_E_FPGA_CFG FPGA configuration error detected. + * \retval ALT_E_FPGA_CRC FPGA CRC error detected. + * \retval ALT_E_FPGA_PWR_OFF FPGA is not powered on. + * \retval ALT_E_FPGA_NO_SOC_CTRL SoC software is not in control of the + * FPGA. Use alt_fpga_control_enable() to + * gain control. + * \retval ALT_E_BAD_ARG The user provided buffer is unaligned + * to the 32-bit boundary. + */ + +ALT_STATUS_CODE alt_fpga_configure_dma(const void* cfg_buf, + size_t cfg_buf_len, + ALT_DMA_CHANNEL_t dma_channel); + +#endif + +/*! + * Perform a full configuration of the FPGA from the user defined configuration + * bitstream input source. + * + * Due to the nature of FPGA configuration, there may be intermittent and + * recoverable errors during the process. When the API returns ALT_E_FPGA_CFG, + * it is advisable to retry configuration up to 5 times. If the error still + * persists, there may be an unrecoverable configuration error or a problem + * with configuration image bitstream data. + * + * \internal + * Source: FPGA Manager NPP, section 4.2.1.3 "Error handling and corrupted + * configuration file" + * \endinternal + * + * \param cfg_stream + * A pointer to a callback function used to consecutively read + * configuration bitstream data from a user defined input stream. + * + * \param user_data + * A 32-bit user defined data word. The content of this parameter + * is user defined. The FPGA Manager merely forwards the \e + * user_data value when it invokes the \e cfg_stream callback. + * + * \retval ALT_E_SUCCESS FPGA configuration FPGA was successful. + * \retval ALT_E_FPGA_CFG FPGA configuration error detected. + * \retval ALT_E_FPGA_CRC FPGA CRC error detected. + * \retval ALT_E_FPGA_CFG_STM An error occurred on the FPGA + * configuration bitstream input source. + * \retval ALT_E_FPGA_PWR_OFF FPGA is not powered on. + * \retval ALT_E_FPGA_NO_SOC_CTRL SoC software is not in control of the + * FPGA. Use alt_fpga_control_enable() to + * gain control. + */ +ALT_STATUS_CODE alt_fpga_istream_configure(alt_fpga_istream_t cfg_stream, + void * user_data); + +#if ALT_FPGA_ENABLE_DMA_SUPPORT + +/*! + * Perform a full configuration of the FPGA from the user defined configuration + * bitstream input source using the DMA engine. Using DMA can have a large + * performance benefit in FPGA programming time. + * + * Due to the nature of FPGA configuration, there may be intermittent and + * recoverable errors during the process. When the API returns ALT_E_FPGA_CFG, + * it is advisable to retry configuration up to 5 times. If the error still + * persists, there may be an unrecoverable configuration error or a problem + * with configuration image bitstream data. + * + * \internal + * Source: FPGA Manager NPP, section 4.2.1.3 "Error handling and corrupted + * configuration file" + * \endinternal + * + * \param cfg_stream + * A pointer to a callback function used to consecutively read + * configuration bitstream data from a user defined input stream. + * + * \param user_data + * A 32-bit user defined data word. The content of this parameter + * is user defined. The FPGA Manager merely forwards the \e + * user_data value when it invokes the \e cfg_stream callback. + * + * \retval ALT_E_SUCCESS FPGA configuration FPGA was successful. + * \retval ALT_E_FPGA_CFG FPGA configuration error detected. + * \retval ALT_E_FPGA_CRC FPGA CRC error detected. + * \retval ALT_E_FPGA_CFG_STM An error occurred on the FPGA + * configuration bitstream input source. + * \retval ALT_E_FPGA_PWR_OFF FPGA is not powered on. + * \retval ALT_E_FPGA_NO_SOC_CTRL SoC software is not in control of the + * FPGA. Use alt_fpga_control_enable() to + * gain control. + * \retval ALT_E_BAD_ARG The user provided buffer is unaligned + * to the 32-bit boundary. + */ +ALT_STATUS_CODE alt_fpga_istream_configure_dma(alt_fpga_istream_t cfg_stream, + void * user_data, + ALT_DMA_CHANNEL_t dma_channel); + +#endif + +/*! + * @} + */ + +/*! + * @} + */ + +/*! + * \addtogroup FPGA_MGR_INT FPGA Manager Interrupt Control + * + * The functions in this group provide management of interrupts originating + * from the FPGA Manager. + * + * The following interrupt request (IRQ) signal is sourced from the FPGA + * Manager: + * + * * \b fpga_man_IRQ - FPGA Manager control block interrupt output. Provides + * monitoring of the configuration and operational status + * of the FPGA. The interrupt signal assertion value is + * the logical \e OR of twelve sources that monitor the + * status of the FPGA control block (CB). The twelve FPGA + * CB interrupt sources are enumerated and described by the + * type \ref ALT_FPGA_MON_STATUS_t. + * + * Each FPGA monitor status condition may be individually + * disabled/enabled as a contributor to the determination + * of the \b fpga_man_IRQ assertion status. + * + * The \b fpga_man_IRQ and its contributing FPGA monitor + * status conditions are treated as a level sensitive + * interrupt. As as consequence, there are no explicit + * functions to explicitly clear an asserted FPGA monitor + * status conditions. + * + * @{ + */ + +/*! + * Disable the \b fpga_man_IRQ interrupt signal source monitor status + * condition(s). + * + * This function disables one or more of the monitor status conditions as + * contributors to the \b fpga_man_IRQ interrupt signal state. + * + * NOTE: A set bit for a monitor status condition in the mask value does not + * have the effect of enabling it as a contributor to the \b fpga_man_IRQ + * interrupt signal state. The function alt_fpga_man_irq_enable() is used to + * enable monitor status source condition(s). + * + * \param mon_stat_mask + * Specifies the monitor status conditions to disable as interrupt + * source contributors. \e mon_stat_mask is a mask of logically + * OR'ed ALT_FPGA_MON_STATUS_t values that designate the monitor + * status conditions to disable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_BAD_ARG The \e mon_stat_mask argument contains an + * unknown monitor status value. + */ +ALT_STATUS_CODE alt_fpga_man_irq_disable(ALT_FPGA_MON_STATUS_t mon_stat_mask); + +/*! + * Enable the \b fpga_man_IRQ interrupt signal source monitor status + * condition(s). + * + * This function enables one or more of the monitor status conditions as + * contributors to the \b fpga_man_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any monitor status condition in the mask value does + * not have the effect of disabling it as a contributor to the \b fpga_man_IRQ + * interrupt signal state. The function alt_fpga_man_irq_disable() is used to + * disable monitor status source condition(s). + * + * \param mon_stat_mask + * Specifies the monitor status conditions to enable as interrupt + * source contributors. \e mon_stat_mask is a mask of logically + * OR'ed ALT_FPGA_MON_STATUS_t values that designate the monitor + * conditions to enable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_BAD_ARG The \e mon_stat_mask argument contains an + * unknown monitor status value. + */ +ALT_STATUS_CODE alt_fpga_man_irq_enable(ALT_FPGA_MON_STATUS_t mon_stat_mask); + +/*! + * @} + */ + +/*! + * \addtogroup FPGA_MGR_GPIO SoC to FPGA General Purpose I/O Signals + * + * These functions provide a simple, low-latency, low-performance signal + * interface between the SoC and the FPGA. There is a General Purpose Output + * (GPO) register that provides a path to drive up to 32 signals from the SoC + * to the FPGA. There is a General Purpose Input (GPI) register that provides + * a path to read up to 32 signals driven from the FPGA to the SoC. + * + * @{ + */ + +/*! + * This type definition enumerates the signal mask selections for the General + * Purpose Input (GPI) signals driven from the FPGA to the SoC. + */ +typedef enum ALT_FPGA_GPI_e +{ + /*! Signal driven from the FPGA fabric on f2s_gp[0] */ + ALT_FPGA_GPI_0 = (int32_t)(1UL << 0), + + /*! Signal driven from the FPGA fabric on f2s_gp[1] */ + ALT_FPGA_GPI_1 = (int32_t)(1UL << 1), + + /*! Signal driven from the FPGA fabric on f2s_gp[2] */ + ALT_FPGA_GPI_2 = (int32_t)(1UL << 2), + + /*! Signal driven from the FPGA fabric on f2s_gp[3] */ + ALT_FPGA_GPI_3 = (int32_t)(1UL << 3), + + /*! Signal driven from the FPGA fabric on f2s_gp[4] */ + ALT_FPGA_GPI_4 = (int32_t)(1UL << 4), + + /*! Signal driven from the FPGA fabric on f2s_gp[5] */ + ALT_FPGA_GPI_5 = (int32_t)(1UL << 5), + + /*! Signal driven from the FPGA fabric on f2s_gp[6] */ + ALT_FPGA_GPI_6 = (int32_t)(1UL << 6), + + /*! Signal driven from the FPGA fabric on f2s_gp[7] */ + ALT_FPGA_GPI_7 = (int32_t)(1UL << 7), + + /*! Signal driven from the FPGA fabric on f2s_gp[8] */ + ALT_FPGA_GPI_8 = (int32_t)(1UL << 8), + + /*! Signal driven from the FPGA fabric on f2s_gp[9] */ + ALT_FPGA_GPI_9 = (int32_t)(1UL << 9), + + /*! Signal driven from the FPGA fabric on f2s_gp[10] */ + ALT_FPGA_GPI_10 = (int32_t)(1UL << 10), + + /*! Signal driven from the FPGA fabric on f2s_gp[11] */ + ALT_FPGA_GPI_11 = (int32_t)(1UL << 11), + + /*! Signal driven from the FPGA fabric on f2s_gp[12] */ + ALT_FPGA_GPI_12 = (int32_t)(1UL << 12), + + /*! Signal driven from the FPGA fabric on f2s_gp[13] */ + ALT_FPGA_GPI_13 = (int32_t)(1UL << 13), + + /*! Signal driven from the FPGA fabric on f2s_gp[14] */ + ALT_FPGA_GPI_14 = (int32_t)(1UL << 14), + + /*! Signal driven from the FPGA fabric on f2s_gp[15] */ + ALT_FPGA_GPI_15 = (int32_t)(1UL << 15), + + /*! Signal driven from the FPGA fabric on f2s_gp[16] */ + ALT_FPGA_GPI_16 = (int32_t)(1UL << 16), + + /*! Signal driven from the FPGA fabric on f2s_gp[17] */ + ALT_FPGA_GPI_17 = (int32_t)(1UL << 17), + + /*! Signal driven from the FPGA fabric on f2s_gp[18] */ + ALT_FPGA_GPI_18 = (int32_t)(1UL << 18), + + /*! Signal driven from the FPGA fabric on f2s_gp[19] */ + ALT_FPGA_GPI_19 = (int32_t)(1UL << 19), + + /*! Signal driven from the FPGA fabric on f2s_gp[20] */ + ALT_FPGA_GPI_20 = (int32_t)(1UL << 20), + + /*! Signal driven from the FPGA fabric on f2s_gp[21] */ + ALT_FPGA_GPI_21 = (int32_t)(1UL << 21), + + /*! Signal driven from the FPGA fabric on f2s_gp[22] */ + ALT_FPGA_GPI_22 = (int32_t)(1UL << 22), + + /*! Signal driven from the FPGA fabric on f2s_gp[23] */ + ALT_FPGA_GPI_23 = (int32_t)(1UL << 23), + + /*! Signal driven from the FPGA fabric on f2s_gp[24] */ + ALT_FPGA_GPI_24 = (int32_t)(1UL << 24), + + /*! Signal driven from the FPGA fabric on f2s_gp[25] */ + ALT_FPGA_GPI_25 = (int32_t)(1UL << 25), + + /*! Signal driven from the FPGA fabric on f2s_gp[26] */ + ALT_FPGA_GPI_26 = (int32_t)(1UL << 26), + + /*! Signal driven from the FPGA fabric on f2s_gp[27] */ + ALT_FPGA_GPI_27 = (int32_t)(1UL << 27), + + /*! Signal driven from the FPGA fabric on f2s_gp[28] */ + ALT_FPGA_GPI_28 = (int32_t)(1UL << 28), + + /*! Signal driven from the FPGA fabric on f2s_gp[29] */ + ALT_FPGA_GPI_29 = (int32_t)(1UL << 29), + + /*! Signal driven from the FPGA fabric on f2s_gp[30] */ + ALT_FPGA_GPI_30 = (int32_t)(1UL << 30), + + /*! Signal driven from the FPGA fabric on f2s_gp[31] */ + ALT_FPGA_GPI_31 = (int32_t)(1UL << 31) + +} ALT_FPGA_GPI_t; + +/*! + * Reads the General Purpose Input (GPI) register value. + * + * Returns the GPI register value that is the masked selection of the 32 \b + * f2s_gp signal values driven by the FPGA. The \e mask may be defined by the + * logical OR of \ref ALT_FPGA_GPI_t values. + * + * NOTE: If the FPGA is not in User Mode then the value of this register + * undefined. + * + * \param mask + * The set of signals (where mask bits equal one) to read. Other + * signals values (where mask bits equal zero) are returned as 0. + * + * \returns Returns the GPI register value that is the masked selection of + * the 32 \b f2s_gp signals from the FPGA. + */ +uint32_t alt_fpga_gpi_read(uint32_t mask); + +/*! + * This type definition enumerates the signal mask selections for the General + * Purpose Output (GPO) signals driven from the SoC to the FPGA. + */ +typedef enum ALT_FPGA_GPO_e +{ + /*! Signal driven from the FPGA fabric on s2f_gp[0] */ + ALT_FPGA_GPO_0 = (int32_t)(1UL << 0), + + /*! Signal driven from the FPGA fabric on s2f_gp[1] */ + ALT_FPGA_GPO_1 = (int32_t)(1UL << 1), + + /*! Signal driven from the FPGA fabric on s2f_gp[2] */ + ALT_FPGA_GPO_2 = (int32_t)(1UL << 2), + + /*! Signal driven from the FPGA fabric on s2f_gp[3] */ + ALT_FPGA_GPO_3 = (int32_t)(1UL << 3), + + /*! Signal driven from the FPGA fabric on s2f_gp[4] */ + ALT_FPGA_GPO_4 = (int32_t)(1UL << 4), + + /*! Signal driven from the FPGA fabric on s2f_gp[5] */ + ALT_FPGA_GPO_5 = (int32_t)(1UL << 5), + + /*! Signal driven from the FPGA fabric on s2f_gp[6] */ + ALT_FPGA_GPO_6 = (int32_t)(1UL << 6), + + /*! Signal driven from the FPGA fabric on s2f_gp[7] */ + ALT_FPGA_GPO_7 = (int32_t)(1UL << 7), + + /*! Signal driven from the FPGA fabric on s2f_gp[8] */ + ALT_FPGA_GPO_8 = (int32_t)(1UL << 8), + + /*! Signal driven from the FPGA fabric on s2f_gp[9] */ + ALT_FPGA_GPO_9 = (int32_t)(1UL << 9), + + /*! Signal driven from the FPGA fabric on s2f_gp[10] */ + ALT_FPGA_GPO_10 = (int32_t)(1UL << 10), + + /*! Signal driven from the FPGA fabric on s2f_gp[11] */ + ALT_FPGA_GPO_11 = (int32_t)(1UL << 11), + + /*! Signal driven from the FPGA fabric on s2f_gp[12] */ + ALT_FPGA_GPO_12 = (int32_t)(1UL << 12), + + /*! Signal driven from the FPGA fabric on s2f_gp[13] */ + ALT_FPGA_GPO_13 = (int32_t)(1UL << 13), + + /*! Signal driven from the FPGA fabric on s2f_gp[14] */ + ALT_FPGA_GPO_14 = (int32_t)(1UL << 14), + + /*! Signal driven from the FPGA fabric on s2f_gp[15] */ + ALT_FPGA_GPO_15 = (int32_t)(1UL << 15), + + /*! Signal driven from the FPGA fabric on s2f_gp[16] */ + ALT_FPGA_GPO_16 = (int32_t)(1UL << 16), + + /*! Signal driven from the FPGA fabric on s2f_gp[17] */ + ALT_FPGA_GPO_17 = (int32_t)(1UL << 17), + + /*! Signal driven from the FPGA fabric on s2f_gp[18] */ + ALT_FPGA_GPO_18 = (int32_t)(1UL << 18), + + /*! Signal driven from the FPGA fabric on s2f_gp[19] */ + ALT_FPGA_GPO_19 = (int32_t)(1UL << 19), + + /*! Signal driven from the FPGA fabric on s2f_gp[20] */ + ALT_FPGA_GPO_20 = (int32_t)(1UL << 20), + + /*! Signal driven from the FPGA fabric on s2f_gp[21] */ + ALT_FPGA_GPO_21 = (int32_t)(1UL << 21), + + /*! Signal driven from the FPGA fabric on s2f_gp[22] */ + ALT_FPGA_GPO_22 = (int32_t)(1UL << 22), + + /*! Signal driven from the FPGA fabric on s2f_gp[23] */ + ALT_FPGA_GPO_23 = (int32_t)(1UL << 23), + + /*! Signal driven from the FPGA fabric on s2f_gp[24] */ + ALT_FPGA_GPO_24 = (int32_t)(1UL << 24), + + /*! Signal driven from the FPGA fabric on s2f_gp[25] */ + ALT_FPGA_GPO_25 = (int32_t)(1UL << 25), + + /*! Signal driven from the FPGA fabric on s2f_gp[26] */ + ALT_FPGA_GPO_26 = (int32_t)(1UL << 26), + + /*! Signal driven from the FPGA fabric on s2f_gp[27] */ + ALT_FPGA_GPO_27 = (int32_t)(1UL << 27), + + /*! Signal driven from the FPGA fabric on s2f_gp[28] */ + ALT_FPGA_GPO_28 = (int32_t)(1UL << 28), + + /*! Signal driven from the FPGA fabric on s2f_gp[29] */ + ALT_FPGA_GPO_29 = (int32_t)(1UL << 29), + + /*! Signal driven from the FPGA fabric on s2f_gp[30] */ + ALT_FPGA_GPO_30 = (int32_t)(1UL << 30), + + /*! Signal driven from the FPGA fabric on s2f_gp[31] */ + ALT_FPGA_GPO_31 = (int32_t)(1UL << 31) + +} ALT_FPGA_GPO_t; + +/*! + * Writes the General Purpose Output (GPO) register value. + * + * Writes the GPO data outputs with the specified values. The GPO drives the 32 + * \b s2f_gp signal values to the FPGA. Output signals are only written if + * their corresponding mask bits are set. + * + * NOTE: If the FPGA is not in User Mode then the effect of this operation is + * undefined. + * + * \param mask + * The set of signals (where mask bits equal one) to write. Other + * signals (where mask bits equal zero) are not changed. The \e + * mask may be defined by the logical OR of \ref ALT_FPGA_GPO_t + * values. + * + * \param value + * The 32-bit aggregate GPO register value. Values for the + * corressponding signal bits specified in the \e mask are written + * to the FPGA signals. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR The write failed. + */ +ALT_STATUS_CODE alt_fpga_gpo_write(uint32_t mask, uint32_t value); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_FPGA_MGR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_generalpurpose_io.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_generalpurpose_io.h new file mode 100644 index 000000000..325fdde4d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_generalpurpose_io.h @@ -0,0 +1,1254 @@ +/*! \file + * Altera - GPIO Module + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_GPIO_H__ +#define __ALT_GPIO_H__ + +#include +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ALT_GPIO_BITMASK 0x1FFFFFFF + +/* If the GPIO special test mode flag was not defined in the makefile, */ + /* set the ALT_GPIO_DATAREAD_TEST_MODE flag to false to specify that */ + /* the production code version of alt_gpio_port_data_read() is included. */ + /* If the flag is defined as true in the makefile, then the test version */ + /* located in the test code file is substituted instead of the version */ + /* in this file. */ +#ifndef ALT_GPIO_DATAREAD_TEST_MODE +#define ALT_GPIO_DATAREAD_TEST_MODE false +#endif + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API + * + * This module defines the General Purpose Input/Output Manager API for + * accessing, configuring, and controlling the General Purpose Input/Output + * Manager resources. These include both the general-purpose GPIO signals and + * the input-only GPI signals that are shared with the DDR interface.\n \n + * The GPIO API presents two views or perspectives of the GPIO signals. The first + * is to view the GPIO signals in a traditional way, as separate GPIO ports + * each comprised of a number of GPIO bits. The second perspective is of a + * unified flat view that presents the GPIO and GPI signals as a set of indexed + * bits, a view that allows the programmer to mostly ignore the port and pin + * hardware configuration and read/write/configure the GPIO and GPI signals + * independently of the underlying hardware implementation. + * + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions + * + * This functional group contains functions to control, configure and manage + * the general-purpose IO signals as individual signals or as groups of signals. + * This group of functions can operate on multiple bits within the same GPIO + * port and accepts a bit mask to specify which bits an operation will operate on. + * Other bits within the same GPIO port are not changed. + * + * This example shows how multiple drivers or applications can use this feature + * to easily prevent conflict while accessing the same GPIO port: + * \verbatim + #define DRIVER_0_GPIO_MSK 0x0010FF03; + #define DRIVER_1_GPIO_MSK 0x002000F8; + #define DRIVER_2_GPIO_MSK 0x03C00004; + #define DRIVER_3_GPIO_MSK 0x000F0000; + + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_0_GPIO_MSK, init_val0); + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, init_val1); + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_2_GPIO_MSK, init_val2); + alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_3_GPIO_MSK, init_val3); + alt_gpio_port_int_type_set(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, config_val1); + \endverbatim + * + * @{ + */ +/******************************************************************************/ +/*! + * This type definition enumerates the data direction (input or output) of + * the GPIO signals. + */ + +typedef enum ALT_GPIO_PIN_DIR_e +{ + /*! # */ + ALT_GPIO_PIN_INPUT, + /*! # */ + ALT_GPIO_PIN_OUTPUT +} ALT_GPIO_PIN_DIR_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the type of interrupt source + * (level-triggered or edge-triggered) of the GPIO signals. + */ + +typedef enum ALT_GPIO_PIN_TYPE_e +{ + /*! # */ + ALT_GPIO_PIN_LEVEL_TRIG_INT, + /*! # */ + ALT_GPIO_PIN_EDGE_TRIG_INT +} ALT_GPIO_PIN_TYPE_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the polarity of the interrupt sources + * (falling-edge or rising-edge for edge-triggered interrupts, active-low or + * active-high for level-triggered interrupts) of the GPIO signals. + */ + +typedef enum ALT_GPIO_PIN_POL_e +{ + /*! Indicates active-low for level-triggered interrupts and + * falling-edge for edge-triggered interrupts */ + ALT_GPIO_PIN_ACTIVE_LOW, + + /*! Indicates active-high for level-triggered interrupts and + * rising-edge for edge-triggered interrupt */ + ALT_GPIO_PIN_ACTIVE_HIGH +} ALT_GPIO_PIN_POL_t; + +/******************************************************************************/ +/*! + * This type definition enumerates whether or not the debounce metastability + * flip-flops are inserted or not. These are used to debounce signals presented + * to the GPIO inputs. A signal must be steady for two periods of the + * gpio_db_clk clock before it is considered valid. The frequency of the + * gpio_db_clk clock may be set using the Clock Manager API. + */ + +typedef enum ALT_GPIO_PIN_DEBOUNCE_e +{ + /*! # */ + ALT_GPIO_PIN_NODEBOUNCE, + /*! # */ + ALT_GPIO_PIN_DEBOUNCE +} ALT_GPIO_PIN_DEBOUNCE_t; + +/******************************************************************************/ +/*! + * This type definition enumerates whether or not level-sensitive interrupts + * are synchronized to the internal pclk_intr clock. It has no effect for GPIO + * signals that are selected as outputs, or if the interrupt is not enabled, + * or if the interrupt is set to be edge-triggered. This is a port-wide option. + */ + +typedef enum ALT_GPIO_PIN_SYNC_e +{ + /*! # */ + ALT_GPIO_PIN_NOSYNC, + /*! # */ + ALT_GPIO_PIN_SYNC +} ALT_GPIO_PIN_SYNC_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the possible data states of the GPIO bits. + */ + +typedef enum ALT_GPIO_PIN_DATA_e +{ + /*! # */ + ALT_GPIO_PIN_DATAZERO, + /*! # */ + ALT_GPIO_PIN_DATAONE +} ALT_GPIO_PIN_DATA_t; + + +/******************************************************************************/ +/*! + * This type definition enumerates the GPIO ports that the GPIO manager + * handles. + */ + +typedef enum ALT_GPIO_PORT_e +{ + /*! + * \b Port \b A - 29-bit GPIO port A. + */ + ALT_GPIO_PORTA, + + /*! + * \b Port \b B - 29-bit GPIO port B. + */ + ALT_GPIO_PORTB, + + /*! + * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals, + * 14 bits are used for GPI-only signals that are shared + * with the DDR interface, 2 bits are not used. Some signals + * may not be connected on some versions. See the relevant + * pin mux data. + */ + ALT_GPIO_PORTC, + + /*! + * \b Unknown \b Port - Used to indicate an error. + */ + ALT_GPIO_PORT_UNKNOWN +} ALT_GPIO_PORT_t; + + +/******************************************************************************/ +/*! + * This type definition enumerates the individual bits within the GPIO ports + * used by the GPIO manager. The bit-ordering must match the hardware + * bit-ordering. Since the ordering and packing of bitfields is not + * standardized in C/C++, the following are defined as masks. \n + * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits + * had previously been set to outputs), the user could use the syntax: \par + * \b alt_gpio_port_data_write(\b ALT_GPIO_PORTB, \b ALT_GPIO_BIT3 \b | \b + * ALT_GPIO_BIT4); + */ + +typedef enum ALT_GPIO_PORTBIT_e +{ + /*! # */ + ALT_GPIO_BIT0 = ALT_TWO_TO_POW0, + /*! # */ + ALT_GPIO_BIT1 = ALT_TWO_TO_POW1, + /*! # */ + ALT_GPIO_BIT2 = ALT_TWO_TO_POW2, + /*! # */ + ALT_GPIO_BIT3 = ALT_TWO_TO_POW3, + /*! # */ + ALT_GPIO_BIT4 = ALT_TWO_TO_POW4, + /*! # */ + ALT_GPIO_BIT5 = ALT_TWO_TO_POW5, + /*! # */ + ALT_GPIO_BIT6 = ALT_TWO_TO_POW6, + /*! # */ + ALT_GPIO_BIT7 = ALT_TWO_TO_POW7, + /*! # */ + ALT_GPIO_BIT8 = ALT_TWO_TO_POW8, + /*! # */ + ALT_GPIO_BIT9 = ALT_TWO_TO_POW9, + /*! # */ + ALT_GPIO_BIT10 = ALT_TWO_TO_POW10, + /*! # */ + ALT_GPIO_BIT11 = ALT_TWO_TO_POW11, + /*! # */ + ALT_GPIO_BIT12 = ALT_TWO_TO_POW12, + /*! # */ + ALT_GPIO_BIT13 = ALT_TWO_TO_POW13, + /*! # */ + ALT_GPIO_BIT14 = ALT_TWO_TO_POW14, + /*! # */ + ALT_GPIO_BIT15 = ALT_TWO_TO_POW15, + /*! # */ + ALT_GPIO_BIT16 = ALT_TWO_TO_POW16, + /*! # */ + ALT_GPIO_BIT17 = ALT_TWO_TO_POW17, + /*! # */ + ALT_GPIO_BIT18 = ALT_TWO_TO_POW18, + /*! # */ + ALT_GPIO_BIT19 = ALT_TWO_TO_POW19, + /*! # */ + ALT_GPIO_BIT20 = ALT_TWO_TO_POW20, + /*! # */ + ALT_GPIO_BIT21 = ALT_TWO_TO_POW21, + /*! # */ + ALT_GPIO_BIT22 = ALT_TWO_TO_POW22, + /*! # */ + ALT_GPIO_BIT23 = ALT_TWO_TO_POW23, + /*! # */ + ALT_GPIO_BIT24 = ALT_TWO_TO_POW24, + /*! # */ + ALT_GPIO_BIT25 = ALT_TWO_TO_POW25, + /*! # */ + ALT_GPIO_BIT26 = ALT_TWO_TO_POW26, + /*! # */ + ALT_GPIO_BIT27 = ALT_TWO_TO_POW27, + /*! # */ + ALT_GPIO_BIT28 = ALT_TWO_TO_POW28, + ALT_GPIO_BIT29 = ALT_TWO_TO_POW29, /* Not currently used */ + ALT_GPIO_BIT30 = ALT_TWO_TO_POW30, /* Not currently used */ + ALT_GPIO_BIT31 = (int32_t) (1UL<<31), /* Not currently used */ + + ALT_GPIO_BITNUM_MAX = (28), + ALT_GPIO_BIT_MAX = (1 << ALT_GPIO_BITNUM_MAX), + ALT_END_OF_GPIO_PORT_SIGNALS = (32) +} ALT_GPIO_PORTBIT_t; + + + +/******************************************************************************/ +/*! + * Initialize the GPIO modules before use + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_init(void); + +/******************************************************************************/ +/*! + * Uninitialize the GPIO modules & return to reset state + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_gpio_uninit(void); + +/******************************************************************************/ +/*! + * Sets the specified GPIO data bits to use the data direction(s) + * specified. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * configure all data direction bits of the port. + * \param config + * The data-directions of the bits to be set in this operation. + * Individual bits are: \n \b 0 - Use as an input (default). \n + * \b 1 - Use as an output. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the data direction configuration of selected bits of the + * specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to read and + * return. Other bits (where mask bits equal zero) are returned + * as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * return all data direction bits of the port. + * + * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is + * configured as an input. + * \n \b 1 - The signal is configured as an output. + * + */ +uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + +/******************************************************************************/ +/*! + * Sets the GPIO data outputs of the specified GPIO module to a logic one or + * zero. Outputs are only set if the data direction for those bits is also + * set to configure them as outputs. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (mask bits equal one) to apply this + * operation to. Other bits (mask bits equal zero) are + * not changed. + * \param val + * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs + * are used. Setting the three MSBs causes an error. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t val); + +/******************************************************************************/ +/*! + * Returns the value of the data inputs of the specified GPIO module. This is + * the current logic value of the pin, whether set to be an input or an output. + * \n If a given signal is set to be an output, this input value can be read to + * determine if the pin is grounded, pulled high, or is floating. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of + * the port. + * + * \retval uint32_t The current value of the GPIO module input signals. + */ +uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask); + + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions + * + * This functional group contains functions to control and manage the + * interrupts of the General-Purpose IO modules. + * + * @{ + */ +/******************************************************************************/ +/*! + * Sets edge-triggered or level-triggered interrupt configuration for the + * specified signals of the specified GPIO module. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * configure all interrupt type bits of the port. + * \param config + * The interrupt configuration to write. Individual bits + * are: \n \b 0 - Set the + * interrupt for this bit to be level-sensitive (default). \n \b + * 1 - Set the interrupt for this bit to be edge-sensitive. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the interrupt configuration (edge-triggered or level-triggered) for + * the specified bits of the specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration + * bits of the port. + * \retval uint32_t + * The current interrupt source configuration. Individual bits + * are: \n \b 0 - The interrupt for this bit is set to be + * level-sensitive. \n \b 1 - + * The interrupt for this bit is set to be edge-sensitive. + * + */ +uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + +/******************************************************************************/ +/*! + * Sets the interrupt polarity of the signals of the specified GPIO register + * (when used as inputs) to active-high or active-low (for level-sensitive + * interrupts) or to rising-edge or falling-edge (for edge-sensitive interrupts). + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. + * \param config + * The interrupt polarity configuration to set. Individual bits + * are: \n \b 0 - Set the interrupt polarity for this bit to + * active-low or falling-edge mode (default). \n \b 1 - Set the + * interrupt polarity for this bit to active-high or rising-edge mode. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the active-high or active-low polarity configuration for the + * possible interrupt sources of the specified GPIO module. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the + * configuration bits of the port. + * + * \retval uint32_t + * The current polarity configuration. Individual bits are: \n + * \b 0 = The interrupt polarity for this bit is set to + * active-low or falling-edge mode. \n \b 1 = The interrupt + * polarity for this bit is set to active-high or rising-edge mode. + * + */ +uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions + * + * @{ + */ +/******************************************************************************/ +/*! + * Sets the debounce configuration for input signals of the specified GPIO + * module. If debounce is selected, metastability flip-flops are inserted to + * debounce signals presented to the GPIO inputs. A signal must be steady for + * two periods of the gpio_db_clk clock before it is considered valid. The + * frequency of the gpio_db_clk clock may be set using the Clock Manager API. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to apply this + * operation to. Other bits (where mask bits equal zero) are + * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to + * configure the debounce setting for all bits of the port. + * \param config + * The debounce configuration to set. Individual bits are: \n + * \b 0 - Debounce is not selected for this signal (default). \n + * \b 1 - Debounce is selected for this signal. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the debounce configuration for the input signals of the specified + * GPIO register. If debounce is selected, metastability flip-flops are + * inserted to debounce signals presented to the GPIO inputs. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits (where mask bits equal one) to return. Other + * bits (where mask bits equal zero) are returned as zero. Specify + * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce + * configuration bits of the port. + * + * \retval uint32_t + * The current debounce configuration.Individual bits are: \n + * \b 0 - Debounce is not selected for this signal. \n \b 1 - + * Debounce is selected for this signal. + * + */ +uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask); + +/******************************************************************************/ +/*! + * Sets the synchronization configuration for the signals of the specified + * GPIO register. This allows for synchronizing level-sensitive interrupts to + * an internal clock signal. This is a port-wide option that controls all + * level-sensitive interrupt signals of that GPIO port. + * + * \param gpio_pid + * The GPIO port identifier. + * \param config + * \n \b Any \b non-zero \b value - Synchronize to internal clock signal. + * \n \b Zero - Do not synchronize to internal clock signal. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t config); + +/******************************************************************************/ +/*! + * + * Returns the synchronization configuration for the signals of the + * specified GPIO register. This allows for synchronizing level-sensitive + * interrupts to the internal clock signal. This is a port-wide option that + * controls all level-sensitive interrupt signals of that GPIO port. + * + * \param gpio_pid + * The GPIO port identifier. + + + * \retval ALT_E_TRUE Synchronization to clock is enabled for + * level-sensitive interrupts. + * \retval ALT_E_FALSE Synchronization to clock is disabled for + * level-sensitive interrupts. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Configures a group of GPIO signals with identical setup parameters. Allows + * for configuring all parameters of a given port at one time. + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * The group of bits to apply this operation to. Other bits (mask + * set to zero) are not changed. + * \param dir + * Data direction. + * \param type + * Edge-triggered or level-triggered interrupts. + * \param pol + * Active-high or active-low polarity. + * \param debounc + * Debounce signals or not. + * \param data + * Set the data output to this value. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, + ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc, + uint32_t data); + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions + * + * @{ + */ +/******************************************************************************/ +/*! + * Enables the specified GPIO data input interrupts. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param config + * Individual bit interrupt enables \n + * \b 0 - Interrupt disabled. \n + * \b 1 - Interrupt enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config); + +/******************************************************************************/ +/*! + * Disables the specified GPIO data module interrupt. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param config + * Individual bit interrupt enables \n + * \b 0 - Interrupt disabled. \n + * \b 1 - Interrupt enabled. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Bad input argument. + */ +ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config); + +/******************************************************************************/ +/*! + * Returns the current state of the specified GPIO port interrupts enables. + * + * \param gpio_pid + * The GPIO port identifier. + * + * \retval uint32_t + * The interrupt enable configuration that was read. Individual bits + * are: \n \b 0 = The interrupt for this bit is not enabled. \n \b + * 1 = The interrupt for this bit is enabled. + */ +uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid); + + +/******************************************************************************/ +/*! + * Masks or unmasks selected interrupt source bits of the data register of + * the specified GPIO module. Uses a second bit mask to determine which + * signals may be changed by this call. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param mask + * Which bits to change among the port \n \b 0 = + * Do not change this bit. \n \b 1 = Allow this bit to change. + * \param val + * The interrupt mask to write. Individual bits are: \n \b 0 = + * Do not mask the interrupt for this bit (default). \n \b 1 = + * Mask the interrupt for this bit. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid, + uint32_t mask, uint32_t val); + +/******************************************************************************/ +/*! + * Returns the interrupt mask of the specified GPIO module. + * + * + * \param gpio_pid + * The GPIO port identifier. + * + * \retval uint32_t + * The interrupt mask that was read. Individual bits are: \n + * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The + * interrupt for this bit is masked. + * + */ +uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Returns the interrupt pending status of all signals of the specified GPIO + * register. + * + * + * \param gpio_pid + * The GPIO port identifier. + + * \retval uint32_t + * The current interrupt pending status. Individual bits are: \n + * \b 0 - The interrupt for this bit is not pending. \n \b 1 - + * The interrupt for this bit is pending. + * + */ +uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Clear the interrupt pending status of selected signals of the + * specified GPIO register. + * + * + * \param gpio_pid + * The GPIO port identifier. + * \param clrmask + * The interrupt bits to clear. Individual bits are: \n \b 0 - + * The interrupt for this bit will not be changed. \n \b 1 - + * The interrupt for this bit will be cleared. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input data. + */ +ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid, + uint32_t clrmask); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index + * + * This functional group presents a perspective of the General-Purpose IO + * signals as individual GPIO and GPI bits spread across a number of signals + * across several GPIO ports. This allows the programmer the freedom to generally + * ignore the underlying port and signal structure of the GPIO hardware if + * desired. + * + * @{ + */ +/******************************************************************************/ +/*! + * This type definition enumerates the individual bits as one flat array spread + * across the multiple GPIO ports handled by the GPIO manager. The bit-ordering + * must match the hardware bit-ordering. + * + */ +typedef enum ALT_GPIO_1BIT_e +{ + /*! # */ + ALT_GPIO_1BIT_0, + /*! # */ + ALT_GPIO_1BIT_1, + /*! # */ + ALT_GPIO_1BIT_2, + /*! # */ + ALT_GPIO_1BIT_3, + /*! # */ + ALT_GPIO_1BIT_4, + /*! # */ + ALT_GPIO_1BIT_5, + /*! # */ + ALT_GPIO_1BIT_6, + /*! # */ + ALT_GPIO_1BIT_7, + /*! # */ + ALT_GPIO_1BIT_8, + /*! # */ + ALT_GPIO_1BIT_9, + /*! # */ + ALT_GPIO_1BIT_10, + /*! # */ + ALT_GPIO_1BIT_11, + /*! # */ + ALT_GPIO_1BIT_12, + /*! # */ + ALT_GPIO_1BIT_13, + /*! # */ + ALT_GPIO_1BIT_14, + /*! # */ + ALT_GPIO_1BIT_15, + /*! # */ + ALT_GPIO_1BIT_16, + /*! # */ + ALT_GPIO_1BIT_17, + /*! # */ + ALT_GPIO_1BIT_18, + /*! # */ + ALT_GPIO_1BIT_19, + /*! # */ + ALT_GPIO_1BIT_20, + /*! # */ + ALT_GPIO_1BIT_21, + /*! # */ + ALT_GPIO_1BIT_22, + /*! # */ + ALT_GPIO_1BIT_23, + /*! # */ + ALT_GPIO_1BIT_24, + /*! # */ + ALT_GPIO_1BIT_25, + /*! # */ + ALT_GPIO_1BIT_26, + /*! # */ + ALT_GPIO_1BIT_27, + /*! # */ + ALT_GPIO_1BIT_28, + /*! # */ + ALT_GPIO_1BIT_29, + /*! # */ + ALT_GPIO_1BIT_30, + /*! # */ + ALT_GPIO_1BIT_31, + /*! # */ + ALT_GPIO_1BIT_32, + /*! # */ + ALT_GPIO_1BIT_33, + /*! # */ + ALT_GPIO_1BIT_34, + /*! # */ + ALT_GPIO_1BIT_35, + /*! # */ + ALT_GPIO_1BIT_36, + /*! # */ + ALT_GPIO_1BIT_37, + /*! # */ + ALT_GPIO_1BIT_38, + /*! # */ + ALT_GPIO_1BIT_39, + /*! # */ + ALT_GPIO_1BIT_40, + /*! # */ + ALT_GPIO_1BIT_41, + /*! # */ + ALT_GPIO_1BIT_42, + /*! # */ + ALT_GPIO_1BIT_43, + /*! # */ + ALT_GPIO_1BIT_44, + /*! # */ + ALT_GPIO_1BIT_45, + /*! # */ + ALT_GPIO_1BIT_46, + /*! # */ + ALT_GPIO_1BIT_47, + /*! # */ + ALT_GPIO_1BIT_48, + /*! # */ + ALT_GPIO_1BIT_49, + /*! # */ + ALT_GPIO_1BIT_50, + /*! # */ + ALT_GPIO_1BIT_51, + /*! # */ + ALT_GPIO_1BIT_52, + /*! # */ + ALT_GPIO_1BIT_53, + /*! # */ + ALT_GPIO_1BIT_54, + /*! # */ + ALT_GPIO_1BIT_55, + /*! # */ + ALT_GPIO_1BIT_56, + /*! # */ + ALT_GPIO_1BIT_57, + /*! # */ + ALT_GPIO_1BIT_58, + /*! # */ + ALT_GPIO_1BIT_59, + /*! # */ + ALT_GPIO_1BIT_60, + /*! # */ + ALT_GPIO_1BIT_61, + /*! # */ + ALT_GPIO_1BIT_62, + /*! # */ + ALT_GPIO_1BIT_63, + /*! # */ + ALT_GPIO_1BIT_64, + /*! # */ + ALT_GPIO_1BIT_65, + /*! # */ + ALT_GPIO_1BIT_66, + /*! # */ + ALT_GPIO_1BIT_67, /* Not bonded out on some versions */ + /*! # */ + ALT_GPIO_1BIT_68, /* Not bonded out on some versions */ + /*! # */ + ALT_GPIO_1BIT_69, /* Not bonded out on some versions */ + + /*! The last of the input/output bits */ + ALT_GPIO_1BIT_70, /* Not bonded out on some versions */ + + + /*! This and the following signals are not present on all SoCs. \n + * If present, the selection between their use as 14 General-purpose inputs or + * use as 14 DDR interface signals is made in the IOCSR (IO Configuration Shift + * Register) and software to make this selection is in the IO Manager API. If + * they are present, they are restricted to using the same power supply voltage + * as the SDRAM module.*/ + ALT_HLGPI_0, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_1, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_2, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_3, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_4, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_5, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_6, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_7, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_8, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_9, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_10, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_11, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_12, /* Not bonded out on some versions */ + /*! # */ + ALT_HLGPI_13, /* Not bonded out on some versions */ + + ALT_HLGPI_14, /* Not bonded out */ + + ALT_HLGPI_15, /* Not bonded out */ + + ALT_GPIO_INVALID, + ALT_END_OF_GPIO_SIGNALS = -1, + ALT_LAST_VALID_GPIO_BIT = ALT_HLGPI_15 +} ALT_GPIO_1BIT_t; + + +/******************************************************************************/ +/*! + * This configuration record definition is used for configuring bits and + * groups of bits of the GPIO interface. + */ +typedef struct ALT_GPIO_CONFIG_RECORD_s +{ + /*! + * The index number of the signal to configure. */ + ALT_GPIO_1BIT_t signal_number; + /*! + * The data direction of the signal. */ + ALT_GPIO_PIN_DIR_t direction; + /*! + * Edge-triggered or level triggered interrupts. */ + ALT_GPIO_PIN_TYPE_t type; + /*! + * Active-high or active-low trigger for the interrupt. */ + ALT_GPIO_PIN_POL_t polarity; + /*! + * Enable or disable GPIO debounce capability. */ + ALT_GPIO_PIN_DEBOUNCE_t debounce; + /*! + * If the signal is an output, the data value to be output. */ + ALT_GPIO_PIN_DATA_t data; +} ALT_GPIO_CONFIG_RECORD_t; + +/******************************************************************************/ +/*! + * This pin record type definition is comprised of the signal index and + * associated input or output data. + */ +typedef struct ALT_GPIO_PIN_RECORD_s +{ + /*! + * The index number of the signal. */ + ALT_GPIO_1BIT_t signal_number; + /*! + * Data - zero or one. */ + ALT_GPIO_PIN_DATA_t val; +} ALT_GPIO_PIN_RECORD_t; + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index + * + * @{ + */ +/******************************************************************************/ +/*! + * Configures all parameters for one bit (signal) of the GPIO ports. + * + * \param signal_num + * The GPIO port signal index. + * \param dir + * The data direction for this signal. + * \param type + * Edge-triggered or Level-triggered interrupt for this signal. + * \param pol + * Active-high or active-low interrupt polarity for this signal. + * \param debounce + * Enable the debounce flip-flops for this signal or not. + * \param data + * If the GPIO signal is set to be an output, set it to + * this value + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num, + ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, + ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce, + ALT_GPIO_PIN_DATA_t data); + +/******************************************************************************/ +/*! + * Returns the configuration parameters of a given GPIO bit. + * + * \param signal_num + * The GPIO port signal index. + * \param config + * Pointer to a single GPIO_CONFIG_RECORD_s configuration record. + * The fields of this configuration record are filled in + * by the function. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num, + ALT_GPIO_CONFIG_RECORD_t *config); + +/******************************************************************************/ +/*! + * Configures a list of GPIO bits. The GPIO bits do not have to be + * configured the same, as was the case for the mask version of this function, + * alt_gpio_port_config(). Each bit may be configured differently and bits may + * be listed in any order. + * + * \param config_array + * Pointer to an array of GPIO_CONFIG_RECORD_s configuration + * records. These definitions contain all the parameters + * needed to set up the listed pins. All or + * any subset of the GPIO signals can be configured. Signals do + * not have to be listed in numerical order or be unique. If a + * signal number is listed multiple times, the last configuration + * listed is used. \n Configuration terminates either when \b len + * signals have been configured or if the next signal number index + * in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1). + * + * \param len + * Length of array to configure. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, + uint32_t len); + +/******************************************************************************/ +/*! + * Returns a list of the pin signal indices and the associated configuration + * settings (data direction, interrupt type, polarity, and debounce) of that + * list of signals. + * + * \param config_array + * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration + * records. Only the signal indices in the first field of each + * configuration record need be filled in. This function will + * fill in all the other fields of the configuration record, + * returning all configuration parameters in the array. + * Signals do not have to be listed in numerical order or be + * unique. If a signal number is listed multiple times, the + * configuration record will contain multiple entries for + * that signal. \n Configuration reading terminates either when + * \b len signal configurations have been read or if the next + * signal number index in the array is equal to + * \b ALT_END_OF_GPIO_SIGNALS (-1). + * \param len + * Length of configuration array to read and return. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + + */ +ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array, + uint32_t len); + +/******************************************************************************/ +/*! + * Returns a list of the pin signal indices and the associated configuration + * settings (data direction, interrupt type, polarity, and debounce) of that + * list of signals. The difference between this version and + * alt_gpio_group_config_get() is this version follows a separate list of + * signal indices instead of having the signal list provided in the first + * field of the configuration records in the array. + * + * \param pinid_array + * Pointer to a list of signal index numbers. These indices + * are copied to the first field of each configuration record + * in the returned array. + * \param config_array + * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration + * records. This function will fill in the fields of the + * configuration record, returning all configuration parameters + * in the array. Signals do not have to be listed in numerical + * order or be unique. If a signal number is listed multiple + * times, the configuration record array will contain multiple + * identical entries for that signal. \n Configuration reading + * terminates either when \b len signal configurations have been + * read or if the next signal number index in the array is equal + * to \b ALT_END_OF_GPIO_SIGNALS (-1). + * \param len + * Length of configuration array to read. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + * + */ +ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array, + ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len); + + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup ALT_GPIO_UTILITY General-Purpose IO Utility Functions + * + * These are useful utility functions for the general-purpose input & output + * module. + * + * @{ */ +/******************************************************************************/ +/*! + * Returns the ID code of the specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * + * + * \retval uint32_t The component code of the module, GPIO_MODULE_IDCODE. + */ +uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid); + +/******************************************************************************/ +/*! + * Returns the version code of the specified GPIO module. + * + * \param gpio_pid + * The GPIO port identifier. + * + * + * \retval uint32_t The encoded revision number of the module. + */ +uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid); + + +/******************************************************************************/ +/*! + * Extracts the GPIO port ID from the supplied GPIO Signal Index Number. + */ +ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num); + + +/******************************************************************************/ +/*! + * Extracts the GPIO signal (pin) offset from the supplied GPIO Signal Index + * Number. + * */ +ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num); + +/******************************************************************************/ +/*! + * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and + * signal mask. If passed a bitmask composed of more than one signal, the + * signal number of the lowest bit in the bitmask presented is returned. + * + */ +ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid, + uint32_t bitmask); + + +/*! @} */ +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_GPIO_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_globaltmr.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_globaltmr.h new file mode 100644 index 000000000..b8505f82a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_globaltmr.h @@ -0,0 +1,488 @@ +/*! \file + * Altera - Module Description + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_GBLTMR_H__ +#define __ALT_GBLTMR_H__ + +#include +#include +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/******************************************************************************/ +/*! \addtogroup GBLTMR_MGR The Global Timer Manager API + * + * This functional group handles setting and reading various parameters of the + * global 64-bit incrementing counter. There is one 64-bit continuously + * incrementing counter for all CPU cores and it is clocked by PERIPHCLK. + * This section manages the comparator value, compare enable, + * auto-increment value, auto-increment enable, and interrupt enable for the + * CPU that this code is running on (referenced as \b CPU_GLOBAL_TMR). + * @{ + */ +/******************************************************************************/ +/*! Uninitialize the Global timer module + * + */ +ALT_STATUS_CODE alt_globaltmr_uninit(void); + +/******************************************************************************/ +/*! Initialize the Global timer module + * + */ +ALT_STATUS_CODE alt_globaltmr_init(void); + +/******************************************************************************/ +/*! + * Stops the global timer counter compare function for this CPU and disables + * its interrupt. It does + * not stop the global timer itself. This function is identical to calling + * \b alt_gpt_tmr_stop() with a tmr_id of \b CPU_GLOBAL_TMR. + * + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_globaltmr_stop(void); + +/******************************************************************************/ +/*! + * Starts the global timer compare function for this CPU, enables its interrupt + * function and, if free-running mode is selected also enables its + * auto-increment function. If the global timer is not yet running, it starts + * the timer. This function is identical to calling \b alt_gpt_tmr_start() + * with a tmr_id of \b CPU_GLOBAL_TMR. + * + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_globaltmr_start(void); + +/******************************************************************************/ +/*! + * Returns the current counter value of the 64-bit global timer. + * + * + * \param highword + * Location used to return the most significant 32-bit word of + * the current global timer count. + * \param lowword + * Location used to return the least significant 32-bit word + * of the current global timer count. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_get(uint32_t* highword, uint32_t* lowword); + +/******************************************************************************/ +/*! + * Returns the current counter value of the 64-bit global timer. This function + * is identical to alt_globaltmr_get() except that the value is returned as a + * 64-bit unsigned integer rather than as two 32-bit words. + * + * + * + * \retval uint64_t + * The current value of the 64-bit counter. + */ +uint64_t alt_globaltmr_get64(void); + +/******************************************************************************/ +/*! + * Returns the 32 low-order bits of the global timer. This + * is identical to calling \b alt_gpt_counter_get() with a tmr_id equal + * to \b CPU_GLOBAL_TMR. Use alt_globaltmr_get() or alt_globaltmr_get64() to + * obtain the full 64-bit timer value. + * + * + * + * \retval uint32_t The current 32-bit counter value. + */ +uint32_t alt_globaltmr_counter_get_low32(void); + +/******************************************************************************/ +/*! + * Returns the 32 higher-order bits of the global timer. Use alt_globaltmr_get() + * or alt_globaltmr_get64() to obtain the full 64-bit timer value. + * + * + * + * \retval uint32_t The current 32-bit counter value. + */ +uint32_t alt_globaltmr_counter_get_hi32(void); + +/******************************************************************************/ +/*! + * Sets the value of the 64-bit global timer comparator for this CPU. The + * global timer increments its count and when it reaches this value or above, + * it triggers the following actions. If the interrupt is enabled, it forwards + * an interrupt request to the core. If free-run mode is selected, it adds the + * auto-increment value to the value of the global counter and the resulting + * sum is saved as the new comparator value. + * + * + * \param highword + * The 32 MSBits of the new comparator value. + * \param loword + * The 32 LSBits of the new comparator value. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_comp_set(uint32_t highword, uint32_t loword); + +/******************************************************************************/ +/*! + * Sets the value of the 64-bit global timer comparator for this CPU. The + * global timer increments its count and when it reaches this value or above, + * it triggers the following actions. If the interrupt is enabled, it forwards + * an interrupt request to the core. If free-run mode is selected, it adds the + * auto-increment value to the value of the global counter and the resulting + * sum is saved as the new comparator value. + * + * + * \param compval + * The new comparator value to set. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_comp_set64(uint64_t compval); + +/******************************************************************************/ +/*! + * Returns the current 64-bit global timer comparator value for this CPU. The + * global timer increments its count and when it reaches this value or above, + * it triggers the following actions. If the interrupt is enabled, it forwards + * an interrupt request to the core. If free-run mode is selected, it adds the + * auto-increment value to the value of the global counter and the resulting + * sum is saved as the new comparator value. This value will increase by the + * auto-increment value each time the global timer reaches the comparator + * value. + * + * + * \param highword + * Pointer to location to store the 32 MSBits of the comparator value. + * \param lowword + * Pointer to location to store the 32 LSBits of the comparator value. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_comp_get(uint32_t *highword, uint32_t *lowword); + +/******************************************************************************/ +/*! + * Returns the current 64-bit global timer comparator value for this CPU. The + * global timer increments its count and when it reaches this value or above, + * it triggers the following actions. If the interrupt is enabled, it forwards + * an interrupt request to the core. If free-run mode is selected, it adds the + * auto-increment value to the value of the global counter and the resulting + * sum is saved as the new comparator value. This value will increase by the + * auto-increment value each time the global timer reaches the comparator + * value. This function is identical to alt_globaltmr_comp_get() except that the + * value is returned in a 64-bit unsigned integer rather than as two 32-bit + * words. + * + * + * \retval uint64_t + * The 64-bit value of the global timer comparator. + */ +uint64_t alt_globaltmr_comp_get64(void); + + +/******************************************************************************/ +/*! + * Enables the comparison function of the global timer for this CPU. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_comp_mode_start(void); + +/******************************************************************************/ +/*! + * Disables the comparison function of the global timer for this CPU. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_comp_mode_stop(void); + +/******************************************************************************/ +/*! + * Returns the comparison mode selection of the global + * timer for this CPU. + * + * + * \retval FALSE Comparison mode is not enabled. + * \retval TRUE Comparison mode is enabled. + */ +bool alt_globaltmr_is_comp_mode(void); + + +/******************************************************************************/ +/*! + * Returns the clock prescaler value of the global timer. + * + * + * \retval uint32_t The prescaler value. Valid range is 0-255. + * Actual clock divisor ratio is this number plus one. + */ +uint32_t alt_globaltmr_prescaler_get(void); + + +/******************************************************************************/ +/*! + * Sets the clock prescaler value of the global timer. + * + * + * \param val + * The 8-bit prescaler value to load. Valid range is 0-255. + * Actual clock divisor ratio is this number plus one. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_prescaler_set(uint32_t val); + +/******************************************************************************/ +/*! + * Sets a 32-bit global timer auto-increment value in the global + * timer block for this CPU. The global timer continually increments its count + * and when it reaches the value set in the comparator register or above, if + * both comparison and free-run modes are selected, it adds the value set by this + * function to the comparator value and saves it as the new comparator value. + * This count then sets the time delay until the next global timer compare + * value is reached. + * + * + * \param inc + * Auto-increment value to set. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_autoinc_set(uint32_t inc); + +/******************************************************************************/ +/*! + * Returns the global timer auto-increment value for this CPU. When the global + * timer reaches the comparator value, if both comparison and free-run modes + * are selected this value is added to the previous comparator value and saved + * as the new comparator value. + * + * + * \retval uint32_t + * The current comparator auto-increment value. + */ +uint32_t alt_globaltmr_autoinc_get(void); + +/******************************************************************************/ +/*! + * Enables the auto-increment function of the global timer for this CPU. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_autoinc_mode_start(void); + +/******************************************************************************/ +/*! + * Disables the auto-increment function of the global timer for this CPU. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_autoinc_mode_stop(void); + +/******************************************************************************/ +/*! + * Returns the auto-increment selection of the global timer for this CPU. + * + * + * \retval FALSE Auto-increment mode is not enabled. + * \retval TRUE Auto-increment mode is enabled. + */ +bool alt_globaltmr_is_autoinc_mode(void); + +/******************************************************************************/ +/*! + * Returns the maximum counter value available for \b CPU_GLOBAL_TMR. \n + * The value returned does not factor in the value of the clock prescaler. + * + * + * + * + * \retval uint32_t The maximum counter value available for this timer. + * \retval 0 An error occurred. + * + */ +uint32_t alt_globaltmr_maxcounter_get(void); + +/******************************************************************************/ +/*! + * Disables the interrupt from the global timer module. Identical to calling + * alt_gpt_int_disable() with tmr_id of \b CPU_GLOBAL_TMR. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_int_disable(void); + +/******************************************************************************/ + +#if 0 +/*! + * + * Enables the interrupt of the global timer + * module. Identical to calling alt_gpt_int_enable() with tmr_id of + * \b CPU_GLOBAL_TMR. If global timer is not already running, this function + * returns an error. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_globaltmr_int_enable(void); + +#else +/*! + * + * Enables the interrupt of the global timer + * module. Identical to calling alt_gpt_int_enable() with tmr_id of + * \b CPU_GLOBAL_TMR. If global timer is not already running, this function + * attempts to start it. + * + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_globaltmr_int_enable(void); + +#endif + +/******************************************************************************/ +/*! + * Return \b TRUE if the interrupt of the global timer module is enabled + * and \b FALSE if the interrupt is disabled or masked. Identical to calling + * alt_gpt_int_is_enabled() with tmr_id of + * \b CPU_GLOBAL_TMR. + * + * \internal - note that there's more to this than just enabling the + * interrupt and clearing the status. + * \endinternal + * + * + * \retval TRUE The timer interrupt is currently enabled. + * \retval FALSE The timer interrupt is currently disabled. + */ +bool alt_globaltmr_int_is_enabled(void); + +/******************************************************************************/ +/*! + * Clear the pending interrupt status of the global timer module. Identical to + * calling alt_gpt_int_clear_pending() with tmr_id of + * \b CPU_GLOBAL_TMR. + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_globaltmr_int_clear_pending(void); + +/******************************************************************************/ +/*! + * Read the state (pending or not) of the interrupt of the global timer + * module without changing the interrupt state. Identical to + * calling alt_gpt_int_is_pending() with tmr_id of + * \b CPU_GLOBAL_TMR. + * + * + * + * \retval TRUE The timer interrupt is currently pending. + * \retval FALSE The timer interrupt is not currently pending. + */ +bool alt_globaltmr_int_is_pending(void); + +/******************************************************************************/ +/*! + * Read the state of the interrupt of the global timer + * module and if the interrupt is set, clear it. Identical to + * calling alt_gpt_int_is_pending_and_clear() with tmr_id of + * \b CPU_GLOBAL_TMR. + * + * + * + * \retval TRUE The timer interrupt was pending. + * \retval FALSE The timer interrupt was not pending. + */ +bool alt_globaltmr_int_if_pending_clear(void); + +/*! @} */ +/*! @} */ +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_GBLTMR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_hwlibs_ver.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_hwlibs_ver.h new file mode 100644 index 000000000..623c01a1e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_hwlibs_ver.h @@ -0,0 +1,56 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_HWLIBS_VER_H__ + +/*********************************************************************** + * + * Set of macros to provide version information + * + ***********************************************************************/ + +/* This is the major revision of the Altera ACDS Release */ +#define ALTERA_ACDS_MAJOR_REV 13 + +/* This is the minor revision of the Altera ACDS Release */ +#define ALTERA_ACDS_MINOR_REV 1 + +/* This is an internal HwLibs revision/feature control code. */ +/* End-users should NOT depend upon the value of this field */ +#define ALTERA_HWLIBS_REV 0 + +/* This is a text string containing the current release and service pack IDs */ +#define ALTERA_ACDS_REV_STR "13.1" + +/* This is a text string containing the current SoC EDS ID */ +#define ALTERA_SOCEDS_REV_STR "Altera SoC Embedded Design Suite v13.1" + + +#endif /* __ALT_HWLIBS_VER_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_i2c.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_i2c.h new file mode 100644 index 000000000..d3d9f09c6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_i2c.h @@ -0,0 +1,2024 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/*! \file + * Altera - I2C Controller API + */ + +#ifndef __ALT_I2C_H__ +#define __ALT_I2C_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "socal/alt_i2c.h" +#include "socal/alt_rstmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C I2C Controller API + * + * This module defines an API for configuring and managing the HPS I2C controllers. + * + * The I2C controller provides support for a communication link between integrated + * circuits on a board. It is a simple two-wire bus which consists of a serial + * data line (SDA) and a serial clock (SCL) for use in applications such as + * temperature sensors and voltage level translators to EEPROMs, A/D and D/A + * converters, CODECs, and many types of microprocessors. + * + * The Hard Processor System (HPS) provides four I2C controllers to enable system + * software to communicate serially with I2C buses. Each I2C controller can + * operate in master or slave mode, and support standard mode of up to 100 + * kilobits per second (Kbps) or fast mode of up to 400 Kbps. These I2C + * controllers are instances of the Synopsys DesignWare APB I2C (DW_apb_i2c) + * controller. + * + * NOTE: Each I2C controller must be programmed to operate in either master or + * slave mode only. Operating as a master and slave simultaneously is not + * supported. + * + * Features of the I2C Controller: + * * Support both 100 KBps and 400 KBps modes + * * One of the following I2C operations: master or slave + * * Support both 7-bit and 10-bit addressing modes + * * Mixed read and write combined-format transactions + * * Bulk transmit mode + * * DMA handshaking interface + * + * For a complete details on the configuration and operation of I2C controller, + * consult the following references: + * * Cyclone V Device Handbook Volume 3: Hard Processor System Technical + * Reference Manual, Chapter 20. I2C Controller (cv_54020-1.2) + * * Synopsys DesignWare DW_apb_i2c Databook DW_apb_i2c, Version 1.15a + * * The I2C-Bus Specification Version 2.1 + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the operational state of I2C by + * transfer operation. + */ +typedef enum ALT_I2C_TRANSFER_TYPE_e +{ + ALT_I2C_TRANSFER_NONE = 0, /*!< No transfer operation */ + ALT_I2C_TRANSFER_START = 1, /*!< Start detect */ + ALT_I2C_TRANSFER_COMPLETE = 2, /*!< All operations done */ + ALT_I2C_TRANSFER_READ = 3, /*!< Read operation is active */ + ALT_I2C_TRANSFER_WRITE = 4, /*!< Write operation is active */ +} +ALT_I2C_TRANSFER_TYPE_t; + + +/* + * A pointer or handle to the I2C controller device instance. The ALT_I2C_DEV_t is + * initialized by a call to alt_i2c_init() and subsequently used by the other I2C + * controller API functions as a reference to a specific device. + * + * \internal + * ALT_I2C_DEV_t may be a struct or reference to an opaque data + * structure. Whatever "internal" type is suited to the needs of the + * implementation. + * \endinternal + */ +typedef struct ALT_I2C_DEV_s +{ + void * location; /*!< HPS address of I2C instance. */ + alt_freq_t clock_freq; /*!< Input clock frequency. */ + uint32_t last_target; /*!< Last issued target address. */ +} +ALT_I2C_DEV_t; + +/*! + * This type enumerates the HPS I2C controller instances. + */ +typedef enum ALT_I2C_CTLR_e +{ + ALT_I2C_I2C0 = (int)ALT_I2C0_OFST, /*!< I2C0 instance. */ + ALT_I2C_I2C1 = (int)ALT_I2C1_OFST, /*!< I2C1 instance. */ + ALT_I2C_I2C2 = (int)ALT_I2C2_OFST, /*!< I2C2 instance. */ + ALT_I2C_I2C3 = (int)ALT_I2C3_OFST, /*!< I2C3 instance. */ +} ALT_I2C_CTLR_t; + +/*! + * This type enumerates the modes that the I2C controller may operate in. + * + * NOTE: Each I2C controller must be programmed to operate in either master or + * slave mode only. Operating as a master and slave simultaneously is not + * supported. + */ +typedef enum ALT_I2C_MODE_e +{ + ALT_I2C_MODE_SLAVE = ALT_I2C_CON_MST_MOD_E_DIS, /*!< Slave Mode */ + ALT_I2C_MODE_MASTER = ALT_I2C_CON_MST_MOD_E_EN /*!< Master Mode */ +} ALT_I2C_MODE_t; + +/*! + * This type enumerates the I2C controller operational speed modes. + * + * The I2C controller can operate in standard mode (with data rates 0 to 100 Kbps) + * or fast mode (with data rates less than or equal to 400 Kbps). Additionally, + * fast mode devices are downward compatible. For instance, fast mode devices can + * communicate with standard mode devices in 0 to 100 Kbps I2C bus + * system. However, standard mode devices are not upward compatible and should not + * be incorporated in a fast-mode I2C bus system as they cannot follow the higher + * transfer rate and therefore unpredictable states would occur. + * + * This setting is relevant only if one is operating the I2C in master mode. + */ +typedef enum ALT_I2C_SPEED_e +{ + ALT_I2C_SPEED_STANDARD = ALT_I2C_CON_SPEED_E_STANDARD, + /*!< Standard mode (0 to 100 Kbps) */ + ALT_I2C_SPEED_FAST = ALT_I2C_CON_SPEED_E_FAST + /*!< Fast mode (<= 400 Kbps) */ +} ALT_I2C_SPEED_t; + +/*! + * This type enumerates the two addressing modes formats supported by the I2C + * controller. + * + * The I2C controller does not support mixed address format - that is, a 7-bit + * address transaction followed by a 10-bit address transaction or vice versa - + * combined format transactions. + */ +typedef enum ALT_I2C_ADDR_MODE_e +{ + ALT_I2C_ADDR_MODE_7_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START7, + /*!< 7-Bit Address Format */ + ALT_I2C_ADDR_MODE_10_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 + /*!< 10-Bit Address Format */ +} ALT_I2C_ADDR_MODE_t; + +/*! + * This type enumerates interrupt status conditions for the I2C controller. + */ +typedef enum ALT_I2C_STATUS_e +{ + ALT_I2C_STATUS_RX_UNDER = 1UL << 0, + /*!< Set if the processor attempts to read the + * receive buffer when it is empty. If the I2C + * controller is disabled, this status keeps + * maintains its state until the master or slave + * state machines go into idle, then this + * interrupt is cleared. + */ + ALT_I2C_STATUS_RX_OVER = 1UL << 1, + /*!< Set if the receive buffer is completely + * filled to capacity and an additional byte is + * received from an external I2C device. The I2C + * controller acknowledges this, but any data + * bytes received after the FIFO is full are + * discarded. If the I2C controller is disabled, + * this status maintains its statue until the + * master or slave state machines go into idle, + * then this interrupt is cleared. + */ + ALT_I2C_STATUS_RX_FULL = 1UL << 2, + /*!< Set when the receive buffer reaches or goes + * above the RX_TL threshold. It is + * automatically cleared by hardware when buffer + * level goes below the threshold. If the I2C + * controller is disabled, the RX FIFO is + * flushed and held in reset; therefore the RX + * FIFO is not full. So this bit is cleared once + * the I2C controller is disabled, regardless of + * the activity that continues. + */ + ALT_I2C_STATUS_TX_OVER = 1UL << 3, + /*!< Set during transmit if the transmit buffer is + * filled to capacity and the processor attempts + * to issue another I2C command. When the I2C + * controller is disabled, this bit maintains + * its state until the master or slave state + * machines go into idle, then this interrupt is + * cleared. + */ + ALT_I2C_STATUS_TX_EMPTY = 1UL << 4, + /*!< This bit is set to 1 when the transmit buffer + * is at or below the configured threshold + * value. It is automatically cleared by + * hardware when the buffer level goes above the + * threshold. When the I2C controller is + * disabled, the TX FIFO is flushed and held in + * reset. The TX FIFO appears as if it has no + * data in it, so this bit is set to 1, provided + * there is activity in the master or slave + * state machines. When there is no longer + * activity, then this bit is set to 0. + * + */ + ALT_I2C_STATUS_RD_REQ = 1UL << 5, + /*!< This bit is set to 1 when I2C is acting as a + * slave and another I2C master is attempting to + * read data from the I2C. The I2C holds the bus + * in a wait state until this interrupt is + * serviced, which means that the slave has been + * addressed by a remote master that is asking + * for data to be transferred. The processor + * must respond to this interrupt and then write + * the requested data. This bit is set to 0 just + * after the processor by calling + * alt_i2c_int_clear() with + * ALT_I2C_STATUS_RD_REQ in the mask.. + */ + ALT_I2C_STATUS_TX_ABORT = 1UL << 6, + /*!< This bit indicates if I2C, as an I2C + * transmitter, is unable to complete the + * intended actions on the contents of the + * transmit FIFO. This situation can occur both + * as an I2C master or an I2C slave, and is + * referred to as a 'transmit abort'. When this + * bit is set to 1, the IC_TX_ABRT_SOURCE + * register indicates the reason why the + * transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX + * FIFO whenever this bit is set. The TX FIFO + * remains in this flushed state until the + * register alt_i2c_int_clear() with + * ALT_I2C_STATUS_TX_ABORT in the mask is + * called. Once this happens, the TX FIFO is + * then ready to accept more data bytes from the + * APB interface. + */ + ALT_I2C_STATUS_RX_DONE = 1UL << 7, + /*!< When the I2C is acting as a + * slave-transmitter, this bit is set to 1 if + * the master does not acknowledge a transmitted + * byte. This occurs on the last byte of the + * transmission, indicating that the + * transmission is done. + */ + ALT_I2C_STATUS_ACTIVITY = 1UL << 8, + /*!< This bit captures I2C activity and stays set + * until it is cleared. There are four ways to + * clear it: + * * Disabling the I2C controller + * * Calling alt_i2c_int_clear() with + * ALT_I2C_STATUS_ACTIVITY in the mask. + * * Calling alt_i2c_int_clear() with + * ALT_I2C_STATUS_ALL in the mask. + * * System reset + * + * Once this bit is set, it stays set unless one + * of the four methods is used to clear it. Even + * if the I2C module is idle, this bit remains + * set until cleared, indicating that there was + * activity on the bus. + */ + ALT_I2C_STATUS_STOP_DET = 1UL << 9, + /*!< Indicates whether a STOP condition has + * occurred on the I2C interface regardless of + * whether I2C is operating in slave or master + * mode. + */ + ALT_I2C_STATUS_START_DET = 1UL << 10, + /*!< Indicates whether a START or RESTART + * condition has occurred on the I2C interface + * regardless of whether I2C is operating in + * slave or master mode. + */ + ALT_I2C_STATUS_INT_CALL = 1UL << 11, + /*!< Set only when a General Call address is + * received and it is acknowledged. It stays set + * until it is cleared either by disabling I2C + * or when alt_i2c_int_clear() with + * ALT_I2C_STATUS_CALL in the mask is + * called. I2C stores the received data in the + * Rx buffer. + */ + ALT_I2C_STATUS_INT_ALL = 0xFFF, + /*!< All Combined and Individual Interrupts. This + * enumeration value can be used to clear, + * disable, and enable the combined interrupt + * and all individual interrupt status + * conditions. As a side effect, when passed to + * alt_i2c_int_clear(), clears the source causes + * (\ref ALT_I2C_TX_ABORT_CAUSE_t) of the + * ALT_I2C_STATUS_TX_ABORT condition. + */ +} ALT_I2C_STATUS_t; + +/*! + * This type enumerates the source causes of a ALT_I2C_STATUS_TX_ABORT condition. + * + * The active ALT_I2C_TX_ABORT_CAUSE_t source conditions are cleared when + * alt_i2c_int_clear() with is called ALT_I2C_STATUS_TX_ABORT in the mask or + * alt_i2c_int_clear() is called with ALT_I2C_STATUS_ALL in the mask. + * + * \internal + * Discuss special handling of abrt_sbyte_norstrt TX_ABRT source required in ???() function. + * \endinternal + */ +typedef enum ALT_I2C_TX_ABORT_CAUSE_e +{ + ALT_I2C_TX_ABORT_CAUSE_7B_ADDR_NOACK = 1UL << 0, + /*!< Master Abort 7 Bit Address - If set (1), + * Master is in 7-bit addressing mode and the + * address sent was not acknowledged by any + * slave. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_10ADDR1_NOACK = 1UL << 1, + /*!< Master Abort 10 Bit Address Byte 1 - If set + * (1), Master is in 10-bit address mode and the + * first 10-bit address byte was not + * acknowledged by any slave. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_10ADDR2_NOACK = 1UL << 2, + /*!< Master Abort 10 Bit Address Byte 2 - If set + * (1), Master is in 10-bit address mode and the + * second address byte of the 10-bit address was + * not acknowledged by any slave + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_TXDATA_NOACK = 1UL << 3, + /*!< Master Abort TX NOACK Bit - If set (1), + * Master has received an acknowledgement for + * the address, but when it sent data byte(s) + * following the address, it did not receive an + * acknowledge from the remote slave(s). This is + * a master-mode only bit. + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_GCALL_NOACK = 1UL << 4, + /*!< Master Abort GC Noack Bit - If set (1), I2C + * controller in master mode sent a General Call + * and no slave on the bus acknowledged the + * General Call. + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_GCALL_RD = 1UL << 5, + /*!< Master Abort GC Read Bit - If set (1), I2C + * controller in master mode sent a General Call + * but the user programmed the byte following + * the General Call to be a read from the bus + * (IC_DATA_CMD[9] is set to 1). + * + * Role of I2C: Master-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_HS_ACKDET = 1UL << 6, + /*!< Master HS MC Ack - If set (1), Master is in + * High Speed mode and the High Speed Master + * code was acknowledged (wrong behavior). + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_SBYTE_ACKDET = 1UL << 7, + /*!< Master Abort START Byte - If set (1), Master + * has sent a START Byte and the START Byte was + * acknowledged (wrong behavior). + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_HS_NORSTRT = 1UL << 8, + /*!< Master HS Restart Disabled - If set (1), the + * restart is disabled (IC_RESTART_EN bit + * (IC_CON[5]) = 0) and the user is trying to + * use the master to transfer data in High Speed + * mode. + * + * Role of I2C: Master-Transmitter or + * Master-Receiver + */ + ALT_I2C_TX_ABORT_CAUSE_SBYTE_NORSTRT = 1UL << 9, + /*!< Master Abort START No Restart - To clear, the + * source of the ABRT_SBYTE_NORSTRT must be + * fixed first; restart must be enabled + * (IC_CON[5]=1), the SPECIAL bit must be + * cleared (IC_TAR[11]), or the GC_OR_START bit + * must be cleared (IC_TAR[10]). Once the source + * of the ABRT_SBYTE_NORSTRT is fixed, then this + * bit can be cleared in the same manner as + * other bits in this register. If the source of + * the ABRT_SBYTE_NORSTRT is not fixed before + * attempting to clear this bit, bit 9 clears + * for one cycle and then gets re-asserted. + * + * If set (1), the restart is disabled + * (IC_RESTART_EN bit (IC_CON[5]) = 0) and the + * user is trying to send a START Byte. + * + * Role of I2C: Master. + */ + ALT_I2C_TX_ABORT_CAUSE_10B_RD_NORSTRT = 1UL << 10, + /*!< Master Abort 10 Bit No Restart - If set (1), + * the restart is disabled (IC_RESTART_EN bit + * (IC_CON[5]) = 0) and the master sends a read + * command in 10-bit addressing mode. + * + * Role of I2C: Master Receiver. + */ + ALT_I2C_TX_ABORT_CAUSE_MST_DIS = 1UL << 11, + /*!< Master Operation with Master Disabled - If set + * (1), user tries to initiate a Master + * operation with the Master mode disabled. + * + * Role of I2C: Master or Slave-Receiver. + */ + ALT_I2C_TX_ABORT_CAUSE_ARB_LOST = 1UL << 12, + /*!< Master Abort Arbitration Lost - If set (1), + * master has lost arbitration, or if + * IC_TX_ABRT_SOURCE[14] is also set, then the + * slave transmitter has lost arbitration. Note: + * I2C can be both master and slave at the same + * time. + * + * Role of I2C: Master or Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLVFLUSH_TXFIFO = 1UL << 13, + /*!< Slave Abort Flush TXFIFO - If set (1), Slave + * has received a read command and some data + * exists in the TX FIFO so the slave issues a + * TX_ABRT interrupt to flush old data in TX + * FIFO. + * + * Role of I2C: Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLV_ARBLOST = 1UL << 14, + /*!< Slave Abort Arbitration Lost - If set (1), + * Slave lost the bus while transmitting data to + * a remote master. IC_TX_ABRT_SOURCE[12] is set + * at the same time. + * + * Note: Even though the slave never owns the + * bus, something could go wrong on the + * bus. This is a fail safe check. For instance, + * during a data transmission at the low-to-high + * transition of SCL, if what is on the data bus + * is not what is supposed to be transmitted, + * then DW_apb_i2c no longer own the bus. + * + * Role of I2C: Slave-Transmitter. + */ + ALT_I2C_TX_ABORT_CAUSE_SLVRD_INTX = 1UL << 15 + /*!< Slave Abort Read TX - If set (1), + * when the processor side responds to a + * slave mode request for data to be transmitted + * to a remote master and user writes a 1 in CMD + * (bit 8) of IC_DATA_CMD register. + * + * Role of I2C: Slave-Transmitter. + */ +} ALT_I2C_TX_ABORT_CAUSE_t; + +/*! + * This type defines a structure for configuration of the SCL high and low counts + * to ensure proper I/O timing with the device interface. + * + * The SCL count values are only relevant if the I2C controller is enabled to as + * an I2C master. The SCL count values are ignored when the I2C controller is + * enabled as an I2C slave. + * + * See: Clock Frequency Configuration section of Chapter 20. I2C + * Controller in the Cyclone V Device Handbook Volume 3: Hard + * Processor System Technical Reference Manual for a complete discussion + * of calculation of the proper SCL clock high and low times. + */ +typedef struct ALT_I2C_MASTER_CONFIG_s +{ + ALT_I2C_ADDR_MODE_t addr_mode; + /*!< The address mode (7 or 10 bit) when + * acting as a master. + */ + bool restart_enable; + /*!< This setting determines whether RESTART + * conditions may be sent when acting as a + * master. When the \e restart_enable is + * false, the I2C controller master is + * incapable of performing the following + * functions: + * * Sending a START BYTE + * * Performing any high-speed mode + * operation + * * Performing direction changes in + * combined format mode + * * Performing a read operation with a + * 10-bit address + */ + ALT_I2C_SPEED_t speed_mode; + /*!< The speed mode of the I2C operation. + */ + uint16_t ss_scl_hcnt; + /*!< The SCL clock high-period count for + * standard speed. + */ + uint16_t ss_scl_lcnt; + /*!< The SCL clock low-period count for + * standard speed. + */ + uint16_t fs_scl_hcnt; + /*!< The SCL clock high-period count for fast + * speed. + */ + uint16_t fs_scl_lcnt; + /*!< The SCL clock low-period count for fast + * speed. + */ + uint8_t fs_spklen; + /*!< The duration, measured in ic_clk cycles, + * of the longest spike that is filtered out + * by the spike suppression logic when the + * component is operating in SS or FS modes. + */ +} ALT_I2C_MASTER_CONFIG_t; + +/*! + * This type defines a structure for configuration of the I2C controller when it + * is operating in slave mode. + */ +typedef struct ALT_I2C_SLAVE_CONFIG_s +{ + ALT_I2C_ADDR_MODE_t addr_mode; /*!< The address mode (7 or 10 bit) when + * acting as a slave. + */ + uint32_t addr; /*!< The slave address to which the I2C + * controller responds when acting as a + * slave. + */ + bool nack_enable; /*!< Enable generation of a NACK. when the + * I2C controller is a + * slave-receiver. If \b true, it can + * only generate a NACK after a data + * byte is received; hence, the data + * transfer is aborted and the data + * received is not pushed onto the + * receive buffer. When \b false, it + * generates NACK/ACK, depending on + * normal criteria. + * * \b true = generate NACK after data + * byte received + * * \b false = generate NACK/ACK normally + */ +} ALT_I2C_SLAVE_CONFIG_t; + +/*! + * Initialize the specified I2C controller instance for use and return a device + * handle referencing it. + * + * \param i2c + * The HPS I2C controller instance to initialize. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Initialization process: + * * Initialize internal driver state + * * Check clock setup (ALT_CLK_L4_SP) + * * Take I2C instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial I2C controller state + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_init(const ALT_I2C_CTLR_t i2c, ALT_I2C_DEV_t *i2c_dev); + +/*! + * Reset the specified I2C controller instance for use. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Reset process: + * * Disable controller + * * Initialize internal driver state + * * Check clock setup (ALT_CLK_L4_SP) + * * Take I2C instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial I2C controller state + * * Enable controller + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_reset(ALT_I2C_DEV_t * i2c_dev); + +/*! + * Uninitialize the I2C controller referenced by the \e i2c_dev handle. + * + * This function attempts to gracefully shutdown the I2C controller by waiting for + * any inpcomplete transactions to finish and then putting the I2C controller into + * reset. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_uninit(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Disables the I2C controller. + * + * When the I2C controller is disabled, the following occurs: + * * The TX FIFO and RX FIFO get flushed. + * * The I2C interrupt status conditions remain active until the I2C controller + * goes into IDLE state. + * + * If the controller is transmitting, it stops as well as deletes the contents of + * the transmit buffer after the current transfer is complete. If the module is + * receiving, the controller stops the current transfer at the end of the current + * byte and does not acknowledge the transfer. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE = 0 + * Follow the procedure in section 3.8.3 Disabling DW_apb_i2c of the DW Databook. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_disable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Enables the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_enable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE if the I2C controller is enabled. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ENABLE.ENABLE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_is_enabled(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Gets the current configuration of the I2C controller when operating in master + * mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_I2C_MASTER_CONFIG_t structure for holding + * the returned I2C master mode configuration parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t* cfg); + +/*! + * Sets the configuration of the I2C controller with operational parameters for + * operating in master mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * Pointer to a ALT_I2C_MASTER_CONFIG_t structure holding the desired + * I2C master mode operational parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg); + +/*! + * This is a utility function that returns the speed based on parameters of the + * I2C master configuration. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * A pointer to the master confugurations. + * + * \param speed_in_hz + * [out] Speed (Hz) of the I2C bus currently configured at. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_master_config_speed_get(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MASTER_CONFIG_t* cfg, + uint32_t * speed_in_hz); + +/*! + * This is a utility function that computes parameters for the I2C master + * configuration that best matches the speed requested. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * A pointer to the master confugurations. + * + * \param speed_in_hz + * Speed (Hz) of the I2C bus to configure. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_config_speed_set(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MASTER_CONFIG_t * cfg, + uint32_t speed_in_hz); + +/*! + * Definition included for backwards compatibility. + */ +#define alt_i2c_cfg_to_speed(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_get((i2c_dev), (cfg), (speed_in_hz)) + +/*! + * Definition included for backwards compatibility. + */ +#define alt_i2c_speed_to_cfg(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_set((i2c_dev), (cfg), (speed_in_hz)) + +/*! + * Gets the current configuration of the I2C controller when operating in slave + * mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_I2C_SLAVE_CONFIG_t structure for holding + * the returned I2C slave mode configuration parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_config_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_SLAVE_CONFIG_t* cfg); + +/*! + * Sets the configuration of the I2C controller with operational parameters for + * operating in slave mode. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cfg + * Pointer to a ALT_I2C_SLAVE_CONFIG_t structure holding the desired + * I2C slave mode operational parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_config_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_SLAVE_CONFIG_t* cfg); + +/*! \addtogroup ALT_I2C_SDA_HOLD SDA Hold Time Configuration + * + * The I2C protocol specification requires 300ns of hold time on the SDA signal in + * standard and fast speed modes. Board delays on the SCL and SDA signals can mean + * that the hold-time requirement is met at the I2C master, but not at the I2C + * slave (or vice-versa). Because each system may encounter differing board signal + * delays, the I2C controller provides the capability to adjust of the SDA + * hold-time. + * + * The functions in this section provide software configuration of SDA hold time + * for the I2C controller. + * + * @{ + */ + +/*! + * Gets the currently configured value for the SDA hold time in I2C controller + * clock (\ref ALT_CLK_L4_SP) clock ticks. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param hold_time + * [out] The configured SDA hold time in \ref ALT_CLK_L4_SP clock + * ticks. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_sda_hold_time_get(ALT_I2C_DEV_t *i2c_dev, + uint16_t *hold_time); + +/*! + * Sets the configured value for the SDA hold time in terms of I2C controller + * clock (\ref ALT_CLK_L4_SP) clock ticks. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param hold_time + * The SDA hold time in \ref ALT_CLK_L4_SP clock ticks. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_SDA_HOLD is 16 bits wide. hold_time must be in range 0..65535. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_sda_hold_time_set(ALT_I2C_DEV_t *i2c_dev, + const uint16_t hold_time); + +/*! @} */ + +/*! + * Gets the current operational mode of the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mode + * [out] The current operational mode enabled for the I2C + * controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_op_mode_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_MODE_t* mode); + +/*! + * Sets the operational mode of the I2C controller. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mode + * The operational mode to enable for the I2C controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_op_mode_set(ALT_I2C_DEV_t *i2c_dev, + const ALT_I2C_MODE_t mode); + +/*! + * Returns ALT_E_TRUE if the I2C controller is busy. The I2C controller is busy if + * either the Slave Finite State Machine (FSM) is not in the IDLE state or the + * Master Finite State Machine (FSM) is not in the IDLE state. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.ACTIVITY == 1 + * NOTE: IC_STATUS[0] that is, the ACTIVITY bit is the OR of SLV_ACTIVITY and + * MST_ACTIVITY bits. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_is_busy(ALT_I2C_DEV_t *i2c_dev); + +/*! + * This function reads a single data byte from the receive FIFO. + * + * This function is used to perform low level access to the data bytes + * received by the I2C controller and buffered in the receive FIFO. It + * may be used by master-receivers or slave receivers. + * + * This function does not check for valid data in the receive FIFO + * beforehand and may cause an underflow if improperly used. It is + * meant to be called from a context where preconditions have been + * previously asserted such as in the implementation of the + * alt_i2c_slave_receive() or alt_i2c_master_receive() function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param val + * [out] The single data byte read from the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_read(ALT_I2C_DEV_t *i2c_dev, uint8_t *val); + +/*! + * This function writes a single data byte to the transmit FIFO. + * + * This function is used to perform low level writes of data to the + * transmit FIFO for transmission by the I2C controller. It may be + * used by slave receivers. + * + * This function does not check whether the transmit FIFO is full or + * not beforehand and may cause an overflow if improperly used. It is + * meant to be called from a context where preconditions have been + * previously asserted such as in the implementation of the + * alt_i2c_slave_transmit() function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param val + * The data byte to write to the transmission FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_write(ALT_I2C_DEV_t *i2c_dev, const uint8_t val); + +/*! + * This function acts in the role of a slave-receiver by receiving a single data + * byte from the I2C bus in response to a write command from the master. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is data in the RX FIFO to + * accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * [out] A pointer to a buffer to contain the received data byte. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_receive(ALT_I2C_DEV_t *i2c_dev, + uint8_t *data); + +/*! + * This function acts in the role of a slave-transmitter by transmitting a single + * data byte to the I2C bus in response to a read request from the master. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * The data byte to transmit. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_transmit(ALT_I2C_DEV_t *i2c_dev, + const uint8_t data); + +/*! + * This function acts in the role of a slave-transmitter by transmitting data in + * bulk to the I2C bus in response to a series of read requests from a master. + * + * In the standard I2C protocol, all transactions are single byte transactions and + * the slave responds to a remote master read request by writing one byte into the + * slave's TX FIFO. When a slave (slave-transmitter) is issued with a read request + * from the remote master (master-receiver), at a minimum there should be at least + * one entry placed into the slave-transmitter's TX FIFO. The I2C controller is + * capable of handling more data in the TX FIFO so that subsequent read requests + * can receive that data without raising an interrupt or software having to poll + * to request more data. This eliminates overhead latencies from being incurred by + * servicing the interrupt or polling for data requests each time had there been a + * restriction of having only one entry placed in the TX FIFO. + * + * If the remote master acknowledges the data sent by the slave-transmitter and + * there is no data in the slave's TX FIFO, the I2C controller raises the read + * request interrupt and waits for data to be written into the TX FIFO before it + * can be sent to the remote master. + * + * If the programmer knows in advance that the master is requesting a packet of \e + * n bytes, then when another master request for data is received, the TX FIFO + * could be written with \e n number bytes and the master receives it as a + * continuous stream of data. For example, the slave continues to send data to the + * master as long as the master is acknowledging the data sent and there is data + * available in the TX FIFO. There is no need to hold the SCL line low or to issue + * READ request again. + * + * If the remote master is to receive \e n bytes from the slave but the programmer + * wrote a number of bytes larger than \e n to the TX FIFO, then when the slave + * finishes sending the requested \e n bytes, it clears the TX FIFO and ignores + * any excess bytes. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * The I2C controller must be in slave mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * A pointer to the data buffer to transmit. + * + * \param size + * The size of the data buffer in bytes to place in the TX FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * See: Section Slave-Transfer Operation for Bulk Transfers of the DW + * Databook for details of implementation and error conditions that may occur. + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_slave_bulk_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size); + +/*! + * This function returns the current target address. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param target_addr + * [out] The 7 or 10 bit slave target address. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_i2c_master_target_get(ALT_I2C_DEV_t * i2c_dev, uint32_t * target_addr); + +/*! + * This function updates the target slave address for any upcoming I2C bus IO. + * + * This API is not suitlabe for being called in an interrupt context as it + * will wait for the TX FIFO to flush before applying the changes. If the TX + * FIFO is known to be empty and the controller idle, then it can be safely + * called. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param target_addr + * The 7 or 10 bit slave target address. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code. + */ +ALT_STATUS_CODE alt_i2c_master_target_set(ALT_I2C_DEV_t * i2c_dev, uint32_t target_addr); + +/*! + * This function acts in the role of a master-transmitter by issuing a write + * command and transmitting data to the I2C bus. + * + * This API is not suitable for being called in an interrupt context as it may + * wait for certain controller states before completing. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * A pointer to a data buffer to transmit + * + * \param size + * The size of the data buffer in bytes to place in the TX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_transmit(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function acts in the role of a master-receiver by receiving one or more + * data bytes transmitted from a slave in response to read requests issued from + * this master. + * + * This function causes the master to issue the required number of read requests + * to the slave and read the received data bytes from the Rx FIFO. + * + * The \e issue_restart and \e issue_stop parameters apply to the final read + * request transaction in the \e num_data_entries sequence required to fulfill the + * aggregate receive request. + * + * This API is not suitable for being called in an interrupt context as it may + * wait for certain controller states before completing. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * [out] The data buffer to receive the requested \e size bytes. + * + * \param size + * The size of the data buffer to read from the RX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_receive(ALT_I2C_DEV_t *i2c_dev, + void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function causes the I2C controller master to issue a READ request on the + * bus. This function is typically used during master-receiver transfers. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Write IC_DATA_CMD.CMD = 1 (read request). IC_DATA_CMD.DAT is + * written with "don't care" values as these bits are ignored by the + * I2C controller . + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_issue_read(ALT_I2C_DEV_t *i2c_dev, + const bool issue_restart, + const bool issue_stop); + +/*! + * This function causes the I2C controller master to issue a send byte on the + * bus. This function is typically used during master-transmitter/slave-transmitter + * transfers. + * + * The I2C controller must be in master mode before calling this function. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param value + * The data item to be transmitted. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Write IC_DATA_CMD.CMD = 0 (write request). + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_issue_write(ALT_I2C_DEV_t *i2c_dev, + const uint8_t value, + const bool issue_restart, + const bool issue_stop); + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_GEN_CALL General Call + * + * The functions in this group support General Call addresses. + * + * The general call address is for addressing every device connected to the I2C + * bus at the same time. However, if a device does not need any of the data + * supplied within the general call structure, it can ignore this address by not + * issuing an acknowledgment. If a device does require data from a general call + * address, it acknowledges this address and behaves as a slave-receiver. The + * master does not actually know how many devices acknowledged if one or more + * devices respond. The second and following bytes are acknowledged by every + * slave-receiver capable of handling this data. A slave who cannot process one of + * these bytes must ignore it by not-acknowledging. If one or more slaves + * acknowledge, the not-acknowledge will not be seen by the master. + * + * The functions in this group do not provide any general call functional command + * interpretation or implementation (e.g. software reset). + * + * @{ + */ + +/*! + * This function acts in the role of a master-transmitter by issuing a general + * call command to all devices connected to the I2C bus. + * + * The \e issue_restart and \e issue_stop parameters apply to the final write + * transaction in the \e num_data_entries byte transmission sequence. + * + * The I2C controller must be in master mode before calling this function. + * + * The target slave address will be modified by this function. Call + * alt_i2c_master_target_set() to reset the slave target address for + * subsequent IO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param data + * An array of data byte(s) to transmit. + * + * \param num_data_entries + * The number of entries (bytes) in \e data to place in the TX FIFO. + * + * \param issue_restart + * This parameter controls whether a RESTART is issued before the + * byte is sent or received. If: + * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued before the data is sent/received + * (according to the value of CMD), regardless of whether or not + * the transfer direction is changing from the previous command; if + * \e restart_enabled is \b false, a STOP followed by a START is + * issued instead. + * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t + * is \b true, a RESTART is issued only if the transfer direction + * is changing from the previous command; if \e restart_enabled is + * \b false, a STOP followed by a START is issued instead. + * + * \param issue_stop + * This parameter controls whether a STOP is issued after the byte is + * sent or received. If: + * * \b true - STOP is issued after this byte, regardless of whether or + * not the Tx FIFO is empty. If the Tx FIFO is not empty, the + * master immediately tries to start a new transfer by issuing a + * START and arbitrating for the bus. + * * \b false - STOP is not issued after this byte, regardless of + * whether or not the Tx FIFO is empty. If the Tx FIFO is not + * empty, the master continues the current transfer by + * sending/receiving data bytes according to the value of the CMD + * bit. If the Tx FIFO is empty, the master holds the SCL line low + * and stalls the bus until a new command is available in the Tx + * FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_master_general_call(ALT_I2C_DEV_t *i2c_dev, + const void * data, + const size_t size, + const bool issue_restart, + const bool issue_stop); + +/*! + * Disables the I2C controller from responding to a General Call address. The + * controller will respond with a NACK and no General Call status conditions or + * interrupts are generated. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_disable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Enables the I2C controller to respond with an ACK when it receives a General + * Call address. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_enable(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE if the I2C controller is enabled to respond to General Call + * addresses. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_ACK_GENERAL_CALL.ACK_GEN_CALL == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_general_call_ack_is_enabled(ALT_I2C_DEV_t *i2c_dev); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_INT Interrupt and Status Conditions + * + * The functions in this group provide management for the I2C controller status + * conditions and interrupts. + * + * Each I2C controller has a single combined interrupt output (\b + * ALT_INT_INTERRUPT_I2Cn_IRQ). The following events can generate an + * interrupt: + * * General Call Address Received + * * Start or Restart Condition Occurred + * * Stop Condition Occurred + * * I2C Controller Activity + * * Receive Done + * * Transmit Abort + * * Read Request + * * Transmit Buffer Empty + * * Transmit Overflow + * * Receive Buffer Full + * * Receive Overflow + * * Receive Underflow + * + * These interrupt status conditions may be monitored either by polling their + * status or by configuring interrupt handlers using the HWLIB Interrupt + * Controller API. + * + * Functions to get the current status, enable or disable (i.e. mass or unmask), + * and clear interrupt status conditions for the I2C controller are defined in + * this section. + * + * @{ + */ + +/*! + * Returns the current I2C controller interrupt status conditions. + * + * This function returns the current value of the I2C controller interrupt status + * register value which reflects the current I2C controller status conditions that + * are not disabled (i.e. masked). + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_INTR_STAT + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status); + +/*! + * Returns the I2C controller raw interrupt status conditions irrespective of + * the interrupt status condition enablement state. + * + * This function returns the current value of the I2C controller raw interrupt + * status register value which reflects the current I2C controller status + * conditions regardless of whether they are disabled (i.e. masked) or not. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_INTR_STAT + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_raw_status_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *status); + +/*! + * Clears the specified I2C controller interrupt status conditions identified + * in the mask. + * + * This function clears one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the QSPI interrupt status conditions to clear. \e mask + * is a mask of logically OR'ed \ref ALT_I2C_STATUS_t values that + * designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_clear(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Disable the specified I2C controller interrupt status conditions identified in + * the mask. + * + * This function disables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b + * ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. The function + * alt_i2c_int_enable() is used to enable status source conditions. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_I2C_STATUS_t values that designate the status conditions to + * disable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_disable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Enable the specified I2C controller interrupt status conditions identified in + * the mask. + * + * This function enables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b + * ALT_INT_INTERRUPT_I2Cn_IRQ interrupt signal state. The function + * alt_i2c_int_disable() is used to disable status source conditions. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_I2C_STATUS_t values that designate the status conditions to + * enable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_int_enable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); + +/*! + * Gets the cause of I2C transmission abort. A I2C transmission abort indicates + * that the I2C transmitter is unable to complete the intended actions on the + * contents of the transmit FIFO. This situation can occur both as an I2C master + * or an I2C slave, and is referred to as a "transmit abort". + * + * The returned value of this function is the value of the IC_TX_ABRT_SOURCE + * register which indicates the cause why the transmit abort occurred. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param cause + * [out] A pointer to a bit mask of the \ref ALT_I2C_TX_ABORT_CAUSE_t + * causes of the transmission abort. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_ABRT_SOURCE + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_abort_cause_get(ALT_I2C_DEV_t *i2c_dev, + ALT_I2C_TX_ABORT_CAUSE_t *cause); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_RX_FIFO RX FIFO Management + * + * The receive FIFO has a configurable threshold value that controls the level of + * entries (or above) that sets the RX_FULL status condition and triggers an + * interrupt. The valid range is 0 - (ALT_I2C_RX_FIFO_NUM_ENTRIES-1), with the + * additional restriction that I2C controller does not allow this value to be set + * to a value larger than the depth of the buffer. If an attempt is made to do + * that, the actual value set will be the maximum depth of the buffer. A value of + * 0 sets the threshold for 1 entry, and a value of (ALT_I2C_RX_FIFO_NUM_ENTRIES-1) + * sets the threshold for ALT_I2C_RX_FIFO_NUM_ENTRIES entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the I2C controller receive FIFO. + */ +#define ALT_I2C_RX_FIFO_NUM_ENTRIES 64 + +/*! + * Returns ALT_E_TRUE when the receive FIFO is empty. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.RFNE == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE when the receive FIFO is completely full. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.RFF == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns the number of valid entries in the receive FIFO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param num_entries + * [out] The number of entries in the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RXFLR.RXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries); + +/*! + * Gets the current receive FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold); + +/*! + * Sets the current receive FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_TX_FIFO TX FIFO Management + * + * The transmit FIFO has a configurable threshold value that controls the level of + * entries (or below) that sets the TX_EMPTY status condition and triggers an + * interrupt. The valid range is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES-1), with the + * additional restriction that I2C controller does not allow this value to be set + * to a value larger than the depth of the buffer. If an attempt is made to do + * that, the actual value set will be the maximum depth of the buffer. A value of + * 0 sets the threshold for 0 entries, and a value of (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) + * sets the threshold for (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the I2C controller transmit FIFO. + */ +#define ALT_I2C_TX_FIFO_NUM_ENTRIES 64 + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is empty. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.TFE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is completely full. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_STATUS.TFNF == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); + +/*! + * Returns the number of valid entries in the transmit FIFO. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param num_entries + * [out] The number of entries in the transmit FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TXFLR.TXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, + uint32_t *num_entries); + +/*! + * Gets the current transmit FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, + uint8_t *threshold); + +/*! + * Sets the current transmit FIFO threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_I2C_DMA DMA Interface + * + * The DMA interface has a configurable threshold value that controls the + * level of entries that triggers the burst handshaking request used for DMA + * integration. + * + * For the TX threshold, if the number of entries in the TX FIFO is at or + * below the set threshold, a DMA handshaking request will be made. The valid + * range for the TX threshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). + * + * For the RX threshold, if the number of entries in the RX FIFO is above the + * set threshold, a DMA handshaking request will be made. The valid range for + * the RX treshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). + * + * Having a higher threshold can improve the AXI bus utilization at the + * expense of the likelyhoold of overflow / underflow conditions. + * @{ + */ + +/*! + * Gets the current RX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); + +/*! + * Sets the current RX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_rx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); + +/*! + * Gets the current TX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * [out] The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); + +/*! + * Sets the current TX DMA threshold level value. + * + * \param i2c_dev + * A pointer to the I2C controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_i2c_tx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_I2C_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_interrupt.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_interrupt.h new file mode 100644 index 000000000..85e9c1b60 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_interrupt.h @@ -0,0 +1,1039 @@ +/*! + * Altera - SoC Interrupt Manager - Secure interface + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_INT_H__ +#define __ALT_INT_H__ + +#ifdef __ALT_INT_NS_H__ +#error Secure and Non-Secure interrupt API cannot be used together. +#endif + +#include "alt_interrupt_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup INT_LL Interrupt Controller Low-Level API [Secure] + * + * This module defines the Interrupt Low-Level API for accessing, configuring, + * and controlling interrupts for SoC. + * + * The following reference materials was used in the design of this API: + * * Cortex™-A9 Technical Reference Manual + * * Cortex™-A9 MPCore® Technical Reference Manual + * * ARM® Generic Interrupt Controller Architecture, Version 1.0 + * Architecture Specification + * + * @{ + */ + +/*! + * \addtogroup INT_LL_DEFINE Interrupt Controller Preprocessor Defines \ + * [Secure] + * + * This group of APIs configures the compile time options for the Interrupt + * API or provides information about the Interrupt API. It allows the + * interrupt API to be integrated with operating systems which already + * provides interrupt support. + * + * @{ + */ + +/*! + * This preprocessor definition determines if the Mentor toolchain's interrupt + * vector table symbol should be used. If a vector table is already provided + * somewhere else, it is not necessary to have multiple vector tables. + * + * To use another interrupt vector, define ALT_INT_PROVISION_CPU_COUNT=(0) in + * the Makefile. To connect to the interrupt handling system, configure the + * ARM IRQ interrupt to call alt_int_handler_irq() in the custom solution. In + * this case, compiler support for interrupt handler entry and exit sequences + * will not be added. + */ +#ifndef ALT_INT_PROVISION_VECTOR_SUPPORT +#define ALT_INT_PROVISION_VECTOR_SUPPORT (1) +#endif + +/*! + * This preprocessor definition determines if the stack space for interrupts + * should be configured by the Interrupt API. If that space is already + * configured somewhere else, it is not necessary to provide another stack + * space. + * + * If the interrupt stack is already configured, define + * ALT_INT_PROVISION_STACK_SUPPORT=(0) in the Makefile. + */ +#ifndef ALT_INT_PROVISION_STACK_SUPPORT +#define ALT_INT_PROVISION_STACK_SUPPORT (1) +#endif + +/*! + * This preprocessor definition determines the size of the interrupt stack if + * interrupt stack provisioning is requested. The same stack size will be + * provisioned for each CPU if multiple CPUs are provisioned. While the + * default should provide more than adequate space for most use cases, if + * interrupt servicing routines are complicated or uses a lot of stack, the + * stack provisioned can be adjusted to be larger. The stack size can also be + * adjust smaller to reduce the memory used. Stack sizes should be a multiple + * of 32. + * + * To specify another interrupt stack size, ALT_INT_PROVISION_STACK_SIZE + * should be defined to a multiple of 32 in the Makefile. + */ +#ifndef ALT_INT_PROVISION_STACK_SIZE +#define ALT_INT_PROVISION_STACK_SIZE (4096) +#endif + +/*! + * This preprocessor definition determines the total number of interrupts that + * the Interrupt API should support. The default value is corresponds to the + * number of interrupts defined in the hardware. Valid values are multiples of + * 16. + * + * This preprocessor definition should not be redefined in the Makefile. + */ +#define ALT_INT_PROVISION_INT_COUNT (256) + +/*! + * This preprocessor definition determines the total number of CPUs that the + * Interrupt API should support. For the SoC FPGA, the definition should be + * limited to values of 1 or 2 as it is a dual CPU ARM core. Provisioning more + * CPUs than is used trivially impact performance but may impact the amount of + * memory used more. + * + * To control the number of CPUs to provision for, define + * ALT_INT_PROVISION_CPU_COUNT in the Makefile. + */ +#ifndef ALT_INT_PROVISION_CPU_COUNT +#define ALT_INT_PROVISION_CPU_COUNT (1) +#endif + +/*! + * @} + */ + +/*! + * \addtogroup INT_LL_GLOBAL Interrupt Controller Global Interface [Secure] + * + * This group of APIs provide access, configuration, and control of the + * interrupt controller global functions when in the Secure state. + * + * @{ + */ + +/*! + * Performs the initialization steps needed by the interrupt controller + * system. This should be the first API calls made when using the interrupt + * controller API. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_global_init(void); + +/*! + * Performs the uninitialization steps needed by the interrupt controller + * system. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_global_uninit(void); + +/*! + * Enables all secure interrupt forwarding from the interrupt controller to + * the CPU interfaces. + * + * The interrupt controller monitors all secure interrupt signals and forwards + * pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_global_enable(void); + +/*! + * Disables all secure interrupt forwarding from the interrupt controller to + * the CPU interfaces. + * + * The interrupt controller ignores all secure interrupt signals and does not + * forward pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_global_disable(void); + +/*! + * Enables all non-secure interrupt forwarding from the interrupt controller to + * the CPU interfaces using the secure interface. + * + * The interrupt controller monitors all non-secure interrupt signals and + * forwards pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_global_enable_ns(void); + +/*! + * Disables all non-secure interrupt forwarding from the interrupt controller to + * the CPU interfaces using the secure interface. + * + * The interrupt controller ignores all non-secure interrupt signals and does + * not forward pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_global_disable_ns(void); + +/*! + * Enables all secure and non-secure interrupt forwarding from the interrupt + * controller to the CPU interfaces using the secure interface. + * + * The interrupt controller monitors all secure and non-secure interrupt + * signals and forwards pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_global_enable_all(void); + +/*! + * Disables all secure and non-secure interrupt forwarding from the interrupt + * controller to the CPU interfaces using the secure interface. + * + * The interrupt controller ignores all secure and non-secure interrupt + * signals and does not forward pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_global_disable_all(void); + +/*! + * @} + */ + +/*! + * \addtogroup INT_LL_DIST Interrupt Controller Distributor Interface [Secure] + * + * This group of APIs provide access, configuration, and control of the + * Generic Interrupt Controller (GIC) Distributor interface when in the + * Secure state. + * + * @{ + */ + +/*! + * Enable the specified interrupt for secure operation. + * + * This function configures the interrupt as Secure. + * + * All interrupts are secure by default. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_secure_enable(ALT_INT_INTERRUPT_t int_id); + +/*! + * Disable the specified interrupt from secure operation. + * + * This function configures the interrupt as non-secure. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_secure_disable(ALT_INT_INTERRUPT_t int_id); + +/*! + * Returns \b true if the specified interrupt is enabled for secure operation + * and \b false otherwise. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \retval ALT_E_TRUE Interrupt is Secure. + * \retval ALT_E_FALSE Interrupt is Non-Secure. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_is_secure(ALT_INT_INTERRUPT_t int_id); + + +/*! + * Enable the specified interrupt to be forwarded to the CPU interface. + * + * For Software Generated Interrupts (SGI) (interrupts 0 - 15) and Private + * Peripheral Interrupt (PPI) (interrupts 16 - 32), interrupts must be enabled + * on each CPU that will service the interrupt. This is done by calling this + * API when executing on that CPU. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_enable(ALT_INT_INTERRUPT_t int_id); + +/*! + * Disables the specified interrupt from being forwarded to the CPU interface. + * + * For Software Generated Interrupts (SGI) (interrupts 0 - 15) and Private + * Peripheral Interrupt (PPI) (interrupts 16 - 32), interrupts must be + * disabled on each CPU that will no longer service the interrupt. This is + * done by calling this API when executing on that CPU. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_disable(ALT_INT_INTERRUPT_t int_id); + +/*! + * Return \b true if the specified interrupt is enabled and \b false + * otherwise. + * + * For Software Generated Interrupts (SGI) (interrupts 0 - 15) and Private + * Peripheral Interrupt (PPI) (interrupts 16 - 32), interrupts must be + * queried on each CPU that may service the interrupt. This is done by + * calling this API when executing on that CPU. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \retval ALT_E_TRUE Interrupt is enabled. + * \retval ALT_E_FALSE Interrupt is disabled. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_is_enabled(ALT_INT_INTERRUPT_t int_id); + + +/*! + * Set the pending status of the specified peripheral interrupt. + * + * This API is not valid for Software Generated Interrupts (SGI) + * (interrupts 0 - 15). + * + * For Private Peripheral Interrupt (PPI) (interrupts 16 - 32), pending is set + * on a per CPU basis. This is done by calling this API when executing on that + * CPU. + * + * \param int_id + * The interrupt identifier. All peripheral interrupts are valid, + * 16 - 1019. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_pending_set(ALT_INT_INTERRUPT_t int_id); + +/*! + * Clear the pending status of the specified peripheral interrupt. + * + * This API is not valid for Software Generated Interrupts (SGI) + * (interrupts 0 - 15). + * + * For Private Peripheral Interrupt (PPI) (interrupts 16 - 32), pending is + * cleared on a per CPU basis. This is done by calling this API when executing + * on that CPU. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 16 - 1019. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_pending_clear(ALT_INT_INTERRUPT_t int_id); + +/*! + * Returns \b true if the specified interrupt is pending or active and + * pending, otherwise returns \b false. + * + * For Software Generated Interrupts (SGI) (interrupts 0 - 15) and Private + * Peripheral Interrupt (PPI) (interrupts 16 - 32), is pending is queried on a + * per CPU basis. This is done by calling this API when executing on that CPU. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \retval ALT_E_TRUE The specified interrupt is pending or active + * and pending. + * \retval ALT_E_FALSE The specified interrupt is not pending and is + * not active and pending. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_is_pending(ALT_INT_INTERRUPT_t int_id); + +/*! + * Returns \b true if the specified interrupt is active or active and pending, + * otherwise returns \b false. + * + * For Software Generated Interrupts (SGI) (interrupts 0 - 15) and Private + * Peripheral Interrupt (PPI) (interrupts 16 - 32), is active is queried on a + * per CPU basis. This is done by calling this API when executing on that CPU. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \retval ALT_E_TRUE The specified interrupt is active or active + * and pending. + * \retval ALT_E_FALSE The specified interrupt is not active and is + * not active and pending. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_is_active(ALT_INT_INTERRUPT_t int_id); + + +/*! + * Get the priority field value of the specified interrupt. + * + * Higher priority corresponds to a lower priority field value. + * + * For Software Generated Interrupts (SGI) (interrupts 0 - 15) and Private + * Peripheral Interrupt (PPI) (interrupts 16 - 32), priority is queried on a + * per CPU basis. This is done by calling this API when executing on that CPU. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \param priority + * [out] Pointer to an output parameter that contains the + * interrupt priority. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_priority_get(ALT_INT_INTERRUPT_t int_id, + uint32_t * priority); + +/*! + * Sets the priority field value of the specified interrupt. + * + * Higher priority corresponds to a lower priority field value. + * + * For Software Generated Interrupts (SGI) (interrupts 0 - 15) and Private + * Peripheral Interrupt (PPI) (interrupts 16 - 32), priority is set on a per + * CPU basis. This is done by calling this API when executing on that CPU. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \param priority + * The interrupt priority. Valid values are 0 - 255. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier and / or + * priority value is invalid. + */ +ALT_STATUS_CODE alt_int_dist_priority_set(ALT_INT_INTERRUPT_t int_id, + uint32_t priority); + + +/*! + * Get the processor target list for the specified interrupt. + * + * For Software Generated Interrupts (SGI) (interrupts 0 - 15) and Private + * Peripheral Interrupt (PPI) (interrupts 16 - 32), get target will return a + * set corresponding to the current CPU. + * + * \param int_id + * The interrupt identifier. All interrupts are valid, 0 - 1019. + * + * \param target + * [out] Pointer to an output parameter that contains the set of + * CPU(s) servicing the interrupt. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_target_get(ALT_INT_INTERRUPT_t int_id, + alt_int_cpu_target_t * target); + +/*! + * Sets the the list of processors that the interrupt is sent to if it is + * asserted. This function is only valid for Shared Peripheral Interrupts + * (SPI). + * + * \param int_id + * The interrupt identifier. Only SPI are valid, 32 - 1019. + * + * \param target + * The set of CPUs which will handle the interrupt. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier and / or target + * list is invalid. + */ +ALT_STATUS_CODE alt_int_dist_target_set(ALT_INT_INTERRUPT_t int_id, + alt_int_cpu_target_t target); + + +/*! + * Get the configured trigger type for the specified Private Peripheral + * Interrupt (PPI) or Shared Peripheral Interrupt (SPI). + * + * For PPI (interrupts 16 - 32), triggering is queried on a per CPU basis. + * This is done by calling this API when executing on that CPU. + * + * \param int_id + * The interrupt identifier. Only PPI and SPI are valid, + * 16 - 1019. + * + * \param trigger_type + * [out] Pointer to an output parameter that contains the trigger + * type of the interrupt. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier is invalid. + */ +ALT_STATUS_CODE alt_int_dist_trigger_get(ALT_INT_INTERRUPT_t int_id, + ALT_INT_TRIGGER_t * trigger_type); + +/*! + * Sets the trigger type for the specified interrupt Private Peripheral + * Interrupt (PPI) or Shared Peripheral Interrupt (SPI). + * + * For PPI (interrupts 16 - 32), triggering is set on a per CPU basis. This is + * done by calling this API when executing on that CPU. + * + * \param int_id + * The interrupt identifier. Only PPI and SPI are valid, + * 16 - 1019. + * + * \param trigger_type + * A parameter value which specifies the type of triggering to + * configure the given interrupt as. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier and / or other + * configuration is invalid. + */ +ALT_STATUS_CODE alt_int_dist_trigger_set(ALT_INT_INTERRUPT_t int_id, + ALT_INT_TRIGGER_t trigger_type); + +/*! + * @} + */ + +/*! + * \addtogroup INT_LL_SGI Software Generated Interrupts [Secure] + * + * Software Generated Interrupts (SGI) + * + * An SGI can specify multiple processors in its target list. The target list + * may be further refined by a target filter that designates: + * * interrupting only the processor that initiates the SGI + * * interrupting all processors other than the one that initiates the SGI + * * interrupting the processor initiating the SGI + * + * SGIs from different processors use the same interrupt IDs. Therefore, any + * target processor can receive SGIs with the same interrupt ID from different + * processors. On the CPU interface of the target processor, the pending + * status of each of these interrupts is independent of the pending status of + * any other interrupt, but only one interrupt with this ID can be active. + * Reading the Interrupt Controller CPU Interrupt Acknowledge Register + * (ICCIAR) for an SGI returns both the interrupt ID and the CPU ID of the + * processor that generated the interrupt, uniquely identifying the interrupt. + * In a multiprocessor implementation, the interrupt priority of each SGI + * interrupt ID is defined independently for each CPU interface. This means + * that, for each CPU interface, all SGIs with a particular interrupt ID that + * are pending on that interface have the same priority and must be handled + * serially. + * + * @{ + */ + +/*! + * Triggers the generation of a Software Generated Interrupts (SGI). + * + * \param int_id + * The interrupt identifier to send. Only SGI are valid, + * 0 - 15. + * + * \param target_filter + * The filtering parameter. + * + * \param target_list + * The set of CPUs which will receive the interrupt. + * + * \param secure_only + * If \b true, then send the SGI to the target processor(s) only if + * the SGI is configured as Secure on that interface. If \b false, + * then send the SGI to the target processor(s) only if the SGI is + * configured as Non-Secure on that interface. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given interrupt identifier, target filter, + * and / or target list is invalid. + */ +ALT_STATUS_CODE alt_int_sgi_trigger(ALT_INT_INTERRUPT_t int_id, + ALT_INT_SGI_TARGET_t target_filter, + alt_int_cpu_target_t target_list, + bool secure_only); + +/*! + * @} + */ + +/*! + * \addtogroup INT_LL_CPU Interrupt Controller CPU Interface [Secure] + * + * This group of APIs provide access, configuration, and control of the + * individual CPU interfaces. + * + * @{ + */ + +/*! + * Performs the initialization steps needed by the interrupt controller CPU + * interface. This should be the first CPU API call made when using the CPU + * interface. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_cpu_init(void); + +/*! + * Performs the uninitialization steps needed by the interrupt controller CPU + * interface. + */ +ALT_STATUS_CODE alt_int_cpu_uninit(void); + +/*! + * Enables all secure interrupt forwarding from the interrupt controller to + * the target CPU. + * + * The CPU interrupt monitors all secure interrupt signals and forwards + * pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_cpu_enable(void); + +/*! + * Disables all secure interrupt forwarding from the interrupt controller to + * the target CPU. + * + * The CPU interface ignores all secure interrupt signals and does not forward + * pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_cpu_disable(void); + +/*! + * Enables all non-secure interrupt forwarding from the interrupt controller + * to the target CPU using the secure interface. + * + * The CPU interrupt monitors all non-secure interrupt signals and forwards + * pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_cpu_enable_ns(void); + +/*! + * Disables all non-secure interrupt forwarding from the interrupt controller + * to the target CPU using the secure interface. + * + * The CPU interface ignores all non-secure interrupt signals and does not + * forward pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_cpu_disable_ns(void); + +/*! + * Enables all secure and non-secure interrupt forwarding from the interrupt + * controller to the target CPU. + * + * The CPU interrupt monitors all secure and non-secure interrupt signals and + * forwards pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_cpu_enable_all(void); + +/*! + * Disables all secure and non-secure interrupt forwarding from the interrupt + * controller to the target CPU. + * + * The CPU interface ignores all secure and non-secure interrupt signals and + * does not forward pending interrupts to the processors. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_cpu_disable_all(void); + + +/*! + * Gets the configuration of the signaling interface between the GIC and the + * CPU. + * + * Secure Binary Point for Preemption + * ---------------------------------- + * The binary point is point at which the priority value fields split into two + * parts, the group priority field and the subpriority field. The group + * priority field is used to determine interrupt preemption. + * + * On systems where secure and non-secure interrupts coexist, preemption can + * be determined by using secure binary point for secure interrupts and + * non-secure binary point for non-secure interrupts, or by using the secure + * binary point for both secure and non-secure interrupts. + * + * FIQ for Secure Interrupts + * ------------------------- + * FIQ or Fast Interrupt reQuest is a special interrupt signal specific to ARM + * CPUs. The CPU supports two interrupt signals for interrupts, the IRQ and + * FIQ. The FIQ is a separate interrupt signal which has lower latency and + * different preemption characteristics than regular interrupts. + * + * Secure acknowledgement for all interrupts + * ----------------------------------------- + * When in the secure mode, modifying the non-secure states can be seen as + * undesireable. One area which this may be problematic is the secure read of + * the Interrupt Controller CPU Interrupt Acknowledgement Register (ICCIAR) + * when the next pending interrupt is a non-secure. To prevent this scenario, + * the CPU can be configured to return a special interrupt ID (1022) and leave + * the non-secure interrupt in the pending state. + * + * \param use_secure_binary_point + * [out] Pointer to an output parameter that contains whether the + * Secure Binary Point Register is used for both secure and + * non-secure interrupts. If \b true then use the Secure Binary + * Point Register for both Secure and Non-secure interrupts. If \b + * false then use Secure Binary Point Register for secure + * interrupts and non-secure Binary Point Register for non-secure + * interrupts. + * + * \param use_FIQ_for_secure_interrupts + * [out] Pointer to an output parameter that contains whether + * Secure interrupts use the FIQ signal or not. If \b true then + * signal Secure interrupts using the FIQ signal. If \b false then + * signal Secure interrupts using the IRQ signal. + * + * \param allow_secure_ack_all_interrupts + * [out] Pointer to an output parameter that contains whether + * Secure acknowledgement of a Non-Secure interrupt is completed or + * not. If \b true then a Secure acknowledgement of the interrupt + * is not completed and the Interrupt ID of the Non-secure + * interrupt is returned. If \b false then a Secure acknowledgement + * of the interrupt is not completed and the Interrupt ID of 1022 + * is returned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_cpu_config_get(bool* use_secure_binary_point, + bool* use_FIQ_for_secure_interrupts, + bool* allow_secure_ack_all_interrupts); + +/*! + * Sets the configuration of the signaling interface between the GIC and the + * CPU. + * + * Secure Binary Point for Preemption + * ---------------------------------- + * The binary point is point at which the priority value fields split into two + * parts, the group priority field and the subpriority field. The group + * priority field is used to determine interrupt preemption. + * + * On systems where secure and non-secure interrupts coexist, preemption can + * be determined by using secure binary point for secure interrupts and + * non-secure binary point for non-secure interrupts, or by using the secure + * binary point for both secure and non-secure interrupts. + * + * FIQ for Secure Interrupts + * ------------------------- + * FIQ or Fast Interrupt reQuest is a special interrupt signal specific to ARM + * CPUs. The CPU supports two interrupt signals for interrupts, the IRQ and + * FIQ. The FIQ is a separate interrupt signal which has lower latency and + * different preemption characteristics than regular interrupts. + * + * Secure acknowledgement for all interrupts + * ----------------------------------------- + * When in the secure mode, modifying the non-secure states can be seen as + * undesireable. One area which this may be problematic is the secure read of + * the Interrupt Controller CPU Interrupt Acknowledgement Register (ICCIAR) + * when the next pending interrupt is a non-secure. To prevent this scenario, + * the CPU can be configured to return a special interrupt ID (1022) and leave + * the non-secure interrupt in the pending state. + * + * \param use_secure_binary_point + * If \b true then use the Secure Binary Point Register for both + * secure and non-secure interrupts. If \b false then use Secure + * Binary Point Register for secure interrupts and non-secure + * Binary Point Register for non-secure interrupts. + * + * \param use_FIQ_for_secure_interrupts + * If \b true then signal secure interrupts using the FIQ + * signal. If \b false then signal secure interrupts using the IRQ + * signal. + * + * \param allow_secure_ack_all_interrupts + * Controls whether a secure acknowledgement of an interrupt, when + * the highest priority pending interrupt is non-secure, causes the + * CPU interface to acknowledge the interrupt. If \b true then a + * secure acknowledgement of the interrupt is not completed and the + * Interrupt ID of the Non-secure interrupt is returned. If \b + * false then a secure acknowledgement of the interrupt is not + * completed and the Interrupt ID of 1022 is returned. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_cpu_config_set(bool use_secure_binary_point, + bool use_FIQ_for_secure_interrupts, + bool allow_secure_ack_all_interrupts); + + +/*! + * Gets the secure interrupt priority mask for the current CPU. Only + * interrupts with a higher priority than the priority mask can be forwarded + * to the CPU. + * + * \returns The interrupt priority mask used to determine interrupt + * preemption. + */ +uint32_t alt_int_cpu_priority_mask_get(void); + +/*! + * Sets the secure interrupt priority mask for the current CPU. Only + * interrupts with a higher priority than the priority mask can be forwarded + * to the CPU. + * + * \param priority_mask + * The interrupt priority mask is the group priority needed to + * instruct the GIC to preempt lower priority interrupt. The + * valid range for this value is 0 - 255. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given priority mask is invalid. + */ +ALT_STATUS_CODE alt_int_cpu_priority_mask_set(uint32_t priority_mask); + +/*! + * Gets the binary point value for the current CPU. + * + * The binary point is point at which the priority value fields split into two + * parts, the group priority field and the subpriority field. The group + * priority field is used to determine interrupt preemption. + * + * \returns The configured binary point value. + */ +uint32_t alt_int_cpu_binary_point_get(void); + +/*! + * Sets the binary point value for the current CPU. + * + * The binary point is point at which the priority value fields split into two + * parts, the group priority field and the subpriority field. The group + * priority field is used to determine interrupt preemption. + * + * \param binary_point + * The binary point to use. The valid range for the value is + * 0 - 7. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given binary point value is invalid. + */ +ALT_STATUS_CODE alt_int_cpu_binary_point_set(uint32_t binary_point); + +/*! + * Gets the non-secure binary point value for the current CPU using the secure + * interface. + * + * The binary point is point at which the priority value fields split into two + * parts, the group priority field and the subpriority field. The group + * priority field is used to determine interrupt preemption. + * + * \returns The configured binary point value. + */ +uint32_t alt_int_cpu_binary_point_get_ns(void); + +/*! + * Sets the non-secure binary point value for the current CPU using the secure + * interface. + * + * The binary point is point at which the priority value fields split into two + * parts, the group priority field and the subpriority field. The group + * priority field is used to determine interrupt preemption. + * + * \param binary_point + * The binary point to use. The valid range for the value is + * 0 - 7. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The given binary point value is invalid. + */ +ALT_STATUS_CODE alt_int_cpu_binary_point_set_ns(uint32_t binary_point); + +/*! + * @} + */ + +/*! + * \addtogroup INT_LL_ISR Interrupt Service Routine [Secure] + * + * This group of APIs performs Interrupt Service Routine (ISR) related + * functions. + * + * @{ + */ + +/*! + * Registers a callback for the specified secure interrupt for the CPU + * interface. + * + * This API only registers a callback for secure interrupts. If a callback is + * registered for a non-secure interrupt, the behaviour is undefined. + * + * \param int_id + * The interrupt identifier to register the handler for. All + * defined interrupts are valid, 0 - 1019. + * + * \param callback + * The callback to use when the given interrupt is issued. + * + * \param context + * The callback context to use for the above callback. When the + * callback is issued, this parameter will be provided to the + * callback. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_isr_register(ALT_INT_INTERRUPT_t int_id, + alt_int_callback_t callback, + void * context); + +/*! + * Unregisters the callback for the specified secure interrupt for the CPU + * interface. + * + * This API only unregisters a callback for secure interrupts. If a callback + * is unregistered for a non-secure interrupt, the behaviour is undefined. + * + * \param int_id + * The interrupt identifier to register the handler for. All + * defined interrupts are valid, 0 - 1019. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_int_isr_unregister(ALT_INT_INTERRUPT_t int_id); + +/*! + * @} + */ + +/*! + * \addtogroup INT_LL_UTIL Interrupt Utility Functions [Secure] + * + * This group of APIs provide utilities to query the system properties. + * + * @{ + */ + +/*! + * Gets the number of CPUs in the system. + * + * \returns The CPU count of the system. + */ +uint32_t alt_int_util_cpu_count(void); + +/*! + * Gets the number of supported interrupts in the system. + * + * \returns The supported interrupt count of the system. + */ +uint32_t alt_int_util_int_count(void); + +/*! + * Gets the CPU indentifier of the current CPU interface. + * + * \returns The set of CPUs representing the current CPU interface. + */ +alt_int_cpu_target_t alt_int_util_cpu_current(void); + +/*! + * @} + */ + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_INT_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_interrupt_common.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_interrupt_common.h new file mode 100644 index 000000000..b4a1a7670 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_interrupt_common.h @@ -0,0 +1,533 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_INT_COMMON_H__ +#define __ALT_INT_COMMON_H__ + +#include "hwlib.h" +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! + * \addtogroup INT_COMMON Interrupt Controller Common Definitions + * + * This module contains the definitions common to the Interrupt Controller + * Low-Level API and Interrupt Controller Manager Interface. + * + * @{ + */ + +/*! + * This type definition enumerates all the interrupt identification types. + */ +typedef enum ALT_INT_INTERRUPT_e +{ + ALT_INT_INTERRUPT_SGI0 = 0, /*!< # */ + ALT_INT_INTERRUPT_SGI1 = 1, /*!< # */ + ALT_INT_INTERRUPT_SGI2 = 2, /*!< # */ + ALT_INT_INTERRUPT_SGI3 = 3, /*!< # */ + ALT_INT_INTERRUPT_SGI4 = 4, /*!< # */ + ALT_INT_INTERRUPT_SGI5 = 5, /*!< # */ + ALT_INT_INTERRUPT_SGI6 = 6, /*!< # */ + ALT_INT_INTERRUPT_SGI7 = 7, /*!< # */ + ALT_INT_INTERRUPT_SGI8 = 8, /*!< # */ + ALT_INT_INTERRUPT_SGI9 = 9, /*!< # */ + ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */ + ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */ + ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */ + ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */ + ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */ + ALT_INT_INTERRUPT_SGI15 = 15, + /*!< + * Software Generated Interrupts (SGI), 0 - 15. + * * All interrupts in this group are software triggered. + */ + + ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL = 27, /*!< # */ + ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE = 29, /*!< # */ + ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */ + /*!< + * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU + * private timer, and watchdog timer. + * * All interrupts in this group are edge triggered. + */ + + ALT_INT_INTERRUPT_CPU0_PARITYFAIL = 32, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC = 33, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB = 34, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG = 35, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA = 36, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB = 37, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG = 39, /*!< # */ + ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA = 40, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS0 = 41, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS1 = 42, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS2 = 43, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS3 = 44, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS4 = 45, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS5 = 46, /*!< # */ + ALT_INT_INTERRUPT_CPU0_DEFLAGS6 = 47, + /*!< + * Interrupts sourced from CPU0. + * + * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the + * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts + * for CPU0. + * + * * PARITYFAIL interrupts in this group are edge triggered. + * * DEFFLAGS interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CPU1_PARITYFAIL = 48, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC = 49, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB = 50, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG = 51, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA = 52, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB = 53, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG = 55, /*!< # */ + ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA = 56, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS0 = 57, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS1 = 58, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS2 = 59, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS3 = 60, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS4 = 61, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS5 = 62, /*!< # */ + ALT_INT_INTERRUPT_CPU1_DEFLAGS6 = 63, + /*!< + * Interrupts sourced from CPU1. + * + * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the + * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts + * for CPU1. + * + * * PARITYFAIL interrupts in this group are edge triggered. + * * DEFFLAGS interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_SCU_PARITYFAIL0 = 64, /*!< # */ + ALT_INT_INTERRUPT_SCU_PARITYFAIL1 = 65, /*!< # */ + ALT_INT_INTERRUPT_SCU_EV_ABORT = 66, + /*!< + * Interrupts sourced from the Snoop Control Unit (SCU). + * * All interrupts in this group are edge triggered. + */ + + ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ = 67, /*!< # */ + ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ = 68, /*!< # */ + ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */ + ALT_INT_INTERRUPT_L2_COMBINED_IRQ = 70, + /*!< + * Interrupts sourced from the L2 Cache Controller. + * + * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache + * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR, + * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts. + * Consult the L2C documentation for information on these interrupts. + * + * * ECC interrupts in this group are edge triggered. + * * Other interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ = 71, + /*!< + * Interrupts sourced from the SDRAM Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_F2S_FPGA_IRQ0 = 72, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ1 = 73, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ2 = 74, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ3 = 75, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ4 = 76, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ5 = 77, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ6 = 78, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ7 = 79, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ8 = 80, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ9 = 81, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 = 82, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 = 83, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 = 84, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 = 85, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 = 86, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 = 87, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 = 88, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 = 89, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 = 90, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 = 91, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 = 92, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 = 93, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 = 94, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 = 95, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 = 96, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 = 97, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 = 98, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 = 99, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */ + ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135, + /*!< + * Interrupt request from the FPGA logic, 0 - 63. + * * Trigger type depends on the implementation in the FPGA. + */ + + ALT_INT_INTERRUPT_DMA_IRQ0 = 136, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ1 = 137, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ2 = 138, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ3 = 139, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ4 = 140, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ5 = 141, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ6 = 142, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ7 = 143, /*!< # */ + ALT_INT_INTERRUPT_DMA_IRQ_ABORT = 144, /*!< # */ + ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ = 145, /*!< # */ + ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146, + /*!< + * Interrupts sourced from the DMA Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_EMAC0_IRQ = 147, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ = 148, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ = 150, /*!< # */ + ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151, + /*!< + * Interrupts sourced from the Ethernet MAC 0 (EMAC0). + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_EMAC1_IRQ = 152, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ = 153, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ = 155, /*!< # */ + ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156, + /*!< + * Interrupts sourced from the Ethernet MAC 1 (EMAC1). + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_USB0_IRQ = 157, /*!< # */ + ALT_INT_INTERRUPT_USB0_ECC_CORRECTED = 158, /*!< # */ + ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159, + /*!< + * Interrupts sourced from the USB OTG 0. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_USB1_IRQ = 160, /*!< # */ + ALT_INT_INTERRUPT_USB1_ECC_CORRECTED = 161, /*!< # */ + ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162, + /*!< + * Interrupts sourced from the USB OTG 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CAN0_STS_IRQ = 163, /*!< # */ + ALT_INT_INTERRUPT_CAN0_MO_IRQ = 164, /*!< # */ + ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ = 165, /*!< # */ + ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166, + /*!< + * Interrupts sourced from the CAN Controller 0. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CAN1_STS_IRQ = 167, /*!< # */ + ALT_INT_INTERRUPT_CAN1_MO_IRQ = 168, /*!< # */ + ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ = 169, /*!< # */ + ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170, + /*!< + * Interrupts sourced from the CAN Controller 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_SDMMC_IRQ = 171, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED = 172, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED = 174, /*!< # */ + ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175, + /*!< + * Interrupts sourced from the SDMMC Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_NAND_IRQ = 176, /*!< # */ + ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ = 177, /*!< # */ + ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */ + ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ = 179, /*!< # */ + ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */ + ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ = 181, /*!< # */ + ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182, + /*!< + * Interrupts sourced from the NAND Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_QSPI_IRQ = 183, /*!< # */ + ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ = 184, /*!< # */ + ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185, + /*!< + * Interrupts sourced from the QSPI Controller. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */ + ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */ + ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */ + ALT_INT_INTERRUPT_SPI3_IRQ = 189, + /*!< + * Interrupts sourced from the SPI Controllers 0 - 3. + * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1. + * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */ + ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */ + ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */ + ALT_INT_INTERRUPT_I2C3_IRQ = 193, + /*!< + * Interrupts sourced from the I2C Controllers 0 - 3. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_UART0 = 194, /*!< # */ + ALT_INT_INTERRUPT_UART1 = 195, + /*!< + * Interrupts sourced from the UARTs 0 - 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */ + ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */ + ALT_INT_INTERRUPT_GPIO2 = 198, + /*!< + * Interrupts sourced from the GPIO 0 - 2. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */ + ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */ + ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */ + ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202, + /*!< + * Interrupts sourced from the Timer controllers. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */ + ALT_INT_INTERRUPT_WDOG1_IRQ = 204, + /*!< + * Interrupts sourced from the Watchdog Timers 0 - 1. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_CLKMGR_IRQ = 205, + /*!< + * Interrupts sourced from the Clock Manager. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206, + /*!< + * Interrupts sourced from the Clock Manager MPU Wakeup. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207, + /*!< + * Interrupts sourced from the FPGA Manager. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */ + ALT_INT_INTERRUPT_NCTIIRQ1 = 209, + /*!< + * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI. + * * All interrupts in this group are level triggered. + */ + + ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ = 210, /*!< # */ + ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211 + /*!< + * Interrupts sourced from the On-chip RAM. + * * All interrupts in this group are level triggered. + */ + +} ALT_INT_INTERRUPT_t; + +/*! + * This is the CPU target type. It is used to specify a set of CPUs on the + * system. If only bit 0 is set then it specifies a set of CPUs containing + * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit + * up to the number of CPUs on the system. + */ +typedef uint32_t alt_int_cpu_target_t; + +/*! + * This type definition enumerates all the interrupt trigger types. + */ +typedef enum ALT_INT_TRIGGER_e +{ + /*! + * Edge triggered interrupt. This applies to Private Peripheral Interrupts + * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs + * 16 - 1019. + */ + ALT_INT_TRIGGER_EDGE, + + /*! + * Level triggered interrupt. This applies to Private Peripheral + * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with + * interrupt IDs 16 - 1019. + */ + ALT_INT_TRIGGER_LEVEL, + + /*! + * Software triggered interrupt. This applies to Software Generated + * Interrupts (SGI) only, with interrupt IDs 0 - 15. + */ + ALT_INT_TRIGGER_SOFTWARE, + + /*! + * All triggering types except for those in the Shared Peripheral Interrupts + * (SPI) F2S FPGA family interrupts can be determined by the system + * automatically. In all functions which ask for the triggering type, the + * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger + * type for all non F2S interrupt types. + */ + ALT_INT_TRIGGER_AUTODETECT, + + /*! + * The interrupt triggering information is not applicable. This is possibly + * due to querying an invalid interrupt identifier. + */ + ALT_INT_TRIGGER_NA +} +ALT_INT_TRIGGER_t; + +/*! + * This type definition enumerates all the target list filter options. This is + * used by the trigger Software Generated Interrupt (SGI) feature to issue a + * SGI to the specified processor(s) in the system. Depending on the target + * list filter and the target list, interrupts can be routed to any + * combinations of CPUs. + */ +typedef enum ALT_INT_SGI_TARGET_e +{ + /*! + * This filter list uses the target list parameter to specify which CPUs + * to send the interrupt to. If target list is 0, no interrupts are sent. + */ + ALT_INT_SGI_TARGET_LIST, + + /*! + * This filter list sends the interrupt all CPUs except the current CPU. + * The target list parameter is ignored. + */ + ALT_INT_SGI_TARGET_ALL_EXCL_SENDER, + + /*! + * This filter list sends the interrupt to the current CPU only. The + * target list parameter is ignored. + */ + ALT_INT_SGI_TARGET_SENDER_ONLY +} +ALT_INT_SGI_TARGET_t; + +/*! + * Extracts the CPUID field from the ICCIAR register. + */ +#define ALT_INT_ICCIAR_CPUID_GET(icciar) ((icciar >> 10) & 0x7) + +/*! + * Extracts the ACKINTID field from the ICCIAR register. + */ +#define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF) + +/*! + * The callback to use when an interrupt needs to be serviced. + * + * \param icciar The Interrupt Controller CPU Interrupt + * Acknowledgement Register value (ICCIAR) value + * corresponding to the current interrupt. + * + * \param context The user provided context. + */ +typedef void (*alt_int_callback_t)(uint32_t icciar, void * context); + +/*! + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_INT_COMMON_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_mmu.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_mmu.h new file mode 100644 index 000000000..d7ccf4a7a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_mmu.h @@ -0,0 +1,1644 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/*! \file + * Altera - MMU Management API + */ + +#ifndef __ALT_MMU_H__ +#define __ALT_MMU_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_MMU MMU Management API + * + * This module defines an API for configuring and managing the Cortex-A9 MMU. + * + * The APIs in this module are divided into two categories: + * * Support for low-level MMU configuration and operation. + * * Support for simplified virtual address space definition and enablement. + * + * The functions in the low-level MMU API provide capabilities to: + * * Control and maintain the MMU operational state. + * * Create and maintain MMU translation tables using a low-level API. + * + * The low-level API does not directly support any particular virtual address + * implementation model. Many features of the MMU hardware are oriented toward + * efficient implementation of protected virtual addressing in a multi-tasking + * operating system environment. + * + * While the functions in the low-level MMU API could be used to facilitate a port + * to an operating system exploiting these MMU features, the API itself does not + * directly implement any particular virtual address implementation model or + * policy. + * + * The other API does directly support a simplified virtual address space + * implementation model. This API provides a client facility to programmatically + * define a simplified virtual address space from a set of high level memory + * region configurations. The API also provides a convenient method to enable the + * virtual address space once it is defined. + * + * For a complete understanding of the possible configurations and operation of + * the MMU, consult the following references: + * * ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition (ARM DDI + * 0406C), Chapter B3 Virtual Memory System Architecture (VMSA) + * * ARM Cortex-A9 Technical Reference Manual(ARM DDI 0388G), Chapter 6 Memory + * Management Unit + * + * @{ + */ + +/*! + * This type enumerates the options for Shareability (S) properties in translation + * table descriptors. This control determines whether the addressed region is + * Shareable memory or not. + * + * The Shareability property (S bit): + * * Is ignored if the entry refers to Device or Strongly-ordered memory. + * * For Normal memory, determines whether the memory region is Shareable or Non-shareable: + * - S == 0 Normal memory region is Non-shareable. + * - S == 1 Normal memory region is Shareable. + */ +typedef enum ALT_MMU_TTB_S_e +{ + ALT_MMU_TTB_S_NON_SHAREABLE = 0, /*!< Non-Shareable address map */ + ALT_MMU_TTB_S_SHAREABLE = 1 /*!< Shareable address map */ +} ALT_MMU_TTB_S_t; + + +/*! + * This type enumerates the options for Non-Secure (NS) controls in translation + * table descriptors. This control specifies whether memory accesses made from the + * secure state translate physical address in the secure or non-secure address + * map. The value of the NS bit in the first level page table descriptor applies + * to all entries in the corresponding second-level translation table. + */ +typedef enum ALT_MMU_TTB_NS_e +{ + ALT_MMU_TTB_NS_SECURE = 0, /*!< Secure address map */ + ALT_MMU_TTB_NS_NON_SECURE = 1 /*!< Non-Secure address map */ +} ALT_MMU_TTB_NS_t; + +/*! + * This type enumerates the options for Execute Never (XN) controls in translation + * table descriptors that determine whether the processor can execute instructions + * from the addressed region. + */ +typedef enum ALT_MMU_TTB_XN_e +{ + ALT_MMU_TTB_XN_DISABLE = 0, /*!< Instructions can be executed from + * this memory region. + */ + ALT_MMU_TTB_XN_ENABLE = 1 /*!< Instructions cannot be executed from + * this memory region. A permission + * fault is generated if an attempt to + * execute an instruction from this + * memory region. However, if using the + * short-descriptor translation table + * format, the fault is generated only + * if the access is to memory in the + * client domain. + */ +} ALT_MMU_TTB_XN_t; + +/*! + * This type enumerates the Domain Access Permission (DAP) options that can be set + * in the Domain Access Control Register (DACR). + */ +typedef enum ALT_MMU_DAP_e +{ + ALT_MMU_DAP_NO_ACCESS = 0x0, /*!< No access. Any access to the domain + * generates a Domain fault. + */ + ALT_MMU_DAP_CLIENT = 0x1, /*!< Client. Accesses are checked against + * the permission bits in the + * translation tables. + */ + ALT_MMU_DAP_RESERVED = 0x2, /*!< Reserved, effect is UNPREDICTABLE. */ + ALT_MMU_DAP_MANAGER = 0x3 /*!< Manager. Accesses are not checked + * against the permission bits in the + * translation tables. + */ +} ALT_MMU_DAP_t; + +/*! + * This type enumerates the Access Permissions that can be specified for a memory + * region. + * + * Memory access control is defined using access permission bits in translation + * table descriptors that control access to the corresponding memory region. + * + * The HWLIB uses the short-descriptor translation table format for defining the + * access permissions where three bits, AP[2:0], define the access + * permissions. The SCTLR.AFE must be set to 0. + * + * The following table provides a summary of the enumerations, AP bit encodings, + * and access permission descriptions for this type. + * + * Enumeration | AP Value | Privileged (PL1) Access | User (PL0) Access | Description + * :--------------------------|:---------|:------------------------|:------------------|:------------------------------------- + * ALT_MMU_AP_NO_ACCESS | 000 | No Access | No Access | No Access + * ALT_MMU_AP_PRIV_ACCESS | 001 | Read/Write | No Access | Privileged access only + * ALT_MMU_AP_USER_READ_ONLY | 010 | Read/Write | Read Only | Write in user mode generates a fault + * ALT_MMU_AP_FULL_ACCESS | 011 | Read/Write | Read/Write | Full Access + * N/A | 100 | Unknown | Unknown | Reserved + * ALT_MMU_AP_PRIV_READ_ONLY | 101 | Read Only | No Access | Privileged read only + * N/A | 110 | Read Only | Read Only | Read Only - deprecated + * ALT_MMU_AP_READ_ONLY | 111 | Read Only | Read Only | Read Only + */ +enum ALT_MMU_AP_e +{ + ALT_MMU_AP_NO_ACCESS = 0, /*!< No Access */ + ALT_MMU_AP_PRIV_ACCESS = 1, /*!< Privileged access only */ + ALT_MMU_AP_USER_READ_ONLY = 2, /*!< Write in user mode generates a fault */ + ALT_MMU_AP_FULL_ACCESS = 3, /*!< Full Access */ + ALT_MMU_AP_PRIV_READ_ONLY = 5, /*!< Privileged read only */ + ALT_MMU_AP_READ_ONLY = 7 /*!< Read Only */ +}; +/*! Typedef name for enum ALT_MMU_AP_e */ +typedef enum ALT_MMU_AP_e ALT_MMU_AP_t; + +/*! + * This type enumerates the Memory Region attributes that can be specifed in MMU + * translation table entries. Memory attributes determine the memory ordering and + * cache policies for inner/outer domains used for a particular range of memory. + * + * Within the translation table entries, the memory region attributes are encoded + * using a combination of the descriptor entry data fields (TEX, C, B). Memory + * attribute settings also affect the meaning of other memory region properties + * such as shareability (S). + * + * The tables below describe the available enumerations for specifying different + * memory region attributes and their affect on shareability. + * + * The memory attributes enumerated here are meant to be used is a system where + * TEX remap is disabled (i.e. SCTLR.TRE is set to 0). + * + * Enumeration | TEX | C | B | Description | Shareability + * :-----------------------|:----|:--|:--|:--------------------------------------------------|:-------------------------------- + * ALT_MMU_ATTR_STRONG | 000 | 0 | 0 | Strongly Ordered | Shareable + * ALT_MMU_ATTR_DEVICE | 000 | 0 | 1 | Device | Shareable + * ALT_MMU_ATTR_WT | 000 | 1 | 0 | Inner/Outer Write-Through, No Write Allocate | Determined by desciptor [S] bit + * ALT_MMU_ATTR_WB | 000 | 1 | 1 | Inner/Outer Write-Back, No Write Allocate | Determined by desciptor [S] bit + * ALT_MMU_ATTR_NC | 001 | 0 | 0 | Inner/Outer Non-Cacheable | Determined by desciptor [S] bit + * N/A | 001 | 0 | 1 | Reserved | Reserved + * N/A | 001 | 1 | 0 | Implementation Defined | - + * ALT_MMU_ATTR_WBA | 001 | 1 | 1 | Inner/Outer Write-Back, Write Allocate | Determined by desciptor [S] bit + * ALT_MMU_ATTR_DEVICE_NS | 010 | 0 | 0 | Device | Non-Shareable + * N/A | 010 | 0 | 1 | Reserved | Reserved + * N/A | 010 | 1 | 0 | Reserved | Reserved + * N/A | 010 | 1 | 1 | Reserved | Reserved + * ALT_MMU_ATTR_AA_BB | 1BB | A | A | Cached where AA = Inner Policy, BB = Outer Policy | Determined by desciptor [S] bit + * + * Cache Policy Encoding for AA, BB + * + * Mnemonic Encoding | Bit Encoding | Cache Policy + * :------------------|:-------------|:--------------------------------- + * NC | 00 | Non-Cacheable + * WBA | 01 | Write-Back, Write Allocate + * WT | 10 | Write-Through, No Write Allocate + * WB | 11 | Write-Back, No Write Allocate + * + * \internal + * The encoding of the enum values is that the MSB 4 bits is TEX while the + * LSB is C | B. Fault is 0xff. This makes it easier to decode TEX, C, B from + * the actual enum value. + * \endinternal + */ +enum ALT_MMU_ATTR_e +{ + ALT_MMU_ATTR_FAULT = 0xff, /*!< Generates fault descriptor entries for memory region */ + ALT_MMU_ATTR_STRONG = 0x00, /*!< Strongly Ordered Shareable */ + ALT_MMU_ATTR_DEVICE = 0x01, /*!< Device Shareable */ + ALT_MMU_ATTR_WT = 0x02, /*!< Inner/Outer Write-Through, No Write Allocate, Shareability determined by [S] */ + ALT_MMU_ATTR_WB = 0x03, /*!< Inner/Outer Write-Back, No Write Allocate, Shareability determined by [S] bit */ + ALT_MMU_ATTR_NC = 0x10, /*!< Inner/Outer Non-Cacheable, Shareability determined by [S] bit */ + ALT_MMU_ATTR_WBA = 0x13, /*!< Inner/Outer Write-Back, Write Allocate, Shareability determined by [S] bit */ + ALT_MMU_ATTR_DEVICE_NS = 0x20, /*!< Device Non-Shareable */ + + ALT_MMU_ATTR_NC_NC = 0x40, /*!< Inner Non-Cacheable, Outer Non-Cacheable, Shareability determined by [S] bit */ + ALT_MMU_ATTR_NC_WBA = 0x50, /*!< Inner Non-Cacheable, Outer Write-Back Write Allocate, Shareability determined by [S] bit */ + ALT_MMU_ATTR_NC_WT = 0x60, /*!< Inner Non-Cacheable, Outer Write-Through, Shareability determined by [S] bit */ + ALT_MMU_ATTR_NC_WB = 0x70, /*!< Inner Non-Cacheable, Outer Write-Back, Shareability determined by [S] bit */ + + ALT_MMU_ATTR_WBA_NC = 0x41, /*!< Inner Write-Back Write Allocate, Outer Non-Cacheable, Shareability determined by [S] bit */ + ALT_MMU_ATTR_WBA_WBA = 0x51, /*!< Inner Write-Back Write Allocate, Outer Write-Back Write Allocate, Shareability determined by [S] bit */ + ALT_MMU_ATTR_WBA_WT = 0x61, /*!< Inner Write-Back Write Allocate, Outer Write-Through, Shareability determined by [S] bit */ + ALT_MMU_ATTR_WBA_WB = 0x71, /*!< Inner Write-Back Write Allocate, Outer Write-Back, Shareability determined by [S] bit */ + + ALT_MMU_ATTR_WT_NC = 0x42, /*!< Inner Write-Through, Outer Non-Cacheable, Shareability determined by [S] bit */ + ALT_MMU_ATTR_WT_WBA = 0x52, /*!< Inner Write-Through, Outer Write-Back Write Allocate, Shareability determined by [S] bit */ + ALT_MMU_ATTR_WT_WT = 0x62, /*!< Inner Write-Through, Outer Write-Through, Shareability determined by [S] bit */ + ALT_MMU_ATTR_WT_WB = 0x72, /*!< Inner Write-Through, Outer Write-Back, Shareability determined by [S] bit */ + + ALT_MMU_ATTR_WB_NC = 0x43, /*!< Inner Write-Back, Outer Non-Cacheable, Shareability determined by [S] bit */ + ALT_MMU_ATTR_WB_WBA = 0x53, /*!< Inner Write-Back, Outer Write-Back Write Allocate, Shareability determined by [S] bit */ + ALT_MMU_ATTR_WB_WT = 0x63, /*!< Inner Write-Back, Outer Write-Through, Shareability determined by [S] bit */ + ALT_MMU_ATTR_WB_WB = 0x73, /*!< Inner Write-Back, Outer Write-Back, Shareability determined by [S] bit */ + +}; +/*! Typedef name for enum ALT_MMU_ATTR_e */ +typedef enum ALT_MMU_ATTR_e ALT_MMU_ATTR_t; + + +/******************************************************************************/ +/*! \addtogroup ALT_MMU_MGMT MMU Management + * + * This section defines low-level declarations, macros, and functions for creating + * and maintaining MMU first and second level translation tables and their short + * descriptor entries. + * + * The basic functions to enable/disable and configure the opertational state of + * the MMU are in this section. + * + * The operations in this section are for users that want to exercise a fine + * degree of configuration and control over the MMU. It requires a more detailed + * understanding of the MMU, its different modes of operation, and puts more + * responsibility on the user for correct functioning. + * + * Users desiring basic configuration and enablement of the MMU to support a + * virtual address space should use the operations in the section \ref ALT_MMU_VA + * "MMU Virtual Address Space Creation". + * + * @{ + */ + +/*! + * The size of a supersection in bytes is 16 MiB. + */ +#define ALT_MMU_SUPERSECTION_SIZE (1UL << 24) + +/*! + * The size of a section in bytes is 1 MiB. + */ +#define ALT_MMU_SECTION_SIZE (1UL << 20) + +/*! + * The size of a large page in bytes is 64 KiB. + */ +#define ALT_MMU_LARGE_PAGE_SIZE (1UL << 16) + +/*! + * The size of a small page in bytes is 4 KiB. + */ +#define ALT_MMU_SMALL_PAGE_SIZE (1UL << 12) + +/*! + * The size of a first level translation table for the short descriptor format in + * bytes. + */ +#define ALT_MMU_TTB1_SIZE 16384 + +/*! + * The size of a second level translation table for the short descriptor format in + * bytes. + */ +#define ALT_MMU_TTB2_SIZE 1024 + +/******************************************************************************/ +/*! \addtogroup ALT_MMU_MGMT_MACRO_TTB1 MMU Management Macros - First Level Translation Table + * + * The macro definitions in this section support access to the short-descriptor + * first-level table entries and their constituent fields. + * + * These macros may be used to create descriptor entry values that are passed to a + * first level translation table contruction function such as + * alt_mmu_ttb1_desc_set(). + * + * Each short-descriptor has a set of macro definitions of the following form: + * + * * \b ALT_MMU_TTB1__MASK - bit mask for the descriptor type + * and field. + * + * * \b ALT_MMU_TTB1__GET(desc) - extracts the field value + * from the descriptor entry \e + * desc. + * + * * \b ALT_MMU_TTB1__SET(val) - returns a field \e val + * shifted and masked that is + * suitable for setting a + * descriptor entry. + * + * @{ + */ + +/*! + * + */ +#define ALT_MMU_TTB1_TYPE_MASK 0x00000003 +#define ALT_MMU_TTB1_TYPE_GET(desc) (((desc) & ALT_MMU_TTB1_TYPE_MASK) >> 0) +#define ALT_MMU_TTB1_TYPE_SET(val) (((val) << 0) & ALT_MMU_TTB1_TYPE_MASK) + +/*! + * \name First Level Translation Table Page Table Entry [NS] + * + * The Non-Secure [NS] bit. This bit specifies whether the translated PA is in + * the Secure or Non-Secure address map. + * @{ + */ +#define ALT_MMU_TTB1_PAGE_TBL_NS_MASK 0x00000008 +#define ALT_MMU_TTB1_PAGE_TBL_NS_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_NS_MASK) >> 3) +#define ALT_MMU_TTB1_PAGE_TBL_NS_SET(val) (((val) << 3) & ALT_MMU_TTB1_PAGE_TBL_NS_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Page Table Entry [DOMAIN] + * + * Domain field. Page table descriptor applies to all entries in the corresponding + * second-level translation table. + * @{ + */ +#define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK 0x000001e0 +#define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK) >> 5) +#define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Page Table Entry Page Table Base Address + * @{ + */ +#define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK 0xfffffc00 +#define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK) >> 10) +#define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_SET(val) (((val) << 10) & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Section Entry [B] + * + * The [B] field of the memory region attributes. [B] is an arcane reference to + * Bufferable attribute. + * @{ + */ +#define ALT_MMU_TTB1_SECTION_B_MASK 0x00000004 +#define ALT_MMU_TTB1_SECTION_B_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_B_MASK) >> 2) +#define ALT_MMU_TTB1_SECTION_B_SET(val) (((val) << 2) & ALT_MMU_TTB1_SECTION_B_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Section Entry [C] + * + * The [C] field of the memory region attributes. [C] is an arcane reference to + * Cacheable attribute. + * @{ + */ +#define ALT_MMU_TTB1_SECTION_C_MASK 0x00000008 +#define ALT_MMU_TTB1_SECTION_C_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_C_MASK) >> 3) +#define ALT_MMU_TTB1_SECTION_C_SET(val) (((val) << 3) & ALT_MMU_TTB1_SECTION_C_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Section Entry [XN] + * + * The Execute-Never bit. Determines whether the processor can execute software + * from the addressed region. + * @{ + */ +#define ALT_MMU_TTB1_SECTION_XN_MASK 0x00000010 +#define ALT_MMU_TTB1_SECTION_XN_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_XN_MASK) >> 4) +#define ALT_MMU_TTB1_SECTION_XN_SET(val) (((val) << 4) & ALT_MMU_TTB1_SECTION_XN_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Section Entry [DOMAIN] + * + * Domain field. + * @{ + */ +#define ALT_MMU_TTB1_SECTION_DOMAIN_MASK 0x000001e0 +#define ALT_MMU_TTB1_SECTION_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_DOMAIN_MASK) >> 5) +#define ALT_MMU_TTB1_SECTION_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_SECTION_DOMAIN_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Section Entry [AP] + * + * Access Permissions bits. + * @{ + */ +#define ALT_MMU_TTB1_SECTION_AP_MASK 0x00008c00 +#define ALT_MMU_TTB1_SECTION_AP_GET(desc) ((((desc) & 0x00008000) >> 13) | (((desc) & 0x00000c00) >> 10)) +#define ALT_MMU_TTB1_SECTION_AP_SET(val) ((((val) << 13) & 0x00008000) | (((val) << 10) & 0x00000c00)) +/*! @} */ + +/*! + * \name First Level Translation Table Section Entry [TEX] + * + * The [TEX] field of the memory region attributes. [TEX] is an arcane reference to + * Type EXtension attribute. + * @{ + */ +#define ALT_MMU_TTB1_SECTION_TEX_MASK 0x00007000 +#define ALT_MMU_TTB1_SECTION_TEX_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_TEX_MASK) >> 12) +#define ALT_MMU_TTB1_SECTION_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB1_SECTION_TEX_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Section Entry [S] + * + * The Shareable bit. Determines whether the addressed region is shareable memory. + * @{ + */ +#define ALT_MMU_TTB1_SECTION_S_MASK 0x00010000 +#define ALT_MMU_TTB1_SECTION_S_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_S_MASK) >> 16) +#define ALT_MMU_TTB1_SECTION_S_SET(val) (((val) << 16) & ALT_MMU_TTB1_SECTION_S_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Section Entry [nG] + * + * The not global bit. Determines how the translation is marked in the TLB. + * @{ + */ +#define ALT_MMU_TTB1_SECTION_NG_MASK 0x00020000 +#define ALT_MMU_TTB1_SECTION_NG_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_NG_MASK) >> 17) +#define ALT_MMU_TTB1_SECTION_NG_SET(val) (((val) << 17) & ALT_MMU_TTB1_SECTION_NG_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Section Entry [NS] + * + * The Non-Secure [NS] bit. This bit specifies whether the translated PA is in + * the Secure or Non-Secure address map. + * @{ + */ +#define ALT_MMU_TTB1_SECTION_NS_MASK 0x00080000 +#define ALT_MMU_TTB1_SECTION_NS_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_NS_MASK) >> 19) +#define ALT_MMU_TTB1_SECTION_NS_SET(val) (((val) << 19) & ALT_MMU_TTB1_SECTION_NS_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Section Entry Section Base Address + * @{ + */ +#define ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK 0xfff00000 +#define ALT_MMU_TTB1_SECTION_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK) >> 20) +#define ALT_MMU_TTB1_SECTION_BASE_ADDR_SET(val) (((val) << 20) & ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Supersection Entry [B] + * + * The [B] field of the memory region attributes. [B] is an arcane reference to + * Bufferable attribute. + * @{ + */ +#define ALT_MMU_TTB1_SUPERSECTION_B_MASK 0x00000004 +#define ALT_MMU_TTB1_SUPERSECTION_B_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_B_MASK) >> 2) +#define ALT_MMU_TTB1_SUPERSECTION_B_SET(val) (((val) << 2) & ALT_MMU_TTB1_SUPERSECTION_B_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Supersection Entry [C] + * + * The [C] field of the memory region attributes. [C] is an arcane reference to + * Cacheable attribute. + * @{ + */ +#define ALT_MMU_TTB1_SUPERSECTION_C_MASK 0x00000008 +#define ALT_MMU_TTB1_SUPERSECTION_C_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_C_MASK) >> 3) +#define ALT_MMU_TTB1_SUPERSECTION_C_SET(val) (((val) << 3) & ALT_MMU_TTB1_SUPERSECTION_C_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Supersection Entry [XN] + * + * The Execute-Never bit. Determines whether the processor can execute software + * from the addressed region. + * @{ + */ +#define ALT_MMU_TTB1_SUPERSECTION_XN_MASK 0x00000010 +#define ALT_MMU_TTB1_SUPERSECTION_XN_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_XN_MASK) >> 4) +#define ALT_MMU_TTB1_SUPERSECTION_XN_SET(val) (((val) << 4) & ALT_MMU_TTB1_SUPERSECTION_XN_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Supersection Entry [DOMAIN] + * + * Domain field. + * @{ + */ +#define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK 0x000001e0 +#define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK) >> 5) +#define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Supersection Entry [AP] + * + * Access Permissions bits. + * @{ + */ +#define ALT_MMU_TTB1_SUPERSECTION_AP_MASK 0x00008c00 +#define ALT_MMU_TTB1_SUPERSECTION_AP_GET(desc) ((((desc) & 0x00008000) >> 13) | (((desc) & 0x00000c00) >> 10)) +#define ALT_MMU_TTB1_SUPERSECTION_AP_SET(val) ((((val) << 13) & 0x00008000) | (((val) << 10) & 0x00000c00)) +/*! @} */ + +/*! + * \name First Level Translation Table Supersection Entry [TEX] + * + * The [TEX] field of the memory region attributes. [TEX] is an arcane reference to + * Type EXtension attribute. + * @{ + */ +#define ALT_MMU_TTB1_SUPERSECTION_TEX_MASK 0x00007000 +#define ALT_MMU_TTB1_SUPERSECTION_TEX_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_TEX_MASK) >> 12) +#define ALT_MMU_TTB1_SUPERSECTION_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB1_SUPERSECTION_TEX_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Supersection Entry [S] + * + * The Shareable bit. Determines whether the addressed region is shareable memory. + * @{ + */ +#define ALT_MMU_TTB1_SUPERSECTION_S_MASK 0x00010000 +#define ALT_MMU_TTB1_SUPERSECTION_S_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_S_MASK) >> 16) +#define ALT_MMU_TTB1_SUPERSECTION_S_SET(val) (((val) << 16) & ALT_MMU_TTB1_SUPERSECTION_S_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Supersection Entry [nG] + * + * The not global bit. Determines how the translation is marked in the TLB. + * @{ + */ +#define ALT_MMU_TTB1_SUPERSECTION_NG_MASK 0x00020000 +#define ALT_MMU_TTB1_SUPERSECTION_NG_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_NG_MASK) >> 17) +#define ALT_MMU_TTB1_SUPERSECTION_NG_SET(val) (((val) << 17) & ALT_MMU_TTB1_SUPERSECTION_NG_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Supersection Entry [NS] + * + * The Non-Secure [NS] bit. This bit specifies whether the translated PA is in + * the Secure or Non-Secure address map. + * @{ + */ +#define ALT_MMU_TTB1_SUPERSECTION_NS_MASK 0x00080000 +#define ALT_MMU_TTB1_SUPERSECTION_NS_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_NS_MASK) >> 19) +#define ALT_MMU_TTB1_SUPERSECTION_NS_SET(val) (((val) << 19) & ALT_MMU_TTB1_SUPERSECTION_NS_MASK) +/*! @} */ + +/*! + * \name First Level Translation Table Supersection Entry Supersection Base Address + */ +#define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK 0xff000000 +#define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK) >> 24) +#define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_SET(val) (((val) << 24) & ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK) +/*! @} */ + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_MMU_MGMT_MACRO_TTB2 MMU Management Macros - Second Level Translation Table + * + * The macro definitions in this section support access to the short-descriptor + * second-level table entries and their constituent fields. + * + * These macros may be used to create descriptor entry values that are passed to a + * second level translation table contruction function such as + * alt_mmu_ttb2_desc_set(). + * + * Each short-descriptor has a set of macro definitions of the following form: + * + * * \b ALT_MMU_TTB2__MASK - bit mask for the descriptor type + * and field. + * + * * \b ALT_MMU_TTB2__GET(desc) - extracts the field value + * from the descriptor entry \e + * desc. + * + * * \b ALT_MMU_TTB2__SET(val) - returns a field \e val + * shifted and masked that is + * suitable for setting a + * descriptor entry. + * @{ + */ +/*! + * + */ +#define ALT_MMU_TTB2_TYPE_MASK 0x00000003 +#define ALT_MMU_TTB2_TYPE_GET(desc) (((desc) & ALT_MMU_TTB2_TYPE_MASK) >> 0) +#define ALT_MMU_TTB2_TYPE_SET(val) (((val) << 0) & ALT_MMU_TTB2_TYPE_MASK) + +/*! + * \name Second Level Translation Table Large Page Table Entry [B] + * + * The [B] field of the memory region attributes. [B] is an arcane reference to + * Bufferable attribute. + * @{ + */ +#define ALT_MMU_TTB2_LARGE_PAGE_B_MASK 0x00000004 +#define ALT_MMU_TTB2_LARGE_PAGE_B_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_B_MASK) >> 2) +#define ALT_MMU_TTB2_LARGE_PAGE_B_SET(val) (((val) << 2) & ALT_MMU_TTB2_LARGE_PAGE_B_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Large Page Table Entry [C] + * + * The [C] field of the memory region attributes. [C] is an arcane reference to + * Cacheable attribute. + * @{ + */ +#define ALT_MMU_TTB2_LARGE_PAGE_C_MASK 0x00000008 +#define ALT_MMU_TTB2_LARGE_PAGE_C_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_C_MASK) >> 3) +#define ALT_MMU_TTB2_LARGE_PAGE_C_SET(val) (((val) << 3) & ALT_MMU_TTB2_LARGE_PAGE_C_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Large Page Table Entry [AP] + * + * Access Permissions bits. + * @{ + */ +#define ALT_MMU_TTB2_LARGE_PAGE_AP_MASK 0x00000230 +#define ALT_MMU_TTB2_LARGE_PAGE_AP_GET(desc) ((((desc) & 0x00000200) >> 7) | (((desc) & 0x00000030) >> 4)) +#define ALT_MMU_TTB2_LARGE_PAGE_AP_SET(val) ((((val) << 7) & 0x00000200) | (((val) << 4) & 0x00000030)) +/*! @} */ + +/*! + * \name Second Level Translation Table Large Page Table Entry [S] + * + * The Shareable bit. Determines whether the addressed region is shareable memory. + * @{ + */ +#define ALT_MMU_TTB2_LARGE_PAGE_S_MASK 0x00000400 +#define ALT_MMU_TTB2_LARGE_PAGE_S_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_S_MASK) >> 10) +#define ALT_MMU_TTB2_LARGE_PAGE_S_SET(val) (((val) << 10) & ALT_MMU_TTB2_LARGE_PAGE_S_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Large Page Table Entry [nG] + * + * The not global bit. Determines how the translation is marked in the TLB. + * @{ + */ +#define ALT_MMU_TTB2_LARGE_PAGE_NG_MASK 0x00000800 +#define ALT_MMU_TTB2_LARGE_PAGE_NG_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_NG_MASK) >> 11) +#define ALT_MMU_TTB2_LARGE_PAGE_NG_SET(val) (((val) << 11) & ALT_MMU_TTB2_LARGE_PAGE_NG_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Large Page Table Entry [TEX] + * + * The [TEX] field of the memory region attributes. [TEX] is an arcane reference to + * Type EXtension attribute. + * @{ + */ +#define ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK 0x00007000 +#define ALT_MMU_TTB2_LARGE_PAGE_TEX_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK) >> 12) +#define ALT_MMU_TTB2_LARGE_PAGE_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Large Page Table Entry [XN] + * + * The Execute-Never bit. Determines whether the processor can execute software + * from the addressed region. + * @{ + */ +#define ALT_MMU_TTB2_LARGE_PAGE_XN_MASK 0x00008000 +#define ALT_MMU_TTB2_LARGE_PAGE_XN_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_XN_MASK) >> 15) +#define ALT_MMU_TTB2_LARGE_PAGE_XN_SET(val) (((val) << 15) & ALT_MMU_TTB2_LARGE_PAGE_XN_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Large Page Table Entry Large Page Base Address + * @{ + */ +#define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK 0xffff0000 +#define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK) >> 16) +#define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_SET(val) (((val) << 16) & ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Small Page Table Entry [XN] + * + * The Execute-Never bit. Determines whether the processor can execute software + * from the addressed region. + * @{ + */ +#define ALT_MMU_TTB2_SMALL_PAGE_XN_MASK 0x00000001 +#define ALT_MMU_TTB2_SMALL_PAGE_XN_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_XN_MASK) >> 0) +#define ALT_MMU_TTB2_SMALL_PAGE_XN_SET(val) (((val) << 0) & ALT_MMU_TTB2_SMALL_PAGE_XN_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Small Page Table Entry [B] + * + * The [B] field of the memory region attributes. [B] is an arcane reference to + * Bufferable attribute. + * @{ + */ +#define ALT_MMU_TTB2_SMALL_PAGE_B_MASK 0x00000004 +#define ALT_MMU_TTB2_SMALL_PAGE_B_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_B_MASK) >> 2) +#define ALT_MMU_TTB2_SMALL_PAGE_B_SET(val) (((val) << 2) & ALT_MMU_TTB2_SMALL_PAGE_B_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Small Page Table Entry [C] + * + * The [C] field of the memory region attributes. [C] is an arcane reference to + * Cacheable attribute. + * @{ + */ +#define ALT_MMU_TTB2_SMALL_PAGE_C_MASK 0x00000008 +#define ALT_MMU_TTB2_SMALL_PAGE_C_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_C_MASK) >> 3) +#define ALT_MMU_TTB2_SMALL_PAGE_C_SET(val) (((val) << 3) & ALT_MMU_TTB2_SMALL_PAGE_C_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Small Page Table Entry [AP] + * + * Access Permissions bits. + * @{ + */ +#define ALT_MMU_TTB2_SMALL_PAGE_AP_MASK 0x00000230 +#define ALT_MMU_TTB2_SMALL_PAGE_AP_GET(desc) ((((desc) & 0x00000200) >> 7) | (((desc) & 0x00000030) >> 4)) +#define ALT_MMU_TTB2_SMALL_PAGE_AP_SET(val) ((((val) << 7) & 0x00000200) | (((val) << 4) & 0x00000030)) +/*! @} */ + +/*! + * \name Second Level Translation Table Small Page Table Entry [TEX] + * + * The [TEX] field of the memory region attributes. [TEX] is an arcane reference to + * Type EXtension attribute. + * @{ + */ +#define ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK 0x000001c0 +#define ALT_MMU_TTB2_SMALL_PAGE_TEX_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK) >> 6) +#define ALT_MMU_TTB2_SMALL_PAGE_TEX_SET(val) (((val) << 6) & ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Small Page Table Entry [S] + * + * The Shareable bit. Determines whether the addressed region is shareable memory. + * @{ + */ +#define ALT_MMU_TTB2_SMALL_PAGE_S_MASK 0x00000400 +#define ALT_MMU_TTB2_SMALL_PAGE_S_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_S_MASK) >> 10) +#define ALT_MMU_TTB2_SMALL_PAGE_S_SET(val) (((val) << 10) & ALT_MMU_TTB2_SMALL_PAGE_S_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Small Page Table Entry [nG] + * + * The not global bit. Determines how the translation is marked in the TLB. + * @{ + */ +#define ALT_MMU_TTB2_SMALL_PAGE_NG_MASK 0x00000800 +#define ALT_MMU_TTB2_SMALL_PAGE_NG_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_NG_MASK) >> 11) +#define ALT_MMU_TTB2_SMALL_PAGE_NG_SET(val) (((val) << 11) & ALT_MMU_TTB2_SMALL_PAGE_NG_MASK) +/*! @} */ + +/*! + * \name Second Level Translation Table Small Page Table Entry Large Page Base Address + * @{ + */ +#define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK 0xfffff000 +#define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK) >> 12) +#define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_SET(val) (((val) << 12) & ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK) +/*! @} */ + +/*! @} */ + + +/******************************************************************************/ +/*! \addtogroup ALT_MMU_MGMT_STRUCT_TTB1 MMU Management Data Structures - First Level Translation Table + * + * The data structure declarations in this section support direct access to the + * short-descriptor first-level table entries and their constituent fields. + * + * These data structures are an alternative method to create descriptor entry + * values that are passed to a first level translation table contruction function + * such as alt_mmu_ttb1_desc_set(). + * + * @{ + */ + +/*! + * This type defines the structure of a First Level Translation Table Fault Entry. + */ +typedef struct ALT_MMU_TTB1_FAULT_s +{ + uint32_t type : 2; + uint32_t : 30; +} ALT_MMU_TTB1_FAULT_t; + +/*! + * This type defines a union for accessing a First Level Translation Table Fault + * Entry by fields or aggregate raw entry value. + */ +typedef union ALT_MMU_TTB1_FAULT_ENTRY_u +{ + ALT_MMU_TTB1_FAULT_t fld; /*!< access to individual entry data fields */ + uint32_t raw; /*!< access to aggregate entry value */ +} ALT_MMU_TTB1_FAULT_ENTRY_t; + +/*! + * This type defines the structure of a First Level Translation Table Page Table + * Entry. + */ +typedef struct ALT_MMU_TTB1_PAGE_TABLE_s +{ + uint32_t type : 2; /*!< Descriptor type field */ + uint32_t : 1; + uint32_t ns : 1; /*!< The Non-Secure [NS] bit. This bit specifies + * whether the translated PA is in the Secure + * or Non-Secure address map. + */ + uint32_t : 1; + uint32_t domain : 4; /*!< Domain field. Page table descriptor applies + * to all entries in the corresponding + * second-level translation table. + */ + uint32_t : 1; + uint32_t base_addr : 22; /*!< Page Table Base Address */ +} ALT_MMU_TTB1_PAGE_TABLE_t; + +/*! + * This type defines a union for accessing a First Level Translation Table Page + * Table Entry by fields or aggregate raw entry value. + */ +typedef union ALT_MMU_TTB1_PAGE_TABLE_ENTRY_u +{ + ALT_MMU_TTB1_PAGE_TABLE_t fld; /*!< access to individual entry data fields */ + uint32_t raw; /*!< access to aggregate entry value */ +} ALT_MMU_TTB1_PAGE_TABLE_ENTRY_t; + +/*! + * This type defines the structure of a First Level Translation Table Section Entry. + */ +typedef struct ALT_MMU_TTB1_SECTION_s +{ + uint32_t type : 2; /*!< Descriptor type field */ + uint32_t b : 1; /*!< The [B] field of the memory region + * attributes. [B] is an arcane reference to + * Bufferable attribute. + */ + uint32_t c : 1; /*!< The [C] field of the memory region + * attributes. [C] is an arcane reference to + * Cacheable attribute. + */ + + uint32_t xn : 1; /*!< The Execute-Never bit. Determines whether + * the processor can execute software from the + * addressed region. + */ + uint32_t domain : 4; /*!< Domain field. */ + uint32_t : 1; + uint32_t ap_1_0 : 2; /*!< Access Permissions AP[1:0] bits. */ + uint32_t tex : 3; /*!< The [TEX] field of the memory region + * attributes. [TEX] is an arcane reference to + * Type EXtension attribute. + */ + uint32_t ap_2 : 1; /*!< Access Permissions AP[2] bits. */ + uint32_t s : 1; /*!< The Shareable bit. Determines whether the + * addressed region is shareable memory. + */ + uint32_t ng : 1; /*!< The not global bit. Determines how the + * translation is marked in the TLB. + */ + uint32_t : 1; + uint32_t ns : 1; /*!< The Non-Secure [NS] bit. This bit specifies + * whether the translated PA is in the Secure + * or Non-Secure address map. + */ + uint32_t base_addr : 12; /*!< Section Base Address */ +} ALT_MMU_TTB1_SECTION_t; + +/*! + * This type defines a union for accessing a First Level Translation Table Section + * Entry by fields or aggregate raw entry value. + */ +typedef union ALT_MMU_TTB1_SECTION_ENTRY_u +{ + ALT_MMU_TTB1_SECTION_t fld; /*!< access to individual entry data fields */ + uint32_t raw; /*!< access to aggregate entry value */ +} ALT_MMU_TTB1_SECTION_ENTRY_t; + +/*! + * This type defines the structure of a First Level Translation Table Supersection + * Entry. + */ +typedef struct ALT_MMU_TTB1_SUPERSECTION_s +{ + uint32_t type : 2; /*!< Descriptor type field */ + uint32_t b : 1; /*!< The [B] field of the memory region + * attributes. [B] is an arcane reference to + * Bufferable attribute. + */ + uint32_t c : 1; /*!< The [C] field of the memory region + * attributes. [C] is an arcane reference to + * Cacheable attribute. + */ + + uint32_t xn : 1; /*!< The Execute-Never bit. Determines whether + * the processor can execute software from the + * addressed region. + */ + uint32_t domain : 4; /*!< Domain field. */ + uint32_t : 1; + uint32_t ap_1_0 : 2; /*!< Access Permissions AP[1:0] bits. */ + uint32_t tex : 3; /*!< The [TEX] field of the memory region + * attributes. [TEX] is an arcane reference to + * Type EXtension attribute. + */ + uint32_t ap_2 : 1; /*!< Access Permissions AP[2] bits. */ + uint32_t s : 1; /*!< The Shareable bit. Determines whether the + * addressed region is shareable memory. + */ + uint32_t ng : 1; /*!< The not global bit. Determines how the + * translation is marked in the TLB. + */ + uint32_t : 1; + uint32_t ns : 1; /*!< The Non-Secure [NS] bit. This bit specifies + * whether the translated PA is in the Secure + * or Non-Secure address map. + */ + uint32_t : 4; + uint32_t base_addr : 8; /*!< Supersection Base Address */ +} ALT_MMU_TTB1_SUPERSECTION_t; + +/*! + * This type defines a union for accessing a First Level Translation Table + * Supersection Entry by fields or aggregate raw entry value. + */ +typedef union ALT_MMU_TTB1_SUPERSECTION_ENTRY_u +{ + ALT_MMU_TTB1_SUPERSECTION_t fld; /*!< access to individual entry data fields */ + uint32_t raw; /*!< access to aggregate entry value */ +} ALT_MMU_TTB1_SUPERSECTION_ENTRY_t; + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_MMU_MGMT_STRUCT_TTB2 MMU Management Data Structures - Second Level Translation Table + * + * The data structure declarations in this section support direct access to the + * short-descriptor second-level table entries and their constituent fields. + * + * These data structures are an alternative method to create descriptor entry + * values that are passed to a first level translation table contruction function + * such as alt_mmu_ttb2_desc_set(). + * + * @{ + */ + +/*! + * This type defines the structure of a Second Level Translation Table Fault Entry. + */ +typedef struct ALT_MMU_TTB2_FAULT_s +{ + uint32_t type : 2; // b00 + uint32_t : 30; // IGNORE +} ALT_MMU_TTB2_FAULT_t; + +/*! + * This type defines a union for accessing a Second Level Translation Table Fault + * Entry by fields or aggregate raw entry value. + */ +typedef union ALT_MMU_TTB2_FAULT_ENTRY_u +{ + ALT_MMU_TTB2_FAULT_t fld; /*!< access to individual entry data fields */ + uint32_t raw; /*!< access to aggregate entry value */ +} ALT_MMU_TTB2_FAULT_ENTRY_t; + +/*! + * This type defines the structure of a Second Level Translation Table Large Page + * Table Entry. + */ +typedef struct ALT_MMU_TTB2_LARGE_PAGE_s +{ + uint32_t : 2; /*!< always b01 */ + uint32_t b : 1; /*!< The [B] field of the memory region + * attributes. [B] is an arcane reference to + * Bufferable attribute. + */ + uint32_t c : 1; /*!< The [C] field of the memory region + * attributes. [C] is an arcane reference to + * Cacheable attribute. + */ + uint32_t ap_1_0 : 2; /*!< Access Permissions AP[1:0] bits. */ + uint32_t : 3; // SBZ - b000 + uint32_t ap_2 : 1; /*!< Access Permissions AP[2] bits. */ + uint32_t s : 1; /*!< The Shareable bit. Determines whether the + * addressed region is shareable memory. + */ + uint32_t ng : 1; /*!< The not global bit. Determines how the + * translation is marked in the TLB. + */ + uint32_t tex : 3; /*!< The [TEX] field of the memory region + * attributes. [TEX] is an arcane reference to + * Type EXtension attribute. + */ + uint32_t xn : 1; /*!< The Execute-Never bit. Determines whether + * the processor can execute software from the + * addressed region. + */ + uint32_t base_addr : 16; /*!< Large Page Base Address PA[31:16] */ +} ALT_MMU_TTB2_LARGE_PAGE_t; + +/*! + * This type defines a union for accessing a Second Level Translation Table Large + * Page Table Entry by fields or aggregate raw entry value. + */ +typedef union ALT_MMU_TTB2_LARGE_PAGE_ENTRY_u +{ + ALT_MMU_TTB2_LARGE_PAGE_t fld; /*!< access to individual entry data fields */ + uint32_t raw; /*!< access to aggregate entry value */ +} ALT_MMU_TTB2_LARGE_PAGE_ENTRY_t; + +/*! + * This type defines the structure of a Second Level Translation Table Small Page + * Table Entry. + */ +typedef struct ALT_MMU_TTB2_SMALL_PAGE_s +{ + uint32_t xn : 1; /*!< The Execute-Never bit. Determines whether + * the processor can execute software from the + * addressed region. + */ + uint32_t : 1; /*!< always b1 */ + uint32_t b : 1; /*!< The [B] field of the memory region + * attributes. [B] is an arcane reference to + * Bufferable attribute. + */ + uint32_t c : 1; /*!< The [C] field of the memory region + * attributes. [C] is an arcane reference to + * Cacheable attribute. + */ + uint32_t ap_1_0 : 2; /*!< Access Permissions AP[1:0] bits. */ + uint32_t tex : 3; /*!< The [TEX] field of the memory region + * attributes. [TEX] is an arcane reference to + * Type EXtension attribute. + */ + uint32_t ap_2 : 1; /*!< Access Permissions AP[2] bits. */ + uint32_t s : 1; /*!< The Shareable bit. Determines whether the + * addressed region is shareable memory. + */ + uint32_t ng : 1; /*!< The not global bit. Determines how the + * translation is marked in the TLB. + */ + uint32_t base_addr : 20; /*!< Small Page Base Address PA[31:12] */ +} ALT_MMU_TTB2_SMALL_PAGE_t; + +/*! + * This type defines a union for accessing a Second Level Translation Table Small + * Page Table Entry by fields or aggregate raw entry value. + */ +typedef union ALT_MMU_TTB2_SMALL_PAGE_ENTRY_u +{ + ALT_MMU_TTB2_SMALL_PAGE_t fld; /*!< access to individual entry data fields */ + uint32_t raw; /*!< access to aggregate entry value */ +} ALT_MMU_TTB2_SMALL_PAGE_ENTRY_t; + +/*! @} */ + +/******************************************************************************/ +/*! + * Initializes the processor MMU subsystem. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_init(void); + +/******************************************************************************/ +/*! + * Uninitializes the processor MMU subsystem. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_uninit(void); + +/******************************************************************************/ +/*! + * Initialize a block of memory for use as a first level translation table. + * + * The memory block is initialized for use as a first level translation table by + * setting all table entries to section fault entry values. + * + * \param ttb1 + * A pointer to a block of memory to be initialized for use as a + * first level translation table. The memory block must be at least + * ALT_MMU_TTB1_SIZE bytes and the pointer aligned to 2^x bytes + * where x is (14 - TTBCR.N). TTBCR.N is configured using + * alt_mmu_TTBCR_set()'s base_addr_width argument. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Alignment requirements documented at ARMv7-A,R, section B4.1.154. + * \endinternal + */ +ALT_STATUS_CODE alt_mmu_ttb1_init(uint32_t* ttb1); + +/******************************************************************************/ +/*! + * Set the first level translation table descriptor entry for the virtual address + * \e va to the descriptor value \e desc. + * + * Based on the virtual address parameter value \e va, this function computes the + * appropriate entry in the first level translation table specified by the base + * address value \e ttb1 to set. + * + * If the descriptor type of \e desc is a fault, section, or page table descriptor + * then the virtual address value \e va must be a 1 MiB aligned address and the + * corresponding entry in the first level translation table specified by \e ttb1 + * is set to the \e desc value. + * + * If the descriptor type of \e desc is a supersection descriptor then the virtual + * address value \e va must be a 16 MiB aligned address and the corresponding 16 + * entries in the first level translation table specified by \e ttb1 are set to \e + * desc values. + * + * \param ttb1 + * The base address of the first level translation table. + * + * \param va + * The virtual address of the first level translation table + * descriptor entry to set the descriptor entry value for. The \e va + * must be an appropriately aligned address (1 or 16 MiB aligned) + * value per type of the \e desc. + * + * \param desc + * The short descriptor value to use for the virtual address entry in + * the first level translation table. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_ttb1_desc_set(uint32_t* ttb1, + const void* va, + const uint32_t desc); + +/******************************************************************************/ +/*! + * Set the second level translation table descriptor entry for the virtual address + * \e va to the descriptor value \e desc. + * + * Based on the virtual address parameter value \e va, this function computes the + * appropriate entry in the second level translation table to set. This requires + * the corresponding first level translation table page table descriptor entry to + * have been previously configured prior to setting up any second level + * translation table entries in that 1 MiB virtual address range. + * + * If the descriptor type of \e desc is a fault or small page descriptor then the + * virtual address value \e va must be a 4 KiB aligned address and the + * appropriate entry in the second level translation table is set to the + * \e desc value. + * + * If the descriptor type of \e desc is a large page descriptor then the virtual + * address value \e va must be a 64 KiB aligned address and the appropriate 16 + * entries in the second level translation table are set to the \e desc value. + * + * \param ttb1 + * The base address of the first level translation table. + * + * \param va + * The virtual address of the second level translation table + * descriptor entry to set the descriptor entry value for. The \e va + * must be an appropriately aligned address (4 or 64 KiB aligned) + * value per type of the \e desc. + * + * \param desc + * The short descriptor value to use for the virtual address entry in + * the first level translation table. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_ttb2_desc_set(const uint32_t* ttb1, + const void* va, + const uint32_t desc); + +/******************************************************************************/ +/*! + * Disable operation of the MMU. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_disable(void); + +/******************************************************************************/ +/*! + * Enable operation of the MMU. + * + * This function only enables the MMU. It does not perform any of the necessary + * prerequisite configuration of the MMU. + * + * Before this function is called, the MMU configuration should have been + * established. This means: + * * The MMU translation table(s) configured. + * * The translation table control register (TTBCR) configured. + * * The values of the TTBR0 (and TTBR1 if applicable) set to the translation + * table base addresses. + * * The domain access control register (DACR) configured. + * * The TLBs, caches, and branch predication buffers invalidated. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_enable(void); + +/******************************************************************************/ +/*! + * Get the current address value in the Translation Table Base Register 0. + * + * \returns The address value in the Translation Table Base Register 0. + */ +void *alt_mmu_TTBR0_get(void); + +/******************************************************************************/ +/*! + * Set the address value in the Translation Table Base Register 0. + * + * \param addr + * The base address of a first level translation table. + * The memory block must be aligned to 2^x bytes where + * x is (14 - TTBCR.N). TTBCR.N is configured using + * alt_mmu_TTBCR_set()'s base_addr_width argument. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Alignment requirements documented at ARMv7-A,R, section B4.1.154. + * \endinternal + */ +ALT_STATUS_CODE alt_mmu_TTBR0_set(const void* addr); + +/******************************************************************************/ +/*! + * Get the current address value in the Translation Table Base Register 1. + * + * \returns The address value in the Translation Table Base Register 1. + */ +void *alt_mmu_TTBR1_get(void); + +/******************************************************************************/ +/*! + * Set the address value in the Translation Table Base Register 1. + * + * \param addr + * The base address of a first level translation table. + * The memory block must be aligned to 2^14 bytes. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Alignment requirements documented at ARMv7-A,R, section B4.1.155. + * \endinternal + */ +ALT_STATUS_CODE alt_mmu_TTBR1_set(const void* addr); + +/******************************************************************************/ +/*! + * Sets the control options in the Translation Table Base Control Register + * (TTBCR). + * + * Many APIs within the MMU module are designed to work with a base address + * width set to 0. Setting a value other than 0 will cause problems many APIs + * not specifically designed to work with a non-zero value. These include the + * following APIs: + * * alt_mmu_ttb1_desc_set() + * * alt_mmu_ttb2_desc_set() + * * alt_mmu_va_space_create() + * + * \param enable_ttbr0_walk + * A value of \b true enables translation table walks for TLB misses + * using TTBR0. A value of \b false causes a TLB miss on an address + * that is translated using TTBR0 to generate a translation fault and + * a translation table walk is performed. + * + * \param enable_ttbr1_walk + * A value of \b true enables translation table walks for TLB misses + * using TTBR1. A value of \b false causes a TLB miss on an address + * that is translated using TTBR1 to generate a translation fault and + * a translation table walk is performed. + * + * \param base_addr_width + * Specifies the width of the base address held in TTBR0. In TTBR0, + * the base address field is bits[31:14-N] where N is the value of + * the \e base_addr_width parameter. \e base_addr_width may be any + * value from 0 to 7. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_TTBCR_set(const bool enable_ttbr0_walk, + const bool enable_ttbr1_walk, + const uint32_t base_addr_width); + +/******************************************************************************/ +/*! + * Sets the access permissions for the sixteen memory domains of the Domain Access + * Control Register (DACR). + * + * \param domain_ap + * An array of sixteen domain access permission settings for each of + * the respective sixteen memory domains. + * + * \param num_elem + * The number of domain access permission elements in \e + * domain_ap. This should always be 16. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_DACR_set(const ALT_MMU_DAP_t domain_ap[], + const size_t num_elem); + +/******************************************************************************/ +/*! + * Sets the Context ID Register (CONTEXTIDR). + * + * This function sets the the current Process Identifier (PROCID) and the Address + * Space Identifier (ASID) values of the Context ID Register (CONTEXTIDR). + * + * \param procid + * The process identifier value. This field must be programmed with a + * unique value that identifies the current process should not exceed + * 22 bits in width. + * + * \param asid + * The address space identifier. This field is programmed with the + * value of the current ASID and should not exceed 8 bits in width. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_CONTEXTIDR_set(const uint32_t procid, const uint32_t asid); + +/******************************************************************************/ +/*! + * Invalidate the entire unified TLB. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_tlb_invalidate(void); + +/******************************************************************************/ +/*! + * Invalidate the entire unified TLB in the inner shareable domain. + * + * This function applies the unified TLB invalidation operation across all + * processors in the same inner shareable domain. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_tlb_invalidate_is(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_MMU_VA MMU Virtual Address Space Creation + * + * This section provides functions to support the creation of a virtual address + * space from a set of high level memory region descriptions. + * + * The virtual address space creation results in the allocation and initialization + * of a set of MMU first and second level translaction tables that can be used to + * actualize the virtual address space once the MMU is configured and enabled. + * + * The virtual address space creation functions attempt to create a space optimal + * set of first and second level translation tables that represent the address + * space specified in the memory region descriptors. + * + * The user is responsible for providing the storage required for the first and + * second level translation tables. The mechanism for allocating storage is via + * the user defined callback function as defined by the type \ref alt_mmu_ttb_alloc_t. + * + * The simplified virtual address space model is implemented by the following ARM + * Cortex-A9 MPCore configuration: + * + * * MMU short descriptor translation table format. + * + * * Supports storage optimal first and second level translation table encoding of + * virtual address space specified in memory region descriptors. + * + * * Memory region attributes encoded in TEX[2:0], C, and B with TEX remap + * disabled (i.e. SCTLR.TRE is set to 0). + * + * * Memory access control uses 3-bit AP[2:0] access permissions and SCTLR.AFE = 0 + * + * * MMU translation table DOMAIN entry values are set to 0 and the Domain Access + * Control Register (DACR) has all domain access permissions set to \b Client + * (i.e. the access permissions set in translation tables are in effect). + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type defines a structure for specifying the properties of a virtual + * address range called a memory region. The structure defines fields to specify + * the virtual to physical address mapping, the access permissions, the + * shareability, the ordering, and the cacheability properties of a particular + * memory region that comprises a virtual address space. + */ +typedef struct ALT_MMU_MEM_REGION_s +{ + void * va; /*!< The beginning virtual address for the memory + * region. The address must be aligned to one of 4KiB, + * 64KiB, 1MiB, or 16MiB boundaries. + */ + void * pa; /*!< The beginning physical address mapping for the + * virtual address of the memory region. The address + * must be aligned to one of 4KiB, 64KiB, 1MiB, or 16MiB + * boundaries. + */ + uint32_t size; /*!< The size of the memory region in bytes. The size + * must be a multiple of 4KiB, 64KiB, 1MiB, or 16MiB + * sizes. + */ + ALT_MMU_AP_t access; /*!< The access permissions for the memory region. */ + ALT_MMU_ATTR_t attributes;/*!< The memory region attributes. These attributes + * determine the memory type (ordering), cache + * policy, and as a possible side effect, the + * shareablity of the memory region. + */ + ALT_MMU_TTB_S_t shareable; /*!< The shareability of the memory region. */ + ALT_MMU_TTB_XN_t execute; /*!< Whether instructions can be executed from this + * memory region. + */ + ALT_MMU_TTB_NS_t security; /*!< Controls whether address translations made from + * the secure state translate physical address in + * the secure or non-secure address map. + */ +} ALT_MMU_MEM_REGION_t; + +/*! + * Type definition for a user defined function that allocates storage for MMU + * translation tables. This memory is intended to be used by + * alt_mmu_va_space_create() to allocate the TTB1 and, if needed, TTB2. + * alt_mmu_va_space_create() allocates all the space required with one single + * call and divides the space up internally. + * + * The function returns a \e size block of memory. The returned pointer must be + * a 16 KiB (2^14) aligned address. + * + * \param size + * The size in bytes of the storage request. The value will be + * same reported by alt_mmu_va_space_storage_required() if + * non-zero, given the same set of memory regions. + * + * \param context + * A user provided context for the allocator function. + * + * \returns A 16 KiB aligned pointer to the allocated memory or NULL if the + * storage request cannot be satisfied. + * + * \internal + * Alignment requirements for TTBR0 documented at ARMv7-A,R, section B4.1.154. + * The VA space APIs expects TTBCR.N to be 0. + * For TTB2 (page tables), the page table base address in TTB1 is + * bits[31:10]. Thus it must be 2^10 byte aligned or 1 KiB. + * This is document at ARMv7-A,R, section B3.5.1. + * \endinternal + */ +typedef void* (*alt_mmu_ttb_alloc_t)(const size_t size, void * context); + +/******************************************************************************/ +/*! + * Returns the cumulative size in bytes of the storage required for the first and + * second level translation tables that implement the virtual address space + * defined by the array of memory region descriptors. + * + * This function does not allocate any actual storage but merely computes the + * amount of storage that would be required by the MMU translation tables created + * for the specified virtual address space. + * + * \param mem_regions + * A pointer to an array of memory region descriptors that define the + * virtual address space. + * + * \param num_mem_regions + * The number of memory region descriptors in the \e mem_regions + * array. + * + * \returns The number of storage bytes required for the MMU translation + * tables described by the virtual address space specfication, or + * zero if an error has occurred. + */ +size_t alt_mmu_va_space_storage_required(const ALT_MMU_MEM_REGION_t* mem_regions, + const size_t num_mem_regions); + +/******************************************************************************/ +/*! + * Creates the MMU translation tables needed to implement the virtual address + * space defined by the memory region descriptors. + * + * The address space defined by the memory regions should have no overlapping + * virtual address ranges. + * + * The largest region that can be specified by a single entry is 2 GiB. Use multiple + * entries to describe a memory region larger than 2 GiB. + * + * Any address ranges in the potential 4 GiB virtual address space left + * unspecified in the \e mem_regions parameter default to fault descriptor entries + * in the generated translation tables. + * + * \param ttb1 + * [out] A pointer to the MMU first level translation table created + * to implement the virtual address space. + * + * \param mem_regions + * A pointer to an array of memory region descriptors that define the + * virtual address space. + * + * \param num_mem_regions + * The number of memory region descriptors in the \e mem_regions + * array. + * + * \param ttb_alloc + * A pointer to a user defined function used for allocating storage + * for first and second level translation tables. + * + * \param ttb_alloc_context + * A user provided context for the allocation function. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_va_space_create(uint32_t ** ttb1, + const ALT_MMU_MEM_REGION_t* mem_regions, + const size_t num_mem_regions, + alt_mmu_ttb_alloc_t ttb_alloc, + void * ttb_alloc_context); + +/******************************************************************************/ +/*! + * Enables the virtual address space described by the MMU translation table \e + * ttb1. + * + * This function actualizes the virtual address space rooted a the MMU first level + * translation table \e ttb1. The function performs the following steps to enable + * the virtual address space: + * * Configure the Translation Table Control Register (TTBCR) to use a single + * table (i.e. TTBR0). + * * Set Translation Table Base Register (TTBR0) to \e ttb1. + * * Configure Domain Access Control Register (DACR) to the client domain. + * * Invalidate + * - TLBs + * - caches + * - branch prediction buffers (BTAC, etc.) + * * Enable MMU and branch prediction. + * + * \param ttb1 + * The base address of a first level translation table. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_mmu_va_space_enable(const uint32_t * ttb1); + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_MMU_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_mpu_registers.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_mpu_registers.h new file mode 100644 index 000000000..811bf7e2f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_mpu_registers.h @@ -0,0 +1,156 @@ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_MPUSCU_H__ +#define __ALT_MPUSCU_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/************************************************************************************************************/ +/* alt_mpuscu.h */ +/* */ +/* Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog */ +/* Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor. */ +/* */ +/************************************************************************************************************/ + +#ifndef ALT_HPS_ADDR +#define ALT_HPS_ADDR 0x00 +#endif + + +/* ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h */ +/* and is the address of the base of the Snoop Control Unit (SCU) */ +#define GLOBALTMR_BASE (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET) +#define CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET) +#define CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET) +#define CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET) +#define CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET) + + + /* offsets */ + /* Global Timer offsets */ +#define GLOBALTMR_MODULE_BASE_OFFSET 0x00000200 +#define GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000 +#define GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004 +#define GLOBALTMR_CTRL_REG_OFFSET 0x00000008 +#define GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C +#define GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010 +#define GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014 +#define GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018 + +/* Global Timer bitmasks */ +#define GLOBALTMR_ENABLE_BIT 0x00000001 +#define GLOBALTMR_COMP_ENABLE_BIT 0x00000002 +#define GLOBALTMR_INT_ENABLE_BIT 0x00000004 +#define GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008 +#define GLOBALTMR_PS_MASK 0x0000FF00 +#define GLOBALTMR_PS_SHIFT 8 +#define GLOBALTMR_INT_STATUS_BIT 0x00000001 + +/* Global timer constants */ +#define GLOBALTMR_MAX 0xFFFFFFFF +#define GLOBALTMR_PS_MAX 0x000000FF + + +/* Private timer offsets */ +#define CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600 +#define CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000 +#define CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004 +#define CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008 +#define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C + +/* Private timer bitmasks */ +#define CPU_PRIV_TMR_ENABLE 0x00000001 +#define CPU_PRIV_TMR_AUTO_RELOAD 0x00000002 +#define CPU_PRIV_TMR_INT_EN 0x00000004 +#define CPU_PRIV_TMR_PS_MASK 0x0000FF00 +#define CPU_PRIV_TMR_PS_SHIFT 8 +#define CPU_PRIV_TMR_INT_STATUS 0x00000001 + +/* Private timer constants */ +#define CPU_PRIV_TMR_MAX 0xFFFFFFFF +#define CPU_PRIV_TMR_PS_MAX 0x000000FF + + + + /* Watchdog timer offsets */ +#define WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620 +#define WDOG_LOAD_REG_OFFSET 0x00000000 +#define WDOG_CNTR_REG_OFFSET 0x00000004 +#define WDOG_CTRL_REG_OFFSET 0x00000008 +#define WDOG_INTSTAT_REG_OFFSET 0x0000000C +#define WDOG_RSTSTAT_REG_OFFSET 0x00000010 +#define WDOG_DISABLE_REG_OFFSET 0x00000014 + + /* Watchdog timer bitmasks : */ + /* Control Register bitmasks */ +#define WDOG_TMR_ENABLE 0x00000001 +#define WDOG_AUTO_RELOAD 0x00000002 +#define WDOG_INT_EN 0x00000004 +#define WDOG_WDT_MODE 0x00000008 +#define WDOG_PS_MASK 0x0000FF00 +#define WDOG_PS_SHIFT 8 + /* Interrupt Status Register bitmasks */ +#define WDOG_INT_STAT_BIT 0x00000001 + /* Reset Status Register bitmasks */ +#define WDOG_RST_STAT_BIT 0x00000001 + + /* Watchdog timer constants */ +#define WDOG_TMR_MAX UINT32_MAX +#define WDOG_PS_MAX UINT8_MAX +#define WDOG_DISABLE_VAL0 0x12345678 +#define WDOG_DISABLE_VAL1 0x87654321 + + + + /* Interrupt Manager offsets */ +/* */ +#define INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100 +#define INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000 +#define INT_DIST_TYPE_REG 0x00000004 + + +/* Upper bound of the MPUSCU address space */ +#define MPUSCU_MAX 0x00001FFF + + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_MPUSCU_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_nand_flash.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_nand_flash.h new file mode 100644 index 000000000..08eeb5842 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_nand_flash.h @@ -0,0 +1,1019 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/*! \file + * Altera - NAND Flash Controller Module + */ + +#ifndef __ALT_NAND_FLASH_H__ +#define __ALT_NAND_FLASH_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_NAND_FLASH NAND Flash Controller + * + * This module defines an API for configuration and management of access to NAND + * flash memory devices through the HPS NAND flash controller. + * + * This API supports the following features: + * * Support for ONFI 1.0 devices or legacy devices that can be identified by + * the NAND flash controller. + * * Automatic initialization and discovery of supported NAND flash devices. + * * ECC protection in hardware. + * * Erase by block. + * * Read/Write by (whole) pages. + * * DMA read/write transfers. + * + * This API provides basic I/O operations to unmanaged NAND flash memory with + * optional hardware assisted ECC protection. This module does not provide higher + * level flash I/O features such as a flash file system or capabilities for bad + * block life cycle management or wear leveling. + + * Support of certain operational features may be device dependent and therefore + * it is important to consult the data sheet for the specific NAND flash device + * that the NAND flash controller will interface to. + * + * The comments in this module use the following NAND flash terminology: + * * \b Plane - A collection of blocks typically on a single die of a multi-die + * device. + * * \b Block - The basic unit of NAND flash memory. Blocks are the smallest unit + * that can be erased. Blocks contain pages. + * * \b Page - A subdivision of a block. It contains the data payload and spare + * data areas used to store ECC and bad block information. + * * \b Sector - A subdivision of a page. It contains the data payload protected + * by ECC. + * * \b Spare - The area of a page used to store ECC and bad block information. + * + * The NAND flash controller uses indexed addressing to operate on flash device + * blocks or pages. The NAND flash 32-bit address is organized as follows: + * + * Bits | Description + * :----------|:------------------------------------------------------------------------- + * [31:24] | Reserved - Unused + * [23:\e m] | Specifies the block address portion of the address. + * [\e m:0] | Specifies the page address portion of the address. + * + * where \e m depends on the number of pages per block for the flash device. + * + * For functions expecting \e block_addr parameters, only the bits 23 : \e m are + * relevant in a 32-bit address argument value. All other bits should be zero or a + * ALT_E_BAD_ARG is returned. + * + * For functions expecting \e page_addr parameters, both the bits \e m : 0 + * specifying the page as well as the bits 23 : \e m specifying the block + * containing the page are relevant in a 32-bit address argument. All other bits + * should be zero or a ALT_E_BAD_ARG is returned. + * + * \internal + * General Implementation Notes: + * * Command data and control paths that bypass HW ECC or require SW ECC are not + * used in this implementation or supported by the API. This does not imply that + * a user must elect to enable ECC in order to use flash memory but if the user + * so chooses then this module API only employs HW assisted ECC protection in + * its implementation. + * * Whether to use ECC protection or not should be decided from the first used of + * the NAND flash device and then used consistently thereafter. Once ECC + * protection is enabled then the flash memory locations must be initialized + * before ever reading from them. Flash memory is initialized by erasing and + * then writing to the flash memory while ECC is enabled. + * * The ECC program mode of "Main Area Transfer Mode" operation is used and + * maintained throughout the implementation of this API. No API is provided for + * switching ECC program modes in order to simplify the implementation and user + * programming model. + * \endinternal + * + * @{ + */ + +/*! + * Type definition for a callback function prototype used by NAND flash controller + * API functions to notify users of asynchronous operation completion or + * operational error status. + * + * \param status + * The final status of the asynchronous operation success or failure. + * + * \param completion_arg + * A pointer for passing user defined data. The content of this + * parameter is user defined and is passed when the asynchronous + * operation is initiated. + */ +typedef void (*alt_nand_callback_t)(ALT_STATUS_CODE status, void *callback_arg); + +/*! + * Type definition for a user defined custom flash device initialization + * function. This function should be provided for flash devices that do not + * support automatic device discovery and parameter configuration or devices + * where customized settings are desired. + * + * This function is invoked by the alt_nand_flash_init() routine at the proper + * point during the NAND flash controller initialization process. + * + * Returning any status code other than ALT_E_SUCCESS from this custom + * initialization function will cause the alt_nand_flash_init() function to fail + * as well. + * + * \param user_arg + * A pointer for optionally passing user defined data. The content of + * this parameter is user defined and its value may be NULL if + * unused. + * + * \retval ALT_E_SUCCESS Custom flash device initialization was successful. + * \retval ALT_E_ERROR Custom flash device initialization failed. + */ +typedef ALT_STATUS_CODE (*alt_nand_flash_custom_init_t)(void *user_arg); + +/*! + * This function initializes the NAND flash controller and attached flash device by: + * * Taking the NAND flash controller out of reset. + * * Performing automatic NAND flash device discovery and parameter configuration + * for supported devices. + * * Optionally loading block 0, page 0 of the device and configuring direct read + * access (preloader use case only). + * * And assuming the device discovery and parameter configuration (automatic or + * custom) process is successful, then scans the device for blocks marked as + * defective at manufacture time and builds a bad block table. The bad block + * table is used at runtime to avoid erasing or programming any block marked as + * defective. + * + * \param load_block0_page0 + * If \b true then load block 0, page 0 from the flash device and + * configure the NAND flash controller for direct read access. This + * option is typically used by custom preloaders and should be set to + * \b false by most users. + * + * \param page_size_512 + * If \b true the flash device has a 512 byte page size. This type of + * device typically does not support automatic discovery and + * therefore requires custom flash device initialization via the \e + * custom_init function. + * + * \param custom_init + * A pointer to a user defined function to perform customized flash + * device initialization. The function must program the applicable + * NAND flash controller registers in the config group based on + * specific device features and operational performance + * parameters. The NAND flash controller registers are accessible via + * the NAND flash controller SoCAL header file "socal/alt_nand.h". A + * NULL value for this parameter allows the NAND flash controller to + * do automatic device discovery and parameter configuration. A NULL + * value should normally be passed for ONFI and supported legacy + * flash devices. + * + * \param user_arg + * A user defined argument that is passed to the custom + * initialization function when invoked. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * See: + * * Cadence DB + * - Section 4.4 Initialization Protocol + * - Section 11.2 Device Initialization Sequence + * - Section 11.3 Device Operation Control (Maybe?) + * * CV Device Handbook + * - Discovery and Initialization + * - Bootstrap Interface + * - Configuration by Host (Provide SW hook) + * - Clocks + * - Resets + * - Device Initialization Sequence + * * Open NAND Flash Interface Specification Revision 1.0 + * - Section 3.2. Factory Defect Mapping for bad block table construction. + * + * 1) Discovery and Initialization section of HPS TRM + * 2) Bootstrap Interface section of HPS TRM + * 3) Configuration by Host section of HPS TRM + * + * Checks: + * - nand_x_clk and nand_clk + * + * ONFI - Use ONFI discovery protocol to identify device and read its feature properties. + * + * Legacy - Use the Read Electronic Signature command to identify device. + * + * Others - Generally 512 byte page size devices. + * + * Unless bootstrap_inhibit_b0p0_load (sysmgr.nandgrp.bootstrap.noloadb0p0) signal + * is asserted, the NAND flash controller will page load block 0/page 0 to + * allow for booting. + * + * If bootstrap_inhibit_init () is asserted the NAND flash controller do not + * perform initialization and just issues a RESET command to the device. + * + * \endinternal + */ +ALT_STATUS_CODE alt_nand_flash_init(const bool load_block0_page0, + const bool page_size_512, + alt_nand_flash_custom_init_t custom_init, + void *user_arg); + +/*! + * Uninitialize the NAND flash controller. + * + * Uninitialize the NAND flash controller by putting the flash controller into + * reset. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_nand_flash_uninit(void); + +/*! + * Defines an value to represent an invalid or bad flash device address. + */ +#define ALT_NAND_INVALID_FLASH_ADDR 0xffffffff + +/*! + * Returns the block number of the specified block or page address. The returned + * block address is right shift aligned to bit 0. + * + * This function may be used after a successful call to alt_nand_flash_init(). + * + * \param addr + * A block or page address value. + * + * \returns The bit 0 right aligned block address portion of the \e addr + * argument. + */ +uint32_t alt_nand_block_address_get(const uint32_t addr); + +/*! + * Returns the page number of the specified block or page address. The returned + * page address is right shift aligned to bit 0. + * + * This function may be used after a successful call to alt_nand_flash_init(). + * + * \param addr + * A block or page address value. + * + * \returns The bit 0 right aligned page address portion of the \e addr + * argument. + */ +uint32_t alt_nand_page_address_get(const uint32_t addr); + +/*! + * Returns a valid block or page address for a flash device with the given block + * and page argument values. + * + * This function may be used after a successful call to alt_nand_flash_init(). + * + * \param block_num + * The flash device block number to use in composing the final flash + * device address. + * + * \param page_num + * The flash device page number within the block to use in composing + * the final flash device address. + * + * \returns A valid block or page address for the flash + * device. ALT_NAND_INVALID_FLASH_ADDR is returned if either of the \e + * block_num or \e page_num arguments is invalid for the device. + */ +uint32_t alt_nand_flash_addr_compose(const uint32_t block_num, + const uint32_t page_num); + +/*! + * Erases the designated flash device block. + * + * Erases the flash device block designated by \e block_addr. The erase operation + * proceeds asynchronously with a user callback notification upon completion or + * error. + * + * Flash memory must be erased before being written. Erasing sets all bits in a + * given block of flash memory to '1' which is the erased state. + * + * \param block_addr + * The block address to erase. + * + * \param completion_callback + * A user defined callback function that is called when the operation + * completes or an error occurs. + * + * \param completion_arg + * A user defined argument that is passed to the callback function + * when the operation completes or an error occurs. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * \retval ALT_E_BAD_BLK One or more device block(s) are marked defective + * and hence the operation was ignored. + * + * \internal + * See: + * * CV Device Handbook + * - Flash-Related Special Function Operations - Erase Operations + * + Single Block Erase + * + Multi-Plane Erase + * + * Command to erase a single block (section 5.2.3.1 of Cadence DB). + * \endinternal + */ +ALT_STATUS_CODE alt_nand_flash_block_erase(const uint32_t block_addr, + alt_nand_callback_t completion_callback, + void *completion_arg); + +/*! + * Read one or more pages from the flash device. + * + * Reads \e num_pages from the flash device beginning at \e page_addr. Whole pages + * are read from flash memory. The pages are copied into the \e dest location. + * + * If ECC is enabled then the NAND flash controller performs ECC correction and + * detection on the fly as data is read from the device and before being + * transferred out of the controller. + * + * \param page_addr + * The beginning page address to read. + * + * \param num_pages + * The number of pages to read. + * + * \param dest + * The address of the destination buffer. + * + * \param dest_size + * The size of the destination buffer in bytes. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * \retval ALT_E_BAD_BLK The device block is marked defective and hence the + * operation was ignored. + * \retval ALT_E_BUF_OVF The destination buffer does not contain enough space + * for the operation. + * \retval ALT_E_ECC_UNCOR An uncorrected ECC error occurred. + * + * \internal + * See: + * * CV Device Handbook + * - Indexed Addressing + * - MAP01 Commands + * - MAP10 Commands + * - Data DMA (ignore Burst DMA) + * * Pipeline Read-Ahead and Write-Ahead Operations + * + * Map01 Commands (section 5.2.2 of Cadence DB). + + * Pipeline read-ahead operations (sections 5.2.3.6 and 5.2.3.6.1 of Cadence DB). + * + * Do not use Map00 in this implementation. ECC correction is not performed while + * doing such operations and is not recommended in MLC devices. + * + * Entire page(s) are read. + * + * Use Map01 for single page reads. + * + * Use pipeline read-ahead technique to optimize multi-page reads. + * \endinternal + */ +ALT_STATUS_CODE alt_nand_flash_page_read(const uint32_t page_addr, + const uint32_t num_pages, + void *dest, + const uint32_t dest_size); + +/*! + * Write one or more pages to the flash device. + * + * Writes \e num_pages to the flash device beginning at \e page_addr. Whole pages + * are written to flash memory. The block(s) containing the pages must have been + * previously erased. + * + * \param page_addr + * The beginning page address to write. + * + * \param num_pages + * The number of pages to write. + * + * \param src + * The address of the source buffer containing th data to be written + * to the flash device. + * + * \param src_size + * The size of the source buffer in bytes. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * \retval ALT_E_BAD_BLK The device block is marked defective and hence the + * operation was ignored. + * \retval ALT_E_BUF_OVF The source buffer is larger than the flash device + * page(s) destination. + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_nand_flash_page_write(const uint32_t page_addr, + const uint32_t num_pages, + const void *src, + const uint32_t src_size); + +/*! + * Read one or more pages from the flash device using the NAND flash controller's + * internal DMA. The read operation proceeds asynchronously with a user callback + * notification upon completion or error. + * + * Reads \e num_pages from the flash device beginning at \e page_addr. Whole pages + * are read from flash memory. The pages are copied into the \e dest location. + * + * If ECC is enabled then the NAND flash controller performs ECC correction and + * detection on the fly as data is read from the device and before being + * transferred out of the controller. + * + * \param page_addr + * The beginning page address to read. + * + * \param num_pages + * The number of pages to read. + * + * \param dest + * The address of the destination buffer. + * + * \param dest_size + * The size of the destination buffer in bytes. + * + * \param completion_callback + * A user defined callback function that is called when the operation + * completes or an error occurs. + * + * \param completion_arg + * A user defined argument that is passed to the callback function + * when the operation completes or an error occurs. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * \retval ALT_E_BAD_BLK The device block is marked defective and hence the + * operation was ignored. + * \retval ALT_E_BUF_OVF The destination buffer does not contain enough space + * for the operation. + * + * \internal + * See: + * * CV Device Handbook + * - Data DMA + * - Multitransaction DMA Command + * - Interrupt and DMA Enabling + * * Pipeline Read-Ahead and Write-Ahead Operations + * \endinternal + */ +ALT_STATUS_CODE alt_nand_flash_page_dma_read(const uint32_t page_addr, + const uint32_t num_pages, + void *dest, + const uint32_t dest_size, + alt_nand_callback_t completion_callback, + void *completion_arg); +/*! + * Write one or more pages to the flash device using the NAND flash controller's + * internal DMA. The write operation proceeds asynchronously with a user callback + * notification upon completion or error. + * + * Writes \e num_pages to the flash device beginning at \e page_addr. Whole pages + * are written to flash memory. The block(s) containing the pages must have been + * previously erased. + * + * \param page_addr + * The beginning page address to write. + * + * \param num_pages + * The number of pages to write. + * + * \param src + * The address of the source buffer containing th data to be written + * to the flash device. + * + * \param src_size + * The size of the source buffer in bytes. + * + * \param completion_callback + * A user defined callback function that is called when the operation + * completes or an error occurs. + * + * \param completion_arg + * A user defined argument that is passed to the callback function + * when the operation completes or an error occurs. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * \retval ALT_E_BAD_BLK The device block is marked defective and hence the + * operation was ignored. + * \retval ALT_E_BUF_OVF The destination buffer does not contain enough space + * for the operation. + * + * \internal + * See: + * * CV Device Handbook + * - Data DMA + * - Multitransaction DMA Command + * - Interrupt and DMA Enabling + * * Pipeline Read-Ahead and Write-Ahead Operations + * \endinternal + */ +ALT_STATUS_CODE alt_nand_flash_page_dma_write(const uint32_t page_addr, + const uint32_t num_pages, + const void *src, + const uint32_t src_size, + alt_nand_callback_t completion_callback, + void *completion_arg); + +/*! + * This type definition enumerates the possible ECC correction code bit encodings + * and their applicability to sector size. + */ +typedef enum ALT_NAND_ECC_CORRECTION_e +{ + ALT_NAND_ECC_4_BIT_CORRECTION = 4, /*!< Performs 4 bit correction over a 512 byte sector */ + ALT_NAND_ECC_8_BIT_CORRECTION = 8, /*!< Performs 8 bit correction over a 512 byte sector */ + ALT_NAND_ECC_16_BIT_CORRECTION = 16, /*!< Performs 16 bit correction over a 512 byte sector */ + ALT_NAND_ECC_24_BIT_CORRECTION = 24 /*!< Performs 24 bit correction over a 1024 byte sector */ +} ALT_NAND_ECC_CORRECTION_t; + +/*! + * Enable hardware ECC protection for the flash device. + * + * \param ecc_correction + * The desired ECC correction code bit encoding. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + * \retval ALT_E_INV_OPTION The specified ECC correction value is not + * appropriate for the device page size and + * spare area available. + * + * \internal + * See: Cadence DB - Section 11.4 ECC Enabling + * \endinternal + */ +ALT_STATUS_CODE alt_nand_flash_ecc_enable(const ALT_NAND_ECC_CORRECTION_t ecc_correction); + +/*! + * Disable hardware ECC protection for the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + * + * \internal + * See: Cadence DB - Section 11.4 ECC Enabling + * \endinternal + */ +ALT_STATUS_CODE alt_nand_flash_ecc_disable(void); + + +/*! + * This type defines a structure for accessing the ECC error correction + * information for the last transaction completed by the NAND flash controller. + */ +typedef struct ALT_NAND_FLASH_ECC_STATUS_s +{ + uint32_t corrected_errors[4]; /*!< Maximum of number of errors corrected + * per sector in a bank. This field is + * not valid for uncorrectable errors. A + * value of zero indicates that no ECC + * error occurred in last completed + * transaction. Index \e n corressponds + * to bank \e n. + */ + bool uncorrected_error[4]; /*!< \b true if an uncorrectable error + * occurred while reading pages for last + * transaction in a bank. Uncorrectable + * errors also generate + * ALT_NAND_INT_STATUS_ECC_UNCOR_ERR + * interrupt status conditions. Index + * \e n corressponds to bank \e n. + */ +} ALT_NAND_FLASH_ECC_STATUS_t; + +/*! + * Gets the ECC error correction information for the last transaction completed by + * the NAND flash controller. + * + * \param ecc_status + * [out] Pointer to a \ref ALT_NAND_FLASH_ECC_STATUS_t structure + * containing the ECC status for the last completed transaction. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + * + * \internal + * nandregs.ecc.ECCCorInfo_b01 + * nandregs.ecc.ECCCorInfo_b23 + * \endinternal + */ +ALT_STATUS_CODE alt_nand_flash_ecc_status_get(ALT_NAND_FLASH_ECC_STATUS_t *ecc_status); + +/*! + * This type definition enumerates the interrupt status conditions for the NAND + * flash controller. + * + * The enumerations serve as masks for the NAND flash controller events that can + * be set when the designated conditions occur and the corresponding event is + * enabled. When any of these event source conditions are true, the \b + * ALT_INT_INTERRUPT_NAND_IRQ interrupt output is asserted high. + * + * Interrupt sources are cleared when software calls alt_nand_int_clear(). The + * interrupt sources are individually maskable using alt_nand_int_disable() and + * alt_nand_int_enable(). + * + * The NAND flash controller has a single active high interrupt output + * (nand_int). This interrupt is the logical "OR" of all of the interrupt bits + * within the flash controller that are enabled and set. There is also a global + * interrupt enable in the flash controller block that must be set to enable + * interrupts. Each interrupt source within the IP has an active high enable bit + * and a sticky bit. The sticky bit is an active high "write one to clear" status + * bit. There are four sets of identical interrupt bits, one for each of the four + * banks. The following conditions can trigger an interrupt: + * - Page transfer + * - Pipeline command sequence violation + * - Rest/initialization complete + * - Ready/Busy pin low to high transition + * - Unsupported command + * - Locked block command failure + * - Pipeline command or copyback command complete + * - Erase complete + * - Program complete + * - Load complete + * - Erase fail + * - Program fail + * - Timeout + * - DMA command complete + * - Uncorrectable ECC error + */ +typedef enum ALT_NAND_INT_STATUS_e +{ + ALT_NAND_INT_STATUS_PAGE_XFER_INC = (1 << 15), + /*!< For every page of data + * transfer to or from the + * device, this status will be + * set. + */ + ALT_NAND_INT_STATUS_PIPE_CMD_ERR = (1 << 14), + /*!< A pipeline command sequence + * has been violated. This + * occurs when MAP01 page + * read/write address does not + * match the corresponding + * expected address from the + * pipeline commands issued + * earlier. + */ + ALT_NAND_INT_STATUS_RST_COMP = (1 << 13), + /*!< The NAND flash controller + * has finished reset and + * initialization process. + */ + ALT_NAND_INT_STATUS_INT_ACT = (1 << 12), + /*!< R/B pin of device + * transitioned from low to + * high. + */ + ALT_NAND_INT_STATUS_UNSUP_CMD = (1 << 11), + /*!< An unsupported command was + * received. This interrupt is + * set when an invalid command + * is received, or when a + * command sequence is broken. + */ + ALT_NAND_INT_STATUS_LOCKED_BLK = (1 << 10), + /*!< The address to program or + * erase operation is to a + * locked block and the + * operation failed due to this + * reason. + */ + ALT_NAND_INT_STATUS_PIPE_CPYBCK_CMD_COMP = (1 << 9), + /*!< A pipeline command or a + * copyback bank command has + * completed on this particular + * bank. + */ + ALT_NAND_INT_STATUS_ERASE_COMP = (1 << 8), + /*!< Device erase operation + * complete. + */ + ALT_NAND_INT_STATUS_PROGRAM_COMP = (1 << 7), + /*!< Device finished the last + * issued program command. + */ + ALT_NAND_INT_STATUS_LOAD_COMP = (1 << 6), + /*!< Device finished the last + * issued load command. + */ + ALT_NAND_INT_STATUS_ERASE_FAIL = (1 << 5), + /*!< Erase failure occurred in the + * device on issuance of a erase + * command. err_block_addr and + * err_page_addr contain the + * block address and page + * address that failed erase + * operation. + */ + ALT_NAND_INT_STATUS_PROGRAM_FAIL = (1 << 4), + /*!< Program failure occurred in + * the device on issuance of a + * program + * command. err_block_addr and + * err_page_addr contain the + * block address and page + * address that failed program + * operation. + */ + ALT_NAND_INT_STATUS_TIME_OUT = (1 << 3), + /*!< Watchdog timer has triggered + * in the controller due to one + * of the reasons like device + * not responding or controller + * state machine did not get + * back to idle. + */ + ALT_NAND_INT_STATUS_DMA_CMD_COMP = (1 << 2), + /*!< A data DMA command has + * completed on this bank. + */ + ALT_NAND_INT_STATUS_ECC_UNCOR_ERR = (1 << 0) + /*!< ECC logic detected + * uncorrectable error while + * reading data from flash + * device. + */ +} ALT_NAND_INT_STATUS_t; + +/*! + * Returns the NAND flash controller interrupt status register value. + * + * This function returns the current value of the NAND flash controller interrupt + * status register value which reflects the current NAND flash controller status + * conditions. + * + * \returns The current value of the NAND flash controller interrupt status + * register value which reflects the current NAND flash controller + * status conditions as defined by the \ref ALT_NAND_INT_STATUS_t + * mask. If the corresponding bit is set then the condition is + * asserted. + */ +uint32_t alt_nand_int_status_get(void); + +/*! + * Clears the specified NAND flash controller interrupt status conditions + * identified in the mask. + * + * This function clears one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_NAND_IRQ interrupt signal state. + * + * \param mask + * Specifies the QSPI interrupt status conditions to clear. \e mask + * is a mask of logically OR'ed \ref ALT_NAND_INT_STATUS_t values + * that designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_nand_int_clear(const uint32_t mask); + +/*! + * Disable the specified NAND flash controller interrupt status conditions + * identified in the mask. + * + * This function disables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_NAND_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b ALT_INT_INTERRUPT_NAND_IRQ + * interrupt signal state. The function alt_nand_int_enable() is used to enable + * status source conditions. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_NAND_INT_STATUS_t values that designate the status conditions + * to disable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_nand_int_disable(const uint32_t mask); + +/*! + * Enable the specified NAND flash controller interrupt status conditions + * identified in the mask. + * + * This function enables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_NAND_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b ALT_INT_INTERRUPT_NAND_IRQ + * interrupt signal state. The function alt_nand_int_disable() is used to disable + * status source conditions. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_NAND_INT_STATUS_t values that designate the status conditions + * to enable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_nand_int_enable(const uint32_t mask); + +/*! + * Returns the number of planes in the flash memory device. + * + * Returns the number of planes as read from the device during discovery and + * parameter configuration. For 512 byte devices this information typically has to + * be manually programmed by software. + * + * \returns The number of planes contained in the device. + * + * \internal + * nandregs.config.number_of_planes + * \endinternal + */ +uint32_t alt_nand_num_planes_get(void); + +/*! + * Returns the number of blocks in the flash memory device. + * + * Returns the number of blocks as read from the device during discovery and + * parameter configuration. For 512 byte devices this information typically has to + * be manually programmed by software. + * + * \returns The number of blocks contained in the device. + * + * \internal + * ??? + * \endinternal + */ +uint32_t alt_nand_num_blocks_get(void); + +/*! + * Returnes the number of pages per device block. + * + * Returns the number of pages per block as read from the device during discovery + * and parameter configuration. For 512 byte devices this information typically + * has to be manually programmed by software. + * + * \returns The number of pages per device block. + * + * \internal + * nandregs.config.pages_per_block + * \endinternal + */ +uint32_t alt_nand_num_pages_per_block_get(void); + +/*! + * Returns the size of a page sector in bytes. + * + * Returns the size of a page sector in bytes as read from the device during + * discovery and parameter configuration. For 512 byte devices this information + * typically has to be manually programmed by software. + * + * \returns Returns the size of a page sector in bytes. + * + * \internal + * nandregs.config.device_main_area_size + * \endinternal + */ +uint32_t alt_nand_sector_size_get(void); + +/*! + * Returns the size of a page spare area in bytes. + * + * Returns the size of a page spare area in bytes as read from the device during + * discovery and parameter configuration. For 512 byte devices this information + * typically has to be manually programmed by software. + * + * \returns Returns the size of a page spare area in bytes. + * + * \internal + * nandregs.config.device_spare_area_size + * \endinternal + */ +uint32_t alt_nand_spare_size_get(void); + +/*! + * Returns \b true if the specified device block is bad otherwise returns \b + * false. + * + * Returns \b true if the specified device block is marked defective + * (i.e. bad) and should not be used. Otherwise the device block is assumed usable + * and \b true is returned. + * + * \param block_addr + * The block address to check. + * + * \returns \b true if the specified device block is bad otherwise returns + * \b false. + * + * \internal + * Uses the bad block table constructed by alt_nand_flash_init(). + * \endinternal + */ +bool alt_nand_block_is_bad(const uint32_t block_addr); + +/*! + * The ONFI Factory Defect Mapping defined value used by manufacturers to mark a + * block as defective. A manufacturer marks defective blocks by setting at least + * one byte in the spare area of the first or last page of the defective block to + * a value of 0. + */ +#define ALT_NAND_BAD_BLOCK_MARKER 0 + +/*! + * This type defines the data structure used to hold the bad block table. + * + * The table is an array composed of uint32_t elements. Each array element + * contains the bad block status for 32 consecutive blocks on the flash + * device. The array is of length ceil( alt_nand_num_blocks_get() / 32 ) + * elements. + * + * Each bit holds the defect status of a block in the device. The LSB bit position + * of the first element of the array corressponds to the defect status of Block + * 0. The MSB of the first element of the array corressponds to the defect status + * of Block 31. The second element of the array contains the defect status of the + * next 32 consecutive blocks of the device (Blocks 32-63) and so on. + * + * The following code fragment illustrates how the bad block table is used to + * determine whether a particular block is bad or not: + * + * \code + * #define ALT_NAND_GOOD_BLOCK_FLAG 0 + * #define ALT_NAND_BAD_BLOCK_FLAG 1 + * + * block_is_bad = false; + * block_table_index = block_number / 32; + * block_bit_position = block_number % 32; + * if ((( bad_block_table[block_table_index] >> block_bit_position) & 0x1) == ALT_NAND_BAD_BLOCK_FLAG) + * block_is_bad = true; + * \endcode + */ +typedef uint32_t * alt_nand_bad_block_table_t; + +/*! + * Get a copy of the bad block table for the device. + * + * Returns a copy of the bad block table for the device in a user specified + * buffer. The size and organization of the bad block table are described in \ref + * alt_nand_bad_block_table_t. + * + * \param bad_block_table + * [out] Pointer to a buffer of type alt_nand_bad_block_table_t to + * return a copy of the bad block table in. + * + * \param bad_block_table_len + * The length of the \e bad_block_table parameter in number of + * elements. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + * \retval ALT_E_BAD_ARG The \e bad_block_table_len specifies a bad_block_table + * length that is not large enough to hold a copy of + * the bad block table for the device. + * + */ +ALT_STATUS_CODE alt_nand_bad_block_table_get(alt_nand_bad_block_table_t bad_block_table, + const uint32_t bad_block_table_len); + + + + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_NAND_FLASH_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_nand_private.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_nand_private.h new file mode 100644 index 000000000..6c4f2135c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_nand_private.h @@ -0,0 +1,190 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/*! \file + * Altera - NAND Flash Controller Module + */ + +#ifndef __ALT_NAND_PRIVATE_H__ +#define __ALT_NAND_PRIVATE_H__ + + +/* + * ***************************************** + * Struct for NAND Manager IO block + * which consists of cfg, param, status, ecc and dma register blocks + * located at address: ALT_NAND_CFG_ADDR + * ***************************************** + */ +typedef struct { + ALT_NAND_CFG_raw_t* cfg; // nand configuration block + ALT_NAND_PARAM_raw_t* param; // nand parameter block + ALT_NAND_STAT_raw_t* stat; // nand status block + ALT_NAND_ECC_raw_t* ecc; // nand ecc block + ALT_NAND_DMA_raw_t* dma; // nand dma block + volatile uint32_t * const ctrl_addr; // indirect access address control + volatile uint32_t * const data_addr; // fifo access address control +} ALT_NAND_MGR_t; + +// +// flash memory characterization +// +typedef struct +{ + uint32_t manufacturer_id; + uint32_t device_id; + uint32_t device_param_0; + uint32_t device_param_1; + uint32_t device_param_2; + uint32_t page_size; + uint32_t spare_size; + uint32_t revision; + uint32_t onfi_device_features; + uint32_t onfi_optional_commands; + uint32_t onfi_timing_mode; + uint32_t onfi_pgm_cache_timing_mode; + uint32_t onfi_compliant; + uint32_t onfi_device_no_of_luns; + uint32_t onfi_device_no_of_blocks_per_lun; + uint32_t features; + + uint32_t number_of_planes; + uint32_t pages_per_block; + uint32_t device_width; + uint32_t device_main_area_size; + uint32_t device_spare_area_size; + uint32_t block_size; + uint32_t spare_area_skip_bytes; + uint32_t first_block_of_next_plane; + uint32_t page_size_32; + uint32_t page_shift; + uint32_t block_shift; + uint32_t dma_burst_length; + uint32_t ecc_correct; +} FLASH_CHARACTERIZATION_t; + + +typedef uint32_t (*nand_interrupt_handler_t)(uint32_t interrup_status_register, uint32_t interrup_status_mask ); + + +/* + * Some default values. + */ +#define ALT_HHP_NAND_SECTOR_SIZE (512) +#define ALT_HHP_NAND_PAGE_SIZE (2048) +#define ALT_HHP_NAND_PAGE_SHIFT (11) +#define ALT_HHP_NAND_SPARE_SIZE (128) /* Spare bytes per page. */ +#define ALT_HHP_NAND_PAGES_PER_BLOCK (64) /* 128 pages per block (512KB) */ +#define ALT_HHP_NAND_BLOCK_SIZE (ALT_HHP_NAND_PAGE_SIZE *ALT_HHP_NAND_PAGES_PER_BLOCK) +#define ALT_HHP_NAND_ECC_CORRECT (8) /* 8 bit ECC. */ +#define ALT_HHP_NAND_SPARE_SKIP (2) /* Skip the first 2 bytes of the spare space. */ +#define ALT_HHP_NAND_BLOCK_SHIFT (6) /* from page boundary */ +#define ALT_HHP_NAND_MANUFACTURER_ID (0x1) +#define ALT_HHP_NAND_DEVICE_ID (0xd3) +#define ALT_HHP_NAND_REVISION (5) + +#define ALT_HHP_NAND_NUMBER_OF_PLANES (2) +#define ALT_HHP_NAND_DEVICE_WIDTH (0) +#define ALT_HHP_NAND_FIRST_BLOCK_OF_NEXT_PLANE (2048) + +#define ALT_HHP_NAND_NUM_OF_LUNS (2) +#define ALT_HHP_NAND_NUM_OF_BLOCK_PER_LUNS (4096) +#define ALT_HHP_NAND_NUM_OF_BLOCK_TOTAL (ALT_HHP_NAND_NUM_OF_LUNS * ALT_HHP_NAND_NUM_OF_BLOCK_PER_LUNS) + +// +// Constants from 8.1. Address Mapping +// +// Table 8.2 +#define ALT_HHP_NAND_MODE_00 (0x00000000) +#define ALT_HHP_NAND_MODE_01 (0x04000000) +#define ALT_HHP_NAND_MODE_10 (0x08000000) +#define ALT_HHP_NAND_MODE_11 (0x0C000000) + +#define ALT_HHP_NAND_ADDR_MAP_CMD_MAP_LSB_INDEX (26) +#define ALT_HHP_NAND_ADDR_MAP_BANK_SEL_LSB_INDEX (24) +#define ALT_HHP_NAND_ADDR_MAP_MEM_ADDR_LSB_INDEX (0) + +#define ALT_HHP_NAND_10_OP_DEFAULT_AREA (0x0042) +#define ALT_HHP_NAND_10_OP_ERASE_BLOCK (0x0001) +#define ALT_HHP_NAND_10_OP_LOAD_PAGE (0x0060) +#define ALT_HHP_NAND_10_OP_DEST_ADDR (0x0061) +#define ALT_HHP_NAND_10_OP_WRITE_PAGE (0x0062) + +#define ALT_HHP_NAND_10_OP_READ_PIPE (0x2000) +#define ALT_HHP_NAND_10_OP_WRITE_PIPE (0x2100) + +#define ALT_HHP_UINT32_MASK ((uint32_t) -1) + + +#define ALT_NAND_BOOTSTRAP_INHIBIT_INIT_ENABLE (1) +#define ALT_NAND_BOOTSTRAP_INHIBIT_INIT_DISABLE (0) +#define ALT_NAND_BOOTSTRAP_INHIBIT_B0P0_LOAD_ENABLE (1) +#define ALT_NAND_BOOTSTRAP_INHIBIT_B0P0_LOAD_DISABLE (0) +#define ALT_NAND_BOOTSTRAP_512B_DEVICE_ENABLE (1) +#define ALT_NAND_BOOTSTRAP_512B_DEVICE_DISABLE (0) +#define ALT_NAND_BOOTSTRAP_TWO_ROW_ADDR_CYCLES_EABLE (1) +#define ALT_NAND_BOOTSTRAP_TWO_ROW_ADDR_CYCLES_DISABLE (0) + +#define ALT_NAND_FLASH_MEM_BANK_0 (0) +#define ALT_NAND_FLASH_MEM_BANK_1 (1) +#define ALT_NAND_FLASH_MEM_BANK_2 (2) +#define ALT_NAND_FLASH_MEM_BANK_3 (3) + +uint32_t alt_nand_poll_for_interrupt_status_register(uint32_t , uint32_t ); +uint32_t ffs32(uint32_t); +uint32_t alt_nand_compose_map10_cmd_addr(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr); +int32_t alt_nand_full_page_read_with_map10(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t *buffer); +void alt_nand_write_indirect(const uint32_t address, const uint32_t value); +uint32_t alt_nand_read_indirect(const uint32_t address); +int32_t alt_nand_full_page_write_with_map10(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t *buffer); +void alt_nand_full_page_read_with_map10_post_read_with_map01(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t *buffer); +void alt_nand_full_page_write_with_map10_post_write_with_map01(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t *buffer); + +void alt_nand_set_sysmgr_bootstrap_value( uint32_t bootstrp_inhibit_init, + uint32_t bootstrp_inhibit_b0p0_load, + uint32_t bootstrp_512b_device, + uint32_t bootstrp_two_row_addr_cycles); +void alt_nand_reset_bank(uint32_t bank); +uint32_t alt_nand_bank_get(void); + +void alt_nand_dma_write_cmd_structure( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t page_count, uint64_t mem_addr, int32_t is_read_op, const uint32_t burst_len ); + +void alt_nand_dma_set_enabled( int32_t is_enabled ); +int32_t alt_nand_dma_page_read( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t mem_addr ); +int32_t alt_nand_dma_page_write( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t mem_addr ); +ALT_STATUS_CODE alt_nand_flash_init_manual(void *); +void alt_nand_erase_block_callback(ALT_STATUS_CODE, void *); +void alt_nand_dma_page_callback(ALT_STATUS_CODE, void *); +void nand_print_device(void); +uint32_t nand_read_register(uint32_t offset); +void alt_nand_rb_pin_mode_set(uint32_t); +void alt_nand_rb_pin_mode_clear(uint32_t); + +#endif /* __ALT_NAND_PRIVATE_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_qspi.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_qspi.h new file mode 100644 index 000000000..badc27af9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_qspi.h @@ -0,0 +1,1535 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/****************************************************************************** +* +* !!!! Customer Be Aware, Exception!!! +* +* 1. Qspi Direct Access Mode is not working! +* +* This is because the qspi flash memory installed on our DevKit board, Micro +* part N25Q00xx, 8 Gb, is not completely compatible with our embedded Synopsis +* QSPI controller IP. Therefore there is no viable direct access code offered +* in the lib. All the memory rea/write functionality is offered with indirect +* access only. +* +* Should you install a different flash memory part in your custom board, and +* wondering wether direct access mode works, please contact with us. +* +******************************************************************************/ + +/*! \file + * Altera - QSPI Flash Controller Module + */ + +#ifndef __ALT_QSPI_H__ +#define __ALT_QSPI_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI QSPI Flash Controller Module + * + * This module defines a low level driver API for the hardware processor system + * (HPS) quad serial peripheral interface (QSPI) flash controller for access to + * serial NOR flash devices. The quad SPI flash controller supports standard SPI + * flash devices as well as high-performance dual and quad SPI flash + * devices. + * + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_CSR General Control and Status Functions + * + * The declarations and functions in this group provide general purpose control + * and status functions for the QSPI Flash Controller. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Initialize the QSPI flash controller for use. + * + * \internal + * Implementation Notes: + * * The QSPI Controller has been designed to wake up in a state that is + * suitable for performing basic reads and writes using the direct access + * controller. + * * Bring out of reset + * * QSPI reference clock validation + * * See Programmer's Guide, Configuring the QSPI Controller for use after + * reset, in QSPI_FLASH_CTRL for full initialization details. + * \endinternal + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_init(void); + +/******************************************************************************/ +/*! + * Uninitialize the QSPI flash controller. + * + * Uninitialize the QSPI flash controller by cancelling any indirect transfers + * in progress and putting the QSPI controller into reset. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_uninit(void); + +/******************************************************************************/ +/*! + * Disable the QSPI Controller. + * + * Disable the QSPI once the current transfer of the data word (FF_W) is + * complete. All output enables are inactive and all pins are set to input + * mode. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_disable(void); + +/******************************************************************************/ +/*! + * Enable the QSPI Controller. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_enable(void); + +/******************************************************************************/ +/*! + * This type definition enumerates the interrupt status conditions for the QSPI + * controller. + * + * The enumerations serve as masks for the QSPI controller events that can be + * set when the designated conditions occur and the corresponding event is + * enabled. When any of these event source conditions are true, the \b + * ALT_INT_INTERRUPT_QSPI_IRQ interrupt output is asserted high. + * + * Interrupt sources are cleared when software calls alt_qspi_int_clear(). The + * interrupt sources are individually maskable using alt_qspi_int_disable() and + * alt_qspi_int_enable(). + */ +typedef enum ALT_QSPI_INT_STATUS_e +{ + /*! + * Mode fail M - indicates the voltage on pin n_ss_in is inconsistent with + * the SPI mode. Set = 1 if n_ss_in is low in master mode (multi-master + * contention). These conditions will clear the spi_enable bit and disable + * the SPI. + * * 0 = no mode fault has been detected. + * * 1 = a mode fault has occurred. + */ + ALT_QSPI_INT_STATUS_MODE_FAIL = (0x1 << 0), + + /*! + * Underflow Detected. + * * 0 = no underflow has been detected. + * * 1 = underflow is detected and an attempt to transfer data is made + * when the small TX FIFO is empty. This may occur when AHB write + * data is being supplied too slowly to keep up with the requested + * write operation. + */ + ALT_QSPI_INT_STATUS_UFL = (0x1 << 1), + + /*! + * Controller has completed last triggered indirect operation. + */ + ALT_QSPI_INT_STATUS_IDAC_OP_COMPLETE = (0x1 << 2), + + /*! + * Indirect operation was requested but could not be accepted. Two indirect + * operations already in storage. + */ + ALT_QSPI_INT_STATUS_IDAC_OP_REJECT = (0x1 << 3), + + /*! + * Write to protected area was attempted and rejected. + */ + ALT_QSPI_INT_STATUS_WR_PROT_VIOL = (0x1 << 4), + + /*! + * Illegal AHB Access Detected. AHB write wrapping bursts and the use of + * SPLIT/RETRY accesses will cause this interrupt to trigger. + */ + ALT_QSPI_INT_STATUS_ILL_AHB_ACCESS = (0x1 << 5), + + /*! + * Indirect Transfer Watermark Level Breached. + */ + ALT_QSPI_INT_STATUS_IDAC_WTRMK_TRIG = (0x1 << 6), + + /*! + * Receive Overflow. This should only occur in Legacy SPI mode. + * + * Set if an attempt is made to push the RX FIFO when it is full. This bit + * is reset only by a system reset and cleared only when this register is + * read. If a new push to the RX FIFO occurs coincident with a register read + * this flag will remain set. + * * 0 = no overflow has been detected. + * * 1 = an overflow has occurred. + */ + ALT_QSPI_INT_STATUS_RX_OVF = (0x1 << 7), + + /*! + * Small TX FIFO not full (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO has >= THRESHOLD entries. + * * 1 = FIFO has < THRESHOLD entries. + */ + ALT_QSPI_INT_STATUS_TX_FIFO_NOT_FULL = (0x1 << 8), + + /*! + * Small TX FIFO full (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO is not full. + * * 1 = FIFO is full. + */ + ALT_QSPI_INT_STATUS_TX_FIFO_FULL = (0x1 << 9), + + /*! + * Small RX FIFO not empty (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO has < RX THRESHOLD entries. + * * 1 = FIFO has >= THRESHOLD entries. + */ + ALT_QSPI_INT_STATUS_RX_FIFO_NOT_EMPTY = (0x1 << 10), + + /*! + * Small RX FIFO full (current FIFO status). Can be ignored in non-SPI + * legacy mode. + * * 0 = FIFO is not full. + * * 1 = FIFO is full. + */ + ALT_QSPI_INT_STATUS_RX_FIFO_FULL = (0x1 << 11), + + /*! + * Indirect Read partition of SRAM is full and unable to immediately + * complete indirect operation. + */ + ALT_QSPI_INT_STATUS_IDAC_RD_FULL = (0x1 << 12) + +} ALT_QSPI_INT_STATUS_t; + +/******************************************************************************/ +/*! + * Returns the QSPI controller interrupt status register value. + * + * This function returns the current value of the QSPI controller interrupt + * status register value which reflects the current QSPI controller status + * conditions. + * + * \returns The current value of the QSPI controller interrupt status + * register value which reflects the current QSPI controller status + * conditions as defined by the \ref ALT_QSPI_INT_STATUS_t mask. + * If the corresponding bit is set then the condition is asserted. + */ +uint32_t alt_qspi_int_status_get(void); + +/******************************************************************************/ +/*! + * Clears the specified QSPI controller interrupt status conditions identified + * in the mask. + * + * This function clears one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. + * + * \param mask + * Specifies the QSPI interrupt status conditions to clear. \e + * mask is a mask of logically OR'ed \ref ALT_QSPI_INT_STATUS_t + * values that designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_int_clear(const uint32_t mask); + +/******************************************************************************/ +/*! + * Disable the specified QSPI controller interrupt status conditions identified + * in the mask. + * + * This function disables one or more of the status conditions as contributors + * to the \b ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b + * ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. The function + * alt_qspi_int_enable() is used to enable status source conditions. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed + * \ref ALT_QSPI_INT_STATUS_t values that designate the status + * conditions to disable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_int_disable(const uint32_t mask); + +/******************************************************************************/ +/*! + * Enable the specified QSPI controller interrupt status conditions identified + * in the mask. + * + * This function enables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b + * ALT_INT_INTERRUPT_QSPI_IRQ interrupt signal state. The function + * alt_qspi_int_disable() is used to disable status source conditions. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed + * \ref ALT_QSPI_INT_STATUS_t values that designate the status + * conditions to enable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_int_enable(const uint32_t mask); + +/******************************************************************************/ +/*! + * Returns true the serial interface and QSPI pipeline is IDLE. + * + * \returns Returns true the serial interface and QSPI pipeline is IDLE. + */ +bool alt_qspi_is_idle(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_GP_BLKIO General Purpose Block I/O + * + * The functions in this group provide general purpose block read and + * write flash functions. + * + * \internal + * These functions use Indirect Read/Write transfers to read and write block + * data to the flash device. An outline of the operational flow for these + * operations can be found in: + * //depot/soc/hhp_sw/baremetal_fw/drivers/qspi/qspi.c + * + * The general flow for an indirect block read is to call + * qspi_configure_mode_indirect_read_start() to initiate the read transfer from + * the flash device into the SRAM buffer and follow with a call to either + * qpsi_write_sram_fifo_poll() or qspi_read_sram_fifo_irq() to copy the data + * from SRAM into the user's buffer. + * + * The general flow for an indirect block write is to call + * qspi_configure_mode_indirect_write_start() to initiate the write transfer + * from the SRAM buffer to the flash device and follow with a call to either + * qpsi_write_sram_fifo_poll() or qspi_write_sram_fifo_irq() to fill the SRAM + * buffer with the user's data as space becomes available. + * \endinternal + * + * @{ + */ + +/******************************************************************************/ +/*! + * Read a block of data from the specified flash address. + * + * Reads a block of \e n data bytes from the flash \e src address into the user + * supplied \e dest buffer. The memory address, flash address, and size must be + * word aligned. + * + * \param dest + * The address of a caller supplied destination buffer large enough + * to contain the requested block of flash data. + * + * \param src + * The flash device address to start reading data from. + * + * \param size + * The requested number of data bytes to read from the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_read(void * dest, uint32_t src, size_t size); + +/******************************************************************************/ +/*! + * Write a block of data to the specified flash address. + * + * Writes a block of \e n data bytes to the flash \e dest address from the + * designated \e src buffer. The applicable destination flash address range + * should have been erased prior to calling this function. The flash address, + * memory address, and size must be word aligned. + * + * \param dest + * The destination flash address to begin writing data to. + * + * \param src + * The source address to start writing data from. + * + * \param size + * The requested number of data bytes to write to the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_write(uint32_t dest, const void * src, size_t size); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_DEV_CFG Flash Device Configuration + * + * The declarations and functions in this group are used to configure the QSPI + * controller interface to external flash devices. + * + * The following steps describe how to initialize and configure the + * QSPI controller to operate with a flash device. + * + * * Wait until any pending QSPI operations have completed. + * * Disable the QSPI controller using alt_qspi_disable(). + * * Configure the device for optimal read transaction performance using + * alt_qspi_device_read_config_set(). + * * Configure the device for optimal write transaction performance using + * alt_qspi_device_write_config_set(). + * * Enable (alt_qspi_mode_bit_disable()) or disable + * (alt_qspi_mode_bit_disable()) the mode bits per the device + * requirements. If mode bits are enabled, then configure the mode + * bit values using alt_qspi_mode_bit_config_set(). + * * Configure the device size and write protection information using + * alt_qspi_device_size_config_set(). + * * Configure the QSPI device delay and timing settings using + * alt_qspi_device_write_config_set(). + * * Configure the baud divisor setting to define the required clock frequency + * to the device using alt_qspi_baud_rate_div_set(). + * * Enable the QSPI controller using alt_qspi_enable(). + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type enumerates the operational modes the QSPI controller can be + * configured for. It may apply to instruction, address, and/or data width + * interactions between the QSPI controller and the flash device. + */ +typedef enum ALT_QSPI_MODE_e +{ + ALT_QSPI_MODE_SINGLE = 0, /*!< Use Standard Single SPI (SIO-SPI) mode (bits + * always transferred into the device on DQ0 + * only). Supported by all SPI flash devices. + */ + ALT_QSPI_MODE_DUAL = 1, /*!< Use Dual SPI (DIO-SPI) SPI mode where bits are + * transferred on DQ0 and DQ1. + */ + ALT_QSPI_MODE_QUAD = 2 /*!< Use Dual SPI (QIO-SPI) SPI mode where bits are + * transferred on DQ0, DQ1, DQ3, and DQ3. + */ +} ALT_QSPI_MODE_t; + +/******************************************************************************/ +/*! + * This type enumerates the mode configurations available for driving the + * ss_n[3:0] device chip selects. The chip selects may be controlled as either + * in a '1 of 4' or '4 to 16 decode' mode. + */ +typedef enum ALT_QSPI_CS_MODE_e +{ + ALT_QSPI_CS_MODE_SINGLE_SELECT = 0, /*!< Select 1 of 4 chip select ss_n[3:0] + */ + ALT_QSPI_CS_MODE_DECODE = 1 /*!< Select external 4 to 16 decode of + * ss_n[3:0]. + */ +} ALT_QSPI_CS_MODE_t; + +/******************************************************************************/ +/*! + * This type enumerates the QSPI controller master baud rate divisor selections. + */ +typedef enum ALT_QSPI_BAUD_DIV_e +{ + ALT_QSPI_BAUD_DIV_2 = 0x0, /*!< Divide by 2 */ + ALT_QSPI_BAUD_DIV_4 = 0x1, /*!< Divide by 4 */ + ALT_QSPI_BAUD_DIV_6 = 0x2, /*!< Divide by 6 */ + ALT_QSPI_BAUD_DIV_8 = 0x3, /*!< Divide by 8 */ + ALT_QSPI_BAUD_DIV_10 = 0x4, /*!< Divide by 10 */ + ALT_QSPI_BAUD_DIV_12 = 0x5, /*!< Divide by 12 */ + ALT_QSPI_BAUD_DIV_14 = 0x6, /*!< Divide by 14 */ + ALT_QSPI_BAUD_DIV_16 = 0x7, /*!< Divide by 16 */ + ALT_QSPI_BAUD_DIV_18 = 0x8, /*!< Divide by 18 */ + ALT_QSPI_BAUD_DIV_20 = 0x9, /*!< Divide by 20 */ + ALT_QSPI_BAUD_DIV_22 = 0xA, /*!< Divide by 22 */ + ALT_QSPI_BAUD_DIV_24 = 0xB, /*!< Divide by 24 */ + ALT_QSPI_BAUD_DIV_26 = 0xC, /*!< Divide by 26 */ + ALT_QSPI_BAUD_DIV_28 = 0xD, /*!< Divide by 28 */ + ALT_QSPI_BAUD_DIV_30 = 0xE, /*!< Divide by 30 */ + ALT_QSPI_BAUD_DIV_32 = 0xF /*!< Divide by 32 */ +} ALT_QSPI_BAUD_DIV_t; + +/******************************************************************************/ +/*! + * Device Size Configuration + * + * This type defines the structure used to specify flash device size and write + * protect regions. + */ +typedef struct ALT_QSPI_DEV_SIZE_CONFIG_s +{ + uint32_t block_size; /*!< Number of bytes per device block. The + * number is specified as a power of 2. + * That is 0 = 1 byte, 1 = 2 bytes, ... + * 16 = 65535 bytes, etc. + */ + uint32_t page_size; /*!< Number of bytes per device page. This + * is required by the controller for + * performing flash writes up to and + * across page boundaries. + */ + uint32_t addr_size; /*!< Number of bytes used for the flash + * address. The value is \e n + 1 + * based. That is 0 = 1 byte, 1 = 2 bytes, + * 2 = 3 bytes, 3 = 4 bytes. + */ + uint32_t lower_wrprot_block; /*!< The block number that defines the lower + * block in the range of blocks that is + * protected from writing. This field + * is ignored it write protection is + * disabled. + */ + uint32_t upper_wrprot_block; /*!< The block number that defines the upper + * block in the range of blocks that is + * protected from writing. This field + * is ignored it write protection is + * disabled. + */ + bool wrprot_enable; /*!< The write region enable value. A value + * of \b true enables write protection + * on the region specified by the + * \e lower_wrprot_block and + * \e upper_wrprot_block range. + */ +} ALT_QSPI_DEV_SIZE_CONFIG_t; + +/******************************************************************************/ +/*! + * This type enumerates the QSPI clock phase activity options outside the SPI + * word. + */ +typedef enum ALT_QSPI_CLK_PHASE_e +{ + ALT_QSPI_CLK_PHASE_ACTIVE = 0, /*!< The SPI clock is active outside the + * word + */ + ALT_QSPI_CLK_PHASE_INACTIVE = 1 /*!< The SPI clock is inactive outside the + * word + */ +} ALT_QSPI_CLK_PHASE_t; + +/******************************************************************************/ +/*! + * This type enumerates the QSPI clock polarity options outside the SPI word. + */ +typedef enum ALT_QSPI_CLK_POLARITY_e +{ + ALT_QSPI_CLK_POLARITY_LOW = 0, /*!< SPI clock is quiescent low outside the + * word. + */ + ALT_QSPI_CLK_POLARITY_HIGH = 1 /*!< SPI clock is quiescent high outside the + * word. + */ +} ALT_QSPI_CLK_POLARITY_t; + +/******************************************************************************/ +/*! + * QSPI Controller Timing Configuration + * + * This type defines the structure used to configure timing paramaters used by + * the QSPI controller to communicate with a target flash device. + * + * All timing values are defined in cycles of the SPI master ref clock. + */ +typedef struct ALT_QSPI_TIMING_CONFIG_s +{ + ALT_QSPI_CLK_PHASE_t clk_phase; /*!< Selects whether the clock is in an + * active or inactive phase outside the + * SPI word. + */ + + ALT_QSPI_CLK_POLARITY_t clk_pol; /*!< Selects whether the clock is quiescent + * low or high outside the SPI word. + */ + + uint32_t cs_da; /*!< Chip Select De-Assert. Added delay in + * master reference clocks for the length + * that the master mode chip select + * outputs are de-asserted between + * transactions. If CSDA = \e X, then the + * chip select de-assert time will be: 1 + * sclk_out + 1 ref_clk + \e X ref_clks. + */ + uint32_t cs_dads; /*!< Chip Select De-Assert Different + * Slaves. Delay in master reference + * clocks between one chip select being + * de-activated and the activation of + * another. This is used to ensure a quiet + * period between the selection of two + * different slaves. CSDADS is only + * relevant when switching between 2 + * different external flash devices. If + * CSDADS = \e X, then the delay will be: + * 1 sclk_out + 3 ref_clks + \e X + * ref_clks. + */ + uint32_t cs_eot; /*!< Chip Select End Of Transfer. Delay in + * master reference clocks between last + * bit of current transaction and + * de-asserting the device chip select + * (n_ss_out). By default (when CSEOT=0), + * the chip select will be de-asserted on + * the last falling edge of sclk_out at + * the completion of the current + * transaction. If CSEOT = \e X, then chip + * selected will de-assert \e X ref_clks + * after the last falling edge of + * sclk_out. + */ + uint32_t cs_sot; /*!< Chip Select Start Of Transfer. Delay in + * master reference clocks between setting + * n_ss_out low and first bit transfer. By + * default (CSSOT=0), chip select will be + * asserted half a SCLK period before the + * first rising edge of sclk_out. If CSSOT + * = \e X, chip select will be asserted + * half an sclk_out period before the + * first rising edge of sclk_out + \e X + * ref_clks. + */ + + uint32_t rd_datacap; /*!< The additional number of read data + * capture cycles (ref_clk) that should be + * applied to the internal read data + * capture circuit. The large + * clock-to-out delay of the flash memory + * together with trace delays as well as + * other device delays may impose a + * maximum flash clock frequency which is + * less than the flash memory device + * itself can operate at. To compensate, + * software should set this register to a + * value that guarantees robust data + * captures. + */ +} ALT_QSPI_TIMING_CONFIG_t; + +/******************************************************************************/ +/*! + * Device Instruction Configuration + * + * This type defines a structure for specifying the optimal instruction set + * configuration to use with a target flash device. + */ +typedef struct ALT_QSPI_DEV_INST_CONFIG_s +{ + uint32_t op_code; /*!< The read or write op code to use + * for the device transaction. + */ + ALT_QSPI_MODE_t inst_type; /*!< Instruction mode type for the + * controller to use with the + * device. The instruction type + * applies to all instructions + * (reads and writes) issued from + * either the Direct Access + * Controller or the Indirect + * Acces Controller. + */ + ALT_QSPI_MODE_t addr_xfer_type; /*!< Address transfer mode type. The + * value of this field is ignored + * if the \e inst_type data member + * is set to anything other than + * ALT_QSPI_MODE_SINGLE. In that + * case, the addr_xfer_type + * assumes the same mode as the \e + * inst_type. + */ + ALT_QSPI_MODE_t data_xfer_type; /*!< Data transfer mode type. The + * value of this field is ignored + * if the \e inst_type data member + * is set to anything other than + * ALT_QSPI_MODE_SINGLE. In that + * case, the data_xfer_type + * assumes the same mode as the \e + * inst_type. + */ + uint32_t dummy_cycles; /*!< Number of dummy clock cycles + * required by device for a read + * or write instruction. + */ + +} ALT_QSPI_DEV_INST_CONFIG_t; + +/******************************************************************************/ +/*! + * Get the current value of the QSPI master baud rate divisor. + * + * \returns The value of the QSPI master baud rate divisor. + */ +ALT_QSPI_BAUD_DIV_t alt_qspi_baud_rate_div_get(void); + +/******************************************************************************/ +/*! + * Set the current value of the QSPI master baud rate divisor. + * + * Sets the value of the QSPI master baud rate divisor. + * + * \param baud_rate_div + * The master baud rate divisor. Valid range includes + * even values 2 to 32. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_baud_rate_div_set(const ALT_QSPI_BAUD_DIV_t baud_rate_div); + +/******************************************************************************/ +/*! + * Get the current QSPI device peripheral chip select output and decode function + * configuration values. + * + * \param cs + * [out] The chip select line output values. + * + * \param cs_mode + * [out] The decode mode to use for the chip selects. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_chip_select_config_get(uint32_t* cs, ALT_QSPI_CS_MODE_t* cs_mode); + +/******************************************************************************/ +/*! + * Set the QSPI device peripheral chip select outputs and decode function + * configuration. + * + * The chip select lines output values operate according to the selected chip + * select decode mode. If \e cs_mode is ALT_QSPI_CS_MODE_SINGLE_SELECT then + * cs[3:0] are output thus: + * + * cs[3:0] | n_ss_out[3:0] + * :---------|:---------------------------- + * xxx0 | 1110 + * xx01 | 1101 + * x011 | 1011 + * 0111 | 0111 + * 1111 | 1111 (no peripheral selected) + * + * Otherwise if \e cs_mode is ALT_QSPI_CS_MODE_DECODE then cs[3:0] directly + * drives n_ss_out[3:0]. + * + * \param cs + * The chip select line output values. + * + * \param cs_mode + * The decode mode to use for the chip selects. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_chip_select_config_set(const uint32_t cs, + const ALT_QSPI_CS_MODE_t cs_mode); + +/******************************************************************************/ +/*! + * Disable the mode bits from being sent after the address bytes. + * + * Prevent the mode bits defined in the Mode Bit Configuration register from + * being sent following the address bytes. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_mode_bit_disable(void); + +/******************************************************************************/ +/*! + * Enable the mode bits to be sent after the address bytes. + * + * Ensure the mode bits defined in the Mode Bit Configuration register to + * be sent following the address bytes. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_mode_bit_enable(void); + +/******************************************************************************/ +/*! + * Get the current value of the Mode Bit Configuration register. + * + * \returns The 8 bit value that is sent to the device following the address + * bytes when the mode bit is enabled (see: alt_qspi_mode_bit_enable()) + */ +uint32_t alt_qspi_mode_bit_config_get(void); + +/******************************************************************************/ +/*! + * Set the value of the Mode Bit Configuration register. + * + * Set the value of the 8 bits that are sent to the device following the address + * bytes when the mode bit is enabled (see: alt_qspi_mode_bit_enable()) + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param mode_bits + * The 8 bit value sent to the device following the address bytes. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_mode_bit_config_set(const uint32_t mode_bits); + +/******************************************************************************/ +/*! + * Get the current flash device size and write protection configuration. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_DEV_SIZE_CONFIG_t structure to + * contain the returned flash device size and write protection + * configuration. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_size_config_get(ALT_QSPI_DEV_SIZE_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the flash device size and write protection configuration. + * + * \param cfg + * Pointer to a ALT_QSPI_DEV_SIZE_CONFIG_t structure containing the + * flash device size and write protection configuration. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_size_config_set(const ALT_QSPI_DEV_SIZE_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Get the current QSPI device read instruction configuration. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure to + * contain the returned QSPI controller instruction configuration + * used when performing read transactions with the device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_read_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the QSPI device read instruction configuration. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param cfg + * Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure specifying the + * desired op code, transfer widths, and dummy cycles for the QSPI + * controller to use when performing read transactions with the + * device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_read_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Get the current QSPI device write instruction configuration. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure to + * contain the returned QSPI controller instruction configuration + * used when performing write transactions with the device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_write_config_get(ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the QSPI device write instruction configuration. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param cfg + * Pointer to a ALT_QSPI_DEV_INST_CONFIG_t structure specifying the + * desired op code, transfer widths, and dummy cycles for the QSPI + * controller to use when performing write transactions with the + * device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_device_write_config_set(const ALT_QSPI_DEV_INST_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Get the QSPI device delay and timing configuration parameters. + * + * This function returns the settings of the chip select delay and timing + * configurations. + * + * \param cfg + * [out] Pointer to a ALT_QSPI_TIMING_CONFIG_t structure to return + * the device timing and delay settings. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_timing_config_get(ALT_QSPI_TIMING_CONFIG_t * cfg); + +/******************************************************************************/ +/*! + * Set the QSPI device delay and timing configuration parameters. + * + * This function allows the user to configure how the chip select is driven + * after each flash access. This is required as each device may have different + * timing requirements. As the serial clock frequency is increased, these + * timing parameters become more important and can be adjusted to meet the + * requirements of a specific flash device. All timings are defined in cycles + * of the SPI master ref clock. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param cfg + * Pointer to a ALT_QSPI_TIMING_CONFIG_t structure specifying the + * desired timing and delay settings. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_timing_config_set(const ALT_QSPI_TIMING_CONFIG_t * cfg); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_DAC Direct Access Mode + * + * In direct access mode, an access to the AHB data slave triggers a read or + * write command to the flash memory. To use the direct access mode, enable the + * direct access controller with the alt_qspi_direct_enable() function. An + * external master, for example a processor, triggers the direct access + * controller with a read or write operation to the AHB data slave + * interface. The data slave exposes a 1MB window into the flash device. You can + * remap this window to any 1MB location within the flash device address range. + * + * To remap the AHB data slave to access other 1MB regions of the flash device, + * enable address remapping by calling alt_qspi_ahb_address_remap_enable(). All + * incoming data slave accesses remap to the offset specified in the remap + * address register which is configured by alt_qspi_ahb_remap_address_set(). + * + * The 20 LSBs of incoming addresses are used for accessing the 1MB region and + * the higher bits are ignored. + * + * The quad SPI controller does not issue any error status for accesses that lie + * outside the connected flash memory space. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Disable the QSPI Direct Access Controller. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_direct_disable(void); + +/******************************************************************************/ +/*! + * Enable the QSPI Direct Access Controller. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_direct_enable(void); + +/******************************************************************************/ +/*! + * Get the current AHB address remap value. + * + * Returns the current value of the AHB remap address register. + * + * \returns The value used to remap an incoming AHB address to a + * different address used by the flash device. + */ +uint32_t alt_qspi_ahb_remap_address_get(void); + +/******************************************************************************/ +/*! + * Set the AHB address remap value. + * + * Sets the value of the AHB remap address register. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param ahb_remap_addr + * The value used to remap an incoming AHB address to a different + * address used by the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_ahb_remap_address_set(const uint32_t ahb_remap_addr); + +/******************************************************************************/ +/*! + * Disable AHB address remapping. + * + * Disables remapping of incoming AHB addresses so they are sent unmodified to + * the flash device. The incoming AHB address maps directly to the address + * serially sent to the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_ahb_address_remap_disable(void); + +/******************************************************************************/ +/*! + * Enable AHB address remapping. + * + * Enables remapping of incoming AHB addresses so they are modified to + * \ + \e N, where \e N is the configured remap address value. + * + * See: alt_qspi_ahb_remap_address_set(). + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_ahb_address_remap_enable(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_INDAC Indirect Access Mode + * + * In indirect access mode, flash data is temporarily buffered in the QSPI + * controller's SRAM. Software controls and triggers indirect accesses through + * the APB register slave interface. The controller transfers data through the + * AHB data slave interface. + * + * An indirect read operation reads data from the flash memory, places the data + * into the SRAM, and transfers the data to an external master through the AHB + * data slave interface. + * + * An indirect write operation programs data from the SRAM to the flash memory. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Starts an indirect read transfer. + * + * Initiates an indirect read transfer of the requested number of bytes from the + * designated flash address. + * + * After calling this function, flash data may be read from the QSPI SRAM buffer + * as it becomes available via one of the following methods: + * * Directly from the AHB data slave interface at the configured AHB trigger + * address. If the requested data is not immediately available in the SRAM + * buffer then AHB wait states will be applied until the data has been read + * from flash into the SRAM buffer. Alternatively, data may be read from the + * AHB data slave as the SRAM is filled. The availability of data in the SRAM + * buffer may be determined by an SRAM watermark interrupt notification or by + * polling the SRAM fill level. + * * Configuring and enabling the QSPI DMA peripheral controller. + * + * The following is a list of restrictions: + * * flash_addr must be word aligned. + * * num_bytes must be word aligned. + * * The transfer must not cross the 3-byte addressing boundary. This + * restriction may be device specific and may be lifted in the future. + * + * \param flash_addr + * The flash source address to read data from. + * + * \param num_bytes + * The number of bytes to read from the flash source address. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_start(const uint32_t flash_addr, + const size_t num_bytes); + +/******************************************************************************/ +/*! + * Finish the indirect read operation that was completed or canceled. This + * function should be called before another indirect read is started. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_finish(void); + +/******************************************************************************/ +/*! + * Cancel all indirect read transfers in progress. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_cancel(void); + +/******************************************************************************/ +/*! + * Get the current indirect read SRAM fill level value. + * + * Returns the SRAM fill level for the indirect read partition in units of SRAM + * words (4 bytes). + * + * \returns The SRAM fill level for the indirect read partition in units of + * SRAM words (4 bytes). + */ +uint32_t alt_qspi_indirect_read_fill_level(void); + +/******************************************************************************/ +/*! + * Get the current indirect read watermark value. + * + * The watermark value (in bytes) represents the minimum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level passes + * the watermark, an interrupt source is also generated. This can be disabled by + * writing a value of all zeroes. + * + * \returns The current indirect read watermark value. + */ +uint32_t alt_qspi_indirect_read_watermark_get(void); + +/******************************************************************************/ +/*! + * Set the indirect read watermark value. + * + * The watermark value (in bytes) represents the minimum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level passes + * the watermark, an interrupt source is also generated. This can be disabled by + * writing a value of all zeroes. The watermark can only be set when no indirect + * read is in progress. + * + * \param watermark + * The watermark value (in bytes). + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_read_watermark_set(const uint32_t watermark); + +/******************************************************************************/ +/*! + * Returns true when an indirect read has completed otherwise false. + * + * \internal + * Returns Indirect Read Transfer Control Register bit 5 "Indirect Completion Status". + * \endinternal + * + * \returns Returns true when an indirect read has completed otherwise false. + */ +bool alt_qspi_indirect_read_is_complete(void); + +/******************************************************************************/ +/*! + * Starts an indirect write transfer. + * + * Initiates an indirect write transfer of the requested number of bytes to the + * designated flash address. + * + * After calling this function, flash data may be written to the QSPI SRAM + * buffer there is space via one of the following methods: + * * Directly from the AHB data slave interface at the configured AHB trigger + * address. If the requested space is not immediately available in the SRAM + * buffer then AHB wait states will be applied until the space becomes + * available. Alternatively, the data may be written to the AHB data slave + * as the SRAM is drained. The space in the SRAM buffer may be determined by + * an SRAM watermark interrupt notification or by polling the SRAM fill + * level and subtracting that value from the SRAM space devoted to writes. + * * Configuring and enabling the QSPI DMA peripheral controller. + * + * The following is a list of restrictions: + * * flash_addr must be word aligned. + * * num_bytes must be word aligned. + * * num_bytes must be 256 or below. This is due to a device specific + * limitation and may be lifted in the future. + * * The transfer must not cross the page (256 byte) addressing boundary. This + * restriction may be device specific and may be lifted in the future. + * + * \param flash_addr + * The flash destination address to write data to. + * + * \param num_bytes + * The number of bytes to write to the flash. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_start(const uint32_t flash_addr, + const size_t num_bytes); + +/******************************************************************************/ +/*! + * Finish the indirect write operation that was completed or canceled. This + * function should be called before another indirect write is started. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_finish(void); + +/******************************************************************************/ +/*! + * Cancel all indirect write transfers in progress. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_cancel(void); + +/******************************************************************************/ +/*! + * Get the current indirect write SRAM fill level value. + * + * Returns the SRAM fill level for the indirect write partition in units of SRAM + * words (4 bytes). + * + * \returns The SRAM fill level for the indirect write partition in units of + * SRAM words (4 bytes). + */ +uint32_t alt_qspi_indirect_write_fill_level(void); + +/******************************************************************************/ +/*! + * Get the current indirect write watermark value. + * + * The watermark value (in bytes) represents the maximum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level falls + * below the watermark, an interrupt is also generated. This can be disabled by + * writing a value of all ones. + * + * \returns The current indirect write watermark value. + */ +uint32_t alt_qspi_indirect_write_watermark_get(void); + +/******************************************************************************/ +/*! + * Set the indirect write watermark value. + * + * The watermark value (in bytes) represents the maximum fill level of the SRAM + * before a DMA peripheral access is permitted. When the SRAM fill level falls + * below the watermark, an interrupt is also generated. This can be disabled by + * writing a value of all ones. The watermark can only be set when no indirect + * write is in progress. + * + * \param watermark + * The watermark value (in bytes). + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_indirect_write_watermark_set(const uint32_t watermark); + +/******************************************************************************/ +/*! + * Returns true when an indirect write has completed otherwise false. + * + * \internal + * Returns Indirect Write Transfer Control Register bit 5 "Indirect Completion + * Status". + * \endinternal + * + * \returns Returns true when an indirect write has completed otherwise + * false. + */ +bool alt_qspi_indirect_write_is_complete(void); + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_CFG_SRAM SRAM Partition + * + * The SRAM local memory buffer is a 128 by 32-bit (512 total bytes) memory. The + * SRAM has two partitions, with the lower partition reserved for indirect read + * operations and the upper partition for indirect write operations. The size of + * the partitions is specified in the SRAM partition register, based on 32-bit + * word sizes. For example, to specify four bytes of storage, write the value 1. + * The value written to the indirect read partition size field ( addr ) defines + * the number of entries reserved for indirect read operations. For example, write + * the value 32 (0x20) to partition the 128-entry SRAM to 32 entries (25%) for + * read usage and 96 entries (75%) for write usage. + * + * The functions in this section provide accces to configure the SRAM read + * partition allocation. + * + * @{ + */ + +/*! + * The size of the onboard SRAM in bytes. + */ +#define ALT_QSPI_SRAM_FIFO_SIZE (512) + +/* + * The size of the onboard SRAM in entries. Each entry is word (32-bit) sized. + */ +#define ALT_QSPI_SRAM_FIFO_ENTRY_COUNT (512 / sizeof(uint32_t)) + +/******************************************************************************/ +/*! + * Get the entry count (words) of the indirect read partition in the QSPI + * controller SRAM. + * + * There is an additional word of read memory not in the SRAM but used to + * buffer the SRAM and the AHB. As such, the total on board memory buffer for + * indirect read is 1 more than the value reported by this function. + * + * \returns The count of 32-bit words of the indirect read partition in the + * QSPI controller SRAM. + * + * \internal + * The documentation states that the number of locations allocated to indirect + * read = SRAM_PARTITION_REG + 1. Cadence clarified that the +1 comes from an + * additional register slice for read's, implemented in FLOPs, which was done + * to avoid connection the SRAM directly to the AHB interface. This was done + * for performance / timing reasons. The +1 will not be included in the return + * value but documented as an additional entry. + * \endinternal + */ +uint32_t alt_qspi_sram_partition_get(void); + +/******************************************************************************/ +/*! + * Set the entry count (words) of the indirect read partition in the QSPI + * controller SRAM. + * + * Note: It is recommended that setting SRAM partition to 0 or 127 should be + * avoided although it is not prohibited. + * + * \param read_part_size + * The count of 32-bit words to allocate to the indirect read + * partition in the QSPI controller SRAM. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_sram_partition_set(const uint32_t read_part_size); + +/*! @} */ + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_ERASE Flash Erase + * + * The functions in this group are used to erase selected portions of a flash + * device. + * @{ + */ + +/******************************************************************************/ +/*! + * This function erases the designated flash device subsector. + * + * This function erases the flash device subsector containing the designated + * flash address. Any address within the subsector is valid. + * + * \param addr + * A flash address contained within the the subsector to be erased. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_erase_subsector(const uint32_t addr); + +/******************************************************************************/ +/*! + * This function erases the designated flash device sector. + * + * This function erases the flash device sector containing the designated flash + * address. Any address within the sector is valid. + * + * \param addr + * A flash address contained within the the sector to be erased. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_erase_sector(const uint32_t addr); + +/******************************************************************************/ +/*! + * This function erases the entire flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_erase_chip(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_QSPI_DMA DMA Peripheral Interface + * + * The DMA peripheral request controller is only used for the indirect mode of + * operation where data is temporarily stored in the SRAM. The QSPI flash + * controller uses the DMA peripheral request interface to trigger the external + * DMA into performing data transfers between memory and the QSPI + * controller. + * + * There are two DMA peripheral request interfaces, one for indirect reads and + * one for indirect writes. The DMA peripheral request controller can issue two + * types of DMA requests, single or burst, to the external DMA. The number of + * bytes for each single or burst request is specified using the + * alt_qspi_dma_config_set(). The DMA peripheral request controller splits the + * total amount of data to be transferred into a number of DMA burst and single + * requests by dividing the total number of bytes by the number of bytes + * specified in the burst request, and then dividing the remainder by the number + * of bytes in a single request. + * + * When programming the DMA controller, the burst request size must match the + * burst request size set in the quad SPI controller to avoid quickly reaching + * an overflow or underflow condition. + * @{ + */ + +/******************************************************************************/ +/*! + * Disable the QSPI DMA peripheral interface. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_disable(void); + +/******************************************************************************/ +/*! + * Enable the QSPI DMA peripheral interface. + * + * Enable the QSPI DMA handshaking logic. When enabled the QSPI will trigger DMA + * transfer requests via the DMA peripheral interface. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_enable(void); + +/******************************************************************************/ +/*! + * Get the current DMA peripheral configuration. + * + * This function returns the QSPI DMA peripheral interface single and burst type + * transfer size configurations. + * + * \param single_type_sz + * [out] The number of bytes for each DMA single type + * request. Value must be a power of 2 between 1 and 32728. + * + * \param burst_type_sz + * [out] The number of bytes for each DMA burst type request. Value + * must be a power of 2 between 1 and 32728. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_config_get(uint32_t * single_type_sz, + uint32_t * burst_type_sz); + +/******************************************************************************/ +/*! + * Set the DMA peripheral configuration. + * + * This function configures the QSPI DMA peripheral interface single and burst + * type transfer sizes. The DMA configruation should be setup while the + * controller is idle. Because all transfers are required to be word aligned, + * the smallest DMA request is 4 bytes. + * + * This API requires that the QSPI controller be idle, as determined by + * alt_qspi_is_idle(). + * + * \param single_type_sz + * The number of bytes for each DMA single type request. Value must + * be a power of 2 between 4 and 32768. + * + * \param burst_type_sz + * The number of bytes for each DMA burst type request. Value must + * be a power of 2 between 4 and 32768. Bursts must be equal or + * larger than single requests. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_qspi_dma_config_set(const uint32_t single_type_sz, + const uint32_t burst_type_sz); + + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_QSPI_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_qspi_private.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_qspi_private.h new file mode 100644 index 000000000..e0e63e65d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_qspi_private.h @@ -0,0 +1,167 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! \file + * Altera - QSPI Flash Controller Module + */ + +#ifndef __ALT_QSPI_PRIVATE_H__ +#define __ALT_QSPI_PRIVATE_H__ + +#include "socal/socal.h" + +// +// This section provisions support for various flash devices. +// + +#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1 + +///// + +#define ALT_QSPI_PAGE_ADDR_MSK 0xFFFFFF00 +#define ALT_QSPI_PAGE_SIZE 0x00000100 // 256 B +#define ALT_QSPI_SUBSECTOR_ADDR_MSK 0xFFFFF000 +#define ALT_QSPI_SUBSECTOR_SIZE 0x00001000 // 4096 B +#define ALT_QSPI_SECTOR_ADDR_MSK 0xFFFF0000 +#define ALT_QSPI_SECTOR_SIZE 0x00010000 // 64 KiB +#define ALT_QSPI_BANK_ADDR_MSK 0xFF000000 +#define ALT_QSPI_BANK_SIZE 0x01000000 // 16 MiB + +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +#define ALT_QSPI_N25Q_DIE_ADDR_MSK 0xFE000000 +#define ALT_QSPI_N25Q_DIE_SIZE 0x02000000 // 32 MiB +#endif + +///// + +// Default delay timing (in ns) for N25Q. +// These values are from the N25Q handbook. The timing correctness is difficult +// to test because the test setup does not feature mutliple chips. +#define ALT_QSPI_TSHSL_NS_DEF (50) +#define ALT_QSPI_TSD2D_NS_DEF (0) +#define ALT_QSPI_TCHSH_NS_DEF (4) +#define ALT_QSPI_TSLCH_NS_DEF (4) + +/* +// Default delay timing (in ns) +#define ALT_QSPI_TSHSL_NS_DEF (200) +#define ALT_QSPI_TSD2D_NS_DEF (255) +#define ALT_QSPI_TCHSH_NS_DEF (20) +#define ALT_QSPI_TSLCH_NS_DEF (20) +*/ + +// Flash commands +#define ALT_QSPI_STIG_OPCODE_READ (0x03) +#define ALT_QSPI_STIG_OPCODE_4BYTE_READ (0x13) +#define ALT_QSPI_STIG_OPCODE_FASTREAD (0x0B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO (0xBB) +#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO (0xEB) +#define ALT_QSPI_STIG_OPCODE_PP (0x02) +#define ALT_QSPI_STIG_OPCODE_DUAL_PP (0xA2) +#define ALT_QSPI_STIG_OPCODE_QUAD_PP (0x32) +#define ALT_QSPI_STIG_OPCODE_RDID (0x9F) +#define ALT_QSPI_STIG_OPCODE_WREN (0x06) +#define ALT_QSPI_STIG_OPCODE_WRDIS (0x04) +#define ALT_QSPI_STIG_OPCODE_RDSR (0x05) +#define ALT_QSPI_STIG_OPCODE_WRSR (0x01) +#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE (0x20) +#define ALT_QSPI_STIG_OPCODE_SEC_ERASE (0xD8) +#define ALT_QSPI_STIG_OPCODE_BULK_ERASE (0xC7) +#define ALT_QSPI_STIG_OPCODE_DIE_ERASE (0xC4) +#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE (0x60) +#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG (0xC8) +#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG (0xC5) +#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG (0x05) +#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG (0x01) +#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE (0xB7) +#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE (0xE9) + +// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts. +#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT +#define ALT_QSPI_STIG_OPCODE_RESET_EN (0x66) +#define ALT_QSPI_STIG_OPCODE_RESET_MEM (0x99) +#define ALT_QSPI_STIG_OPCODE_RDFLGSR (0x70) +#define ALT_QSPI_STIG_OPCODE_CLRFLGSR (0x50) +#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM (0x5A) +#endif + +// Spansion commands +// #define OPCODE_ECRM (0xFF) // Exit continuous read mode + +#define QSPI_READ_CLK_MHZ (50) +#define QSPI_FASTREAD_CLK_MHZ (100) + +// Manufacturer ID +#define ALT_QSPI_STIG_RDID_JEDECID_MICRON (0x20) +#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX (0x20) // Same as Micron +#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION (0xEF) +#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND (0xEF) // Same as Spansion +#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC (0xC2) +#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL (0x1F) + +#define ALT_QSPI_STIG_RDID_JEDECID_GET(value) ((value >> 0) & 0xff) +#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff) + +#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value) ((value >> 7) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value) ((value >> 5) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value) ((value >> 4) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value) ((value >> 1) & 0x1) +#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value) ((value >> 0) & 0x1) + +#define ALT_QSPI_STIG_SR_BUSY_GET(value) ((value >> 0) & 0x1) + +///// + +#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff) + +ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size); + +ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy, + uint32_t num_bytes, uint32_t * output, + uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy, + uint32_t num_bytes, const uint32_t * input, + uint32_t timeout); +ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy, + uint32_t address, + uint32_t timeout); + +ALT_STATUS_CODE alt_qspi_device_wren(void); +ALT_STATUS_CODE alt_qspi_device_wrdis(void); +ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid); +ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param); +ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank); + +#endif // __ALT_PRIVATE_QSPI_H__ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_reset_manager.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_reset_manager.h new file mode 100644 index 000000000..dd3b5a498 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_reset_manager.h @@ -0,0 +1,291 @@ +/*! \file + * Altera - SoC Reset Manager + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_RESET_MGR_H__ +#define __ALT_RESET_MGR_H__ + +#include "hwlib.h" +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! \addtogroup RST_MGR The Reset Manager + * + * The Reset Manager API defines functions for accessing, configuring, and + * controlling the HPS reset behavior. + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup RST_MGR_STATUS Reset Status + * + * This functional group provides information on various aspects of SoC reset + * status and timeout events. + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the set of reset causes and timeout events as + * register mask values. + */ +typedef enum ALT_RESET_EVENT_e +{ + /*! Power-On Voltage Detector Cold Reset */ + ALT_RESET_EVENT_PORVOLTRST = 0x00000001, + + /*! nPOR Pin Cold Reset */ + ALT_RESET_EVENT_NPORPINRST = 0x00000002, + + /*! FPGA Core Cold Reset */ + ALT_RESET_EVENT_FPGACOLDRST = 0x00000004, + + /*! CONFIG_IO Cold Reset */ + ALT_RESET_EVENT_CONFIGIOCOLDRST = 0x00000008, + + /*! Software Cold Reset */ + ALT_RESET_EVENT_SWCOLDRST = 0x00000010, + + /*! nRST Pin Warm Reset */ + ALT_RESET_EVENT_NRSTPINRST = 0x00000100, + + /*! FPGA Core Warm Reset */ + ALT_RESET_EVENT_FPGAWARMRST = 0x00000200, + + /*! Software Warm Reset */ + ALT_RESET_EVENT_SWWARMRST = 0x00000400, + + /*! MPU Watchdog 0 Warm Reset */ + ALT_RESET_EVENT_MPUWD0RST = 0x00001000, + + /*! MPU Watchdog 1 Warm Reset */ + ALT_RESET_EVENT_MPUWD1RST = 0x00002000, + + /*! L4 Watchdog 0 Warm Reset */ + ALT_RESET_EVENT_L4WD0RST = 0x00004000, + + /*! L4 Watchdog 1 Warm Reset */ + ALT_RESET_EVENT_L4WD1RST = 0x00008000, + + /*! FPGA Core Debug Reset */ + ALT_RESET_EVENT_FPGADBGRST = 0x00040000, + + /*! DAP Debug Reset */ + ALT_RESET_EVENT_CDBGREQRST = 0x00080000, + + /*! SDRAM Self-Refresh Timeout */ + ALT_RESET_EVENT_SDRSELFREFTIMEOUT = 0x01000000, + + /*! FPGA manager handshake Timeout */ + ALT_RESET_EVENT_FPGAMGRHSTIMEOUT = 0x02000000, + + /*! SCAN manager handshake Timeout */ + ALT_RESET_EVENT_SCANHSTIMEOUT = 0x04000000, + + /*! FPGA handshake Timeout */ + ALT_RESET_EVENT_FPGAHSTIMEOUT = 0x08000000, + + /*! ETR Stall Timeout */ + ALT_RESET_EVENT_ETRSTALLTIMEOUT = 0x10000000 +} ALT_RESET_EVENT_t; + +/******************************************************************************/ +/*! + * Gets the reset and timeout events that caused the last reset. + * + * The ALT_RESET_EVENT_t enumeration values should be used to selectively + * examine the returned reset cause(s). + * + * \returns A mask of the reset and/or timeout events that caused the last + * reset. + */ +uint32_t alt_reset_event_get(void); + +/******************************************************************************/ +/*! + * Clears the reset and timeout events that caused the last reset. + * + * \param event_mask + * A mask of the selected reset and timeout events to clear in the + * Reset Manager \e stat register. The mask selection can be formed + * using the ALT_RESET_EVENT_t enumeration values. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup RST_MGR_CTRL Reset Control + * + * This functional group provides global and selective reset control for the SoC + * and its constituent modules. + * + * @{ + */ + +/******************************************************************************/ +/*! + * Initiate a cold reset of the SoC. + * + * If this function is successful, then it should never return. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_reset_cold_reset(void); + +/******************************************************************************/ +/*! + * Initiate a warm reset of the SoC. + * + * Perform a hardware sequenced warm reset of the SoC. A hardware sequenced + * reset handshake with certain modules can optionally be requested in an + * attempt to ensure an orderly reset transition. + * + * \param warm_reset_delay + * Specifies the number of cycles after the Reset Manager releases + * the Clock Manager reset before releasing any other hardware + * controlled resets. Value must be greater than 16 and less than + * 256. + * + * \param nRST_pin_clk_assertion + * Specifies that number of clock cycles (osc1_clk?) to externally + * assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <= + * (2**20 - 1). A value of 0 prevents any assertion of nRST. + * + * \param sdram_refresh + * Controls whether the contents of SDRAM survive a hardware + * sequenced warm reset. The reset manager requests the SDRAM + * controller to put SDRAM devices into self-refresh mode before + * asserting warm reset signals. An argument value of \b true + * enables the option, \b false disables the option. + * + * \param fpga_mgr_handshake + * Controls whether a handshake between the reset manager and FPGA + * manager occurs before a warm reset. The handshake is used to + * warn the FPGA manager that a warm reset is imminent so it can + * prepare for it by driving its output clock to a quiescent state + * to avoid glitches. An argument value of \b true enables the + * option, \b false disables the option. + * + * \param scan_mgr_handshake + * Controls whether a handshake between the reset manager and scan + * manager occurs before a warm reset. The handshake is used to + * warn the scan manager that a warm reset is imminent so it can + * prepare for it by driving its output clock to a quiescent state + * to avoid glitches. An argument value of \b true enables the + * option, \b false disables the option. + * + * \param fpga_handshake + * Controls whether a handshake between the reset manager and the + * FPGA occurs before a warm reset. The handshake is used to warn + * the FPGA that a warm reset is imminent so that the FPGA prepare + * for the reset event in soft IP. An argument value of \b true + * enables the option, \b false disables the option. + * + * \param etr_stall + * Controls whether the ETR is requested to idle its AXI master + * interface (i.e. finish outstanding transactions and not initiate + * any more) to the L3 Interconnect before a warm reset. An + * argument value of \b true enables the option, \b false disables + * the option. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay, + uint32_t nRST_pin_clk_assertion, + bool sdram_refresh, + bool fpga_mgr_handshake, + bool scan_mgr_handshake, + bool fpga_handshake, + bool etr_stall); + +#if 0 +/*! \addtogroup RST_MGR_MPU + * + * This functional group provides reset control for the Cortex-A9 MPU module. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_PERIPH + * + * This functional group provides inidividual reset control for the HPS + * peripheral modules. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_BRG + * + * This functional group provides inidividual reset control for the bridge + * interfaces between the HPS and FPGA. + * + * @{ + */ + +/*! @} */ + +/*! \addtogroup RST_MGR_MISC + * + * This functional group provides inidividual reset control for miscellaneous + * HPS modules. + * + * @{ + */ + +/*! @} */ + +#endif + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_RESET_MGR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_sdmmc.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_sdmmc.h new file mode 100644 index 000000000..99255e77b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_sdmmc.h @@ -0,0 +1,1508 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_SDMMC_H__ +#define __ALT_SDMMC_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! + * \addtogroup ALT_SDMMC SD/MMC Controller API + * + * This module defines the API for controlling and accessing devices through the + * HPS SD/MMC Controller. + * + * This module provides programmatic access to the SD/MMC host + * controller functions for: + * * control and status + * * card/device interface configuration + * * command processor interface + * * internal DMA controller + * * FIFO + * + * The primary purpose of this API is to a provide a general purpose framework + * that can be used for writing software drivers that interact with a wide range of + * card and device types that may interface to HPS through the SD/MMC host controller. + * + * Although the HPS SD/MMC Controller supports SD, SDIO, CE-ATA, and MMC card and + * device types, this driver only supports block read/write data transfers to + * SD and MMC storage devices. + * + * Supported: + * * Integrated DMA Controller (IDMAC) + * * Host Bus: AHB (32-bit) + * * SD/MMC controller may be used by FPGA + * + * Unsupported: + * * Dual Data Rate (DDR) + * * More than one card + * * SDR104, SDR50, and DDR5 timing modes + * + * Clock Signals: + * * l4_mp_clk - AHB/APB Clock, Frequency Range: 0-100MHz, Must be greater than or equal to 1/10 cclk_in + * * sdmmc_clk - Card input clock. Both positive and negative edges are used, Frequency Range: 0-200MHz + * * sdmmc_cclk_out - Card Clock. Output from internal clock dividers. + * * sdmmc_fb_clk_in - Feedback version of cclk_out to compensate for external delays, Frequency Range: 0-50MHz + * + * Interface Signals: + * SD/MMC Controller Interface I/O Pins + * Signal Width Direction Description + * ====================================================================== + * sdmmc_cclk_out 1 Out Clock from controller to the card + * sdmmc_cmd 1 In/Out Card command + * sdmmc_pwren 1 Out External device power enable + * sdmmc_data 8 In/Out Card data + * + * Interrupts: + * * Three (3) interrupt outputs: + * - sdmmc_int + * + SDIO card interrupts + * + End bit error(read)/no CRC(write) + * + Auto command done + * + Start bit error + * + Hardware locked write error + * + FIFO underrun/overrun error + * + Data starvation by host timeout + * + Data read timeout/boot data start + * + Response Timeout/Boot ack received + * + Data CRC error + * + Response CRC error + * + Receive FIFO data request + * + Transmit FIFO data request + * + Data transfer over + * + Command done + * + Response error + * - sdmmc_sberr, single bit ECC error + * - sdmmc_dberr, double bit ECC error + * + * References: + * * Altera, Cyclone V Device Handbook Volume 3: Hard Processor System + * Technical Reference Manual, SD/MMC Controller. + * * Synopsys, DesignWare Cores Mobile Storage Host Databook, DWC_mobile_storage + * + * Notes: + * * To avoid glitches in the card clock outputs (cclk_out), the software should + * use the steps outlined in section 7.4 Phase Switching of the databook when + * changing the card clock frequency. + * + * * In order to utilize ECC, follow the embedded RAM initialization procedure in + * section 8 Enabling ECC of the data book. + * + * * The SD/MMC controller does not directly support voltage switching, card + * interrupts, or back-end power control of eSDIO card devices. However, you can + * connect these signals to general-purpose I/Os (GPIOs). + * + * * The SD/MMC controller does not contain a reset output as part of the external + * card interface. To reset the flash card device, consider using a general + * purpose output pin. + * + * Features: + * * Block Read/Write support + * - Internal DMA used for efficiency + * * Command Engine Interface + * * Internal DMA Interface + * * Configuration and Status Interface + * * Interrupt Status and Control Interface + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ALT_SDMMC_CSR General Control and Status Functions + * + * The declarations and functions in this group provide general purpose control + * and status functions for the SD/MMC Controller. + * @{ + */ + +/*! + * This type enumerates the possible card/device type that may be connected to the + * SD/MMC controller. + */ +typedef enum ALT_SDMMC_CARD_TYPE_e +{ + ALT_SDMMC_CARD_TYPE_NOTDETECT = 0, /*!< Cart type has not identified yet */ + ALT_SDMMC_CARD_TYPE_MMC = 1, /*!< MultiMedia Card */ + ALT_SDMMC_CARD_TYPE_SD = 2, /*!< Secure Digital Memory Card */ + ALT_SDMMC_CARD_TYPE_SDIOIO = 3, /*!< Secure Digital Input Output */ + ALT_SDMMC_CARD_TYPE_SDIOCOMBO = 4, /*!< Secure Digital Input Output Combo */ + ALT_SDMMC_CARD_TYPE_SDHC = 5, /*!< Secure Digital High Capacity */ + ALT_SDMMC_CARD_TYPE_CEATA = 6, /*!< Serial ATA interface based on the + * MultiMediaCard standard + */ +} ALT_SDMMC_CARD_TYPE_t; + +/*! + * This type defines a structure to hold identification and type information for a + * card connected to the SD/MMC controller. + * + * \internal + * See: Card_info declaration in synopmob_bus.h + * \endinternal + */ +typedef struct ALT_SDMMC_CARD_INFO_s +{ + ALT_SDMMC_CARD_TYPE_t card_type; /*!< Type of the card */ + uint32_t rca; /*!< Releative Card Address (RCA) */ + uint32_t xfer_speed; /*!< The maximum data transfer rate (bit/s) */ + uint32_t max_r_blkln; /*!< Max read data block length */ + uint32_t max_w_blkln; /*!< Max write data block length */ + bool partial_r_allowed; /*!< Partial blocks for read allowed */ + bool partial_w_allowed; /*!< Partial blocks for write allowed */ +} ALT_SDMMC_CARD_INFO_t; + +/*! + * Initialize the SD/MMC controller. + * + * Initializes the SD/MMC controller by gracefully bringing the controller out of + * reset. This function also initializes the registers, FIFO buffer pointers, DMA + * interface controls, and state machines in the controller. All interrupts are + * cleared and disabled (masked) and timeout parameters set to default values. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_sdmmc_init(void); + +/*! + * Uninitializes the SD/MMC controller by stopping any data transfers in progress and + * putting the controller into reset. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_sdmmc_uninit(void); + +/*! + * Reset the SD/MMC controller by stopping any data transfers in progress and + * putting the controller into reset and reinit it after reset complete. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_sdmmc_reset(void); + +/*! + * This type enumerates the SDMMC evailable commands. Read specification + * to the appropriate card type + */ +typedef enum ALT_SDMMC_CMD_INDEX_e +{ + /* TBD - Standart sdmmc commands... */ + ALT_SDMMC_GO_IDLE_STATE = 0, + ALT_SDMMC_ALL_SEND_CID = 2, + ALT_SDMMC_SET_RELATIVE_ADDR = 3, + ALT_SDMMC_SET_DSR = 4, + ALT_SDMMC_SEND_OP_COND = 5, + ALT_SDMMC_SWITCH = 6, + ALT_SDMMC_SEL_DES_CARD = 7, + ALT_SDMMC_IF_COND = 8, + ALT_SDMMC_SEND_EXT_CSD = 8, + ALT_SDMMC_SEND_CSD = 9, + ALT_SDMMC_SEND_CID = 10, + ALT_SDMMC_READ_DAT_UNTIL_STOP = 11, + ALT_SDMMC_STOP_TRANSMISSION = 12, + ALT_SDMMC_SEND_STATUS = 13, + ALT_SDMMC_GO_INACTIVE_STATE = 15, + ALT_SDMMC_SET_BLOCKLEN = 16, + ALT_SDMMC_READ_SINGLE_BLOCK = 17, + ALT_SDMMC_READ_MULTIPLE_BLOCK = 18, + ALT_SDMMC_WRITE_DAT_UNTIL_STOP = 20, + ALT_SDMMC_WRITE_BLOCK = 24, + ALT_SDMMC_WRITE_MULTIPLE_BLOCK = 25, + ALT_SDMMC_PROGRAM_CID = 26, + ALT_SDMMC_PROGRAM_CSD = 27, + ALT_SDMMC_SET_WRITE_PROT = 28, + ALT_SDMMC_CLR_WRITE_PROT = 29, + ALT_SDMMC_SEND_WRITE_PROT = 30, + ALT_SDMMC_TAG_SECTOR_START = 32, + ALT_SDMMC_TAG_SECTOR_END = 33, + ALT_SDMMC_UNTAG_SECTOR = 34, + ALT_SDMMC_TAG_ERASE_GROUP_START = 35, + ALT_SDMMC_TAG_ERASE_GROUP_END = 36, + ALT_SDMMC_UNTAG_ERASE_GROUP = 37, + ALT_SDMMC_ERASE = 38, + ALT_SDMMC_FAST_IO = 39, + ALT_SDMMC_GO_IRQ_STATE = 40, + ALT_SDMMC_LOCK_UNLOCK = 42, + ALT_SDMMC_APP_CMD = 55, + ALT_SDMMC_GEN_CMD = 56, + ALT_SDMMC_READ_OCR = 58, + ALT_SDMMC_CRC_ON_OFF = 59, + + ALT_SDMMC_STANDART_CMD_ALL = 60, + + /* TBD - Commands specific for card type. */ + ALT_SD_SET_BUS_WIDTH = 6, + ALT_SD_SEND_OP_COND = 41, + ALT_SD_SEND_SCR = 51, + + /* TBD - Clock command or command index does not matter... */ + ALT_SDMMC_CLK_INDEX = -1, + + ALT_SDMMC_CMD_ALL = ALT_SDMMC_STANDART_CMD_ALL + 1 +} ALT_SDMMC_CMD_INDEX_t; + +/*! + * This type defines a structure for command with options. + */ +typedef struct ALT_SDMMC_CMD_CONFIG_s +{ + uint32_t cmd_index : 6; //0-5 + /*!< Command index */ + uint32_t response_expect : 1; //6 + /*!< Response expected from card */ + uint32_t response_length_long : 1; //7 + /*!< Long response expected from card */ + uint32_t check_response_crc : 1; //8 + /*!< Check response CRC */ + uint32_t data_expected : 1; //9 + /*!< Data transfer expected (read/write) */ + uint32_t write_active : 1; //10 + /*!< 0 – Read from card + * 1 – Write to card + */ + uint32_t stream_mode_active : 1; //11 + /*!< Stream data transfer command */ + uint32_t send_auto_stop : 1; //12 + /*!< Send stop command at end of data transfer */ + uint32_t wait_prvdata_complete : 1; //13 + /*!< Wait for previous data transfer completion + * before sending command + */ + uint32_t stop_abort_cmd : 1; //14 + /*!< Stop or abort command intended to stop + * current data transfer in progress. + */ + uint32_t send_initialization : 1; //15 + /*!< Send initialization sequence before + * sending this command + */ + uint32_t card_number : 5; //16-20 + /*!< Card number in use. Represents physical + * slot number of card being accessed. + */ + uint32_t update_clock_registers_only : 1; //21 + /*!< Do not send commands, just update clock + * register value into card clock domain + */ + uint32_t read_ceata_device : 1; //22 + /*!< Host is performing read access (RW_REG or RW_BLK) + * towards CE-ATA device + */ + uint32_t ccs_expected : 1; //23 + /*!< Interrupts are enabled in CE-ATA device (nIEN = 0), + * and RW_BLK command expects command completion + * signal from CE-ATA device + */ + uint32_t enable_boot : 1; //24 + /*!< Enable Boot—this bit should be set only for + * mandatory boot mode. + */ + uint32_t expect_boot_ack : 1; //25 + /*!< Expect Boot Acknowledge. When Software sets + * this bit along with enable_boot, CIU expects a boot + * acknowledge start pattern of 0-1-0 from the selected card + */ + uint32_t disable_boot : 1; //26 + /*!< Disable Boot. */ + uint32_t boot_mode : 1; //27 + /*!< Boot Mode + * 0 - Mandatory Boot operation + * 1 - Alternate Boot operation + */ + uint32_t volt_switch : 1; //28 + /*!< Voltage switching enabled; must be set for CMD11 only */ + uint32_t use_hold_reg : 1; //29 + /*!< CMD and DATA sent to card through the HOLD Register */ + uint32_t reserved : 1; //30 + uint32_t start_bit : 1; //31 + /*!< Start command. Once command is taken by CIU, + * bit is cleared. When bit is set, host should + * not attempt to write to any command registers. + * If write is attempted, hardware lock error + * is set in raw interrupt register. + */ +} ALT_SDMMC_CMD_CONFIG_t; + +/*! + * Send the a command and command argument to the card and optionally return the + * command response. + * + * \param command + * The card command. + * + * \param command_arg + * The card command argument. + * + * \param response + * [out] A pointer to a 4 (32-bit) word to return the card command + * response. If NULL is passed then any card command response is + * ignored. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_sdmmc_command_send(ALT_SDMMC_CMD_INDEX_t command, + uint32_t command_arg, uint32_t *response); + +/*! + * This type defines a structure for get long response of last + * last complete command. + */ +typedef struct ALT_SDMMC_RESPONSE_s +{ + uint32_t resp0; + uint32_t resp1; + uint32_t resp2; + uint32_t resp3; + } ALT_SDMMC_RESPONSE_t; + +/*! + * Get the long response of the last compleated command. + * + * \param response + * [out] Pointer to a \ref ALT_SDMMC_RESPONSE_t structure to hold + * the long response. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_read_long_response(ALT_SDMMC_RESPONSE_t *response); + +/*! + * Returns the SD/MMC controller interrupt status register value which reflects + * interrupt controller interrupt status conditions before masking. + * + * \returns The raw value of the SD/MMC controller interrupt status register + * which reflects the current SD/MMC controller interrupt status + * conditions before masking. + */ +uint32_t alt_sdmmc_int_status_get(void); + +/*! + * Returns the SD/MMC controller interrupt mask register value which reflects the + * enabled (i.e. unmasked) interrupt status conditions. + * + * \returns The aggregate value of the enabled SD/MMC controller interrupt + * status conditions. A set (1) bit in the corresponding + * ALT_SDMMC_INT_STATUS_t position indicates an interrupt that is + * enabled. A clear (0) bit the corresponding ALT_SDMMC_INT_STATUS_t + * position indicates an interrupt that is masked. + */ +uint32_t alt_sdmmc_int_mask_get(void); + +/*! + * Clears the specified SD/MMC controller interrupt status conditions identified in + * the mask. + * + * This function clears one or more of the status conditions as contributors to the + * \b ALT_INT_INTERRUPT_SDMMC_IRQ interrupt signal state. + * + * \param mask + * Specifies the SD/MMC controller status conditions to clear. \e mask + * is a mask of logically OR'ed \ref ALT_SDMMC_INT_STATUS_t values that + * designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_sdmmc_int_clear(const uint32_t mask); + +/*! + * Disable the specified SD/MMC controller interrupt status conditions identified in + * the mask. + * + * This function disables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_SDMMC_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have the + * effect of enabling it as a contributor to the \b ALT_INT_INTERRUPT_SDMMC_IRQ + * interrupt signal state. The function alt_sdmmc_int_enable() is used to enable + * status source conditions. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_SDMMC_INT_STATUS_t values that designate the status conditions + * to disable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_sdmmc_int_disable(const uint32_t mask); + +/*! + * Enable the specified SD/MMC controller interrupt status conditions identified in + * the mask. + * + * This function enables one or more of the status conditions as contributors to the + * \b ALT_INT_INTERRUPT_SDMMC_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have the + * effect of disabling it as a contributor to the \b ALT_INT_INTERRUPT_SDMMC_IRQ + * interrupt signal state. The function alt_sdmmc_int_disable() is used to disable + * status source conditions. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_SDMMC_INT_STATUS_t values that designate the status conditions + * to enable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_sdmmc_int_enable(const uint32_t mask); + +/*! + * This type definition enumerates the interrupt status conditions that contribute + * to the \b ALT_INT_INTERRUPT_SDMMC_IRQ signal state. + * + * NOTE: Both the general purpose interrupt status conditions for the SD/MMC + * controller (\ref ALT_SDMMC_INT_STATUS_t) and the interrupt status conditions + * for the internal DMA controller (\ref ALT_SDMMC_DMA_INT_STATUS_t) contribute to + * the overall \b ALT_INT_INTERRUPT_SDMMC_IRQ signal state + */ +typedef enum ALT_SDMMC_INT_STATUS_e +{ + ALT_SDMMC_INT_STATUS_CD = (1UL << 0), /*!< Card Detect (CD) */ + ALT_SDMMC_INT_STATUS_RE = (1UL << 1), /*!< Response Error (RE) */ + ALT_SDMMC_INT_STATUS_CMD = (1UL << 2), /*!< Command Done (CMD) */ + ALT_SDMMC_INT_STATUS_DTO = (1UL << 3), /*!< Data Transfer Over (DTO) */ + ALT_SDMMC_INT_STATUS_TXDR = (1UL << 4), /*!< Transmit FIFO Data Request (TXDR) */ + ALT_SDMMC_INT_STATUS_RXDR = (1UL << 5), /*!< Receive FIFO Data Request (RXDR) */ + ALT_SDMMC_INT_STATUS_RCRC = (1UL << 6), /*!< Response CRC Error (RCRC) */ + ALT_SDMMC_INT_STATUS_DCRC = (1UL << 7), /*!< Data CRC Error (DCRC) */ + ALT_SDMMC_INT_STATUS_RTO = (1UL << 8), /*!< Response Timeout Boot Ack Received (RTO) */ + ALT_SDMMC_INT_STATUS_DRTO = (1UL << 9), /*!< Data Read Timeout Boot Data Start (DRTO) */ + ALT_SDMMC_INT_STATUS_HTO = (1UL << 10), /*!< Data Starvation Host Timeout (HTO) / Volt Switch_int */ + ALT_SDMMC_INT_STATUS_FRUN = (1UL << 11), /*!< FIFO Underrun Overrun Error (FRUN) */ + ALT_SDMMC_INT_STATUS_HLE = (1UL << 12), /*!< Hardware Locked Write Error (HLE) */ + ALT_SDMMC_INT_STATUS_SBE = (1UL << 13), /*!< Start-Bit Error (SBE) */ + ALT_SDMMC_INT_STATUS_ACD = (1UL << 14), /*!< Auto Command Done (ACD) */ + ALT_SDMMC_INT_STATUS_EBE = (1UL << 15), /*!< End-Bit Error (read) / write no CRC (EBE) */ + ALT_SDMMC_INT_STATUS_SDIO_0 = (1UL << 16), /*!< SDIO Interrupt Card 0 - only one card supported */ + + ALT_SDMMC_INT_STATUS_ALL = 0x1FFFF /*!< All previous status types*/ +} ALT_SDMMC_INT_STATUS_t; + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_SDMMC_CARD_INTFC Card Interface + * + * The clock control block provides different clock frequencies required for + * SD/MMC/CE-ATA cards. The clock control block has one clock divider, which is + * used to generate different card clock frequencies. + * + * The clock divider is used to generate different clock frequencies required for + * the cards. The division factor for the clock divider can be set by calling the + * alt_sdmmc_card_clk_div_set() function. The clock divider is an 8-bit value that + * provides a clock division factor from 1 to 510; a value of 0 represents a + * clock-divider bypass, a value of 1 represents a divide by 2, a value of 2 + * represents a divide by 4, and so on. + * + * @{ + */ + +/*! + * This type enumerates the SDMMC evailable bus width. + */ +typedef enum ALT_SDMMC_BUS_WIDTH_e +{ + ALT_SDMMC_BUS_WIDTH_1 = 1, + ALT_SDMMC_BUS_WIDTH_4 = 4, + ALT_SDMMC_BUS_WIDTH_8 = 8 +}ALT_SDMMC_BUS_WIDTH_t; + +/*! + * This type defines a structure for configuration of miscellaneous interface + * parameters for an attached card. + */ +typedef struct ALT_SDMMC_CARD_MISC_s +{ + uint32_t response_timeout; /*!< Card response timeout period in + * sdmmc_cclk_out (SD/MMC card clock) ticks. + */ + uint32_t data_timeout; /*!< Card data read timeout period in + * sdmmc_cclk_out (SD/MMC card clock) ticks. + */ + ALT_SDMMC_BUS_WIDTH_t card_width; /*!< Indicates card interface width (1, 4, or + * 8 bits). + */ + uint32_t block_size; /*!< The card block size in bytes. */ + uint32_t debounce_count; /*!< Number of host clock (l4_mp_clk) ticks + * used to debounce card interface signals. + */ +} ALT_SDMMC_CARD_MISC_t; + +/*! + * Get the current card interface configuration values for the miscellaneous set + * of parameters. + * + * \param card_misc_cfg + * [out] Pointer to a \ref ALT_SDMMC_CARD_MISC_t structure to hold + * the returned card interface parameters. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_card_misc_get(ALT_SDMMC_CARD_MISC_t *card_misc_cfg); + +/*! + * Set the specified card interface configuration for the miscellaneous set of + * parameters. + * + * \param card_misc_cfg + * Pointer to a \ref ALT_SDMMC_CARD_MISC_t structure holding the card + * interface parameters to configure. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_card_misc_set(const ALT_SDMMC_CARD_MISC_t *card_misc_cfg); + +/*! + * Set the bus width appropriate supported by the card, send this parameter to the card. + * + * \param width + * Indicates card interface width. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_card_bus_width_set(const ALT_SDMMC_BUS_WIDTH_t width); + +/*! + * Send block size to the card. + * + * \param block_size + * The card block size in bytes. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_card_block_size_set(const uint16_t block_size); + +/*! + * Detects and identifies any connected card. + * + * Detects any connected card (only one connected card is possible in this + * implementation) and returns the device identity and properties. + * + * \param card_info + * [out] A pointer to a ALT_SDMMC_CARD_INFO_t structure to hold + * identification and device property information for any detected + * card. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_card_identify(ALT_SDMMC_CARD_INFO_t *card_info); + +/*! + * Gets the configured card clock divider value (\b sdmmc_cclk_out). + * + * Returns the card clock divider value. Clock division is a 2 * n value. For + * example, a value of 0 means divide by 2 * 0 = 0 (no division, effectively a + * bypass), a value of 1 means divide by 2 * 1 = 2, value of 0xff means divide by 2 + * * 255 = 510. Valid range is 0 to 255. + * + * \returns The clock divider value. + */ +uint32_t alt_sdmmc_card_clk_div_get(void); + +/*! + * Sets the card clock divider configuration (\b sdmmc_cclk_out). + * + * \param clk_div + * Clock divider value. Clock division is 2 * n. For example, a value + * of 0 means divide by 2 * 0 = 0 (no division, effectively a bypass), + * a value of 1 means divide by 2 * 1 = 2, value of 0xff means divide + * by 2 * 255 = 510. Valid range is 0 to 255. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * + * \internal + * The card clock must be diesabled before changing the clk_div value. + * \endinternal + */ +ALT_STATUS_CODE alt_sdmmc_card_clk_div_set(const uint32_t clk_div); + +/*! + * Gets the configured card data transfer rate in bit/s. The units is + * compatible with ALT_SDMMC_CARD_INFO_t::tran_speed. + * + * \returns The data transfer rate in bit/s. + */ +uint32_t alt_sdmmc_card_speed_get(void); + +/*! + * Sets the card data transfer rate. The units is compatible with + * ALT_SDMMC_CARD_INFO_t::tran_speed. + * + * \param Desired data transfer rate in bit/s. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_sdmmc_card_speed_set(uint32_t xfer_speed); + +/*! + * Disables the card clock (\b sdmmc_cclk_out). + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_sdmmc_card_clk_disable(void); + +/*! + * Enables the card clock (\b sdmmc_cclk_out). + * + * \param use_low_pwr_mode + * If true then low-power mode is enabled to save card power, the \b + * sdmmc_cclk_out signal is disabled when the card is idle for at + * least eight card clock cycles. Low-power mode is enabled when a + * new command is loaded and the command path goes to a non-idle + * state. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_sdmmc_card_clk_enable(const bool use_low_pwr_mode); + +/*! + * Returns true if the card clock (\b sdmmc_cclk_out) is enabled otherwise returns + * false. + * + * \retval true The card clock is enabled. + * \retval false The card clock is not enabled. + */ +bool alt_sdmmc_card_clk_is_enabled(void); + +/*! + * Reset the card device. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * + * \internal + * NOT IMPLEMENTED + * The SD/MMC controller does not contain a reset output as part of the external + * card interface. To reset the flash card device, consider using a general + * purpose output pin. + * \endinternal + */ +ALT_STATUS_CODE alt_sdmmc_card_reset(void); + +/*! + * Returns true if a card presence is detected otherwise returns false. + * + * \retval true A card is present. + * \retval false A card is not present. + * + * \internal + * \endinternal + */ +bool alt_sdmmc_card_is_detected(void); + +/*! + * Returns true if card write protection is enabled otherwise returns false. + * + * \retval true Card is write protected. + * \retval false Card is not write protected. + * + * \internal + * \endinternal + */ +bool alt_sdmmc_card_is_write_protected(void); + +/*! + * Returns true if power is on (enabled) to the card otherwise returns false. + * + * \retval true Card power is on (enabled). + * \retval false Card power is off (disabled). + * + * \internal + * pwren + * \endinternal + */ +bool alt_sdmmc_card_pwr_is_on(void); + +/*! + * Enable (turn on) power to the card device. + * + * This function enables power to the card device allowing for power ramp-up time + * before returning. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_card_pwr_on(void); + +/*! + * Disable (turn off) power to the card device. + * + * This function disables power to the card device. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_card_pwr_off(void); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_SDMMC_DMA SD/MMC Controller Internal DMA + * + * The internal DMA controller has a control and status register interface and a + * single transmit or receive engine, which transfers data from system memory to + * the card and vice versa. The controller uses a descriptor mechanism to + * efficiently move data from source to destination with minimal host processor + * intervention. You can set up the controller to interrupt the host processor in + * situations such as transmit and receive data transfer completion from the card, + * as well as other normal or error conditions. The DMA controller and the host + * driver communicate through a single data structure. + * + * The internal DMA controller transfers the data received from the card to the + * data buffer in the system memory, and transfers transmit data from the data + * buffer in the memory to the controller's FIFO buffer. Descriptors that reside + * in the system memory act as pointers to these buffers. + * + * A data buffer resides in the physical memory space of the system memory and + * consists of complete or partial data. The buffer status is maintained in the + * descriptor. Data chaining refers to data that spans multiple data + * buffers. However, a single descriptor cannot span multiple data buffers. + * + * A single descriptor is used for both reception and transmission. The base + * address of the list is written into the descriptor list base address + * register. A descriptor list is forward linked. The last descriptor can point + * back to the first entry to create a ring structure. The descriptor list resides + * in the physical memory address space of the host. Each descriptor can point to + * a maximum of two data buffers. + * + * @{ + */ + +/*! + * This type definition enumerates the interrupt status conditions from the + * SD/MMC internal DMA controller that contribute to the \b + * ALT_INT_INTERRUPT_SDMMC_IRQ signal state. + * + * NOTE: Both the general purpose interrupt status conditions for the SD/MMC + * controller (\ref ALT_SDMMC_INT_STATUS_t) and the interrupt status conditions + * for the internal DMA controller (\ref ALT_SDMMC_DMA_INT_STATUS_t) contribute to + * the overall \b ALT_INT_INTERRUPT_SDMMC_IRQ signal state + */ +typedef enum ALT_SDMMC_DMA_INT_STATUS_e +{ + ALT_SDMMC_DMA_INT_STATUS_TI = (1UL << 0), /*!< Transmit Interrupt Enable */ + ALT_SDMMC_DMA_INT_STATUS_RI = (1UL << 1), /*!< Receive Interrupt Enable */ + ALT_SDMMC_DMA_INT_STATUS_FBE = (1UL << 2), /*!< Fatal Bus Error */ + ALT_SDMMC_DMA_INT_STATUS_DU = (1UL << 4), /*!< Descriptor Unavailable Interrupt */ + ALT_SDMMC_DMA_INT_STATUS_CES = (1UL << 5), /*!< Card Error Summary Interrupt Enable */ + ALT_SDMMC_DMA_INT_STATUS_NI = (1UL << 8), /*!< Normal Interrupt Summary Enable */ + ALT_SDMMC_DMA_INT_STATUS_AI = (1UL << 9), /*!< Abnormal Interrupt Summary Enable. */ + + ALT_SDMMC_DMA_INT_STATUS_ALL = 0x337, +} ALT_SDMMC_DMA_INT_STATUS_t; + +/*! + * This type defines the SD/MMC controller internal DMA controller descriptor + * structure. + * + * The internal DMA controller uses these types of descriptor structures: + * * Dual-buffer structure - The distance between two descriptors is determined + * by the skip length value written to the descriptor skip length field + * of the bus mode register. + * * Chain structure - Each descriptor points to a unique buffer, and to the next + * descriptor in a linked list. + */ +typedef struct ALT_SDMMC_DMA_BUF_DESC_s +{ + /*! The DES0 field in the internal DMA controller descriptor contains control and + * status information. + */ + union DES0 + { + /*! Structure for DES0 register data fields. */ + struct + { + uint32_t : 1; /*!< Reserved */ + uint32_t dic : 1; /*!< Disable Interrupt on Completion + * (DIC). When set to 1, this bit + * prevents the setting of the + * TI/RI bit of the internal DMA + * controller status register + * (idsts) for the data that ends + * in the buffer pointed to by + * this descriptor. + */ + uint32_t ld : 1; /*!< Last Descriptor (LD). When set + * to 1, this bit indicates that + * the buffers pointed to by this + * descriptor are the last buffers + * of the data. + */ + uint32_t fs : 1; /*!< First Descriptor (FS). When set + * to 1, this bit indicates that + * this descriptor contains the + * first buffer of the data. If + * the size of the first buffer is + * 0, next descriptor contains the + * beginning of the data. + */ + uint32_t ch : 1; /*!< Second Address Chained + * (CH). When set to 1, this bit + * indicates that the second + * address in the descriptor is + * the next descriptor address + * rather than the second buffer + * address. When this bit is set + * to 1, BS2 (DES1[25:13]) must be + * all zeros. + */ + uint32_t er : 1; /*!< End of Ring (ER). When set to + * 1, this bit indicates that the + * descriptor list reached its + * final descriptor. The internal + * DMA controller returns to the + * base address of the list, + * creating a descriptor ring. ER + * is meaningful for only a + * dual-buffer descriptor + * structure. + */ + uint32_t ces : 1; /*!< Card Error Summary (CES). The + * CES bit indicates whether a + * transaction error occurred. The + * CES bit is the logical OR of + * the following error bits in the + * rintsts register. + * * End-bit error (ebe) + * * Response timeout (rto) + * * Response CRC (rcrc) + * * Start-bit error (sbe) + * * Data read timeout (drto) + * * Data CRC for receive (dcrc) + * * Response error (re) + */ + uint32_t : 24; /*!< Reserved */ + uint32_t own : 1; /*!< When set to 1, this bit + * indicates that the descriptor + * is owned by the internal DMA + * controller. When this bit is + * set to 0, it indicates that the + * descriptor is owned by the + * host. The internal DMA + * controller resets this bit to 0 + * when it completes the data + * transfer. + */ + } fld; /*!< Union data member access to + * DES0 fields. + */ + uint32_t raw; /*!< The DES0 raw register aggregate + * value. + */ + } des0; /*!< The DES0 field in the internal + * DMA controller descriptor + * contains control and status + * information. + */ + /*! The DES1 descriptor field contains the buffer size. */ + union DES1 + { + /*! Structure for DES1 register data fields. */ + struct + { + uint32_t bs1 : 13; /*!< Buffer 1 Size (BS1). Indicates + * the data buffer byte size, + * which must be a multiple of + * four bytes. When the buffer + * size is not a multiple of four, + * the resulting behavior is + * undefined. If this field is 0, + * the DMA ignores the buffer and + * proceeds to the next descriptor + * for a chain structure, or to + * the next buffer for a + * dual-buffer structure. If there + * is only one descriptor and only + * one buffer to be programmed, + * you need to use only buffer 1 + * and not buffer 2. + */ + uint32_t bs2 : 13; /*!< Buffer 2 Size (BS2). These bits + * indicate the second data buffer + * byte size. The buffer size must + * be a multiple of four. When the + * buffer size is not a multiple + * of four, the resulting behavior + * is undefined. This field is not + * valid if DES0[4] is set to 1. + */ + uint32_t : 6; /*!< Reserved */ + + } fld; /*!< Union data member access to + * DES1 fields. + */ + uint32_t raw; /*!< The DES1 raw register aggregate + * value. + */ + } des1; /*!< The DES1 descriptor field + * contains the buffer size. + */ + /*! The DES2 descriptor field contains the address pointer to the data buffer. */ + union DES2 + { + /*! Structure for DES2 register data fields. */ + struct + { + uint32_t bap1 : 32; /*!< Buffer Address Pointer 1 + * (BAP1). These bits indicate the + * physical address of the first + * data buffer. The internal DMA + * controller ignores DES2 [1:0], + * because it only performs + * 32-bit-aligned accesses. + */ + } fld; /*!< Union data member access to + * DES2 fields. + */ + uint32_t raw; /*!< The DES2 raw register aggregate + * value. + */ + } des2; /*!< The DES2 descriptor field + * contains the address pointer to + * the data buffer. + */ + /*! The DES3 descriptor field contains the address pointer to the next descriptor + * if the present descriptor is not the last descriptor in a chained descriptor + * structure or the second buffer address for a dual-buffer structure. + */ + union DES3 + { + /*! Structure for DES3 register data fields. */ + struct + { + uint32_t bap2_or_next : 32; /*!< Buffer Address Pointer 2 (BAP2) + * or Next Descriptor + * Address. These bits indicate + * the physical address of the + * second buffer when the + * dual-buffer structure is + * used. If the Second Address + * Chained (DES0[4]) bit is set to + * 1, this address contains the + * pointer to the physical memory + * where the next descriptor is + * present. If this is not the + * last descriptor, the next + * descriptor address pointer must + * be aligned to 32 bits. Bits 1 + * and 0 are ignored. + */ + } fld; /*!< Union data member access to + * DES3 fields. + */ + uint32_t raw; /*!< The DES3 raw register aggregate + * value. + */ + } des3; /*!< The DES3 descriptor field + * contains the address pointer to + * the next descriptor if the + * present descriptor is not the + * last descriptor in a chained + * descriptor structure or the + * second buffer address for a + * dual-buffer structure. + */ + +} ALT_SDMMC_DMA_BUF_DESC_t; + +/*! + * Resets the SD/MMC internal DMA controller. + * + * This function resets the SD/MMC controller DMA interface control logic and all + * internal registers of the DMA controller. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * + * \internal + * ctrl.dma_reset + * bmod.swr + * What's the difference if the effect of these two controls? + * \endinternal + */ +ALT_STATUS_CODE alt_sdmmc_dma_reset(void); + +/*! + * Disables use of the SD/MMC controller internal DMA for data transfers. + * + * This function disables use of the SD/MMC controller internal DMA for data + * transfers and requires the host to conduct data transfers through the slave + * interface. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * + * \internal + * ctrl.use_internal_dmac + * bmod.de + * What's the difference if the effect of these two controls? + * \endinternal + */ +ALT_STATUS_CODE alt_sdmmc_dma_disable(void); + +/*! + * Enables use of the SD/MMC controller internal DMA for data transfers. + * + * This function enables use of the SD/MMC controller internal DMA for data + * transfers, otherwise the host must conduct data transfers through the slave + * interface. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * + * \internal + * ctrl.use_internal_dmac + * bmod.de + * What's the difference if the effect of these two controls? + * \endinternal + */ +ALT_STATUS_CODE alt_sdmmc_dma_enable(void); + +/*! + * This type enumerates the host bus programmable burst length options + * available to the SD/MMC internal DMA controller. + */ +typedef enum ALT_SDMMC_DMA_PBL_e +{ + ALT_SDMMC_DMA_PBL_1 = 0x0, /*!< 1 transfer unit */ + ALT_SDMMC_DMA_PBL_4 = 0x1, /*!< 4 transfer units */ + ALT_SDMMC_DMA_PBL_8 = 0x2, /*!< 8 transfer units */ + ALT_SDMMC_DMA_PBL_16 = 0x3, /*!< 16 transfer units */ + ALT_SDMMC_DMA_PBL_32 = 0x4, /*!< 32 transfer units */ + ALT_SDMMC_DMA_PBL_64 = 0x5, /*!< 64 transfer units */ + ALT_SDMMC_DMA_PBL_128 = 0x6, /*!< 128 transfer units */ + ALT_SDMMC_DMA_PBL_256 = 0x7, /*!< 256 transfer units */ + +} ALT_SDMMC_DMA_PBL_t; + +/*! + * Starts the SD/MMC internal DMA transfer with the specified + * descriptor an bus mode transfer configuration. + * + * \param buf_desc_list + * Pointer to the beginning of a SD/MMC internal DMA buffer + * descriptor list. + * + * \param desc_skip_len + * Descriptor Skip Length. Specifies the number of + * half/full/double words (depending on 16/32/64-bit bus) + * to skip between two unchained descriptors. Only + * applicable for dual buffer structures otherwise + * ignored. + * + * \param burst_len + * Programmable Burst Length. Specifies the maximum + * number of beats to be performed in one DMA + * transaction. The DMA will always attempt to burst as + * specified each time it starts a burst transfer on the + * host bus. + * + * \param use_fixed_burst + * Fixed Burst. Controls whether the AHB Master interface + * performs fixed burst transfers or not. When set, the + * AHB will use only SINGLE, INCR4, INCR8 or INCR16 + * during start of normal burst transfers. When reset, + * the AHB will use SINGLE and INCR burst transfer + * operations. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_dma_start(ALT_SDMMC_DMA_BUF_DESC_t *buf_desc_list, + const uint32_t desc_skip_len, + const ALT_SDMMC_DMA_PBL_t burst_len, + const bool use_fixed_burst); + +/*! + * Sets any value for the IDMAC FSM to resume normal descriptor + * fetch operation. + * + * \param value + * This value will write for the IDMAC FSM. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_sdmmc_poll_demand_set(const uint32_t value); + +/*! + * Returns the SD/MMC internal DMA controller status register value which + * reflects current DMA interrupt status conditions. + * + * \returns The value of the SD/MMC internal DMA status register which + * reflects the current SD/MMC internal DMA interrupt status + * conditions. + */ +uint32_t alt_sdmmc_dma_int_status_get(void); + +/*! + * Returns the SD/MMC internal DMA controller interrupt mask value which + * reflects the enabled internal DMA controller interrupt status conditions. + * + * \returns The aggregate value of the enabled SD/MMC internal DMA + * controller interrupt status conditions. A set (1) bit in the + * corresponding ALT_SDMMC_DMA_INT_STATUS_t position indicates an + * interrupt that is enabled. A clear (0) bit the corresponding + * ALT_SDMMC_DMA_INT_STATUS_t position indicates an interrupt that + * is masked. + */ +uint32_t alt_sdmmc_dma_int_mask_get(void); + +/*! + * Clears the specified SD/MMC internal DMA controller interrupt status + * conditions identified in the mask. + * + * This function clears one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_SDMMC_IRQ interrupt signal state. + * + * \param mask + * Specifies the SD/MMC internal DMA controller status conditions + * to clear. \e mask is a mask of logically OR'ed \ref + * ALT_SDMMC_DMA_INT_STATUS_t values that designate the status + * conditions to clear. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_sdmmc_dma_int_clear(const uint32_t mask); + +/*! + * Disable the specified SD/MMC internal DMA controller interrupt status + * conditions identified in the mask. + * + * This function disables one or more of the status conditions as contributors + * to the \b ALT_INT_INTERRUPT_SDMMC_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b + * ALT_INT_INTERRUPT_SDMMC_IRQ interrupt signal state. The function + * alt_sdmmc_dma_int_enable() is used to enable status source conditions. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_SDMMC_DMA_INT_STATUS_t values that designate the status + * conditions to disable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_sdmmc_dma_int_disable(const uint32_t mask); + +/*! + * Enable the specified SD/MMC internal DMA controller interrupt status conditions + * identified in the mask. + * + * This function enables one or more of the status conditions as contributors to + * the \b ALT_INT_INTERRUPT_SDMMC_IRQ interrupt signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b + * ALT_INT_INTERRUPT_SDMMC_IRQ interrupt signal state. The function + * alt_sdmmc_dma_int_disable() is used to disable status source conditions. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_SDMMC_DMA_INT_STATUS_t values that designate the status + * conditions to enable. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_sdmmc_dma_int_enable(const uint32_t mask); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_SDMMC_FIFO SD/MMC Controller FIFO + * + * + * @{ + */ + +/*! + * The number of entries (depth) of the SDMMC controller FIFO. + */ +#define ALT_SDMMC_FIFO_NUM_ENTRIES 1024 + +/*! + * Resets the SD/MMC controller FIFO. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * + * \internal + * ctrl.fifo_reset - write 1 to reset FIFO + * \endinternal + */ +ALT_STATUS_CODE alt_sdmmc_fifo_reset(void); + +/*! + * This type enumerates the burst size of multiple transaction + * available to the SD/MMC internal DMA controller. + */ +typedef enum ALT_SDMMC_MULT_TRANS_e +{ + ALT_SDMMC_MULT_TRANS_TXMSIZE1 = 0x0, /*!< Msize 1 and TX_WMARK 1-1023 */ + ALT_SDMMC_MULT_TRANS_TXMSIZE4 = 0x1, /*!< Msize 1 and TX_WMARK 1-1023 */ + ALT_SDMMC_MULT_TRANS_TXMSIZEK8 = 0x2, /*!< Msize 4 and TX_WMARK 256 */ + ALT_SDMMC_MULT_TRANS_TXMSIZEK16 = 0x3, /*!< Msize 16 and TX_WMARK 64 */ + ALT_SDMMC_MULT_TRANS_RXMSIZEK1 = 0x5, /*!< Msize 1 and RX_WMARK 512 */ + ALT_SDMMC_MULT_TRANS_RXMSIZEK4 = 0x6, /*!< Msize 1 and RX_WMARK 512 */ + ALT_SDMMC_MULT_TRANS_RXMSIZE8 = 0x7, /*!< Msize 8 and RX_WMARK 64 */ +} ALT_SDMMC_MULT_TRANS_t; + +/*! + * Gets the configured FIFO operational parameter values. + * + * This function returns the FIFO configuration parameter set for the receive and + * transmit watermark threshold values and the DMA multiple transaction size. + * + * \param rx_wtrmk + * [out] FIFO threshold watermark value when receiving data to card. + * + * \param tx_wtrmk + * [out] FIFO threshold watermark value when transmitting data to card. + * + * \param mult_trans_size + * [out] Burst size of multiple transaction. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ + +ALT_STATUS_CODE alt_sdmmc_fifo_param_get(uint32_t *rx_wtrmk, uint32_t *tx_wtrmk, + ALT_SDMMC_MULT_TRANS_t *mult_trans_size); + +/*! + * Sets the configured FIFO operational parameter values. + * + * This function sets the FIFO configuration parameter for the receive and + * transmit watermark threshold values and the DMA multiple transaction size. + * + * \param rx_wtrmk + * FIFO threshold watermark value when receiving data to card. + * + * \param tx_wtrmk + * FIFO threshold watermark value when transmitting data to card. + * + * \param mult_trans_size + * Burst size of multiple transaction. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_sdmmc_fifo_param_set(uint32_t rx_wtrmk, uint32_t tx_wtrmk, ALT_SDMMC_MULT_TRANS_t mult_trans_size); + +/*! + * Returns true if SD/MMC controller FIFO has reached the receive watermark level + * otherwise returns false. + * + * \retval true The FIFO has reached the receive watermark level. + * \retval false The FIFO has not reached the receive watermark level. + * + * \internal + * \endinternal + */ +bool alt_sdmmc_fifo_is_rx_wtrmk_reached(void); + +/*! + * Returns true if SD/MMC controller FIFO has reached the transmit watermark level + * otherwise returns false. + * + * \retval true The FIFO has reached the transmit watermark level. + * \retval false The FIFO has not reached the transmit watermark level. + * + * \internal + * \endinternal + */ +bool alt_sdmmc_fifo_is_tx_wtrmk_reached(void); + +/*! + * Returns true if SD/MMC controller FIFO is empty otherwise returns false. + * + * \retval true The FIFO is empty. + * \retval false The FIFO is not empty. + * + * \internal + * \endinternal + */ +bool alt_sdmmc_fifo_is_empty(void); + +/*! + * Returns true if SD/MMC controller FIFO is full otherwise returns false. + * + * \retval true The FIFO is full. + * \retval false The FIFO is not full. + * + * \internal + * \endinternal + */ +bool alt_sdmmc_fifo_is_full(void); + +/*! + * Returns the number of filled FIFO locations. + * + * \returns The number of filled FIFO locations. + */ +int32_t alt_sdmmc_fifo_count(void); + +/*! + * Read data from the SD/MMC controller FIFO. + * + * Reads the requested number of bytes (rounded up to nearest whole 32-bit word) + * from the FIFO. The function returns when the requested number of bytes has been + * read from the FIFO or if an error occurs. + * + * \param dest + * A pointer to a user supplied destination buffer for the data read + * from the FIFO. The buffer must be as large the requested number of + * bytes rounded up to the nearest 32-bit word size. + * + * \param size + * The requested number of bytes to read from the FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_fifo_read(void *dest, const size_t size); + +/*! + * Writes data to the SD/MMC controller FIFO. + * + * Writes the requested number of bytes (rounded up to nearest whole 32-bit word) + * to the FIFO. The function returns when the requested number of bytes has been + * written to the FIFO or if an error occurs. + * + * \param src + * A pointer to + * A pointer to the source buffer containing the data to be written to the + * FIFO. The buffer must be as large the requested number of + * bytes rounded up to the nearest 32-bit word size. + * + * \param size + * The number of bytes to write to the FIFO. If size is not a + * multiple of 4 then the number of bytes is rounded up to the next + * 32-but word size and the byte difference padded with zeroes. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + */ +ALT_STATUS_CODE alt_sdmmc_fifo_write(const void *src, const size_t size); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_SDMMC_BLKIO General Purpose Block I/O + * + * The functions in this group provide general purpose block read and write flash + * functions. + * + * @{ + */ + +/*! + * Reads a block of data from the SD/MMC flash card. + * + * Reads a block of \e size data bytes from the SD/MMC flash \e src address into the + * user supplied \e dest buffer. + * + * \param dest + * The address of a caller supplied destination buffer in system + * memory large enough to contain the requested block of flash data. + * + * \param src + * The flash memory address to begin reading data from. + * + * \param size + * The requested number of data bytes to read from the flash device. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_sdmmc_read(void *dest, void *src, const size_t size); + +/*! + * Write a block of data to the SD/MMC flash card. + * + * Writes a block of \e size data bytes to the SD/MMC flash \e dest address from the + * designated \e src buffer. The actual number of bytes written to the flash card is + * \e size bytes rounded up to the next whole multiple flash card block size. That + * is: + * \e actual_bytes_written = ((\e size / \e flash_block_size) + 1) * \e flash_block_size + * + * + * \param dest + * The destination flash memory address to begin writing data to. + * + * \param src + * The source address in system memory to begin writing data from. + * + * \param size + * The requested number of data bytes to write to the flash device. + * + * \retval ALT_E_SUCCESS Indicates successful completion. + * \retval ALT_E_ERROR Indicates an error occurred. + */ +ALT_STATUS_CODE alt_sdmmc_write(void *dest, void *src, const size_t size); + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_SDMMC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_spi.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_spi.h new file mode 100644 index 000000000..4f5463010 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_spi.h @@ -0,0 +1,1847 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +/*! \file + * Altera - SPI Flash Controller Module + */ + +#ifndef __ALT_SPI_H__ +#define __ALT_SPI_H__ + +#include "hwlib.h" +#include "alt_clock_manager.h" +#include "socal/alt_spis.h" +#include "socal/alt_spim.h" +#include "socal/alt_sysmgr.h" +#include "socal/hps.h" +#include "socal/socal.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup ALT_SPI SPI Flash Controller Module + * + * This module defines an API for configuring and managing the HPS serial + * peripheral interface (SPI) master and slave controller instances. + * + * The hard processor system (HPS) provides two SPI masters and two SPI + * slaves. The SPI masters and slaves are instances of the Synopsys DesignWare + * Synchronous Serial Interface (SSI) controller. + * + * @{ + */ + +/*! + * This type enumerates the HPS SPI controller instances. + */ +typedef enum ALT_SPI_CTLR_e +{ + ALT_SPI_SPIS0 = (int32_t)ALT_SPIS0_OFST, /*!< SPI Slave Controller 0 instance */ + ALT_SPI_SPIS1 = (int32_t)ALT_SPIS1_OFST, /*!< SPI Slave Controller 1 instance */ + ALT_SPI_SPIM0 = (int32_t)ALT_SPIM0_OFST, /*!< SPI Master Controller 0 instance */ + ALT_SPI_SPIM1 = (int32_t)ALT_SPIM1_OFST /*!< SPI Master Controller 1 instance */ +} ALT_SPI_CTLR_t; + +/*! + * This type enumerates the serial protocol frame formats supported by the SPI + * controller. + * + * See: Functional Description of the SPI Controller section of + * Chapter 19. SPI Controller in the Cyclone V Device Handbook + * Volume 3: Hard Processor System Technical Reference Manual for a full + * description of the supported protocols. + */ +typedef enum ALT_SPI_FRF_e +{ + ALT_SPI_FRF_SPI = 0, /*!< Motorola SPI protocol - A four-wire, full-duplex + * serial protocol from Motorola. + */ + ALT_SPI_FRF_SSP = 1, /*!< Texas Instruments Serial Protocol (SSP) - A + * four-wire, full-duplex serial protocol. + */ + ALT_SPI_FRF_MICROWIRE = 2 /*!< National Semiconductor Microwire - A half-duplex + * serial protocol, which uses a control word + * transmitted from the serial master to the target + * serial slave. + */ +} ALT_SPI_FRF_t; + +/*! + * This type enumerates the SPI serial clock polarity choices. Only valid when the + * frame format is set to Motorola SPI. Used to select the polarity of the + * inactive serial clock, which is held inactive when the SPI controller master is + * not actively transferring data on the serial bus. + */ +typedef enum ALT_SPI_SCPOL_e +{ + ALT_SPI_SCPOL_INACTIVE_LOW = 0, /*!< Inactive state of serial clock is low */ + ALT_SPI_SCPOL_INACTIVE_HIGH = 1 /*!< Inactive state of serial clock is high */ +} ALT_SPI_SCPOL_t; + +/*! + * This type enumerates the SPI serial clock phase choices. Only valid when the + * frame format is set to Motorola SPI. The serial clock phase selects the + * relationship of the serial clock with the slave select signal. When + * ALT_SPI_SCPH_TOGGLE_MIDDLE, data are captured on the first edge of the serial + * clock. When ALT_SPI_SCPH_TOGGLE_START, the serial clock starts toggling one + * cycle after the slave select line is activated, and data are captured on the + * second edge of the serial clock. + */ +typedef enum ALT_SPI_SCPH_e +{ + ALT_SPI_SCPH_TOGGLE_MIDDLE = 0, /*!< Serial clock toggles in middle of first data bit. */ + ALT_SPI_SCPH_TOGGLE_START = 1 /*!< Serial clock toggles at start of first data bit. */ +} ALT_SPI_SCPH_t; + +/*! + * This type enumerates the SPI available frame size. Specifies the frame size of + * transfer for serial communication. + */ +typedef enum ALT_SPI_DFS_e +{ + ALT_SPI_DFS_4BIT = 3, /*!< 4-bit serial data transfer */ + ALT_SPI_DFS_5BIT = 4, /*!< 5-bit serial data transfer */ + ALT_SPI_DFS_6BIT = 5, /*!< 6-bit serial data transfer */ + ALT_SPI_DFS_7BIT = 6, /*!< 7-bit serial data transfer */ + ALT_SPI_DFS_8BIT = 7, /*!< 8-bit serial data transfer */ + ALT_SPI_DFS_9BIT = 8, /*!< 9-bit serial data transfer */ + ALT_SPI_DFS_10BIT = 9, /*!< 10-bit serial data transfer */ + ALT_SPI_DFS_11BIT = 10, /*!< 11-bit serial data transfer */ + ALT_SPI_DFS_12BIT = 11, /*!< 12-bit serial data transfer */ + ALT_SPI_DFS_13BIT = 12, /*!< 13-bit serial data transfer */ + ALT_SPI_DFS_14BIT = 13, /*!< 14-bit serial data transfer */ + ALT_SPI_DFS_15BIT = 14, /*!< 15-bit serial data transfer */ + ALT_SPI_DFS_16BIT = 15 /*!< 16-bit serial data transfer */ +} ALT_SPI_DFS_t; + +/*! + * This type enumerates the SPI transfer mode choices. Specifies the mode of + * transfer for serial communication. + */ +typedef enum ALT_SPI_TMOD_e +{ + ALT_SPI_TMOD_TXRX = 0, /*!< Transmit & Receive */ + ALT_SPI_TMOD_TX = 1, /*!< Transmit Only */ + ALT_SPI_TMOD_RX = 2, /*!< Receive Only */ + ALT_SPI_TMOD_EEPROM = 3, /*!< EEPROM Read */ +} ALT_SPI_TMOD_t; + +/*! + * This type enumerates the HPS SPI controller type mode. + */ +typedef enum ALT_SPI_OP_MODE_e +{ + ALT_SPI_OP_MODE_SLAVE = 0, /*!< SPI Slave Controller */ + ALT_SPI_OP_MODE_MASTER = 1 /*!< SPI Master Controller */ +} ALT_SPI_OP_MODE_t; + +/* + * A pointer or handle to the SPI controller device instance. The ALT_SPI_DEV_t is + * initialized by a call to alt_spi_init() and subsequently used by the other SPI + * controller API functions as a reference to a specific device. + * + * \internal + * ALT_SPI_DEV_t may be a struct or reference to an opaque data + * structure. Whatever "internal" type is suited to the needs of the + * implementation. + * \endinternal + */ +typedef struct ALT_SPI_DEV_s +{ + void * location; + /*!< HPS address of spi instance*/ + alt_freq_t clock_freq; + /*!< Input clock frequency. */ + uint32_t last_slave_mask; + /*!< Last issued slave mask. */ + uint32_t last_transfer_mode; + /*!< Last transfer mode. */ + ALT_SPI_OP_MODE_t op_mode; + /*!< HPS SPI operation mode*/ +} ALT_SPI_DEV_t; + +/*! + * This type defines a structure for specifying configuration parameters for a SPI + * controller. + */ +typedef struct ALT_SPI_CONFIG_s +{ + ALT_SPI_DFS_t frame_size; + /*!< Data Frame Size. Selects the data + * frame length. When the data frame size is + * programmed to be less than 16 bits, the + * receive data are automatically + * right-justified by the receive logic, + * with the upper bits of the receive FIFO + * zero-padded. You must right-justify + * transmit data before writing into the + * transmit FIFO. The transmit logic ignores + * the upper unused bits when transmitting + * the data. Valid range 4..16. + */ + ALT_SPI_FRF_t frame_format; + /*!< Frame Format. Selects which serial + * protocol transfers the data. + */ + ALT_SPI_SCPH_t clk_phase; + /*!< Serial Clock Phase. Valid when the frame + * format (FRF) is set to Motorola SPI. The + * serial clock phase selects the + * relationship of the serial clock with the + * slave select signal. + */ + ALT_SPI_SCPOL_t clk_polarity; + /*!< Serial Clock Polarity. Only valid when + * the frame format (FRF) is set to Motorola + * SPI. Used to select the polarity of the + * inactive serial clock. + */ + ALT_SPI_TMOD_t transfer_mode; + /*!< Transfer Mode. Selects the mode of + * transfer for serial communication. + */ + bool slave_output_enable; + /*!< Slave Output Enable. Relevant only for + * SPI controller slaves. This data member + * has no applicability for SPI controller + * masters. This data member specifies + * whether the \b ssi_oe_n output is enabled + * or disabled from the SPI controller + * slave. When \b true, the \b ssi_oe_n + * output can never be active. When the \b + * ssi_oe_n output controls the tri-state + * buffer on the \b txd output from the + * slave, a high impedance state is always + * present on the slave \b txd output when + * \e slv_oe = \b true. This is useful when + * the master transmits in broadcast mode. + * Only one slave may respond with data on + * the master \b rxd line. This data member + * is enabled after reset and must be + * disabled by software (when broadcast mode + * is used), if you do not want this device + * to respond with data. + */ + bool loopback_mode; + /*!< Used for testing purposes only. When \b + * true, creates an internal loopback by + * connecting the transmit shift register + * output to the receive shift register + * input. Can be used in both serial- slave + * and serial-master modes. For SPI + * controller slaves in loopback mode, the + * \b ss_in_n and \b ssi_clk signals must be + * provided by an external source. In this + * mode, the slave cannot generate these + * signals because there is nothing to which + * to loop back. For normal operation this + * data member should be set to \b false. + */ +} ALT_SPI_CONFIG_t; + +/*! + * This type enumerates the Microwire transfer mode choices. Specifies whether the + * Microwire transfer is sequential or non-sequential. When sequential mode is + * used, only one control word is needed to transmit or receive a block of data + * words. When non-sequential mode is used, there must be a control word for each + * data word that is transmitted or received. + */ +typedef enum ALT_SPI_MW_MODE_e +{ + ALT_SPI_MW_NON_SEQUENTIAL = 0, /*!< Non-Sequential Transfer */ + ALT_SPI_MW_SEQUENTIAL = 1 /*!< Sequential Transfer */ +} ALT_SPI_MW_MODE_t; + +/*! + * This type enumerates the slave select output lines for SPI controller modules + * configured as masters. + */ +typedef enum ALT_SPI_SS_e +{ + ALT_SPI_SS0 = 1UL << 0, /*!< Slave select 0 output \b ss_0_n */ + ALT_SPI_SS1 = 1UL << 1, /*!< Slave select 1 output \b ss_1_n */ + ALT_SPI_SS2 = 1UL << 2, /*!< Slave select 2 output \b ss_2_n */ + ALT_SPI_SS3 = 1UL << 3 /*!< Slave select 3 output \b ss_3_n */ +} ALT_SPI_SS_t; + +/*! + * This type enumerates the Microwire direction control choices. The enumerations + * specify the direction of the data word when the Microwire serial protocol is + * used. + */ +typedef enum ALT_SPI_MW_DIR_e +{ + ALT_SPI_MW_DIR_RX = 0, /*!< The data word is received by the + * controller from an external serial + * device. + */ + ALT_SPI_MW_DIR_TX = 1 /*!< The data word is transmitted from the + * controller to an external serial device. + */ +} ALT_SPI_MW_DIR_t; + +/*! + * This definition specifies the largest possible control frame size. + */ +#define ALT_SPI_MW_CTL_FRAME_SIZE_MAX (16) + +/*! + * This type defines a structure for configuration of the SPI controller when + * using the Microwire serial protocol. + */ +typedef struct ALT_SPI_MW_CONFIG_s +{ + uint32_t ctl_frame_size; + /*!< Control Frame Size. Selects the length of + * the control word for the Microwire frame + * format. Valid range 0 <= \e n <= 16 where + * \e n sets the bit field to \e n - 1. + */ + ALT_SPI_MW_MODE_t mode; + /*!< Transfer Mode. Specifies whether the + * Microwire transfer is sequential or + * non-sequential. + */ + ALT_SPI_MW_DIR_t dir; + /*!< Direction. This setting controls the + * direction of the data word for the + * half-duplex Microwire serial protocol. + */ + bool handshake_enabled; + /*!< Microwire handshaking enable + * flag. Relevant only when the SPI + * controller is a master. Used to enable + * and disable the "busy/ready" handshaking + * interface for the Microwire + * protocol. When enabled (\e true), the SPI + * controller checks for a ready status from + * the target slave, after the transfer of + * the last data/control bit, before + * clearing the controller busy status. + */ +} ALT_SPI_MW_CONFIG_t; + +/*! + * Initialize the specified SPI controller instance for use and return a device + * handle referencing it. + * + * \param spi + * The HPS SPI controller instance to initialize. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Initialization process: + * * Initialize internal driver state + * * Check clock setup + * - spi_m_clk (ALT_CLK_SPI_M) for master instances + * - l4_main_clk (ALT_CLK_L4_MAIN) for slave instances + * * Take SPI module instance out of reset (System Manager) + * - RSTMGR.PERMODRST.SPIM[01] for master instances + * - RSTMGR.PERMODRST.SPIS[01] for slave instances + * * Disable and clear all interrupts and status conditions + * * Setup and initialize any expected initial SPI controller state + * \endinternal + */ +ALT_STATUS_CODE alt_spi_init(const ALT_SPI_CTLR_t spi, ALT_SPI_DEV_t *spi_dev); + +/*! + * Reset the specified SPI controller instance for use. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Reset process: + * * Disable controller + * * Initialize internal driver state + * * Take SPI instance out of reset (System Manager) + * * Disable and clear all interrupts and status conditions + * * Enable controller + * \endinternal + */ +ALT_STATUS_CODE alt_spi_reset(ALT_SPI_DEV_t * spi_dev); + +/*! + * Uninitialize the SPI controller referenced by the \e spi_dev handle. + * + * This function attempts to gracefully shutdown the SPI controller by waiting for + * any incomplete transactions to finish and then putting the SPI controller into + * reset. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * * Put SPI module instance into reset (System Manager) + * - RSTMGR.PERMODRST.SPIM[01] for master instances + * - RSTMGR.PERMODRST.SPIS[01] for slave instances + * \endinternal + */ +ALT_STATUS_CODE alt_spi_uninit(ALT_SPI_DEV_t *spi_dev); + +/*! + * Disables the SPI controller. + * + * When the SPI controller is disabled, the following occurs: + * * All transfers are halted immediately. + * * The TX FIFO and RX FIFO are cleared. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * SSIENR.SSI_EN = 0 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_disable(ALT_SPI_DEV_t *spi_dev); + +/*! + * Enables the SPI controller. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * SSIENR.SSI_EN = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_enable(ALT_SPI_DEV_t *spi_dev); + +/*! + * Returns ALT_E_TRUE if the SPI controller is enabled. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_BAD_ARG Details about error status code + * \retval ALT_E_TRUE SPI controller is enabled. + * \retval ALT_E_FALSE SPI controller is not enabled. + * + * \internal + * SSIENR.SSI_EN == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_is_enabled(ALT_SPI_DEV_t *spi_dev); + +/*! + * Returns ALT_E_TRUE if the SPI controller is busy. The SPI controller is busy if + * a serial transfer is in progress. If ALT_E_FALSE is returned, then the SPI + * controller is idle or disabled. + * + * NOTE: A busy status is not indicated when data is written into the transmit + * FIFO. The busy status only is set only when the target slave has been + * selected and the actual transfer is underway. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * SR.BUSY == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_is_busy(ALT_SPI_DEV_t *spi_dev); + +/*! + * Gets the current configuration of the SPI controller. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_SPI_CONFIG_t structure for holding the + * returned SPI controller configuration parameters. + * + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_config_get(ALT_SPI_DEV_t *spi_dev, ALT_SPI_CONFIG_t *cfg); + +/*! + * Sets the configuration of the SPI controller. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param cfg + * Pointer to a ALT_SPI_CONFIG_t structure holding the desired SPI + * controller configuration parameters. + * + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_config_set(ALT_SPI_DEV_t *spi_dev, const ALT_SPI_CONFIG_t *cfg); + +/*! + * Gets the current Microwire specific configuration parameters of the SPI + * controller. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param cfg + * [out] Pointer to a ALT_SPI_MW_CONFIG_t structure for holding the + * returned SPI controller Microwire specific configuration + * parameters. + * + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_mw_config_get(ALT_SPI_DEV_t *spi_dev, ALT_SPI_MW_CONFIG_t *cfg); + +/*! + * Sets the Microwire specific configuration parameters of the SPI controller. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param cfg + * Pointer to a ALT_SPI_MW_CONFIG_t structure holding the desired SPI + * controller Microwire specific configuration parameters. + * + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_mw_config_set(ALT_SPI_DEV_t *spi_dev, const ALT_SPI_MW_CONFIG_t *cfg); + +/*! + * This definition specifies a mask that applies to all slaves. + */ +#define ALT_SPI_SLAVE_MASK_ALL 0xF + +/*! + * Disable the specified SPI controller slave select output lines. + * + * This function is only valid for SPI controllers configured as masters. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param mask + * Specifies the slave select output signal line(s) to disable. \e + * mask is a mask of logically OR'ed \ref ALT_SPI_SS_t values that + * designate the slave select outputs to disable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * SER + * \endinternal + */ +ALT_STATUS_CODE alt_spi_slave_select_disable(ALT_SPI_DEV_t *spi_dev, + const uint32_t mask); + +/*! + * Enable the specified SPI controller slave select output lines. + * + * Normally, unless operating in broadcast mode, only one slave select output + * should be specified in \e mask. + * + * This function is only valid for SPI controllers configured as masters. + * + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param mask + * Specifies the slave select output signal line(s) to enable. \e + * mask is a mask of logically OR'ed \ref ALT_SPI_SS_t values that + * designate the slave select outputs to enable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * SER + * \endinternal + */ +ALT_STATUS_CODE alt_spi_slave_select_enable(ALT_SPI_DEV_t *spi_dev, + const uint32_t mask); + +/*! + * Gets the speed of the SPI master, which is calculated from divider value and + * the SPI controller internal clock. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param speed_in_hz + * Speed (Hz) of the SPI bus. + * + * \param div + * Clock divider. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_speed_get(ALT_SPI_DEV_t * spi_dev, + uint32_t * speed_in_hz); + + +/*! + * Set the baud rate divider to configure the generated \b sclk_out frequency. + * + * The generated \b sclk_out frequency is defined by the formula: + * + * Fsclk_out = Fspi_m_clk / DIV + * + * Where: + * * Fsclk_out is the generated frequency of \b sclk_out. + * * Fspi_m_clk is the input clock frequency to the SPI master + * peripheral module. + * * DIV is the baud rate divider value. + * + * This function is only valid for SPI master controllers. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param div + * The clock divider value. Valid clock divider values must be an + * even value in the range 2 to 65,534. If \e div is 0, then \b + * sclk_out is disabled. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * BAUDR + * \endinternal + */ +ALT_STATUS_CODE alt_spi_divider_set(ALT_SPI_DEV_t *spi_dev, const uint32_t div); + + + +/*! + * Get the configured baud rate divider value for the specified SPI controller. + * + * This function is only valid for SPI master controllers. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param div + * [out] The configured clock divider value. A returned value of 0 + * indicates that \b sclk_out is disabled. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * BAUDR + * \endinternal + */ +ALT_STATUS_CODE alt_spi_baud_rate_get(ALT_SPI_DEV_t *spi_dev, uint32_t *div); + +/*! + * Set the baud rate divider to configure the generated \b sclk_out frequency. + * + * The generated \b sclk_out frequency is defined by the formula: + * + * Fsclk_out = Fspi_m_clk / DIV + * + * Where: + * * Fsclk_out is the generated frequency of \b sclk_out. + * * Fspi_m_clk is the input clock frequency to the SPI master + * peripheral module. + * * DIV is the baud rate divider value. + * + * This function is only valid for SPI master controllers. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param div + * The clock divider value. Valid clock divider values must be an + * even value in the range 2 to 65,534. If \e div is 0, then \b + * sclk_out is disabled. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * BAUDR + * \endinternal + */ +ALT_STATUS_CODE alt_spi_baud_rate_set(ALT_SPI_DEV_t *spi_dev, const uint32_t div); + +/*! + * Gets the speed of the SPI master, which is calculated from divider value and + * the SPI controller internal clock. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param speed_in_hz + * Speed (Hz) of the SPI bus. + * + * \param div + * Clock divider. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_speed_get(ALT_SPI_DEV_t * spi_dev, + uint32_t * speed_in_hz); + +/*! + * Attempts to sets the speed of the SPI master to the requested speed by + * calculating and setting the most suitable divider value. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param speed_in_hz + * Speed (Hz) of the SPI bus. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_speed_set(ALT_SPI_DEV_t * spi_dev, + uint32_t speed_in_hz); + + +/*! + * Gets the speed of the SPI master, which is calculated from divider value and + * the SPI controller internal clock. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param speed_in_hz + * Speed (Hz) of the SPI bus. + * + * \param div + * Clock divider. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_speed_to_divider(ALT_SPI_DEV_t * spi_dev, + uint32_t speed_in_hz, + uint32_t * div); + +/*! + * Attempts to sets the speed of the SPI master to the requested speed by + * calculating and setting the most suitable divider value. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param speed_in_hz + * Speed (Hz) of the SPI bus. + * + * \param div + * A pointer to the clock divider. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_divider_to_speed(ALT_SPI_DEV_t * spi_dev, + uint32_t * speed_in_hz, + const uint32_t * div); + +/*! + * Get the current number of data frames configured for the SPI controller. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param num_data_frames + * [out] The current number of data frames parameter configured for + * the SPI controller. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * *num_data_frames = CTRLR1.NDF + 1 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_num_data_frames_get(ALT_SPI_DEV_t *spi_dev, uint32_t *num_data_frames); + +/*! + * Set the number of data frames configured for the SPI controller. + * + * Sets the number of data frames to be continuously received by the SPI + * controller. The SPI controller continues to receive serial data until the + * number of data frames received is equal to this parameter, which enables you to + * receive up to 64 KiB of data in a continuous transfer. + * + * This function is only valid for SPI master controller instances. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param num_data_frames + * The desired number of data frames for the SPI controller to + * receive. valid range: 1 to 65536. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * assert( alt_spi_is_enabled() == false ) + * assert( CRTLR0.TMOD == ALT_SPI_TMOD_RX or CRTLR0.TMOD == ALT_SPI_TMOD_EEPROM ) + * CTRLR1.NDF = num_data_frames - 1 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_num_data_frames_set(ALT_SPI_DEV_t *spi_dev, const uint32_t num_data_frames); + +/******************************************************************************/ +/*! \addtogroup ALT_SPI_INT Interrupt Status Conditions + * + * The SPI controller supports combined interrupt requests, which can be + * masked. The combined interrupt request is the ORed result of all other SPI + * interrupts after masking. All SPI interrupts have active-high polarity + * level. The SPI interrupts are described as follows: + * + * * Transmit FIFO Empty Interrupt - Set when the transmit FIFO is equal to + * or below its threshold value and requires service to prevent an + * under-run. The threshold value determines the level of transmit FIFO entries + * at which an interrupt is generated. This interrupt is cleared by hardware + * when data are written into the transmit FIFO buffer, bringing it over the + * threshold level. + * + * * Transmit FIFO Overflow Interrupt - Set when the host attempts to write + * into the transmit FIFO after it has been completely filled. When set, data + * written from the host is discarded. This interrupt remains set until you + * call alt_spi_int_clear() with ALT_SPI_STATUS_TXOI in the mask. + * + * * Receive FIFO Full Interrupt - Set when the receive FIFO is equal to or + * above its threshold value plus 1 and requires service to prevent an + * overflow. The threshold value determines the level of receive FIFO entries at + * which an interrupt is generated. This interrupt is cleared by hardware when + * data are read from the receive FIFO buffer, bringing it below the threshold + * level. + * + * * Receive FIFO Overflow Interrupt - Set when the receive logic attempts + * to place data into the receive FIFO after it has been completely filled. When + * set, newly received data are discarded. This interrupt remains set until you + * call alt_spi_int_clear() with ALT_SPI_STATUS_RXOI in the mask. + * + * * Receive FIFO Underflow Interrupt - Set when the host attempts to read + * from the receive FIFO when it is empty. When set, zeros are read back from + * the receive FIFO. This interrupt remains set until you call + * alt_spi_int_clear() with ALT_SPI_STATUS_RXUI in the mask. + * + * * Combined Interrupt Request - The OR'ed result of all the previously + * discussed interrupt status conditions after masking. Masking all interrupt + * status conditions will mask the combined interrupt signal (\b + * ALT_INT_INTERRUPT_SPIn_IRQ where \e n is 0-3) generated for the SPI + * controller that is sent to the Generic Interrupt Controller (GIC). + * + * Interrupt status conditions may be monitored by polling () or setting up an + * interrupt handler using the \ref INT_LL_ISR "HWLIB Interrupt Manager API". + * + * @{ + */ + +/*! + * This type enumerates interrupt status conditions for the SPI controller. + * + * For any interrupt status condition, a 0 value indicates the interrupt condition + * is not active and a 1 value indicates the interrupt condition is active. + */ +typedef enum ALT_SPI_STATUS_e +{ + ALT_SPI_STATUS_TXEI = 1UL << 0, /*!< Transmit FIFO Empty Interrupt Status */ + ALT_SPI_STATUS_TXOI = 1UL << 1, /*!< Transmit FIFO Overflow Interrupt Status */ + ALT_SPI_STATUS_RXUI = 1UL << 2, /*!< Receive FIFO Underflow Interrupt Status */ + ALT_SPI_STATUS_RXOI = 1UL << 3, /*!< Receive FIFO Overflow Interrupt Status */ + ALT_SPI_STATUS_RXFI = 1UL << 4, /*!< Receive FIFO Full Interrupt Status */ + ALT_SPI_STATUS_ALL = 0x1f /*!< All interrupt status conditions */ +} ALT_SPI_STATUS_t; + +/*! + * Returns the current SPI controller interrupt status conditions. + * + * This function returns the current value of the SPI controller interrupt status + * register value which reflects the current SPI controller interrupt status + * conditions that are not disabled (i.e. masked). + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_SPI_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * ISR + * \endinternal + */ +ALT_STATUS_CODE alt_spi_int_status_get(ALT_SPI_DEV_t *spi_dev, + uint32_t *status); + +/*! + * Returns the SPI controller raw interrupt status conditions irrespective of the + * interrupt status condition enablement state. + * + * This function returns the current value of the SPI controller raw interrupt + * status register value which reflects the current SPI controller status + * conditions regardless of whether they are disabled (i.e. masked) or not. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param status + * [out] A pointer to a bit mask of the active \ref ALT_SPI_STATUS_t + * interrupt and status conditions. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * RISR + * \endinternal + */ +ALT_STATUS_CODE alt_spi_int_raw_status_get(ALT_SPI_DEV_t *spi_dev, + uint32_t *status); + +/*! + * Clears the specified SPI controller interrupt status conditions identified in + * the mask. + * + * This function clears one or more of the interrupt status conditions that + * contribute to the combined \b ALT_INT_INTERRUPT_SPIn_IRQ interrupt + * signal state. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param mask + * Specifies the QSPI interrupt status conditions to clear. \e mask + * is a mask of logically OR'ed \ref ALT_SPI_STATUS_t values that + * designate the status conditions to clear. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * RXOICR + * TXOICR + * RXUICR + * MSTICR + * ICR + * \endinternal + */ +ALT_STATUS_CODE alt_spi_int_clear(ALT_SPI_DEV_t *spi_dev, const uint32_t mask); + +/*! + * Disable the specified SPI controller interrupt status conditions identified in + * the mask. + * + * This function disables one or more of the interrupt status conditions that + * contribute to the combined \b ALT_INT_INTERRUPT_SPIn_IRQ interrupt + * signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of enabling it as a contributor to the \b + * ALT_INT_INTERRUPT_SPIn_IRQ interrupt signal state. The function + * alt_spi_int_enable() is used to enable status source conditions. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param mask + * Specifies the status conditions to disable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_SPI_STATUS_t values that designate the status conditions to + * disable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_int_disable(ALT_SPI_DEV_t *spi_dev, const uint32_t mask); + +/*! + * Enable the specified SPI controller interrupt status conditions identified in + * the mask. + * + * This function enables one or more of the interrupt status conditions that + * contribute to the combined \b ALT_INT_INTERRUPT_SPIn_IRQ interrupt + * signal state. + * + * NOTE: A cleared bit for any status condition in the mask value does not have + * the effect of disabling it as a contributor to the \b + * ALT_INT_INTERRUPT_SPIn_IRQ interrupt signal state. The function + * alt_spi_int_disable() is used to disable status source conditions. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param mask + * Specifies the status conditions to enable as interrupt source + * contributors. \e mask is a mask of logically OR'ed \ref + * ALT_SPI_STATUS_t values that designate the status conditions to + * enable. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_int_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t mask); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_SPI_SAMPLE_DELAY RX Sample Delay Configuration + * + * SPI master controllers can configure a delay in the sample time of the \b rxd + * signal in order to increase the maximum achievable frequency on the serial bus. + * + * The delay value specifies an additional amount of delay applied to the \b rxd + * sample, in number of spi_m_clk clock cycles, up to \ref + * ALT_SPI_RXD_SAMPLE_DELAY_MAX cycles. + * + * The functions in this group only apply to SPI master controllers. + * @{ + */ + +/*! + * The maximum number of clock cycles that can be used to delay the sampling of + * the \b rxd input signal. + */ +#define ALT_SPI_RXD_SAMPLE_DELAY_MAX 4 + +/*! + * Get the configured Rx sample delay value. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param delay + * [out] The configured Rx sample delay in spi_m_clk clock cycles for + * the \b rxd signal. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_rx_sample_delay_get(ALT_SPI_DEV_t *spi_dev, uint32_t *delay); + +/*! + * Set the configured Rx sample delay value. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param delay + * The desired Rx sample delay in spi_m_clk clock cycles for the \b + * rxd signal. Must be in the range 0 .. \ref ALT_SPI_RXD_SAMPLE_DELAY_MAX. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * \endinternal + */ +ALT_STATUS_CODE alt_spi_rx_sample_delay_set(ALT_SPI_DEV_t *spi_dev, const uint32_t delay); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_SPI_RX_FIFO RX FIFO Management + * + * The receive FIFO has a configurable threshold value that controls the level of + * entries (or above) that sets the RX_FULL status condition and triggers an + * interrupt. The valid range is 0..(\ref ALT_SPI_RX_FIFO_NUM_ENTRIES - 1), with the + * additional restriction that SPI controller does not allow this value to be set to + * a value larger than the depth of the buffer. If an attempt is made to do that, the + * actual value set will be the maximum depth of the buffer. A value of 0 sets the + * threshold for 1 entry, and a value of (\ref ALT_SPI_RX_FIFO_NUM_ENTRIES - 1) sets + * the threshold for \ref ALT_SPI_RX_FIFO_NUM_ENTRIES entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the SPI controller receive FIFO. + */ +#define ALT_SPI_RX_FIFO_NUM_ENTRIES 256 + +/*! + * Reads a data frame from the receive (Rx) FIFO. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param data + * [out] The data frame read from into the Rx FIFO. The + * \e data parameter type is sized large enough to + * contain the widest possible data frame size. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * assert( alt_spi_is_enabled() ) + * DR = data + * \endinternal + */ +ALT_STATUS_CODE alt_spi_rx_fifo_deq(ALT_SPI_DEV_t *spi_dev, uint16_t *data); + +/*! + * Returns ALT_E_TRUE when the receive FIFO is empty. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * SR.RFNE == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_rx_fifo_is_empty(ALT_SPI_DEV_t *spi_dev); + +/*! + * Returns ALT_E_TRUE when the receive FIFO is completely full. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * SR.RFF == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_rx_fifo_is_full(ALT_SPI_DEV_t *spi_dev); + +/*! + * Returns the number of valid entries in the receive FIFO. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param num_entries + * [out] The number of entries in the receive FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RXFLR.RXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_spi_rx_fifo_level_get(ALT_SPI_DEV_t *spi_dev, + uint32_t *num_entries); + +/*! + * Gets the current receive FIFO threshold level value. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_spi_rx_fifo_threshold_get(ALT_SPI_DEV_t *spi_dev, + uint8_t *threshold); + +/*! + * Sets the current receive FIFO threshold level value. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_RX_TL.RX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_spi_rx_fifo_threshold_set(ALT_SPI_DEV_t *spi_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_SPI_TX_FIFO TX FIFO Management + * + * The transmit FIFO has a configurable threshold value that controls the level of + * entries (or below) that sets the TX_EMPTY status condition and triggers an + * interrupt. The valid range is 0..(\ref ALT_SPI_TX_FIFO_NUM_ENTRIES - 1), with the + * additional restriction that SPI controller does not allow this value to be set to + * a value larger than the depth of the buffer. If an attempt is made to do that, the + * actual value set will be the maximum depth of the buffer. A value of 0 sets the + * threshold for 0 entries, and a value of (\ref ALT_SPI_TX_FIFO_NUM_ENTRIES - 1) + * sets the threshold for (\ref ALT_SPI_TX_FIFO_NUM_ENTRIES - 1) entries. + * + * @{ + */ + +/*! + * The number of entries (depth) of the SPI controller transmit FIFO. + */ +#define ALT_SPI_TX_FIFO_NUM_ENTRIES 256 + +/*! + * Writes a data frame to the transmit (Tx) FIFO for transmittal. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param data + * The data frame to put into the Tx FIFO. The \e data + * parameter type is sized large enough to contain the + * widest possible data frame size. The data in each + * frame should be right justified within the \e data + * parameter. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * assert( alt_spi_is_enabled() ) + * DR = data + * \endinternal + */ +ALT_STATUS_CODE alt_spi_tx_fifo_enq(ALT_SPI_DEV_t *spi_dev, const uint16_t data); + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is empty. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * SR.TFE == 1 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_tx_fifo_is_empty(ALT_SPI_DEV_t *spi_dev); + +/*! + * Returns ALT_E_TRUE when the transmit FIFO is completely full. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * SR.TFNF == 0 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_tx_fifo_is_full(ALT_SPI_DEV_t *spi_dev); + +/*! + * Returns the number of valid entries in the transmit FIFO. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param num_entries + * [out] The number of entries in the transmit FIFO. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TXFLR.TXFLR + * \endinternal + */ +ALT_STATUS_CODE alt_spi_tx_fifo_level_get(ALT_SPI_DEV_t *spi_dev, + uint32_t *num_entries); + +/*! + * Gets the current transmit FIFO threshold level value. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param threshold + * [out] The current threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL + * \endinternal + */ +ALT_STATUS_CODE alt_spi_tx_fifo_threshold_get(ALT_SPI_DEV_t *spi_dev, + uint8_t *threshold); + +/*! + * Sets the current transmit FIFO threshold level value. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param threshold + * The threshold value. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * IC_TX_TL.TX_TL = threshold + * \endinternal + */ +ALT_STATUS_CODE alt_spi_tx_fifo_threshold_set(ALT_SPI_DEV_t *spi_dev, + const uint8_t threshold); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_SPI_TRANSFER Transfer Functions + * + * The functions in this section provide a high level serial transfer operations. + * + * These functions assume that the SPI master or serial controller configuration + * has already been established by calls to configuration functions like + * alt_spi_config_set() and alt_spi_baud_rate_set(). + * + * The transfer functions in this section modify settings for the SPI controller + * interrupts and Tx/Rx FIFOs as part of their implementation. No attempt to + * preserve established settings for interrupts and Tx/Rx FIFOs across calls to + * the transfer functions in this section is made. + * + * \internal + * The functions in this section are variations of procedures detailed in chapter 3. + * of DesignWare DW_apb_ssi Databook. + * + * You may implement the transfer functions to internally factor out common steps + * of the transfer procedure as you deem appropriate. + * \endinternal + * + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup ALT_SPI_TRANSFER_MASTER SPI Master Controller Transfer Functions + * + * The transfer functions in this group are for SPI controllers configured as + * masters. + * + * @{ + */ + +/*! + * This function performs a master SPI/SSP serial transmit and receive transfer. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param slave_select + * A mask of the slave select output signal line(s) to enable. \e + * slave_selects is a mask of logically OR'ed \ref ALT_SPI_SS_t + * values that designate the slave select outputs to enable during the + * transfer operation. + * + * \param num_frames + * The number of data frames involved in the transfer + * operation. Valid range: 1 to 65536. + * + * \param tx_buf + * A buffer of data frames to transmit. The \e tx_buf element type is + * sized large enough to contain the widest possible data frame + * size. The data in each frame should be right justified within its + * \e tx_buf element. The buffer is expected to contain \e num_frames + * data frames for transmittal. + * + * \param rx_buf + * [out] An buffer to receive data frames sent from the slave. The + * buffer is expected to be at least \e num_frames data frames in + * length. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Use procedure specified in section 3.6.1.4 of DesignWare DW_apb_ssi + * Databook. You may use interrupts to handle Tx FIFO, Rx FIFO, and BUSY event + * conditions. + * + * * Preconditions to calling this function are that the SPI + * controller has been configured with calls to: + * - alt_spi_config_set() + * - alt_spi_baud_rate_set() + * * CTRLR0.TMOD = ALT_SPI_TMOD_TXRX + * * Follow steps 3 - 8 of the procedure. + * \endinternal + */ +ALT_STATUS_CODE alt_spi_master_tx_rx_transfer(ALT_SPI_DEV_t *spi_dev, + const uint32_t slave_select, + const size_t num_frames, + const uint16_t * tx_buf, + uint16_t * rx_buf); + +/*! + * This function performs a master SPI/SSP serial transmit only transfer. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param slave_select + * A mask of the slave select output signal line(s) to enable. \e + * slave_selects is a mask of logically OR'ed \ref ALT_SPI_SS_t + * values that designate the slave select outputs to enable during the + * transfer operation. + * + * \param num_frames + * The number of data frames involved in the transfer + * operation. Valid range: 1 to 65536. + * + * \param tx_buf + * A buffer of data frames to transmit. The \e tx_buf element type is + * sized large enough to contain the widest possible data frame + * size. The data in each frame should be right justified within its + * \e tx_buf element. The buffer is expected to contain \e num_frames + * data frames for transmittal. + * + * \internal + * Use procedure specified in section 3.6.1.4 of DesignWare DW_apb_ssi + * Databook. You may use interrupts to handle Tx FIFO, Rx FIFO, and BUSY event + * conditions. + * + * * Preconditions to calling this function are that the SPI + * controller has been configured with calls to: + * - alt_spi_config_set() + * - alt_spi_baud_rate_set() + * * CTRLR0.TMOD = ALT_SPI_TMOD_TX + * * Follow steps 3 - 8 of the procedure. + * \endinternal + */ +ALT_STATUS_CODE alt_spi_master_tx_transfer(ALT_SPI_DEV_t *spi_dev, + const uint32_t slave_select, + const size_t num_frames, + const uint16_t * tx_buf); + +/*! + * This function performs a master SPI/SSP serial receive only transfer. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param slave_select + * A mask of the slave select output signal line(s) to enable. \e + * slave_selects is a mask of logically OR'ed \ref ALT_SPI_SS_t + * values that designate the slave select outputs to enable during the + * transfer operation. + * + * \param num_frames + * The number of data frames involved in the transfer + * operation. Valid range: 1 to 65536. + * + * \param rx_buf + * [out] An buffer to receive data frames sent from the slave. The + * buffer is expected to be at least \e num_frames data frames in + * length. + * + * \internal + * Use procedure specified in section 3.6.1.4 of DesignWare DW_apb_ssi + * Databook. You may use interrupts to handle Tx FIFO, Rx FIFO, and BUSY event + * conditions. + * + * * Preconditions to calling this function are that the SPI + * controller has been configured with calls to: + * - alt_spi_config_set() + * - alt_spi_baud_rate_set() + * * CTRLR0.TMOD = ALT_SPI_TMOD_RX + * * CTRLR1.NDF = num_frames - 1 + * * Follow steps 3 - 8 of the procedure. + * \endinternal + */ +ALT_STATUS_CODE alt_spi_master_rx_transfer(ALT_SPI_DEV_t *spi_dev, + const uint32_t slave_select, + const size_t num_frames, + uint16_t * rx_buf); + +/*! + * This function performs a master SPI EEPROM read transfer. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param slave_select + * A mask of the slave select output signal line(s) to enable. \e + * slave_selects is a mask of logically OR'ed \ref ALT_SPI_SS_t + * values that designate the slave select outputs to enable during the + * transfer operation. + * + * \param opcode + * The opcode to transmit to the EEPROM device. + * + * \param eeprom_addr + * The address transmitted to access the EEPROM device. + * + * \param num_frames + * The number of data frames involved in the transfer + * operation. Valid range: 1 to 65536. + * + * \param rx_buf + * [out] An buffer to receive data frames sent from the slave. The + * buffer is expected to be at least \e num_frames data frames in + * length. + * + * \internal + * Use procedure specified in section 3.6.1.4 of DesignWare DW_apb_ssi + * Databook. You may use interrupts to handle Tx FIFO, Rx FIFO, and BUSY event + * conditions. + * + * * Preconditions to calling this function are that the SPI + * controller has been configured with calls to: + * - alt_spi_config_set() + * - alt_spi_baud_rate_set() + * * assert( CTRLR0.FRF == ALT_SPI_FRF_SPI ) + * * CTRLR0.TMOD = ALT_SPI_TMOD_EEPROM + * * CTRLR1.NDF = num_frames - 1 + * * DR = opcode + * * DR = (eeprom_addr >> 8) & 0xff + * * DR = eeprom_addr & 0xff + * * Follow steps 3 - 8 of the procedure. + * \endinternal + */ +ALT_STATUS_CODE alt_spi_master_eeprom_transfer(ALT_SPI_DEV_t *spi_dev, + const uint32_t slave_select, + const uint8_t opcode, + const uint16_t eeprom_addr, + const size_t num_frames, + uint16_t * rx_buf); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_SPI_TRANSFER_SLAVE SPI Slave Controller Transfer Functions + * + * The transfer functions in this group are for SPI controllers configured as + * slaves. + * + * @{ + */ + +/*! + * This function performs a slave SPI/SSP serial transmit and receive transfer. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO and space in the RX FIFO to accomodate the request made. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param tx_buf + * A buffer of data frames to transmit. The \e tx_buf element type is + * sized large enough to contain the widest possible data frame + * size. The data in each frame should be right justified within its + * \e tx_buf element. + * + * \param rx_buf + * [out] An buffer to receive data frames sent from the master. The + * buffer is expected to be at least \e buf_len data frames in + * length. + * + * \param buf_len + * The length in data frames of the \e tx_buf and \e rx_buf buffers. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * Use procedure specified in section 3.6.2.1 of DesignWare DW_apb_ssi + * Databook. You may use interrupts to handle Tx FIFO, Rx FIFO, and BUSY event + * conditions. + * + * * Preconditions to calling this function are that the SPI + * controller has been configured with calls to: + * - alt_spi_config_set() + * - alt_spi_baud_rate_set() + * * CTRLR0.TMOD = ALT_SPI_TMOD_TXRX + * * Follow steps 3 - 8 of the procedure. + * \endinternal + */ +ALT_STATUS_CODE alt_spi_slave_tx_rx_transfer(ALT_SPI_DEV_t *spi_dev, + const uint16_t * tx_buf, + uint16_t * rx_buf, + const size_t buf_len); + +/*! + * This function performs a slave SPI/SSP serial transmit only transfer. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough space in the TX + * FIFO to accomodate the request made. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param tx_buf + * A buffer of data frames to transmit. The \e tx_buf element type is + * sized large enough to contain the widest possible data frame + * size. The data in each frame should be right justified within its + * \e tx_buf element. + * + * \param buf_len + * The length in data frames of the \e tx_buf buffer. + * + * \internal + * Use procedure specified in section 3.6.2.1 of DesignWare DW_apb_ssi + * Databook. You may use interrupts to handle Tx FIFO, Rx FIFO, and BUSY event + * conditions. + * + * * Preconditions to calling this function are that the SPI + * controller has been configured with calls to: + * - alt_spi_config_set() + * - alt_spi_baud_rate_set() + * * CTRLR0.TMOD = ALT_SPI_TMOD_TX + * * Follow steps 3 - 8 of the procedure. + * \endinternal + */ +ALT_STATUS_CODE alt_spi_slave_tx_transfer(ALT_SPI_DEV_t *spi_dev, + const uint16_t * tx_buf, + const size_t buf_len); + +/*! + * This function performs a slave SPI/SSP serial receive only transfer. + * + * This API is suitable for being called during an interrupt context. It is the + * programmer's responsibility to ensure that there is enough data in the RX + * FIFO to accomodate the request made. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param rx_buf + * [out] An buffer to receive data frames sent from the master. The + * buffer is expected to be at least \e buf_len data frames in + * length. + * + * \param buf_len + * The length in data frames of the \e rx_buf buffer. + * + * \internal + * Use procedure specified in section 3.6.2.1 of DesignWare DW_apb_ssi + * Databook. You may use interrupts to handle Tx FIFO, Rx FIFO, and BUSY event + * conditions. + * + * * Preconditions to calling this function are that the SPI + * controller has been configured with calls to: + * - alt_spi_config_set() + * - alt_spi_baud_rate_set() + * * CTRLR0.TMOD = ALT_SPI_TMOD_RX + * * CTRLR1.NDF = num_frames - 1 + * * Follow steps 3 - 8 of the procedure. + * \endinternal + */ +ALT_STATUS_CODE alt_spi_slave_rx_transfer(ALT_SPI_DEV_t *spi_dev, + uint16_t * rx_buf, + const size_t buf_len); + +/*! @} */ + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup ALT_SPI_DMA DMA Interface + * + * The functions in this section provide control and accsss to the DMA interface + * of the SPI controller. + * + * The SPI controller supports DMA signaling to indicate when the receive FIFO + * buffer has data ready to be read or when the transmit FIFO buffer needs + * data. It requires two DMA channels, one for transmit data and one for receive + * data. The SPI controller can issue single or burst DMA transfers and accepts + * burst acknowledges from the DMA. Software can trigger the DMA burst mode by + * enabling and programming an appropriate threshold value for the DMA + * interface. The typical setting of the threshold value is half the size of the + * Tx/Rx FIFO. + * + * @{ + */ + +/*! + * Disable the transmit (Tx) FIFO DMA channel. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * DMACR.TDMAE = 0 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_dma_tx_disable(ALT_SPI_DEV_t *spi_dev); + +/*! + * Enable and set the transmit data level for the transmit (Tx) FIFO DMA channel. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param level + * The transmit data level value at which the DMA request is made by + * the SPI controller transmit logic. The DMA request signal is + * generated when the number of valid data entries in the Tx FIFO is + * equal or below the \e level value. Valid values: 0 <= \e level < + * ALT_SPI_TX_FIFO_NUM_ENTRIES. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * DMATLDLR.DMATDL = level + * DMACR.TDMAE = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_dma_tx_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t level); + +/*! + * Disable the receive (Rx) FIFO DMA channel. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * DMACR.RDMAE = 0 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_dma_rx_disable(ALT_SPI_DEV_t *spi_dev); + +/*! + * Enable and set the receive data level for the receive (Rx) FIFO DMA channel. + * + * \param spi_dev + * A pointer to the SPI controller device block instance. + * + * \param level + * The receive data level value at which the DMA request is made by + * the SPI controller receive logic. The DMA request signal is + * generated when the number of valid data entries in the Rx FIFO is + * equal or below the \e level value. Valid values: 0 < \e level <= + * ALT_SPI_RX_FIFO_NUM_ENTRIES. + * + * \retval ALT_E_SUCCESS Successful status. + * \retval ALT_E_ERROR Details about error status code + * + * \internal + * DMARDLR.DMARDL = level + 1 + * DMACR.RDMAE = 1 + * \endinternal + */ +ALT_STATUS_CODE alt_spi_dma_rx_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t level); + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_SPI_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_system_manager.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_system_manager.h new file mode 100644 index 000000000..b30a5b8f8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_system_manager.h @@ -0,0 +1,209 @@ +/*! \file + * Altera - SoC FPGA System Manager + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_SYS_MGR_H__ +#define __ALT_SYS_MGR_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/******************************************************************************/ +/*! \addtogroup SYS_MGR The System Manager + * + * The System Manager API defines functions for control of system operation and + * for other modules requiring external control as part of system integration. + * + * The major functional APIs include: + * * HPS I/O configuration and pin muxing + * * External control of other modules + * * Control and status of ECC + * * Fault injection for ECC and parity errors. + * @{ + */ + +/******************************************************************************/ +/*! \addtogroup SYS_MGR_FPGA_INTERFACE FPGA Interface Group + * + * These functions provide enable/disable control and operational status of the + * signal interfaces between the FPGA and HPS. Selective enabling/disabling of + * interfaces may be required under the following scenarios: + * * Interfaces that are associated with an HPS module but that are not disabled + * when the HPS module associated with the interface is put into reset. + * * An HPS module accepts signals from the FPGA and those signals might + * otherwise interfere with the normal operation of the HPS module. + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the FPGA to HPS signal interfaces controlled + * by the functions in this API group. + */ +typedef enum ALT_FPGA_INTERFACE_e +{ + ALT_FPGA_INTERFACE_GLOBAL, /*!< All interfaces between the FPGA and + * HPS. If ALT_FPGA_INTERFACE_ALL is disabled + * then all of the individual and module + * interfaces between the FPGA and HPS are + * disabled regardless of their separate + * enable/disable settings. If + * ALT_FPGA_INTERFACE_ALL is enabled then each + * individual and module interface between + * the FPGA and HPS may be separately + * enabled/disabled. + */ + ALT_FPGA_INTERFACE_RESET_REQ, /*!< The reset request interface. This + * interface allows logic in the FPGA to + * request HPS resets. The following reset + * request signals from the FPGA fabric to + * HPS are part of this interface: + * * \b f2h_cold_rst_req_n - Triggers a HPS cold reset + * * \b f2h_warm_rst_req_n - Triggers a HPS warm reset + * * \b f2h_dbg_rst_req_n - Triggers a HPS debug reset + */ + ALT_FPGA_INTERFACE_JTAG_ENABLE, /*!< The JTAG enable interface. This + * interface allows logic in the FPGA + * fabric to disable the HPS JTAG + * operation. + */ + ALT_FPGA_INTERFACE_CONFIG_IO, /*!< The CONFIG_IO interface. This interface + * allows the FPGA JTAG TAP controller to + * execute the CONFIG_IO instruction and + * configure all device I/O (FPGA and + * HPS). + */ + ALT_FPGA_INTERFACE_BSCAN, /*!< The boundary-scan interface. This + * interface allows the FPGA JTAG TAP + * controller to execute boundary-scan + * instructions. + */ + ALT_FPGA_INTERFACE_TRACE, /*!< The trace interface. This interface + * allows the HPS debug logic to send + * trace data to logic in the FPGA. + */ + ALT_FPGA_INTERFACE_DBG_APB, /*!< (Private) The debug APB interface. This + * interface allows the HPS debug logic to + * communicate with debug APB slaves in + * the FPGA fabric. + */ + ALT_FPGA_INTERFACE_STM, /*!< The STM event interface. This interface + * allows logic in the FPGA to trigger + * events to the HPS STM debug module. + */ + ALT_FPGA_INTERFACE_CTI, /*!< The Cross Trigger Interface (CTI). This + * interface allows logic in the FPGA to + * send triggers to HPS debug logic. Note + * that this does not prevent the HPS + * debug logic from sending triggers to + * the FPGA. + */ + ALT_FPGA_INTERFACE_EMAC0, /*!< Signal interface from the FPGA to the + * EMAC0 module. + */ + ALT_FPGA_INTERFACE_EMAC1, /*!< Signal interface from the FPGA to the + * EMAC1 module. + */ + ALT_FPGA_INTERFACE_SPIM0, /*!< (Private) Signal interface from the + * FPGA to the SPI Master 0 module. + */ + ALT_FPGA_INTERFACE_SPIM1, /*!< (Private) Signal interface from the + * FPGA to the SPI Master 0 module. + */ + ALT_FPGA_INTERFACE_NAND, /*!< (Private) Signal interface from the + * FPGA to the NAND Flash Controller + * module. + */ + ALT_FPGA_INTERFACE_SDMMC /*!< (Private) Signal interface from the + * FPGA to the SD/MMC Controller module. + */ +} ALT_FPGA_INTERFACE_t; + +/******************************************************************************/ +/*! + * Disables the specified FPGA to HPS signal interface. + * + * Isolates and disables the designated FPGA/HPS signal interface. User is + * responsible for determining that the interface is inactive before disabling + * it. + * + * \param intfc + * The interface to disable. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The \e intfc argument designates an invalid + * FPGA/HPS signal interface. + */ +ALT_STATUS_CODE alt_fpga_interface_disable(ALT_FPGA_INTERFACE_t intfc); + +/******************************************************************************/ +/*! + * Enables the specified FPGA to HPS signal interface. + * + * \param intfc + * The interface to enable. + * + * \retval ALT_E_SUCCESS The operation was succesful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG The \e intfc argument designates an invalid + * FPGA/HPS signal interface. + */ +ALT_STATUS_CODE alt_fpga_interface_enable(ALT_FPGA_INTERFACE_t intfc); + +/******************************************************************************/ +/*! + * Return whether the specified FPGA/HPS signal interface is enabled or not. + * + * \param intfc + * The interface to enable. + * + * \retval ALT_E_TRUE The interface is enabled. + * \retval ALT_E_FALSE The interface is not enabled. + * \retval ALT_E_BAD_ARG The \e intfc argument designates an invalid + * FPGA/HPS signal interface. + */ +ALT_STATUS_CODE alt_fpga_interface_is_enabled(ALT_FPGA_INTERFACE_t intfc); + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_SYS_MGR_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_timers.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_timers.h new file mode 100644 index 000000000..3c9918f50 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_timers.h @@ -0,0 +1,681 @@ +/*! \file + * Altera - Module Description + */ + +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_GPT_H__ +#define __ALT_GPT_H__ + +#include +#include +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/******************************************************************************/ +/*! \addtogroup GPT_MGR The General Purpose Timer Manager API + * + * There are nine on-chip general purpose timers. Seven timers are available + * to each CPU.\n\n + * There are four types of timers available: + * - Four general-purpose countdown timers available to CPU0, CPU1, or the + * FPGA.\n + * - Each CPU has a private GP countdown timer available only to itself.\n + * - Each CPU has a watchdog timer available only to itself that can work in + * GP timer countdown mode.\n + * - One continuous-countup global timer with compare capabilities available to + * both CPUs and the FPGA.\n\n + * Each type has a somewhat different HW interface This API presents the same + * external interface for each. + * + * @{ + */ + +/******************************************************************************/ +/*! + * This type definition enumerates the names of the timers + * managed by the General Purpose Timers Manager. + */ +typedef enum ALT_GPT_TIMER_e +{ + /*! + * \b CPU_GLOBAL_TMR - CPU Core Global timer - There is one 64-bit + * continuously incrementing counter for all CPU cores that is clocked + * by PERIPHCLK. CPU_GLOBAL_TMR selects the comparator value, compare + * enable, autoincrement value, autoincrement enable, and interrupt + * enable for the CPU this code is running on. + */ + ALT_GPT_CPU_GLOBAL_TMR, + + /*! + * \b CPU_PRIVATE_TMR - CPU Core 32-bit Private Timer - The private timer + * for the CPU this code is running on. Clocked by PERIPHCLK. Counts + * down to zero and can either stop or restart. + */ + ALT_GPT_CPU_PRIVATE_TMR, + + /*! + * \b CPU_WDTGPT_TMR - CPU Core 32-bit Watchdog Timer - The watchdog + * timer can be used as a general-purpose timer by calling + * alt_wdt_response_mode_set() to put the watchdog timer in general-purpose + * timer mode. It is recommended that programmers use the other available + * timers first before using the watchdog timer as there is more software + * overhead involved in using the watchdog timer in this mode. This enum is + * for the core watchdog timer of the CPU this code is running on. Counts + * down to zero and can either stop or restart. + */ + ALT_GPT_CPU_WDTGPT_TMR, + + /* Peripheral Timers */ + /* OSC1 Clock Group */ + /*! + * \b osc1_timer0 - 32-bit timer connected to the L4_OSC1 bus clocked by + * osc1_clk. Counts down to zero and can either stop or restart. + */ + ALT_GPT_OSC1_TMR0, + + /*! + * \b osc1_timer1 - 32-bit timer connected to the L4_OSC1 bus clocked by + * osc1_clk. Counts down to zero and can either stop or restart. + */ + ALT_GPT_OSC1_TMR1, + + /* L4_SP Clock Group */ + /*! + * \b sp_timer0 - 32-bit timer connected to the L4_SP bus clocked by + * l4_sp_clk. Counts down to zero and can either stop or restart. + */ + ALT_GPT_SP_TMR0, + + /*! + * \b sp_timer1 - 32-bit timer connected to the L4_SP bus clocked by + * l4_sp_clk. Counts down to zero and can either stop or restart. + */ + ALT_GPT_SP_TMR1 + +} ALT_GPT_TIMER_t; + + +/*! + * This type definition enumerates the possible rollover or restart modes + * of the general purpose timers. + */ +typedef enum ALT_GPT_RESTART_MODE_e +{ + /*! + * \b ONE-SHOT \b MODE - \b CPU_PRIVATE_TMR, + * \b OSC1_TMR0, \b OSC1_TMR1, \b SP_TMR0, and \b SP_TMR1 + * count down from the value set with alt_gpt_counter_set() to + * zero, trigger an interrupt and stop.\n + * The global timer \b CPU_GLOBAL_TMR counts up to the next compare value + * set by the compare value, triggers an interrupt and stops + * comparing. + */ + ALT_GPT_RESTART_MODE_ONESHOT, + + /*! + * \b USER-SUPPLIED \b COUNT - For \b CPU_PRIVATE_TMR, \b OSC1_TMR0, + * \b OSC1_TMR1, \b SP_TMR0, and \b SP_TMR1, the timer counts down + * to zero and then resets to a value previously set using + * alt_gpt_counter_set() and continues counting.\n + * \b CPU_GLOBAL_TMR counts up to the comparator value, then adds + * the value set in alt_gpt_counter_set() to the comparator value and + * continues counting. + */ + ALT_GPT_RESTART_MODE_PERIODIC + +} ALT_GPT_RESTART_MODE_t; + + +/******************************************************************************/ +/*! \addtogroup GPT_STATUS Enable, Disable, and Status + * + * This functional group handles enabling, disabling, and reading the + * current enable state of the general purpose timers and the global timer. + * + * @{ + */ +/******************************************************************************/ +/*! Uninitialize all of the general-purpose timer modules + * + */ +ALT_STATUS_CODE alt_gpt_all_tmr_uninit(void); + +/******************************************************************************/ +/*! Initialize all of the general-purpose timer modules + * + */ +ALT_STATUS_CODE alt_gpt_all_tmr_init(void); + +/******************************************************************************/ +/*! + * Stop and disable the specified general purpose timer or global timer. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Tried to stop an invalid timer. + */ +ALT_STATUS_CODE alt_gpt_tmr_stop(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Enable and start the specified general purpose timer or global timer. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Tried to start an invalid timer. + */ +ALT_STATUS_CODE alt_gpt_tmr_start(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns whether the specified timer is currently running or not. + * For the free-running 64-bit global timer, returns whether its comparison + * mode is enabled or not. + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_TRUE The timer is currently enabled and running. + * \retval ALT_E_FALSE The timer is currently disabled and stopped. + * \retval ALT_E_BAD_ARG Tried to access an invalid timer. + */ +ALT_STATUS_CODE alt_gpt_tmr_is_running(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Restarts the specified general purpose timer with its original value. If + * used for the global timer, it updates the comparator value with the sum of + * the auto-increment value and the current global timer value and enables + * comparison mode. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Tried to access an invalid timer. + */ +ALT_STATUS_CODE alt_gpt_tmr_reset(ALT_GPT_TIMER_t tmr_id); + + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup GPT_COUNTER Counters Interface + * + * This functional group handles setting and reading the general purpose + * timer counters and the global timer. + * + * @{ + * */ +/******************************************************************************/ +/*! + * For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b + * OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1, sets the countdown value of the + * specified timer and the value that the counter will reset to (in rollover + * mode) or if restarted (in one-shot mode). It does not automatically start + * the counter. \n For tmr_id = \b CPU_GLOBAL_TMR, + * this function sets the auto-increment value instead, which is similar in + * function to setting the reset value of the other timers. The effect of this + * function is identical to using alt_globaltmr_autoinc_set(). + * + * + * \param tmr_id + * The timer identifier. + * + * \param val + * The 32-bit counter value to load. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpt_counter_set(ALT_GPT_TIMER_t tmr_id, + uint32_t val); + +/******************************************************************************/ +/*! + * For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b + * OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1, returns the current counter value of + * the specified timer. \n For tmr_id = \b CPU_GLOBAL_TMR, returns the 32 + * low-order bits of the counter and is identical to the result returned by + * alt_globaltmr_counter_get_low32(). Use alt_globaltmr_get() to obtain the full + * 64-bit timer value. + * + * \param tmr_id + * The timer identifier. + * + * + * \retval uint32_t The current 32-bit counter value. + */ +uint32_t alt_gpt_counter_get(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * For tmr_id = \b CPU_PRIVATE_TMR, \b OSC1_TMR0, \b + * OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1, returns the counter value that is + * set to be reloaded when the specified timer hits zero. \n + * For tmr_id = \b CPU_GLOBAL_TMR, returns the value that will + * autoincrement the comparator value, which defines the time until the next + * comparator interrupt is triggered. This is similar in function to the + * reset value of the other timers. It is identical to the result returned by + * alt_globaltmr_autoinc_get(). \n The value returned does not take into + * CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR. The prescaler value may be obtained + * with alt_gpt_prescaler_get(). + * + * + * \param tmr_id + * The timer identifier. + * + * + * \retval uint32_t The reset counter value currently set. + * \retval 0 An error occurred. + */ +uint32_t alt_gpt_reset_value_get(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the maximum counter value available for the specified + * timer. Valid for \b CPU_PRIVATE_TMR, \b OSC1_TMR0, + * \b OSC1_TMR1, \b SP_TMR0, \b SP_TMR1, and \b CPU_GLOBAL_TMR. \n + * The value returned does not factor in the value of the clock prescaler + * available for \b CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR. + * + * + * \param tmr_id + * The timer identifier. + * + * + * \retval uint32_t The maximum counter value available for this timer. + * \retval 0 An error occurred. + * + */ +uint32_t alt_gpt_maxcounter_get(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Sets the clock prescaler value of the specified timer. Valid for \b + * CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR. Returns an error + * if called with a tmr_id of \b OSC1_TMR0, + * \b OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1 since they have no prescaler. + * + * \param tmr_id + * The timer identifier. + * + * \param val + * The 32-bit prescaler value to load. Valid range is 1-256. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpt_prescaler_set(ALT_GPT_TIMER_t tmr_id, + uint32_t val); + +/******************************************************************************/ +/*! + * Returns the clock prescaler value of the specified timer. Valid for \b + * CPU_PRIVATE_TMR and \b CPU_GLOBAL_TMR. Returns one if + * called with a tmr_id of \b OSC1_TMR0, \b + * OSC1_TMR1, \b SP_TMR0, or \b SP_TMR1 since they have no prescaler. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval uint32_t The prescaler value. Valid range is 1-256. + * Zero indicates an error. + */ +uint32_t alt_gpt_prescaler_get(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the integer portion of the current countdown frequency of the + * specified timer. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval unint32_t The integer portion of the repeat frequency of the + * given timer, measured in Hertz (cycles per second). + */ +uint32_t alt_gpt_freq_get(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the current period of the specified timer measured in seconds. + * If the result is less than 64, alt_gpt_millisecs_get() will give a more + * precise result. + * + * \param tmr_id + * The timer identifier. + * + * \retval uint32_t The current period of the given timer, measured + * in seconds. + */ +uint32_t alt_gpt_time_get(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the current period of the specified timer measured in milliseconds. + * + * + * + * \param tmr_id + * The timer identifier. + * + * \retval uint32_t The current period of the given timer, measured + * in milliseconds. Returns 0 if result cannot fit + * in 32 bits. alt_gpt_time_get() can be used to + * obtain measurements of longer periods. + * alt_gpt_microsecs_get() can be used to obtain + * more precise measurements of shorter periods. + */ +uint32_t alt_gpt_time_millisecs_get(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the current period of the specified timer measured in milliseconds. + * + * + * + * \param tmr_id + * The timer identifier. + * + * \retval uint32_t The current period of the given timer, measured + * in microseconds. Returns 0 if result cannot fit + * in 32 bits. alt_gpt_millisecs_get() and + * alt_gpt_time_get() can be used to obtain + * measurements of longer periods. + */ +uint32_t alt_gpt_time_microsecs_get(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the current time until the specified timer counts + * down to zero, measured in seconds. + * + * \param tmr_id + * The timer identifier. + * + * + * \retval uint32_t The current 32-bit counter value. + */ +uint32_t alt_gpt_curtime_get(ALT_GPT_TIMER_t tmr_id); + + +/******************************************************************************/ +/*! + * Returns the current time until the specified timer counts + * down to zero, measured in milliseconds. \n Returns 0xFFFFFFFF if the value + * is too large to be expressed in 32 bits. + * + * \param tmr_id + * The timer identifier. + * + * + * \retval uint32_t The current 32-bit counter value. + */ +uint32_t alt_gpt_curtime_millisecs_get(ALT_GPT_TIMER_t tmr_id); + + +/******************************************************************************/ +/*! + * Returns the current time until the specified timer counts + * down to zero, measured in microseconds. \n Returns 0xFFFFFFFF if the value + * is too large to be expressed in 32 bits. + * + * \param tmr_id + * The timer identifier. + * + * + * \retval uint32_t The current 32-bit counter value. + */ +uint32_t alt_gpt_curtime_microsecs_get(ALT_GPT_TIMER_t tmr_id); + + +/******************************************************************************/ +/*! + * Returns the current time until the specified timer counts + * down to zero, measured in nanoseconds. \n Returns 0xFFFFFFFF if the value + * is too large to be expressed in 32 bits. + * + * \param tmr_id + * The timer identifier. + * + * + * \retval uint32_t The current 32-bit counter value. + */ +uint32_t alt_gpt_curtime_nanosecs_get(ALT_GPT_TIMER_t tmr_id); + + +/******************************************************************************/ +/*! + * Returns the maximum available period of the specified + * timer measured in seconds. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval uint32_t The maximum period of the given timer, measured + * in seconds. Returns 0 if result cannot fit + * in 32 bits. + */ +uint32_t alt_gpt_maxtime_get(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the maximum available period of the specified + * timer measured in milliseconds. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval uint32_t The maximum period of the given timer, measured + * in milliseconds. Returns 0 if result cannot fit + * in 32 bits. + */ +uint32_t alt_gpt_maxtime_millisecs_get(ALT_GPT_TIMER_t tmr_id); + +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup GPT_INT Interrupts + * This functional group handles managing, setting, clearing, and disabling + * the interrupts of the general purpose timers and the global timer. + * @{ */ +/******************************************************************************/ +/*! + * Disables the interrupt from the specified general purpose timer or + * global timer module. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpt_int_disable(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Enables the interrupt of the specified general purpose timer or global + * timer module. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpt_int_enable(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Return \b TRUE if the interrupt of the specified timer module is enabled + * and \b FALSE if the interrupt is disabled or masked. + * + * \param tmr_id + * The timer identifier. + * + * \retval TRUE The timer interrupt is currently enabled. + * \retval FALSE The timer interrupt is currently disabled. + */ +bool alt_gpt_int_is_enabled(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Clear the pending interrupt status of the specified timer module. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpt_int_clear_pending(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Read the state (pending or not) of the interrupt of the specified timer + * module without changing the interrupt state. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_TRUE The timer interrupt is currently pending. + * \retval ALT_E_FALSE The timer interrupt is not currently pending. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpt_int_is_pending(ALT_GPT_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Read the state of the interrupt of the specified general purpose timer + * module and if the interrupt is set, clear it. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_TRUE The timer interrupt is currently pending. + * \retval ALT_E_FALSE The timer interrupt is not currently pending. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpt_int_if_pending_clear(ALT_GPT_TIMER_t tmr_id); +/*! @} */ + +/******************************************************************************/ +/*! \addtogroup GPT_MODE Mode Control + * This functional group handles setting and reading the operational mode of + * the general purpose timers. The module version ID read function is also + * located here. + * @{ + */ +/******************************************************************************/ +/*! + * Sets the mode of the specified timer, the behavior that occurs when either + * the general-purpose timer counts down to zero or when the the global timer + * reaches its comparator value. + * + * + * \param tmr_id + * The timer identifier. + * + * \param mode + * \b GPT_RESTART_MODE_ONESHOT - To select one-shot mode for + * the timer. + * \n \b GPT_RESTART_MODE_PERIODIC - To select free-run mode for + * the timer. + * + * \internal + * The HHP HPS Timer NPP states that the value of the counter (Timer1LoadCount + * register) must be set to 0xFFFFFFFF before changing this setting to free- + * running mode (and timer must be disabled). The relevent L4 peripheral + * document does not mention the requirement to write 0xFFFFFFFF to the + * Timer1LoadCount register though. + * \endinternal + * + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +ALT_STATUS_CODE alt_gpt_mode_set(ALT_GPT_TIMER_t tmr_id, + ALT_GPT_RESTART_MODE_t mode); + +/******************************************************************************/ +/*! + * Reads the mode of the specified timer. + * + * \param tmr_id + * The timer identifier. + * + * \retval GPT_RESTART_MODE_ONESHOT Timer is set to one-shot mode. + * \retval GPT_RESTART_MODE_PERIODIC Counter value is set to a + * user-defined value. + * \retval ALT_E_BAD_ARG Invalid input argument. + */ +int32_t alt_gpt_mode_get(ALT_GPT_TIMER_t tmr_id); + +/*! @} */ +/*! @} */ +/*! @} */ +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_GPT_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_watchdog.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_watchdog.h new file mode 100644 index 000000000..f5a13e196 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/alt_watchdog.h @@ -0,0 +1,797 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ALT_WDOG_H__ +#define __ALT_WDOG_H__ + +#include "hwlib.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! \addtogroup WDOG_MGR The Watchdog Timer Manager API + * + * This module defines the Watchdog Timer Manager API for accessing, configuring, and + * controlling the HPS Watchdog Timer resources. + * + * +A typical initialization might be: +\verbatim +ALT_STATUS_CODE ret; +ret = alt_wdog_int_clear(ALT_CPU_WATCHDOG); +if (ret == ALT_E_SUCCESS) {ret = alt_wdog_counter_set(ALT_CPU_WATCHDOG, 0x7FFFFFFF); } +if (ret == ALT_E_SUCCESS) {ret = alt_wdog_core_prescaler_set(0x80); } +if (ret == ALT_E_SUCCESS) {ret = alt_wdog_response_mode_set(ALT_CPU_WATCHDOG, ALT_WDOG_TIMER_MODE_FREERUN); } +if (ret == ALT_E_SUCCESS) {ret = alt_wdog_int_enable(ALT_CPU_WATCHDOG); } +if (ret == ALT_E_SUCCESS) {ret = alt_wdog_start(ALT_CPU_WATCHDOG); } +\endverbatim + +Then periodically (before it runs out) call this function to restart the watchdog: +\verbatim +alt_wdog_reset(ALT_CPU_WATCHDOG); +\endverbatim + +If the interrupt is enabled in the interrupt manager and is triggered, it can be +cleared like this: +\verbatim +alt_wdog_int_clear(ALT_CPU_WATCHDOG); +\endverbatim + + +If the interrupt is not enabled in the interrupt manager, you can still poll to +see if it hit zero and clear any pending interrupts like this: +\verbatim +alt_wdog_int_if_pending_clear(ALT_CPU_WATCHDOG); +\endverbatim + * + * @{ + */ +/******************************************************************************/ + +/*! + * This type definition enumerates the names of the timers managed by + * the Watchdog Timers Manager. + */ +typedef enum ALT_WDOG_TIMER_e { + /* OSC1 Clock Group */ + /*! + * \b ALT_CPU_WATCHDOG - Each CPU core has its own watchdog timer, which is + * clocked by PERIPHCLK. Can be loaded with any 32-bit counter + * value, not limited to powers of two, and it has an 8-bit prescaler. + * This timer also has a pause-enable input that can allow other HW + * to freeze the countdown. + */ + ALT_WDOG_CPU, + + /* OSC1 Clock Group */ + /*! + * \b watchdog_timer0 - Connected to the L4_OSC1 bus clocked by osc1_clk. + * Counter values are limited to powers of two between 15 and 31 + * and there is no prescaler. + */ + ALT_WDOG0, + + /*! + * \b watchdog_timer1 - Connected to the L4_OSC1 bus clocked by osc1_clk. + * Counter values are limited to powers of two between 15 and 31 + * and there is no prescaler. + */ + ALT_WDOG1, + + /*! + * \b watchdog_init_timer0 - This is for the initial timout only (not + * necessarily immediately after system restart), watchdog_timer0 is then + * used for all subsequent timeouts. Connected to the L4_OSC1 bus clocked + * by osc1_clk. + * Counter values are limited to powers of two between 15 and 31 and + * there is no prescaler. + */ + ALT_WDOG0_INIT, + + /*! + * \b watchdog_init_timer1 - This is for the initial timout only (not + * necessarily immediately after system restart), watchdog_timer1 is then + * used for all subsequent timeouts. Connected to the L4_OSC1 bus clocked + * by osc1_clk. + * Counter values are limited to powers of two between 15 and 31 and + * there is no prescaler. + */ + ALT_WDOG1_INIT +} ALT_WDOG_TIMER_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the encoded countdown values that \b + * ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL + * can be set to use. + */ +typedef enum ALT_WDOG_TIMEOUT_e { + /*! + * \b ALT_WDOG_TIMEOUT64K - Timeout = 65,536 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT64K, + + /*! + * \b ALT_WDOG_TIMEOUT128K - Timeout = 131,072 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT128K, + + /*! + * \b ALT_WDOG_TIMEOUT256K - Timeout = 262,144 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT256K, + + /*! + * \b ALT_WDOG_TIMEOUT512K - Timeout = 524,288 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT512K, + + /*! + * \b ALT_WDOG_TIMEOUT1M - Timeout = 1,048,576 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT1M, + + /*! + * \b ALT_WDOG_TIMEOUT2M - Timeout = 2,097,152 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT2M, + + /*! + * \b ALT_WDOG_TIMEOUT4M - Timeout = 4,194,304 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT4M, + + /*! + * \b ALT_WDOG_TIMEOUT8M - Timeout = 8,388,608 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT8M, + + /*! + * \b ALT_WDOG_TIMEOUT16M - Timeout = 16,777,216 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT16M, + + /*! + * \b ALT_WDOG_TIMEOUT32M - Timeout = 33,554,432 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT32M, + + /*! + * \b ALT_WDOG_TIMEOUT64M - Timeout = 67,108,864 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT64M, + + /*! + * \b ALT_WDOG_TIMEOUT128M - Timeout = 134,217,728 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT128M, + + /*! + * \b ALT_WDOG_TIMEOUT256M - Timeout = 268,435,456 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT256M, + + /*! + * \b ALT_WDOG_TIMEOUT512M - Timeout = 536,870,912 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT512M, + + /*! + * + * \b ALT_WDOG_TIMEOUT1G - Timeout = 1,073,741,824 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT1G, + + /*! + * \b ALT_WDOG_TIMEOUT2G - Timeout = 2,147,483,648 osc1_clk periods. + */ + ALT_WDOG_TIMEOUT2G +} ALT_WDOG_TIMEOUT_t; + +/******************************************************************************/ +/*! + * This type definition enumerates the reset types that the watchdog + * timers can be set to trigger. + */ +typedef enum ALT_WDOG_RESET_TYPE_e { + /*! + * \b Reset - For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL, + * and \b ALT_WATCHDOG1_INITIAL, if the counter reaches zero without being + * reset, generate a system-wide warm reset request. + * This is the default mode out of reset. \n For \b ALT_CPU_WATCHDOG, no + * interrupt is triggered and a reset request is asserted. The response + * to the reset request is set in the reset controller block and may + * not automatically trigger a system reset. + */ + ALT_WDOG_WARM_RESET, + + /*! + * \b Interrupt_First - When the counter reaches zero without being + * reset, generate an interrupt. For \b ALT_WATCHDOG0, \b + * ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL, if the + * interrupt is not cleared by the time a second timeout occurs, then + * generate a system warm reset request. \n For \b ALT_CPU_WATCHDOG, the + * interrupt is triggered and a \b WDRESETREQ + * reset request is asserted. The response to the interrupt and the reset + * request is set in the interrupt and reset controller blocks and may + * not automatically trigger a system reset. + */ + ALT_WDOG_INT_THEN_RESET, + + /*! + * \b Timer_mode_oneshot - The \b ALT_CPU_WATCHDOG timer has the capability + * to not only operate as a watchdog timer, but also to operate as a + * general-purpose countdown timer. This selection specifies the \b + * ALT_CPU_WATCHDOG runs + * in one-shot timer mode, and can optionally trigger an interrupt when + * the counter reaches zero without being reset. This + * is the default selection for \b ALT_CPU_WATCHDOG out of reset. \n + * This selection has no meaning for \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b + * ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL. + */ + ALT_WDOG_TIMER_MODE_ONESHOT, + + /*! + * \b Timer_mode_freerun - The \b ALT_CPU_WATCHDOG timer has the capability + * to not only operate as a watchdog timer, but also to operate as a + * general-purpose countdown timer. This selection specifies the \b + * ALT_CPU_WATCHDOG in + * free-run or wraparound timer mode, and can optionally trigger an + * interrupt when the counter reaches zero without being reset. \n + * This selection has no meaning for \b + * ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL, and \b ALT_WATCHDOG1_INITIAL. + */ + ALT_WDOG_TIMER_MODE_FREERUN +} ALT_WDOG_RESET_TYPE_t; + +/******************************************************************************/ +/*! \addtogroup WDOG_STATUS Watchdog Timer Enable, Disable, Restart, Status + * + * This functional group contains the basic functions to control and manage + * the watchdog timers. + * + * @{ + */ +/******************************************************************************/ +/*! + * Initialize the watchdog timer module before use + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_wdog_init(void); + +/******************************************************************************/ +/*! + * Uninitialize the watchdog timer module & return to reset state + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_wdog_uninit(void); + +/******************************************************************************/ +/*! + * Stop the specified watchdog timer. \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b + * ALT_WATCHDOG0_INITIAL and \b ALT_WATCHDOG1_INITIAL cannot be stopped + * once started. + * + * \param tmr_id + * The watchdog timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Tried to stop an invalid watchdog timer. + */ +ALT_STATUS_CODE alt_wdog_stop(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Start the specified watchdog timer. + * + * + * \param tmr_id + * The watchdog timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Tried to enable an invalid watchdog timer. + */ +ALT_STATUS_CODE alt_wdog_start(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns whether the specified watchdog timer is currently running or not. + * + * + * \param tmr_id + * The watchdog timer identifier. + * + * \retval TRUE The timer is currently running. + * \retval FALSE The timer is currently not running. + */ +bool alt_wdog_tmr_is_enabled(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Reloads the counter countdown value, clears the timer interrupt, and + * restarts the watchdog timer. User can reset the timer at any time before + * timeout. This is also known as kicking, petting, feeding, waking, or + * walking the watchdog. \n If the timer is reset while stopped, it remains + * stopped, the timer reset value is reloaded and the countdown will start + * from there when it is started. The timer configuration is retained. + * + * + * \param tmr_id + * The watchdog timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Tried to reset an invalid watchdog timer. + */ +ALT_STATUS_CODE alt_wdog_reset(ALT_WDOG_TIMER_t tmr_id); + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup WDOG_COUNTERS Watchdog Timer Counter Configuration + * + * + * This functional group implements setting, configuring and reading + * the counters of the watchdog timers. + * + * @{ + */ +/******************************************************************************/ +/*! Sets the countdown value of the specified timer. This is a regular value + * for \b ALT_CPU_WATCHDOG. For tmr_id = \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b + * ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL however, this is an encoded + * power-of-two value such that 2**(16 + val). \n + * If this value is set before the watchdog timer is started, then this + * value is used from the start. If this value is set after the timer + * has been started, it takes effect when the timer rolls over or the next + * time it is started. + * + * \param tmr_id + * The watchdog timer identifier. + * + * \param val + * The counter value to load. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Tried to write an invalid watchdog timer or + * timeout value. + */ +ALT_STATUS_CODE alt_wdog_counter_set(ALT_WDOG_TIMER_t tmr_id, + uint32_t val); + +/******************************************************************************/ +/*! + * Returns the current counter value of the specified timer. + * + * \param tmr_id + * The watchdog timer identifier. + * + * + * \retval uint32_t The current 32-bit counter value. + */ +uint32_t alt_wdog_counter_get_current(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the current counter value of the specified timer, as measured in + * milliseconds. For \b ALT_CPU_WATCHDOG, this includes the effects of the + * prescaler setting. + * + * \param tmr_id + * The watchdog timer identifier. + * + * + * \retval uint32_t The current 32-bit counter value (in milliseconds). + */ +uint32_t alt_wdog_counter_get_curtime_millisecs(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the initial counter value of the specified timer as a 32-bit + * integer value. This is the value that will be reloaded when the timer + * is reset or restarted. For the timers where this value is set as an + * encoded powers-of-two between 15 and 31, the value is converted into the + * equivalent binary value before returning it. \n For \b ALT_CPU_WATCHDOG, + * the returned value does not include the effects of the prescaler setting. + * + * \param tmr_id + * The watchdog timer identifier. + * + * \retval uint32_t The current 32-bit counter value. + * 0 Indicates an error. + */ +uint32_t alt_wdog_counter_get_init(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the initial value of the specified timer in nanoseconds. + * This is the value that will be reloaded when the timer is reset or + * restarted. For \b ALT_CPU_WATCHDOG, this includes the effects of the + * prescaler setting. This call returns a more precise result than + * alt_wdog_counter_get_inittime_millisecs(), but as an unsigned 64-bit + * integer. + * + * \param tmr_id + * The watchdog timer identifier. + * + * \retval uint64_t The currently-selected watchdog delay time (in + * nanoseconds). + */ +uint64_t alt_wdog_counter_get_inittime_nanosecs(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the initialized value of the specified timer in milliseconds. + * This is the value that will be reloaded when the timer is reset or + * restarted. For \b ALT_CPU_WATCHDOG, this includes the effects of the + * prescaler setting. This call returns a 32-bit unsigned integer, though is + * less precise than alt_wdog_counter_get_inittime_nanosecs(). + * + * \param tmr_id + * The watchdog timer identifier. + * + * \retval uint32_t The currently-selected watchdog delay time (in + * milliseconds). + * 0 Indicates an error. +*/ +uint32_t alt_wdog_counter_get_inittime_millisecs(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Sets the value of the CPU watchdog timer \b ALT_CPU_WATCHDOG prescaler. + * Must be set before the watchdog timer is enabled. + * + * + * \param val + * The eight-bit prescaler value to load (maximum 255). + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_BAD_ARG Bad prescaler value specified. + */ +ALT_STATUS_CODE alt_wdog_core_prescaler_set(uint32_t val); + +/******************************************************************************/ +/*! + * Returns the value of the prescaler of the CPU core watchdog timer + * \b ALT_CPU_WATCHDOG. + * + * \retval val + * The eight-bit prescaler value. + * + */ +uint32_t alt_wdog_core_prescaler_get(void); + +/******************************************************************************/ +/*! + * Returns the maximum possible counter value of the specified timer as a + * 32-bit value. For the timers where this value is encoded (as + * powers-of-two between 15 and 31), the encoded value is converted into the + * equivalent binary value before returning it. This does not include the + * effects of the prescaler available for \b ALT_CPU_WATCHDOG. + * + * \param tmr_id + * The watchdog timer identifier. + * + * \retval uint32_t The current 32-bit counter value. + */ +uint32_t alt_wdog_counter_get_max(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the maximum possible delay time of the specified timer specified in + * nanoseconds. For \b ALT_CPU_WATCHDOG, this includes the prescaler setting. + * This call returns a more precise reading of the counter than + * alt_wdog_counter_get_max_millisecs(), though in an unsigned 64-bit integer. + * + * \param tmr_id + * The watchdog timer identifier. + * + * \retval uint64_t The maximum delay time before timeout (in + * nanoseconds). + */ +uint64_t alt_wdog_counter_get_max_nanosecs(ALT_WDOG_TIMER_t tmr_id); + + +/******************************************************************************/ +/*! + * Returns the maximum possible delay time of the specified timer specified in + * milliseconds. For \b ALT_CPU_WATCHDOG, this includes the prescaler setting. + * This call returns a 32-bit unsigned integer, though is less precise than + * alt_wdog_counter_get_max_nanosecs(). + * + * \param tmr_id + * The watchdog timer identifier. + * + * \retval uint32_t The maximum delay time before timeout (in + * milliseconds). + */ +uint32_t alt_wdog_counter_get_max_millisecs(ALT_WDOG_TIMER_t tmr_id); + +/*! @} */ +/******************************************************************************/ +/*! \addtogroup WDOG_INTS Watchdog Timer Interrupt Management + * + * + * This functional group implements management of the interrupts + * of the watchdog timers. + * + * @{ + */ +/******************************************************************************/ +/*! + * Disables the interrupt of the specified watchdog timer module. + * If the watchdog timer is one of the watchdog timers that can be used in + * general-purpose mode, and if the timer is in general-purpose timer mode, + * disable the interrupt. + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Specified an incorrect timer. + */ +ALT_STATUS_CODE alt_wdog_int_disable(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Sets/enables the interrupt of the specified watchdog timer module. + * If the watchdog timer is one of the watchdog timers that can be used in + * general-purpose mode, and if the timer is in general-purpose timer mode, + * enable the interrupt. + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Specified an incorrect timer. + */ +ALT_STATUS_CODE alt_wdog_int_enable(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the status of the interrupt of the specified watchdog timer module + * but does not clear it. Return \b TRUE if the interrupt of the specified + * general purpose timer module is pending and \b FALSE otherwise. + * + * \param tmr_id + * The timer identifier. + * + * \retval TRUE The timer interrupt is currently pending. + * \retval FALSE The timer interrupt is not currently pending. + */ +bool alt_wdog_int_is_pending(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the state of the interrupt of the specified watchdog timer module. + * If the watchdog timer is one of the watchdog timers that can be used in + * general-purpose mode, and if the timer is in general-purpose timer mode, + * returns \b TRUE if the interrupt of the specified general purpose timer + * module is enabled and \b FALSE if disabled. If the timer is not in + * general-purpose timer mode, returns /b TRUE, as watchdog interrupts are + * always enabled. + * + * \param tmr_id + * The timer identifier. + * + * \retval TRUE The timer interrupt is currently pending. + * \retval FALSE The timer interrupt is not currently pending. + */ +bool alt_wdog_int_is_enabled(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Clears the pending status of the interrupt of the specified watchdog + * timer module. + * + * + * \param tmr_id + * The timer identifier. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + */ +ALT_STATUS_CODE alt_wdog_int_clear(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the status of the interrupt of the specified watchdog timer module + * and also clears it. Return \b TRUE if the interrupt of the specified + * general purpose timer module is pending and \b FALSE otherwise. + * + * \param tmr_id + * The timer identifier. + * + * \retval TRUE The timer interrupt was pending. + * \retval FALSE The timer interrupt was not pending. + */ +bool alt_wdog_int_if_pending_clear(ALT_WDOG_TIMER_t tmr_id); + +/*! @} */ +#if ALTERA_INTERNAL_ONLY_DOCS +/******************************************************************************/ +/*! \addtogroup WDOG_MODE_CONF Watchdog Timer Miscellaneous Configuration + * + * This functional group implements setting and reading the current + * timer mode as well as reading the module component code and version code. + * + * @{ + */ +#else +/******************************************************************************/ +/*! \addtogroup WDOG_MODE_CONF Watchdog Timer Miscellaneous Configuration + * + * This functional group implements setting and reading the current + * timer mode. + * + * @{ + */ +#endif +/******************************************************************************/ +/*! + * Sets the timeout response mode of the specified watchdog timer. For \b + * ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, the + * options are to generate a system reset or to generate an interrupt and then + * generate a system reset if the interrupt is not cleared by the next time + * the watchdog timer counter rolls over.\n + * For \b ALT_CPU_WATCHDOG, the options are to trigger an interrupt request (with + * the result set in the interrupt manager) or a reset request (with the + * result set in the reset manager) plus two more options available + * when it is used as a general-purpose timer. + * \param tmr_id + * The timer identifier. + * + * \param type + * \b ALT_WDOG_WARM_RESET - For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b + * ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, reset the core + * immediately. \n For \b ALT_CPU_WATCHDOG, the action is + * determined by the current setting in the reset manager.\n\n + * \b ALT_WDOG_INT_THEN_RESET - For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b + * ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, raise an interrupt. + * If the interrupt is not cleared before the timer counts down + * to zero again, reset the CPU cores. \n For \b ALT_CPU_WATCHDOG, + * raise an interrupt. \n\n \b ALT_WDOG_TIMER_MODE_ONESHOT - For \b + * ALT_CPU_WATCHDOG, watchdog timer is set to timer mode and one-shot + * operation is selected.\n\n \b ALT_WDOG_TIMER_MODE_FREERUN - For \b + * ALT_CPU_WATCHDOG, watchdog timer is set to timer mode and free-run + * operation is selected. + * + * \retval ALT_E_SUCCESS The operation was successful. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Specified an incorrect timer or an unsupported + * response mode for the specified timer. + */ +ALT_STATUS_CODE alt_wdog_response_mode_set(ALT_WDOG_TIMER_t tmr_id, + ALT_WDOG_RESET_TYPE_t type); + +/******************************************************************************/ +/*! + * Returns the response mode of the specified timer. + * + * \param tmr_id + * The timer identifier. + * + * + * \retval ALT_WDOG_WARM_RESET + * For \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b + * ALT_WATCHDOG1_INITIAL, reset the core immediately. \n For \b + * ALT_CPU_WATCHDOG, the action is determined by the current setting + * in the reset manager. + * \retval ALT_WDOG_INT_THEN_RESET Raise an interrupt. For \b ALT_WATCHDOG0, \b + * ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b ALT_WATCHDOG1_INITIAL, if + * the interrupt is not cleared before timer wraps around again, + * reset the CPU cores. \n For \b ALT_CPU_WATCHDOG, the action is + * determined by the current setting in the interrupt manager. + * \retval ALT_WDOG_TIMER_MODE_ONESHOT Core watchdog timer is set to timer + * mode and one-shot operation is selected. + * \retval ALT_WDOG_TIMER_MODE_FREERUN Core watchdog timer is set to timer + * mode and free-run operation is selected. + * \retval ALT_E_ERROR The operation failed. + * \retval ALT_E_BAD_ARG Specified an invalid timer. + */ +int32_t alt_wdog_response_mode_get(ALT_WDOG_TIMER_t tmr_id); + + +#if ALTERA_INTERNAL_ONLY_DOCS + +/******************************************************************************/ +/*! + * Returns the component code of the watchdog timer module. \n Only valid + * for \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b + * ALT_WATCHDOG1_INITIAL. + * + * \param tmr_id + * The timer identifier. + * + * \retval uint32_t The component code of the module. + * It should be 0x44570120. + * + * \note This is an Altera Internal Only function + * + */ +uint32_t alt_wdog_compcode_get(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/*! + * Returns the version code of the watchdog timer module. \n Only valid for + * \b ALT_WATCHDOG0, \b ALT_WATCHDOG1, \b ALT_WATCHDOG0_INITIAL or \b + * ALT_WATCHDOG1_INITIAL. + * + * + * \param tmr_id + * The timer identifier. + * + * + * \retval uint32_t The encoded revision number of the module. + * + * \note This is an Altera Internal Only function + * + */ +uint32_t alt_wdog_ver_get(ALT_WDOG_TIMER_t tmr_id); + +#else + +/******************************************************************************/ +/* Returns the component code of the watchdog timer module. Only valid + * for ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL or ALT_WATCHDOG1_INITIAL. + * + * This is an Altera Internal Only function + */ + +uint32_t alt_wdog_compcode_get(ALT_WDOG_TIMER_t tmr_id); + +/******************************************************************************/ +/* Returns the version code of the watchdog timer module. Only valid for + * ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL or ALT_WATCHDOG1_INITIAL. + * + * This is an Altera Internal Only function + */ + +uint32_t alt_wdog_ver_get(ALT_WDOG_TIMER_t tmr_id); + +#endif /* ALTERA_INTERNAL_ONLY_DOCS */ + +/******************************************************************************/ + +/*! @} */ +/*! @} */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_WDOG_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/hwlib.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/hwlib.h new file mode 100644 index 000000000..9f908dfbc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/hwlib.h @@ -0,0 +1,189 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HWLIB_H__ +#define __HWLIB_H__ + +#ifdef __cplusplus +#include +#include +#include +#else /* __cplusplus */ +#include +#include +#include +#endif /* __cplusplus */ + +#include "alt_hwlibs_ver.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * The type definition for status codes returned by the HWLIB. + */ +typedef int32_t ALT_STATUS_CODE; + +/*! Definitions of status codes returned by the HWLIB. */ + +/*! The operation was successful. */ +#define ALT_E_SUCCESS 0 + +/*! The operation failed. */ +#define ALT_E_ERROR (-1) +/*! FPGA configuration error detected.*/ +#define ALT_E_FPGA_CFG (-2) +/*! FPGA CRC error detected. */ +#define ALT_E_FPGA_CRC (-3) +/*! An error occurred on the FPGA configuration bitstream input source. */ +#define ALT_E_FPGA_CFG_STM (-4) +/*! The FPGA is powered off. */ +#define ALT_E_FPGA_PWR_OFF (-5) +/*! The SoC does not currently control the FPGA. */ +#define ALT_E_FPGA_NO_SOC_CTRL (-6) +/*! The FPGA is not in USER mode. */ +#define ALT_E_FPGA_NOT_USER_MODE (-7) +/*! An argument violates a range constraint. */ +#define ALT_E_ARG_RANGE (-8) +/*! A bad argument value was passed. */ +#define ALT_E_BAD_ARG (-9) +/*! The operation is invalid or illegal. */ +#define ALT_E_BAD_OPERATION (-10) +/*! An invalid option was selected. */ +#define ALT_E_INV_OPTION (-11) +/*! An operation or response timeout period expired. */ +#define ALT_E_TMO (-12) +/*! The argument value is reserved or unavailable. */ +#define ALT_E_RESERVED (-13) +/*! A clock is not enabled or violates an operational constraint. */ +#define ALT_E_BAD_CLK (-14) +/*! The version ID is invalid. */ +#define ALT_E_BAD_VERSION (-15) +/*! The buffer does not contain enough free space for the operation. */ +#define ALT_E_BUF_OVF (-20) + +/*! + * Indicates a FALSE condition. + */ +#define ALT_E_FALSE (0) +/*! + * Indicates a TRUE condition. + */ +#define ALT_E_TRUE (1) + +/* Note, additional positive status codes may be defined to return + * a TRUE condition with additional information */ + + +/* Some other useful definitions */ + +/*! + * Specifies the current major and minor revision of the HWLibs. The + * MS four decimal digits specify the Altera ACDS release number, the + * LS two decimal digits specify minor revisions of the HWLibs, if any. + * + * A typical use is: + * \code + * #if ALTERA_HWLIBS_VERSION_CODE >= ALT_HWLIBS_VERSION(13, 1, 0) + * \endcode + * for a dependency on the major or minor ACDS revision + * or + * \code + * #if ALTERA_HWLIBS_VERSION_CODE == ALT_HWLIBS_VERSION(13, 0, 12) + * \endcode + * for a dependency on the hwlibs revision + * + */ +#define ALT_HWLIBS_VERSION(a,b,c) (((a)*10000)+((b)*100)+(c)) + +#define ALTERA_HWLIBS_VERSION_CODE ALT_HWLIBS_VERSION(ALTERA_ACDS_MAJOR_REV, \ + ALTERA_ACDS_MINOR_REV, ALTERA_HWLIBS_REV) + +/*! + * Allow some parts of the documentation to be hidden by setting to zero + */ +#define ALTERA_INTERNAL_ONLY_DOCS 1 + + +/*! + * Provide base address of MPU address space + */ + +#ifndef ALT_HPS_ADDR +#define ALT_HPS_ADDR 0 +#endif + +/*! + * These constants are sometimes useful: + */ +#define ALT_MILLISECS_IN_A_SEC 1000 +#define ALT_MICROSECS_IN_A_SEC 1000000 +#define ALT_NANOSECS_IN_A_SEC 1000000000 + +#define ALT_TWO_TO_POW0 (1) +#define ALT_TWO_TO_POW1 (1<<1) +#define ALT_TWO_TO_POW2 (1<<2) +#define ALT_TWO_TO_POW3 (1<<3) +#define ALT_TWO_TO_POW4 (1<<4) +#define ALT_TWO_TO_POW5 (1<<5) +#define ALT_TWO_TO_POW6 (1<<6) +#define ALT_TWO_TO_POW7 (1<<7) +#define ALT_TWO_TO_POW8 (1<<8) +#define ALT_TWO_TO_POW9 (1<<9) +#define ALT_TWO_TO_POW10 (1<<10) +#define ALT_TWO_TO_POW11 (1<<11) +#define ALT_TWO_TO_POW12 (1<<12) +#define ALT_TWO_TO_POW13 (1<<13) +#define ALT_TWO_TO_POW14 (1<<14) +#define ALT_TWO_TO_POW15 (1<<15) +#define ALT_TWO_TO_POW16 (1<<16) +#define ALT_TWO_TO_POW17 (1<<17) +#define ALT_TWO_TO_POW18 (1<<18) +#define ALT_TWO_TO_POW19 (1<<19) +#define ALT_TWO_TO_POW20 (1<<20) +#define ALT_TWO_TO_POW21 (1<<21) +#define ALT_TWO_TO_POW22 (1<<22) +#define ALT_TWO_TO_POW23 (1<<23) +#define ALT_TWO_TO_POW24 (1<<24) +#define ALT_TWO_TO_POW25 (1<<25) +#define ALT_TWO_TO_POW26 (1<<26) +#define ALT_TWO_TO_POW27 (1<<27) +#define ALT_TWO_TO_POW28 (1<<28) +#define ALT_TWO_TO_POW29 (1<<29) +#define ALT_TWO_TO_POW30 (1<<30) +#define ALT_TWO_TO_POW31 (1<<31) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __HWLIB_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_acpidmap.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_acpidmap.h new file mode 100644 index 000000000..50cd1e8ae --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_acpidmap.h @@ -0,0 +1,3569 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_ACPIDMAP */ + +#ifndef __ALTERA_ALT_ACPIDMAP_H__ +#define __ALTERA_ALT_ACPIDMAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : ACP ID Mapper Registers - ALT_ACPIDMAP + * ACP ID Mapper Registers + * + * Registers in the ACP ID Mapper module + * + */ +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 2 - vid2rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | ARUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : ARUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD. + */ +struct ALT_ACPIDMAP_VID2RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_s ALT_ACPIDMAP_VID2RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_OFST 0x0 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 2 - vid2wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x1 | AWUSER value to SCU for ID=2 + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x4 | Remap Master ID = DAP ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x1 | Force Mapping for ID=2 + * + */ +/* + * Field : AWUSER value to SCU for ID=2 - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR. + */ +struct ALT_ACPIDMAP_VID2WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU for ID=2 */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID = DAP ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping for ID=2 */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_s ALT_ACPIDMAP_VID2WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_OFST 0x4 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 3 - vid3rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD. + */ +struct ALT_ACPIDMAP_VID3RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_s ALT_ACPIDMAP_VID3RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_OFST 0x8 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 3 - vid3wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR. + */ +struct ALT_ACPIDMAP_VID3WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_s ALT_ACPIDMAP_VID3WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_OFST 0xc + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 4 - vid4rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD. + */ +struct ALT_ACPIDMAP_VID4RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_s ALT_ACPIDMAP_VID4RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_OFST 0x10 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 4 - vid4wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR. + */ +struct ALT_ACPIDMAP_VID4WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_s ALT_ACPIDMAP_VID4WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_OFST 0x14 + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 5 - vid5rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD. + */ +struct ALT_ACPIDMAP_VID5RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_s ALT_ACPIDMAP_VID5RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_OFST 0x18 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 5 - vid5wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR. + */ +struct ALT_ACPIDMAP_VID5WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_s ALT_ACPIDMAP_VID5WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_OFST 0x1c + +/* + * Register : Read AXI Master Mapping Register for Fixed Virtual ID 6 - vid6rd + * + * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD. + */ +struct ALT_ACPIDMAP_VID6RD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_s ALT_ACPIDMAP_VID6RD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_OFST 0x20 + +/* + * Register : Write AXI Master Mapping Register for Fixed Virtual ID 6 - vid6wr + * + * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID + * signals mapping values for particular transaction with 12-bit ID which locks the + * fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Remap Master ID + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Force Mapping + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR. + */ +struct ALT_ACPIDMAP_VID6WR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t mid : 12; /* Remap Master ID */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t force : 1; /* Force Mapping */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_s ALT_ACPIDMAP_VID6WR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_OFST 0x24 + +/* + * Register : Read AXI Master Mapping Register for Dynamic Virtual ID Remap - dynrd + * + * The Read AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | ARUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD. + */ +struct ALT_ACPIDMAP_DYNRD_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* ARUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* ARADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_s ALT_ACPIDMAP_DYNRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_OFST 0x28 + +/* + * Register : Write AXI Master Mapping Register for Dynamic Virtual ID Remap - dynwr + * + * The Write AXI Master Mapping Register contains the USER, and ADDR page signals + * mapping values for transaction that dynamically remapped to one of the available + * 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | RW | 0x0 | AWUSER value to SCU + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR. + */ +struct ALT_ACPIDMAP_DYNWR_s +{ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t user : 5; /* AWUSER value to SCU */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t page : 2; /* AWADDR 1GB Page Decoder */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_s ALT_ACPIDMAP_DYNWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_OFST 0x2c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | ARUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : ARUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2RD_S. + */ +struct ALT_ACPIDMAP_VID2RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2RD_S_s ALT_ACPIDMAP_VID2RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2RD_S_OFST 0x30 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | 0x1 | AWUSER value to SCU for ID=2 (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Force Mapping for ID=2 (Status) + * + */ +/* + * Field : AWUSER value to SCU for ID=2 (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID2WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID2WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID = DAP ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_RESET 0x4 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID2WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping for ID=2 (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_RESET 0x1 +/* Extracts the ALT_ACPIDMAP_VID2WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID2WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID2WR_S. + */ +struct ALT_ACPIDMAP_VID2WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU for ID=2 (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID2WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID2WR_S_s ALT_ACPIDMAP_VID2WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID2WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID2WR_S_OFST 0x34 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3RD_S. + */ +struct ALT_ACPIDMAP_VID3RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3RD_S_s ALT_ACPIDMAP_VID3RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3RD_S_OFST 0x38 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID3WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID3WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID3WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID3WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID3WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID3WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID3WR_S. + */ +struct ALT_ACPIDMAP_VID3WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID3WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID3WR_S_s ALT_ACPIDMAP_VID3WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID3WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID3WR_S_OFST 0x3c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4RD_S. + */ +struct ALT_ACPIDMAP_VID4RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4RD_S_s ALT_ACPIDMAP_VID4RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4RD_S_OFST 0x40 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID4WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID4WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID4WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID4WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID4WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID4WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID4WR_S. + */ +struct ALT_ACPIDMAP_VID4WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID4WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID4WR_S_s ALT_ACPIDMAP_VID4WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID4WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID4WR_S_OFST 0x44 + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5RD_S. + */ +struct ALT_ACPIDMAP_VID5RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5RD_S_s ALT_ACPIDMAP_VID5RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5RD_S_OFST 0x48 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID5WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID5WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID5WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID5WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID5WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID5WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID5WR_S. + */ +struct ALT_ACPIDMAP_VID5WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID5WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID5WR_S_s ALT_ACPIDMAP_VID5WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID5WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID5WR_S_OFST 0x4c + +/* + * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6rd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6RD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6RD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6RD_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6RD_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6RD_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6RD_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6RD_S. + */ +struct ALT_ACPIDMAP_VID6RD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6RD_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6RD_S_s ALT_ACPIDMAP_VID6RD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6RD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6RD_S_OFST 0x50 + +/* + * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6wr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, ADDR + * page, and ID signals mapping values for particular transaction with 12-bit ID + * which locks the fixed 3-bit virtual ID. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [27:16] | R | Unknown | Remap Master ID (Status) + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | Unknown | Force Mapping (Status) + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_VID6WR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_VID6WR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Remap Master ID (Status) - mid + * + * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit + * ID to use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_MSB 27 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_WIDTH 12 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_CLR_MSK 0xf000ffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_MID register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_MID field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_ACPIDMAP_VID6WR_S_MID register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : Force Mapping (Status) - force + * + * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set + * to 0 to allow the 3-bit ID N to be dynamically allocated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_MSB 31 +/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_WIDTH 1 +/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_ACPIDMAP_VID6WR_S_FORCE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_VID6WR_S_FORCE field value from a register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_ACPIDMAP_VID6WR_S_FORCE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_VID6WR_S. + */ +struct ALT_ACPIDMAP_VID6WR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t mid : 12; /* Remap Master ID (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t force : 1; /* Force Mapping (Status) */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_VID6WR_S. */ +typedef volatile struct ALT_ACPIDMAP_VID6WR_S_s ALT_ACPIDMAP_VID6WR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_VID6WR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_VID6WR_S_OFST 0x54 + +/* + * Register : Read AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynrd_s + * + * The Read AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | ARUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ARUSER value to SCU (Status) - user + * + * This value is propagated to SCU as ARUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNRD_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : ARADDR 1GB Page Decoder (Status) - page + * + * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNRD_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNRD_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNRD_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNRD_S. + */ +struct ALT_ACPIDMAP_DYNRD_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* ARUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNRD_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNRD_S_s ALT_ACPIDMAP_DYNRD_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNRD_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNRD_S_OFST 0x58 + +/* + * Register : Write AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynwr_s + * + * The Write AXI Master Mapping Status Register contains the configured USER, and + * ADDR page signals mapping values for transaction that dynamically remapped to + * one of the available 3-bit virtual IDs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------- + * [3:0] | ??? | 0x0 | *UNDEFINED* + * [8:4] | R | Unknown | AWUSER value to SCU (Status) + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AWUSER value to SCU (Status) - user + * + * This value is propagated to SCU as AWUSERS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_MSB 8 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_WIDTH 5 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_USER register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_USER field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_ACPIDMAP_DYNWR_S_USER register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_USER_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : AWADDR 1GB Page Decoder (Status) - page + * + * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_MSB 13 +/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_WIDTH 2 +/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET_MSK 0x00003000 +/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_CLR_MSK 0xffffcfff +/* The reset value of the ALT_ACPIDMAP_DYNWR_S_PAGE register field is UNKNOWN. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_RESET 0x0 +/* Extracts the ALT_ACPIDMAP_DYNWR_S_PAGE field value from a register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_ACPIDMAP_DYNWR_S_PAGE register field value suitable for setting the register. */ +#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_ACPIDMAP_DYNWR_S. + */ +struct ALT_ACPIDMAP_DYNWR_S_s +{ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t user : 5; /* AWUSER value to SCU (Status) */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_ACPIDMAP_DYNWR_S. */ +typedef volatile struct ALT_ACPIDMAP_DYNWR_S_s ALT_ACPIDMAP_DYNWR_S_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_ACPIDMAP_DYNWR_S register from the beginning of the component. */ +#define ALT_ACPIDMAP_DYNWR_S_OFST 0x5c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_ACPIDMAP. + */ +struct ALT_ACPIDMAP_s +{ + volatile ALT_ACPIDMAP_VID2RD_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile ALT_ACPIDMAP_VID2WR_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile ALT_ACPIDMAP_VID3RD_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile ALT_ACPIDMAP_VID3WR_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile ALT_ACPIDMAP_VID4RD_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile ALT_ACPIDMAP_VID4WR_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile ALT_ACPIDMAP_VID5RD_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile ALT_ACPIDMAP_VID5WR_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile ALT_ACPIDMAP_VID6RD_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile ALT_ACPIDMAP_VID6WR_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile ALT_ACPIDMAP_DYNRD_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile ALT_ACPIDMAP_DYNWR_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile ALT_ACPIDMAP_VID2RD_S_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile ALT_ACPIDMAP_VID2WR_S_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile ALT_ACPIDMAP_VID3RD_S_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile ALT_ACPIDMAP_VID3WR_S_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile ALT_ACPIDMAP_VID4RD_S_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile ALT_ACPIDMAP_VID4WR_S_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile ALT_ACPIDMAP_VID5RD_S_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile ALT_ACPIDMAP_VID5WR_S_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile ALT_ACPIDMAP_VID6RD_S_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile ALT_ACPIDMAP_VID6WR_S_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile ALT_ACPIDMAP_DYNRD_S_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile ALT_ACPIDMAP_DYNWR_S_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_s ALT_ACPIDMAP_t; +/* The struct declaration for the raw register contents of register group ALT_ACPIDMAP. */ +struct ALT_ACPIDMAP_raw_s +{ + volatile uint32_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ + volatile uint32_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ + volatile uint32_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ + volatile uint32_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ + volatile uint32_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ + volatile uint32_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ + volatile uint32_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ + volatile uint32_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ + volatile uint32_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ + volatile uint32_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ + volatile uint32_t dynrd; /* ALT_ACPIDMAP_DYNRD */ + volatile uint32_t dynwr; /* ALT_ACPIDMAP_DYNWR */ + volatile uint32_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ + volatile uint32_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ + volatile uint32_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ + volatile uint32_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ + volatile uint32_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ + volatile uint32_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ + volatile uint32_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ + volatile uint32_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ + volatile uint32_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ + volatile uint32_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ + volatile uint32_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ + volatile uint32_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ + volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_ACPIDMAP. */ +typedef volatile struct ALT_ACPIDMAP_raw_s ALT_ACPIDMAP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_ACPIDMAP_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_can.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_can.h new file mode 100644 index 000000000..ded9a28b7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_can.h @@ -0,0 +1,36873 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_CAN */ + +#ifndef __ALTERA_ALT_CAN_H__ +#define __ALTERA_ALT_CAN_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : CAN Controller Module - ALT_CAN + * CAN Controller Module + * + * Registers in the CAN Controller module + * + */ +/* + * Register Group : Protocol Group - ALT_CAN_PROTO + * Protocol Group + * + * These registers are related to the CAN protocol controller in the CAN Core. They + * control the operating modes and the configuration of the CAN bit timing and + * provide status information. + * + */ +/* + * Register : Control Register - CCTRL + * + * Control Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------- + * [0] | RW | 0x1 | Initialization + * [1] | RW | 0x0 | Module Interrupt Line Enable + * [2] | RW | 0x0 | Status Interrupt Enable + * [3] | RW | 0x0 | Error Interrupt Enable + * [4] | ??? | 0x0 | *UNDEFINED* + * [5] | RW | 0x0 | Disable Automatic Retransmission + * [6] | RW | 0x0 | Configuration Change Enable + * [7] | RW | 0x0 | Test Mode Enable + * [16:8] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Message Object Interrupt Line Enable + * [18] | RW | 0x0 | DMA Enable for IF1 + * [19] | RW | 0x0 | DMA Enable for IF2 + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Initialization - Init + * + * Initialization + * + * Note: Due to the synchronization mechanism between the two clock domains, there + * may be a delay until the value written to CCTRL.Init can be read back. Therefore + * the programmer has to assure that the previous value written to CCTRL.Init has + * been accepted by reading CCTRL.Init before setting CCTRL.Init to a new value.\n + * + * Note: The Bus_Off recovery sequence (see CAN Specification Rev. 2.0) cannot be + * shortened by setting or resetting CCTRL.Init. If the device goes Bus_Off, it + * will set CCTRL.Init of its own accord, stopping all bus activities. Once + * CCTRL.Init has been cleared by the CPU, the device will then wait for 129 + * occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming + * normal operations. At the end of the Bus_Off recovery sequence, the Error + * Management Counters will be reset. During the waiting time after the resetting + * of CCTRL.Init, each time a sequence of 11 recessive bits has been monitored, a + * Bit0Error code is written to the Status Register, enabling the CPU to readily + * check up whether the CAN bus is stuck at dominant or continuously disturbed and + * to monitor the proceeding of the us_Off recovery sequence. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:--------------------------- + * ALT_CAN_PROTO_CCTL_INIT_E_NORMAL | 0x0 | Normal Operation. + * ALT_CAN_PROTO_CCTL_INIT_E_START | 0x1 | Initialization is started. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_INIT + * + * Normal Operation. + */ +#define ALT_CAN_PROTO_CCTL_INIT_E_NORMAL 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_INIT + * + * Initialization is started. + */ +#define ALT_CAN_PROTO_CCTL_INIT_E_START 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_INIT register field. */ +#define ALT_CAN_PROTO_CCTL_INIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_INIT register field. */ +#define ALT_CAN_PROTO_CCTL_INIT_MSB 0 +/* The width in bits of the ALT_CAN_PROTO_CCTL_INIT register field. */ +#define ALT_CAN_PROTO_CCTL_INIT_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CCTL_INIT register field value. */ +#define ALT_CAN_PROTO_CCTL_INIT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_PROTO_CCTL_INIT register field value. */ +#define ALT_CAN_PROTO_CCTL_INIT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_PROTO_CCTL_INIT register field. */ +#define ALT_CAN_PROTO_CCTL_INIT_RESET 0x1 +/* Extracts the ALT_CAN_PROTO_CCTL_INIT field value from a register. */ +#define ALT_CAN_PROTO_CCTL_INIT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_PROTO_CCTL_INIT register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CCTL_INIT_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Module Interrupt Line Enable - ILE + * + * Module Interrupt Line Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------ + * ALT_CAN_PROTO_CCTL_ILE_E_DISD | 0x0 | Module Interrupt Line CAN_INT_STATUS is always + * : | | LOW. + * ALT_CAN_PROTO_CCTL_ILE_E_END | 0x1 | Error and status interrupts (if CCTRL.EIE=1 and + * : | | CCTRL.SIE=1) will set line CAN_INT_STATUS to + * : | | one, signal remains one until all pending + * : | | interrupts are processed. If MIL is disabled, + * : | | the message object interrupts will also affect + * : | | this interrupt line. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_ILE + * + * Module Interrupt Line CAN_INT_STATUS is always LOW. + */ +#define ALT_CAN_PROTO_CCTL_ILE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_ILE + * + * Error and status interrupts (if CCTRL.EIE=1 and CCTRL.SIE=1) will set line + * CAN_INT_STATUS to one, signal remains one until all pending interrupts are + * processed. If MIL is disabled, the message object interrupts will also affect + * this interrupt line. + */ +#define ALT_CAN_PROTO_CCTL_ILE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_ILE register field. */ +#define ALT_CAN_PROTO_CCTL_ILE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_ILE register field. */ +#define ALT_CAN_PROTO_CCTL_ILE_MSB 1 +/* The width in bits of the ALT_CAN_PROTO_CCTL_ILE register field. */ +#define ALT_CAN_PROTO_CCTL_ILE_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CCTL_ILE register field value. */ +#define ALT_CAN_PROTO_CCTL_ILE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_PROTO_CCTL_ILE register field value. */ +#define ALT_CAN_PROTO_CCTL_ILE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_PROTO_CCTL_ILE register field. */ +#define ALT_CAN_PROTO_CCTL_ILE_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CCTL_ILE field value from a register. */ +#define ALT_CAN_PROTO_CCTL_ILE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_PROTO_CCTL_ILE register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CCTL_ILE_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Status Interrupt Enable - SIE + * + * Status Interrupt Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------- + * ALT_CAN_PROTO_CCTL_SIE_E_DISD | 0x0 | CSTS.RxOk, CSTS.TxOk and CSTS.LEC will still be + * : | | updated, but without affecting interrupt line + * : | | CAN_INT_STATUS and Interrupt register CIR. + * ALT_CAN_PROTO_CCTL_SIE_E_END | 0x1 | When a message transfer is successfully + * : | | completed or a CAN bus error is detected, + * : | | indicated by flags CSTS.RxOk, CSTS.TxOk and + * : | | CSTS.LEC, the interrupt line CAN_INT_STATUS gets + * : | | active (if ILE=1) and CIR.StatusInt is set. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_SIE + * + * CSTS.RxOk, CSTS.TxOk and CSTS.LEC will still be updated, but without affecting + * interrupt line CAN_INT_STATUS and Interrupt register CIR. + */ +#define ALT_CAN_PROTO_CCTL_SIE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_SIE + * + * When a message transfer is successfully completed or a CAN bus error is + * detected, indicated by flags CSTS.RxOk, CSTS.TxOk and CSTS.LEC, the interrupt + * line CAN_INT_STATUS gets active (if ILE=1) and CIR.StatusInt is set. + */ +#define ALT_CAN_PROTO_CCTL_SIE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_SIE register field. */ +#define ALT_CAN_PROTO_CCTL_SIE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_SIE register field. */ +#define ALT_CAN_PROTO_CCTL_SIE_MSB 2 +/* The width in bits of the ALT_CAN_PROTO_CCTL_SIE register field. */ +#define ALT_CAN_PROTO_CCTL_SIE_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CCTL_SIE register field value. */ +#define ALT_CAN_PROTO_CCTL_SIE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_PROTO_CCTL_SIE register field value. */ +#define ALT_CAN_PROTO_CCTL_SIE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_PROTO_CCTL_SIE register field. */ +#define ALT_CAN_PROTO_CCTL_SIE_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CCTL_SIE field value from a register. */ +#define ALT_CAN_PROTO_CCTL_SIE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_PROTO_CCTL_SIE register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CCTL_SIE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Error Interrupt Enable - EIE + * + * Error Interrupt Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------------------- + * ALT_CAN_PROTO_CCTL_EIE_E_DISD | 0x0 | CSTS.PER, CSTS.BOff and CSTS.EWarn flags will + * : | | still be updated, but without affecting + * : | | interrupt line CAN_INT_STATUS and Interrupt + * : | | register CIR + * ALT_CAN_PROTO_CCTL_EIE_E_END | 0x1 | If CSTS.PER flag is one, or CSTS.BOff or + * : | | CSTS.EWarn are changed, the interrupt line + * : | | CAN_INT_STATUS gets active (if ILE=1) and + * : | | CIR.StatusInt is set. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_EIE + * + * CSTS.PER, CSTS.BOff and CSTS.EWarn flags will still be updated, but without + * affecting interrupt line CAN_INT_STATUS and Interrupt register CIR + */ +#define ALT_CAN_PROTO_CCTL_EIE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_EIE + * + * If CSTS.PER flag is one, or CSTS.BOff or CSTS.EWarn are changed, the interrupt + * line CAN_INT_STATUS gets active (if ILE=1) and CIR.StatusInt is set. + */ +#define ALT_CAN_PROTO_CCTL_EIE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_EIE register field. */ +#define ALT_CAN_PROTO_CCTL_EIE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_EIE register field. */ +#define ALT_CAN_PROTO_CCTL_EIE_MSB 3 +/* The width in bits of the ALT_CAN_PROTO_CCTL_EIE register field. */ +#define ALT_CAN_PROTO_CCTL_EIE_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CCTL_EIE register field value. */ +#define ALT_CAN_PROTO_CCTL_EIE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_PROTO_CCTL_EIE register field value. */ +#define ALT_CAN_PROTO_CCTL_EIE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_PROTO_CCTL_EIE register field. */ +#define ALT_CAN_PROTO_CCTL_EIE_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CCTL_EIE field value from a register. */ +#define ALT_CAN_PROTO_CCTL_EIE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_PROTO_CCTL_EIE register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CCTL_EIE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Disable Automatic Retransmission - DAR + * + * Disable Automatic Retransmission + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------- + * ALT_CAN_PROTO_CCTL_DAR_E_END | 0x0 | Automatic Retransmission of not successful + * : | | messages enabled. + * ALT_CAN_PROTO_CCTL_DAR_E_DISD | 0x1 | Automatic Retransmission disabled. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_DAR + * + * Automatic Retransmission of not successful messages enabled. + */ +#define ALT_CAN_PROTO_CCTL_DAR_E_END 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_DAR + * + * Automatic Retransmission disabled. + */ +#define ALT_CAN_PROTO_CCTL_DAR_E_DISD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_DAR register field. */ +#define ALT_CAN_PROTO_CCTL_DAR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_DAR register field. */ +#define ALT_CAN_PROTO_CCTL_DAR_MSB 5 +/* The width in bits of the ALT_CAN_PROTO_CCTL_DAR register field. */ +#define ALT_CAN_PROTO_CCTL_DAR_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CCTL_DAR register field value. */ +#define ALT_CAN_PROTO_CCTL_DAR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_PROTO_CCTL_DAR register field value. */ +#define ALT_CAN_PROTO_CCTL_DAR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_PROTO_CCTL_DAR register field. */ +#define ALT_CAN_PROTO_CCTL_DAR_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CCTL_DAR field value from a register. */ +#define ALT_CAN_PROTO_CCTL_DAR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_PROTO_CCTL_DAR register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CCTL_DAR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Configuration Change Enable - CCE + * + * Configuration Change Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------------- + * ALT_CAN_PROTO_CCTL_CCE_E_NOWRACC | 0x0 | The CPU has no write access to the configuration + * : | | registers. + * ALT_CAN_PROTO_CCTL_CCE_E_WRACC | 0x1 | The CPU has write access to the Bit Timing + * : | | Register CBT (while CCTRL.Init = 1). + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_CCE + * + * The CPU has no write access to the configuration registers. + */ +#define ALT_CAN_PROTO_CCTL_CCE_E_NOWRACC 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_CCE + * + * The CPU has write access to the Bit Timing Register CBT (while CCTRL.Init = 1). + */ +#define ALT_CAN_PROTO_CCTL_CCE_E_WRACC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_CCE register field. */ +#define ALT_CAN_PROTO_CCTL_CCE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_CCE register field. */ +#define ALT_CAN_PROTO_CCTL_CCE_MSB 6 +/* The width in bits of the ALT_CAN_PROTO_CCTL_CCE register field. */ +#define ALT_CAN_PROTO_CCTL_CCE_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CCTL_CCE register field value. */ +#define ALT_CAN_PROTO_CCTL_CCE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_PROTO_CCTL_CCE register field value. */ +#define ALT_CAN_PROTO_CCTL_CCE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_PROTO_CCTL_CCE register field. */ +#define ALT_CAN_PROTO_CCTL_CCE_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CCTL_CCE field value from a register. */ +#define ALT_CAN_PROTO_CCTL_CCE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_PROTO_CCTL_CCE register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CCTL_CCE_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Test Mode Enable - Test + * + * Test Mode Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:-------------------------------------------- + * ALT_CAN_PROTO_CCTL_TEST_E_DISD | 0x0 | Normal Operation. + * ALT_CAN_PROTO_CCTL_TEST_E_TESTMOD | 0x1 | Test Mode. Enables the write access to Test + * : | | Register CTR. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_TEST + * + * Normal Operation. + */ +#define ALT_CAN_PROTO_CCTL_TEST_E_DISD 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_TEST + * + * Test Mode. Enables the write access to Test Register CTR. + */ +#define ALT_CAN_PROTO_CCTL_TEST_E_TESTMOD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_TEST register field. */ +#define ALT_CAN_PROTO_CCTL_TEST_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_TEST register field. */ +#define ALT_CAN_PROTO_CCTL_TEST_MSB 7 +/* The width in bits of the ALT_CAN_PROTO_CCTL_TEST register field. */ +#define ALT_CAN_PROTO_CCTL_TEST_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CCTL_TEST register field value. */ +#define ALT_CAN_PROTO_CCTL_TEST_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_PROTO_CCTL_TEST register field value. */ +#define ALT_CAN_PROTO_CCTL_TEST_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_PROTO_CCTL_TEST register field. */ +#define ALT_CAN_PROTO_CCTL_TEST_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CCTL_TEST field value from a register. */ +#define ALT_CAN_PROTO_CCTL_TEST_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_PROTO_CCTL_TEST register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CCTL_TEST_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Message Object Interrupt Line Enable - MIL + * + * Message Object Interrupt Line Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------- + * ALT_CAN_PROTO_CCTL_MIL_E_DISD | 0x0 | Message Object Interrupt CAN_INT_MO is always + * : | | LOW. If CCTRL.ILE is enabled all message object + * : | | interrupts are routed to line CAN_INT_STATUS + * : | | otherwise no message object interrupt will be + * : | | visible. + * ALT_CAN_PROTO_CCTL_MIL_E_END | 0x1 | Message object interrupts will set CAN_INT_MO to + * : | | one, signal remains one until all pending + * : | | interrupts are processed. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_MIL + * + * Message Object Interrupt CAN_INT_MO is always LOW. If CCTRL.ILE is enabled all + * message object interrupts are routed to line CAN_INT_STATUS otherwise no message + * object interrupt will be visible. + */ +#define ALT_CAN_PROTO_CCTL_MIL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_MIL + * + * Message object interrupts will set CAN_INT_MO to one, signal remains one until + * all pending interrupts are processed. + */ +#define ALT_CAN_PROTO_CCTL_MIL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_MIL register field. */ +#define ALT_CAN_PROTO_CCTL_MIL_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_MIL register field. */ +#define ALT_CAN_PROTO_CCTL_MIL_MSB 17 +/* The width in bits of the ALT_CAN_PROTO_CCTL_MIL register field. */ +#define ALT_CAN_PROTO_CCTL_MIL_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CCTL_MIL register field value. */ +#define ALT_CAN_PROTO_CCTL_MIL_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_PROTO_CCTL_MIL register field value. */ +#define ALT_CAN_PROTO_CCTL_MIL_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_PROTO_CCTL_MIL register field. */ +#define ALT_CAN_PROTO_CCTL_MIL_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CCTL_MIL field value from a register. */ +#define ALT_CAN_PROTO_CCTL_MIL_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_PROTO_CCTL_MIL register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CCTL_MIL_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : DMA Enable for IF1 - DE1 + * + * DMA Enable for IF1 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------- + * ALT_CAN_PROTO_CCTL_DE1_E_DISD | 0x0 | Module DMA output port CAN_IF1DMA is always LOW. + * ALT_CAN_PROTO_CCTL_DE1_E_END | 0x1 | Requesting a message object transfer from IF1 to + * : | | Message RAM or vice versa with IF1CMR.DMAactive + * : | | enabled the end of the transfer will be marked + * : | | with setting port CAN_IF1DMA to one. The port + * : | | remains one until first access to one of the IF1 + * : | | registers. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_DE1 + * + * Module DMA output port CAN_IF1DMA is always LOW. + */ +#define ALT_CAN_PROTO_CCTL_DE1_E_DISD 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_DE1 + * + * Requesting a message object transfer from IF1 to Message RAM or vice versa with + * IF1CMR.DMAactive enabled the end of the transfer will be marked with setting + * port CAN_IF1DMA to one. The port remains one until first access to one of the + * IF1 registers. + */ +#define ALT_CAN_PROTO_CCTL_DE1_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_DE1 register field. */ +#define ALT_CAN_PROTO_CCTL_DE1_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_DE1 register field. */ +#define ALT_CAN_PROTO_CCTL_DE1_MSB 18 +/* The width in bits of the ALT_CAN_PROTO_CCTL_DE1 register field. */ +#define ALT_CAN_PROTO_CCTL_DE1_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CCTL_DE1 register field value. */ +#define ALT_CAN_PROTO_CCTL_DE1_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_PROTO_CCTL_DE1 register field value. */ +#define ALT_CAN_PROTO_CCTL_DE1_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_PROTO_CCTL_DE1 register field. */ +#define ALT_CAN_PROTO_CCTL_DE1_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CCTL_DE1 field value from a register. */ +#define ALT_CAN_PROTO_CCTL_DE1_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_PROTO_CCTL_DE1 register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CCTL_DE1_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : DMA Enable for IF2 - DE2 + * + * DMA Enable for IF2 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------- + * ALT_CAN_PROTO_CCTL_DE2_E_DISD | 0x0 | Module DMA output port CAN_IF2DMA is always LOW. + * ALT_CAN_PROTO_CCTL_DE2_E_END | 0x1 | Requesting a message object transfer from IF2 to + * : | | Message RAM or vice versa with IF2CMR.DMAactive + * : | | enabled the end of the transfer will be marked + * : | | with setting port CAN_IF2DMA to one. The port + * : | | remains one until first access to one of the IF2 + * : | | registers. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_DE2 + * + * Module DMA output port CAN_IF2DMA is always LOW. + */ +#define ALT_CAN_PROTO_CCTL_DE2_E_DISD 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CCTL_DE2 + * + * Requesting a message object transfer from IF2 to Message RAM or vice versa with + * IF2CMR.DMAactive enabled the end of the transfer will be marked with setting + * port CAN_IF2DMA to one. The port remains one until first access to one of the + * IF2 registers. + */ +#define ALT_CAN_PROTO_CCTL_DE2_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CCTL_DE2 register field. */ +#define ALT_CAN_PROTO_CCTL_DE2_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CCTL_DE2 register field. */ +#define ALT_CAN_PROTO_CCTL_DE2_MSB 19 +/* The width in bits of the ALT_CAN_PROTO_CCTL_DE2 register field. */ +#define ALT_CAN_PROTO_CCTL_DE2_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CCTL_DE2 register field value. */ +#define ALT_CAN_PROTO_CCTL_DE2_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_PROTO_CCTL_DE2 register field value. */ +#define ALT_CAN_PROTO_CCTL_DE2_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_PROTO_CCTL_DE2 register field. */ +#define ALT_CAN_PROTO_CCTL_DE2_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CCTL_DE2 field value from a register. */ +#define ALT_CAN_PROTO_CCTL_DE2_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_PROTO_CCTL_DE2 register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CCTL_DE2_SET(value) (((value) << 19) & 0x00080000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_PROTO_CCTL. + */ +struct ALT_CAN_PROTO_CCTL_s +{ + uint32_t Init : 1; /* Initialization */ + uint32_t ILE : 1; /* Module Interrupt Line Enable */ + uint32_t SIE : 1; /* Status Interrupt Enable */ + uint32_t EIE : 1; /* Error Interrupt Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t DAR : 1; /* Disable Automatic Retransmission */ + uint32_t CCE : 1; /* Configuration Change Enable */ + uint32_t Test : 1; /* Test Mode Enable */ + uint32_t : 9; /* *UNDEFINED* */ + uint32_t MIL : 1; /* Message Object Interrupt Line Enable */ + uint32_t DE1 : 1; /* DMA Enable for IF1 */ + uint32_t DE2 : 1; /* DMA Enable for IF2 */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_PROTO_CCTL. */ +typedef volatile struct ALT_CAN_PROTO_CCTL_s ALT_CAN_PROTO_CCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_PROTO_CCTL register from the beginning of the component. */ +#define ALT_CAN_PROTO_CCTL_OFST 0x0 +/* The address of the ALT_CAN_PROTO_CCTL register. */ +#define ALT_CAN_PROTO_CCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CCTL_OFST)) + +/* + * Register : Status Register - CSTS + * + * Status Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------- + * [2:0] | R | 0x7 | Last Error Code + * [3] | R | 0x0 | Transmitted a Message Successfully + * [4] | R | 0x0 | Received a Message Successfully + * [5] | R | 0x0 | Error Passive + * [6] | R | 0x0 | Warning Status + * [7] | R | 0x0 | Bus_Off Status + * [8] | R | 0x0 | Parity Error Detected + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Last Error Code - LEC + * + * The LEC field holds a code which indicates the type of the last error to occur + * on the CAN bus. This field will be cleared to 0 when a message has been + * transferred (reception or transmission) without error. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_PROTO_CSTS_LEC_E_NOERROR | 0x0 | Set together with CSTS.RxOK or CSTS.TxOK. + * ALT_CAN_PROTO_CSTS_LEC_E_STUFFERROR | 0x1 | More than 5 equal bits in a sequence have + * : | | occurred in a part of a received message where + * : | | this is not allowed. + * ALT_CAN_PROTO_CSTS_LEC_E_FORMERROR | 0x2 | A fixed format part of a received frame has the + * : | | wrong format. + * ALT_CAN_PROTO_CSTS_LEC_E_ACKERROR | 0x3 | The message this CAN Core transmitted was not + * : | | acknowledged by another node. + * ALT_CAN_PROTO_CSTS_LEC_E_BIT1ERROR | 0x4 | During the transmission of a message (with the + * : | | exception of the arbitration field), the device + * : | | wanted to send a recessive level (bit of logical + * : | | value 1), but the monitored bus value was + * : | | dominant. + * ALT_CAN_PROTO_CSTS_LEC_E_BIT0ERROR | 0x5 | During the transmission of a message (or + * : | | acknowledge bit, or active error flag, or + * : | | overload flag), the device wanted to send a + * : | | dominant level (data or identifier bit logical + * : | | value 0), but the monitored bus value was + * : | | recessive. During Bus_Off recovery this status + * : | | is set each time a sequence of 11 recessive bits + * : | | has been monitored. This enables the CPU to + * : | | monitor the proceeding of the Bus_Off recovery + * : | | sequence (indicating the bus is not stuck at + * : | | dominant or continuously disturbed). + * ALT_CAN_PROTO_CSTS_LEC_E_CRCERROR | 0x6 | The CRC checksum was incorrect in the message + * : | | received, the CRC received for an incoming + * : | | message does not match with the calculated CRC + * : | | for the received data. + * ALT_CAN_PROTO_CSTS_LEC_E_NOCHANGE | 0x7 | Any read access to the Status Register re + * : | | initializes the LEC to 7. When the LEC shows the + * : | | value 7, no CAN bus event was detected since the + * : | | last CPU read access to the Status Register. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC + * + * Set together with CSTS.RxOK or CSTS.TxOK. + */ +#define ALT_CAN_PROTO_CSTS_LEC_E_NOERROR 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC + * + * More than 5 equal bits in a sequence have occurred in a part of a received + * message where this is not allowed. + */ +#define ALT_CAN_PROTO_CSTS_LEC_E_STUFFERROR 0x1 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC + * + * A fixed format part of a received frame has the wrong format. + */ +#define ALT_CAN_PROTO_CSTS_LEC_E_FORMERROR 0x2 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC + * + * The message this CAN Core transmitted was not acknowledged by another node. + */ +#define ALT_CAN_PROTO_CSTS_LEC_E_ACKERROR 0x3 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC + * + * During the transmission of a message (with the exception of the arbitration + * field), the device wanted to send a recessive level (bit of logical value 1), + * but the monitored bus value was dominant. + */ +#define ALT_CAN_PROTO_CSTS_LEC_E_BIT1ERROR 0x4 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC + * + * During the transmission of a message (or acknowledge bit, or active error flag, + * or overload flag), the device wanted to send a dominant level (data or + * identifier bit logical value 0), but the monitored bus value was recessive. + * During Bus_Off recovery this status is set each time a sequence of 11 recessive + * bits has been monitored. This enables the CPU to monitor the proceeding of the + * Bus_Off recovery sequence (indicating the bus is not stuck at dominant or + * continuously disturbed). + */ +#define ALT_CAN_PROTO_CSTS_LEC_E_BIT0ERROR 0x5 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC + * + * The CRC checksum was incorrect in the message received, the CRC received for an + * incoming message does not match with the calculated CRC for the received data. + */ +#define ALT_CAN_PROTO_CSTS_LEC_E_CRCERROR 0x6 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_LEC + * + * Any read access to the Status Register re initializes the LEC to 7. When the LEC + * shows the value 7, no CAN bus event was detected since the last CPU read access + * to the Status Register. + */ +#define ALT_CAN_PROTO_CSTS_LEC_E_NOCHANGE 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_LEC register field. */ +#define ALT_CAN_PROTO_CSTS_LEC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_LEC register field. */ +#define ALT_CAN_PROTO_CSTS_LEC_MSB 2 +/* The width in bits of the ALT_CAN_PROTO_CSTS_LEC register field. */ +#define ALT_CAN_PROTO_CSTS_LEC_WIDTH 3 +/* The mask used to set the ALT_CAN_PROTO_CSTS_LEC register field value. */ +#define ALT_CAN_PROTO_CSTS_LEC_SET_MSK 0x00000007 +/* The mask used to clear the ALT_CAN_PROTO_CSTS_LEC register field value. */ +#define ALT_CAN_PROTO_CSTS_LEC_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_CAN_PROTO_CSTS_LEC register field. */ +#define ALT_CAN_PROTO_CSTS_LEC_RESET 0x7 +/* Extracts the ALT_CAN_PROTO_CSTS_LEC field value from a register. */ +#define ALT_CAN_PROTO_CSTS_LEC_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_CAN_PROTO_CSTS_LEC register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CSTS_LEC_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : Transmitted a Message Successfully - TxOK + * + * Transmitted a Message Successfully + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------------ + * ALT_CAN_PROTO_CSTS_TXOK_E_NOTXOK | 0x0 | Since this bit was last read by the CPU, no + * : | | message has been successfully transmitted. This + * : | | bit is never reset by CAN internal events. + * ALT_CAN_PROTO_CSTS_TXOK_E_TXOK | 0x1 | Since this bit was last reset by a read access + * : | | of the CPU, a message has been successfully + * : | | (error free and acknowledged by at least one + * : | | other node) transmitted. This bit will be reset + * : | | by reading the Status Register. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_TXOK + * + * Since this bit was last read by the CPU, no message has been successfully + * transmitted. This bit is never reset by CAN internal events. + */ +#define ALT_CAN_PROTO_CSTS_TXOK_E_NOTXOK 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_TXOK + * + * Since this bit was last reset by a read access of the CPU, a message has been + * successfully (error free and acknowledged by at least one other node) + * transmitted. This bit will be reset by reading the Status Register. + */ +#define ALT_CAN_PROTO_CSTS_TXOK_E_TXOK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_TXOK register field. */ +#define ALT_CAN_PROTO_CSTS_TXOK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_TXOK register field. */ +#define ALT_CAN_PROTO_CSTS_TXOK_MSB 3 +/* The width in bits of the ALT_CAN_PROTO_CSTS_TXOK register field. */ +#define ALT_CAN_PROTO_CSTS_TXOK_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CSTS_TXOK register field value. */ +#define ALT_CAN_PROTO_CSTS_TXOK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_PROTO_CSTS_TXOK register field value. */ +#define ALT_CAN_PROTO_CSTS_TXOK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_PROTO_CSTS_TXOK register field. */ +#define ALT_CAN_PROTO_CSTS_TXOK_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CSTS_TXOK field value from a register. */ +#define ALT_CAN_PROTO_CSTS_TXOK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_PROTO_CSTS_TXOK register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CSTS_TXOK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Received a Message Successfully - RxOK + * + * Received a Message Successfully + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------------- + * ALT_CAN_PROTO_CSTS_RXOK_E_NORXOK | 0x0 | Since this bit was read by the CPU, no message + * : | | has been successfully received. This bit is + * : | | never reset by CAN internal events. + * ALT_CAN_PROTO_CSTS_RXOK_E_RXOK | 0x1 | Since this bit was last reset by a read access + * : | | of the CPU, a message has been successfully + * : | | received (independently of the result of + * : | | acceptance filtering). This bit will be reset by + * : | | reading the Status Register. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_RXOK + * + * Since this bit was read by the CPU, no message has been successfully received. + * This bit is never reset by CAN internal events. + */ +#define ALT_CAN_PROTO_CSTS_RXOK_E_NORXOK 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_RXOK + * + * Since this bit was last reset by a read access of the CPU, a message has been + * successfully received (independently of the result of acceptance filtering). + * This bit will be reset by reading the Status Register. + */ +#define ALT_CAN_PROTO_CSTS_RXOK_E_RXOK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_RXOK register field. */ +#define ALT_CAN_PROTO_CSTS_RXOK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_RXOK register field. */ +#define ALT_CAN_PROTO_CSTS_RXOK_MSB 4 +/* The width in bits of the ALT_CAN_PROTO_CSTS_RXOK register field. */ +#define ALT_CAN_PROTO_CSTS_RXOK_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CSTS_RXOK register field value. */ +#define ALT_CAN_PROTO_CSTS_RXOK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_PROTO_CSTS_RXOK register field value. */ +#define ALT_CAN_PROTO_CSTS_RXOK_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_PROTO_CSTS_RXOK register field. */ +#define ALT_CAN_PROTO_CSTS_RXOK_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CSTS_RXOK field value from a register. */ +#define ALT_CAN_PROTO_CSTS_RXOK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_PROTO_CSTS_RXOK register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CSTS_RXOK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Error Passive - EPASS + * + * Error Passive + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------------------------- + * ALT_CAN_PROTO_CSTS_EPASS_E_ACT | 0x0 | The CAN Core is in the error active state. It + * : | | normally takes part in bus communication and + * : | | sends an active error flag when an error has + * : | | been detected. + * ALT_CAN_PROTO_CSTS_EPASS_E_PASSIVE | 0x1 | The CAN Core is in the error passive state as + * : | | defined in the CAN Specification. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_EPASS + * + * The CAN Core is in the error active state. It normally takes part in bus + * communication and sends an active error flag when an error has been detected. + */ +#define ALT_CAN_PROTO_CSTS_EPASS_E_ACT 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_EPASS + * + * The CAN Core is in the error passive state as defined in the CAN Specification. + */ +#define ALT_CAN_PROTO_CSTS_EPASS_E_PASSIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_EPASS register field. */ +#define ALT_CAN_PROTO_CSTS_EPASS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_EPASS register field. */ +#define ALT_CAN_PROTO_CSTS_EPASS_MSB 5 +/* The width in bits of the ALT_CAN_PROTO_CSTS_EPASS register field. */ +#define ALT_CAN_PROTO_CSTS_EPASS_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CSTS_EPASS register field value. */ +#define ALT_CAN_PROTO_CSTS_EPASS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_PROTO_CSTS_EPASS register field value. */ +#define ALT_CAN_PROTO_CSTS_EPASS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_PROTO_CSTS_EPASS register field. */ +#define ALT_CAN_PROTO_CSTS_EPASS_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CSTS_EPASS field value from a register. */ +#define ALT_CAN_PROTO_CSTS_EPASS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_PROTO_CSTS_EPASS register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CSTS_EPASS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Warning Status - EWarn + * + * Warning Status + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_CAN_PROTO_CSTS_EWARN_E_BELOWLIMIT | 0x0 | Both error counters are below the error warning + * : | | limit of 96. + * ALT_CAN_PROTO_CSTS_EWARN_E_ABOVELIMIT | 0x1 | At least one of the error counters in the EML + * : | | has reached the error warning limit of 96. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_EWARN + * + * Both error counters are below the error warning limit of 96. + */ +#define ALT_CAN_PROTO_CSTS_EWARN_E_BELOWLIMIT 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_EWARN + * + * At least one of the error counters in the EML has reached the error warning + * limit of 96. + */ +#define ALT_CAN_PROTO_CSTS_EWARN_E_ABOVELIMIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_EWARN register field. */ +#define ALT_CAN_PROTO_CSTS_EWARN_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_EWARN register field. */ +#define ALT_CAN_PROTO_CSTS_EWARN_MSB 6 +/* The width in bits of the ALT_CAN_PROTO_CSTS_EWARN register field. */ +#define ALT_CAN_PROTO_CSTS_EWARN_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CSTS_EWARN register field value. */ +#define ALT_CAN_PROTO_CSTS_EWARN_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_PROTO_CSTS_EWARN register field value. */ +#define ALT_CAN_PROTO_CSTS_EWARN_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_PROTO_CSTS_EWARN register field. */ +#define ALT_CAN_PROTO_CSTS_EWARN_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CSTS_EWARN field value from a register. */ +#define ALT_CAN_PROTO_CSTS_EWARN_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_PROTO_CSTS_EWARN register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CSTS_EWARN_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Bus_Off Status - BOff + * + * Bus_Off Status + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------ + * ALT_CAN_PROTO_CSTS_BOFF_E_NOTBUSOFF | 0x0 | The CAN module is not Bus_Off. + * ALT_CAN_PROTO_CSTS_BOFF_E_BUSOFF | 0x1 | The CAN module is in Bus_Off state. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_BOFF + * + * The CAN module is not Bus_Off. + */ +#define ALT_CAN_PROTO_CSTS_BOFF_E_NOTBUSOFF 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_BOFF + * + * The CAN module is in Bus_Off state. + */ +#define ALT_CAN_PROTO_CSTS_BOFF_E_BUSOFF 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_BOFF register field. */ +#define ALT_CAN_PROTO_CSTS_BOFF_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_BOFF register field. */ +#define ALT_CAN_PROTO_CSTS_BOFF_MSB 7 +/* The width in bits of the ALT_CAN_PROTO_CSTS_BOFF register field. */ +#define ALT_CAN_PROTO_CSTS_BOFF_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CSTS_BOFF register field value. */ +#define ALT_CAN_PROTO_CSTS_BOFF_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_PROTO_CSTS_BOFF register field value. */ +#define ALT_CAN_PROTO_CSTS_BOFF_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_PROTO_CSTS_BOFF register field. */ +#define ALT_CAN_PROTO_CSTS_BOFF_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CSTS_BOFF field value from a register. */ +#define ALT_CAN_PROTO_CSTS_BOFF_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_PROTO_CSTS_BOFF register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CSTS_BOFF_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Parity Error Detected - PER + * + * Parity Error Detected + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_PROTO_CSTS_PER_E_NONE | 0x0 | No parity error detected since last read access. + * ALT_CAN_PROTO_CSTS_PER_E_ERRORDETECTED | 0x1 | The Parity CheckMechanism has detected a parity + * : | | error in the Message RAM, this bit will be reset + * : | | if Status Register is read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_PER + * + * No parity error detected since last read access. + */ +#define ALT_CAN_PROTO_CSTS_PER_E_NONE 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CSTS_PER + * + * The Parity CheckMechanism has detected a parity error in the Message RAM, this + * bit will be reset if Status Register is read + */ +#define ALT_CAN_PROTO_CSTS_PER_E_ERRORDETECTED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CSTS_PER register field. */ +#define ALT_CAN_PROTO_CSTS_PER_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CSTS_PER register field. */ +#define ALT_CAN_PROTO_CSTS_PER_MSB 8 +/* The width in bits of the ALT_CAN_PROTO_CSTS_PER register field. */ +#define ALT_CAN_PROTO_CSTS_PER_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CSTS_PER register field value. */ +#define ALT_CAN_PROTO_CSTS_PER_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_PROTO_CSTS_PER register field value. */ +#define ALT_CAN_PROTO_CSTS_PER_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_PROTO_CSTS_PER register field. */ +#define ALT_CAN_PROTO_CSTS_PER_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CSTS_PER field value from a register. */ +#define ALT_CAN_PROTO_CSTS_PER_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_PROTO_CSTS_PER register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CSTS_PER_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_PROTO_CSTS. + */ +struct ALT_CAN_PROTO_CSTS_s +{ + const uint32_t LEC : 3; /* Last Error Code */ + const uint32_t TxOK : 1; /* Transmitted a Message Successfully */ + const uint32_t RxOK : 1; /* Received a Message Successfully */ + const uint32_t EPASS : 1; /* Error Passive */ + const uint32_t EWarn : 1; /* Warning Status */ + const uint32_t BOff : 1; /* Bus_Off Status */ + const uint32_t PER : 1; /* Parity Error Detected */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_PROTO_CSTS. */ +typedef volatile struct ALT_CAN_PROTO_CSTS_s ALT_CAN_PROTO_CSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_PROTO_CSTS register from the beginning of the component. */ +#define ALT_CAN_PROTO_CSTS_OFST 0x4 +/* The address of the ALT_CAN_PROTO_CSTS register. */ +#define ALT_CAN_PROTO_CSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CSTS_OFST)) + +/* + * Register : Error Counter Register - CERC + * + * Error Counter Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [7:0] | R | 0x0 | Transmit Error Counter + * [14:8] | R | 0x0 | Receive Error Counter + * [15] | R | 0x0 | Receive Error Passive + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit Error Counter - TEC + * + * Actual state of the Transmit Error Counter. Values between 0 and 255. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CERC_TEC register field. */ +#define ALT_CAN_PROTO_CERC_TEC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CERC_TEC register field. */ +#define ALT_CAN_PROTO_CERC_TEC_MSB 7 +/* The width in bits of the ALT_CAN_PROTO_CERC_TEC register field. */ +#define ALT_CAN_PROTO_CERC_TEC_WIDTH 8 +/* The mask used to set the ALT_CAN_PROTO_CERC_TEC register field value. */ +#define ALT_CAN_PROTO_CERC_TEC_SET_MSK 0x000000ff +/* The mask used to clear the ALT_CAN_PROTO_CERC_TEC register field value. */ +#define ALT_CAN_PROTO_CERC_TEC_CLR_MSK 0xffffff00 +/* The reset value of the ALT_CAN_PROTO_CERC_TEC register field. */ +#define ALT_CAN_PROTO_CERC_TEC_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CERC_TEC field value from a register. */ +#define ALT_CAN_PROTO_CERC_TEC_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_CAN_PROTO_CERC_TEC register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CERC_TEC_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Receive Error Counter - REC + * + * Actual state of the Receive Error Counter. Values between 0 and 127. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CERC_REC register field. */ +#define ALT_CAN_PROTO_CERC_REC_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CERC_REC register field. */ +#define ALT_CAN_PROTO_CERC_REC_MSB 14 +/* The width in bits of the ALT_CAN_PROTO_CERC_REC register field. */ +#define ALT_CAN_PROTO_CERC_REC_WIDTH 7 +/* The mask used to set the ALT_CAN_PROTO_CERC_REC register field value. */ +#define ALT_CAN_PROTO_CERC_REC_SET_MSK 0x00007f00 +/* The mask used to clear the ALT_CAN_PROTO_CERC_REC register field value. */ +#define ALT_CAN_PROTO_CERC_REC_CLR_MSK 0xffff80ff +/* The reset value of the ALT_CAN_PROTO_CERC_REC register field. */ +#define ALT_CAN_PROTO_CERC_REC_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CERC_REC field value from a register. */ +#define ALT_CAN_PROTO_CERC_REC_GET(value) (((value) & 0x00007f00) >> 8) +/* Produces a ALT_CAN_PROTO_CERC_REC register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CERC_REC_SET(value) (((value) << 8) & 0x00007f00) + +/* + * Field : Receive Error Passive - RP + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------ + * ALT_CAN_PROTO_CERC_RP_E_BELOW | 0x0 | The Receive Error Counter is below the error + * : | | passive level. + * ALT_CAN_PROTO_CERC_RP_E_REACHED | 0x1 | The Receive Error Counter has reached the error + * : | | passive level as defined in the CAN + * : | | Specification. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CERC_RP + * + * The Receive Error Counter is below the error passive level. + */ +#define ALT_CAN_PROTO_CERC_RP_E_BELOW 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CERC_RP + * + * The Receive Error Counter has reached the error passive level as defined in the + * CAN Specification. + */ +#define ALT_CAN_PROTO_CERC_RP_E_REACHED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CERC_RP register field. */ +#define ALT_CAN_PROTO_CERC_RP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CERC_RP register field. */ +#define ALT_CAN_PROTO_CERC_RP_MSB 15 +/* The width in bits of the ALT_CAN_PROTO_CERC_RP register field. */ +#define ALT_CAN_PROTO_CERC_RP_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CERC_RP register field value. */ +#define ALT_CAN_PROTO_CERC_RP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_PROTO_CERC_RP register field value. */ +#define ALT_CAN_PROTO_CERC_RP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_PROTO_CERC_RP register field. */ +#define ALT_CAN_PROTO_CERC_RP_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CERC_RP field value from a register. */ +#define ALT_CAN_PROTO_CERC_RP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_PROTO_CERC_RP register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CERC_RP_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_PROTO_CERC. + */ +struct ALT_CAN_PROTO_CERC_s +{ + const uint32_t TEC : 8; /* Transmit Error Counter */ + const uint32_t REC : 7; /* Receive Error Counter */ + const uint32_t RP : 1; /* Receive Error Passive */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_PROTO_CERC. */ +typedef volatile struct ALT_CAN_PROTO_CERC_s ALT_CAN_PROTO_CERC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_PROTO_CERC register from the beginning of the component. */ +#define ALT_CAN_PROTO_CERC_OFST 0x8 +/* The address of the ALT_CAN_PROTO_CERC register. */ +#define ALT_CAN_PROTO_CERC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CERC_OFST)) + +/* + * Register : Bit Timing / BRP Extension Register - CBT + * + * This register is only writable if bits CCTRL.CCE and CCTRL.Init are set. The CAN + * bit time may be programed in the range of [4 .. 25] time quanta. The CAN time + * quantum may be programmed in the range of [1 .. 1024] CAN_CLK periods. For + * details see Application Note 001 "Configuration of Bit Timing". The actual + * interpretation by the hardware of this value is such that one more than the + * value programmed here is used. TSeg1 is the sum of Prop_Seg and Phase_Seg1. + * TSeg2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) + * [TSeg1 + TSeg2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + * + Phase_Seg2] tq. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------- + * [5:0] | RW | 0x1 | Baud Rate Prescaler + * [7:6] | RW | 0x0 | (Re) Synchronization Jump Width + * [11:8] | RW | 0x3 | The time segment before the sample point + * [14:12] | RW | 0x2 | The time segment after the sample point + * [15] | ??? | 0x0 | *UNDEFINED* + * [19:16] | RW | 0x0 | Baud Rate Prescaler Extension + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Baud Rate Prescaler - BRP + * + * The value by which the oscillator frequency is divided for generating the bit + * time quanta. The bit time is built up from a multiple of this quanta. Valid + * values for the Baud Rate Prescaler are [0 .. 63]. The actual interpretation by + * the hardware of this value is such that one more than the value programmed here + * is used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CBT_BRP register field. */ +#define ALT_CAN_PROTO_CBT_BRP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CBT_BRP register field. */ +#define ALT_CAN_PROTO_CBT_BRP_MSB 5 +/* The width in bits of the ALT_CAN_PROTO_CBT_BRP register field. */ +#define ALT_CAN_PROTO_CBT_BRP_WIDTH 6 +/* The mask used to set the ALT_CAN_PROTO_CBT_BRP register field value. */ +#define ALT_CAN_PROTO_CBT_BRP_SET_MSK 0x0000003f +/* The mask used to clear the ALT_CAN_PROTO_CBT_BRP register field value. */ +#define ALT_CAN_PROTO_CBT_BRP_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_CAN_PROTO_CBT_BRP register field. */ +#define ALT_CAN_PROTO_CBT_BRP_RESET 0x1 +/* Extracts the ALT_CAN_PROTO_CBT_BRP field value from a register. */ +#define ALT_CAN_PROTO_CBT_BRP_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_CAN_PROTO_CBT_BRP register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CBT_BRP_SET(value) (((value) << 0) & 0x0000003f) + +/* + * Field : (Re) Synchronization Jump Width - SJW + * + * Valid programmed values are [0 .. 3]. The actual interpretation by the hardware + * of this value is such that one more than the value programmed here is used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CBT_SJW register field. */ +#define ALT_CAN_PROTO_CBT_SJW_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CBT_SJW register field. */ +#define ALT_CAN_PROTO_CBT_SJW_MSB 7 +/* The width in bits of the ALT_CAN_PROTO_CBT_SJW register field. */ +#define ALT_CAN_PROTO_CBT_SJW_WIDTH 2 +/* The mask used to set the ALT_CAN_PROTO_CBT_SJW register field value. */ +#define ALT_CAN_PROTO_CBT_SJW_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_CAN_PROTO_CBT_SJW register field value. */ +#define ALT_CAN_PROTO_CBT_SJW_CLR_MSK 0xffffff3f +/* The reset value of the ALT_CAN_PROTO_CBT_SJW register field. */ +#define ALT_CAN_PROTO_CBT_SJW_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CBT_SJW field value from a register. */ +#define ALT_CAN_PROTO_CBT_SJW_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_CAN_PROTO_CBT_SJW register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CBT_SJW_SET(value) (((value) << 6) & 0x000000c0) + +/* + * Field : The time segment before the sample point - TSeg1 + * + * Valid values for TSeg1 are [1 .. 15]. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CBT_TSEG1 register field. */ +#define ALT_CAN_PROTO_CBT_TSEG1_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CBT_TSEG1 register field. */ +#define ALT_CAN_PROTO_CBT_TSEG1_MSB 11 +/* The width in bits of the ALT_CAN_PROTO_CBT_TSEG1 register field. */ +#define ALT_CAN_PROTO_CBT_TSEG1_WIDTH 4 +/* The mask used to set the ALT_CAN_PROTO_CBT_TSEG1 register field value. */ +#define ALT_CAN_PROTO_CBT_TSEG1_SET_MSK 0x00000f00 +/* The mask used to clear the ALT_CAN_PROTO_CBT_TSEG1 register field value. */ +#define ALT_CAN_PROTO_CBT_TSEG1_CLR_MSK 0xfffff0ff +/* The reset value of the ALT_CAN_PROTO_CBT_TSEG1 register field. */ +#define ALT_CAN_PROTO_CBT_TSEG1_RESET 0x3 +/* Extracts the ALT_CAN_PROTO_CBT_TSEG1 field value from a register. */ +#define ALT_CAN_PROTO_CBT_TSEG1_GET(value) (((value) & 0x00000f00) >> 8) +/* Produces a ALT_CAN_PROTO_CBT_TSEG1 register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CBT_TSEG1_SET(value) (((value) << 8) & 0x00000f00) + +/* + * Field : The time segment after the sample point - TSeg2 + * + * Valid values for TSeg2 are [0 .. 7]. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CBT_TSEG2 register field. */ +#define ALT_CAN_PROTO_CBT_TSEG2_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CBT_TSEG2 register field. */ +#define ALT_CAN_PROTO_CBT_TSEG2_MSB 14 +/* The width in bits of the ALT_CAN_PROTO_CBT_TSEG2 register field. */ +#define ALT_CAN_PROTO_CBT_TSEG2_WIDTH 3 +/* The mask used to set the ALT_CAN_PROTO_CBT_TSEG2 register field value. */ +#define ALT_CAN_PROTO_CBT_TSEG2_SET_MSK 0x00007000 +/* The mask used to clear the ALT_CAN_PROTO_CBT_TSEG2 register field value. */ +#define ALT_CAN_PROTO_CBT_TSEG2_CLR_MSK 0xffff8fff +/* The reset value of the ALT_CAN_PROTO_CBT_TSEG2 register field. */ +#define ALT_CAN_PROTO_CBT_TSEG2_RESET 0x2 +/* Extracts the ALT_CAN_PROTO_CBT_TSEG2 field value from a register. */ +#define ALT_CAN_PROTO_CBT_TSEG2_GET(value) (((value) & 0x00007000) >> 12) +/* Produces a ALT_CAN_PROTO_CBT_TSEG2 register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CBT_TSEG2_SET(value) (((value) << 12) & 0x00007000) + +/* + * Field : Baud Rate Prescaler Extension - BRPE + * + * By programming BRPE the Baud Rate Prescaler can be extended to values up to + * 1023. The actual interpretation by the hardware is that one more than the value + * programmed by BRPE (MSBs) and BRP (LSBs) is used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CBT_BRPE register field. */ +#define ALT_CAN_PROTO_CBT_BRPE_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CBT_BRPE register field. */ +#define ALT_CAN_PROTO_CBT_BRPE_MSB 19 +/* The width in bits of the ALT_CAN_PROTO_CBT_BRPE register field. */ +#define ALT_CAN_PROTO_CBT_BRPE_WIDTH 4 +/* The mask used to set the ALT_CAN_PROTO_CBT_BRPE register field value. */ +#define ALT_CAN_PROTO_CBT_BRPE_SET_MSK 0x000f0000 +/* The mask used to clear the ALT_CAN_PROTO_CBT_BRPE register field value. */ +#define ALT_CAN_PROTO_CBT_BRPE_CLR_MSK 0xfff0ffff +/* The reset value of the ALT_CAN_PROTO_CBT_BRPE register field. */ +#define ALT_CAN_PROTO_CBT_BRPE_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CBT_BRPE field value from a register. */ +#define ALT_CAN_PROTO_CBT_BRPE_GET(value) (((value) & 0x000f0000) >> 16) +/* Produces a ALT_CAN_PROTO_CBT_BRPE register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CBT_BRPE_SET(value) (((value) << 16) & 0x000f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_PROTO_CBT. + */ +struct ALT_CAN_PROTO_CBT_s +{ + uint32_t BRP : 6; /* Baud Rate Prescaler */ + uint32_t SJW : 2; /* (Re) Synchronization Jump Width */ + uint32_t TSeg1 : 4; /* The time segment before the sample point */ + uint32_t TSeg2 : 3; /* The time segment after the sample point */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t BRPE : 4; /* Baud Rate Prescaler Extension */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_PROTO_CBT. */ +typedef volatile struct ALT_CAN_PROTO_CBT_s ALT_CAN_PROTO_CBT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_PROTO_CBT register from the beginning of the component. */ +#define ALT_CAN_PROTO_CBT_OFST 0xc +/* The address of the ALT_CAN_PROTO_CBT register. */ +#define ALT_CAN_PROTO_CBT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CBT_OFST)) + +/* + * Register : Interrupt Register - CIR + * + * If several interrupts are pending, the CAN Interrupt Register will point to the + * pending interrupt with the highest priority, disregarding their chronological + * order. An interrupt remains pending until the CPU has cleared it. If IntID is + * different from 0x00 and CCTRL.MIL is set, the interrupt port CAN_INT_MO is + * active. The interrupt port remains active until IntID is back to value 0x00 (the + * cause of the interrupt is reset) or until CCTRL.MIL is reset. If CCTRL.ILE is + * set and CCTRL.MIL is reseted the Message Object interrupts will be routed to + * interrupt port CAN_INT_STATUS. The interrupt port remains active until IntID is + * back to value 0x00 (the cause of the interrupt is reset) or until CCTRL.MIL is + * set or CCTRL.ILE is reset. + * + * The Message Object's interrupt priority decreases with increasing message + * number. + * + * A message interrupt is cleared by clearing the Message Object's IntPnd bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [7:0] | R | 0x0 | Interrupt Identifier + * [14:8] | ??? | 0x0 | *UNDEFINED* + * [15] | R | 0x0 | A Status Interrupt has occurred + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Identifier - IntId + * + * 0x00 No Message Object interrupt is pending. + * + * 0x01-0x80 Number of Message Object which caused the interrupt. + * + * 0x81-0xFF unused. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CIR_INTID register field. */ +#define ALT_CAN_PROTO_CIR_INTID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CIR_INTID register field. */ +#define ALT_CAN_PROTO_CIR_INTID_MSB 7 +/* The width in bits of the ALT_CAN_PROTO_CIR_INTID register field. */ +#define ALT_CAN_PROTO_CIR_INTID_WIDTH 8 +/* The mask used to set the ALT_CAN_PROTO_CIR_INTID register field value. */ +#define ALT_CAN_PROTO_CIR_INTID_SET_MSK 0x000000ff +/* The mask used to clear the ALT_CAN_PROTO_CIR_INTID register field value. */ +#define ALT_CAN_PROTO_CIR_INTID_CLR_MSK 0xffffff00 +/* The reset value of the ALT_CAN_PROTO_CIR_INTID register field. */ +#define ALT_CAN_PROTO_CIR_INTID_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CIR_INTID field value from a register. */ +#define ALT_CAN_PROTO_CIR_INTID_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_CAN_PROTO_CIR_INTID register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CIR_INTID_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : A Status Interrupt has occurred - StatusInt + * + * The Status Interrupt is cleared by reading the Status Register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CIR_STATINT register field. */ +#define ALT_CAN_PROTO_CIR_STATINT_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CIR_STATINT register field. */ +#define ALT_CAN_PROTO_CIR_STATINT_MSB 15 +/* The width in bits of the ALT_CAN_PROTO_CIR_STATINT register field. */ +#define ALT_CAN_PROTO_CIR_STATINT_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CIR_STATINT register field value. */ +#define ALT_CAN_PROTO_CIR_STATINT_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_PROTO_CIR_STATINT register field value. */ +#define ALT_CAN_PROTO_CIR_STATINT_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_PROTO_CIR_STATINT register field. */ +#define ALT_CAN_PROTO_CIR_STATINT_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CIR_STATINT field value from a register. */ +#define ALT_CAN_PROTO_CIR_STATINT_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_PROTO_CIR_STATINT register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CIR_STATINT_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_PROTO_CIR. + */ +struct ALT_CAN_PROTO_CIR_s +{ + const uint32_t IntId : 8; /* Interrupt Identifier */ + uint32_t : 7; /* *UNDEFINED* */ + const uint32_t StatusInt : 1; /* A Status Interrupt has occurred */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_PROTO_CIR. */ +typedef volatile struct ALT_CAN_PROTO_CIR_s ALT_CAN_PROTO_CIR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_PROTO_CIR register from the beginning of the component. */ +#define ALT_CAN_PROTO_CIR_OFST 0x10 +/* The address of the ALT_CAN_PROTO_CIR register. */ +#define ALT_CAN_PROTO_CIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CIR_OFST)) + +/* + * Register : Test Register - CTR + * + * The Test Mode is entered by setting bit CCTRL.Test to one. In Test Mode the bits + * EXL, Tx1, Tx0, LBack and Silent in the Test Register are writable. Bit Rx + * monitors the state of pin CAN_RXD and therefore is only readable. All Test + * Register functions are disabled when bit Test is reset to zero. + * + * Loop Back Mode and CAN_TXD Control Mode are hardware test modes, not to be used + * by application programs. + * + * Note: This register is only writable if bit CCTRL.Test is set. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------- + * [2:0] | ??? | 0x0 | *UNDEFINED* + * [3] | RW | 0x0 | Silent Mode + * [4] | RW | 0x0 | Loop Back Mode + * [6:5] | RW | 0x0 | Transmit Pin + * [7] | R | Unknown | Receive Pin + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Silent Mode - Silent + * + * Silent Mode + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------------------- + * ALT_CAN_PROTO_CTR_SILENT_E_NORMAL | 0x0 | Normal operation. + * ALT_CAN_PROTO_CTR_SILENT_E_SILENT | 0x1 | The CAN is in Silent Mode. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CTR_SILENT + * + * Normal operation. + */ +#define ALT_CAN_PROTO_CTR_SILENT_E_NORMAL 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CTR_SILENT + * + * The CAN is in Silent Mode. + */ +#define ALT_CAN_PROTO_CTR_SILENT_E_SILENT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CTR_SILENT register field. */ +#define ALT_CAN_PROTO_CTR_SILENT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CTR_SILENT register field. */ +#define ALT_CAN_PROTO_CTR_SILENT_MSB 3 +/* The width in bits of the ALT_CAN_PROTO_CTR_SILENT register field. */ +#define ALT_CAN_PROTO_CTR_SILENT_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CTR_SILENT register field value. */ +#define ALT_CAN_PROTO_CTR_SILENT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_PROTO_CTR_SILENT register field value. */ +#define ALT_CAN_PROTO_CTR_SILENT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_PROTO_CTR_SILENT register field. */ +#define ALT_CAN_PROTO_CTR_SILENT_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CTR_SILENT field value from a register. */ +#define ALT_CAN_PROTO_CTR_SILENT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_PROTO_CTR_SILENT register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CTR_SILENT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Loop Back Mode - LBack + * + * Loop Back Mode + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------- + * ALT_CAN_PROTO_CTR_LBACK_E_DISD | 0x0 | Loop Back Mode is disabled. + * ALT_CAN_PROTO_CTR_LBACK_E_END | 0x1 | Loop Back Mode is enabled. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CTR_LBACK + * + * Loop Back Mode is disabled. + */ +#define ALT_CAN_PROTO_CTR_LBACK_E_DISD 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CTR_LBACK + * + * Loop Back Mode is enabled. + */ +#define ALT_CAN_PROTO_CTR_LBACK_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CTR_LBACK register field. */ +#define ALT_CAN_PROTO_CTR_LBACK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CTR_LBACK register field. */ +#define ALT_CAN_PROTO_CTR_LBACK_MSB 4 +/* The width in bits of the ALT_CAN_PROTO_CTR_LBACK register field. */ +#define ALT_CAN_PROTO_CTR_LBACK_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CTR_LBACK register field value. */ +#define ALT_CAN_PROTO_CTR_LBACK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_PROTO_CTR_LBACK register field value. */ +#define ALT_CAN_PROTO_CTR_LBACK_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_PROTO_CTR_LBACK register field. */ +#define ALT_CAN_PROTO_CTR_LBACK_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CTR_LBACK field value from a register. */ +#define ALT_CAN_PROTO_CTR_LBACK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_PROTO_CTR_LBACK register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CTR_LBACK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Transmit Pin - Tx + * + * Controls CAN_TXD pin. Setting to non-zero disturbs message transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_CAN_PROTO_CTR_TX_E_RST | 0x0 | Reset value, CAN_TXD is controlled by the + * : | | CAN_Core. + * ALT_CAN_PROTO_CTR_TX_E_SMPL | 0x1 | Sample Point can be monitored at CAN_TXD pin. + * ALT_CAN_PROTO_CTR_TX_E_DOMINANT | 0x2 | CAN_TXD pin drives a dominant (0) value. + * ALT_CAN_PROTO_CTR_TX_E_RECESSIVE | 0x3 | CAN_TXD pin drives a recessive (1) value. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CTR_TX + * + * Reset value, CAN_TXD is controlled by the CAN_Core. + */ +#define ALT_CAN_PROTO_CTR_TX_E_RST 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CTR_TX + * + * Sample Point can be monitored at CAN_TXD pin. + */ +#define ALT_CAN_PROTO_CTR_TX_E_SMPL 0x1 +/* + * Enumerated value for register field ALT_CAN_PROTO_CTR_TX + * + * CAN_TXD pin drives a dominant (0) value. + */ +#define ALT_CAN_PROTO_CTR_TX_E_DOMINANT 0x2 +/* + * Enumerated value for register field ALT_CAN_PROTO_CTR_TX + * + * CAN_TXD pin drives a recessive (1) value. + */ +#define ALT_CAN_PROTO_CTR_TX_E_RECESSIVE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CTR_TX register field. */ +#define ALT_CAN_PROTO_CTR_TX_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CTR_TX register field. */ +#define ALT_CAN_PROTO_CTR_TX_MSB 6 +/* The width in bits of the ALT_CAN_PROTO_CTR_TX register field. */ +#define ALT_CAN_PROTO_CTR_TX_WIDTH 2 +/* The mask used to set the ALT_CAN_PROTO_CTR_TX register field value. */ +#define ALT_CAN_PROTO_CTR_TX_SET_MSK 0x00000060 +/* The mask used to clear the ALT_CAN_PROTO_CTR_TX register field value. */ +#define ALT_CAN_PROTO_CTR_TX_CLR_MSK 0xffffff9f +/* The reset value of the ALT_CAN_PROTO_CTR_TX register field. */ +#define ALT_CAN_PROTO_CTR_TX_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CTR_TX field value from a register. */ +#define ALT_CAN_PROTO_CTR_TX_GET(value) (((value) & 0x00000060) >> 5) +/* Produces a ALT_CAN_PROTO_CTR_TX register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CTR_TX_SET(value) (((value) << 5) & 0x00000060) + +/* + * Field : Receive Pin - Rx + * + * Monitors the actual value of the CAN_RXD pin. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------- + * ALT_CAN_PROTO_CTR_RX_E_DOMINANT | 0x0 | The CAN bus is dominant (CAN_RXD = 0). + * ALT_CAN_PROTO_CTR_RX_E_RECESSIVE | 0x1 | The CAN bus is recessive (CAN_RXD = 1). + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CTR_RX + * + * The CAN bus is dominant (CAN_RXD = 0). + */ +#define ALT_CAN_PROTO_CTR_RX_E_DOMINANT 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CTR_RX + * + * The CAN bus is recessive (CAN_RXD = 1). + */ +#define ALT_CAN_PROTO_CTR_RX_E_RECESSIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CTR_RX register field. */ +#define ALT_CAN_PROTO_CTR_RX_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CTR_RX register field. */ +#define ALT_CAN_PROTO_CTR_RX_MSB 7 +/* The width in bits of the ALT_CAN_PROTO_CTR_RX register field. */ +#define ALT_CAN_PROTO_CTR_RX_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CTR_RX register field value. */ +#define ALT_CAN_PROTO_CTR_RX_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_PROTO_CTR_RX register field value. */ +#define ALT_CAN_PROTO_CTR_RX_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_PROTO_CTR_RX register field is UNKNOWN. */ +#define ALT_CAN_PROTO_CTR_RX_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CTR_RX field value from a register. */ +#define ALT_CAN_PROTO_CTR_RX_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_PROTO_CTR_RX register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CTR_RX_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_PROTO_CTR. + */ +struct ALT_CAN_PROTO_CTR_s +{ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t Silent : 1; /* Silent Mode */ + uint32_t LBack : 1; /* Loop Back Mode */ + uint32_t Tx : 2; /* Transmit Pin */ + const uint32_t Rx : 1; /* Receive Pin */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_PROTO_CTR. */ +typedef volatile struct ALT_CAN_PROTO_CTR_s ALT_CAN_PROTO_CTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_PROTO_CTR register from the beginning of the component. */ +#define ALT_CAN_PROTO_CTR_OFST 0x14 +/* The address of the ALT_CAN_PROTO_CTR register. */ +#define ALT_CAN_PROTO_CTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CTR_OFST)) + +/* + * Register : Function Register - CFR + * + * The Function Register controls the features RAM_Initialisation and Power_Down + * also by application register. + * + * The CAN module can be prepared for Power_Down by setting the port + * CAN_CLKSTOP_REQ to one or writing to CFR.ClkStReq a one. The power down state is + * left by setting port CAN_CLKSTOP_REQ to zero or writing to CFR.ClkStReq a zero, + * acknowledged by CAN_CLKSTOP_ACK is going to zero as well as CFR.ClkStAck. The + * CCTRL.Init bit is left one and has to be written by the application to re-enable + * CAN transfers. + * + * Note: It's recommended to use either the ports CAN_CLKSTOP_REQ and + * CAN_CLKSTOP_ACK or the CCTRL.ClkStReq and CFR.ClkStAck. The application + * CFR.ClkStReq showsalso the actual status of the portCAN_CLKSTOP_REQ. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | R | 0x0 | Clock Stop Acknowledgement + * [1] | RW | 0x0 | Clock Stop Request + * [2] | ??? | 0x0 | *UNDEFINED* + * [3] | RW | 0x0 | Request for automatic RAM Initialization + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clock Stop Acknowledgement - ClkStAck + * + * Clock Stop Acknowledgement + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CFR_CLKSTACK register field. */ +#define ALT_CAN_PROTO_CFR_CLKSTACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CFR_CLKSTACK register field. */ +#define ALT_CAN_PROTO_CFR_CLKSTACK_MSB 0 +/* The width in bits of the ALT_CAN_PROTO_CFR_CLKSTACK register field. */ +#define ALT_CAN_PROTO_CFR_CLKSTACK_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CFR_CLKSTACK register field value. */ +#define ALT_CAN_PROTO_CFR_CLKSTACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_PROTO_CFR_CLKSTACK register field value. */ +#define ALT_CAN_PROTO_CFR_CLKSTACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_PROTO_CFR_CLKSTACK register field. */ +#define ALT_CAN_PROTO_CFR_CLKSTACK_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CFR_CLKSTACK field value from a register. */ +#define ALT_CAN_PROTO_CFR_CLKSTACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_PROTO_CFR_CLKSTACK register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CFR_CLKSTACK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Clock Stop Request - ClkStReq + * + * Clock Stop Request + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CFR_CLKSTREQ register field. */ +#define ALT_CAN_PROTO_CFR_CLKSTREQ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CFR_CLKSTREQ register field. */ +#define ALT_CAN_PROTO_CFR_CLKSTREQ_MSB 1 +/* The width in bits of the ALT_CAN_PROTO_CFR_CLKSTREQ register field. */ +#define ALT_CAN_PROTO_CFR_CLKSTREQ_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CFR_CLKSTREQ register field value. */ +#define ALT_CAN_PROTO_CFR_CLKSTREQ_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_PROTO_CFR_CLKSTREQ register field value. */ +#define ALT_CAN_PROTO_CFR_CLKSTREQ_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_PROTO_CFR_CLKSTREQ register field. */ +#define ALT_CAN_PROTO_CFR_CLKSTREQ_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CFR_CLKSTREQ field value from a register. */ +#define ALT_CAN_PROTO_CFR_CLKSTREQ_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_PROTO_CFR_CLKSTREQ register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CFR_CLKSTREQ_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Request for automatic RAM Initialization - RAMinit + * + * Request for automatic RAM Initialization + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_PROTO_CFR_RAMINIT_E_NOAUTO | 0x0 | No automatic RAM Initialization is requested, if + * : | | once a ram initialization is started a write of + * : | | a zero will be ignored. The Bit is cleared by + * : | | hardware, after RAM Initialization is completed. + * ALT_CAN_PROTO_CFR_RAMINIT_E_STARTAUTO | 0x1 | Start automatic RAM Initialization. All message + * : | | objects will be written with zeros and the + * : | | parity bits will be set. The RAMInit Bit will + * : | | return to zero after the RAM-Initialization + * : | | process is completed. A RAM Initialization + * : | | Request is only possible if CCTRL.Init is set. + * : | | The duration of the automatic RAM Initialization + * : | | is messagebuffer-size + 4 host_clock cycles. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_CFR_RAMINIT + * + * No automatic RAM Initialization is requested, if once a ram initialization is + * started a write of a zero will be ignored. The Bit is cleared by hardware, after + * RAM Initialization is completed. + */ +#define ALT_CAN_PROTO_CFR_RAMINIT_E_NOAUTO 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_CFR_RAMINIT + * + * Start automatic RAM Initialization. All message objects will be written with + * zeros and the parity bits will be set. The RAMInit Bit will return to zero after + * the RAM-Initialization process is completed. A RAM Initialization Request is + * only possible if CCTRL.Init is set. The duration of the automatic RAM + * Initialization is messagebuffer-size + 4 host_clock cycles. + */ +#define ALT_CAN_PROTO_CFR_RAMINIT_E_STARTAUTO 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CFR_RAMINIT register field. */ +#define ALT_CAN_PROTO_CFR_RAMINIT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CFR_RAMINIT register field. */ +#define ALT_CAN_PROTO_CFR_RAMINIT_MSB 3 +/* The width in bits of the ALT_CAN_PROTO_CFR_RAMINIT register field. */ +#define ALT_CAN_PROTO_CFR_RAMINIT_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_CFR_RAMINIT register field value. */ +#define ALT_CAN_PROTO_CFR_RAMINIT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_PROTO_CFR_RAMINIT register field value. */ +#define ALT_CAN_PROTO_CFR_RAMINIT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_PROTO_CFR_RAMINIT register field. */ +#define ALT_CAN_PROTO_CFR_RAMINIT_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_CFR_RAMINIT field value from a register. */ +#define ALT_CAN_PROTO_CFR_RAMINIT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_PROTO_CFR_RAMINIT register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CFR_RAMINIT_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_PROTO_CFR. + */ +struct ALT_CAN_PROTO_CFR_s +{ + const uint32_t ClkStAck : 1; /* Clock Stop Acknowledgement */ + uint32_t ClkStReq : 1; /* Clock Stop Request */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t RAMinit : 1; /* Request for automatic RAM Initialization */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_PROTO_CFR. */ +typedef volatile struct ALT_CAN_PROTO_CFR_s ALT_CAN_PROTO_CFR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_PROTO_CFR register from the beginning of the component. */ +#define ALT_CAN_PROTO_CFR_OFST 0x18 +/* The address of the ALT_CAN_PROTO_CFR register. */ +#define ALT_CAN_PROTO_CFR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CFR_OFST)) + +/* + * Register : Core Release Register - CRR + * + * Core Release Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [7:0] | R | 0x28 | Design Time Stamp, Day + * [15:8] | R | 0x11 | Design Time Stamp, Month + * [19:16] | R | 0x6 | Design Time Stamp, Year + * [27:20] | R | 0x11 | Step of Core Release + * [31:28] | R | 0x1 | Core Release + * + */ +/* + * Field : Design Time Stamp, Day - DAY + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CRR_DAY register field. */ +#define ALT_CAN_PROTO_CRR_DAY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CRR_DAY register field. */ +#define ALT_CAN_PROTO_CRR_DAY_MSB 7 +/* The width in bits of the ALT_CAN_PROTO_CRR_DAY register field. */ +#define ALT_CAN_PROTO_CRR_DAY_WIDTH 8 +/* The mask used to set the ALT_CAN_PROTO_CRR_DAY register field value. */ +#define ALT_CAN_PROTO_CRR_DAY_SET_MSK 0x000000ff +/* The mask used to clear the ALT_CAN_PROTO_CRR_DAY register field value. */ +#define ALT_CAN_PROTO_CRR_DAY_CLR_MSK 0xffffff00 +/* The reset value of the ALT_CAN_PROTO_CRR_DAY register field. */ +#define ALT_CAN_PROTO_CRR_DAY_RESET 0x28 +/* Extracts the ALT_CAN_PROTO_CRR_DAY field value from a register. */ +#define ALT_CAN_PROTO_CRR_DAY_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_CAN_PROTO_CRR_DAY register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CRR_DAY_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Design Time Stamp, Month - MON + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CRR_MON register field. */ +#define ALT_CAN_PROTO_CRR_MON_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CRR_MON register field. */ +#define ALT_CAN_PROTO_CRR_MON_MSB 15 +/* The width in bits of the ALT_CAN_PROTO_CRR_MON register field. */ +#define ALT_CAN_PROTO_CRR_MON_WIDTH 8 +/* The mask used to set the ALT_CAN_PROTO_CRR_MON register field value. */ +#define ALT_CAN_PROTO_CRR_MON_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_CAN_PROTO_CRR_MON register field value. */ +#define ALT_CAN_PROTO_CRR_MON_CLR_MSK 0xffff00ff +/* The reset value of the ALT_CAN_PROTO_CRR_MON register field. */ +#define ALT_CAN_PROTO_CRR_MON_RESET 0x11 +/* Extracts the ALT_CAN_PROTO_CRR_MON field value from a register. */ +#define ALT_CAN_PROTO_CRR_MON_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_CAN_PROTO_CRR_MON register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CRR_MON_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Design Time Stamp, Year - YEAR + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CRR_YEAR register field. */ +#define ALT_CAN_PROTO_CRR_YEAR_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CRR_YEAR register field. */ +#define ALT_CAN_PROTO_CRR_YEAR_MSB 19 +/* The width in bits of the ALT_CAN_PROTO_CRR_YEAR register field. */ +#define ALT_CAN_PROTO_CRR_YEAR_WIDTH 4 +/* The mask used to set the ALT_CAN_PROTO_CRR_YEAR register field value. */ +#define ALT_CAN_PROTO_CRR_YEAR_SET_MSK 0x000f0000 +/* The mask used to clear the ALT_CAN_PROTO_CRR_YEAR register field value. */ +#define ALT_CAN_PROTO_CRR_YEAR_CLR_MSK 0xfff0ffff +/* The reset value of the ALT_CAN_PROTO_CRR_YEAR register field. */ +#define ALT_CAN_PROTO_CRR_YEAR_RESET 0x6 +/* Extracts the ALT_CAN_PROTO_CRR_YEAR field value from a register. */ +#define ALT_CAN_PROTO_CRR_YEAR_GET(value) (((value) & 0x000f0000) >> 16) +/* Produces a ALT_CAN_PROTO_CRR_YEAR register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CRR_YEAR_SET(value) (((value) << 16) & 0x000f0000) + +/* + * Field : Step of Core Release - STEP + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CRR_STEP register field. */ +#define ALT_CAN_PROTO_CRR_STEP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CRR_STEP register field. */ +#define ALT_CAN_PROTO_CRR_STEP_MSB 27 +/* The width in bits of the ALT_CAN_PROTO_CRR_STEP register field. */ +#define ALT_CAN_PROTO_CRR_STEP_WIDTH 8 +/* The mask used to set the ALT_CAN_PROTO_CRR_STEP register field value. */ +#define ALT_CAN_PROTO_CRR_STEP_SET_MSK 0x0ff00000 +/* The mask used to clear the ALT_CAN_PROTO_CRR_STEP register field value. */ +#define ALT_CAN_PROTO_CRR_STEP_CLR_MSK 0xf00fffff +/* The reset value of the ALT_CAN_PROTO_CRR_STEP register field. */ +#define ALT_CAN_PROTO_CRR_STEP_RESET 0x11 +/* Extracts the ALT_CAN_PROTO_CRR_STEP field value from a register. */ +#define ALT_CAN_PROTO_CRR_STEP_GET(value) (((value) & 0x0ff00000) >> 20) +/* Produces a ALT_CAN_PROTO_CRR_STEP register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CRR_STEP_SET(value) (((value) << 20) & 0x0ff00000) + +/* + * Field : Core Release - REL + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_CRR_REL register field. */ +#define ALT_CAN_PROTO_CRR_REL_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_CRR_REL register field. */ +#define ALT_CAN_PROTO_CRR_REL_MSB 31 +/* The width in bits of the ALT_CAN_PROTO_CRR_REL register field. */ +#define ALT_CAN_PROTO_CRR_REL_WIDTH 4 +/* The mask used to set the ALT_CAN_PROTO_CRR_REL register field value. */ +#define ALT_CAN_PROTO_CRR_REL_SET_MSK 0xf0000000 +/* The mask used to clear the ALT_CAN_PROTO_CRR_REL register field value. */ +#define ALT_CAN_PROTO_CRR_REL_CLR_MSK 0x0fffffff +/* The reset value of the ALT_CAN_PROTO_CRR_REL register field. */ +#define ALT_CAN_PROTO_CRR_REL_RESET 0x1 +/* Extracts the ALT_CAN_PROTO_CRR_REL field value from a register. */ +#define ALT_CAN_PROTO_CRR_REL_GET(value) (((value) & 0xf0000000) >> 28) +/* Produces a ALT_CAN_PROTO_CRR_REL register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_CRR_REL_SET(value) (((value) << 28) & 0xf0000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_PROTO_CRR. + */ +struct ALT_CAN_PROTO_CRR_s +{ + const uint32_t DAY : 8; /* Design Time Stamp, Day */ + const uint32_t MON : 8; /* Design Time Stamp, Month */ + const uint32_t YEAR : 4; /* Design Time Stamp, Year */ + const uint32_t STEP : 8; /* Step of Core Release */ + const uint32_t REL : 4; /* Core Release */ +}; + +/* The typedef declaration for register ALT_CAN_PROTO_CRR. */ +typedef volatile struct ALT_CAN_PROTO_CRR_s ALT_CAN_PROTO_CRR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_PROTO_CRR register from the beginning of the component. */ +#define ALT_CAN_PROTO_CRR_OFST 0x20 +/* The address of the ALT_CAN_PROTO_CRR register. */ +#define ALT_CAN_PROTO_CRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_CRR_OFST)) + +/* + * Register : Hardware Configuration Status Register - HWS + * + * Hardware Configuration Status Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [1:0] | R | 0x3 | Message Buffer Count + * [2] | R | 0x0 | Parity Generation + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Message Buffer Count - mb_w + * + * Message Buffer Count + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS16 | 0x0 | 16 Message Objects + * ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS32 | 0x1 | 32 Message Objects + * ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS64 | 0x2 | 64 Message Objects + * ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS128 | 0x3 | 128 Message Objects + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_HWS_MB_W + * + * 16 Message Objects + */ +#define ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS16 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_HWS_MB_W + * + * 32 Message Objects + */ +#define ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS32 0x1 +/* + * Enumerated value for register field ALT_CAN_PROTO_HWS_MB_W + * + * 64 Message Objects + */ +#define ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS64 0x2 +/* + * Enumerated value for register field ALT_CAN_PROTO_HWS_MB_W + * + * 128 Message Objects + */ +#define ALT_CAN_PROTO_HWS_MB_W_E_MSGOBJS128 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_HWS_MB_W register field. */ +#define ALT_CAN_PROTO_HWS_MB_W_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_HWS_MB_W register field. */ +#define ALT_CAN_PROTO_HWS_MB_W_MSB 1 +/* The width in bits of the ALT_CAN_PROTO_HWS_MB_W register field. */ +#define ALT_CAN_PROTO_HWS_MB_W_WIDTH 2 +/* The mask used to set the ALT_CAN_PROTO_HWS_MB_W register field value. */ +#define ALT_CAN_PROTO_HWS_MB_W_SET_MSK 0x00000003 +/* The mask used to clear the ALT_CAN_PROTO_HWS_MB_W register field value. */ +#define ALT_CAN_PROTO_HWS_MB_W_CLR_MSK 0xfffffffc +/* The reset value of the ALT_CAN_PROTO_HWS_MB_W register field. */ +#define ALT_CAN_PROTO_HWS_MB_W_RESET 0x3 +/* Extracts the ALT_CAN_PROTO_HWS_MB_W field value from a register. */ +#define ALT_CAN_PROTO_HWS_MB_W_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_CAN_PROTO_HWS_MB_W register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_HWS_MB_W_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Parity Generation - paren + * + * Parity Generation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------ + * ALT_CAN_PROTO_HWS_PAREN_E_NOTPRESENT | 0x0 | Parity generation harware is not present. + * ALT_CAN_PROTO_HWS_PAREN_E_PRESENT | 0x1 | Parity generation harware is present. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_PROTO_HWS_PAREN + * + * Parity generation harware is not present. + */ +#define ALT_CAN_PROTO_HWS_PAREN_E_NOTPRESENT 0x0 +/* + * Enumerated value for register field ALT_CAN_PROTO_HWS_PAREN + * + * Parity generation harware is present. + */ +#define ALT_CAN_PROTO_HWS_PAREN_E_PRESENT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_PROTO_HWS_PAREN register field. */ +#define ALT_CAN_PROTO_HWS_PAREN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_PROTO_HWS_PAREN register field. */ +#define ALT_CAN_PROTO_HWS_PAREN_MSB 2 +/* The width in bits of the ALT_CAN_PROTO_HWS_PAREN register field. */ +#define ALT_CAN_PROTO_HWS_PAREN_WIDTH 1 +/* The mask used to set the ALT_CAN_PROTO_HWS_PAREN register field value. */ +#define ALT_CAN_PROTO_HWS_PAREN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_PROTO_HWS_PAREN register field value. */ +#define ALT_CAN_PROTO_HWS_PAREN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_PROTO_HWS_PAREN register field. */ +#define ALT_CAN_PROTO_HWS_PAREN_RESET 0x0 +/* Extracts the ALT_CAN_PROTO_HWS_PAREN field value from a register. */ +#define ALT_CAN_PROTO_HWS_PAREN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_PROTO_HWS_PAREN register field value suitable for setting the register. */ +#define ALT_CAN_PROTO_HWS_PAREN_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_PROTO_HWS. + */ +struct ALT_CAN_PROTO_HWS_s +{ + const uint32_t mb_w : 2; /* Message Buffer Count */ + const uint32_t paren : 1; /* Parity Generation */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_PROTO_HWS. */ +typedef volatile struct ALT_CAN_PROTO_HWS_s ALT_CAN_PROTO_HWS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_PROTO_HWS register from the beginning of the component. */ +#define ALT_CAN_PROTO_HWS_OFST 0x24 +/* The address of the ALT_CAN_PROTO_HWS register. */ +#define ALT_CAN_PROTO_HWS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_PROTO_HWS_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CAN_PROTO. + */ +struct ALT_CAN_PROTO_s +{ + volatile ALT_CAN_PROTO_CCTL_t CCTRL; /* ALT_CAN_PROTO_CCTL */ + volatile ALT_CAN_PROTO_CSTS_t CSTS; /* ALT_CAN_PROTO_CSTS */ + volatile ALT_CAN_PROTO_CERC_t CERC; /* ALT_CAN_PROTO_CERC */ + volatile ALT_CAN_PROTO_CBT_t CBT; /* ALT_CAN_PROTO_CBT */ + volatile ALT_CAN_PROTO_CIR_t CIR; /* ALT_CAN_PROTO_CIR */ + volatile ALT_CAN_PROTO_CTR_t CTR; /* ALT_CAN_PROTO_CTR */ + volatile ALT_CAN_PROTO_CFR_t CFR; /* ALT_CAN_PROTO_CFR */ + volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */ + volatile ALT_CAN_PROTO_CRR_t CRR; /* ALT_CAN_PROTO_CRR */ + volatile ALT_CAN_PROTO_HWS_t HWS; /* ALT_CAN_PROTO_HWS */ +}; + +/* The typedef declaration for register group ALT_CAN_PROTO. */ +typedef volatile struct ALT_CAN_PROTO_s ALT_CAN_PROTO_t; +/* The struct declaration for the raw register contents of register group ALT_CAN_PROTO. */ +struct ALT_CAN_PROTO_raw_s +{ + volatile uint32_t CCTRL; /* ALT_CAN_PROTO_CCTL */ + volatile uint32_t CSTS; /* ALT_CAN_PROTO_CSTS */ + volatile uint32_t CERC; /* ALT_CAN_PROTO_CERC */ + volatile uint32_t CBT; /* ALT_CAN_PROTO_CBT */ + volatile uint32_t CIR; /* ALT_CAN_PROTO_CIR */ + volatile uint32_t CTR; /* ALT_CAN_PROTO_CTR */ + volatile uint32_t CFR; /* ALT_CAN_PROTO_CFR */ + volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */ + volatile uint32_t CRR; /* ALT_CAN_PROTO_CRR */ + volatile uint32_t HWS; /* ALT_CAN_PROTO_HWS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CAN_PROTO. */ +typedef volatile struct ALT_CAN_PROTO_raw_s ALT_CAN_PROTO_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Message Handler Group - ALT_CAN_MSGHAND + * Message Handler Group + * + * These registers are related to the operation of the Message Handler. The Message + * Handler is a state machine that controls the data transfer between the single + * ported Message RAM and the CAN Core's Rx/Tx Shift Register. It also handles + * acceptance filtering and the interrupt setting as programmed in the Control and + * Configuration Registers. + * + */ +/* + * Register : Transmission Request X Register - MOTRX + * + * Reading this register allows the CPU to quickly detect if any of the + * transmission request bits in each of the MOTRA, MOTRB, MOTRC, and MOTRD + * Transmission Request Registers are set. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [0] | R | 0x0 | TxRqstA + * [1] | R | 0x0 | TxRqstA + * [2] | R | 0x0 | TxRqstA + * [3] | R | 0x0 | TxRqstA + * [4] | R | 0x0 | TxRqstB + * [5] | R | 0x0 | TxRqstB + * [6] | R | 0x0 | TxRqstB + * [7] | R | 0x0 | TxRqstB + * [8] | R | 0x0 | TxRqstC + * [9] | R | 0x0 | TxRqstC + * [10] | R | 0x0 | TxRqstC + * [11] | R | 0x0 | TxRqstC + * [12] | R | 0x0 | TxRqstD + * [13] | R | 0x0 | TxRqstD + * [14] | R | 0x0 | TxRqstD + * [15] | R | 0x0 | TxRqstD + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : TxRqstA - TxRqstA_0 + * + * Each bit in this field is a logical OR of a byte of the MOTRA register. Array + * index i corresponds to byte i of the MOTRA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRA are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRA are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 + * + * The Message Objects in the corresponding byte of MOTRA are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRA are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TxRqstA - TxRqstA_1 + * + * Each bit in this field is a logical OR of a byte of the MOTRA register. Array + * index i corresponds to byte i of the MOTRA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRA are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRA are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 + * + * The Message Objects in the corresponding byte of MOTRA are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRA are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : TxRqstA - TxRqstA_2 + * + * Each bit in this field is a logical OR of a byte of the MOTRA register. Array + * index i corresponds to byte i of the MOTRA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRA are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRA are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 + * + * The Message Objects in the corresponding byte of MOTRA are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRA are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : TxRqstA - TxRqstA_3 + * + * Each bit in this field is a logical OR of a byte of the MOTRA register. Array + * index i corresponds to byte i of the MOTRA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRA are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRA are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 + * + * The Message Objects in the corresponding byte of MOTRA are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRA are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTA_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : TxRqstB - TxRqstB_0 + * + * Each bit in this field is a logical OR of a byte of the MOTRB register. Array + * index i corresponds to byte i of the MOTRB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRB are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRB are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 + * + * The Message Objects in the corresponding byte of MOTRB are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRB are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : TxRqstB - TxRqstB_1 + * + * Each bit in this field is a logical OR of a byte of the MOTRB register. Array + * index i corresponds to byte i of the MOTRB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRB are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRB are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 + * + * The Message Objects in the corresponding byte of MOTRB are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRB are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TxRqstB - TxRqstB_2 + * + * Each bit in this field is a logical OR of a byte of the MOTRB register. Array + * index i corresponds to byte i of the MOTRB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRB are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRB are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 + * + * The Message Objects in the corresponding byte of MOTRB are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRB are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_2_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : TxRqstB - TxRqstB_3 + * + * Each bit in this field is a logical OR of a byte of the MOTRB register. Array + * index i corresponds to byte i of the MOTRB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRB are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRB are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 + * + * The Message Objects in the corresponding byte of MOTRB are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRB are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTB_3_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : TxRqstC - TxRqstC_0 + * + * Each bit in this field is a logical OR of a byte of the MOTRC register. Array + * index i corresponds to byte i of the MOTRC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRC are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRC are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 + * + * The Message Objects in the corresponding byte of MOTRC are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRC are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : TxRqstC - TxRqstC_1 + * + * Each bit in this field is a logical OR of a byte of the MOTRC register. Array + * index i corresponds to byte i of the MOTRC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRC are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRC are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 + * + * The Message Objects in the corresponding byte of MOTRC are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRC are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : TxRqstC - TxRqstC_2 + * + * Each bit in this field is a logical OR of a byte of the MOTRC register. Array + * index i corresponds to byte i of the MOTRC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRC are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRC are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 + * + * The Message Objects in the corresponding byte of MOTRC are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRC are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_2_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : TxRqstC - TxRqstC_3 + * + * Each bit in this field is a logical OR of a byte of the MOTRC register. Array + * index i corresponds to byte i of the MOTRC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRC are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRC are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 + * + * The Message Objects in the corresponding byte of MOTRC are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRC are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTC_3_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : TxRqstD - TxRqstD_0 + * + * Each bit in this field is a logical OR of a byte of the MOTRD register. Array + * index i corresponds to byte i of the MOTRD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRD are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRD are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 + * + * The Message Objects in the corresponding byte of MOTRD are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRD are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_0_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : TxRqstD - TxRqstD_1 + * + * Each bit in this field is a logical OR of a byte of the MOTRD register. Array + * index i corresponds to byte i of the MOTRD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRD are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRD are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 + * + * The Message Objects in the corresponding byte of MOTRD are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRD are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_1_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : TxRqstD - TxRqstD_2 + * + * Each bit in this field is a logical OR of a byte of the MOTRD register. Array + * index i corresponds to byte i of the MOTRD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRD are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRD are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 + * + * The Message Objects in the corresponding byte of MOTRD are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRD are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_2_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : TxRqstD - TxRqstD_3 + * + * Each bit in this field is a logical OR of a byte of the MOTRD register. Array + * index i corresponds to byte i of the MOTRD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_E_NOTWAITING | 0x0 | The Message Objects in the corresponding byte of + * : | | MOTRD are not waiting for transmission. + * ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_E_PENDING | 0x1 | One or more of the transmission of the Message + * : | | Objects in the corresponding byte of MOTRD are + * : | | requested and are not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 + * + * The Message Objects in the corresponding byte of MOTRD are not waiting for + * transmission. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 + * + * One or more of the transmission of the Message Objects in the corresponding byte + * of MOTRD are requested and are not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRX_TXRQSTD_3_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOTRX. + */ +struct ALT_CAN_MSGHAND_MOTRX_s +{ + const uint32_t TxRqstA_0 : 1; /* TxRqstA */ + const uint32_t TxRqstA_1 : 1; /* TxRqstA */ + const uint32_t TxRqstA_2 : 1; /* TxRqstA */ + const uint32_t TxRqstA_3 : 1; /* TxRqstA */ + const uint32_t TxRqstB_0 : 1; /* TxRqstB */ + const uint32_t TxRqstB_1 : 1; /* TxRqstB */ + const uint32_t TxRqstB_2 : 1; /* TxRqstB */ + const uint32_t TxRqstB_3 : 1; /* TxRqstB */ + const uint32_t TxRqstC_0 : 1; /* TxRqstC */ + const uint32_t TxRqstC_1 : 1; /* TxRqstC */ + const uint32_t TxRqstC_2 : 1; /* TxRqstC */ + const uint32_t TxRqstC_3 : 1; /* TxRqstC */ + const uint32_t TxRqstD_0 : 1; /* TxRqstD */ + const uint32_t TxRqstD_1 : 1; /* TxRqstD */ + const uint32_t TxRqstD_2 : 1; /* TxRqstD */ + const uint32_t TxRqstD_3 : 1; /* TxRqstD */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOTRX. */ +typedef volatile struct ALT_CAN_MSGHAND_MOTRX_s ALT_CAN_MSGHAND_MOTRX_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOTRX register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOTRX_OFST 0x0 +/* The address of the ALT_CAN_MSGHAND_MOTRX register. */ +#define ALT_CAN_MSGHAND_MOTRX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOTRX_OFST)) + +/* + * Register : Transmission Request A Register - MOTRA + * + * Transmission request bits for Message Objects 1 to 32. By reading the TxRqst + * bits, the CPU can check for which Message Object a Transmission Request is + * pending. The TxRqst bit of a specific Message Object can be set/reset by the CPU + * via the IFx Message Interface Registers or set by the Message Handler after + * reception of a Remote Frame or reset by the Message Handler after a successful + * transmission. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | TxRqst32-1 + * [1] | R | 0x0 | TxRqst32-1 + * [2] | R | 0x0 | TxRqst32-1 + * [3] | R | 0x0 | TxRqst32-1 + * [4] | R | 0x0 | TxRqst32-1 + * [5] | R | 0x0 | TxRqst32-1 + * [6] | R | 0x0 | TxRqst32-1 + * [7] | R | 0x0 | TxRqst32-1 + * [8] | R | 0x0 | TxRqst32-1 + * [9] | R | 0x0 | TxRqst32-1 + * [10] | R | 0x0 | TxRqst32-1 + * [11] | R | 0x0 | TxRqst32-1 + * [12] | R | 0x0 | TxRqst32-1 + * [13] | R | 0x0 | TxRqst32-1 + * [14] | R | 0x0 | TxRqst32-1 + * [15] | R | 0x0 | TxRqst32-1 + * [16] | R | 0x0 | TxRqst32-1 + * [17] | R | 0x0 | TxRqst32-1 + * [18] | R | 0x0 | TxRqst32-1 + * [19] | R | 0x0 | TxRqst32-1 + * [20] | R | 0x0 | TxRqst32-1 + * [21] | R | 0x0 | TxRqst32-1 + * [22] | R | 0x0 | TxRqst32-1 + * [23] | R | 0x0 | TxRqst32-1 + * [24] | R | 0x0 | TxRqst32-1 + * [25] | R | 0x0 | TxRqst32-1 + * [26] | R | 0x0 | TxRqst32-1 + * [27] | R | 0x0 | TxRqst32-1 + * [28] | R | 0x0 | TxRqst32-1 + * [29] | R | 0x0 | TxRqst32-1 + * [30] | R | 0x0 | TxRqst32-1 + * [31] | R | 0x0 | TxRqst32-1 + * + */ +/* + * Field : TxRqst32-1 - TxRqst_0 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_0_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_0_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_0 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_0 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TxRqst32-1 - TxRqst_1 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_1_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_1_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_1 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_1 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : TxRqst32-1 - TxRqst_2 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_2_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_2_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_2 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_2 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : TxRqst32-1 - TxRqst_3 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_3_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_3_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_3 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_3 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : TxRqst32-1 - TxRqst_4 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_4_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_4_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_4 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_4 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : TxRqst32-1 - TxRqst_5 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_5_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_5_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_5 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_5 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TxRqst32-1 - TxRqst_6 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_6_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_6_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_6 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_6 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : TxRqst32-1 - TxRqst_7 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_7_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_7_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_7 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_7 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : TxRqst32-1 - TxRqst_8 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_8_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_8_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_8 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_8 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : TxRqst32-1 - TxRqst_9 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_9_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_9_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_9 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_9 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : TxRqst32-1 - TxRqst_10 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_10_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_10_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_10 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_10 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : TxRqst32-1 - TxRqst_11 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_11_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_11_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_11 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_11 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : TxRqst32-1 - TxRqst_12 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_12_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_12_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_12 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_12 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : TxRqst32-1 - TxRqst_13 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_13_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_13_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_13 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_13 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : TxRqst32-1 - TxRqst_14 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_14_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_14_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_14 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_14 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : TxRqst32-1 - TxRqst_15 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_15_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_15_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_15 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_15 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : TxRqst32-1 - TxRqst_16 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_16_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_16_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_16 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_16 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : TxRqst32-1 - TxRqst_17 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_17_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_17_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_17 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_17 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : TxRqst32-1 - TxRqst_18 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_18_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_18_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_18 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_18 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : TxRqst32-1 - TxRqst_19 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_19_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_19_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_19 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_19 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : TxRqst32-1 - TxRqst_20 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_20_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_20_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_20 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_20 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : TxRqst32-1 - TxRqst_21 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_21_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_21_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_21 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_21 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxRqst32-1 - TxRqst_22 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_22_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_22_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_22 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_22 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : TxRqst32-1 - TxRqst_23 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_23_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_23_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_23 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_23 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : TxRqst32-1 - TxRqst_24 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_24_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_24_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_24 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_24 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : TxRqst32-1 - TxRqst_25 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_25_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_25_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_25 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_25 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : TxRqst32-1 - TxRqst_26 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_26_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_26_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_26 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_26 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : TxRqst32-1 - TxRqst_27 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_27_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_27_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_27 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_27 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : TxRqst32-1 - TxRqst_28 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_28_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_28_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_28 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_28 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : TxRqst32-1 - TxRqst_29 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_29_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_29_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_29 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_29 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : TxRqst32-1 - TxRqst_30 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_30_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_30_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_30 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_30 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : TxRqst32-1 - TxRqst_31 + * + * Transmission request bits for Message Objects 1 to 32. Array index i corresponds + * to Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRA_TXRQST_31_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRA_TXRQST_31_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_31 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRA_TXRQST_31 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field value. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRA_TXRQST_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOTRA_TXRQST_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRA_TXRQST_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOTRA. + */ +struct ALT_CAN_MSGHAND_MOTRA_s +{ + const uint32_t TxRqst_0 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_1 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_2 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_3 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_4 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_5 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_6 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_7 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_8 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_9 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_10 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_11 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_12 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_13 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_14 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_15 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_16 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_17 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_18 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_19 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_20 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_21 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_22 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_23 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_24 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_25 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_26 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_27 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_28 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_29 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_30 : 1; /* TxRqst32-1 */ + const uint32_t TxRqst_31 : 1; /* TxRqst32-1 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOTRA. */ +typedef volatile struct ALT_CAN_MSGHAND_MOTRA_s ALT_CAN_MSGHAND_MOTRA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOTRA register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOTRA_OFST 0x4 +/* The address of the ALT_CAN_MSGHAND_MOTRA register. */ +#define ALT_CAN_MSGHAND_MOTRA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOTRA_OFST)) + +/* + * Register : Transmission Request B Register - MOTRB + * + * Transmission request bits for Message Objects 33 to 64. By reading the TxRqst + * bits, the CPU can check for which Message Object a Transmission Request is + * pending. The TxRqst bit of a specific Message Object can be set/reset by the CPU + * via the IFx Message Interface Registers or set by the Message Handler after + * reception of a Remote Frame or reset by the Message Handler after a successful + * transmission. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | TxRqst64-33 + * [1] | R | 0x0 | TxRqst64-33 + * [2] | R | 0x0 | TxRqst64-33 + * [3] | R | 0x0 | TxRqst64-33 + * [4] | R | 0x0 | TxRqst64-33 + * [5] | R | 0x0 | TxRqst64-33 + * [6] | R | 0x0 | TxRqst64-33 + * [7] | R | 0x0 | TxRqst64-33 + * [8] | R | 0x0 | TxRqst64-33 + * [9] | R | 0x0 | TxRqst64-33 + * [10] | R | 0x0 | TxRqst64-33 + * [11] | R | 0x0 | TxRqst64-33 + * [12] | R | 0x0 | TxRqst64-33 + * [13] | R | 0x0 | TxRqst64-33 + * [14] | R | 0x0 | TxRqst64-33 + * [15] | R | 0x0 | TxRqst64-33 + * [16] | R | 0x0 | TxRqst64-33 + * [17] | R | 0x0 | TxRqst64-33 + * [18] | R | 0x0 | TxRqst64-33 + * [19] | R | 0x0 | TxRqst64-33 + * [20] | R | 0x0 | TxRqst64-33 + * [21] | R | 0x0 | TxRqst64-33 + * [22] | R | 0x0 | TxRqst64-33 + * [23] | R | 0x0 | TxRqst64-33 + * [24] | R | 0x0 | TxRqst64-33 + * [25] | R | 0x0 | TxRqst64-33 + * [26] | R | 0x0 | TxRqst64-33 + * [27] | R | 0x0 | TxRqst64-33 + * [28] | R | 0x0 | TxRqst64-33 + * [29] | R | 0x0 | TxRqst64-33 + * [30] | R | 0x0 | TxRqst64-33 + * [31] | R | 0x0 | TxRqst64-33 + * + */ +/* + * Field : TxRqst64-33 - TxRqst_0 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_0_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_0_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_0 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_0 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TxRqst64-33 - TxRqst_1 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_1_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_1_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_1 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_1 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : TxRqst64-33 - TxRqst_2 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_2_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_2_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_2 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_2 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : TxRqst64-33 - TxRqst_3 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_3_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_3_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_3 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_3 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : TxRqst64-33 - TxRqst_4 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_4_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_4_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_4 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_4 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : TxRqst64-33 - TxRqst_5 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_5_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_5_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_5 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_5 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TxRqst64-33 - TxRqst_6 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_6_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_6_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_6 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_6 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : TxRqst64-33 - TxRqst_7 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_7_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_7_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_7 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_7 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : TxRqst64-33 - TxRqst_8 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_8_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_8_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_8 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_8 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : TxRqst64-33 - TxRqst_9 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_9_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_9_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_9 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_9 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : TxRqst64-33 - TxRqst_10 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_10_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_10_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_10 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_10 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : TxRqst64-33 - TxRqst_11 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_11_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_11_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_11 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_11 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : TxRqst64-33 - TxRqst_12 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_12_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_12_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_12 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_12 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : TxRqst64-33 - TxRqst_13 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_13_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_13_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_13 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_13 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : TxRqst64-33 - TxRqst_14 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_14_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_14_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_14 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_14 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : TxRqst64-33 - TxRqst_15 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_15_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_15_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_15 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_15 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : TxRqst64-33 - TxRqst_16 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_16_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_16_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_16 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_16 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : TxRqst64-33 - TxRqst_17 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_17_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_17_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_17 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_17 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : TxRqst64-33 - TxRqst_18 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_18_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_18_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_18 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_18 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : TxRqst64-33 - TxRqst_19 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_19_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_19_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_19 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_19 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : TxRqst64-33 - TxRqst_20 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_20_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_20_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_20 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_20 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : TxRqst64-33 - TxRqst_21 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_21_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_21_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_21 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_21 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxRqst64-33 - TxRqst_22 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_22_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_22_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_22 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_22 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : TxRqst64-33 - TxRqst_23 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_23_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_23_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_23 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_23 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : TxRqst64-33 - TxRqst_24 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_24_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_24_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_24 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_24 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : TxRqst64-33 - TxRqst_25 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_25_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_25_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_25 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_25 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : TxRqst64-33 - TxRqst_26 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_26_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_26_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_26 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_26 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : TxRqst64-33 - TxRqst_27 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_27_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_27_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_27 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_27 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : TxRqst64-33 - TxRqst_28 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_28_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_28_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_28 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_28 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : TxRqst64-33 - TxRqst_29 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_29_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_29_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_29 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_29 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : TxRqst64-33 - TxRqst_30 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_30_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_30_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_30 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_30 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : TxRqst64-33 - TxRqst_31 + * + * Transmission request bits for Message Objects 33 to 64. Array index i + * corresponds to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRB_TXRQST_31_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRB_TXRQST_31_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_31 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRB_TXRQST_31 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field value. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRB_TXRQST_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOTRB_TXRQST_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRB_TXRQST_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOTRB. + */ +struct ALT_CAN_MSGHAND_MOTRB_s +{ + const uint32_t TxRqst_0 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_1 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_2 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_3 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_4 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_5 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_6 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_7 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_8 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_9 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_10 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_11 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_12 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_13 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_14 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_15 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_16 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_17 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_18 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_19 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_20 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_21 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_22 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_23 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_24 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_25 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_26 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_27 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_28 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_29 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_30 : 1; /* TxRqst64-33 */ + const uint32_t TxRqst_31 : 1; /* TxRqst64-33 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOTRB. */ +typedef volatile struct ALT_CAN_MSGHAND_MOTRB_s ALT_CAN_MSGHAND_MOTRB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOTRB register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOTRB_OFST 0x8 +/* The address of the ALT_CAN_MSGHAND_MOTRB register. */ +#define ALT_CAN_MSGHAND_MOTRB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOTRB_OFST)) + +/* + * Register : Transmission Request C Register - MOTRC + * + * Transmission request bits for Message Objects 65 to 96. By reading the TxRqst + * bits, the CPU can check for which Message Object a Transmission Request is + * pending. The TxRqst bit of a specific Message Object can be set/reset by the CPU + * via the IFx Message Interface Registers or set by the Message Handler after + * reception of a Remote Frame or reset by the Message Handler after a successful + * transmission. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | TxRqst96-65 + * [1] | R | 0x0 | TxRqst96-65 + * [2] | R | 0x0 | TxRqst96-65 + * [3] | R | 0x0 | TxRqst96-65 + * [4] | R | 0x0 | TxRqst96-65 + * [5] | R | 0x0 | TxRqst96-65 + * [6] | R | 0x0 | TxRqst96-65 + * [7] | R | 0x0 | TxRqst96-65 + * [8] | R | 0x0 | TxRqst96-65 + * [9] | R | 0x0 | TxRqst96-65 + * [10] | R | 0x0 | TxRqst96-65 + * [11] | R | 0x0 | TxRqst96-65 + * [12] | R | 0x0 | TxRqst96-65 + * [13] | R | 0x0 | TxRqst96-65 + * [14] | R | 0x0 | TxRqst96-65 + * [15] | R | 0x0 | TxRqst96-65 + * [16] | R | 0x0 | TxRqst96-65 + * [17] | R | 0x0 | TxRqst96-65 + * [18] | R | 0x0 | TxRqst96-65 + * [19] | R | 0x0 | TxRqst96-65 + * [20] | R | 0x0 | TxRqst96-65 + * [21] | R | 0x0 | TxRqst96-65 + * [22] | R | 0x0 | TxRqst96-65 + * [23] | R | 0x0 | TxRqst96-65 + * [24] | R | 0x0 | TxRqst96-65 + * [25] | R | 0x0 | TxRqst96-65 + * [26] | R | 0x0 | TxRqst96-65 + * [27] | R | 0x0 | TxRqst96-65 + * [28] | R | 0x0 | TxRqst96-65 + * [29] | R | 0x0 | TxRqst96-65 + * [30] | R | 0x0 | TxRqst96-65 + * [31] | R | 0x0 | TxRqst96-65 + * + */ +/* + * Field : TxRqst96-65 - TxRqst_0 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_0_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_0_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_0 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_0 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TxRqst96-65 - TxRqst_1 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_1_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_1_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_1 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_1 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : TxRqst96-65 - TxRqst_2 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_2_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_2_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_2 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_2 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : TxRqst96-65 - TxRqst_3 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_3_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_3_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_3 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_3 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : TxRqst96-65 - TxRqst_4 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_4_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_4_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_4 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_4 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : TxRqst96-65 - TxRqst_5 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_5_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_5_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_5 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_5 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TxRqst96-65 - TxRqst_6 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_6_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_6_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_6 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_6 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : TxRqst96-65 - TxRqst_7 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_7_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_7_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_7 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_7 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : TxRqst96-65 - TxRqst_8 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_8_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_8_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_8 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_8 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : TxRqst96-65 - TxRqst_9 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_9_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_9_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_9 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_9 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : TxRqst96-65 - TxRqst_10 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_10_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_10_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_10 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_10 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : TxRqst96-65 - TxRqst_11 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_11_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_11_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_11 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_11 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : TxRqst96-65 - TxRqst_12 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_12_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_12_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_12 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_12 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : TxRqst96-65 - TxRqst_13 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_13_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_13_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_13 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_13 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : TxRqst96-65 - TxRqst_14 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_14_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_14_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_14 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_14 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : TxRqst96-65 - TxRqst_15 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_15_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_15_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_15 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_15 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : TxRqst96-65 - TxRqst_16 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_16_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_16_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_16 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_16 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : TxRqst96-65 - TxRqst_17 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_17_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_17_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_17 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_17 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : TxRqst96-65 - TxRqst_18 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_18_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_18_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_18 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_18 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : TxRqst96-65 - TxRqst_19 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_19_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_19_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_19 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_19 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : TxRqst96-65 - TxRqst_20 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_20_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_20_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_20 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_20 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : TxRqst96-65 - TxRqst_21 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_21_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_21_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_21 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_21 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxRqst96-65 - TxRqst_22 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_22_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_22_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_22 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_22 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_22 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_22 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : TxRqst96-65 - TxRqst_23 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_23_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_23_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_23 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_23_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_23 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_23_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_23 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_23 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : TxRqst96-65 - TxRqst_24 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_24_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_24_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_24 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_24_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_24 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_24_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_24 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_24 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : TxRqst96-65 - TxRqst_25 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_25_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_25_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_25 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_25_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_25 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_25_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_25 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_25 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : TxRqst96-65 - TxRqst_26 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_26_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_26_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_26 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_26_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_26 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_26_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_26 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_26 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : TxRqst96-65 - TxRqst_27 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_27_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_27_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_27 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_27_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_27 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_27_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_27 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_27 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : TxRqst96-65 - TxRqst_28 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_28_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_28_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_28 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_28_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_28 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_28_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_28 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_28 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : TxRqst96-65 - TxRqst_29 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_29_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_29_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_29 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_29_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_29 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_29_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_29 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_29 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : TxRqst96-65 - TxRqst_30 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_30_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_30_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_30 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_30_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_30 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_30_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_30 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_30 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : TxRqst96-65 - TxRqst_31 + * + * Transmission request bits for Message Objects 65 to 96. Array index i + * corresponds to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRC_TXRQST_31_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRC_TXRQST_31_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_31 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_31_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRC_TXRQST_31 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_31_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRC_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRC_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRC_TXRQST_31 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRC_TXRQST_31 register field value. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRC_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRC_TXRQST_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOTRC_TXRQST_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRC_TXRQST_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOTRC. + */ +struct ALT_CAN_MSGHAND_MOTRC_s +{ + const uint32_t TxRqst_0 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_1 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_2 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_3 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_4 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_5 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_6 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_7 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_8 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_9 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_10 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_11 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_12 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_13 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_14 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_15 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_16 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_17 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_18 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_19 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_20 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_21 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_22 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_23 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_24 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_25 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_26 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_27 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_28 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_29 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_30 : 1; /* TxRqst96-65 */ + const uint32_t TxRqst_31 : 1; /* TxRqst96-65 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOTRC. */ +typedef volatile struct ALT_CAN_MSGHAND_MOTRC_s ALT_CAN_MSGHAND_MOTRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOTRC register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOTRC_OFST 0xc +/* The address of the ALT_CAN_MSGHAND_MOTRC register. */ +#define ALT_CAN_MSGHAND_MOTRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOTRC_OFST)) + +/* + * Register : Transmission Request D Register - MOTRD + * + * Transmission request bits for Message Objects 97 to 128. By reading the TxRqst + * bits, the CPU can check for which Message Object a Transmission Request is + * pending. The TxRqst bit of a specific Message Object can be set/reset by the CPU + * via the IFx Message Interface Registers or set by the Message Handler after + * reception of a Remote Frame or reset by the Message Handler after a successful + * transmission. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------- + * [0] | R | 0x0 | TxRqst128-97 + * [1] | R | 0x0 | TxRqst128-97 + * [2] | R | 0x0 | TxRqst128-97 + * [3] | R | 0x0 | TxRqst128-97 + * [4] | R | 0x0 | TxRqst128-97 + * [5] | R | 0x0 | TxRqst128-97 + * [6] | R | 0x0 | TxRqst128-97 + * [7] | R | 0x0 | TxRqst128-97 + * [8] | R | 0x0 | TxRqst128-97 + * [9] | R | 0x0 | TxRqst128-97 + * [10] | R | 0x0 | TxRqst128-97 + * [11] | R | 0x0 | TxRqst128-97 + * [12] | R | 0x0 | TxRqst128-97 + * [13] | R | 0x0 | TxRqst128-97 + * [14] | R | 0x0 | TxRqst128-97 + * [15] | R | 0x0 | TxRqst128-97 + * [16] | R | 0x0 | TxRqst128-97 + * [17] | R | 0x0 | TxRqst128-97 + * [18] | R | 0x0 | TxRqst128-97 + * [19] | R | 0x0 | TxRqst128-97 + * [20] | R | 0x0 | TxRqst128-97 + * [21] | R | 0x0 | TxRqst128-97 + * [22] | R | 0x0 | TxRqst128-97 + * [23] | R | 0x0 | TxRqst128-97 + * [24] | R | 0x0 | TxRqst128-97 + * [25] | R | 0x0 | TxRqst128-97 + * [26] | R | 0x0 | TxRqst128-97 + * [27] | R | 0x0 | TxRqst128-97 + * [28] | R | 0x0 | TxRqst128-97 + * [29] | R | 0x0 | TxRqst128-97 + * [30] | R | 0x0 | TxRqst128-97 + * [31] | R | 0x0 | TxRqst128-97 + * + */ +/* + * Field : TxRqst128-97 - TxRqst_0 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_0_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_0_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_0 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_0_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_0 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_0_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_0 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_0 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TxRqst128-97 - TxRqst_1 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_1_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_1_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_1 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_1_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_1 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_1_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_1 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_1 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : TxRqst128-97 - TxRqst_2 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_2_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_2_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_2 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_2_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_2 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_2_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_2 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_2 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : TxRqst128-97 - TxRqst_3 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_3_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_3_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_3 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_3_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_3 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_3_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_3 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_3 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : TxRqst128-97 - TxRqst_4 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_4_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_4_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_4 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_4_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_4 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_4_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_4 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_4 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_4 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : TxRqst128-97 - TxRqst_5 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_5_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_5_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_5 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_5_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_5 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_5_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_5 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_5 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_5 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TxRqst128-97 - TxRqst_6 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_6_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_6_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_6 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_6_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_6 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_6_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_6 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_6 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_6 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : TxRqst128-97 - TxRqst_7 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_7_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_7_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_7 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_7_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_7 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_7_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_7 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_7 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_7 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : TxRqst128-97 - TxRqst_8 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_8_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_8_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_8 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_8_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_8 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_8_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_8 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_8 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_8 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : TxRqst128-97 - TxRqst_9 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_9_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_9_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_9 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_9_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_9 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_9_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_9 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_9 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_9 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : TxRqst128-97 - TxRqst_10 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_10_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_10_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_10 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_10_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_10 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_10_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_10 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_10 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_10 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : TxRqst128-97 - TxRqst_11 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_11_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_11_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_11 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_11_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_11 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_11_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_11 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_11 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_11 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : TxRqst128-97 - TxRqst_12 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_12_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_12_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_12 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_12_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_12 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_12_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_12 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_12 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_12 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : TxRqst128-97 - TxRqst_13 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_13_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_13_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_13 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_13_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_13 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_13_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_13 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_13 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_13 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : TxRqst128-97 - TxRqst_14 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_14_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_14_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_14 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_14_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_14 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_14_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_14 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_14 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_14 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : TxRqst128-97 - TxRqst_15 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_15_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_15_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_15 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_15_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_15 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_15_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_15 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_15 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_15 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : TxRqst128-97 - TxRqst_16 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_16_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_16_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_16 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_16_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_16 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_16_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_16 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_16 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_16 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : TxRqst128-97 - TxRqst_17 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_17_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_17_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_17 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_17_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_17 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_17_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_17 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_17 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_17 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : TxRqst128-97 - TxRqst_18 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_18_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_18_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_18 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_18_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_18 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_18_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_18 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_18 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_18 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : TxRqst128-97 - TxRqst_19 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_19_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_19_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_19 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_19_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_19 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_19_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_19 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_19 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_19 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : TxRqst128-97 - TxRqst_20 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_20_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_20_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_20 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_20_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_20 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_20_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_20 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_20 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_20 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : TxRqst128-97 - TxRqst_21 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_21_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_21_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_21 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_21_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_21 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_21_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_21 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_21 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_21 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxRqst128-97 - TxRqst_22 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_22_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_22_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_22 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_22_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_22 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_22_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_22 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_22 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_22 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : TxRqst128-97 - TxRqst_23 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_23_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_23_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_23 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_23_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_23 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_23_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_23 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_23 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_23 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : TxRqst128-97 - TxRqst_24 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_24_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_24_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_24 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_24_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_24 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_24_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_24 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_24 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_24 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : TxRqst128-97 - TxRqst_25 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_25_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_25_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_25 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_25_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_25 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_25_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_25 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_25 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_25 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : TxRqst128-97 - TxRqst_26 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_26_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_26_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_26 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_26_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_26 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_26_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_26 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_26 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_26 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : TxRqst128-97 - TxRqst_27 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_27_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_27_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_27 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_27_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_27 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_27_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_27 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_27 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_27 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : TxRqst128-97 - TxRqst_28 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_28_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_28_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_28 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_28_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_28 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_28_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_28 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_28 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_28 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : TxRqst128-97 - TxRqst_29 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_29_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_29_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_29 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_29_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_29 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_29_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_29 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_29 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_29 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : TxRqst128-97 - TxRqst_30 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_30_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_30_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_30 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_30_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_30 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_30_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_30 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_30 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_30 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : TxRqst128-97 - TxRqst_31 + * + * Transmission request bits for Message Objects 97 to 128. Array index i + * corresponds to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOTRD_TXRQST_31_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGHAND_MOTRD_TXRQST_31_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_31 + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_31_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOTRD_TXRQST_31 + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_31_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOTRD_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOTRD_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOTRD_TXRQST_31 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOTRD_TXRQST_31 register field value. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOTRD_TXRQST_31 register field. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOTRD_TXRQST_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOTRD_TXRQST_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOTRD_TXRQST_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOTRD. + */ +struct ALT_CAN_MSGHAND_MOTRD_s +{ + const uint32_t TxRqst_0 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_1 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_2 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_3 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_4 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_5 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_6 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_7 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_8 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_9 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_10 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_11 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_12 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_13 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_14 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_15 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_16 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_17 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_18 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_19 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_20 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_21 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_22 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_23 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_24 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_25 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_26 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_27 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_28 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_29 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_30 : 1; /* TxRqst128-97 */ + const uint32_t TxRqst_31 : 1; /* TxRqst128-97 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOTRD. */ +typedef volatile struct ALT_CAN_MSGHAND_MOTRD_s ALT_CAN_MSGHAND_MOTRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOTRD register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOTRD_OFST 0x10 +/* The address of the ALT_CAN_MSGHAND_MOTRD register. */ +#define ALT_CAN_MSGHAND_MOTRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOTRD_OFST)) + +/* + * Register : New Data X Register - MONDX + * + * Reading this register allows the CPU to quickly detect if any of the new data + * bits in each of the MONDA, MONDB, MONDC, and MONDD New Data Registers are set. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [0] | R | 0x0 | NewDatA + * [1] | R | 0x0 | NewDatA + * [2] | R | 0x0 | NewDatA + * [3] | R | 0x0 | NewDatA + * [4] | R | 0x0 | NewDatB + * [5] | R | 0x0 | NewDatB + * [6] | R | 0x0 | NewDatB + * [7] | R | 0x0 | NewDatB + * [8] | R | 0x0 | NewDatC + * [9] | R | 0x0 | NewDatC + * [10] | R | 0x0 | NewDatC + * [11] | R | 0x0 | NewDatC + * [12] | R | 0x0 | NewDatD + * [13] | R | 0x0 | NewDatD + * [14] | R | 0x0 | NewDatD + * [15] | R | 0x0 | NewDatD + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NewDatA - NewDatA_0 + * + * Each bit in this field is a logical OR of a byte of the MONDA register. Array + * index i corresponds to byte i of the MONDA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATA_0_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDA don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATA_0_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDA have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATA_0 + * + * The Message Objects in the corresponding byte of MONDA don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_0_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATA_0 + * + * One or more of the Message Objects in the corresponding byte of MONDA have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_0_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATA_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATA_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATA_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATA_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATA_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATA_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATA_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATA_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : NewDatA - NewDatA_1 + * + * Each bit in this field is a logical OR of a byte of the MONDA register. Array + * index i corresponds to byte i of the MONDA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATA_1_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDA don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATA_1_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDA have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATA_1 + * + * The Message Objects in the corresponding byte of MONDA don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_1_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATA_1 + * + * One or more of the Message Objects in the corresponding byte of MONDA have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_1_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATA_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATA_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATA_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATA_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATA_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATA_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATA_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATA_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : NewDatA - NewDatA_2 + * + * Each bit in this field is a logical OR of a byte of the MONDA register. Array + * index i corresponds to byte i of the MONDA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATA_2_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDA don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATA_2_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDA have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATA_2 + * + * The Message Objects in the corresponding byte of MONDA don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_2_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATA_2 + * + * One or more of the Message Objects in the corresponding byte of MONDA have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_2_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATA_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATA_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATA_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATA_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATA_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATA_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATA_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATA_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : NewDatA - NewDatA_3 + * + * Each bit in this field is a logical OR of a byte of the MONDA register. Array + * index i corresponds to byte i of the MONDA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATA_3_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDA don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATA_3_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDA have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATA_3 + * + * The Message Objects in the corresponding byte of MONDA don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_3_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATA_3 + * + * One or more of the Message Objects in the corresponding byte of MONDA have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_3_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATA_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATA_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATA_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATA_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATA_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATA_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATA_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATA_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATA_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NewDatB - NewDatB_0 + * + * Each bit in this field is a logical OR of a byte of the MONDB register. Array + * index i corresponds to byte i of the MONDB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATB_0_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDB don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATB_0_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDB have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATB_0 + * + * The Message Objects in the corresponding byte of MONDB don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_0_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATB_0 + * + * One or more of the Message Objects in the corresponding byte of MONDB have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_0_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATB_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATB_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_0_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATB_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATB_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATB_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATB_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATB_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATB_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : NewDatB - NewDatB_1 + * + * Each bit in this field is a logical OR of a byte of the MONDB register. Array + * index i corresponds to byte i of the MONDB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATB_1_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDB don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATB_1_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDB have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATB_1 + * + * The Message Objects in the corresponding byte of MONDB don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_1_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATB_1 + * + * One or more of the Message Objects in the corresponding byte of MONDB have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_1_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATB_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATB_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_1_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATB_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATB_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATB_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATB_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATB_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATB_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NewDatB - NewDatB_2 + * + * Each bit in this field is a logical OR of a byte of the MONDB register. Array + * index i corresponds to byte i of the MONDB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATB_2_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDB don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATB_2_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDB have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATB_2 + * + * The Message Objects in the corresponding byte of MONDB don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_2_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATB_2 + * + * One or more of the Message Objects in the corresponding byte of MONDB have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_2_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATB_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_2_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATB_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_2_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATB_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATB_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_2_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATB_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_2_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATB_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATB_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_2_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATB_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_2_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : NewDatB - NewDatB_3 + * + * Each bit in this field is a logical OR of a byte of the MONDB register. Array + * index i corresponds to byte i of the MONDB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATB_3_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDB don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATB_3_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDB have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATB_3 + * + * The Message Objects in the corresponding byte of MONDB don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_3_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATB_3 + * + * One or more of the Message Objects in the corresponding byte of MONDB have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_3_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATB_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_3_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATB_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_3_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATB_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATB_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_3_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATB_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_3_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATB_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATB_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_3_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATB_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATB_3_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : NewDatC - NewDatC_0 + * + * Each bit in this field is a logical OR of a byte of the MONDC register. Array + * index i corresponds to byte i of the MONDC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATC_0_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDC don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATC_0_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDC have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATC_0 + * + * The Message Objects in the corresponding byte of MONDC don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_0_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATC_0 + * + * One or more of the Message Objects in the corresponding byte of MONDC have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_0_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATC_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATC_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_0_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATC_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATC_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATC_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATC_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATC_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATC_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : NewDatC - NewDatC_1 + * + * Each bit in this field is a logical OR of a byte of the MONDC register. Array + * index i corresponds to byte i of the MONDC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATC_1_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDC don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATC_1_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDC have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATC_1 + * + * The Message Objects in the corresponding byte of MONDC don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_1_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATC_1 + * + * One or more of the Message Objects in the corresponding byte of MONDC have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_1_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATC_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATC_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_1_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATC_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATC_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATC_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATC_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATC_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATC_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : NewDatC - NewDatC_2 + * + * Each bit in this field is a logical OR of a byte of the MONDC register. Array + * index i corresponds to byte i of the MONDC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATC_2_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDC don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATC_2_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDC have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATC_2 + * + * The Message Objects in the corresponding byte of MONDC don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_2_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATC_2 + * + * One or more of the Message Objects in the corresponding byte of MONDC have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_2_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATC_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_2_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATC_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_2_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATC_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATC_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_2_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATC_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_2_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATC_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATC_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_2_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATC_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_2_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : NewDatC - NewDatC_3 + * + * Each bit in this field is a logical OR of a byte of the MONDC register. Array + * index i corresponds to byte i of the MONDC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATC_3_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDC don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATC_3_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDC have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATC_3 + * + * The Message Objects in the corresponding byte of MONDC don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_3_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATC_3 + * + * One or more of the Message Objects in the corresponding byte of MONDC have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_3_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATC_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_3_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATC_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_3_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATC_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATC_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_3_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATC_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_3_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATC_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATC_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_3_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATC_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATC_3_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : NewDatD - NewDatD_0 + * + * Each bit in this field is a logical OR of a byte of the MONDD register. Array + * index i corresponds to byte i of the MONDD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATD_0_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDD don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATD_0_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDD have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATD_0 + * + * The Message Objects in the corresponding byte of MONDD don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_0_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATD_0 + * + * One or more of the Message Objects in the corresponding byte of MONDD have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_0_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATD_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_0_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATD_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_0_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATD_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATD_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_0_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATD_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_0_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATD_0 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATD_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_0_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATD_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_0_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NewDatD - NewDatD_1 + * + * Each bit in this field is a logical OR of a byte of the MONDD register. Array + * index i corresponds to byte i of the MONDD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATD_1_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDD don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATD_1_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDD have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATD_1 + * + * The Message Objects in the corresponding byte of MONDD don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_1_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATD_1 + * + * One or more of the Message Objects in the corresponding byte of MONDD have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_1_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATD_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_1_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATD_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_1_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATD_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATD_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_1_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATD_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_1_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATD_1 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATD_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_1_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATD_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_1_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NewDatD - NewDatD_2 + * + * Each bit in this field is a logical OR of a byte of the MONDD register. Array + * index i corresponds to byte i of the MONDD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATD_2_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDD don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATD_2_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDD have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATD_2 + * + * The Message Objects in the corresponding byte of MONDD don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_2_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATD_2 + * + * One or more of the Message Objects in the corresponding byte of MONDD have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_2_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATD_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_2_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATD_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_2_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATD_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATD_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_2_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATD_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_2_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATD_2 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATD_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_2_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATD_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_2_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : NewDatD - NewDatD_3 + * + * Each bit in this field is a logical OR of a byte of the MONDD register. Array + * index i corresponds to byte i of the MONDD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDX_NEWDATD_3_E_NOTWRITTEN | 0x0 | The Message Objects in the corresponding byte of + * : | | MONDD don't have new data. + * ALT_CAN_MSGHAND_MONDX_NEWDATD_3_E_WRITTEN | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MONDD have new data + * : | | available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATD_3 + * + * The Message Objects in the corresponding byte of MONDD don't have new data. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_3_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDX_NEWDATD_3 + * + * One or more of the Message Objects in the corresponding byte of MONDD have new + * data available. + */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_3_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATD_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_3_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDX_NEWDATD_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_3_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MONDX_NEWDATD_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDX_NEWDATD_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_3_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDX_NEWDATD_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_3_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MONDX_NEWDATD_3 register field. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDX_NEWDATD_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_3_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MONDX_NEWDATD_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDX_NEWDATD_3_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MONDX. + */ +struct ALT_CAN_MSGHAND_MONDX_s +{ + const uint32_t NewDatA_0 : 1; /* NewDatA */ + const uint32_t NewDatA_1 : 1; /* NewDatA */ + const uint32_t NewDatA_2 : 1; /* NewDatA */ + const uint32_t NewDatA_3 : 1; /* NewDatA */ + const uint32_t NewDatB_0 : 1; /* NewDatB */ + const uint32_t NewDatB_1 : 1; /* NewDatB */ + const uint32_t NewDatB_2 : 1; /* NewDatB */ + const uint32_t NewDatB_3 : 1; /* NewDatB */ + const uint32_t NewDatC_0 : 1; /* NewDatC */ + const uint32_t NewDatC_1 : 1; /* NewDatC */ + const uint32_t NewDatC_2 : 1; /* NewDatC */ + const uint32_t NewDatC_3 : 1; /* NewDatC */ + const uint32_t NewDatD_0 : 1; /* NewDatD */ + const uint32_t NewDatD_1 : 1; /* NewDatD */ + const uint32_t NewDatD_2 : 1; /* NewDatD */ + const uint32_t NewDatD_3 : 1; /* NewDatD */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MONDX. */ +typedef volatile struct ALT_CAN_MSGHAND_MONDX_s ALT_CAN_MSGHAND_MONDX_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MONDX register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MONDX_OFST 0x14 +/* The address of the ALT_CAN_MSGHAND_MONDX register. */ +#define ALT_CAN_MSGHAND_MONDX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MONDX_OFST)) + +/* + * Register : New Data A Register - MONDA + * + * New data bits for Message Objects 1 to 32. By reading the NewDat bits, the CPU + * can check for which Message Object the data portion was updated. The NewDat bit + * of a specific Message Object can be set/reset by the CPU via the IFx Message + * Interface Registers or set by the Message Handler after reception of a Data + * Frame or reset by the Message Handler at start of a transmission. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | NewDat32-1 + * [1] | R | 0x0 | NewDat32-1 + * [2] | R | 0x0 | NewDat32-1 + * [3] | R | 0x0 | NewDat32-1 + * [4] | R | 0x0 | NewDat32-1 + * [5] | R | 0x0 | NewDat32-1 + * [6] | R | 0x0 | NewDat32-1 + * [7] | R | 0x0 | NewDat32-1 + * [8] | R | 0x0 | NewDat32-1 + * [9] | R | 0x0 | NewDat32-1 + * [10] | R | 0x0 | NewDat32-1 + * [11] | R | 0x0 | NewDat32-1 + * [12] | R | 0x0 | NewDat32-1 + * [13] | R | 0x0 | NewDat32-1 + * [14] | R | 0x0 | NewDat32-1 + * [15] | R | 0x0 | NewDat32-1 + * [16] | R | 0x0 | NewDat32-1 + * [17] | R | 0x0 | NewDat32-1 + * [18] | R | 0x0 | NewDat32-1 + * [19] | R | 0x0 | NewDat32-1 + * [20] | R | 0x0 | NewDat32-1 + * [21] | R | 0x0 | NewDat32-1 + * [22] | R | 0x0 | NewDat32-1 + * [23] | R | 0x0 | NewDat32-1 + * [24] | R | 0x0 | NewDat32-1 + * [25] | R | 0x0 | NewDat32-1 + * [26] | R | 0x0 | NewDat32-1 + * [27] | R | 0x0 | NewDat32-1 + * [28] | R | 0x0 | NewDat32-1 + * [29] | R | 0x0 | NewDat32-1 + * [30] | R | 0x0 | NewDat32-1 + * [31] | R | 0x0 | NewDat32-1 + * + */ +/* + * Field : NewDat32-1 - NewDat_0 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_0_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_0_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_0 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_0_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_0 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_0_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : NewDat32-1 - NewDat_1 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_1_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_1_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_1 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_1_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_1 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_1_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : NewDat32-1 - NewDat_2 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_2_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_2_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_2 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_2_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_2 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_2_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : NewDat32-1 - NewDat_3 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_3_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_3_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_3 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_3_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_3 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_3_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NewDat32-1 - NewDat_4 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_4_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_4_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_4 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_4_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_4 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_4_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_4 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_4 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : NewDat32-1 - NewDat_5 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_5_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_5_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_5 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_5_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_5 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_5_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_5 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_5 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NewDat32-1 - NewDat_6 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_6_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_6_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_6 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_6_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_6 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_6_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_6 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_6 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : NewDat32-1 - NewDat_7 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_7_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_7_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_7 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_7_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_7 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_7_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_7 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_7 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : NewDat32-1 - NewDat_8 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_8_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_8_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_8 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_8_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_8 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_8_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_8 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_8 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : NewDat32-1 - NewDat_9 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_9_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_9_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_9 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_9_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_9 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_9_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_9 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_9 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : NewDat32-1 - NewDat_10 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_10_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_10_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_10 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_10_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_10 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_10_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_10 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_10 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : NewDat32-1 - NewDat_11 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_11_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_11_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_11 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_11_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_11 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_11_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_11 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_11 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : NewDat32-1 - NewDat_12 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_12_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_12_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_12 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_12_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_12 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_12_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_12 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_12 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NewDat32-1 - NewDat_13 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_13_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_13_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_13 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_13_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_13 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_13_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_13 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_13 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NewDat32-1 - NewDat_14 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_14_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_14_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_14 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_14_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_14 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_14_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_14 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_14 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : NewDat32-1 - NewDat_15 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_15_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_15_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_15 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_15_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_15 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_15_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_15 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_15 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : NewDat32-1 - NewDat_16 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_16_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_16_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_16 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_16_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_16 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_16_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_16 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_16 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NewDat32-1 - NewDat_17 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_17_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_17_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_17 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_17_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_17 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_17_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_17 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_17 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : NewDat32-1 - NewDat_18 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_18_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_18_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_18 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_18_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_18 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_18_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_18 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_18 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : NewDat32-1 - NewDat_19 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_19_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_19_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_19 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_19_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_19 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_19_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_19 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_19 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : NewDat32-1 - NewDat_20 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_20_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_20_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_20 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_20_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_20 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_20_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_20 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_20 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : NewDat32-1 - NewDat_21 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_21_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_21_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_21 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_21_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_21 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_21_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_21 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_21 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : NewDat32-1 - NewDat_22 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_22_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_22_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_22 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_22_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_22 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_22_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_22 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_22 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : NewDat32-1 - NewDat_23 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_23_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_23_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_23 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_23_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_23 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_23_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_23 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_23 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : NewDat32-1 - NewDat_24 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_24_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_24_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_24 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_24_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_24 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_24_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_24 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_24 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : NewDat32-1 - NewDat_25 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_25_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_25_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_25 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_25_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_25 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_25_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_25 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_25 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : NewDat32-1 - NewDat_26 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_26_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_26_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_26 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_26_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_26 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_26_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_26 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_26 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : NewDat32-1 - NewDat_27 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_27_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_27_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_27 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_27_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_27 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_27_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_27 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_27 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : NewDat32-1 - NewDat_28 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_28_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_28_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_28 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_28_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_28 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_28_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_28 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_28 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : NewDat32-1 - NewDat_29 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_29_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_29_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_29 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_29_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_29 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_29_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_29 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_29 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : NewDat32-1 - NewDat_30 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_30_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_30_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_30 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_30_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_30 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_30_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_30 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_30 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : NewDat32-1 - NewDat_31 + * + * New data bits for Message Objects 1 to 32. Array index i corresponds to Message + * Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDA_NEWDAT_31_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDA_NEWDAT_31_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_31 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_31_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDA_NEWDAT_31 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_31_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDA_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MONDA_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDA_NEWDAT_31 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDA_NEWDAT_31 register field value. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDA_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDA_NEWDAT_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MONDA_NEWDAT_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDA_NEWDAT_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MONDA. + */ +struct ALT_CAN_MSGHAND_MONDA_s +{ + const uint32_t NewDat_0 : 1; /* NewDat32-1 */ + const uint32_t NewDat_1 : 1; /* NewDat32-1 */ + const uint32_t NewDat_2 : 1; /* NewDat32-1 */ + const uint32_t NewDat_3 : 1; /* NewDat32-1 */ + const uint32_t NewDat_4 : 1; /* NewDat32-1 */ + const uint32_t NewDat_5 : 1; /* NewDat32-1 */ + const uint32_t NewDat_6 : 1; /* NewDat32-1 */ + const uint32_t NewDat_7 : 1; /* NewDat32-1 */ + const uint32_t NewDat_8 : 1; /* NewDat32-1 */ + const uint32_t NewDat_9 : 1; /* NewDat32-1 */ + const uint32_t NewDat_10 : 1; /* NewDat32-1 */ + const uint32_t NewDat_11 : 1; /* NewDat32-1 */ + const uint32_t NewDat_12 : 1; /* NewDat32-1 */ + const uint32_t NewDat_13 : 1; /* NewDat32-1 */ + const uint32_t NewDat_14 : 1; /* NewDat32-1 */ + const uint32_t NewDat_15 : 1; /* NewDat32-1 */ + const uint32_t NewDat_16 : 1; /* NewDat32-1 */ + const uint32_t NewDat_17 : 1; /* NewDat32-1 */ + const uint32_t NewDat_18 : 1; /* NewDat32-1 */ + const uint32_t NewDat_19 : 1; /* NewDat32-1 */ + const uint32_t NewDat_20 : 1; /* NewDat32-1 */ + const uint32_t NewDat_21 : 1; /* NewDat32-1 */ + const uint32_t NewDat_22 : 1; /* NewDat32-1 */ + const uint32_t NewDat_23 : 1; /* NewDat32-1 */ + const uint32_t NewDat_24 : 1; /* NewDat32-1 */ + const uint32_t NewDat_25 : 1; /* NewDat32-1 */ + const uint32_t NewDat_26 : 1; /* NewDat32-1 */ + const uint32_t NewDat_27 : 1; /* NewDat32-1 */ + const uint32_t NewDat_28 : 1; /* NewDat32-1 */ + const uint32_t NewDat_29 : 1; /* NewDat32-1 */ + const uint32_t NewDat_30 : 1; /* NewDat32-1 */ + const uint32_t NewDat_31 : 1; /* NewDat32-1 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MONDA. */ +typedef volatile struct ALT_CAN_MSGHAND_MONDA_s ALT_CAN_MSGHAND_MONDA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MONDA register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MONDA_OFST 0x18 +/* The address of the ALT_CAN_MSGHAND_MONDA register. */ +#define ALT_CAN_MSGHAND_MONDA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MONDA_OFST)) + +/* + * Register : New Data B Register - MONDB + * + * New data bits for Message Objects 33 to 64. By reading the NewDat bits, the CPU + * can check for which Message Object the data portion was updated. The NewDat bit + * of a specific Message Object can be set/reset by the CPU via the IFx Message + * Interface Registers or set by the Message Handler after reception of a Data + * Frame or reset by the Message Handler at start of a transmission. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | NewDat64-33 + * [1] | R | 0x0 | NewDat64-33 + * [2] | R | 0x0 | NewDat64-33 + * [3] | R | 0x0 | NewDat64-33 + * [4] | R | 0x0 | NewDat64-33 + * [5] | R | 0x0 | NewDat64-33 + * [6] | R | 0x0 | NewDat64-33 + * [7] | R | 0x0 | NewDat64-33 + * [8] | R | 0x0 | NewDat64-33 + * [9] | R | 0x0 | NewDat64-33 + * [10] | R | 0x0 | NewDat64-33 + * [11] | R | 0x0 | NewDat64-33 + * [12] | R | 0x0 | NewDat64-33 + * [13] | R | 0x0 | NewDat64-33 + * [14] | R | 0x0 | NewDat64-33 + * [15] | R | 0x0 | NewDat64-33 + * [16] | R | 0x0 | NewDat64-33 + * [17] | R | 0x0 | NewDat64-33 + * [18] | R | 0x0 | NewDat64-33 + * [19] | R | 0x0 | NewDat64-33 + * [20] | R | 0x0 | NewDat64-33 + * [21] | R | 0x0 | NewDat64-33 + * [22] | R | 0x0 | NewDat64-33 + * [23] | R | 0x0 | NewDat64-33 + * [24] | R | 0x0 | NewDat64-33 + * [25] | R | 0x0 | NewDat64-33 + * [26] | R | 0x0 | NewDat64-33 + * [27] | R | 0x0 | NewDat64-33 + * [28] | R | 0x0 | NewDat64-33 + * [29] | R | 0x0 | NewDat64-33 + * [30] | R | 0x0 | NewDat64-33 + * [31] | R | 0x0 | NewDat64-33 + * + */ +/* + * Field : NewDat64-33 - NewDat_0 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_0_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_0_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_0 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_0_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_0 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_0_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : NewDat64-33 - NewDat_1 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_1_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_1_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_1 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_1_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_1 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_1_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : NewDat64-33 - NewDat_2 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_2_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_2_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_2 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_2_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_2 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_2_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : NewDat64-33 - NewDat_3 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_3_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_3_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_3 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_3_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_3 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_3_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NewDat64-33 - NewDat_4 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_4_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_4_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_4 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_4_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_4 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_4_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_4 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_4 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : NewDat64-33 - NewDat_5 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_5_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_5_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_5 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_5_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_5 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_5_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_5 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_5 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NewDat64-33 - NewDat_6 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_6_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_6_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_6 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_6_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_6 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_6_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_6 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_6 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : NewDat64-33 - NewDat_7 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_7_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_7_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_7 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_7_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_7 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_7_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_7 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_7 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : NewDat64-33 - NewDat_8 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_8_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_8_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_8 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_8_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_8 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_8_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_8 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_8 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : NewDat64-33 - NewDat_9 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_9_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_9_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_9 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_9_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_9 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_9_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_9 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_9 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : NewDat64-33 - NewDat_10 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_10_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_10_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_10 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_10_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_10 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_10_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_10 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_10 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : NewDat64-33 - NewDat_11 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_11_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_11_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_11 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_11_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_11 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_11_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_11 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_11 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : NewDat64-33 - NewDat_12 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_12_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_12_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_12 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_12_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_12 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_12_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_12 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_12 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NewDat64-33 - NewDat_13 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_13_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_13_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_13 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_13_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_13 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_13_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_13 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_13 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NewDat64-33 - NewDat_14 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_14_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_14_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_14 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_14_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_14 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_14_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_14 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_14 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : NewDat64-33 - NewDat_15 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_15_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_15_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_15 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_15_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_15 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_15_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_15 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_15 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : NewDat64-33 - NewDat_16 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_16_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_16_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_16 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_16_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_16 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_16_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_16 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_16 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NewDat64-33 - NewDat_17 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_17_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_17_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_17 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_17_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_17 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_17_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_17 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_17 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : NewDat64-33 - NewDat_18 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_18_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_18_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_18 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_18_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_18 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_18_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_18 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_18 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : NewDat64-33 - NewDat_19 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_19_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_19_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_19 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_19_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_19 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_19_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_19 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_19 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : NewDat64-33 - NewDat_20 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_20_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_20_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_20 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_20_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_20 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_20_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_20 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_20 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : NewDat64-33 - NewDat_21 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_21_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_21_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_21 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_21_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_21 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_21_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_21 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_21 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : NewDat64-33 - NewDat_22 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_22_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_22_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_22 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_22_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_22 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_22_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_22 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_22 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : NewDat64-33 - NewDat_23 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_23_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_23_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_23 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_23_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_23 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_23_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_23 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_23 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : NewDat64-33 - NewDat_24 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_24_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_24_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_24 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_24_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_24 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_24_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_24 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_24 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : NewDat64-33 - NewDat_25 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_25_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_25_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_25 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_25_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_25 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_25_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_25 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_25 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : NewDat64-33 - NewDat_26 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_26_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_26_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_26 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_26_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_26 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_26_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_26 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_26 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : NewDat64-33 - NewDat_27 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_27_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_27_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_27 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_27_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_27 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_27_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_27 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_27 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : NewDat64-33 - NewDat_28 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_28_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_28_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_28 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_28_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_28 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_28_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_28 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_28 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : NewDat64-33 - NewDat_29 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_29_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_29_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_29 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_29_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_29 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_29_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_29 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_29 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : NewDat64-33 - NewDat_30 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_30_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_30_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_30 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_30_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_30 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_30_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_30 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_30 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : NewDat64-33 - NewDat_31 + * + * New data bits for Message Objects 33 to 64. Array index i corresponds to Message + * Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDB_NEWDAT_31_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDB_NEWDAT_31_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_31 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_31_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDB_NEWDAT_31 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_31_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDB_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MONDB_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDB_NEWDAT_31 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDB_NEWDAT_31 register field value. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDB_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDB_NEWDAT_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MONDB_NEWDAT_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDB_NEWDAT_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MONDB. + */ +struct ALT_CAN_MSGHAND_MONDB_s +{ + const uint32_t NewDat_0 : 1; /* NewDat64-33 */ + const uint32_t NewDat_1 : 1; /* NewDat64-33 */ + const uint32_t NewDat_2 : 1; /* NewDat64-33 */ + const uint32_t NewDat_3 : 1; /* NewDat64-33 */ + const uint32_t NewDat_4 : 1; /* NewDat64-33 */ + const uint32_t NewDat_5 : 1; /* NewDat64-33 */ + const uint32_t NewDat_6 : 1; /* NewDat64-33 */ + const uint32_t NewDat_7 : 1; /* NewDat64-33 */ + const uint32_t NewDat_8 : 1; /* NewDat64-33 */ + const uint32_t NewDat_9 : 1; /* NewDat64-33 */ + const uint32_t NewDat_10 : 1; /* NewDat64-33 */ + const uint32_t NewDat_11 : 1; /* NewDat64-33 */ + const uint32_t NewDat_12 : 1; /* NewDat64-33 */ + const uint32_t NewDat_13 : 1; /* NewDat64-33 */ + const uint32_t NewDat_14 : 1; /* NewDat64-33 */ + const uint32_t NewDat_15 : 1; /* NewDat64-33 */ + const uint32_t NewDat_16 : 1; /* NewDat64-33 */ + const uint32_t NewDat_17 : 1; /* NewDat64-33 */ + const uint32_t NewDat_18 : 1; /* NewDat64-33 */ + const uint32_t NewDat_19 : 1; /* NewDat64-33 */ + const uint32_t NewDat_20 : 1; /* NewDat64-33 */ + const uint32_t NewDat_21 : 1; /* NewDat64-33 */ + const uint32_t NewDat_22 : 1; /* NewDat64-33 */ + const uint32_t NewDat_23 : 1; /* NewDat64-33 */ + const uint32_t NewDat_24 : 1; /* NewDat64-33 */ + const uint32_t NewDat_25 : 1; /* NewDat64-33 */ + const uint32_t NewDat_26 : 1; /* NewDat64-33 */ + const uint32_t NewDat_27 : 1; /* NewDat64-33 */ + const uint32_t NewDat_28 : 1; /* NewDat64-33 */ + const uint32_t NewDat_29 : 1; /* NewDat64-33 */ + const uint32_t NewDat_30 : 1; /* NewDat64-33 */ + const uint32_t NewDat_31 : 1; /* NewDat64-33 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MONDB. */ +typedef volatile struct ALT_CAN_MSGHAND_MONDB_s ALT_CAN_MSGHAND_MONDB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MONDB register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MONDB_OFST 0x1c +/* The address of the ALT_CAN_MSGHAND_MONDB register. */ +#define ALT_CAN_MSGHAND_MONDB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MONDB_OFST)) + +/* + * Register : New Data C Register - MONDC + * + * New data bits for Message Objects 65 to 96. By reading the NewDat bits, the CPU + * can check for which Message Object the data portion was updated. The NewDat bit + * of a specific Message Object can be set/reset by the CPU via the IFx Message + * Interface Registers or set by the Message Handler after reception of a Data + * Frame or reset by the Message Handler at start of a transmission. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | NewDat96-65 + * [1] | R | 0x0 | NewDat96-65 + * [2] | R | 0x0 | NewDat96-65 + * [3] | R | 0x0 | NewDat96-65 + * [4] | R | 0x0 | NewDat96-65 + * [5] | R | 0x0 | NewDat96-65 + * [6] | R | 0x0 | NewDat96-65 + * [7] | R | 0x0 | NewDat96-65 + * [8] | R | 0x0 | NewDat96-65 + * [9] | R | 0x0 | NewDat96-65 + * [10] | R | 0x0 | NewDat96-65 + * [11] | R | 0x0 | NewDat96-65 + * [12] | R | 0x0 | NewDat96-65 + * [13] | R | 0x0 | NewDat96-65 + * [14] | R | 0x0 | NewDat96-65 + * [15] | R | 0x0 | NewDat96-65 + * [16] | R | 0x0 | NewDat96-65 + * [17] | R | 0x0 | NewDat96-65 + * [18] | R | 0x0 | NewDat96-65 + * [19] | R | 0x0 | NewDat96-65 + * [20] | R | 0x0 | NewDat96-65 + * [21] | R | 0x0 | NewDat96-65 + * [22] | R | 0x0 | NewDat96-65 + * [23] | R | 0x0 | NewDat96-65 + * [24] | R | 0x0 | NewDat96-65 + * [25] | R | 0x0 | NewDat96-65 + * [26] | R | 0x0 | NewDat96-65 + * [27] | R | 0x0 | NewDat96-65 + * [28] | R | 0x0 | NewDat96-65 + * [29] | R | 0x0 | NewDat96-65 + * [30] | R | 0x0 | NewDat96-65 + * [31] | R | 0x0 | NewDat96-65 + * + */ +/* + * Field : NewDat96-65 - NewDat_0 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_0_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_0_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_0 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_0_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_0 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_0_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : NewDat96-65 - NewDat_1 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_1_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_1_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_1 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_1_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_1 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_1_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : NewDat96-65 - NewDat_2 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_2_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_2_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_2 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_2_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_2 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_2_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : NewDat96-65 - NewDat_3 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_3_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_3_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_3 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_3_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_3 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_3_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NewDat96-65 - NewDat_4 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_4_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_4_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_4 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_4_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_4 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_4_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_4 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_4 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : NewDat96-65 - NewDat_5 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_5_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_5_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_5 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_5_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_5 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_5_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_5 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_5 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NewDat96-65 - NewDat_6 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_6_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_6_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_6 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_6_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_6 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_6_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_6 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_6 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : NewDat96-65 - NewDat_7 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_7_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_7_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_7 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_7_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_7 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_7_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_7 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_7 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : NewDat96-65 - NewDat_8 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_8_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_8_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_8 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_8_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_8 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_8_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_8 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_8 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : NewDat96-65 - NewDat_9 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_9_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_9_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_9 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_9_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_9 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_9_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_9 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_9 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : NewDat96-65 - NewDat_10 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_10_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_10_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_10 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_10_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_10 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_10_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_10 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_10 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : NewDat96-65 - NewDat_11 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_11_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_11_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_11 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_11_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_11 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_11_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_11 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_11 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : NewDat96-65 - NewDat_12 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_12_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_12_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_12 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_12_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_12 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_12_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_12 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_12 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NewDat96-65 - NewDat_13 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_13_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_13_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_13 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_13_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_13 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_13_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_13 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_13 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NewDat96-65 - NewDat_14 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_14_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_14_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_14 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_14_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_14 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_14_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_14 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_14 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : NewDat96-65 - NewDat_15 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_15_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_15_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_15 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_15_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_15 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_15_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_15 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_15 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : NewDat96-65 - NewDat_16 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_16_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_16_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_16 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_16_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_16 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_16_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_16 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_16 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NewDat96-65 - NewDat_17 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_17_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_17_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_17 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_17_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_17 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_17_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_17 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_17 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : NewDat96-65 - NewDat_18 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_18_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_18_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_18 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_18_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_18 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_18_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_18 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_18 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : NewDat96-65 - NewDat_19 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_19_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_19_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_19 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_19_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_19 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_19_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_19 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_19 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : NewDat96-65 - NewDat_20 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_20_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_20_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_20 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_20_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_20 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_20_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_20 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_20 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : NewDat96-65 - NewDat_21 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_21_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_21_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_21 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_21_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_21 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_21_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_21 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_21 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : NewDat96-65 - NewDat_22 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_22_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_22_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_22 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_22_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_22 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_22_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_22 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_22 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : NewDat96-65 - NewDat_23 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_23_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_23_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_23 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_23_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_23 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_23_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_23 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_23 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : NewDat96-65 - NewDat_24 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_24_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_24_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_24 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_24_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_24 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_24_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_24 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_24 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : NewDat96-65 - NewDat_25 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_25_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_25_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_25 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_25_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_25 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_25_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_25 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_25 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : NewDat96-65 - NewDat_26 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_26_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_26_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_26 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_26_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_26 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_26_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_26 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_26 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : NewDat96-65 - NewDat_27 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_27_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_27_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_27 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_27_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_27 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_27_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_27 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_27 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : NewDat96-65 - NewDat_28 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_28_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_28_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_28 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_28_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_28 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_28_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_28 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_28 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : NewDat96-65 - NewDat_29 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_29_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_29_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_29 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_29_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_29 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_29_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_29 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_29 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : NewDat96-65 - NewDat_30 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_30_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_30_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_30 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_30_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_30 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_30_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_30 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_30 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : NewDat96-65 - NewDat_31 + * + * New data bits for Message Objects 65 to 96. Array index i corresponds to Message + * Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDC_NEWDAT_31_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDC_NEWDAT_31_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_31 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_31_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDC_NEWDAT_31 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_31_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDC_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MONDC_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDC_NEWDAT_31 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDC_NEWDAT_31 register field value. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDC_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDC_NEWDAT_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MONDC_NEWDAT_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDC_NEWDAT_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MONDC. + */ +struct ALT_CAN_MSGHAND_MONDC_s +{ + const uint32_t NewDat_0 : 1; /* NewDat96-65 */ + const uint32_t NewDat_1 : 1; /* NewDat96-65 */ + const uint32_t NewDat_2 : 1; /* NewDat96-65 */ + const uint32_t NewDat_3 : 1; /* NewDat96-65 */ + const uint32_t NewDat_4 : 1; /* NewDat96-65 */ + const uint32_t NewDat_5 : 1; /* NewDat96-65 */ + const uint32_t NewDat_6 : 1; /* NewDat96-65 */ + const uint32_t NewDat_7 : 1; /* NewDat96-65 */ + const uint32_t NewDat_8 : 1; /* NewDat96-65 */ + const uint32_t NewDat_9 : 1; /* NewDat96-65 */ + const uint32_t NewDat_10 : 1; /* NewDat96-65 */ + const uint32_t NewDat_11 : 1; /* NewDat96-65 */ + const uint32_t NewDat_12 : 1; /* NewDat96-65 */ + const uint32_t NewDat_13 : 1; /* NewDat96-65 */ + const uint32_t NewDat_14 : 1; /* NewDat96-65 */ + const uint32_t NewDat_15 : 1; /* NewDat96-65 */ + const uint32_t NewDat_16 : 1; /* NewDat96-65 */ + const uint32_t NewDat_17 : 1; /* NewDat96-65 */ + const uint32_t NewDat_18 : 1; /* NewDat96-65 */ + const uint32_t NewDat_19 : 1; /* NewDat96-65 */ + const uint32_t NewDat_20 : 1; /* NewDat96-65 */ + const uint32_t NewDat_21 : 1; /* NewDat96-65 */ + const uint32_t NewDat_22 : 1; /* NewDat96-65 */ + const uint32_t NewDat_23 : 1; /* NewDat96-65 */ + const uint32_t NewDat_24 : 1; /* NewDat96-65 */ + const uint32_t NewDat_25 : 1; /* NewDat96-65 */ + const uint32_t NewDat_26 : 1; /* NewDat96-65 */ + const uint32_t NewDat_27 : 1; /* NewDat96-65 */ + const uint32_t NewDat_28 : 1; /* NewDat96-65 */ + const uint32_t NewDat_29 : 1; /* NewDat96-65 */ + const uint32_t NewDat_30 : 1; /* NewDat96-65 */ + const uint32_t NewDat_31 : 1; /* NewDat96-65 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MONDC. */ +typedef volatile struct ALT_CAN_MSGHAND_MONDC_s ALT_CAN_MSGHAND_MONDC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MONDC register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MONDC_OFST 0x20 +/* The address of the ALT_CAN_MSGHAND_MONDC register. */ +#define ALT_CAN_MSGHAND_MONDC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MONDC_OFST)) + +/* + * Register : New Data D Register - MONDD + * + * New data bits for Message Objects 97 to 128. By reading the NewDat bits, the + * CPU can check for which Message Object the data portion was updated. The NewDat + * bit of a specific Message Object can be set/reset by the CPU via the IFx Message + * Interface Registers or set by the Message Handler after reception of a Data + * Frame or reset by the Message Handler at start of a transmission. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------- + * [0] | R | 0x0 | NewDat128-97 + * [1] | R | 0x0 | NewDat128-97 + * [2] | R | 0x0 | NewDat128-97 + * [3] | R | 0x0 | NewDat128-97 + * [4] | R | 0x0 | NewDat128-97 + * [5] | R | 0x0 | NewDat128-97 + * [6] | R | 0x0 | NewDat128-97 + * [7] | R | 0x0 | NewDat128-97 + * [8] | R | 0x0 | NewDat128-97 + * [9] | R | 0x0 | NewDat128-97 + * [10] | R | 0x0 | NewDat128-97 + * [11] | R | 0x0 | NewDat128-97 + * [12] | R | 0x0 | NewDat128-97 + * [13] | R | 0x0 | NewDat128-97 + * [14] | R | 0x0 | NewDat128-97 + * [15] | R | 0x0 | NewDat128-97 + * [16] | R | 0x0 | NewDat128-97 + * [17] | R | 0x0 | NewDat128-97 + * [18] | R | 0x0 | NewDat128-97 + * [19] | R | 0x0 | NewDat128-97 + * [20] | R | 0x0 | NewDat128-97 + * [21] | R | 0x0 | NewDat128-97 + * [22] | R | 0x0 | NewDat128-97 + * [23] | R | 0x0 | NewDat128-97 + * [24] | R | 0x0 | NewDat128-97 + * [25] | R | 0x0 | NewDat128-97 + * [26] | R | 0x0 | NewDat128-97 + * [27] | R | 0x0 | NewDat128-97 + * [28] | R | 0x0 | NewDat128-97 + * [29] | R | 0x0 | NewDat128-97 + * [30] | R | 0x0 | NewDat128-97 + * [31] | R | 0x0 | NewDat128-97 + * + */ +/* + * Field : NewDat128-97 - NewDat_0 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_0_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_0_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_0 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_0_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_0 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_0_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_0 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_0 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : NewDat128-97 - NewDat_1 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_1_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_1_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_1 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_1_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_1 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_1_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_1 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_1 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : NewDat128-97 - NewDat_2 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_2_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_2_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_2 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_2_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_2 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_2_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_2 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_2 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : NewDat128-97 - NewDat_3 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_3_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_3_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_3 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_3_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_3 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_3_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_3 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_3 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NewDat128-97 - NewDat_4 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_4_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_4_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_4 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_4_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_4 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_4_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_4 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_4 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_4 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : NewDat128-97 - NewDat_5 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_5_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_5_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_5 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_5_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_5 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_5_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_5 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_5 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_5 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NewDat128-97 - NewDat_6 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_6_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_6_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_6 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_6_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_6 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_6_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_6 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_6 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_6 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : NewDat128-97 - NewDat_7 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_7_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_7_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_7 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_7_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_7 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_7_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_7 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_7 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_7 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : NewDat128-97 - NewDat_8 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_8_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_8_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_8 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_8_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_8 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_8_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_8 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_8 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_8 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : NewDat128-97 - NewDat_9 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_9_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_9_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_9 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_9_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_9 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_9_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_9 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_9 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_9 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : NewDat128-97 - NewDat_10 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_10_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_10_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_10 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_10_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_10 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_10_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_10 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_10 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_10 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : NewDat128-97 - NewDat_11 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_11_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_11_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_11 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_11_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_11 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_11_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_11 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_11 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_11 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : NewDat128-97 - NewDat_12 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_12_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_12_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_12 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_12_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_12 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_12_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_12 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_12 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_12 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NewDat128-97 - NewDat_13 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_13_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_13_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_13 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_13_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_13 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_13_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_13 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_13 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_13 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NewDat128-97 - NewDat_14 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_14_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_14_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_14 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_14_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_14 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_14_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_14 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_14 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_14 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : NewDat128-97 - NewDat_15 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_15_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_15_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_15 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_15_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_15 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_15_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_15 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_15 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_15 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : NewDat128-97 - NewDat_16 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_16_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_16_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_16 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_16_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_16 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_16_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_16 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_16 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_16 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NewDat128-97 - NewDat_17 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_17_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_17_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_17 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_17_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_17 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_17_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_17 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_17 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_17 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : NewDat128-97 - NewDat_18 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_18_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_18_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_18 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_18_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_18 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_18_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_18 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_18 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_18 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : NewDat128-97 - NewDat_19 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_19_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_19_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_19 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_19_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_19 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_19_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_19 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_19 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_19 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : NewDat128-97 - NewDat_20 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_20_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_20_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_20 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_20_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_20 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_20_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_20 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_20 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_20 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : NewDat128-97 - NewDat_21 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_21_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_21_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_21 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_21_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_21 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_21_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_21 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_21 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_21 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : NewDat128-97 - NewDat_22 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_22_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_22_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_22 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_22_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_22 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_22_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_22 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_22 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_22 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : NewDat128-97 - NewDat_23 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_23_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_23_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_23 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_23_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_23 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_23_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_23 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_23 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_23 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : NewDat128-97 - NewDat_24 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_24_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_24_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_24 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_24_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_24 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_24_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_24 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_24 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_24 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : NewDat128-97 - NewDat_25 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_25_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_25_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_25 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_25_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_25 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_25_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_25 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_25 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_25 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : NewDat128-97 - NewDat_26 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_26_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_26_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_26 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_26_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_26 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_26_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_26 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_26 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_26 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : NewDat128-97 - NewDat_27 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_27_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_27_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_27 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_27_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_27 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_27_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_27 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_27 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_27 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : NewDat128-97 - NewDat_28 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_28_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_28_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_28 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_28_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_28 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_28_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_28 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_28 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_28 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : NewDat128-97 - NewDat_29 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_29_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_29_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_29 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_29_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_29 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_29_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_29 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_29 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_29 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : NewDat128-97 - NewDat_30 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_30_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_30_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_30 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_30_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_30 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_30_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_30 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_30 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_30 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : NewDat128-97 - NewDat_31 + * + * New data bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MONDD_NEWDAT_31_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGHAND_MONDD_NEWDAT_31_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_31 + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_31_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MONDD_NEWDAT_31 + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_31_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MONDD_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MONDD_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MONDD_NEWDAT_31 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MONDD_NEWDAT_31 register field value. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MONDD_NEWDAT_31 register field. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MONDD_NEWDAT_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MONDD_NEWDAT_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MONDD_NEWDAT_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MONDD. + */ +struct ALT_CAN_MSGHAND_MONDD_s +{ + const uint32_t NewDat_0 : 1; /* NewDat128-97 */ + const uint32_t NewDat_1 : 1; /* NewDat128-97 */ + const uint32_t NewDat_2 : 1; /* NewDat128-97 */ + const uint32_t NewDat_3 : 1; /* NewDat128-97 */ + const uint32_t NewDat_4 : 1; /* NewDat128-97 */ + const uint32_t NewDat_5 : 1; /* NewDat128-97 */ + const uint32_t NewDat_6 : 1; /* NewDat128-97 */ + const uint32_t NewDat_7 : 1; /* NewDat128-97 */ + const uint32_t NewDat_8 : 1; /* NewDat128-97 */ + const uint32_t NewDat_9 : 1; /* NewDat128-97 */ + const uint32_t NewDat_10 : 1; /* NewDat128-97 */ + const uint32_t NewDat_11 : 1; /* NewDat128-97 */ + const uint32_t NewDat_12 : 1; /* NewDat128-97 */ + const uint32_t NewDat_13 : 1; /* NewDat128-97 */ + const uint32_t NewDat_14 : 1; /* NewDat128-97 */ + const uint32_t NewDat_15 : 1; /* NewDat128-97 */ + const uint32_t NewDat_16 : 1; /* NewDat128-97 */ + const uint32_t NewDat_17 : 1; /* NewDat128-97 */ + const uint32_t NewDat_18 : 1; /* NewDat128-97 */ + const uint32_t NewDat_19 : 1; /* NewDat128-97 */ + const uint32_t NewDat_20 : 1; /* NewDat128-97 */ + const uint32_t NewDat_21 : 1; /* NewDat128-97 */ + const uint32_t NewDat_22 : 1; /* NewDat128-97 */ + const uint32_t NewDat_23 : 1; /* NewDat128-97 */ + const uint32_t NewDat_24 : 1; /* NewDat128-97 */ + const uint32_t NewDat_25 : 1; /* NewDat128-97 */ + const uint32_t NewDat_26 : 1; /* NewDat128-97 */ + const uint32_t NewDat_27 : 1; /* NewDat128-97 */ + const uint32_t NewDat_28 : 1; /* NewDat128-97 */ + const uint32_t NewDat_29 : 1; /* NewDat128-97 */ + const uint32_t NewDat_30 : 1; /* NewDat128-97 */ + const uint32_t NewDat_31 : 1; /* NewDat128-97 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MONDD. */ +typedef volatile struct ALT_CAN_MSGHAND_MONDD_s ALT_CAN_MSGHAND_MONDD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MONDD register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MONDD_OFST 0x24 +/* The address of the ALT_CAN_MSGHAND_MONDD register. */ +#define ALT_CAN_MSGHAND_MONDD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MONDD_OFST)) + +/* + * Register : Interrupt Pending X Register - MOIPX + * + * Reading this register allows the CPU to quickly detect if any of the interrupt + * pending bits in each of the MOIPA, MOIPB, MOIPC, and MOIPD Interrupt Pending + * Registers are set. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [0] | R | 0x0 | IntPndA + * [1] | R | 0x0 | IntPndA + * [2] | R | 0x0 | IntPndA + * [3] | R | 0x0 | IntPndA + * [4] | R | 0x0 | IntPndB + * [5] | R | 0x0 | IntPndB + * [6] | R | 0x0 | IntPndB + * [7] | R | 0x0 | IntPndB + * [8] | R | 0x0 | IntPndC + * [9] | R | 0x0 | IntPndC + * [10] | R | 0x0 | IntPndC + * [11] | R | 0x0 | IntPndC + * [12] | R | 0x0 | IntPndD + * [13] | R | 0x0 | IntPndD + * [14] | R | 0x0 | IntPndD + * [15] | R | 0x0 | IntPndD + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IntPndA - IntPndA_0 + * + * Each bit in this field is a logical OR of a byte of the MOIPA register. Array + * index i corresponds to byte i of the MOIPA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPA are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPA are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDA_0 + * + * The Message Objects in the corresponding byte of MOIPA are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDA_0 + * + * One or more of the Message Objects in the corresponding byte of MOIPA are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDA_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDA_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDA_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDA_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IntPndA - IntPndA_1 + * + * Each bit in this field is a logical OR of a byte of the MOIPA register. Array + * index i corresponds to byte i of the MOIPA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPA are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPA are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDA_1 + * + * The Message Objects in the corresponding byte of MOIPA are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDA_1 + * + * One or more of the Message Objects in the corresponding byte of MOIPA are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDA_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDA_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDA_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDA_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IntPndA - IntPndA_2 + * + * Each bit in this field is a logical OR of a byte of the MOIPA register. Array + * index i corresponds to byte i of the MOIPA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPA are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPA are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDA_2 + * + * The Message Objects in the corresponding byte of MOIPA are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDA_2 + * + * One or more of the Message Objects in the corresponding byte of MOIPA are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDA_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDA_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDA_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDA_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IntPndA - IntPndA_3 + * + * Each bit in this field is a logical OR of a byte of the MOIPA register. Array + * index i corresponds to byte i of the MOIPA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPA are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPA are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDA_3 + * + * The Message Objects in the corresponding byte of MOIPA are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDA_3 + * + * One or more of the Message Objects in the corresponding byte of MOIPA are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDA_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDA_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDA_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDA_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDA_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDA_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IntPndB - IntPndB_0 + * + * Each bit in this field is a logical OR of a byte of the MOIPB register. Array + * index i corresponds to byte i of the MOIPB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPB are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPB are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDB_0 + * + * The Message Objects in the corresponding byte of MOIPB are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDB_0 + * + * One or more of the Message Objects in the corresponding byte of MOIPB are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDB_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDB_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDB_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDB_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IntPndB - IntPndB_1 + * + * Each bit in this field is a logical OR of a byte of the MOIPB register. Array + * index i corresponds to byte i of the MOIPB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPB are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPB are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDB_1 + * + * The Message Objects in the corresponding byte of MOIPB are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDB_1 + * + * One or more of the Message Objects in the corresponding byte of MOIPB are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDB_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDB_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDB_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDB_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IntPndB - IntPndB_2 + * + * Each bit in this field is a logical OR of a byte of the MOIPB register. Array + * index i corresponds to byte i of the MOIPB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPB are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPB are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDB_2 + * + * The Message Objects in the corresponding byte of MOIPB are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDB_2 + * + * One or more of the Message Objects in the corresponding byte of MOIPB are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDB_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDB_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDB_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDB_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_2_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IntPndB - IntPndB_3 + * + * Each bit in this field is a logical OR of a byte of the MOIPB register. Array + * index i corresponds to byte i of the MOIPB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPB are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPB are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDB_3 + * + * The Message Objects in the corresponding byte of MOIPB are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDB_3 + * + * One or more of the Message Objects in the corresponding byte of MOIPB are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDB_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDB_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDB_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDB_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDB_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDB_3_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : IntPndC - IntPndC_0 + * + * Each bit in this field is a logical OR of a byte of the MOIPC register. Array + * index i corresponds to byte i of the MOIPC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPC are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPC are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDC_0 + * + * The Message Objects in the corresponding byte of MOIPC are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDC_0 + * + * One or more of the Message Objects in the corresponding byte of MOIPC are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDC_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDC_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDC_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDC_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : IntPndC - IntPndC_1 + * + * Each bit in this field is a logical OR of a byte of the MOIPC register. Array + * index i corresponds to byte i of the MOIPC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPC are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPC are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDC_1 + * + * The Message Objects in the corresponding byte of MOIPC are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDC_1 + * + * One or more of the Message Objects in the corresponding byte of MOIPC are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDC_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDC_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDC_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDC_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : IntPndC - IntPndC_2 + * + * Each bit in this field is a logical OR of a byte of the MOIPC register. Array + * index i corresponds to byte i of the MOIPC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPC are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPC are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDC_2 + * + * The Message Objects in the corresponding byte of MOIPC are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDC_2 + * + * One or more of the Message Objects in the corresponding byte of MOIPC are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDC_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDC_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDC_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDC_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_2_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : IntPndC - IntPndC_3 + * + * Each bit in this field is a logical OR of a byte of the MOIPC register. Array + * index i corresponds to byte i of the MOIPC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPC are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPC are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDC_3 + * + * The Message Objects in the corresponding byte of MOIPC are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDC_3 + * + * One or more of the Message Objects in the corresponding byte of MOIPC are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDC_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDC_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDC_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDC_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDC_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDC_3_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : IntPndD - IntPndD_0 + * + * Each bit in this field is a logical OR of a byte of the MOIPD register. Array + * index i corresponds to byte i of the MOIPD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPD are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPD are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDD_0 + * + * The Message Objects in the corresponding byte of MOIPD are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDD_0 + * + * One or more of the Message Objects in the corresponding byte of MOIPD are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDD_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDD_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDD_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDD_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_0_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : IntPndD - IntPndD_1 + * + * Each bit in this field is a logical OR of a byte of the MOIPD register. Array + * index i corresponds to byte i of the MOIPD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPD are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPD are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDD_1 + * + * The Message Objects in the corresponding byte of MOIPD are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDD_1 + * + * One or more of the Message Objects in the corresponding byte of MOIPD are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDD_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDD_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDD_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDD_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_1_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : IntPndD - IntPndD_2 + * + * Each bit in this field is a logical OR of a byte of the MOIPD register. Array + * index i corresponds to byte i of the MOIPD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPD are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPD are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDD_2 + * + * The Message Objects in the corresponding byte of MOIPD are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDD_2 + * + * One or more of the Message Objects in the corresponding byte of MOIPD are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDD_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDD_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDD_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDD_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_2_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : IntPndD - IntPndD_3 + * + * Each bit in this field is a logical OR of a byte of the MOIPD register. Array + * index i corresponds to byte i of the MOIPD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_E_NOTSRC | 0x0 | The Message Objects in the corresponding byte of + * : | | MOIPD are not the source of an interrupt. + * ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_E_SRC | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOIPD are the source an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDD_3 + * + * The Message Objects in the corresponding byte of MOIPD are not the source of an + * interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPX_INTPNDD_3 + * + * One or more of the Message Objects in the corresponding byte of MOIPD are the + * source an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPX_INTPNDD_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPX_INTPNDD_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOIPX_INTPNDD_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPX_INTPNDD_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOIPX_INTPNDD_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPX_INTPNDD_3_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOIPX. + */ +struct ALT_CAN_MSGHAND_MOIPX_s +{ + const uint32_t IntPndA_0 : 1; /* IntPndA */ + const uint32_t IntPndA_1 : 1; /* IntPndA */ + const uint32_t IntPndA_2 : 1; /* IntPndA */ + const uint32_t IntPndA_3 : 1; /* IntPndA */ + const uint32_t IntPndB_0 : 1; /* IntPndB */ + const uint32_t IntPndB_1 : 1; /* IntPndB */ + const uint32_t IntPndB_2 : 1; /* IntPndB */ + const uint32_t IntPndB_3 : 1; /* IntPndB */ + const uint32_t IntPndC_0 : 1; /* IntPndC */ + const uint32_t IntPndC_1 : 1; /* IntPndC */ + const uint32_t IntPndC_2 : 1; /* IntPndC */ + const uint32_t IntPndC_3 : 1; /* IntPndC */ + const uint32_t IntPndD_0 : 1; /* IntPndD */ + const uint32_t IntPndD_1 : 1; /* IntPndD */ + const uint32_t IntPndD_2 : 1; /* IntPndD */ + const uint32_t IntPndD_3 : 1; /* IntPndD */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOIPX. */ +typedef volatile struct ALT_CAN_MSGHAND_MOIPX_s ALT_CAN_MSGHAND_MOIPX_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOIPX register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOIPX_OFST 0x28 +/* The address of the ALT_CAN_MSGHAND_MOIPX register. */ +#define ALT_CAN_MSGHAND_MOIPX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOIPX_OFST)) + +/* + * Register : Interrupt Pending A Register - MOIPA + * + * Interrupt pending bits for Message Objects 1 to 32. By reading the IntPnd bits, + * the CPU can check for which Message Object an interrupt is pending. The IntPnd + * bit of a specific Message Object can be set/reset by the CPU via the IFx Message + * Interface Registers or set by the Message Handler after reception or after a + * successful transmission of a frame. This will also affect the valid of IntID in + * the Interrupt Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | IntPnd32-1 + * [1] | R | 0x0 | IntPnd32-1 + * [2] | R | 0x0 | IntPnd32-1 + * [3] | R | 0x0 | IntPnd32-1 + * [4] | R | 0x0 | IntPnd32-1 + * [5] | R | 0x0 | IntPnd32-1 + * [6] | R | 0x0 | IntPnd32-1 + * [7] | R | 0x0 | IntPnd32-1 + * [8] | R | 0x0 | IntPnd32-1 + * [9] | R | 0x0 | IntPnd32-1 + * [10] | R | 0x0 | IntPnd32-1 + * [11] | R | 0x0 | IntPnd32-1 + * [12] | R | 0x0 | IntPnd32-1 + * [13] | R | 0x0 | IntPnd32-1 + * [14] | R | 0x0 | IntPnd32-1 + * [15] | R | 0x0 | IntPnd32-1 + * [16] | R | 0x0 | IntPnd32-1 + * [17] | R | 0x0 | IntPnd32-1 + * [18] | R | 0x0 | IntPnd32-1 + * [19] | R | 0x0 | IntPnd32-1 + * [20] | R | 0x0 | IntPnd32-1 + * [21] | R | 0x0 | IntPnd32-1 + * [22] | R | 0x0 | IntPnd32-1 + * [23] | R | 0x0 | IntPnd32-1 + * [24] | R | 0x0 | IntPnd32-1 + * [25] | R | 0x0 | IntPnd32-1 + * [26] | R | 0x0 | IntPnd32-1 + * [27] | R | 0x0 | IntPnd32-1 + * [28] | R | 0x0 | IntPnd32-1 + * [29] | R | 0x0 | IntPnd32-1 + * [30] | R | 0x0 | IntPnd32-1 + * [31] | R | 0x0 | IntPnd32-1 + * + */ +/* + * Field : IntPnd32-1 - IntPnd_0 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_0_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_0_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_0 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_0_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_0 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_0_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IntPnd32-1 - IntPnd_1 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_1_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_1_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_1 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_1_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_1 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_1_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IntPnd32-1 - IntPnd_2 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_2_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_2_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_2 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_2_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_2 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_2_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IntPnd32-1 - IntPnd_3 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_3_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_3_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_3 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_3_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_3 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_3_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IntPnd32-1 - IntPnd_4 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_4_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_4_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_4 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_4_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_4 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_4_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_4 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_4 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IntPnd32-1 - IntPnd_5 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_5_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_5_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_5 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_5_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_5 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_5_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_5 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_5 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IntPnd32-1 - IntPnd_6 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_6_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_6_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_6 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_6_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_6 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_6_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_6 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_6 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IntPnd32-1 - IntPnd_7 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_7_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_7_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_7 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_7_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_7 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_7_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_7 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_7 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : IntPnd32-1 - IntPnd_8 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_8_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_8_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_8 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_8_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_8 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_8_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_8 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_8 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : IntPnd32-1 - IntPnd_9 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_9_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_9_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_9 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_9_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_9 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_9_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_9 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_9 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : IntPnd32-1 - IntPnd_10 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_10_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_10_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_10 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_10_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_10 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_10_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_10 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_10 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : IntPnd32-1 - IntPnd_11 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_11_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_11_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_11 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_11_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_11 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_11_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_11 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_11 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : IntPnd32-1 - IntPnd_12 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_12_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_12_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_12 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_12_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_12 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_12_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_12 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_12 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : IntPnd32-1 - IntPnd_13 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_13_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_13_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_13 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_13_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_13 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_13_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_13 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_13 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : IntPnd32-1 - IntPnd_14 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_14_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_14_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_14 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_14_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_14 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_14_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_14 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_14 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : IntPnd32-1 - IntPnd_15 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_15_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_15_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_15 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_15_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_15 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_15_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_15 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_15 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : IntPnd32-1 - IntPnd_16 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_16_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_16_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_16 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_16_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_16 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_16_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_16 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_16 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : IntPnd32-1 - IntPnd_17 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_17_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_17_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_17 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_17_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_17 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_17_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_17 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_17 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : IntPnd32-1 - IntPnd_18 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_18_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_18_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_18 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_18_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_18 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_18_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_18 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_18 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : IntPnd32-1 - IntPnd_19 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_19_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_19_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_19 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_19_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_19 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_19_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_19 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_19 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : IntPnd32-1 - IntPnd_20 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_20_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_20_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_20 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_20_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_20 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_20_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_20 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_20 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : IntPnd32-1 - IntPnd_21 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_21_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_21_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_21 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_21_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_21 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_21_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_21 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_21 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : IntPnd32-1 - IntPnd_22 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_22_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_22_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_22 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_22_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_22 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_22_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_22 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_22 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : IntPnd32-1 - IntPnd_23 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_23_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_23_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_23 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_23_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_23 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_23_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_23 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_23 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : IntPnd32-1 - IntPnd_24 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_24_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_24_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_24 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_24_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_24 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_24_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_24 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_24 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : IntPnd32-1 - IntPnd_25 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_25_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_25_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_25 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_25_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_25 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_25_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_25 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_25 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : IntPnd32-1 - IntPnd_26 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_26_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_26_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_26 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_26_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_26 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_26_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_26 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_26 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : IntPnd32-1 - IntPnd_27 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_27_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_27_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_27 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_27_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_27 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_27_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_27 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_27 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : IntPnd32-1 - IntPnd_28 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_28_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_28_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_28 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_28_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_28 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_28_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_28 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_28 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : IntPnd32-1 - IntPnd_29 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_29_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_29_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_29 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_29_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_29 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_29_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_29 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_29 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : IntPnd32-1 - IntPnd_30 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_30_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_30_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_30 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_30_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_30 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_30_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_30 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_30 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : IntPnd32-1 - IntPnd_31 + * + * Interrupt pending bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPA_INTPND_31_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPA_INTPND_31_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_31 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_31_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPA_INTPND_31 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_31_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPA_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPA_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPA_INTPND_31 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPA_INTPND_31 register field value. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPA_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPA_INTPND_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOIPA_INTPND_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPA_INTPND_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOIPA. + */ +struct ALT_CAN_MSGHAND_MOIPA_s +{ + const uint32_t IntPnd_0 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_1 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_2 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_3 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_4 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_5 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_6 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_7 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_8 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_9 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_10 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_11 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_12 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_13 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_14 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_15 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_16 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_17 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_18 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_19 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_20 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_21 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_22 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_23 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_24 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_25 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_26 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_27 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_28 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_29 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_30 : 1; /* IntPnd32-1 */ + const uint32_t IntPnd_31 : 1; /* IntPnd32-1 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOIPA. */ +typedef volatile struct ALT_CAN_MSGHAND_MOIPA_s ALT_CAN_MSGHAND_MOIPA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOIPA register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOIPA_OFST 0x2c +/* The address of the ALT_CAN_MSGHAND_MOIPA register. */ +#define ALT_CAN_MSGHAND_MOIPA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOIPA_OFST)) + +/* + * Register : Interrupt Pending B Register - MOIPB + * + * Interrupt pending bits for Message Objects 33 to 64. By reading the IntPnd + * bits, the CPU can check for which Message Object an interrupt is pending. The + * IntPnd bit of a specific Message Object can be set/reset by the CPU via the IFx + * Message Interface Registers or set by the Message Handler after reception or + * after a successful transmission of a frame. This will also affect the valid of + * IntID in the Interrupt Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | IntPnd64-33 + * [1] | R | 0x0 | IntPnd64-33 + * [2] | R | 0x0 | IntPnd64-33 + * [3] | R | 0x0 | IntPnd64-33 + * [4] | R | 0x0 | IntPnd64-33 + * [5] | R | 0x0 | IntPnd64-33 + * [6] | R | 0x0 | IntPnd64-33 + * [7] | R | 0x0 | IntPnd64-33 + * [8] | R | 0x0 | IntPnd64-33 + * [9] | R | 0x0 | IntPnd64-33 + * [10] | R | 0x0 | IntPnd64-33 + * [11] | R | 0x0 | IntPnd64-33 + * [12] | R | 0x0 | IntPnd64-33 + * [13] | R | 0x0 | IntPnd64-33 + * [14] | R | 0x0 | IntPnd64-33 + * [15] | R | 0x0 | IntPnd64-33 + * [16] | R | 0x0 | IntPnd64-33 + * [17] | R | 0x0 | IntPnd64-33 + * [18] | R | 0x0 | IntPnd64-33 + * [19] | R | 0x0 | IntPnd64-33 + * [20] | R | 0x0 | IntPnd64-33 + * [21] | R | 0x0 | IntPnd64-33 + * [22] | R | 0x0 | IntPnd64-33 + * [23] | R | 0x0 | IntPnd64-33 + * [24] | R | 0x0 | IntPnd64-33 + * [25] | R | 0x0 | IntPnd64-33 + * [26] | R | 0x0 | IntPnd64-33 + * [27] | R | 0x0 | IntPnd64-33 + * [28] | R | 0x0 | IntPnd64-33 + * [29] | R | 0x0 | IntPnd64-33 + * [30] | R | 0x0 | IntPnd64-33 + * [31] | R | 0x0 | IntPnd64-33 + * + */ +/* + * Field : IntPnd64-33 - IntPnd_0 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_0_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_0_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_0 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_0_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_0 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_0_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IntPnd64-33 - IntPnd_1 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_1_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_1_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_1 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_1_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_1 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_1_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IntPnd64-33 - IntPnd_2 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_2_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_2_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_2 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_2_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_2 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_2_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IntPnd64-33 - IntPnd_3 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_3_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_3_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_3 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_3_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_3 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_3_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IntPnd64-33 - IntPnd_4 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_4_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_4_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_4 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_4_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_4 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_4_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_4 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_4 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IntPnd64-33 - IntPnd_5 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_5_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_5_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_5 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_5_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_5 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_5_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_5 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_5 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IntPnd64-33 - IntPnd_6 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_6_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_6_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_6 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_6_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_6 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_6_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_6 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_6 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IntPnd64-33 - IntPnd_7 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_7_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_7_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_7 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_7_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_7 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_7_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_7 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_7 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : IntPnd64-33 - IntPnd_8 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_8_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_8_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_8 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_8_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_8 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_8_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_8 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_8 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : IntPnd64-33 - IntPnd_9 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_9_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_9_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_9 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_9_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_9 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_9_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_9 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_9 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : IntPnd64-33 - IntPnd_10 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_10_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_10_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_10 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_10_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_10 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_10_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_10 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_10 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : IntPnd64-33 - IntPnd_11 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_11_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_11_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_11 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_11_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_11 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_11_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_11 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_11 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : IntPnd64-33 - IntPnd_12 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_12_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_12_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_12 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_12_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_12 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_12_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_12 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_12 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : IntPnd64-33 - IntPnd_13 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_13_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_13_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_13 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_13_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_13 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_13_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_13 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_13 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : IntPnd64-33 - IntPnd_14 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_14_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_14_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_14 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_14_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_14 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_14_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_14 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_14 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : IntPnd64-33 - IntPnd_15 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_15_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_15_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_15 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_15_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_15 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_15_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_15 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_15 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : IntPnd64-33 - IntPnd_16 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_16_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_16_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_16 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_16_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_16 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_16_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_16 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_16 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : IntPnd64-33 - IntPnd_17 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_17_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_17_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_17 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_17_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_17 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_17_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_17 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_17 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : IntPnd64-33 - IntPnd_18 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_18_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_18_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_18 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_18_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_18 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_18_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_18 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_18 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : IntPnd64-33 - IntPnd_19 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_19_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_19_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_19 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_19_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_19 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_19_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_19 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_19 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : IntPnd64-33 - IntPnd_20 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_20_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_20_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_20 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_20_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_20 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_20_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_20 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_20 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : IntPnd64-33 - IntPnd_21 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_21_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_21_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_21 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_21_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_21 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_21_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_21 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_21 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : IntPnd64-33 - IntPnd_22 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_22_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_22_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_22 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_22_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_22 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_22_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_22 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_22 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : IntPnd64-33 - IntPnd_23 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_23_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_23_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_23 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_23_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_23 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_23_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_23 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_23 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : IntPnd64-33 - IntPnd_24 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_24_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_24_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_24 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_24_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_24 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_24_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_24 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_24 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : IntPnd64-33 - IntPnd_25 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_25_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_25_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_25 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_25_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_25 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_25_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_25 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_25 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : IntPnd64-33 - IntPnd_26 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_26_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_26_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_26 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_26_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_26 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_26_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_26 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_26 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : IntPnd64-33 - IntPnd_27 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_27_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_27_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_27 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_27_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_27 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_27_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_27 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_27 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : IntPnd64-33 - IntPnd_28 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_28_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_28_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_28 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_28_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_28 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_28_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_28 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_28 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : IntPnd64-33 - IntPnd_29 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_29_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_29_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_29 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_29_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_29 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_29_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_29 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_29 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : IntPnd64-33 - IntPnd_30 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_30_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_30_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_30 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_30_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_30 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_30_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_30 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_30 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : IntPnd64-33 - IntPnd_31 + * + * Interrupt pending bits for Message Objects 33 to 64. Array index i corresponds + * to Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPB_INTPND_31_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPB_INTPND_31_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_31 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_31_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPB_INTPND_31 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_31_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPB_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPB_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPB_INTPND_31 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPB_INTPND_31 register field value. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPB_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPB_INTPND_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOIPB_INTPND_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPB_INTPND_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOIPB. + */ +struct ALT_CAN_MSGHAND_MOIPB_s +{ + const uint32_t IntPnd_0 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_1 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_2 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_3 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_4 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_5 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_6 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_7 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_8 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_9 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_10 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_11 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_12 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_13 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_14 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_15 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_16 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_17 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_18 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_19 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_20 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_21 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_22 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_23 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_24 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_25 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_26 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_27 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_28 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_29 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_30 : 1; /* IntPnd64-33 */ + const uint32_t IntPnd_31 : 1; /* IntPnd64-33 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOIPB. */ +typedef volatile struct ALT_CAN_MSGHAND_MOIPB_s ALT_CAN_MSGHAND_MOIPB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOIPB register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOIPB_OFST 0x30 +/* The address of the ALT_CAN_MSGHAND_MOIPB register. */ +#define ALT_CAN_MSGHAND_MOIPB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOIPB_OFST)) + +/* + * Register : Interrupt Pending C Register - MOIPC + * + * Interrupt pending bits for Message Objects 65 to 96. By reading the IntPnd + * bits, the CPU can check for which Message Object an interrupt is pending. The + * IntPnd bit of a specific Message Object can be set/reset by the CPU via the IFx + * Message Interface Registers or set by the Message Handler after reception or + * after a successful transmission of a frame. This will also affect the valid of + * IntID in the Interrupt Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | IntPnd96-65 + * [1] | R | 0x0 | IntPnd96-65 + * [2] | R | 0x0 | IntPnd96-65 + * [3] | R | 0x0 | IntPnd96-65 + * [4] | R | 0x0 | IntPnd96-65 + * [5] | R | 0x0 | IntPnd96-65 + * [6] | R | 0x0 | IntPnd96-65 + * [7] | R | 0x0 | IntPnd96-65 + * [8] | R | 0x0 | IntPnd96-65 + * [9] | R | 0x0 | IntPnd96-65 + * [10] | R | 0x0 | IntPnd96-65 + * [11] | R | 0x0 | IntPnd96-65 + * [12] | R | 0x0 | IntPnd96-65 + * [13] | R | 0x0 | IntPnd96-65 + * [14] | R | 0x0 | IntPnd96-65 + * [15] | R | 0x0 | IntPnd96-65 + * [16] | R | 0x0 | IntPnd96-65 + * [17] | R | 0x0 | IntPnd96-65 + * [18] | R | 0x0 | IntPnd96-65 + * [19] | R | 0x0 | IntPnd96-65 + * [20] | R | 0x0 | IntPnd96-65 + * [21] | R | 0x0 | IntPnd96-65 + * [22] | R | 0x0 | IntPnd96-65 + * [23] | R | 0x0 | IntPnd96-65 + * [24] | R | 0x0 | IntPnd96-65 + * [25] | R | 0x0 | IntPnd96-65 + * [26] | R | 0x0 | IntPnd96-65 + * [27] | R | 0x0 | IntPnd96-65 + * [28] | R | 0x0 | IntPnd96-65 + * [29] | R | 0x0 | IntPnd96-65 + * [30] | R | 0x0 | IntPnd96-65 + * [31] | R | 0x0 | IntPnd96-65 + * + */ +/* + * Field : IntPnd96-65 - IntPnd_0 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_0_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_0_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_0 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_0_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_0 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_0_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IntPnd96-65 - IntPnd_1 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_1_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_1_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_1 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_1_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_1 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_1_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IntPnd96-65 - IntPnd_2 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_2_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_2_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_2 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_2_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_2 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_2_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IntPnd96-65 - IntPnd_3 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_3_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_3_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_3 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_3_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_3 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_3_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IntPnd96-65 - IntPnd_4 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_4_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_4_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_4 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_4_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_4 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_4_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_4 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_4 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IntPnd96-65 - IntPnd_5 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_5_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_5_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_5 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_5_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_5 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_5_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_5 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_5 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IntPnd96-65 - IntPnd_6 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_6_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_6_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_6 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_6_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_6 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_6_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_6 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_6 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IntPnd96-65 - IntPnd_7 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_7_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_7_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_7 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_7_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_7 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_7_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_7 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_7 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : IntPnd96-65 - IntPnd_8 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_8_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_8_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_8 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_8_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_8 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_8_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_8 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_8 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : IntPnd96-65 - IntPnd_9 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_9_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_9_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_9 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_9_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_9 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_9_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_9 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_9 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : IntPnd96-65 - IntPnd_10 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_10_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_10_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_10 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_10_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_10 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_10_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_10 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_10 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : IntPnd96-65 - IntPnd_11 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_11_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_11_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_11 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_11_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_11 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_11_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_11 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_11 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : IntPnd96-65 - IntPnd_12 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_12_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_12_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_12 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_12_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_12 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_12_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_12 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_12 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : IntPnd96-65 - IntPnd_13 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_13_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_13_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_13 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_13_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_13 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_13_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_13 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_13 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : IntPnd96-65 - IntPnd_14 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_14_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_14_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_14 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_14_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_14 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_14_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_14 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_14 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : IntPnd96-65 - IntPnd_15 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_15_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_15_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_15 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_15_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_15 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_15_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_15 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_15 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : IntPnd96-65 - IntPnd_16 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_16_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_16_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_16 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_16_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_16 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_16_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_16 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_16 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : IntPnd96-65 - IntPnd_17 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_17_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_17_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_17 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_17_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_17 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_17_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_17 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_17 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : IntPnd96-65 - IntPnd_18 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_18_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_18_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_18 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_18_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_18 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_18_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_18 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_18 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : IntPnd96-65 - IntPnd_19 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_19_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_19_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_19 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_19_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_19 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_19_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_19 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_19 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : IntPnd96-65 - IntPnd_20 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_20_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_20_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_20 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_20_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_20 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_20_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_20 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_20 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : IntPnd96-65 - IntPnd_21 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_21_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_21_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_21 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_21_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_21 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_21_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_21 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_21 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : IntPnd96-65 - IntPnd_22 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_22_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_22_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_22 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_22_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_22 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_22_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_22 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_22 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : IntPnd96-65 - IntPnd_23 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_23_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_23_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_23 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_23_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_23 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_23_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_23 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_23 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : IntPnd96-65 - IntPnd_24 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_24_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_24_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_24 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_24_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_24 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_24_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_24 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_24 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : IntPnd96-65 - IntPnd_25 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_25_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_25_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_25 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_25_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_25 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_25_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_25 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_25 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : IntPnd96-65 - IntPnd_26 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_26_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_26_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_26 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_26_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_26 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_26_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_26 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_26 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : IntPnd96-65 - IntPnd_27 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_27_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_27_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_27 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_27_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_27 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_27_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_27 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_27 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : IntPnd96-65 - IntPnd_28 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_28_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_28_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_28 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_28_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_28 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_28_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_28 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_28 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : IntPnd96-65 - IntPnd_29 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_29_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_29_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_29 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_29_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_29 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_29_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_29 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_29 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : IntPnd96-65 - IntPnd_30 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_30_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_30_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_30 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_30_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_30 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_30_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_30 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_30 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : IntPnd96-65 - IntPnd_31 + * + * Interrupt pending bits for Message Objects 65 to 96. Array index i corresponds + * to Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPC_INTPND_31_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPC_INTPND_31_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_31 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_31_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPC_INTPND_31 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_31_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPC_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPC_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPC_INTPND_31 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPC_INTPND_31 register field value. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPC_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPC_INTPND_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOIPC_INTPND_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPC_INTPND_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOIPC. + */ +struct ALT_CAN_MSGHAND_MOIPC_s +{ + const uint32_t IntPnd_0 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_1 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_2 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_3 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_4 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_5 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_6 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_7 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_8 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_9 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_10 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_11 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_12 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_13 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_14 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_15 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_16 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_17 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_18 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_19 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_20 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_21 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_22 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_23 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_24 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_25 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_26 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_27 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_28 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_29 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_30 : 1; /* IntPnd96-65 */ + const uint32_t IntPnd_31 : 1; /* IntPnd96-65 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOIPC. */ +typedef volatile struct ALT_CAN_MSGHAND_MOIPC_s ALT_CAN_MSGHAND_MOIPC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOIPC register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOIPC_OFST 0x34 +/* The address of the ALT_CAN_MSGHAND_MOIPC register. */ +#define ALT_CAN_MSGHAND_MOIPC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOIPC_OFST)) + +/* + * Register : Interrupt Pending D Register - MOIPD + * + * Interrupt pending bits for Message Objects 97 to 128. By reading the IntPnd + * bits, the CPU can check for which Message Object an interrupt is pending. The + * IntPnd bit of a specific Message Object can be set/reset by the CPU via the IFx + * Message Interface Registers or set by the Message Handler after reception or + * after a successful transmission of a frame. This will also affect the valid of + * IntID in the Interrupt Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------- + * [0] | R | 0x0 | IntPnd128-97 + * [1] | R | 0x0 | IntPnd128-97 + * [2] | R | 0x0 | IntPnd128-97 + * [3] | R | 0x0 | IntPnd128-97 + * [4] | R | 0x0 | IntPnd128-97 + * [5] | R | 0x0 | IntPnd128-97 + * [6] | R | 0x0 | IntPnd128-97 + * [7] | R | 0x0 | IntPnd128-97 + * [8] | R | 0x0 | IntPnd128-97 + * [9] | R | 0x0 | IntPnd128-97 + * [10] | R | 0x0 | IntPnd128-97 + * [11] | R | 0x0 | IntPnd128-97 + * [12] | R | 0x0 | IntPnd128-97 + * [13] | R | 0x0 | IntPnd128-97 + * [14] | R | 0x0 | IntPnd128-97 + * [15] | R | 0x0 | IntPnd128-97 + * [16] | R | 0x0 | IntPnd128-97 + * [17] | R | 0x0 | IntPnd128-97 + * [18] | R | 0x0 | IntPnd128-97 + * [19] | R | 0x0 | IntPnd128-97 + * [20] | R | 0x0 | IntPnd128-97 + * [21] | R | 0x0 | IntPnd128-97 + * [22] | R | 0x0 | IntPnd128-97 + * [23] | R | 0x0 | IntPnd128-97 + * [24] | R | 0x0 | IntPnd128-97 + * [25] | R | 0x0 | IntPnd128-97 + * [26] | R | 0x0 | IntPnd128-97 + * [27] | R | 0x0 | IntPnd128-97 + * [28] | R | 0x0 | IntPnd128-97 + * [29] | R | 0x0 | IntPnd128-97 + * [30] | R | 0x0 | IntPnd128-97 + * [31] | R | 0x0 | IntPnd128-97 + * + */ +/* + * Field : IntPnd128-97 - IntPnd_0 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_0_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_0_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_0 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_0_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_0 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_0_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_0 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_0 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IntPnd128-97 - IntPnd_1 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_1_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_1_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_1 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_1_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_1 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_1_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_1 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_1 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IntPnd128-97 - IntPnd_2 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_2_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_2_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_2 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_2_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_2 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_2_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_2 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_2 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IntPnd128-97 - IntPnd_3 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_3_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_3_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_3 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_3_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_3 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_3_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_3 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_3 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IntPnd128-97 - IntPnd_4 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_4_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_4_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_4 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_4_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_4 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_4_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_4 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_4 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_4 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IntPnd128-97 - IntPnd_5 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_5_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_5_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_5 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_5_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_5 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_5_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_5 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_5 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_5 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IntPnd128-97 - IntPnd_6 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_6_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_6_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_6 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_6_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_6 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_6_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_6 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_6 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_6 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IntPnd128-97 - IntPnd_7 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_7_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_7_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_7 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_7_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_7 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_7_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_7 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_7 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_7 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : IntPnd128-97 - IntPnd_8 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_8_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_8_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_8 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_8_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_8 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_8_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_8 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_8 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_8 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : IntPnd128-97 - IntPnd_9 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_9_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_9_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_9 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_9_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_9 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_9_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_9 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_9 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_9 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : IntPnd128-97 - IntPnd_10 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_10_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_10_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_10 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_10_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_10 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_10_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_10 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_10 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_10 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : IntPnd128-97 - IntPnd_11 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_11_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_11_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_11 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_11_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_11 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_11_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_11 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_11 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_11 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : IntPnd128-97 - IntPnd_12 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_12_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_12_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_12 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_12_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_12 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_12_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_12 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_12 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_12 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : IntPnd128-97 - IntPnd_13 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_13_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_13_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_13 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_13_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_13 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_13_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_13 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_13 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_13 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : IntPnd128-97 - IntPnd_14 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_14_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_14_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_14 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_14_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_14 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_14_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_14 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_14 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_14 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : IntPnd128-97 - IntPnd_15 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_15_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_15_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_15 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_15_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_15 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_15_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_15 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_15 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_15 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : IntPnd128-97 - IntPnd_16 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_16_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_16_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_16 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_16_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_16 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_16_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_16 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_16 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_16 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : IntPnd128-97 - IntPnd_17 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_17_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_17_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_17 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_17_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_17 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_17_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_17 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_17 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_17 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : IntPnd128-97 - IntPnd_18 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_18_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_18_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_18 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_18_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_18 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_18_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_18 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_18 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_18 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : IntPnd128-97 - IntPnd_19 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_19_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_19_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_19 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_19_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_19 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_19_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_19 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_19 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_19 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : IntPnd128-97 - IntPnd_20 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_20_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_20_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_20 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_20_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_20 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_20_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_20 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_20 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_20 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : IntPnd128-97 - IntPnd_21 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_21_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_21_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_21 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_21_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_21 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_21_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_21 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_21 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_21 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : IntPnd128-97 - IntPnd_22 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_22_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_22_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_22 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_22_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_22 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_22_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_22 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_22 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_22 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : IntPnd128-97 - IntPnd_23 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_23_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_23_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_23 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_23_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_23 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_23_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_23 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_23 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_23 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : IntPnd128-97 - IntPnd_24 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_24_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_24_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_24 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_24_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_24 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_24_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_24 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_24 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_24 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : IntPnd128-97 - IntPnd_25 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_25_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_25_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_25 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_25_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_25 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_25_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_25 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_25 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_25 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : IntPnd128-97 - IntPnd_26 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_26_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_26_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_26 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_26_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_26 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_26_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_26 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_26 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_26 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : IntPnd128-97 - IntPnd_27 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_27_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_27_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_27 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_27_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_27 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_27_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_27 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_27 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_27 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : IntPnd128-97 - IntPnd_28 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_28_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_28_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_28 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_28_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_28 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_28_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_28 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_28 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_28 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : IntPnd128-97 - IntPnd_29 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_29_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_29_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_29 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_29_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_29 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_29_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_29 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_29 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_29 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : IntPnd128-97 - IntPnd_30 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_30_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_30_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_30 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_30_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_30 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_30_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_30 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_30 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_30 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : IntPnd128-97 - IntPnd_31 + * + * Interrupt pending bits for Message Objects 97 to 128. Array index i corresponds + * to Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGHAND_MOIPD_INTPND_31_E_NOTSRC | 0x0 | The Message Object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGHAND_MOIPD_INTPND_31_E_SRC | 0x1 | The Message Object is the source of an + * : | | interrupt. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_31 + * + * The Message Object is not the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_31_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOIPD_INTPND_31 + * + * The Message Object is the source of an interrupt. + */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_31_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOIPD_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOIPD_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOIPD_INTPND_31 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOIPD_INTPND_31 register field value. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOIPD_INTPND_31 register field. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOIPD_INTPND_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOIPD_INTPND_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOIPD_INTPND_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOIPD. + */ +struct ALT_CAN_MSGHAND_MOIPD_s +{ + const uint32_t IntPnd_0 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_1 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_2 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_3 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_4 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_5 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_6 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_7 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_8 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_9 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_10 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_11 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_12 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_13 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_14 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_15 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_16 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_17 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_18 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_19 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_20 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_21 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_22 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_23 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_24 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_25 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_26 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_27 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_28 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_29 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_30 : 1; /* IntPnd128-97 */ + const uint32_t IntPnd_31 : 1; /* IntPnd128-97 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOIPD. */ +typedef volatile struct ALT_CAN_MSGHAND_MOIPD_s ALT_CAN_MSGHAND_MOIPD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOIPD register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOIPD_OFST 0x38 +/* The address of the ALT_CAN_MSGHAND_MOIPD register. */ +#define ALT_CAN_MSGHAND_MOIPD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOIPD_OFST)) + +/* + * Register : Message Valid X Register - MOVALX + * + * Reading this register allows the CPU to quickly detect if any of the message + * valid bits in each of the MOVALA, MOVALB, MOVALC, and MOVALD Message Valid + * Registers are set. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [0] | R | 0x0 | MsgValA + * [1] | R | 0x0 | MsgValA + * [2] | R | 0x0 | MsgValA + * [3] | R | 0x0 | MsgValA + * [4] | R | 0x0 | MsgValB + * [5] | R | 0x0 | MsgValB + * [6] | R | 0x0 | MsgValB + * [7] | R | 0x0 | MsgValB + * [8] | R | 0x0 | MsgValC + * [9] | R | 0x0 | MsgValC + * [10] | R | 0x0 | MsgValC + * [11] | R | 0x0 | MsgValC + * [12] | R | 0x0 | MsgValD + * [13] | R | 0x0 | MsgValD + * [14] | R | 0x0 | MsgValD + * [15] | R | 0x0 | MsgValD + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MsgValA - MsgValA_0 + * + * Each bit in this field is a logical OR of a byte of the MOVALA register. Array + * index i corresponds to byte i of the MOVALA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALA are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALA are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALA_0 + * + * The Message Objects in the corresponding byte of MOVALA are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALA_0 + * + * One or more of the Message Objects in the corresponding byte of MOVALA are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALA_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALA_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALA_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALA_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MsgValA - MsgValA_1 + * + * Each bit in this field is a logical OR of a byte of the MOVALA register. Array + * index i corresponds to byte i of the MOVALA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALA are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALA are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALA_1 + * + * The Message Objects in the corresponding byte of MOVALA are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALA_1 + * + * One or more of the Message Objects in the corresponding byte of MOVALA are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALA_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALA_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALA_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALA_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MsgValA - MsgValA_2 + * + * Each bit in this field is a logical OR of a byte of the MOVALA register. Array + * index i corresponds to byte i of the MOVALA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALA are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALA are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALA_2 + * + * The Message Objects in the corresponding byte of MOVALA are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALA_2 + * + * One or more of the Message Objects in the corresponding byte of MOVALA are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALA_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALA_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALA_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALA_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MsgValA - MsgValA_3 + * + * Each bit in this field is a logical OR of a byte of the MOVALA register. Array + * index i corresponds to byte i of the MOVALA register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALA are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALA are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALA_3 + * + * The Message Objects in the corresponding byte of MOVALA are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALA_3 + * + * One or more of the Message Objects in the corresponding byte of MOVALA are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALA_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALA_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALA_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALA_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALA_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALA_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MsgValB - MsgValB_0 + * + * Each bit in this field is a logical OR of a byte of the MOVALB register. Array + * index i corresponds to byte i of the MOVALB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALB are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALB are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALB_0 + * + * The Message Objects in the corresponding byte of MOVALB are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALB_0 + * + * One or more of the Message Objects in the corresponding byte of MOVALB are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALB_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALB_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALB_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALB_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MsgValB - MsgValB_1 + * + * Each bit in this field is a logical OR of a byte of the MOVALB register. Array + * index i corresponds to byte i of the MOVALB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALB are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALB are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALB_1 + * + * The Message Objects in the corresponding byte of MOVALB are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALB_1 + * + * One or more of the Message Objects in the corresponding byte of MOVALB are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALB_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALB_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALB_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALB_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MsgValB - MsgValB_2 + * + * Each bit in this field is a logical OR of a byte of the MOVALB register. Array + * index i corresponds to byte i of the MOVALB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALB are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALB are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALB_2 + * + * The Message Objects in the corresponding byte of MOVALB are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALB_2 + * + * One or more of the Message Objects in the corresponding byte of MOVALB are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALB_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALB_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALB_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALB_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_2_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MsgValB - MsgValB_3 + * + * Each bit in this field is a logical OR of a byte of the MOVALB register. Array + * index i corresponds to byte i of the MOVALB register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALB are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALB are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALB_3 + * + * The Message Objects in the corresponding byte of MOVALB are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALB_3 + * + * One or more of the Message Objects in the corresponding byte of MOVALB are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALB_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALB_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALB_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALB_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALB_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALB_3_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MsgValC - MsgValC_0 + * + * Each bit in this field is a logical OR of a byte of the MOVALC register. Array + * index i corresponds to byte i of the MOVALC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALC are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALC are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALC_0 + * + * The Message Objects in the corresponding byte of MOVALC are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALC_0 + * + * One or more of the Message Objects in the corresponding byte of MOVALC are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALC_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALC_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALC_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALC_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MsgValC - MsgValC_1 + * + * Each bit in this field is a logical OR of a byte of the MOVALC register. Array + * index i corresponds to byte i of the MOVALC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALC are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALC are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALC_1 + * + * The Message Objects in the corresponding byte of MOVALC are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALC_1 + * + * One or more of the Message Objects in the corresponding byte of MOVALC are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALC_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALC_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALC_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALC_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MsgValC - MsgValC_2 + * + * Each bit in this field is a logical OR of a byte of the MOVALC register. Array + * index i corresponds to byte i of the MOVALC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALC are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALC are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALC_2 + * + * The Message Objects in the corresponding byte of MOVALC are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALC_2 + * + * One or more of the Message Objects in the corresponding byte of MOVALC are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALC_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALC_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALC_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALC_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_2_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MsgValC - MsgValC_3 + * + * Each bit in this field is a logical OR of a byte of the MOVALC register. Array + * index i corresponds to byte i of the MOVALC register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALC are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALC are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALC_3 + * + * The Message Objects in the corresponding byte of MOVALC are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALC_3 + * + * One or more of the Message Objects in the corresponding byte of MOVALC are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALC_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALC_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALC_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALC_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALC_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALC_3_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MsgValD - MsgValD_0 + * + * Each bit in this field is a logical OR of a byte of the MOVALD register. Array + * index i corresponds to byte i of the MOVALD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALD are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALD are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALD_0 + * + * The Message Objects in the corresponding byte of MOVALD are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALD_0 + * + * One or more of the Message Objects in the corresponding byte of MOVALD are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALD_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALD_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALD_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALD_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_0_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MsgValD - MsgValD_1 + * + * Each bit in this field is a logical OR of a byte of the MOVALD register. Array + * index i corresponds to byte i of the MOVALD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALD are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALD are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALD_1 + * + * The Message Objects in the corresponding byte of MOVALD are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALD_1 + * + * One or more of the Message Objects in the corresponding byte of MOVALD are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALD_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALD_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALD_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALD_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_1_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MsgValD - MsgValD_2 + * + * Each bit in this field is a logical OR of a byte of the MOVALD register. Array + * index i corresponds to byte i of the MOVALD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALD are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALD are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALD_2 + * + * The Message Objects in the corresponding byte of MOVALD are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALD_2 + * + * One or more of the Message Objects in the corresponding byte of MOVALD are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALD_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALD_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALD_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALD_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_2_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : MsgValD - MsgValD_3 + * + * Each bit in this field is a logical OR of a byte of the MOVALD register. Array + * index i corresponds to byte i of the MOVALD register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_E_IGNORED | 0x0 | The Message Objects in the corresponding byte of + * : | | MOVALD are ignored by the Message Handler. + * ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_E_CONSIDERED | 0x1 | One or more of the Message Objects in the + * : | | corresponding byte of MOVALD are configured and + * : | | should be considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALD_3 + * + * The Message Objects in the corresponding byte of MOVALD are ignored by the + * Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALX_MSGVALD_3 + * + * One or more of the Message Objects in the corresponding byte of MOVALD are + * configured and should be considered by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALX_MSGVALD_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALX_MSGVALD_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOVALX_MSGVALD_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALX_MSGVALD_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOVALX_MSGVALD_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALX_MSGVALD_3_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOVALX. + */ +struct ALT_CAN_MSGHAND_MOVALX_s +{ + const uint32_t MsgValA_0 : 1; /* MsgValA */ + const uint32_t MsgValA_1 : 1; /* MsgValA */ + const uint32_t MsgValA_2 : 1; /* MsgValA */ + const uint32_t MsgValA_3 : 1; /* MsgValA */ + const uint32_t MsgValB_0 : 1; /* MsgValB */ + const uint32_t MsgValB_1 : 1; /* MsgValB */ + const uint32_t MsgValB_2 : 1; /* MsgValB */ + const uint32_t MsgValB_3 : 1; /* MsgValB */ + const uint32_t MsgValC_0 : 1; /* MsgValC */ + const uint32_t MsgValC_1 : 1; /* MsgValC */ + const uint32_t MsgValC_2 : 1; /* MsgValC */ + const uint32_t MsgValC_3 : 1; /* MsgValC */ + const uint32_t MsgValD_0 : 1; /* MsgValD */ + const uint32_t MsgValD_1 : 1; /* MsgValD */ + const uint32_t MsgValD_2 : 1; /* MsgValD */ + const uint32_t MsgValD_3 : 1; /* MsgValD */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOVALX. */ +typedef volatile struct ALT_CAN_MSGHAND_MOVALX_s ALT_CAN_MSGHAND_MOVALX_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOVALX register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOVALX_OFST 0x3c +/* The address of the ALT_CAN_MSGHAND_MOVALX register. */ +#define ALT_CAN_MSGHAND_MOVALX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOVALX_OFST)) + +/* + * Register : Message Valid A Register - MOVALA + * + * Message valid bits for Message Objects 1 to 32. By reading the MsgVal bits, the + * CPU can check for which Message Object is valid. The MsgVal bit of a specific + * Message Object can be set/reset by the CPU via the IFx Message Interface + * Registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | MsgVal32-1 + * [1] | R | 0x0 | MsgVal32-1 + * [2] | R | 0x0 | MsgVal32-1 + * [3] | R | 0x0 | MsgVal32-1 + * [4] | R | 0x0 | MsgVal32-1 + * [5] | R | 0x0 | MsgVal32-1 + * [6] | R | 0x0 | MsgVal32-1 + * [7] | R | 0x0 | MsgVal32-1 + * [8] | R | 0x0 | MsgVal32-1 + * [9] | R | 0x0 | MsgVal32-1 + * [10] | R | 0x0 | MsgVal32-1 + * [11] | R | 0x0 | MsgVal32-1 + * [12] | R | 0x0 | MsgVal32-1 + * [13] | R | 0x0 | MsgVal32-1 + * [14] | R | 0x0 | MsgVal32-1 + * [15] | R | 0x0 | MsgVal32-1 + * [16] | R | 0x0 | MsgVal32-1 + * [17] | R | 0x0 | MsgVal32-1 + * [18] | R | 0x0 | MsgVal32-1 + * [19] | R | 0x0 | MsgVal32-1 + * [20] | R | 0x0 | MsgVal32-1 + * [21] | R | 0x0 | MsgVal32-1 + * [22] | R | 0x0 | MsgVal32-1 + * [23] | R | 0x0 | MsgVal32-1 + * [24] | R | 0x0 | MsgVal32-1 + * [25] | R | 0x0 | MsgVal32-1 + * [26] | R | 0x0 | MsgVal32-1 + * [27] | R | 0x0 | MsgVal32-1 + * [28] | R | 0x0 | MsgVal32-1 + * [29] | R | 0x0 | MsgVal32-1 + * [30] | R | 0x0 | MsgVal32-1 + * [31] | R | 0x0 | MsgVal32-1 + * + */ +/* + * Field : MsgVal32-1 - MsgVal_0 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_0 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_0 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MsgVal32-1 - MsgVal_1 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_1 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_1 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MsgVal32-1 - MsgVal_2 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_2 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_2 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MsgVal32-1 - MsgVal_3 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_3 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_3 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MsgVal32-1 - MsgVal_4 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_4 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_4 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_4 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_4 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MsgVal32-1 - MsgVal_5 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_5 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_5 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_5 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_5 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MsgVal32-1 - MsgVal_6 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_6 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_6 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_6 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_6 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MsgVal32-1 - MsgVal_7 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_7 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_7 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_7 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_7 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MsgVal32-1 - MsgVal_8 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_8 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_8 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_8 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_8 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MsgVal32-1 - MsgVal_9 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_9 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_9 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_9 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_9 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MsgVal32-1 - MsgVal_10 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_10 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_10 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_10 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_10 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MsgVal32-1 - MsgVal_11 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_11 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_11 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_11 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_11 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MsgVal32-1 - MsgVal_12 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_12 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_12 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_12 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_12 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MsgVal32-1 - MsgVal_13 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_13 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_13 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_13 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_13 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MsgVal32-1 - MsgVal_14 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_14 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_14 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_14 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_14 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : MsgVal32-1 - MsgVal_15 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_15 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_15 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_15 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_15 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : MsgVal32-1 - MsgVal_16 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_16 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_16 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_16 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_16 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MsgVal32-1 - MsgVal_17 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_17 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_17 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_17 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_17 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : MsgVal32-1 - MsgVal_18 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_18 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_18 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_18 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_18 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : MsgVal32-1 - MsgVal_19 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_19 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_19 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_19 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_19 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MsgVal32-1 - MsgVal_20 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_20 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_20 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_20 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_20 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : MsgVal32-1 - MsgVal_21 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_21 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_21 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_21 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_21 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : MsgVal32-1 - MsgVal_22 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_22 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_22 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_22 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_22 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MsgVal32-1 - MsgVal_23 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_23 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_23 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_23 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_23 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : MsgVal32-1 - MsgVal_24 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_24 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_24 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_24 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_24 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MsgVal32-1 - MsgVal_25 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_25 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_25 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_25 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_25 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : MsgVal32-1 - MsgVal_26 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_26 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_26 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_26 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_26 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : MsgVal32-1 - MsgVal_27 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_27 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_27 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_27 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_27 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : MsgVal32-1 - MsgVal_28 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_28 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_28 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_28 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_28 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : MsgVal32-1 - MsgVal_29 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_29 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_29 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_29 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_29 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : MsgVal32-1 - MsgVal_30 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_30 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_30 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_30 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_30 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : MsgVal32-1 - MsgVal_31 + * + * Message valid bits for Message Objects 1 to 32. Array index i corresponds to + * Message Object i+1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_31 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALA_MSGVAL_31 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALA_MSGVAL_31 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALA_MSGVAL_31 register field value. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALA_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALA_MSGVAL_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOVALA_MSGVAL_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALA_MSGVAL_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOVALA. + */ +struct ALT_CAN_MSGHAND_MOVALA_s +{ + const uint32_t MsgVal_0 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_1 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_2 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_3 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_4 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_5 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_6 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_7 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_8 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_9 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_10 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_11 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_12 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_13 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_14 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_15 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_16 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_17 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_18 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_19 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_20 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_21 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_22 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_23 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_24 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_25 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_26 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_27 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_28 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_29 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_30 : 1; /* MsgVal32-1 */ + const uint32_t MsgVal_31 : 1; /* MsgVal32-1 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOVALA. */ +typedef volatile struct ALT_CAN_MSGHAND_MOVALA_s ALT_CAN_MSGHAND_MOVALA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOVALA register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOVALA_OFST 0x40 +/* The address of the ALT_CAN_MSGHAND_MOVALA register. */ +#define ALT_CAN_MSGHAND_MOVALA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOVALA_OFST)) + +/* + * Register : Message Valid B Register - MOVALB + * + * Message valid bits for Message Objects 33 to 64. By reading the MsgVal bits, + * the CPU can check for which Message Object is valid. The MsgVal bit of a + * specific Message Object can be set/reset by the CPU via the IFx Message + * Interface Registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | MsgVal64-33 + * [1] | R | 0x0 | MsgVal64-33 + * [2] | R | 0x0 | MsgVal64-33 + * [3] | R | 0x0 | MsgVal64-33 + * [4] | R | 0x0 | MsgVal64-33 + * [5] | R | 0x0 | MsgVal64-33 + * [6] | R | 0x0 | MsgVal64-33 + * [7] | R | 0x0 | MsgVal64-33 + * [8] | R | 0x0 | MsgVal64-33 + * [9] | R | 0x0 | MsgVal64-33 + * [10] | R | 0x0 | MsgVal64-33 + * [11] | R | 0x0 | MsgVal64-33 + * [12] | R | 0x0 | MsgVal64-33 + * [13] | R | 0x0 | MsgVal64-33 + * [14] | R | 0x0 | MsgVal64-33 + * [15] | R | 0x0 | MsgVal64-33 + * [16] | R | 0x0 | MsgVal64-33 + * [17] | R | 0x0 | MsgVal64-33 + * [18] | R | 0x0 | MsgVal64-33 + * [19] | R | 0x0 | MsgVal64-33 + * [20] | R | 0x0 | MsgVal64-33 + * [21] | R | 0x0 | MsgVal64-33 + * [22] | R | 0x0 | MsgVal64-33 + * [23] | R | 0x0 | MsgVal64-33 + * [24] | R | 0x0 | MsgVal64-33 + * [25] | R | 0x0 | MsgVal64-33 + * [26] | R | 0x0 | MsgVal64-33 + * [27] | R | 0x0 | MsgVal64-33 + * [28] | R | 0x0 | MsgVal64-33 + * [29] | R | 0x0 | MsgVal64-33 + * [30] | R | 0x0 | MsgVal64-33 + * [31] | R | 0x0 | MsgVal64-33 + * + */ +/* + * Field : MsgVal64-33 - MsgVal_0 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_0 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_0 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MsgVal64-33 - MsgVal_1 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_1 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_1 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MsgVal64-33 - MsgVal_2 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_2 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_2 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MsgVal64-33 - MsgVal_3 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_3 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_3 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MsgVal64-33 - MsgVal_4 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_4 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_4 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_4 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_4 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MsgVal64-33 - MsgVal_5 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_5 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_5 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_5 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_5 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MsgVal64-33 - MsgVal_6 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_6 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_6 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_6 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_6 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MsgVal64-33 - MsgVal_7 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_7 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_7 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_7 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_7 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MsgVal64-33 - MsgVal_8 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_8 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_8 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_8 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_8 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MsgVal64-33 - MsgVal_9 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_9 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_9 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_9 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_9 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MsgVal64-33 - MsgVal_10 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_10 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_10 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_10 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_10 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MsgVal64-33 - MsgVal_11 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_11 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_11 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_11 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_11 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MsgVal64-33 - MsgVal_12 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_12 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_12 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_12 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_12 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MsgVal64-33 - MsgVal_13 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_13 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_13 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_13 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_13 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MsgVal64-33 - MsgVal_14 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_14 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_14 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_14 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_14 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : MsgVal64-33 - MsgVal_15 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_15 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_15 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_15 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_15 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : MsgVal64-33 - MsgVal_16 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_16 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_16 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_16 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_16 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MsgVal64-33 - MsgVal_17 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_17 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_17 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_17 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_17 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : MsgVal64-33 - MsgVal_18 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_18 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_18 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_18 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_18 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : MsgVal64-33 - MsgVal_19 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_19 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_19 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_19 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_19 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MsgVal64-33 - MsgVal_20 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_20 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_20 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_20 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_20 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : MsgVal64-33 - MsgVal_21 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_21 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_21 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_21 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_21 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : MsgVal64-33 - MsgVal_22 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_22 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_22 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_22 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_22 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MsgVal64-33 - MsgVal_23 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_23 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_23 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_23 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_23 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : MsgVal64-33 - MsgVal_24 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_24 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_24 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_24 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_24 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MsgVal64-33 - MsgVal_25 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_25 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_25 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_25 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_25 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : MsgVal64-33 - MsgVal_26 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_26 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_26 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_26 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_26 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : MsgVal64-33 - MsgVal_27 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_27 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_27 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_27 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_27 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : MsgVal64-33 - MsgVal_28 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_28 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_28 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_28 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_28 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : MsgVal64-33 - MsgVal_29 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_29 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_29 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_29 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_29 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : MsgVal64-33 - MsgVal_30 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_30 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_30 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_30 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_30 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : MsgVal64-33 - MsgVal_31 + * + * Message valid bits for Message Objects 33 to 64. Array index i corresponds to + * Message Object i+33. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_31 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALB_MSGVAL_31 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALB_MSGVAL_31 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALB_MSGVAL_31 register field value. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALB_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALB_MSGVAL_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOVALB_MSGVAL_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALB_MSGVAL_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOVALB. + */ +struct ALT_CAN_MSGHAND_MOVALB_s +{ + const uint32_t MsgVal_0 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_1 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_2 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_3 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_4 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_5 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_6 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_7 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_8 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_9 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_10 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_11 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_12 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_13 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_14 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_15 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_16 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_17 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_18 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_19 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_20 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_21 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_22 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_23 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_24 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_25 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_26 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_27 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_28 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_29 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_30 : 1; /* MsgVal64-33 */ + const uint32_t MsgVal_31 : 1; /* MsgVal64-33 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOVALB. */ +typedef volatile struct ALT_CAN_MSGHAND_MOVALB_s ALT_CAN_MSGHAND_MOVALB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOVALB register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOVALB_OFST 0x44 +/* The address of the ALT_CAN_MSGHAND_MOVALB register. */ +#define ALT_CAN_MSGHAND_MOVALB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOVALB_OFST)) + +/* + * Register : Message Valid C Register - MOVALC + * + * Message valid bits for Message Objects 65 to 96. By reading the MsgVal bits, + * the CPU can check for which Message Object is valid. The MsgVal bit of a + * specific Message Object can be set/reset by the CPU via the IFx Message + * Interface Registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------ + * [0] | R | 0x0 | MsgVal96-65 + * [1] | R | 0x0 | MsgVal96-65 + * [2] | R | 0x0 | MsgVal96-65 + * [3] | R | 0x0 | MsgVal96-65 + * [4] | R | 0x0 | MsgVal96-65 + * [5] | R | 0x0 | MsgVal96-65 + * [6] | R | 0x0 | MsgVal96-65 + * [7] | R | 0x0 | MsgVal96-65 + * [8] | R | 0x0 | MsgVal96-65 + * [9] | R | 0x0 | MsgVal96-65 + * [10] | R | 0x0 | MsgVal96-65 + * [11] | R | 0x0 | MsgVal96-65 + * [12] | R | 0x0 | MsgVal96-65 + * [13] | R | 0x0 | MsgVal96-65 + * [14] | R | 0x0 | MsgVal96-65 + * [15] | R | 0x0 | MsgVal96-65 + * [16] | R | 0x0 | MsgVal96-65 + * [17] | R | 0x0 | MsgVal96-65 + * [18] | R | 0x0 | MsgVal96-65 + * [19] | R | 0x0 | MsgVal96-65 + * [20] | R | 0x0 | MsgVal96-65 + * [21] | R | 0x0 | MsgVal96-65 + * [22] | R | 0x0 | MsgVal96-65 + * [23] | R | 0x0 | MsgVal96-65 + * [24] | R | 0x0 | MsgVal96-65 + * [25] | R | 0x0 | MsgVal96-65 + * [26] | R | 0x0 | MsgVal96-65 + * [27] | R | 0x0 | MsgVal96-65 + * [28] | R | 0x0 | MsgVal96-65 + * [29] | R | 0x0 | MsgVal96-65 + * [30] | R | 0x0 | MsgVal96-65 + * [31] | R | 0x0 | MsgVal96-65 + * + */ +/* + * Field : MsgVal96-65 - MsgVal_0 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_0 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_0 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MsgVal96-65 - MsgVal_1 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_1 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_1 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MsgVal96-65 - MsgVal_2 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_2 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_2 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MsgVal96-65 - MsgVal_3 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_3 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_3 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MsgVal96-65 - MsgVal_4 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_4 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_4 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_4 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_4 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MsgVal96-65 - MsgVal_5 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_5 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_5 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_5 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_5 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MsgVal96-65 - MsgVal_6 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_6 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_6 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_6 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_6 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MsgVal96-65 - MsgVal_7 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_7 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_7 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_7 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_7 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MsgVal96-65 - MsgVal_8 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_8 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_8 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_8 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_8 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MsgVal96-65 - MsgVal_9 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_9 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_9 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_9 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_9 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MsgVal96-65 - MsgVal_10 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_10 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_10 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_10 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_10 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MsgVal96-65 - MsgVal_11 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_11 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_11 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_11 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_11 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MsgVal96-65 - MsgVal_12 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_12 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_12 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_12 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_12 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MsgVal96-65 - MsgVal_13 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_13 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_13 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_13 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_13 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MsgVal96-65 - MsgVal_14 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_14 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_14 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_14 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_14 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : MsgVal96-65 - MsgVal_15 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_15 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_15 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_15 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_15 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : MsgVal96-65 - MsgVal_16 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_16 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_16 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_16 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_16 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MsgVal96-65 - MsgVal_17 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_17 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_17 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_17 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_17 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : MsgVal96-65 - MsgVal_18 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_18 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_18 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_18 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_18 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : MsgVal96-65 - MsgVal_19 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_19 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_19 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_19 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_19 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MsgVal96-65 - MsgVal_20 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_20 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_20 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_20 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_20 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : MsgVal96-65 - MsgVal_21 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_21 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_21 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_21 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_21 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : MsgVal96-65 - MsgVal_22 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_22 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_22 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_22 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_22 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MsgVal96-65 - MsgVal_23 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_23 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_23 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_23 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_23 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : MsgVal96-65 - MsgVal_24 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_24 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_24 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_24 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_24 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MsgVal96-65 - MsgVal_25 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_25 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_25 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_25 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_25 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : MsgVal96-65 - MsgVal_26 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_26 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_26 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_26 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_26 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : MsgVal96-65 - MsgVal_27 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_27 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_27 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_27 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_27 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : MsgVal96-65 - MsgVal_28 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_28 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_28 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_28 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_28 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : MsgVal96-65 - MsgVal_29 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_29 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_29 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_29 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_29 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : MsgVal96-65 - MsgVal_30 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_30 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_30 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_30 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_30 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : MsgVal96-65 - MsgVal_31 + * + * Message valid bits for Message Objects 65 to 96. Array index i corresponds to + * Message Object i+65. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_31 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALC_MSGVAL_31 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALC_MSGVAL_31 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALC_MSGVAL_31 register field value. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALC_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALC_MSGVAL_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOVALC_MSGVAL_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALC_MSGVAL_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOVALC. + */ +struct ALT_CAN_MSGHAND_MOVALC_s +{ + const uint32_t MsgVal_0 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_1 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_2 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_3 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_4 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_5 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_6 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_7 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_8 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_9 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_10 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_11 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_12 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_13 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_14 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_15 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_16 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_17 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_18 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_19 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_20 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_21 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_22 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_23 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_24 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_25 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_26 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_27 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_28 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_29 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_30 : 1; /* MsgVal96-65 */ + const uint32_t MsgVal_31 : 1; /* MsgVal96-65 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOVALC. */ +typedef volatile struct ALT_CAN_MSGHAND_MOVALC_s ALT_CAN_MSGHAND_MOVALC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOVALC register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOVALC_OFST 0x48 +/* The address of the ALT_CAN_MSGHAND_MOVALC register. */ +#define ALT_CAN_MSGHAND_MOVALC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOVALC_OFST)) + +/* + * Register : Message Valid D Register - MOVALD + * + * Message valid bits for Message Objects 97 to 128. By reading the MsgVal bits, + * the CPU can check for which Message Object is valid. The MsgVal bit of a + * specific Message Object can be set/reset by the CPU via the IFx Message + * Interface Registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------- + * [0] | R | 0x0 | MsgVal128-97 + * [1] | R | 0x0 | MsgVal128-97 + * [2] | R | 0x0 | MsgVal128-97 + * [3] | R | 0x0 | MsgVal128-97 + * [4] | R | 0x0 | MsgVal128-97 + * [5] | R | 0x0 | MsgVal128-97 + * [6] | R | 0x0 | MsgVal128-97 + * [7] | R | 0x0 | MsgVal128-97 + * [8] | R | 0x0 | MsgVal128-97 + * [9] | R | 0x0 | MsgVal128-97 + * [10] | R | 0x0 | MsgVal128-97 + * [11] | R | 0x0 | MsgVal128-97 + * [12] | R | 0x0 | MsgVal128-97 + * [13] | R | 0x0 | MsgVal128-97 + * [14] | R | 0x0 | MsgVal128-97 + * [15] | R | 0x0 | MsgVal128-97 + * [16] | R | 0x0 | MsgVal128-97 + * [17] | R | 0x0 | MsgVal128-97 + * [18] | R | 0x0 | MsgVal128-97 + * [19] | R | 0x0 | MsgVal128-97 + * [20] | R | 0x0 | MsgVal128-97 + * [21] | R | 0x0 | MsgVal128-97 + * [22] | R | 0x0 | MsgVal128-97 + * [23] | R | 0x0 | MsgVal128-97 + * [24] | R | 0x0 | MsgVal128-97 + * [25] | R | 0x0 | MsgVal128-97 + * [26] | R | 0x0 | MsgVal128-97 + * [27] | R | 0x0 | MsgVal128-97 + * [28] | R | 0x0 | MsgVal128-97 + * [29] | R | 0x0 | MsgVal128-97 + * [30] | R | 0x0 | MsgVal128-97 + * [31] | R | 0x0 | MsgVal128-97 + * + */ +/* + * Field : MsgVal128-97 - MsgVal_0 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_0 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_0 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_MSB 0 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_0 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_0 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_0 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MsgVal128-97 - MsgVal_1 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_1 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_1 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_MSB 1 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_1 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_1 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_1 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MsgVal128-97 - MsgVal_2 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_2 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_2 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_MSB 2 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_2 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_2 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_2 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MsgVal128-97 - MsgVal_3 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_3 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_3 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_MSB 3 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_3 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_3 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_3 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MsgVal128-97 - MsgVal_4 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_4 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_4 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_MSB 4 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_4 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_4 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_CLR_MSK 0xffffffef +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_4 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_4 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MsgVal128-97 - MsgVal_5 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_5 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_5 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_MSB 5 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_5 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_5 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_5 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_5 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MsgVal128-97 - MsgVal_6 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_6 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_6 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_MSB 6 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_6 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_6 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_6 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_6 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MsgVal128-97 - MsgVal_7 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_7 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_7 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_MSB 7 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_7 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_7 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_7 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_7 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MsgVal128-97 - MsgVal_8 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_8 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_8 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_MSB 8 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_8 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_8 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_8 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_8 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_8 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MsgVal128-97 - MsgVal_9 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_9 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_9 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_MSB 9 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_9 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_9 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_9 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_9 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_9 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MsgVal128-97 - MsgVal_10 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_10 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_10 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_MSB 10 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_10 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_10 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_10 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_10 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_10 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MsgVal128-97 - MsgVal_11 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_11 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_11 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_MSB 11 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_11 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_11 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_11 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_11 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_11 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MsgVal128-97 - MsgVal_12 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_12 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_12 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_MSB 12 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_12 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_12 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_12 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_12 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_12 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MsgVal128-97 - MsgVal_13 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_13 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_13 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_MSB 13 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_13 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_13 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_13 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_13 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_13 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MsgVal128-97 - MsgVal_14 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_14 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_14 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_MSB 14 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_14 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_14 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_14 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_14 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_14 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : MsgVal128-97 - MsgVal_15 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_15 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_15 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_MSB 15 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_15 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_15 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_15 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_15 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_15 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : MsgVal128-97 - MsgVal_16 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_16 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_16 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_MSB 16 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_16 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_16 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_16 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_16 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_16 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_16_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MsgVal128-97 - MsgVal_17 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_17 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_17 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_MSB 17 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_17 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_17 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_17 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_17 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_17 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_17_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : MsgVal128-97 - MsgVal_18 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_18 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_18 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_MSB 18 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_18 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_18 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_18 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_18 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_18 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_18_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : MsgVal128-97 - MsgVal_19 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_19 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_19 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_MSB 19 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_19 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_19 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_19 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_19 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_19 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_19_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MsgVal128-97 - MsgVal_20 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_20 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_20 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_MSB 20 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_20 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_20 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_20 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_20 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_20 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_20_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : MsgVal128-97 - MsgVal_21 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_21 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_21 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_MSB 21 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_21 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_21 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_21 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_21 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_21 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_21_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : MsgVal128-97 - MsgVal_22 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_22 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_22 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_MSB 22 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_22 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_22 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_22 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_22 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_22 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_22_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MsgVal128-97 - MsgVal_23 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_23 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_23 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_MSB 23 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_23 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_23 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_23 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_23 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_23 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_23_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : MsgVal128-97 - MsgVal_24 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_24 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_24 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_MSB 24 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_24 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_24 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_24 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_24 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_24 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_24_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MsgVal128-97 - MsgVal_25 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_25 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_25 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_MSB 25 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_25 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_SET_MSK 0x02000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_25 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_CLR_MSK 0xfdffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_25 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_25 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_25 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_25_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : MsgVal128-97 - MsgVal_26 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_26 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_26 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_MSB 26 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_26 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_SET_MSK 0x04000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_26 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_CLR_MSK 0xfbffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_26 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_26 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_26 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_26_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : MsgVal128-97 - MsgVal_27 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_27 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_27 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_MSB 27 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_27 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_SET_MSK 0x08000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_27 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_27 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_27 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_27 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_27_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : MsgVal128-97 - MsgVal_28 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_28 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_28 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_MSB 28 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_28 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_SET_MSK 0x10000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_28 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_CLR_MSK 0xefffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_28 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_28 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_28 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_28_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : MsgVal128-97 - MsgVal_29 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_29 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_29 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_MSB 29 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_29 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_29 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_29 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_29 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_29 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_29_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : MsgVal128-97 - MsgVal_30 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_30 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_30 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_MSB 30 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_30 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_30 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_30 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_30 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_30 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_30_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : MsgVal128-97 - MsgVal_31 + * + * Message valid bits for Message Objects 97 to 128. Array index i corresponds to + * Message Object i+97. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_31 + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGHAND_MOVALD_MSGVAL_31 + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_MSB 31 +/* The width in bits of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGHAND_MOVALD_MSGVAL_31 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGHAND_MOVALD_MSGVAL_31 register field value. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGHAND_MOVALD_MSGVAL_31 register field. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_RESET 0x0 +/* Extracts the ALT_CAN_MSGHAND_MOVALD_MSGVAL_31 field value from a register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGHAND_MOVALD_MSGVAL_31 register field value suitable for setting the register. */ +#define ALT_CAN_MSGHAND_MOVALD_MSGVAL_31_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGHAND_MOVALD. + */ +struct ALT_CAN_MSGHAND_MOVALD_s +{ + const uint32_t MsgVal_0 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_1 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_2 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_3 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_4 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_5 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_6 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_7 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_8 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_9 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_10 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_11 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_12 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_13 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_14 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_15 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_16 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_17 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_18 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_19 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_20 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_21 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_22 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_23 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_24 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_25 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_26 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_27 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_28 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_29 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_30 : 1; /* MsgVal128-97 */ + const uint32_t MsgVal_31 : 1; /* MsgVal128-97 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGHAND_MOVALD. */ +typedef volatile struct ALT_CAN_MSGHAND_MOVALD_s ALT_CAN_MSGHAND_MOVALD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGHAND_MOVALD register from the beginning of the component. */ +#define ALT_CAN_MSGHAND_MOVALD_OFST 0x4c +/* The address of the ALT_CAN_MSGHAND_MOVALD register. */ +#define ALT_CAN_MSGHAND_MOVALD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGHAND_MOVALD_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CAN_MSGHAND. + */ +struct ALT_CAN_MSGHAND_s +{ + volatile ALT_CAN_MSGHAND_MOTRX_t MOTRX; /* ALT_CAN_MSGHAND_MOTRX */ + volatile ALT_CAN_MSGHAND_MOTRA_t MOTRA; /* ALT_CAN_MSGHAND_MOTRA */ + volatile ALT_CAN_MSGHAND_MOTRB_t MOTRB; /* ALT_CAN_MSGHAND_MOTRB */ + volatile ALT_CAN_MSGHAND_MOTRC_t MOTRC; /* ALT_CAN_MSGHAND_MOTRC */ + volatile ALT_CAN_MSGHAND_MOTRD_t MOTRD; /* ALT_CAN_MSGHAND_MOTRD */ + volatile ALT_CAN_MSGHAND_MONDX_t MONDX; /* ALT_CAN_MSGHAND_MONDX */ + volatile ALT_CAN_MSGHAND_MONDA_t MONDA; /* ALT_CAN_MSGHAND_MONDA */ + volatile ALT_CAN_MSGHAND_MONDB_t MONDB; /* ALT_CAN_MSGHAND_MONDB */ + volatile ALT_CAN_MSGHAND_MONDC_t MONDC; /* ALT_CAN_MSGHAND_MONDC */ + volatile ALT_CAN_MSGHAND_MONDD_t MONDD; /* ALT_CAN_MSGHAND_MONDD */ + volatile ALT_CAN_MSGHAND_MOIPX_t MOIPX; /* ALT_CAN_MSGHAND_MOIPX */ + volatile ALT_CAN_MSGHAND_MOIPA_t MOIPA; /* ALT_CAN_MSGHAND_MOIPA */ + volatile ALT_CAN_MSGHAND_MOIPB_t MOIPB; /* ALT_CAN_MSGHAND_MOIPB */ + volatile ALT_CAN_MSGHAND_MOIPC_t MOIPC; /* ALT_CAN_MSGHAND_MOIPC */ + volatile ALT_CAN_MSGHAND_MOIPD_t MOIPD; /* ALT_CAN_MSGHAND_MOIPD */ + volatile ALT_CAN_MSGHAND_MOVALX_t MOVALX; /* ALT_CAN_MSGHAND_MOVALX */ + volatile ALT_CAN_MSGHAND_MOVALA_t MOVALA; /* ALT_CAN_MSGHAND_MOVALA */ + volatile ALT_CAN_MSGHAND_MOVALB_t MOVALB; /* ALT_CAN_MSGHAND_MOVALB */ + volatile ALT_CAN_MSGHAND_MOVALC_t MOVALC; /* ALT_CAN_MSGHAND_MOVALC */ + volatile ALT_CAN_MSGHAND_MOVALD_t MOVALD; /* ALT_CAN_MSGHAND_MOVALD */ +}; + +/* The typedef declaration for register group ALT_CAN_MSGHAND. */ +typedef volatile struct ALT_CAN_MSGHAND_s ALT_CAN_MSGHAND_t; +/* The struct declaration for the raw register contents of register group ALT_CAN_MSGHAND. */ +struct ALT_CAN_MSGHAND_raw_s +{ + volatile uint32_t MOTRX; /* ALT_CAN_MSGHAND_MOTRX */ + volatile uint32_t MOTRA; /* ALT_CAN_MSGHAND_MOTRA */ + volatile uint32_t MOTRB; /* ALT_CAN_MSGHAND_MOTRB */ + volatile uint32_t MOTRC; /* ALT_CAN_MSGHAND_MOTRC */ + volatile uint32_t MOTRD; /* ALT_CAN_MSGHAND_MOTRD */ + volatile uint32_t MONDX; /* ALT_CAN_MSGHAND_MONDX */ + volatile uint32_t MONDA; /* ALT_CAN_MSGHAND_MONDA */ + volatile uint32_t MONDB; /* ALT_CAN_MSGHAND_MONDB */ + volatile uint32_t MONDC; /* ALT_CAN_MSGHAND_MONDC */ + volatile uint32_t MONDD; /* ALT_CAN_MSGHAND_MONDD */ + volatile uint32_t MOIPX; /* ALT_CAN_MSGHAND_MOIPX */ + volatile uint32_t MOIPA; /* ALT_CAN_MSGHAND_MOIPA */ + volatile uint32_t MOIPB; /* ALT_CAN_MSGHAND_MOIPB */ + volatile uint32_t MOIPC; /* ALT_CAN_MSGHAND_MOIPC */ + volatile uint32_t MOIPD; /* ALT_CAN_MSGHAND_MOIPD */ + volatile uint32_t MOVALX; /* ALT_CAN_MSGHAND_MOVALX */ + volatile uint32_t MOVALA; /* ALT_CAN_MSGHAND_MOVALA */ + volatile uint32_t MOVALB; /* ALT_CAN_MSGHAND_MOVALB */ + volatile uint32_t MOVALC; /* ALT_CAN_MSGHAND_MOVALC */ + volatile uint32_t MOVALD; /* ALT_CAN_MSGHAND_MOVALD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CAN_MSGHAND. */ +typedef volatile struct ALT_CAN_MSGHAND_raw_s ALT_CAN_MSGHAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Message Interface Group - ALT_CAN_MSGIF + * Message Interface Group + * + * These registers provide indirect read and write access for the host CPU to the + * Message RAM. Buffers the data to be transferred to and from the RAM, avoiding + * conflicts between CPU accesses and CAN frame reception/transmission. + * + * The function of the two Interface Register sets is identical. The second + * interface register set is provided to serve application programming. Two groups + * of software drivers may defined, each group is restricted to the use of one of + * the Interface Register sets. The software drivers of one group may interrupt + * software drivers of the other group, but not of the same group. + * + * In a simple example, there is one Read_Message task that uses IF1 to get + * received messages from the Message RAM and there is one Write_Message task that + * uses IF2 to write messages to be transmitted into the Message RAM. Both tasks + * may interrupt each other. + * + * Each set of Interface Registers consists controlled by their own Command + * Registers. The Command Mask Register specifies the direction of the data + * transfer and which parts of a Message Object will be transferred. The Command + * Request Register is used to select a Message Object in the Message RAM as target + * or source for the transfer and to start the action specified in the Command Mask + * Register. + * + */ +/* + * Register : IF1 Command Register - IF1CMR + * + * The control bits of the IF1/2 Command Register specify the transfer direction + * and select which portions of the Message Object should be transferred. A message + * transfer is started as soon as the CPU has written the message number to the low + * byte of the Command Request Register and IFxCMR.AutoInc is zero. With this write + * operation, the IFxCMR.Busy bit is automatically set to 1 to notify the CPU that + * a transfer is in progress. After a wait time of 2 to 8 HOST_CLK periods, the + * transfer between theInterface Register and the Message RAM has been completed + * and the IFxCMR.Busy bit is cleared to 0. The upper limit of the wait time occurs + * when the message transfer coincides with a CAN message transmission, acceptance + * filtering, or message storage. If the CPU writes to both Command Registers + * consecutively (requests a second transfer while another transfer is already in + * progress), the second transfer starts when the first one is completed. Note: + * While Busy bit of IF1/2 Command Register is one, IF1/2 Register Set is write + * protected. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------- + * [7:0] | RW | 0x1 | Message Number + * [12:8] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Automatic Increment of Message Object Number + * [14] | RW | 0x0 | Activation of DMA feature for subsequent internal IFx Register Set + * [15] | R | 0x0 | Busy Flag + * [16] | RW | 0x0 | Access Data Bytes 4-7 + * [17] | RW | 0x0 | Access Data Bytes 0-3 + * [18] | RW | 0x0 | Access Transmission Request Bit and NewDat Bit + * [19] | RW | 0x0 | Clear Interrupt Pending Bit + * [20] | RW | 0x0 | Access Control Bits + * [21] | RW | 0x0 | Access Arbitration Bits + * [22] | RW | 0x0 | Access Mask Bits + * [23] | RW | 0x0 | Write / Read Transfer + * [28:24] | ??? | 0x0 | *UNDEFINED* + * [29] | RW | 0x0 | Clear the AutoInc bit without starting a transfer + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Message Number - MONum + * + * 0x01-0x80 Valid Message Number, the Message Object in the Message RAM is + * selected for data transfer (up to 128 MsgObj). + * + * 0x00 Not a valid Message Number, interpreted as 0x80. + * + * 0x81-0xFF Not a valid Message Number, interpreted as 0x01-0x7F. + * + * Note: When an invalid Message Number is written to IFxCMR.MONum which is higher + * than the last Message Object number, a modulo addressing will occur.When e.g. + * accessing Message Object 33 in a CAN module with 32 Message Objects only, the + * Message Object 1 will be accessed instead. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_MONUM register field. */ +#define ALT_CAN_MSGIF_IF1CMR_MONUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_MONUM register field. */ +#define ALT_CAN_MSGIF_IF1CMR_MONUM_MSB 7 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_MONUM register field. */ +#define ALT_CAN_MSGIF_IF1CMR_MONUM_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_MONUM register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_MONUM_SET_MSK 0x000000ff +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_MONUM register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_MONUM_CLR_MSK 0xffffff00 +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_MONUM register field. */ +#define ALT_CAN_MSGIF_IF1CMR_MONUM_RESET 0x1 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_MONUM field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_MONUM_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_CAN_MSGIF_IF1CMR_MONUM register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_MONUM_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Automatic Increment of Message Object Number - AutoInc + * + * Automatic Increment of Message Object Number + * + * The behavior of the Message Object Number increment depends on the Transfer + * Direction, IFxCMR.WR1RD0. + * + * * Read: The first transfer will be initiated (Busy Bit will set) at write of + * IFxCMR.MONum. The Message Object Number will be incremented and the next + * Message Object will be transferred from Message Object RAM to Interface + * Registers after a read access of Data-Byte 7. + * + * * Write: The first as well as each other transfer will be started after write + * access to Data- Byte7. The Message Object Number will be incremented after + * successful transfer from the Interface Registers to the Message Object RAM. + * + * Always after successful transfer the Busy Bit will be reset. In combination with + * DMAactive the port CAN_IFxDMA is set, too. + * + * Note: If the direction is configured as Read a write access to Data-Byte 7 will + * not start any transfer, as well as if the direction is configured as Write a + * read access to Data-Byte 7 will not start any transfer. At transfer direction + * Read each read of Data-Byte 7 will start a transfer until IFxCMR.AutoInc is + * reset. To aware of resetting a NewDat bit of the following message object, the + * application has to reset IFxCMR.AutoInc before reading the Data-Byte 7 of the + * last message object which will be read. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF1CMR_AUTOINC_E_DISD | 0x0 | AutoIncrement of Message Object Number disabled. + * ALT_CAN_MSGIF_IF1CMR_AUTOINC_E_END | 0x1 | AutoIncrement of Message Object Number enabled. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_AUTOINC + * + * AutoIncrement of Message Object Number disabled. + */ +#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_AUTOINC + * + * AutoIncrement of Message Object Number enabled. + */ +#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field. */ +#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field. */ +#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_MSB 13 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field. */ +#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field. */ +#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_AUTOINC field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGIF_IF1CMR_AUTOINC register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Activation of DMA feature for subsequent internal IFx Register Set - DMAactive + * + * Activation of DMA feature for subsequent internal IFx Register Set + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF1CMR_DMAACT_E_PASSIVE | 0x0 | DMA line leaves passive, independent of IFx + * : | | activities. + * ALT_CAN_MSGIF_IF1CMR_DMAACT_E_INITIATED | 0x1 | By writing to the Command Request Register, an + * : | | internal transfer of Message Object Data between + * : | | RAM and IFx will be initiated. When this + * : | | transfer is complete and DMAactive bit was set, + * : | | the CAN_IFxDMA line gets active. The DMAactive + * : | | bit and port CAN_IFxDMA are staying active until + * : | | first read or write access to one of the IFx + * : | | registers. If AutoInc is set DMAactive will be + * : | | left active, otherwise the bit is reset. Note: + * : | | Due to auto reset feature of DMAactive bit if + * : | | AutoInc is inactive, this bit has to be set for + * : | | each subsequent DMA cycle separately. DMA line + * : | | has to be enabled in CAN Control Register. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_DMAACT + * + * DMA line leaves passive, independent of IFx activities. + */ +#define ALT_CAN_MSGIF_IF1CMR_DMAACT_E_PASSIVE 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_DMAACT + * + * By writing to the Command Request Register, an internal transfer of Message + * Object Data between RAM and IFx will be initiated. When this transfer is + * complete and DMAactive bit was set, the CAN_IFxDMA line gets active. The + * DMAactive bit and port CAN_IFxDMA are staying active until first read or write + * access to one of the IFx registers. If AutoInc is set DMAactive will be left + * active, otherwise the bit is reset. + * + * Note: Due to auto reset feature of DMAactive bit if AutoInc is inactive, this + * bit has to be set for each subsequent DMA cycle separately. DMA line has to be + * enabled in CAN Control Register. + */ +#define ALT_CAN_MSGIF_IF1CMR_DMAACT_E_INITIATED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_DMAACT register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DMAACT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_DMAACT register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DMAACT_MSB 14 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_DMAACT register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DMAACT_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_DMAACT register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_DMAACT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_DMAACT register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_DMAACT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_DMAACT register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DMAACT_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_DMAACT field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_DMAACT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGIF_IF1CMR_DMAACT register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_DMAACT_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Busy Flag - Busy + * + * Busy Flag + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF1CMR_BUSY_E_DONE | 0x0 | Set to zero when read/write action has finished. + * ALT_CAN_MSGIF_IF1CMR_BUSY_E_WRITING | 0x1 | Set to one when writing to the IFxCMR.MONum. + * : | | While bit is one, IFx Register Set is write + * : | | protected. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_BUSY + * + * Set to zero when read/write action has finished. + */ +#define ALT_CAN_MSGIF_IF1CMR_BUSY_E_DONE 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_BUSY + * + * Set to one when writing to the IFxCMR.MONum. While bit is one, IFx Register Set + * is write protected. + */ +#define ALT_CAN_MSGIF_IF1CMR_BUSY_E_WRITING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_BUSY register field. */ +#define ALT_CAN_MSGIF_IF1CMR_BUSY_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_BUSY register field. */ +#define ALT_CAN_MSGIF_IF1CMR_BUSY_MSB 15 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_BUSY register field. */ +#define ALT_CAN_MSGIF_IF1CMR_BUSY_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_BUSY register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_BUSY_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_BUSY register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_BUSY_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_BUSY register field. */ +#define ALT_CAN_MSGIF_IF1CMR_BUSY_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_BUSY field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_BUSY_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGIF_IF1CMR_BUSY register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_BUSY_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Access Data Bytes 4-7 - DataB + * + * Write Direction: + * + * 0= Data Bytes 4-7 unchanged. + * + * 1= transfer Data Bytes 4-7 to Message Object. + * + * Read Direction: + * + * 0= Data Bytes 4-7 unchanged. + * + * 1= transfer Data Bytes 4-7 to IFxDB. + * + * Note: The speed of the message transfer does not depend on how many bytes are + * transferred. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_DATAB register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAB_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_DATAB register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAB_MSB 16 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_DATAB register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAB_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_DATAB register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAB_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_DATAB register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAB_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_DATAB register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAB_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_DATAB field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAB_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGIF_IF1CMR_DATAB register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAB_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Access Data Bytes 0-3 - DataA + * + * Write Direction: + * + * 0= Data Bytes 0-3 unchanged. + * + * 1= transfer Data Bytes 0-3 to Message Object. + * + * Read Direction: + * + * 0= Data Bytes 0-3 unchanged. + * + * 1= transfer Data Bytes 0-3 to IFxDA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_DATAA register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAA_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_DATAA register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAA_MSB 17 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_DATAA register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAA_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_DATAA register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAA_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_DATAA register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAA_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_DATAA register field. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAA_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_DATAA field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAA_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGIF_IF1CMR_DATAA register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_DATAA_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Access Transmission Request Bit and NewDat Bit - TxRqstNewDat + * + * Write Direction: + * + * 0= TxRqst and NewDat bit will be handled according IFxMCTR.NewDat bit and + * IFxMCTR.TxRqst bit. + * + * 1= set TxRqst and NewDat in Message Object to one + * + * Note: If a CAN transmission is requested by setting IFxCMR.TxRqst/NewDat, the + * TxRqst and NewDat bits in the Message Object will be set to one independently of + * the values in IFxMCTR. + * + * Read Direction: + * + * 0= NewDat bit remains unchanged. + * + * 1= clear NewDat bit in the Message Object. + * + * Note: A read access to a Message Object can be combined with the reset of the + * control bits IntPnd and NewDat. The values of these bits transferred to the + * IFxMCTR always reflect the status before resetting them. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field. */ +#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field. */ +#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_MSB 18 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field. */ +#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field. */ +#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Clear Interrupt Pending Bit - ClrIntPnd + * + * Write Direction: + * + * Has no influence to Message Object at write transfer. + * + * Note: When writing to a Message Object, this bit is ignored and copying of + * IntPnd flag from IFx Control Register to Message RAM could only be controlled by + * IFxMTR.IntPnd bit. + * + * Read Direction: + * + * 0= IntPnd bit remains unchanged. + * + * 1= clear IntPnd bit in the Message Object. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_MSB 19 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_CLRINTPND field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Access Control Bits - Control + * + * Write Direction: + * + * 0= Control Bits unchanged. + * + * 1= transfer Control Bits to Message Object. + * + * Note: If IFxCMR.TxRqst/NewDat bit is set, bits IFxMCTR.TxRqst and IFxMCTR.NewDat + * will be ignored. + * + * Read Direction: + * + * 0= Control Bits unchanged. + * + * 1= transfer Control Bits to IFxMCTR Register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_CTL register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CTL_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_CTL register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CTL_MSB 20 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_CTL register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CTL_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_CTL register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_CTL_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_CTL register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_CTL_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_CTL register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CTL_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_CTL field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_CTL_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGIF_IF1CMR_CTL register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_CTL_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Access Arbitration Bits - Arb + * + * Write Direction: + * + * 0= Arbitration bits unchanged. + * + * 1= transfer Identifier + Dir + Xtd + MsgVal to Message Object. + * + * Read Direction: + * + * 0= Arbitration bits unchanged. + * + * 1= transfer Identifier + Dir + Xtd + MsgVal to IFxARB Register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_ARB register field. */ +#define ALT_CAN_MSGIF_IF1CMR_ARB_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_ARB register field. */ +#define ALT_CAN_MSGIF_IF1CMR_ARB_MSB 21 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_ARB register field. */ +#define ALT_CAN_MSGIF_IF1CMR_ARB_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_ARB register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_ARB_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_ARB register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_ARB_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_ARB register field. */ +#define ALT_CAN_MSGIF_IF1CMR_ARB_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_ARB field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_ARB_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGIF_IF1CMR_ARB register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_ARB_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Access Mask Bits - Mask + * + * Write Direction: + * + * 0= Mask bits unchanged. + * + * 1= transfer Identifier Mask + MDir + MXtd to Message Object. + * + * Read Direction: + * + * 0= Mask bits unchanged. + * + * 1= transfer Identifier Mask + MDir + MXtd to IFxMSK Register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_MSK register field. */ +#define ALT_CAN_MSGIF_IF1CMR_MSK_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_MSK register field. */ +#define ALT_CAN_MSGIF_IF1CMR_MSK_MSB 22 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_MSK register field. */ +#define ALT_CAN_MSGIF_IF1CMR_MSK_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_MSK register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_MSK_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_MSK register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_MSK_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_MSK register field. */ +#define ALT_CAN_MSGIF_IF1CMR_MSK_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_MSK field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_MSK_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGIF_IF1CMR_MSK register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_MSK_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : Write / Read Transfer - WR1RD0 + * + * Write / Read Transfer + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF1CMR_WR1RD0_E_RD | 0x0 | Transfer data from the Message Object addressed + * : | | by IFxCMR.MONum into the selected IFx Message + * : | | Buffer Registers. + * ALT_CAN_MSGIF_IF1CMR_WR1RD0_E_WR | 0x1 | Transfer data from the selected IFx Message + * : | | Buffer Registers to the Message Object addressed + * : | | by IFxCMR.MONum. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_WR1RD0 + * + * Transfer data from the Message Object addressed by IFxCMR.MONum into the + * selected IFx Message Buffer Registers. + */ +#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_E_RD 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_WR1RD0 + * + * Transfer data from the selected IFx Message Buffer Registers to the Message + * Object addressed by IFxCMR.MONum. + */ +#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_E_WR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field. */ +#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field. */ +#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_MSB 23 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field. */ +#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field. */ +#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_WR1RD0 field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Clear the AutoInc bit without starting a transfer - ClrAutoInc + * + * Clear the AutoInc bit without starting a transfer + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------ + * ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_E_NOCLR | 0x0 | Has no effect to the other Bits of this + * : | | Register. + * ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_E_CLR | 0x1 | Clear the AutoInc bit without starting a + * : | | transfer, all other bits will be ignored. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC + * + * Has no effect to the other Bits of this Register. + */ +#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC + * + * Clear the AutoInc bit without starting a transfer, all other bits will be + * ignored. + */ +#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_MSB 29 +/* The width in bits of the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field value. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC field value from a register. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_SET(value) (((value) << 29) & 0x20000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF1CMR. + */ +struct ALT_CAN_MSGIF_IF1CMR_s +{ + uint32_t MONum : 8; /* Message Number */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t AutoInc : 1; /* Automatic Increment of Message Object Number */ + uint32_t DMAactive : 1; /* Activation of DMA feature for subsequent internal IFx Register Set */ + const uint32_t Busy : 1; /* Busy Flag */ + uint32_t DataB : 1; /* Access Data Bytes 4-7 */ + uint32_t DataA : 1; /* Access Data Bytes 0-3 */ + uint32_t TxRqstNewDat : 1; /* Access Transmission Request Bit and NewDat Bit */ + uint32_t ClrIntPnd : 1; /* Clear Interrupt Pending Bit */ + uint32_t Control : 1; /* Access Control Bits */ + uint32_t Arb : 1; /* Access Arbitration Bits */ + uint32_t Mask : 1; /* Access Mask Bits */ + uint32_t WR1RD0 : 1; /* Write / Read Transfer */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t ClrAutoInc : 1; /* Clear the AutoInc bit without starting a transfer */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF1CMR. */ +typedef volatile struct ALT_CAN_MSGIF_IF1CMR_s ALT_CAN_MSGIF_IF1CMR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF1CMR register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF1CMR_OFST 0x0 +/* The address of the ALT_CAN_MSGIF_IF1CMR register. */ +#define ALT_CAN_MSGIF_IF1CMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF1CMR_OFST)) + +/* + * Register : IF1 Mask Register - IF1MSK + * + * The Message Object Mask Bits together with the arbitration bits are used for + * acceptance filtering of incoming messages. + * + * Note: While IFxCMR.Busy bit is one, the IF1/2 Register Set is write protected. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------------------- + * [28:0] | RW | 0x1fffffff | Identifier Mask + * [29] | ??? | 0x1 | *UNDEFINED* + * [30] | RW | 0x1 | Mask Message Direction + * [31] | RW | 0x1 | Mask Extended Identifier + * + */ +/* + * Field : Identifier Mask - Msk + * + * 0 = The corresponding bit in the identifier of the message object cannot inhibit + * the match in the acceptance filtering. + * + * 1 = The corresponding identifier bit is used for acceptance filtering. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MSK_MSK register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MSK_MSK register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MSK_MSB 28 +/* The width in bits of the ALT_CAN_MSGIF_IF1MSK_MSK register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MSK_WIDTH 29 +/* The mask used to set the ALT_CAN_MSGIF_IF1MSK_MSK register field value. */ +#define ALT_CAN_MSGIF_IF1MSK_MSK_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_CAN_MSGIF_IF1MSK_MSK register field value. */ +#define ALT_CAN_MSGIF_IF1MSK_MSK_CLR_MSK 0xe0000000 +/* The reset value of the ALT_CAN_MSGIF_IF1MSK_MSK register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MSK_RESET 0x1fffffff +/* Extracts the ALT_CAN_MSGIF_IF1MSK_MSK field value from a register. */ +#define ALT_CAN_MSGIF_IF1MSK_MSK_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_CAN_MSGIF_IF1MSK_MSK register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MSK_MSK_SET(value) (((value) << 0) & 0x1fffffff) + +/* + * Field : Mask Message Direction - MDir + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF1MSK_MDIR_E_NOACCEPTEFFECT | 0x0 | The message direction bit (Dir) has no effect on + * : | | the acceptance filtering. Handle with care + * : | | setting IFxMSK.MDir to zero. + * ALT_CAN_MSGIF_IF1MSK_MDIR_E_ACCEPTEFFECT | 0x1 | The message direction bit (Dir) is used for + * : | | acceptance filtering. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MSK_MDIR + * + * The message direction bit (Dir) has no effect on the acceptance filtering. + * Handle with care setting IFxMSK.MDir to zero. + */ +#define ALT_CAN_MSGIF_IF1MSK_MDIR_E_NOACCEPTEFFECT 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MSK_MDIR + * + * The message direction bit (Dir) is used for acceptance filtering. + */ +#define ALT_CAN_MSGIF_IF1MSK_MDIR_E_ACCEPTEFFECT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MSK_MDIR register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MDIR_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MSK_MDIR register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MDIR_MSB 30 +/* The width in bits of the ALT_CAN_MSGIF_IF1MSK_MDIR register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MDIR_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MSK_MDIR register field value. */ +#define ALT_CAN_MSGIF_IF1MSK_MDIR_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MSK_MDIR register field value. */ +#define ALT_CAN_MSGIF_IF1MSK_MDIR_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGIF_IF1MSK_MDIR register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MDIR_RESET 0x1 +/* Extracts the ALT_CAN_MSGIF_IF1MSK_MDIR field value from a register. */ +#define ALT_CAN_MSGIF_IF1MSK_MDIR_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGIF_IF1MSK_MDIR register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MSK_MDIR_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Mask Extended Identifier - MXtd + * + * When 11-bit (standard) Identifiers are used for a Message Object, the + * identifiers of received Data Frames are written into bits ID28 to ID18. For + * acceptance filtering, only these bits together with mask bits Msk28 to Msk18 are + * considered. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------ + * ALT_CAN_MSGIF_IF1MSK_MXTD_E_NOACCEPTEFFECT | 0x0 | The extended identifier bit (IDE) has no effect + * : | | on the acceptance filtering. + * ALT_CAN_MSGIF_IF1MSK_MXTD_E_ACCEPTEFFECT | 0x1 | The extended identifier bit (IDE) is used for + * : | | acceptance filtering. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MSK_MXTD + * + * The extended identifier bit (IDE) has no effect on the acceptance filtering. + */ +#define ALT_CAN_MSGIF_IF1MSK_MXTD_E_NOACCEPTEFFECT 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MSK_MXTD + * + * The extended identifier bit (IDE) is used for acceptance filtering. + */ +#define ALT_CAN_MSGIF_IF1MSK_MXTD_E_ACCEPTEFFECT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MSK_MXTD register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MXTD_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MSK_MXTD register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MXTD_MSB 31 +/* The width in bits of the ALT_CAN_MSGIF_IF1MSK_MXTD register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MXTD_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MSK_MXTD register field value. */ +#define ALT_CAN_MSGIF_IF1MSK_MXTD_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MSK_MXTD register field value. */ +#define ALT_CAN_MSGIF_IF1MSK_MXTD_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGIF_IF1MSK_MXTD register field. */ +#define ALT_CAN_MSGIF_IF1MSK_MXTD_RESET 0x1 +/* Extracts the ALT_CAN_MSGIF_IF1MSK_MXTD field value from a register. */ +#define ALT_CAN_MSGIF_IF1MSK_MXTD_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGIF_IF1MSK_MXTD register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MSK_MXTD_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF1MSK. + */ +struct ALT_CAN_MSGIF_IF1MSK_s +{ + uint32_t Msk : 29; /* Identifier Mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t MDir : 1; /* Mask Message Direction */ + uint32_t MXtd : 1; /* Mask Extended Identifier */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF1MSK. */ +typedef volatile struct ALT_CAN_MSGIF_IF1MSK_s ALT_CAN_MSGIF_IF1MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF1MSK register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF1MSK_OFST 0x4 +/* The address of the ALT_CAN_MSGIF_IF1MSK register. */ +#define ALT_CAN_MSGIF_IF1MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF1MSK_OFST)) + +/* + * Register : IF1 Arbitration Register - IF1ARB + * + * The Arbitration Registers ID28-0, Xtd, and Dir are used to define the identifier + * and type of outgoing messages and are used (together with the mask registers + * Msk28-0, MXtd, and MDir) for acceptance filtering of incoming messages. A + * received message is stored into the valid Message Object with matching + * identifier and Direction=receive (Data Frame) or Direction=transmit (Remote + * Frame). Extended frames can be stored only in Message Objects with Xtd = one, + * standard frames in Message Objects with Xtd = zero. If a received message (Data + * Frame or Remote Frame) matches with more than one valid Message Object, it is + * stored into that with the lowest message number. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [28:0] | RW | 0x0 | Identifier Mask + * [29] | RW | 0x0 | Message Direction + * [30] | RW | 0x0 | Extended Identifier + * [31] | RW | 0x0 | Message Valid + * + */ +/* + * Field : Identifier Mask - ID + * + * ID28 - ID0 29-bit Identifier (Extended Frame). + * + * ID28 - ID18 11-bit Identifier (Standard Frame). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1ARB_ID register field. */ +#define ALT_CAN_MSGIF_IF1ARB_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1ARB_ID register field. */ +#define ALT_CAN_MSGIF_IF1ARB_ID_MSB 28 +/* The width in bits of the ALT_CAN_MSGIF_IF1ARB_ID register field. */ +#define ALT_CAN_MSGIF_IF1ARB_ID_WIDTH 29 +/* The mask used to set the ALT_CAN_MSGIF_IF1ARB_ID register field value. */ +#define ALT_CAN_MSGIF_IF1ARB_ID_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_CAN_MSGIF_IF1ARB_ID register field value. */ +#define ALT_CAN_MSGIF_IF1ARB_ID_CLR_MSK 0xe0000000 +/* The reset value of the ALT_CAN_MSGIF_IF1ARB_ID register field. */ +#define ALT_CAN_MSGIF_IF1ARB_ID_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1ARB_ID field value from a register. */ +#define ALT_CAN_MSGIF_IF1ARB_ID_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_CAN_MSGIF_IF1ARB_ID register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1ARB_ID_SET(value) (((value) << 0) & 0x1fffffff) + +/* + * Field : Message Direction - Dir + * + * Message Direction + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF1ARB_DIR_E_RX | 0x0 | On TxRqst, a Remote Frame with the identifier of + * : | | this Message Object is transmitted. On reception + * : | | of a Data Frame with matching identifier, that + * : | | message is stored in this Message Object. + * ALT_CAN_MSGIF_IF1ARB_DIR_E_TX | 0x1 | On TxRqst, the respective Message Object is + * : | | transmitted as a Data Frame. On reception of a + * : | | Remote Frame with matching identifier, the + * : | | TxRqst bit of this Message Object is set (if + * : | | RmtEn = one). + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1ARB_DIR + * + * On TxRqst, a Remote Frame with the identifier of this Message Object is + * transmitted. On reception of a Data Frame with matching identifier, that message + * is stored in this Message Object. + */ +#define ALT_CAN_MSGIF_IF1ARB_DIR_E_RX 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1ARB_DIR + * + * On TxRqst, the respective Message Object is transmitted as a Data Frame. On + * reception of a Remote Frame with matching identifier, the TxRqst bit of this + * Message Object is set (if RmtEn = one). + */ +#define ALT_CAN_MSGIF_IF1ARB_DIR_E_TX 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1ARB_DIR register field. */ +#define ALT_CAN_MSGIF_IF1ARB_DIR_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1ARB_DIR register field. */ +#define ALT_CAN_MSGIF_IF1ARB_DIR_MSB 29 +/* The width in bits of the ALT_CAN_MSGIF_IF1ARB_DIR register field. */ +#define ALT_CAN_MSGIF_IF1ARB_DIR_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1ARB_DIR register field value. */ +#define ALT_CAN_MSGIF_IF1ARB_DIR_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1ARB_DIR register field value. */ +#define ALT_CAN_MSGIF_IF1ARB_DIR_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGIF_IF1ARB_DIR register field. */ +#define ALT_CAN_MSGIF_IF1ARB_DIR_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1ARB_DIR field value from a register. */ +#define ALT_CAN_MSGIF_IF1ARB_DIR_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGIF_IF1ARB_DIR register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1ARB_DIR_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Extended Identifier - Xtd + * + * Extended Identifier + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_CAN_MSGIF_IF1ARB_XTD_E_STANDARD | 0x0 | The 11-bit (standard) Identifier will be used + * : | | for this Message Object. + * ALT_CAN_MSGIF_IF1ARB_XTD_E_EXTENDED | 0x1 | The 29-bit (extended) Identifier will be used + * : | | for this Message Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1ARB_XTD + * + * The 11-bit (standard) Identifier will be used for this Message Object. + */ +#define ALT_CAN_MSGIF_IF1ARB_XTD_E_STANDARD 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1ARB_XTD + * + * The 29-bit (extended) Identifier will be used for this Message Object. + */ +#define ALT_CAN_MSGIF_IF1ARB_XTD_E_EXTENDED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1ARB_XTD register field. */ +#define ALT_CAN_MSGIF_IF1ARB_XTD_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1ARB_XTD register field. */ +#define ALT_CAN_MSGIF_IF1ARB_XTD_MSB 30 +/* The width in bits of the ALT_CAN_MSGIF_IF1ARB_XTD register field. */ +#define ALT_CAN_MSGIF_IF1ARB_XTD_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1ARB_XTD register field value. */ +#define ALT_CAN_MSGIF_IF1ARB_XTD_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1ARB_XTD register field value. */ +#define ALT_CAN_MSGIF_IF1ARB_XTD_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGIF_IF1ARB_XTD register field. */ +#define ALT_CAN_MSGIF_IF1ARB_XTD_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1ARB_XTD field value from a register. */ +#define ALT_CAN_MSGIF_IF1ARB_XTD_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGIF_IF1ARB_XTD register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1ARB_XTD_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Message Valid - MsgVal + * + * The CPU must reset the MsgVal bit of all unused Messages Objects during the + * initialization before it resets bit Init in the CAN Control Register. MsgVal + * must also be reset if the Messages Object is no longer used in operation. For + * reconfiguration of Message Objects during normal operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGIF_IF1ARB_MSGVAL_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGIF_IF1ARB_MSGVAL_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1ARB_MSGVAL + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGIF_IF1ARB_MSGVAL_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1ARB_MSGVAL + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGIF_IF1ARB_MSGVAL_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1ARB_MSGVAL register field. */ +#define ALT_CAN_MSGIF_IF1ARB_MSGVAL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1ARB_MSGVAL register field. */ +#define ALT_CAN_MSGIF_IF1ARB_MSGVAL_MSB 31 +/* The width in bits of the ALT_CAN_MSGIF_IF1ARB_MSGVAL register field. */ +#define ALT_CAN_MSGIF_IF1ARB_MSGVAL_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1ARB_MSGVAL register field value. */ +#define ALT_CAN_MSGIF_IF1ARB_MSGVAL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1ARB_MSGVAL register field value. */ +#define ALT_CAN_MSGIF_IF1ARB_MSGVAL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGIF_IF1ARB_MSGVAL register field. */ +#define ALT_CAN_MSGIF_IF1ARB_MSGVAL_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1ARB_MSGVAL field value from a register. */ +#define ALT_CAN_MSGIF_IF1ARB_MSGVAL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGIF_IF1ARB_MSGVAL register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1ARB_MSGVAL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF1ARB. + */ +struct ALT_CAN_MSGIF_IF1ARB_s +{ + uint32_t ID : 29; /* Identifier Mask */ + uint32_t Dir : 1; /* Message Direction */ + uint32_t Xtd : 1; /* Extended Identifier */ + uint32_t MsgVal : 1; /* Message Valid */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF1ARB. */ +typedef volatile struct ALT_CAN_MSGIF_IF1ARB_s ALT_CAN_MSGIF_IF1ARB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF1ARB register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF1ARB_OFST 0x8 +/* The address of the ALT_CAN_MSGIF_IF1ARB register. */ +#define ALT_CAN_MSGIF_IF1ARB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF1ARB_OFST)) + +/* + * Register : IF1 Message Control Register - IF1MCTR + * + * The Arbitration Registers ID28-0, Xtd, and Dir are used to define the identifier + * and type of outgoing messages and are used (together with the mask registers + * Msk28-0, MXtd, and MDir) for acceptance filtering of incoming messages. A + * received message is stored into the valid Message Object with matching + * identifier and Direction=receive (Data Frame) or Direction=transmit (Remote + * Frame). Extended frames can be stored only in Message Objects with Xtd = one, + * standard frames in Message Objects with Xtd = zero. If a received message (Data + * Frame or Remote Frame) matches with more than one valid Message Object, it is + * stored into that with the lowest message number. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------- + * [3:0] | RW | 0x0 | Data Length Code + * [6:4] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | End Of Block + * [8] | RW | 0x0 | Transmit Request + * [9] | RW | 0x0 | Remote Enable + * [10] | RW | 0x0 | Receive Interrupt Enable + * [11] | RW | 0x0 | Transmit Interrupt Enable + * [12] | RW | 0x0 | Use Acceptance Mask + * [13] | RW | 0x0 | Interrupt Pending + * [14] | RW | 0x0 | Message Lost + * [15] | RW | 0x0 | New Data + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Length Code - DLC + * + * 0-8 Data Frame has 0-8 data bytes. + * + * 9-15 Data Frame has 8 data bytes. + * + * Note: The Data Length Code of a Message Object must be defined the same as in + * all the corresponding objects with the same identifier at other nodes. When the + * Message Handler stores a data frame, it will write the DLC to the value given by + * the received message. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MCTR_DLC register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_DLC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MCTR_DLC register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_DLC_MSB 3 +/* The width in bits of the ALT_CAN_MSGIF_IF1MCTR_DLC register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_DLC_WIDTH 4 +/* The mask used to set the ALT_CAN_MSGIF_IF1MCTR_DLC register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_DLC_SET_MSK 0x0000000f +/* The mask used to clear the ALT_CAN_MSGIF_IF1MCTR_DLC register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_DLC_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_CAN_MSGIF_IF1MCTR_DLC register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_DLC_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1MCTR_DLC field value from a register. */ +#define ALT_CAN_MSGIF_IF1MCTR_DLC_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_CAN_MSGIF_IF1MCTR_DLC register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MCTR_DLC_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : End Of Block - EoB + * + * Note: This bit is used to concatenate two or more Message Objects (up to 128) to + * build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer) + * this bit must always be set to one. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------ + * ALT_CAN_MSGIF_IF1MCTR_EOB_E_NOTLAST | 0x0 | Message Object belongs to a FIFO Buffer Block + * : | | and is not the last Message Object of that FIFO + * : | | Buffer Block. + * ALT_CAN_MSGIF_IF1MCTR_EOB_E_SINGLEORLAST | 0x1 | Single Message Object or last Message Object of + * : | | a FIFO Buffer Block. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_EOB + * + * Message Object belongs to a FIFO Buffer Block and is not the last Message Object + * of that FIFO Buffer Block. + */ +#define ALT_CAN_MSGIF_IF1MCTR_EOB_E_NOTLAST 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_EOB + * + * Single Message Object or last Message Object of a FIFO Buffer Block. + */ +#define ALT_CAN_MSGIF_IF1MCTR_EOB_E_SINGLEORLAST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MCTR_EOB register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_EOB_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MCTR_EOB register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_EOB_MSB 7 +/* The width in bits of the ALT_CAN_MSGIF_IF1MCTR_EOB register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_EOB_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MCTR_EOB register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_EOB_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MCTR_EOB register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_EOB_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGIF_IF1MCTR_EOB register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_EOB_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1MCTR_EOB field value from a register. */ +#define ALT_CAN_MSGIF_IF1MCTR_EOB_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGIF_IF1MCTR_EOB register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MCTR_EOB_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit Request - TxRqst + * + * Transmit Request + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGIF_IF1MCTR_TXRQST_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGIF_IF1MCTR_TXRQST_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_TXRQST + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGIF_IF1MCTR_TXRQST_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_TXRQST + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGIF_IF1MCTR_TXRQST_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MCTR_TXRQST register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXRQST_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MCTR_TXRQST register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXRQST_MSB 8 +/* The width in bits of the ALT_CAN_MSGIF_IF1MCTR_TXRQST register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXRQST_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MCTR_TXRQST register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXRQST_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MCTR_TXRQST register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXRQST_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGIF_IF1MCTR_TXRQST register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXRQST_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1MCTR_TXRQST field value from a register. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXRQST_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGIF_IF1MCTR_TXRQST register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXRQST_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Remote Enable - RmtEn + * + * Remote Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------------------- + * ALT_CAN_MSGIF_IF1MCTR_RMTEN_E_UNCHANGED | 0x0 | At the reception of a Remote Frame, TxRqst is + * : | | left unchanged. + * ALT_CAN_MSGIF_IF1MCTR_RMTEN_E_SET | 0x1 | At the reception of a Remote Frame, TxRqst is + * : | | set. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_RMTEN + * + * At the reception of a Remote Frame, TxRqst is left unchanged. + */ +#define ALT_CAN_MSGIF_IF1MCTR_RMTEN_E_UNCHANGED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_RMTEN + * + * At the reception of a Remote Frame, TxRqst is set. + */ +#define ALT_CAN_MSGIF_IF1MCTR_RMTEN_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MCTR_RMTEN register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_RMTEN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MCTR_RMTEN register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_RMTEN_MSB 9 +/* The width in bits of the ALT_CAN_MSGIF_IF1MCTR_RMTEN register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_RMTEN_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MCTR_RMTEN register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_RMTEN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MCTR_RMTEN register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_RMTEN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGIF_IF1MCTR_RMTEN register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_RMTEN_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1MCTR_RMTEN field value from a register. */ +#define ALT_CAN_MSGIF_IF1MCTR_RMTEN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGIF_IF1MCTR_RMTEN register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MCTR_RMTEN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive Interrupt Enable - RxIE + * + * Receive Interrupt Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_CAN_MSGIF_IF1MCTR_RXIE_E_UNCHANGED | 0x0 | IntPnd will be left unchanged after the + * : | | successful reception of a frame. + * ALT_CAN_MSGIF_IF1MCTR_RXIE_E_SET | 0x1 | IntPnd will be set after a successful reception + * : | | of a frame. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_RXIE + * + * IntPnd will be left unchanged after the successful reception of a frame. + */ +#define ALT_CAN_MSGIF_IF1MCTR_RXIE_E_UNCHANGED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_RXIE + * + * IntPnd will be set after a successful reception of a frame. + */ +#define ALT_CAN_MSGIF_IF1MCTR_RXIE_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MCTR_RXIE register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_RXIE_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MCTR_RXIE register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_RXIE_MSB 10 +/* The width in bits of the ALT_CAN_MSGIF_IF1MCTR_RXIE register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_RXIE_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MCTR_RXIE register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_RXIE_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MCTR_RXIE register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_RXIE_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGIF_IF1MCTR_RXIE register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_RXIE_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1MCTR_RXIE field value from a register. */ +#define ALT_CAN_MSGIF_IF1MCTR_RXIE_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGIF_IF1MCTR_RXIE register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MCTR_RXIE_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Transmit Interrupt Enable - TxIE + * + * Transmit Interrupt Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------------------- + * ALT_CAN_MSGIF_IF1MCTR_TXIE_E_UNCHANGED | 0x0 | IntPnd will be left unchanged after the + * : | | successful transmission of a frame. + * ALT_CAN_MSGIF_IF1MCTR_TXIE_E_SET | 0x1 | IntPnd will be set after a successful + * : | | transmission of a frame. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_TXIE + * + * IntPnd will be left unchanged after the successful transmission of a frame. + */ +#define ALT_CAN_MSGIF_IF1MCTR_TXIE_E_UNCHANGED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_TXIE + * + * IntPnd will be set after a successful transmission of a frame. + */ +#define ALT_CAN_MSGIF_IF1MCTR_TXIE_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MCTR_TXIE register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXIE_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MCTR_TXIE register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXIE_MSB 11 +/* The width in bits of the ALT_CAN_MSGIF_IF1MCTR_TXIE register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXIE_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MCTR_TXIE register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXIE_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MCTR_TXIE register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXIE_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGIF_IF1MCTR_TXIE register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXIE_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1MCTR_TXIE field value from a register. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXIE_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGIF_IF1MCTR_TXIE register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MCTR_TXIE_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Use Acceptance Mask - UMask + * + * Use Acceptance Mask + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF1MCTR_UMSK_E_IGNORE | 0x0 | Acceptance formula1: (RTRRx == ~DIR) && (IDERx + * : | | == IDE) && (IDRx == ID) + * ALT_CAN_MSGIF_IF1MCTR_UMSK_E_USE | 0x1 | (Msk28-0, MXtd, and MDir) for acceptance + * : | | filtering, formula: ((RTRRx & MDIR) == (~DIR & + * : | | MDIR)) && ((IDERx & MXtd) == (IDE & MXtd)) && + * : | | ((IDRx & Msk) == (ID & Msk)) Note: If the UMask + * : | | bit is set to one, the Message Object's mask + * : | | bits have to be programmed during initialization + * : | | of the Message Object before MsgVal is set to + * : | | one. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_UMSK + * + * Acceptance formula1: + * + * (RTRRx == ~DIR) && (IDERx == IDE) && (IDRx == ID) + */ +#define ALT_CAN_MSGIF_IF1MCTR_UMSK_E_IGNORE 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_UMSK + * + * (Msk28-0, MXtd, and MDir) for acceptance filtering, formula: + * + * ((RTRRx & MDIR) == (~DIR & MDIR)) && + * + * ((IDERx & MXtd) == (IDE & MXtd)) && + * + * ((IDRx & Msk) == (ID & Msk)) + * + * Note: If the UMask bit is set to one, the Message Object's mask bits have to be + * programmed during initialization of the Message Object before MsgVal is set to + * one. + */ +#define ALT_CAN_MSGIF_IF1MCTR_UMSK_E_USE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MCTR_UMSK register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_UMSK_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MCTR_UMSK register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_UMSK_MSB 12 +/* The width in bits of the ALT_CAN_MSGIF_IF1MCTR_UMSK register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_UMSK_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MCTR_UMSK register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_UMSK_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MCTR_UMSK register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_UMSK_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGIF_IF1MCTR_UMSK register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_UMSK_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1MCTR_UMSK field value from a register. */ +#define ALT_CAN_MSGIF_IF1MCTR_UMSK_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGIF_IF1MCTR_UMSK register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MCTR_UMSK_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Interrupt Pending - IntPnd + * + * Interrupt Pending + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_CAN_MSGIF_IF1MCTR_INTPND_E_NOTSRC | 0x0 | This message object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGIF_IF1MCTR_INTPND_E_SRC | 0x1 | This message object is the source of an + * : | | interrupt. The Interrupt Identifier in the + * : | | Interrupt Register will point to this message + * : | | object if there is no other interrupt source + * : | | with higher priority. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_INTPND + * + * This message object is not the source of an interrupt. + */ +#define ALT_CAN_MSGIF_IF1MCTR_INTPND_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_INTPND + * + * This message object is the source of an interrupt. The Interrupt Identifier in + * the Interrupt Register will point to this message object if there is no other + * interrupt source with higher priority. + */ +#define ALT_CAN_MSGIF_IF1MCTR_INTPND_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MCTR_INTPND register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_INTPND_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MCTR_INTPND register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_INTPND_MSB 13 +/* The width in bits of the ALT_CAN_MSGIF_IF1MCTR_INTPND register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_INTPND_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MCTR_INTPND register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_INTPND_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MCTR_INTPND register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_INTPND_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGIF_IF1MCTR_INTPND register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_INTPND_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1MCTR_INTPND field value from a register. */ +#define ALT_CAN_MSGIF_IF1MCTR_INTPND_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGIF_IF1MCTR_INTPND register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MCTR_INTPND_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Message Lost - MsgLst + * + * Message Lost + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGIF_IF1MCTR_MSGLST_E_NOTLOST | 0x0 | No message lost since last time this bit was + * : | | reset by the CPU. + * ALT_CAN_MSGIF_IF1MCTR_MSGLST_E_LOST | 0x1 | The Message Handler stored a new message into + * : | | this object when NewDat was still set, the CPU + * : | | has lost a message. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_MSGLST + * + * No message lost since last time this bit was reset by the CPU. + */ +#define ALT_CAN_MSGIF_IF1MCTR_MSGLST_E_NOTLOST 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_MSGLST + * + * The Message Handler stored a new message into this object when NewDat was still + * set, the CPU has lost a message. + */ +#define ALT_CAN_MSGIF_IF1MCTR_MSGLST_E_LOST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MCTR_MSGLST register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_MSGLST_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MCTR_MSGLST register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_MSGLST_MSB 14 +/* The width in bits of the ALT_CAN_MSGIF_IF1MCTR_MSGLST register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_MSGLST_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MCTR_MSGLST register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_MSGLST_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MCTR_MSGLST register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_MSGLST_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGIF_IF1MCTR_MSGLST register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_MSGLST_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1MCTR_MSGLST field value from a register. */ +#define ALT_CAN_MSGIF_IF1MCTR_MSGLST_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGIF_IF1MCTR_MSGLST register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MCTR_MSGLST_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : New Data - NewDat + * + * New Data + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF1MCTR_NEWDAT_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGIF_IF1MCTR_NEWDAT_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_NEWDAT + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGIF_IF1MCTR_NEWDAT_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF1MCTR_NEWDAT + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGIF_IF1MCTR_NEWDAT_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1MCTR_NEWDAT register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_NEWDAT_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1MCTR_NEWDAT register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_NEWDAT_MSB 15 +/* The width in bits of the ALT_CAN_MSGIF_IF1MCTR_NEWDAT register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_NEWDAT_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF1MCTR_NEWDAT register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_NEWDAT_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1MCTR_NEWDAT register field value. */ +#define ALT_CAN_MSGIF_IF1MCTR_NEWDAT_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGIF_IF1MCTR_NEWDAT register field. */ +#define ALT_CAN_MSGIF_IF1MCTR_NEWDAT_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1MCTR_NEWDAT field value from a register. */ +#define ALT_CAN_MSGIF_IF1MCTR_NEWDAT_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGIF_IF1MCTR_NEWDAT register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1MCTR_NEWDAT_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF1MCTR. + */ +struct ALT_CAN_MSGIF_IF1MCTR_s +{ + uint32_t DLC : 4; /* Data Length Code */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t EoB : 1; /* End Of Block */ + uint32_t TxRqst : 1; /* Transmit Request */ + uint32_t RmtEn : 1; /* Remote Enable */ + uint32_t RxIE : 1; /* Receive Interrupt Enable */ + uint32_t TxIE : 1; /* Transmit Interrupt Enable */ + uint32_t UMask : 1; /* Use Acceptance Mask */ + uint32_t IntPnd : 1; /* Interrupt Pending */ + uint32_t MsgLst : 1; /* Message Lost */ + uint32_t NewDat : 1; /* New Data */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF1MCTR. */ +typedef volatile struct ALT_CAN_MSGIF_IF1MCTR_s ALT_CAN_MSGIF_IF1MCTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF1MCTR register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF1MCTR_OFST 0xc +/* The address of the ALT_CAN_MSGIF_IF1MCTR register. */ +#define ALT_CAN_MSGIF_IF1MCTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF1MCTR_OFST)) + +/* + * Register : IF1 Data A Register - IF1DA + * + * The data bytes of CAN messages are stored in the IF1/2 registers in the + * following order. In a CAN Data Frame, Data(0) is the first, Data(7) is the last + * byte to be transmitted or received. In CAN's serial bit stream, the MSB of each + * byte will be transmitted first. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Data 0 + * [15:8] | RW | 0x0 | Data 1 + * [23:16] | RW | 0x0 | Data 2 + * [31:24] | RW | 0x0 | Data 3 + * + */ +/* + * Field : Data 0 - Data0 + * + * 1st data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1DA_DATA0 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1DA_DATA0 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA0_MSB 7 +/* The width in bits of the ALT_CAN_MSGIF_IF1DA_DATA0 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA0_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF1DA_DATA0 register field value. */ +#define ALT_CAN_MSGIF_IF1DA_DATA0_SET_MSK 0x000000ff +/* The mask used to clear the ALT_CAN_MSGIF_IF1DA_DATA0 register field value. */ +#define ALT_CAN_MSGIF_IF1DA_DATA0_CLR_MSK 0xffffff00 +/* The reset value of the ALT_CAN_MSGIF_IF1DA_DATA0 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA0_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1DA_DATA0 field value from a register. */ +#define ALT_CAN_MSGIF_IF1DA_DATA0_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_CAN_MSGIF_IF1DA_DATA0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1DA_DATA0_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Data 1 - Data1 + * + * 2nd data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1DA_DATA1 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA1_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1DA_DATA1 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA1_MSB 15 +/* The width in bits of the ALT_CAN_MSGIF_IF1DA_DATA1 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA1_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF1DA_DATA1 register field value. */ +#define ALT_CAN_MSGIF_IF1DA_DATA1_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_CAN_MSGIF_IF1DA_DATA1 register field value. */ +#define ALT_CAN_MSGIF_IF1DA_DATA1_CLR_MSK 0xffff00ff +/* The reset value of the ALT_CAN_MSGIF_IF1DA_DATA1 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA1_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1DA_DATA1 field value from a register. */ +#define ALT_CAN_MSGIF_IF1DA_DATA1_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_CAN_MSGIF_IF1DA_DATA1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1DA_DATA1_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Data 2 - Data2 + * + * 3rd data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1DA_DATA2 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA2_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1DA_DATA2 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA2_MSB 23 +/* The width in bits of the ALT_CAN_MSGIF_IF1DA_DATA2 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA2_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF1DA_DATA2 register field value. */ +#define ALT_CAN_MSGIF_IF1DA_DATA2_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1DA_DATA2 register field value. */ +#define ALT_CAN_MSGIF_IF1DA_DATA2_CLR_MSK 0xff00ffff +/* The reset value of the ALT_CAN_MSGIF_IF1DA_DATA2 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA2_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1DA_DATA2 field value from a register. */ +#define ALT_CAN_MSGIF_IF1DA_DATA2_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_CAN_MSGIF_IF1DA_DATA2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1DA_DATA2_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Data 3 - Data3 + * + * 4th data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1DA_DATA3 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA3_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1DA_DATA3 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA3_MSB 31 +/* The width in bits of the ALT_CAN_MSGIF_IF1DA_DATA3 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA3_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF1DA_DATA3 register field value. */ +#define ALT_CAN_MSGIF_IF1DA_DATA3_SET_MSK 0xff000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1DA_DATA3 register field value. */ +#define ALT_CAN_MSGIF_IF1DA_DATA3_CLR_MSK 0x00ffffff +/* The reset value of the ALT_CAN_MSGIF_IF1DA_DATA3 register field. */ +#define ALT_CAN_MSGIF_IF1DA_DATA3_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1DA_DATA3 field value from a register. */ +#define ALT_CAN_MSGIF_IF1DA_DATA3_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_CAN_MSGIF_IF1DA_DATA3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1DA_DATA3_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF1DA. + */ +struct ALT_CAN_MSGIF_IF1DA_s +{ + uint32_t Data0 : 8; /* Data 0 */ + uint32_t Data1 : 8; /* Data 1 */ + uint32_t Data2 : 8; /* Data 2 */ + uint32_t Data3 : 8; /* Data 3 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF1DA. */ +typedef volatile struct ALT_CAN_MSGIF_IF1DA_s ALT_CAN_MSGIF_IF1DA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF1DA register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF1DA_OFST 0x10 +/* The address of the ALT_CAN_MSGIF_IF1DA register. */ +#define ALT_CAN_MSGIF_IF1DA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF1DA_OFST)) + +/* + * Register : IF1 Data B Register - IF1DB + * + * The data bytes of CAN messages are stored in the IF1/2 registers in the + * following order. In a CAN Data Frame, Data(0) is the first, Data(7) is the last + * byte to be transmitted or received. In CAN's serial bit stream, the MSB of each + * byte will be transmitted first. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Data 0 + * [15:8] | RW | 0x0 | Data 1 + * [23:16] | RW | 0x0 | Data 2 + * [31:24] | RW | 0x0 | Data 3 + * + */ +/* + * Field : Data 0 - Data4 + * + * 5th data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1DB_DATA4 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1DB_DATA4 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA4_MSB 7 +/* The width in bits of the ALT_CAN_MSGIF_IF1DB_DATA4 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA4_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF1DB_DATA4 register field value. */ +#define ALT_CAN_MSGIF_IF1DB_DATA4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_CAN_MSGIF_IF1DB_DATA4 register field value. */ +#define ALT_CAN_MSGIF_IF1DB_DATA4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_CAN_MSGIF_IF1DB_DATA4 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA4_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1DB_DATA4 field value from a register. */ +#define ALT_CAN_MSGIF_IF1DB_DATA4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_CAN_MSGIF_IF1DB_DATA4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1DB_DATA4_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Data 1 - Data5 + * + * 6th data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1DB_DATA5 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA5_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1DB_DATA5 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA5_MSB 15 +/* The width in bits of the ALT_CAN_MSGIF_IF1DB_DATA5 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA5_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF1DB_DATA5 register field value. */ +#define ALT_CAN_MSGIF_IF1DB_DATA5_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_CAN_MSGIF_IF1DB_DATA5 register field value. */ +#define ALT_CAN_MSGIF_IF1DB_DATA5_CLR_MSK 0xffff00ff +/* The reset value of the ALT_CAN_MSGIF_IF1DB_DATA5 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA5_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1DB_DATA5 field value from a register. */ +#define ALT_CAN_MSGIF_IF1DB_DATA5_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_CAN_MSGIF_IF1DB_DATA5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1DB_DATA5_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Data 2 - Data6 + * + * 7th data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1DB_DATA6 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA6_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1DB_DATA6 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA6_MSB 23 +/* The width in bits of the ALT_CAN_MSGIF_IF1DB_DATA6 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA6_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF1DB_DATA6 register field value. */ +#define ALT_CAN_MSGIF_IF1DB_DATA6_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1DB_DATA6 register field value. */ +#define ALT_CAN_MSGIF_IF1DB_DATA6_CLR_MSK 0xff00ffff +/* The reset value of the ALT_CAN_MSGIF_IF1DB_DATA6 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA6_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1DB_DATA6 field value from a register. */ +#define ALT_CAN_MSGIF_IF1DB_DATA6_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_CAN_MSGIF_IF1DB_DATA6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1DB_DATA6_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Data 3 - Data7 + * + * 8th data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1DB_DATA7 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA7_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1DB_DATA7 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA7_MSB 31 +/* The width in bits of the ALT_CAN_MSGIF_IF1DB_DATA7 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA7_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF1DB_DATA7 register field value. */ +#define ALT_CAN_MSGIF_IF1DB_DATA7_SET_MSK 0xff000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF1DB_DATA7 register field value. */ +#define ALT_CAN_MSGIF_IF1DB_DATA7_CLR_MSK 0x00ffffff +/* The reset value of the ALT_CAN_MSGIF_IF1DB_DATA7 register field. */ +#define ALT_CAN_MSGIF_IF1DB_DATA7_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF1DB_DATA7 field value from a register. */ +#define ALT_CAN_MSGIF_IF1DB_DATA7_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_CAN_MSGIF_IF1DB_DATA7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF1DB_DATA7_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF1DB. + */ +struct ALT_CAN_MSGIF_IF1DB_s +{ + uint32_t Data4 : 8; /* Data 0 */ + uint32_t Data5 : 8; /* Data 1 */ + uint32_t Data6 : 8; /* Data 2 */ + uint32_t Data7 : 8; /* Data 3 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF1DB. */ +typedef volatile struct ALT_CAN_MSGIF_IF1DB_s ALT_CAN_MSGIF_IF1DB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF1DB register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF1DB_OFST 0x14 +/* The address of the ALT_CAN_MSGIF_IF1DB register. */ +#define ALT_CAN_MSGIF_IF1DB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF1DB_OFST)) + +/* + * Register : IF2 Command Register - IF2CMR + * + * The control bits of the IF1/2 Command Register specify the transfer direction + * and select which portions of the Message Object should be transferred. A message + * transfer is started as soon as the CPU has written the message number to the low + * byte of the Command Request Register and IFxCMR.AutoInc is zero. With this write + * operation, the IFxCMR.Busy bit is automatically set to 1 to notify the CPU that + * a transfer is in progress. After a wait time of 2 to 8 HOST_CLK periods, the + * transfer between theInterface Register and the Message RAM has been completed + * and the IFxCMR.Busy bit is cleared to 0. The upper limit of the wait time occurs + * when the message transfer coincides with a CAN message transmission, acceptance + * filtering, or message storage. If the CPU writes to both Command Registers + * consecutively (requests a second transfer while another transfer is already in + * progress), the second transfer starts when the first one is completed. Note: + * While Busy bit of IF1/2 Command Register is one, IF1/2 Register Set is write + * protected. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------- + * [7:0] | RW | 0x1 | Message Number + * [12:8] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Automatic Increment of Message Object Number + * [14] | RW | 0x0 | Activation of DMA feature for subsequent internal IFx Register Set + * [15] | R | 0x0 | Busy Flag + * [16] | RW | 0x0 | Access Data Bytes 4-7 + * [17] | RW | 0x0 | Access Data Bytes 0-3 + * [18] | RW | 0x0 | Access Transmission Request Bit and NewDat Bit + * [19] | RW | 0x0 | Clear Interrupt Pending Bit + * [20] | RW | 0x0 | Access Control Bits + * [21] | RW | 0x0 | Access Arbitration Bits + * [22] | RW | 0x0 | Access Mask Bits + * [23] | RW | 0x0 | Write / Read Transfer + * [28:24] | ??? | 0x0 | *UNDEFINED* + * [29] | RW | 0x0 | Clear the AutoInc bit without starting a transfer + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Message Number - MONum + * + * 0x01-0x80 Valid Message Number, the Message Object in the Message RAM is + * selected for data transfer (up to 128 MsgObj). + * + * 0x00 Not a valid Message Number, interpreted as 0x80. + * + * 0x81-0xFF Not a valid Message Number, interpreted as 0x01-0x7F. + * + * Note: When an invalid Message Number is written to IFxCMR.MONum which is higher + * than the last Message Object number, a modulo addressing will occur.When e.g. + * accessing Message Object 33 in a CAN module with 32 Message Objects only, the + * Message Object 1 will be accessed instead. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_MONUM register field. */ +#define ALT_CAN_MSGIF_IF2CMR_MONUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_MONUM register field. */ +#define ALT_CAN_MSGIF_IF2CMR_MONUM_MSB 7 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_MONUM register field. */ +#define ALT_CAN_MSGIF_IF2CMR_MONUM_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_MONUM register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_MONUM_SET_MSK 0x000000ff +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_MONUM register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_MONUM_CLR_MSK 0xffffff00 +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_MONUM register field. */ +#define ALT_CAN_MSGIF_IF2CMR_MONUM_RESET 0x1 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_MONUM field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_MONUM_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_CAN_MSGIF_IF2CMR_MONUM register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_MONUM_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Automatic Increment of Message Object Number - AutoInc + * + * Automatic Increment of Message Object Number + * + * The behavior of the Message Object Number increment depends on the Transfer + * Direction, IFxCMR.WR1RD0. + * + * * Read: The first transfer will be initiated (Busy Bit will set) at write of + * IFxCMR.MONum. The Message Object Number will be incremented and the next + * Message Object will be transferred from Message Object RAM to Interface + * Registers after a read access of Data-Byte 7. + * + * * Write: The first as well as each other transfer will be started after write + * access to Data- Byte7. The Message Object Number will be incremented after + * successful transfer from the Interface Registers to the Message Object RAM. + * + * Always after successful transfer the Busy Bit will be reset. In combination with + * DMAactive the port CAN_IFxDMA is set, too. + * + * Note: If the direction is configured as Read a write access to Data-Byte 7 will + * not start any transfer, as well as if the direction is configured as Write a + * read access to Data-Byte 7 will not start any transfer. At transfer direction + * Read each read of Data-Byte 7 will start a transfer until IFxCMR.AutoInc is + * reset. To aware of resetting a NewDat bit of the following message object, the + * application has to reset IFxCMR.AutoInc before reading the Data-Byte 7 of the + * last message object which will be read. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF2CMR_AUTOINC_E_DISD | 0x0 | AutoIncrement of Message Object Number disabled. + * ALT_CAN_MSGIF_IF2CMR_AUTOINC_E_END | 0x1 | AutoIncrement of Message Object Number enabled. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2CMR_AUTOINC + * + * AutoIncrement of Message Object Number disabled. + */ +#define ALT_CAN_MSGIF_IF2CMR_AUTOINC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2CMR_AUTOINC + * + * AutoIncrement of Message Object Number enabled. + */ +#define ALT_CAN_MSGIF_IF2CMR_AUTOINC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_AUTOINC register field. */ +#define ALT_CAN_MSGIF_IF2CMR_AUTOINC_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_AUTOINC register field. */ +#define ALT_CAN_MSGIF_IF2CMR_AUTOINC_MSB 13 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_AUTOINC register field. */ +#define ALT_CAN_MSGIF_IF2CMR_AUTOINC_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_AUTOINC register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_AUTOINC_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_AUTOINC register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_AUTOINC_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_AUTOINC register field. */ +#define ALT_CAN_MSGIF_IF2CMR_AUTOINC_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_AUTOINC field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_AUTOINC_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGIF_IF2CMR_AUTOINC register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_AUTOINC_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Activation of DMA feature for subsequent internal IFx Register Set - DMAactive + * + * Activation of DMA feature for subsequent internal IFx Register Set + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF2CMR_DMAACT_E_PASSIVE | 0x0 | DMA line leaves passive, independent of IFx + * : | | activities. + * ALT_CAN_MSGIF_IF2CMR_DMAACT_E_INITIATED | 0x1 | By writing to the Command Request Register, an + * : | | internal transfer of Message Object Data between + * : | | RAM and IFx will be initiated. When this + * : | | transfer is complete and DMAactive bit was set, + * : | | the CAN_IFxDMA line gets active. The DMAactive + * : | | bit and port CAN_IFxDMA are staying active until + * : | | first read or write access to one of the IFx + * : | | registers. If AutoInc is set DMAactive will be + * : | | left active, otherwise the bit is reset. Note: + * : | | Due to auto reset feature of DMAactive bit if + * : | | AutoInc is inactive, this bit has to be set for + * : | | each subsequent DMA cycle separately. DMA line + * : | | has to be enabled in CAN Control Register. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2CMR_DMAACT + * + * DMA line leaves passive, independent of IFx activities. + */ +#define ALT_CAN_MSGIF_IF2CMR_DMAACT_E_PASSIVE 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2CMR_DMAACT + * + * By writing to the Command Request Register, an internal transfer of Message + * Object Data between RAM and IFx will be initiated. When this transfer is + * complete and DMAactive bit was set, the CAN_IFxDMA line gets active. The + * DMAactive bit and port CAN_IFxDMA are staying active until first read or write + * access to one of the IFx registers. If AutoInc is set DMAactive will be left + * active, otherwise the bit is reset. + * + * Note: Due to auto reset feature of DMAactive bit if AutoInc is inactive, this + * bit has to be set for each subsequent DMA cycle separately. DMA line has to be + * enabled in CAN Control Register. + */ +#define ALT_CAN_MSGIF_IF2CMR_DMAACT_E_INITIATED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_DMAACT register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DMAACT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_DMAACT register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DMAACT_MSB 14 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_DMAACT register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DMAACT_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_DMAACT register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_DMAACT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_DMAACT register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_DMAACT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_DMAACT register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DMAACT_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_DMAACT field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_DMAACT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGIF_IF2CMR_DMAACT register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_DMAACT_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Busy Flag - Busy + * + * Busy Flag + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF2CMR_BUSY_E_DONE | 0x0 | Set to zero when read/write action has finished. + * ALT_CAN_MSGIF_IF2CMR_BUSY_E_WRITING | 0x1 | Set to one when writing to the IFxCMR.MONum. + * : | | While bit is one, IFx Register Set is write + * : | | protected. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2CMR_BUSY + * + * Set to zero when read/write action has finished. + */ +#define ALT_CAN_MSGIF_IF2CMR_BUSY_E_DONE 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2CMR_BUSY + * + * Set to one when writing to the IFxCMR.MONum. While bit is one, IFx Register Set + * is write protected. + */ +#define ALT_CAN_MSGIF_IF2CMR_BUSY_E_WRITING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_BUSY register field. */ +#define ALT_CAN_MSGIF_IF2CMR_BUSY_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_BUSY register field. */ +#define ALT_CAN_MSGIF_IF2CMR_BUSY_MSB 15 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_BUSY register field. */ +#define ALT_CAN_MSGIF_IF2CMR_BUSY_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_BUSY register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_BUSY_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_BUSY register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_BUSY_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_BUSY register field. */ +#define ALT_CAN_MSGIF_IF2CMR_BUSY_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_BUSY field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_BUSY_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGIF_IF2CMR_BUSY register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_BUSY_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Access Data Bytes 4-7 - DataB + * + * Write Direction: + * + * 0= Data Bytes 4-7 unchanged. + * + * 1= transfer Data Bytes 4-7 to Message Object. + * + * Read Direction: + * + * 0= Data Bytes 4-7 unchanged. + * + * 1= transfer Data Bytes 4-7 to IFxDB. + * + * Note: The speed of the message transfer does not depend on how many bytes are + * transferred. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_DATAB register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAB_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_DATAB register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAB_MSB 16 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_DATAB register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAB_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_DATAB register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAB_SET_MSK 0x00010000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_DATAB register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAB_CLR_MSK 0xfffeffff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_DATAB register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAB_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_DATAB field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAB_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_CAN_MSGIF_IF2CMR_DATAB register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAB_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Access Data Bytes 0-3 - DataA + * + * Write Direction: + * + * 0= Data Bytes 0-3 unchanged. + * + * 1= transfer Data Bytes 0-3 to Message Object. + * + * Read Direction: + * + * 0= Data Bytes 0-3 unchanged. + * + * 1= transfer Data Bytes 0-3 to IFxDA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_DATAA register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAA_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_DATAA register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAA_MSB 17 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_DATAA register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAA_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_DATAA register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAA_SET_MSK 0x00020000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_DATAA register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAA_CLR_MSK 0xfffdffff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_DATAA register field. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAA_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_DATAA field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAA_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_CAN_MSGIF_IF2CMR_DATAA register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_DATAA_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Access Transmission Request Bit and NewDat Bit - TxRqstNewDat + * + * Write Direction: + * + * 0= TxRqst and NewDat bit will be handled according IFxMCTR.NewDat bit and + * IFxMCTR.TxRqst bit. + * + * 1= set TxRqst and NewDat in Message Object to one + * + * Note: If a CAN transmission is requested by setting IFxCMR.TxRqst/NewDat, the + * TxRqst and NewDat bits in the Message Object will be set to one independently of + * the values in IFxMCTR. + * + * Read Direction: + * + * 0= NewDat bit remains unchanged. + * + * 1= clear NewDat bit in the Message Object. + * + * Note: A read access to a Message Object can be combined with the reset of the + * control bits IntPnd and NewDat. The values of these bits transferred to the + * IFxMCTR always reflect the status before resetting them. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT register field. */ +#define ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT register field. */ +#define ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT_MSB 18 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT register field. */ +#define ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT_SET_MSK 0x00040000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT_CLR_MSK 0xfffbffff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT register field. */ +#define ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_TXRQSTNEWDAT_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Clear Interrupt Pending Bit - ClrIntPnd + * + * Write Direction: + * + * Has no influence to Message Object at write transfer. + * + * Note: When writing to a Message Object, this bit is ignored and copying of + * IntPnd flag from IFx Control Register to Message RAM could only be controlled by + * IFxMTR.IntPnd bit. + * + * Read Direction: + * + * 0= IntPnd bit remains unchanged. + * + * 1= clear IntPnd bit in the Message Object. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_CLRINTPND register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRINTPND_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_CLRINTPND register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRINTPND_MSB 19 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_CLRINTPND register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRINTPND_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_CLRINTPND register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRINTPND_SET_MSK 0x00080000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_CLRINTPND register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRINTPND_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_CLRINTPND register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRINTPND_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_CLRINTPND field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRINTPND_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_CAN_MSGIF_IF2CMR_CLRINTPND register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRINTPND_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Access Control Bits - Control + * + * Write Direction: + * + * 0= Control Bits unchanged. + * + * 1= transfer Control Bits to Message Object. + * + * Note: If IFxCMR.TxRqst/NewDat bit is set, bits IFxMCTR.TxRqst and IFxMCTR.NewDat + * will be ignored. + * + * Read Direction: + * + * 0= Control Bits unchanged. + * + * 1= transfer Control Bits to IFxMCTR Register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_CTL register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CTL_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_CTL register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CTL_MSB 20 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_CTL register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CTL_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_CTL register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_CTL_SET_MSK 0x00100000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_CTL register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_CTL_CLR_MSK 0xffefffff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_CTL register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CTL_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_CTL field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_CTL_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_CAN_MSGIF_IF2CMR_CTL register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_CTL_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Access Arbitration Bits - Arb + * + * Write Direction: + * + * 0= Arbitration bits unchanged. + * + * 1= transfer Identifier + Dir + Xtd + MsgVal to Message Object. + * + * Read Direction: + * + * 0= Arbitration bits unchanged. + * + * 1= transfer Identifier + Dir + Xtd + MsgVal to IFxARB Register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_ARB register field. */ +#define ALT_CAN_MSGIF_IF2CMR_ARB_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_ARB register field. */ +#define ALT_CAN_MSGIF_IF2CMR_ARB_MSB 21 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_ARB register field. */ +#define ALT_CAN_MSGIF_IF2CMR_ARB_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_ARB register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_ARB_SET_MSK 0x00200000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_ARB register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_ARB_CLR_MSK 0xffdfffff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_ARB register field. */ +#define ALT_CAN_MSGIF_IF2CMR_ARB_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_ARB field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_ARB_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_CAN_MSGIF_IF2CMR_ARB register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_ARB_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Access Mask Bits - Mask + * + * Write Direction: + * + * 0= Mask bits unchanged. + * + * 1= transfer Identifier Mask + MDir + MXtd to Message Object. + * + * Read Direction: + * + * 0= Mask bits unchanged. + * + * 1= transfer Identifier Mask + MDir + MXtd to IFxMSK Register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_MSK register field. */ +#define ALT_CAN_MSGIF_IF2CMR_MSK_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_MSK register field. */ +#define ALT_CAN_MSGIF_IF2CMR_MSK_MSB 22 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_MSK register field. */ +#define ALT_CAN_MSGIF_IF2CMR_MSK_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_MSK register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_MSK_SET_MSK 0x00400000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_MSK register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_MSK_CLR_MSK 0xffbfffff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_MSK register field. */ +#define ALT_CAN_MSGIF_IF2CMR_MSK_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_MSK field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_MSK_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_CAN_MSGIF_IF2CMR_MSK register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_MSK_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : Write / Read Transfer - WR1RD0 + * + * Write / Read Transfer + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF2CMR_WR1RD0_E_RD | 0x0 | Transfer data from the Message Object addressed + * : | | by IFxCMR.MONum into the selected IFx Message + * : | | Buffer Registers. + * ALT_CAN_MSGIF_IF2CMR_WR1RD0_E_WR | 0x1 | Transfer data from the selected IFx Message + * : | | Buffer Registers to the Message Object addressed + * : | | by IFxCMR.MONum. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2CMR_WR1RD0 + * + * Transfer data from the Message Object addressed by IFxCMR.MONum into the + * selected IFx Message Buffer Registers. + */ +#define ALT_CAN_MSGIF_IF2CMR_WR1RD0_E_RD 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2CMR_WR1RD0 + * + * Transfer data from the selected IFx Message Buffer Registers to the Message + * Object addressed by IFxCMR.MONum. + */ +#define ALT_CAN_MSGIF_IF2CMR_WR1RD0_E_WR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_WR1RD0 register field. */ +#define ALT_CAN_MSGIF_IF2CMR_WR1RD0_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_WR1RD0 register field. */ +#define ALT_CAN_MSGIF_IF2CMR_WR1RD0_MSB 23 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_WR1RD0 register field. */ +#define ALT_CAN_MSGIF_IF2CMR_WR1RD0_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_WR1RD0 register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_WR1RD0_SET_MSK 0x00800000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_WR1RD0 register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_WR1RD0_CLR_MSK 0xff7fffff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_WR1RD0 register field. */ +#define ALT_CAN_MSGIF_IF2CMR_WR1RD0_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_WR1RD0 field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_WR1RD0_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_CAN_MSGIF_IF2CMR_WR1RD0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_WR1RD0_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Clear the AutoInc bit without starting a transfer - ClrAutoInc + * + * Clear the AutoInc bit without starting a transfer + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------ + * ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_E_NOCLR | 0x0 | Has no effect to the other Bits of this + * : | | Register. + * ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_E_CLR | 0x1 | Clear the AutoInc bit without starting a + * : | | transfer, all other bits will be ignored. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC + * + * Has no effect to the other Bits of this Register. + */ +#define ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC + * + * Clear the AutoInc bit without starting a transfer, all other bits will be + * ignored. + */ +#define ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_MSB 29 +/* The width in bits of the ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC register field value. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC register field. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC field value from a register. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2CMR_CLRAUTOINC_SET(value) (((value) << 29) & 0x20000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF2CMR. + */ +struct ALT_CAN_MSGIF_IF2CMR_s +{ + uint32_t MONum : 8; /* Message Number */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t AutoInc : 1; /* Automatic Increment of Message Object Number */ + uint32_t DMAactive : 1; /* Activation of DMA feature for subsequent internal IFx Register Set */ + const uint32_t Busy : 1; /* Busy Flag */ + uint32_t DataB : 1; /* Access Data Bytes 4-7 */ + uint32_t DataA : 1; /* Access Data Bytes 0-3 */ + uint32_t TxRqstNewDat : 1; /* Access Transmission Request Bit and NewDat Bit */ + uint32_t ClrIntPnd : 1; /* Clear Interrupt Pending Bit */ + uint32_t Control : 1; /* Access Control Bits */ + uint32_t Arb : 1; /* Access Arbitration Bits */ + uint32_t Mask : 1; /* Access Mask Bits */ + uint32_t WR1RD0 : 1; /* Write / Read Transfer */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t ClrAutoInc : 1; /* Clear the AutoInc bit without starting a transfer */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF2CMR. */ +typedef volatile struct ALT_CAN_MSGIF_IF2CMR_s ALT_CAN_MSGIF_IF2CMR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF2CMR register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF2CMR_OFST 0x20 +/* The address of the ALT_CAN_MSGIF_IF2CMR register. */ +#define ALT_CAN_MSGIF_IF2CMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF2CMR_OFST)) + +/* + * Register : IF2 Mask Register - IF2MSK + * + * The Message Object Mask Bits together with the arbitration bits are used for + * acceptance filtering of incoming messages. + * + * Note: While IFxCMR.Busy bit is one, the IF1/2 Register Set is write protected. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------------------- + * [28:0] | RW | 0x1fffffff | Identifier Mask + * [29] | ??? | 0x1 | *UNDEFINED* + * [30] | RW | 0x1 | Mask Message Direction + * [31] | RW | 0x1 | Mask Extended Identifier + * + */ +/* + * Field : Identifier Mask - Msk + * + * 0 = The corresponding bit in the identifier of the message object cannot inhibit + * the match in the acceptance filtering. + * + * 1 = The corresponding identifier bit is used for acceptance filtering. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MSK_MSK register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MSK_MSK register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MSK_MSB 28 +/* The width in bits of the ALT_CAN_MSGIF_IF2MSK_MSK register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MSK_WIDTH 29 +/* The mask used to set the ALT_CAN_MSGIF_IF2MSK_MSK register field value. */ +#define ALT_CAN_MSGIF_IF2MSK_MSK_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_CAN_MSGIF_IF2MSK_MSK register field value. */ +#define ALT_CAN_MSGIF_IF2MSK_MSK_CLR_MSK 0xe0000000 +/* The reset value of the ALT_CAN_MSGIF_IF2MSK_MSK register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MSK_RESET 0x1fffffff +/* Extracts the ALT_CAN_MSGIF_IF2MSK_MSK field value from a register. */ +#define ALT_CAN_MSGIF_IF2MSK_MSK_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_CAN_MSGIF_IF2MSK_MSK register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MSK_MSK_SET(value) (((value) << 0) & 0x1fffffff) + +/* + * Field : Mask Message Direction - MDir + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF2MSK_MDIR_E_NOACCEPTEFFECT | 0x0 | The message direction bit (Dir) has no effect on + * : | | the acceptance filtering. Handle with care + * : | | setting IFxMSK.MDir to zero. + * ALT_CAN_MSGIF_IF2MSK_MDIR_E_ACCEPTEFFECT | 0x1 | The message direction bit (Dir) is used for + * : | | acceptance filtering. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MSK_MDIR + * + * The message direction bit (Dir) has no effect on the acceptance filtering. + * Handle with care setting IFxMSK.MDir to zero. + */ +#define ALT_CAN_MSGIF_IF2MSK_MDIR_E_NOACCEPTEFFECT 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MSK_MDIR + * + * The message direction bit (Dir) is used for acceptance filtering. + */ +#define ALT_CAN_MSGIF_IF2MSK_MDIR_E_ACCEPTEFFECT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MSK_MDIR register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MDIR_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MSK_MDIR register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MDIR_MSB 30 +/* The width in bits of the ALT_CAN_MSGIF_IF2MSK_MDIR register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MDIR_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MSK_MDIR register field value. */ +#define ALT_CAN_MSGIF_IF2MSK_MDIR_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MSK_MDIR register field value. */ +#define ALT_CAN_MSGIF_IF2MSK_MDIR_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGIF_IF2MSK_MDIR register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MDIR_RESET 0x1 +/* Extracts the ALT_CAN_MSGIF_IF2MSK_MDIR field value from a register. */ +#define ALT_CAN_MSGIF_IF2MSK_MDIR_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGIF_IF2MSK_MDIR register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MSK_MDIR_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Mask Extended Identifier - MXtd + * + * When 11-bit (standard) Identifiers are used for a Message Object, the + * identifiers of received Data Frames are written into bits ID28 to ID18. For + * acceptance filtering, only these bits together with mask bits Msk28 to Msk18 are + * considered. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------ + * ALT_CAN_MSGIF_IF2MSK_MXTD_E_NOACCEPTEFFECT | 0x0 | The extended identifier bit (IDE) has no effect + * : | | on the acceptance filtering. + * ALT_CAN_MSGIF_IF2MSK_MXTD_E_ACCEPTEFFECT | 0x1 | The extended identifier bit (IDE) is used for + * : | | acceptance filtering. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MSK_MXTD + * + * The extended identifier bit (IDE) has no effect on the acceptance filtering. + */ +#define ALT_CAN_MSGIF_IF2MSK_MXTD_E_NOACCEPTEFFECT 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MSK_MXTD + * + * The extended identifier bit (IDE) is used for acceptance filtering. + */ +#define ALT_CAN_MSGIF_IF2MSK_MXTD_E_ACCEPTEFFECT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MSK_MXTD register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MXTD_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MSK_MXTD register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MXTD_MSB 31 +/* The width in bits of the ALT_CAN_MSGIF_IF2MSK_MXTD register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MXTD_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MSK_MXTD register field value. */ +#define ALT_CAN_MSGIF_IF2MSK_MXTD_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MSK_MXTD register field value. */ +#define ALT_CAN_MSGIF_IF2MSK_MXTD_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGIF_IF2MSK_MXTD register field. */ +#define ALT_CAN_MSGIF_IF2MSK_MXTD_RESET 0x1 +/* Extracts the ALT_CAN_MSGIF_IF2MSK_MXTD field value from a register. */ +#define ALT_CAN_MSGIF_IF2MSK_MXTD_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGIF_IF2MSK_MXTD register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MSK_MXTD_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF2MSK. + */ +struct ALT_CAN_MSGIF_IF2MSK_s +{ + uint32_t Msk : 29; /* Identifier Mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t MDir : 1; /* Mask Message Direction */ + uint32_t MXtd : 1; /* Mask Extended Identifier */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF2MSK. */ +typedef volatile struct ALT_CAN_MSGIF_IF2MSK_s ALT_CAN_MSGIF_IF2MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF2MSK register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF2MSK_OFST 0x24 +/* The address of the ALT_CAN_MSGIF_IF2MSK register. */ +#define ALT_CAN_MSGIF_IF2MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF2MSK_OFST)) + +/* + * Register : IF2 Arbitration Register - IF2ARB + * + * The Arbitration Registers ID28-0, Xtd, and Dir are used to define the identifier + * and type of outgoing messages and are used (together with the mask registers + * Msk28-0, MXtd, and MDir) for acceptance filtering of incoming messages. A + * received message is stored into the valid Message Object with matching + * identifier and Direction=receive (Data Frame) or Direction=transmit (Remote + * Frame). Extended frames can be stored only in Message Objects with Xtd = one, + * standard frames in Message Objects with Xtd = zero. If a received message (Data + * Frame or Remote Frame) matches with more than one valid Message Object, it is + * stored into that with the lowest message number. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [28:0] | RW | 0x0 | Identifier Mask + * [29] | RW | 0x0 | Message Direction + * [30] | RW | 0x0 | Extended Identifier + * [31] | RW | 0x0 | Message Valid + * + */ +/* + * Field : Identifier Mask - ID + * + * ID28 - ID0 29-bit Identifier (Extended Frame). + * + * ID28 - ID18 11-bit Identifier (Standard Frame). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2ARB_ID register field. */ +#define ALT_CAN_MSGIF_IF2ARB_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2ARB_ID register field. */ +#define ALT_CAN_MSGIF_IF2ARB_ID_MSB 28 +/* The width in bits of the ALT_CAN_MSGIF_IF2ARB_ID register field. */ +#define ALT_CAN_MSGIF_IF2ARB_ID_WIDTH 29 +/* The mask used to set the ALT_CAN_MSGIF_IF2ARB_ID register field value. */ +#define ALT_CAN_MSGIF_IF2ARB_ID_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_CAN_MSGIF_IF2ARB_ID register field value. */ +#define ALT_CAN_MSGIF_IF2ARB_ID_CLR_MSK 0xe0000000 +/* The reset value of the ALT_CAN_MSGIF_IF2ARB_ID register field. */ +#define ALT_CAN_MSGIF_IF2ARB_ID_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2ARB_ID field value from a register. */ +#define ALT_CAN_MSGIF_IF2ARB_ID_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_CAN_MSGIF_IF2ARB_ID register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2ARB_ID_SET(value) (((value) << 0) & 0x1fffffff) + +/* + * Field : Message Direction - Dir + * + * Message Direction + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF2ARB_DIR_E_RX | 0x0 | On TxRqst, a Remote Frame with the identifier of + * : | | this Message Object is transmitted. On reception + * : | | of a Data Frame with matching identifier, that + * : | | message is stored in this Message Object. + * ALT_CAN_MSGIF_IF2ARB_DIR_E_TX | 0x1 | On TxRqst, the respective Message Object is + * : | | transmitted as a Data Frame. On reception of a + * : | | Remote Frame with matching identifier, the + * : | | TxRqst bit of this Message Object is set (if + * : | | RmtEn = one). + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2ARB_DIR + * + * On TxRqst, a Remote Frame with the identifier of this Message Object is + * transmitted. On reception of a Data Frame with matching identifier, that message + * is stored in this Message Object. + */ +#define ALT_CAN_MSGIF_IF2ARB_DIR_E_RX 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2ARB_DIR + * + * On TxRqst, the respective Message Object is transmitted as a Data Frame. On + * reception of a Remote Frame with matching identifier, the TxRqst bit of this + * Message Object is set (if RmtEn = one). + */ +#define ALT_CAN_MSGIF_IF2ARB_DIR_E_TX 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2ARB_DIR register field. */ +#define ALT_CAN_MSGIF_IF2ARB_DIR_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2ARB_DIR register field. */ +#define ALT_CAN_MSGIF_IF2ARB_DIR_MSB 29 +/* The width in bits of the ALT_CAN_MSGIF_IF2ARB_DIR register field. */ +#define ALT_CAN_MSGIF_IF2ARB_DIR_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2ARB_DIR register field value. */ +#define ALT_CAN_MSGIF_IF2ARB_DIR_SET_MSK 0x20000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2ARB_DIR register field value. */ +#define ALT_CAN_MSGIF_IF2ARB_DIR_CLR_MSK 0xdfffffff +/* The reset value of the ALT_CAN_MSGIF_IF2ARB_DIR register field. */ +#define ALT_CAN_MSGIF_IF2ARB_DIR_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2ARB_DIR field value from a register. */ +#define ALT_CAN_MSGIF_IF2ARB_DIR_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_CAN_MSGIF_IF2ARB_DIR register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2ARB_DIR_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Extended Identifier - Xtd + * + * Extended Identifier + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_CAN_MSGIF_IF2ARB_XTD_E_STANDARD | 0x0 | The 11-bit (standard) Identifier will be used + * : | | for this Message Object. + * ALT_CAN_MSGIF_IF2ARB_XTD_E_EXTENDED | 0x1 | The 29-bit (extended) Identifier will be used + * : | | for this Message Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2ARB_XTD + * + * The 11-bit (standard) Identifier will be used for this Message Object. + */ +#define ALT_CAN_MSGIF_IF2ARB_XTD_E_STANDARD 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2ARB_XTD + * + * The 29-bit (extended) Identifier will be used for this Message Object. + */ +#define ALT_CAN_MSGIF_IF2ARB_XTD_E_EXTENDED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2ARB_XTD register field. */ +#define ALT_CAN_MSGIF_IF2ARB_XTD_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2ARB_XTD register field. */ +#define ALT_CAN_MSGIF_IF2ARB_XTD_MSB 30 +/* The width in bits of the ALT_CAN_MSGIF_IF2ARB_XTD register field. */ +#define ALT_CAN_MSGIF_IF2ARB_XTD_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2ARB_XTD register field value. */ +#define ALT_CAN_MSGIF_IF2ARB_XTD_SET_MSK 0x40000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2ARB_XTD register field value. */ +#define ALT_CAN_MSGIF_IF2ARB_XTD_CLR_MSK 0xbfffffff +/* The reset value of the ALT_CAN_MSGIF_IF2ARB_XTD register field. */ +#define ALT_CAN_MSGIF_IF2ARB_XTD_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2ARB_XTD field value from a register. */ +#define ALT_CAN_MSGIF_IF2ARB_XTD_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_CAN_MSGIF_IF2ARB_XTD register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2ARB_XTD_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Message Valid - MsgVal + * + * The CPU must reset the MsgVal bit of all unused Messages Objects during the + * initialization before it resets bit Init in the CAN Control Register. MsgVal + * must also be reset if the Messages Object is no longer used in operation. For + * reconfiguration of Message Objects during normal operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGIF_IF2ARB_MSGVAL_E_IGNORED | 0x0 | The Message Object is ignored by the Message + * : | | Handler. + * ALT_CAN_MSGIF_IF2ARB_MSGVAL_E_CONSIDERED | 0x1 | The Message Object is configured and should be + * : | | considered by the Message Handler. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2ARB_MSGVAL + * + * The Message Object is ignored by the Message Handler. + */ +#define ALT_CAN_MSGIF_IF2ARB_MSGVAL_E_IGNORED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2ARB_MSGVAL + * + * The Message Object is configured and should be considered by the Message + * Handler. + */ +#define ALT_CAN_MSGIF_IF2ARB_MSGVAL_E_CONSIDERED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2ARB_MSGVAL register field. */ +#define ALT_CAN_MSGIF_IF2ARB_MSGVAL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2ARB_MSGVAL register field. */ +#define ALT_CAN_MSGIF_IF2ARB_MSGVAL_MSB 31 +/* The width in bits of the ALT_CAN_MSGIF_IF2ARB_MSGVAL register field. */ +#define ALT_CAN_MSGIF_IF2ARB_MSGVAL_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2ARB_MSGVAL register field value. */ +#define ALT_CAN_MSGIF_IF2ARB_MSGVAL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2ARB_MSGVAL register field value. */ +#define ALT_CAN_MSGIF_IF2ARB_MSGVAL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CAN_MSGIF_IF2ARB_MSGVAL register field. */ +#define ALT_CAN_MSGIF_IF2ARB_MSGVAL_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2ARB_MSGVAL field value from a register. */ +#define ALT_CAN_MSGIF_IF2ARB_MSGVAL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CAN_MSGIF_IF2ARB_MSGVAL register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2ARB_MSGVAL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF2ARB. + */ +struct ALT_CAN_MSGIF_IF2ARB_s +{ + uint32_t ID : 29; /* Identifier Mask */ + uint32_t Dir : 1; /* Message Direction */ + uint32_t Xtd : 1; /* Extended Identifier */ + uint32_t MsgVal : 1; /* Message Valid */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF2ARB. */ +typedef volatile struct ALT_CAN_MSGIF_IF2ARB_s ALT_CAN_MSGIF_IF2ARB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF2ARB register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF2ARB_OFST 0x28 +/* The address of the ALT_CAN_MSGIF_IF2ARB register. */ +#define ALT_CAN_MSGIF_IF2ARB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF2ARB_OFST)) + +/* + * Register : IF2 Message Control Register - IF2MCTR + * + * The Arbitration Registers ID28-0, Xtd, and Dir are used to define the identifier + * and type of outgoing messages and are used (together with the mask registers + * Msk28-0, MXtd, and MDir) for acceptance filtering of incoming messages. A + * received message is stored into the valid Message Object with matching + * identifier and Direction=receive (Data Frame) or Direction=transmit (Remote + * Frame). Extended frames can be stored only in Message Objects with Xtd = one, + * standard frames in Message Objects with Xtd = zero. If a received message (Data + * Frame or Remote Frame) matches with more than one valid Message Object, it is + * stored into that with the lowest message number. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------- + * [3:0] | RW | 0x0 | Data Length Code + * [6:4] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | End Of Block + * [8] | RW | 0x0 | Transmit Request + * [9] | RW | 0x0 | Remote Enable + * [10] | RW | 0x0 | Receive Interrupt Enable + * [11] | RW | 0x0 | Transmit Interrupt Enable + * [12] | RW | 0x0 | Use Acceptance Mask + * [13] | RW | 0x0 | Interrupt Pending + * [14] | RW | 0x0 | Message Lost + * [15] | RW | 0x0 | New Data + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Length Code - DLC + * + * 0-8 Data Frame has 0-8 data bytes. + * + * 9-15 Data Frame has 8 data bytes. + * + * Note: The Data Length Code of a Message Object must be defined the same as in + * all the corresponding objects with the same identifier at other nodes. When the + * Message Handler stores a data frame, it will write the DLC to the value given by + * the received message. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MCTR_DLC register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_DLC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MCTR_DLC register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_DLC_MSB 3 +/* The width in bits of the ALT_CAN_MSGIF_IF2MCTR_DLC register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_DLC_WIDTH 4 +/* The mask used to set the ALT_CAN_MSGIF_IF2MCTR_DLC register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_DLC_SET_MSK 0x0000000f +/* The mask used to clear the ALT_CAN_MSGIF_IF2MCTR_DLC register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_DLC_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_CAN_MSGIF_IF2MCTR_DLC register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_DLC_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2MCTR_DLC field value from a register. */ +#define ALT_CAN_MSGIF_IF2MCTR_DLC_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_CAN_MSGIF_IF2MCTR_DLC register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MCTR_DLC_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : End Of Block - EoB + * + * Note: This bit is used to concatenate two or more Message Objects (up to 128) to + * build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer) + * this bit must always be set to one. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------ + * ALT_CAN_MSGIF_IF2MCTR_EOB_E_NOTLAST | 0x0 | Message Object belongs to a FIFO Buffer Block + * : | | and is not the last Message Object of that FIFO + * : | | Buffer Block. + * ALT_CAN_MSGIF_IF2MCTR_EOB_E_SINGLEORLAST | 0x1 | Single Message Object or last Message Object of + * : | | a FIFO Buffer Block. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_EOB + * + * Message Object belongs to a FIFO Buffer Block and is not the last Message Object + * of that FIFO Buffer Block. + */ +#define ALT_CAN_MSGIF_IF2MCTR_EOB_E_NOTLAST 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_EOB + * + * Single Message Object or last Message Object of a FIFO Buffer Block. + */ +#define ALT_CAN_MSGIF_IF2MCTR_EOB_E_SINGLEORLAST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MCTR_EOB register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_EOB_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MCTR_EOB register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_EOB_MSB 7 +/* The width in bits of the ALT_CAN_MSGIF_IF2MCTR_EOB register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_EOB_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MCTR_EOB register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_EOB_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MCTR_EOB register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_EOB_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CAN_MSGIF_IF2MCTR_EOB register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_EOB_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2MCTR_EOB field value from a register. */ +#define ALT_CAN_MSGIF_IF2MCTR_EOB_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CAN_MSGIF_IF2MCTR_EOB register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MCTR_EOB_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit Request - TxRqst + * + * Transmit Request + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------- + * ALT_CAN_MSGIF_IF2MCTR_TXRQST_E_NOTWAITING | 0x0 | This Message Object is not waiting for + * : | | transmission. + * ALT_CAN_MSGIF_IF2MCTR_TXRQST_E_PENDING | 0x1 | The transmission of this Message Object is + * : | | requested and is not yet done. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_TXRQST + * + * This Message Object is not waiting for transmission. + */ +#define ALT_CAN_MSGIF_IF2MCTR_TXRQST_E_NOTWAITING 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_TXRQST + * + * The transmission of this Message Object is requested and is not yet done. + */ +#define ALT_CAN_MSGIF_IF2MCTR_TXRQST_E_PENDING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MCTR_TXRQST register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXRQST_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MCTR_TXRQST register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXRQST_MSB 8 +/* The width in bits of the ALT_CAN_MSGIF_IF2MCTR_TXRQST register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXRQST_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MCTR_TXRQST register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXRQST_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MCTR_TXRQST register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXRQST_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CAN_MSGIF_IF2MCTR_TXRQST register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXRQST_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2MCTR_TXRQST field value from a register. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXRQST_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CAN_MSGIF_IF2MCTR_TXRQST register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXRQST_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Remote Enable - RmtEn + * + * Remote Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------------------- + * ALT_CAN_MSGIF_IF2MCTR_RMTEN_E_UNCHANGED | 0x0 | At the reception of a Remote Frame, TxRqst is + * : | | left unchanged. + * ALT_CAN_MSGIF_IF2MCTR_RMTEN_E_SET | 0x1 | At the reception of a Remote Frame, TxRqst is + * : | | set. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_RMTEN + * + * At the reception of a Remote Frame, TxRqst is left unchanged. + */ +#define ALT_CAN_MSGIF_IF2MCTR_RMTEN_E_UNCHANGED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_RMTEN + * + * At the reception of a Remote Frame, TxRqst is set. + */ +#define ALT_CAN_MSGIF_IF2MCTR_RMTEN_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MCTR_RMTEN register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_RMTEN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MCTR_RMTEN register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_RMTEN_MSB 9 +/* The width in bits of the ALT_CAN_MSGIF_IF2MCTR_RMTEN register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_RMTEN_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MCTR_RMTEN register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_RMTEN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MCTR_RMTEN register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_RMTEN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CAN_MSGIF_IF2MCTR_RMTEN register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_RMTEN_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2MCTR_RMTEN field value from a register. */ +#define ALT_CAN_MSGIF_IF2MCTR_RMTEN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CAN_MSGIF_IF2MCTR_RMTEN register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MCTR_RMTEN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive Interrupt Enable - RxIE + * + * Receive Interrupt Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_CAN_MSGIF_IF2MCTR_RXIE_E_UNCHANGED | 0x0 | IntPnd will be left unchanged after the + * : | | successful reception of a frame. + * ALT_CAN_MSGIF_IF2MCTR_RXIE_E_SET | 0x1 | IntPnd will be set after a successful reception + * : | | of a frame. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_RXIE + * + * IntPnd will be left unchanged after the successful reception of a frame. + */ +#define ALT_CAN_MSGIF_IF2MCTR_RXIE_E_UNCHANGED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_RXIE + * + * IntPnd will be set after a successful reception of a frame. + */ +#define ALT_CAN_MSGIF_IF2MCTR_RXIE_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MCTR_RXIE register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_RXIE_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MCTR_RXIE register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_RXIE_MSB 10 +/* The width in bits of the ALT_CAN_MSGIF_IF2MCTR_RXIE register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_RXIE_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MCTR_RXIE register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_RXIE_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MCTR_RXIE register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_RXIE_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CAN_MSGIF_IF2MCTR_RXIE register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_RXIE_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2MCTR_RXIE field value from a register. */ +#define ALT_CAN_MSGIF_IF2MCTR_RXIE_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CAN_MSGIF_IF2MCTR_RXIE register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MCTR_RXIE_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Transmit Interrupt Enable - TxIE + * + * Transmit Interrupt Enable + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------------------- + * ALT_CAN_MSGIF_IF2MCTR_TXIE_E_UNCHANGED | 0x0 | IntPnd will be left unchanged after the + * : | | successful transmission of a frame. + * ALT_CAN_MSGIF_IF2MCTR_TXIE_E_SET | 0x1 | IntPnd will be set after a successful + * : | | transmission of a frame. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_TXIE + * + * IntPnd will be left unchanged after the successful transmission of a frame. + */ +#define ALT_CAN_MSGIF_IF2MCTR_TXIE_E_UNCHANGED 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_TXIE + * + * IntPnd will be set after a successful transmission of a frame. + */ +#define ALT_CAN_MSGIF_IF2MCTR_TXIE_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MCTR_TXIE register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXIE_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MCTR_TXIE register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXIE_MSB 11 +/* The width in bits of the ALT_CAN_MSGIF_IF2MCTR_TXIE register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXIE_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MCTR_TXIE register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXIE_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MCTR_TXIE register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXIE_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CAN_MSGIF_IF2MCTR_TXIE register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXIE_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2MCTR_TXIE field value from a register. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXIE_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CAN_MSGIF_IF2MCTR_TXIE register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MCTR_TXIE_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Use Acceptance Mask - UMask + * + * Use Acceptance Mask + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF2MCTR_UMSK_E_IGNORE | 0x0 | Acceptance formula1: (RTRRx == ~DIR) && (IDERx + * : | | == IDE) && (IDRx == ID) + * ALT_CAN_MSGIF_IF2MCTR_UMSK_E_USE | 0x1 | (Msk28-0, MXtd, and MDir) for acceptance + * : | | filtering, formula: ((RTRRx & MDIR) == (~DIR & + * : | | MDIR)) && ((IDERx & MXtd) == (IDE & MXtd)) && + * : | | ((IDRx & Msk) == (ID & Msk)) Note: If the UMask + * : | | bit is set to one, the Message Object's mask + * : | | bits have to be programmed during initialization + * : | | of the Message Object before MsgVal is set to + * : | | one. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_UMSK + * + * Acceptance formula1: + * + * (RTRRx == ~DIR) && (IDERx == IDE) && (IDRx == ID) + */ +#define ALT_CAN_MSGIF_IF2MCTR_UMSK_E_IGNORE 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_UMSK + * + * (Msk28-0, MXtd, and MDir) for acceptance filtering, formula: + * + * ((RTRRx & MDIR) == (~DIR & MDIR)) && + * + * ((IDERx & MXtd) == (IDE & MXtd)) && + * + * ((IDRx & Msk) == (ID & Msk)) + * + * Note: If the UMask bit is set to one, the Message Object's mask bits have to be + * programmed during initialization of the Message Object before MsgVal is set to + * one. + */ +#define ALT_CAN_MSGIF_IF2MCTR_UMSK_E_USE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MCTR_UMSK register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_UMSK_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MCTR_UMSK register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_UMSK_MSB 12 +/* The width in bits of the ALT_CAN_MSGIF_IF2MCTR_UMSK register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_UMSK_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MCTR_UMSK register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_UMSK_SET_MSK 0x00001000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MCTR_UMSK register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_UMSK_CLR_MSK 0xffffefff +/* The reset value of the ALT_CAN_MSGIF_IF2MCTR_UMSK register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_UMSK_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2MCTR_UMSK field value from a register. */ +#define ALT_CAN_MSGIF_IF2MCTR_UMSK_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_CAN_MSGIF_IF2MCTR_UMSK register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MCTR_UMSK_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Interrupt Pending - IntPnd + * + * Interrupt Pending + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_CAN_MSGIF_IF2MCTR_INTPND_E_NOTSRC | 0x0 | This message object is not the source of an + * : | | interrupt. + * ALT_CAN_MSGIF_IF2MCTR_INTPND_E_SRC | 0x1 | This message object is the source of an + * : | | interrupt. The Interrupt Identifier in the + * : | | Interrupt Register will point to this message + * : | | object if there is no other interrupt source + * : | | with higher priority. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_INTPND + * + * This message object is not the source of an interrupt. + */ +#define ALT_CAN_MSGIF_IF2MCTR_INTPND_E_NOTSRC 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_INTPND + * + * This message object is the source of an interrupt. The Interrupt Identifier in + * the Interrupt Register will point to this message object if there is no other + * interrupt source with higher priority. + */ +#define ALT_CAN_MSGIF_IF2MCTR_INTPND_E_SRC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MCTR_INTPND register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_INTPND_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MCTR_INTPND register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_INTPND_MSB 13 +/* The width in bits of the ALT_CAN_MSGIF_IF2MCTR_INTPND register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_INTPND_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MCTR_INTPND register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_INTPND_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MCTR_INTPND register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_INTPND_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CAN_MSGIF_IF2MCTR_INTPND register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_INTPND_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2MCTR_INTPND field value from a register. */ +#define ALT_CAN_MSGIF_IF2MCTR_INTPND_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CAN_MSGIF_IF2MCTR_INTPND register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MCTR_INTPND_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Message Lost - MsgLst + * + * Message Lost + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------------------------- + * ALT_CAN_MSGIF_IF2MCTR_MSGLST_E_NOTLOST | 0x0 | No message lost since last time this bit was + * : | | reset by the CPU. + * ALT_CAN_MSGIF_IF2MCTR_MSGLST_E_LOST | 0x1 | The Message Handler stored a new message into + * : | | this object when NewDat was still set, the CPU + * : | | has lost a message. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_MSGLST + * + * No message lost since last time this bit was reset by the CPU. + */ +#define ALT_CAN_MSGIF_IF2MCTR_MSGLST_E_NOTLOST 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_MSGLST + * + * The Message Handler stored a new message into this object when NewDat was still + * set, the CPU has lost a message. + */ +#define ALT_CAN_MSGIF_IF2MCTR_MSGLST_E_LOST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MCTR_MSGLST register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_MSGLST_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MCTR_MSGLST register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_MSGLST_MSB 14 +/* The width in bits of the ALT_CAN_MSGIF_IF2MCTR_MSGLST register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_MSGLST_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MCTR_MSGLST register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_MSGLST_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MCTR_MSGLST register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_MSGLST_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CAN_MSGIF_IF2MCTR_MSGLST register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_MSGLST_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2MCTR_MSGLST field value from a register. */ +#define ALT_CAN_MSGIF_IF2MCTR_MSGLST_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CAN_MSGIF_IF2MCTR_MSGLST register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MCTR_MSGLST_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : New Data - NewDat + * + * New Data + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------------- + * ALT_CAN_MSGIF_IF2MCTR_NEWDAT_E_NOTWRITTEN | 0x0 | No new data has been written into the data + * : | | portion of this Message Object by the Message + * : | | Handler since last time this flag was cleared by + * : | | the CPU. + * ALT_CAN_MSGIF_IF2MCTR_NEWDAT_E_WRITTEN | 0x1 | The Message Handler or the CPU has written new + * : | | data into the data portion of this Message + * : | | Object. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_NEWDAT + * + * No new data has been written into the data portion of this Message Object by the + * Message Handler since last time this flag was cleared by the CPU. + */ +#define ALT_CAN_MSGIF_IF2MCTR_NEWDAT_E_NOTWRITTEN 0x0 +/* + * Enumerated value for register field ALT_CAN_MSGIF_IF2MCTR_NEWDAT + * + * The Message Handler or the CPU has written new data into the data portion of + * this Message Object. + */ +#define ALT_CAN_MSGIF_IF2MCTR_NEWDAT_E_WRITTEN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2MCTR_NEWDAT register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_NEWDAT_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2MCTR_NEWDAT register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_NEWDAT_MSB 15 +/* The width in bits of the ALT_CAN_MSGIF_IF2MCTR_NEWDAT register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_NEWDAT_WIDTH 1 +/* The mask used to set the ALT_CAN_MSGIF_IF2MCTR_NEWDAT register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_NEWDAT_SET_MSK 0x00008000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2MCTR_NEWDAT register field value. */ +#define ALT_CAN_MSGIF_IF2MCTR_NEWDAT_CLR_MSK 0xffff7fff +/* The reset value of the ALT_CAN_MSGIF_IF2MCTR_NEWDAT register field. */ +#define ALT_CAN_MSGIF_IF2MCTR_NEWDAT_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2MCTR_NEWDAT field value from a register. */ +#define ALT_CAN_MSGIF_IF2MCTR_NEWDAT_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_CAN_MSGIF_IF2MCTR_NEWDAT register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2MCTR_NEWDAT_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF2MCTR. + */ +struct ALT_CAN_MSGIF_IF2MCTR_s +{ + uint32_t DLC : 4; /* Data Length Code */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t EoB : 1; /* End Of Block */ + uint32_t TxRqst : 1; /* Transmit Request */ + uint32_t RmtEn : 1; /* Remote Enable */ + uint32_t RxIE : 1; /* Receive Interrupt Enable */ + uint32_t TxIE : 1; /* Transmit Interrupt Enable */ + uint32_t UMask : 1; /* Use Acceptance Mask */ + uint32_t IntPnd : 1; /* Interrupt Pending */ + uint32_t MsgLst : 1; /* Message Lost */ + uint32_t NewDat : 1; /* New Data */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF2MCTR. */ +typedef volatile struct ALT_CAN_MSGIF_IF2MCTR_s ALT_CAN_MSGIF_IF2MCTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF2MCTR register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF2MCTR_OFST 0x2c +/* The address of the ALT_CAN_MSGIF_IF2MCTR register. */ +#define ALT_CAN_MSGIF_IF2MCTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF2MCTR_OFST)) + +/* + * Register : IF2 Data A Register - IF2DA + * + * The data bytes of CAN messages are stored in the IF1/2 registers in the + * following order. In a CAN Data Frame, Data(0) is the first, Data(7) is the last + * byte to be transmitted or received. In CAN's serial bit stream, the MSB of each + * byte will be transmitted first. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Data 0 + * [15:8] | RW | 0x0 | Data 1 + * [23:16] | RW | 0x0 | Data 2 + * [31:24] | RW | 0x0 | Data 3 + * + */ +/* + * Field : Data 0 - Data0 + * + * 1st data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2DA_DATA0 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2DA_DATA0 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA0_MSB 7 +/* The width in bits of the ALT_CAN_MSGIF_IF2DA_DATA0 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA0_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF2DA_DATA0 register field value. */ +#define ALT_CAN_MSGIF_IF2DA_DATA0_SET_MSK 0x000000ff +/* The mask used to clear the ALT_CAN_MSGIF_IF2DA_DATA0 register field value. */ +#define ALT_CAN_MSGIF_IF2DA_DATA0_CLR_MSK 0xffffff00 +/* The reset value of the ALT_CAN_MSGIF_IF2DA_DATA0 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA0_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2DA_DATA0 field value from a register. */ +#define ALT_CAN_MSGIF_IF2DA_DATA0_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_CAN_MSGIF_IF2DA_DATA0 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2DA_DATA0_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Data 1 - Data1 + * + * 2nd data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2DA_DATA1 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA1_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2DA_DATA1 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA1_MSB 15 +/* The width in bits of the ALT_CAN_MSGIF_IF2DA_DATA1 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA1_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF2DA_DATA1 register field value. */ +#define ALT_CAN_MSGIF_IF2DA_DATA1_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_CAN_MSGIF_IF2DA_DATA1 register field value. */ +#define ALT_CAN_MSGIF_IF2DA_DATA1_CLR_MSK 0xffff00ff +/* The reset value of the ALT_CAN_MSGIF_IF2DA_DATA1 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA1_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2DA_DATA1 field value from a register. */ +#define ALT_CAN_MSGIF_IF2DA_DATA1_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_CAN_MSGIF_IF2DA_DATA1 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2DA_DATA1_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Data 2 - Data2 + * + * 3rd data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2DA_DATA2 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA2_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2DA_DATA2 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA2_MSB 23 +/* The width in bits of the ALT_CAN_MSGIF_IF2DA_DATA2 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA2_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF2DA_DATA2 register field value. */ +#define ALT_CAN_MSGIF_IF2DA_DATA2_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2DA_DATA2 register field value. */ +#define ALT_CAN_MSGIF_IF2DA_DATA2_CLR_MSK 0xff00ffff +/* The reset value of the ALT_CAN_MSGIF_IF2DA_DATA2 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA2_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2DA_DATA2 field value from a register. */ +#define ALT_CAN_MSGIF_IF2DA_DATA2_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_CAN_MSGIF_IF2DA_DATA2 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2DA_DATA2_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Data 3 - Data3 + * + * 4th data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2DA_DATA3 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA3_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2DA_DATA3 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA3_MSB 31 +/* The width in bits of the ALT_CAN_MSGIF_IF2DA_DATA3 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA3_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF2DA_DATA3 register field value. */ +#define ALT_CAN_MSGIF_IF2DA_DATA3_SET_MSK 0xff000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2DA_DATA3 register field value. */ +#define ALT_CAN_MSGIF_IF2DA_DATA3_CLR_MSK 0x00ffffff +/* The reset value of the ALT_CAN_MSGIF_IF2DA_DATA3 register field. */ +#define ALT_CAN_MSGIF_IF2DA_DATA3_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2DA_DATA3 field value from a register. */ +#define ALT_CAN_MSGIF_IF2DA_DATA3_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_CAN_MSGIF_IF2DA_DATA3 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2DA_DATA3_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF2DA. + */ +struct ALT_CAN_MSGIF_IF2DA_s +{ + uint32_t Data0 : 8; /* Data 0 */ + uint32_t Data1 : 8; /* Data 1 */ + uint32_t Data2 : 8; /* Data 2 */ + uint32_t Data3 : 8; /* Data 3 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF2DA. */ +typedef volatile struct ALT_CAN_MSGIF_IF2DA_s ALT_CAN_MSGIF_IF2DA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF2DA register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF2DA_OFST 0x30 +/* The address of the ALT_CAN_MSGIF_IF2DA register. */ +#define ALT_CAN_MSGIF_IF2DA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF2DA_OFST)) + +/* + * Register : IF2 Data B Register - IF2DB + * + * The data bytes of CAN messages are stored in the IF1/2 registers in the + * following order. In a CAN Data Frame, Data(0) is the first, Data(7) is the last + * byte to be transmitted or received. In CAN's serial bit stream, the MSB of each + * byte will be transmitted first. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Data 0 + * [15:8] | RW | 0x0 | Data 1 + * [23:16] | RW | 0x0 | Data 2 + * [31:24] | RW | 0x0 | Data 3 + * + */ +/* + * Field : Data 0 - Data4 + * + * 5th data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2DB_DATA4 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2DB_DATA4 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA4_MSB 7 +/* The width in bits of the ALT_CAN_MSGIF_IF2DB_DATA4 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA4_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF2DB_DATA4 register field value. */ +#define ALT_CAN_MSGIF_IF2DB_DATA4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_CAN_MSGIF_IF2DB_DATA4 register field value. */ +#define ALT_CAN_MSGIF_IF2DB_DATA4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_CAN_MSGIF_IF2DB_DATA4 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA4_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2DB_DATA4 field value from a register. */ +#define ALT_CAN_MSGIF_IF2DB_DATA4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_CAN_MSGIF_IF2DB_DATA4 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2DB_DATA4_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Data 1 - Data5 + * + * 6th data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2DB_DATA5 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA5_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2DB_DATA5 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA5_MSB 15 +/* The width in bits of the ALT_CAN_MSGIF_IF2DB_DATA5 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA5_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF2DB_DATA5 register field value. */ +#define ALT_CAN_MSGIF_IF2DB_DATA5_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_CAN_MSGIF_IF2DB_DATA5 register field value. */ +#define ALT_CAN_MSGIF_IF2DB_DATA5_CLR_MSK 0xffff00ff +/* The reset value of the ALT_CAN_MSGIF_IF2DB_DATA5 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA5_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2DB_DATA5 field value from a register. */ +#define ALT_CAN_MSGIF_IF2DB_DATA5_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_CAN_MSGIF_IF2DB_DATA5 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2DB_DATA5_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Data 2 - Data6 + * + * 7th data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2DB_DATA6 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA6_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2DB_DATA6 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA6_MSB 23 +/* The width in bits of the ALT_CAN_MSGIF_IF2DB_DATA6 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA6_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF2DB_DATA6 register field value. */ +#define ALT_CAN_MSGIF_IF2DB_DATA6_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2DB_DATA6 register field value. */ +#define ALT_CAN_MSGIF_IF2DB_DATA6_CLR_MSK 0xff00ffff +/* The reset value of the ALT_CAN_MSGIF_IF2DB_DATA6 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA6_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2DB_DATA6 field value from a register. */ +#define ALT_CAN_MSGIF_IF2DB_DATA6_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_CAN_MSGIF_IF2DB_DATA6 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2DB_DATA6_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Data 3 - Data7 + * + * 8th data byte of a CAN Data Frame + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF2DB_DATA7 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA7_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF2DB_DATA7 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA7_MSB 31 +/* The width in bits of the ALT_CAN_MSGIF_IF2DB_DATA7 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA7_WIDTH 8 +/* The mask used to set the ALT_CAN_MSGIF_IF2DB_DATA7 register field value. */ +#define ALT_CAN_MSGIF_IF2DB_DATA7_SET_MSK 0xff000000 +/* The mask used to clear the ALT_CAN_MSGIF_IF2DB_DATA7 register field value. */ +#define ALT_CAN_MSGIF_IF2DB_DATA7_CLR_MSK 0x00ffffff +/* The reset value of the ALT_CAN_MSGIF_IF2DB_DATA7 register field. */ +#define ALT_CAN_MSGIF_IF2DB_DATA7_RESET 0x0 +/* Extracts the ALT_CAN_MSGIF_IF2DB_DATA7 field value from a register. */ +#define ALT_CAN_MSGIF_IF2DB_DATA7_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_CAN_MSGIF_IF2DB_DATA7 register field value suitable for setting the register. */ +#define ALT_CAN_MSGIF_IF2DB_DATA7_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CAN_MSGIF_IF2DB. + */ +struct ALT_CAN_MSGIF_IF2DB_s +{ + uint32_t Data4 : 8; /* Data 0 */ + uint32_t Data5 : 8; /* Data 1 */ + uint32_t Data6 : 8; /* Data 2 */ + uint32_t Data7 : 8; /* Data 3 */ +}; + +/* The typedef declaration for register ALT_CAN_MSGIF_IF2DB. */ +typedef volatile struct ALT_CAN_MSGIF_IF2DB_s ALT_CAN_MSGIF_IF2DB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CAN_MSGIF_IF2DB register from the beginning of the component. */ +#define ALT_CAN_MSGIF_IF2DB_OFST 0x34 +/* The address of the ALT_CAN_MSGIF_IF2DB register. */ +#define ALT_CAN_MSGIF_IF2DB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF2DB_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CAN_MSGIF. + */ +struct ALT_CAN_MSGIF_s +{ + volatile ALT_CAN_MSGIF_IF1CMR_t IF1CMR; /* ALT_CAN_MSGIF_IF1CMR */ + volatile ALT_CAN_MSGIF_IF1MSK_t IF1MSK; /* ALT_CAN_MSGIF_IF1MSK */ + volatile ALT_CAN_MSGIF_IF1ARB_t IF1ARB; /* ALT_CAN_MSGIF_IF1ARB */ + volatile ALT_CAN_MSGIF_IF1MCTR_t IF1MCTR; /* ALT_CAN_MSGIF_IF1MCTR */ + volatile ALT_CAN_MSGIF_IF1DA_t IF1DA; /* ALT_CAN_MSGIF_IF1DA */ + volatile ALT_CAN_MSGIF_IF1DB_t IF1DB; /* ALT_CAN_MSGIF_IF1DB */ + volatile uint32_t _pad_0x18_0x1f[2]; /* *UNDEFINED* */ + volatile ALT_CAN_MSGIF_IF2CMR_t IF2CMR; /* ALT_CAN_MSGIF_IF2CMR */ + volatile ALT_CAN_MSGIF_IF2MSK_t IF2MSK; /* ALT_CAN_MSGIF_IF2MSK */ + volatile ALT_CAN_MSGIF_IF2ARB_t IF2ARB; /* ALT_CAN_MSGIF_IF2ARB */ + volatile ALT_CAN_MSGIF_IF2MCTR_t IF2MCTR; /* ALT_CAN_MSGIF_IF2MCTR */ + volatile ALT_CAN_MSGIF_IF2DA_t IF2DA; /* ALT_CAN_MSGIF_IF2DA */ + volatile ALT_CAN_MSGIF_IF2DB_t IF2DB; /* ALT_CAN_MSGIF_IF2DB */ +}; + +/* The typedef declaration for register group ALT_CAN_MSGIF. */ +typedef volatile struct ALT_CAN_MSGIF_s ALT_CAN_MSGIF_t; +/* The struct declaration for the raw register contents of register group ALT_CAN_MSGIF. */ +struct ALT_CAN_MSGIF_raw_s +{ + volatile uint32_t IF1CMR; /* ALT_CAN_MSGIF_IF1CMR */ + volatile uint32_t IF1MSK; /* ALT_CAN_MSGIF_IF1MSK */ + volatile uint32_t IF1ARB; /* ALT_CAN_MSGIF_IF1ARB */ + volatile uint32_t IF1MCTR; /* ALT_CAN_MSGIF_IF1MCTR */ + volatile uint32_t IF1DA; /* ALT_CAN_MSGIF_IF1DA */ + volatile uint32_t IF1DB; /* ALT_CAN_MSGIF_IF1DB */ + volatile uint32_t _pad_0x18_0x1f[2]; /* *UNDEFINED* */ + volatile uint32_t IF2CMR; /* ALT_CAN_MSGIF_IF2CMR */ + volatile uint32_t IF2MSK; /* ALT_CAN_MSGIF_IF2MSK */ + volatile uint32_t IF2ARB; /* ALT_CAN_MSGIF_IF2ARB */ + volatile uint32_t IF2MCTR; /* ALT_CAN_MSGIF_IF2MCTR */ + volatile uint32_t IF2DA; /* ALT_CAN_MSGIF_IF2DA */ + volatile uint32_t IF2DB; /* ALT_CAN_MSGIF_IF2DB */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CAN_MSGIF. */ +typedef volatile struct ALT_CAN_MSGIF_raw_s ALT_CAN_MSGIF_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CAN. + */ +struct ALT_CAN_s +{ + volatile ALT_CAN_PROTO_t protogrp; /* ALT_CAN_PROTO */ + volatile uint32_t _pad_0x28_0x83[23]; /* *UNDEFINED* */ + volatile ALT_CAN_MSGHAND_t msghandgrp; /* ALT_CAN_MSGHAND */ + volatile uint32_t _pad_0xd4_0xff[11]; /* *UNDEFINED* */ + volatile ALT_CAN_MSGIF_t msgifgrp; /* ALT_CAN_MSGIF */ + volatile uint32_t _pad_0x138_0x200[50]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_CAN. */ +typedef volatile struct ALT_CAN_s ALT_CAN_t; +/* The struct declaration for the raw register contents of register group ALT_CAN. */ +struct ALT_CAN_raw_s +{ + volatile ALT_CAN_PROTO_raw_t protogrp; /* ALT_CAN_PROTO */ + volatile uint32_t _pad_0x28_0x83[23]; /* *UNDEFINED* */ + volatile ALT_CAN_MSGHAND_raw_t msghandgrp; /* ALT_CAN_MSGHAND */ + volatile uint32_t _pad_0xd4_0xff[11]; /* *UNDEFINED* */ + volatile ALT_CAN_MSGIF_raw_t msgifgrp; /* ALT_CAN_MSGIF */ + volatile uint32_t _pad_0x138_0x200[50]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CAN. */ +typedef volatile struct ALT_CAN_raw_s ALT_CAN_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_CAN_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_clkmgr.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_clkmgr.h new file mode 100644 index 000000000..9c1065081 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_clkmgr.h @@ -0,0 +1,6464 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_CLKMGR */ + +#ifndef __ALTERA_ALT_CLKMGR_H__ +#define __ALTERA_ALT_CLKMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : Clock Manager Module - ALT_CLKMGR + * Clock Manager Module + * + * Registers in the Clock Manager module + * + */ +/* + * Register : Control Register - ctrl + * + * Contains fields that control the entire Clock Manager. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x1 | Safe Mode + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x1 | Enable SafeMode on Warm Reset + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Safe Mode - safemode + * + * When set the Clock Manager is in Safe Mode. + * + * In Safe Mode Clock Manager register settings defining clock behavior are ignored + * and clocks are set to a Safe Mode state.In Safe Mode all clocks with the + * optional exception of debug clocks, are directly generated from the EOSC1 clock + * input, all PLLs are bypassed, all programmable dividers are set to 1 and all + * clocks are enabled. + * + * This bit should only be cleared when clocks have been correctly configured + * + * This field is set on a cold reset and optionally on a warm reset and may not be + * set by SW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_MSB 0 +/* The width in bits of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_CTL_SAFEMOD register field value. */ +#define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_CTL_SAFEMOD register field value. */ +#define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_CTL_SAFEMOD register field. */ +#define ALT_CLKMGR_CTL_SAFEMOD_RESET 0x1 +/* Extracts the ALT_CLKMGR_CTL_SAFEMOD field value from a register. */ +#define ALT_CLKMGR_CTL_SAFEMOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_CTL_SAFEMOD register field value suitable for setting the register. */ +#define ALT_CLKMGR_CTL_SAFEMOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable SafeMode on Warm Reset - ensfmdwr + * + * When set the Clock Manager will respond to a Safe Mode request from the Reset + * Manager on a warm reset by setting the Safe Mode bit. When clear the clock + * manager will not set the the Safe Mode bit on a warm reset This bit is cleared + * on a cold reset. Warm reset has no affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_MSB 2 +/* The width in bits of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_CTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_CTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_RESET 0x1 +/* Extracts the ALT_CLKMGR_CTL_ENSFMDWR field value from a register. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_CTL_ENSFMDWR register field value suitable for setting the register. */ +#define ALT_CLKMGR_CTL_ENSFMDWR_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_CTL. + */ +struct ALT_CLKMGR_CTL_s +{ + uint32_t safemode : 1; /* Safe Mode */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t ensfmdwr : 1; /* Enable SafeMode on Warm Reset */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_CTL. */ +typedef volatile struct ALT_CLKMGR_CTL_s ALT_CLKMGR_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_CTL register from the beginning of the component. */ +#define ALT_CLKMGR_CTL_OFST 0x0 + +/* + * Register : PLL Bypass Register - bypass + * + * Contains fields that control bypassing each PLL. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | RW | 0x1 | Main PLL Bypass + * [1] | RW | 0x1 | SDRAM PLL Bypass + * [2] | RW | 0x0 | SDRAM PLL Bypass Source + * [3] | RW | 0x1 | Peripheral PLL Bypass + * [4] | RW | 0x0 | Peripheral PLL Bypass Source + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Main PLL Bypass - mainpll + * + * When set, causes the Main PLL VCO and counters to be bypassed so that all clocks + * generated by the Main PLL are directly driven from the Main PLL input clock. The + * bypass source for Main PLL is the external eosc1_clk. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_MSB 0 +/* The width in bits of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_MAINPLL register field value. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_BYPASS_MAINPLL register field value. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_RESET 0x1 +/* Extracts the ALT_CLKMGR_BYPASS_MAINPLL field value from a register. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_BYPASS_MAINPLL register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_MAINPLL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SDRAM PLL Bypass - sdrpll + * + * When set, causes the SDRAM PLL VCO and counters to be bypassed so that all + * clocks generated by the SDRAM PLL are directly driven from either eosc1_clk or + * the SDRAM PLL input clock. + * + * The bypass clock source for SDRAM PLL is determined by the SDRAM PLL Bypass + * Source Register bit. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_MSB 1 +/* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLL register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLL register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_RESET 0x1 +/* Extracts the ALT_CLKMGR_BYPASS_SDRPLL field value from a register. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_BYPASS_SDRPLL register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_SDRPLL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM PLL Bypass Source - sdrpllsrc + * + * This bit defines the bypass source forSDRAM PLL. + * + * When changing fields that affect VCO lock the PLL must be bypassed and this bit + * must be set to OSC1_CLK. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------- + * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1 + * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC + * + * Select EOSC1 + */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC + * + * Select PLL Input Mux + */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_MSB 2 +/* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_BYPASS_SDRPLLSRC field value from a register. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_BYPASS_SDRPLLSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Peripheral PLL Bypass - perpll + * + * When set, causes the Peripheral PLL VCO and counters to be bypassed so that all + * clocks generated by the Peripheral PLL are directly driven from either eosc1_clk + * or the Peripheral PLL input clock. + * + * The bypass clock source for Peripheral PLL is determined by the Peripheral PLL + * Bypass Source Register bit. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_MSB 3 +/* The width in bits of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_PERPLL register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLL register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_BYPASS_PERPLL register field. */ +#define ALT_CLKMGR_BYPASS_PERPLL_RESET 0x1 +/* Extracts the ALT_CLKMGR_BYPASS_PERPLL field value from a register. */ +#define ALT_CLKMGR_BYPASS_PERPLL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_BYPASS_PERPLL register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_PERPLL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Peripheral PLL Bypass Source - perpllsrc + * + * This bit defines the bypass source forPeripheral PLL. + * + * When changing fields that affect VCO lock the PLL must be bypassed and this bit + * must be set to OSC1_CLK. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------- + * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1 + * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC + * + * Select EOSC1 + */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC + * + * Select PLL Input Mux + */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_MSB 4 +/* The width in bits of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_BYPASS_PERPLLSRC field value from a register. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_BYPASS_PERPLLSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_BYPASS. + */ +struct ALT_CLKMGR_BYPASS_s +{ + uint32_t mainpll : 1; /* Main PLL Bypass */ + uint32_t sdrpll : 1; /* SDRAM PLL Bypass */ + uint32_t sdrpllsrc : 1; /* SDRAM PLL Bypass Source */ + uint32_t perpll : 1; /* Peripheral PLL Bypass */ + uint32_t perpllsrc : 1; /* Peripheral PLL Bypass Source */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_BYPASS. */ +typedef volatile struct ALT_CLKMGR_BYPASS_s ALT_CLKMGR_BYPASS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_BYPASS register from the beginning of the component. */ +#define ALT_CLKMGR_BYPASS_OFST 0x4 + +/* + * Register : Interrupt Status Register - inter + * + * Contains fields that indicate the PLL lock status. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------------------- + * [0] | RW | 0x0 | Main PLL Achieved Lock + * [1] | RW | 0x0 | Peripheral PLL Achieved Lock + * [2] | RW | 0x0 | SDRAM PLL Achieved Lock + * [3] | RW | 0x0 | Main PLL Lost Lock + * [4] | RW | 0x0 | Peripheral PLL Lost Lock + * [5] | RW | 0x0 | SDRAM PLL Lost Lock + * [6] | R | Unknown | Main PLL Current Lock Status + * [7] | R | Unknown | Peripheral PLL Current Lock Status + * [8] | R | Unknown | SDRAM PLL Current Lock Status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Main PLL Achieved Lock - mainpllachieved + * + * If 1, the Main PLL has achieved lock at least once since this bit was cleared. + * If 0, the Main PLL has not achieved lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_MSB 0 +/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_MAINPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Peripheral PLL Achieved Lock - perpllachieved + * + * If 1, the Peripheral PLL has achieved lock at least once since this bit was + * cleared. If 0, the Peripheral PLL has not achieved lock since this bit was + * cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_MSB 1 +/* The width in bits of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_PERPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_INTER_PERPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM PLL Achieved Lock - sdrpllachieved + * + * If 1, the SDRAM PLL has achieved lock at least once since this bit was cleared. + * If 0, the SDRAM PLL has not achieved lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_MSB 2 +/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_SDRPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Main PLL Lost Lock - mainplllost + * + * If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0, + * the Main PLL has not lost lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_MSB 3 +/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_MAINPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_INTER_MAINPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Peripheral PLL Lost Lock - perplllost + * + * If 1, the Peripheral PLL has lost lock at least once since this bit was cleared. + * If 0, the Peripheral PLL has not lost lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_MSB 4 +/* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_PERPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_INTER_PERPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDRAM PLL Lost Lock - sdrplllost + * + * If 1, the SDRAM PLL has lost lock at least once since this bit was cleared. If + * 0, the SDRAM PLL has not lost lock since this bit was cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_MSB 5 +/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_SDRPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_INTER_SDRPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Main PLL Current Lock Status - mainplllocked + * + * If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not + * locked. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_MSB 6 +/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field is UNKNOWN. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_MAINPLLLOCKED field value from a register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CLKMGR_INTER_MAINPLLLOCKED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Peripheral PLL Current Lock Status - perplllocked + * + * If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is + * currently not locked. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_MSB 7 +/* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CLKMGR_INTER_PERPLLLOCKED register field is UNKNOWN. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_PERPLLLOCKED field value from a register. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CLKMGR_INTER_PERPLLLOCKED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : SDRAM PLL Current Lock Status - sdrplllocked + * + * If 1, the SDRAM PLL is currently locked. If 0, the SDRAM PLL is currently not + * locked. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_MSB 8 +/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field is UNKNOWN. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTER_SDRPLLLOCKED field value from a register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CLKMGR_INTER_SDRPLLLOCKED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_INTER. + */ +struct ALT_CLKMGR_INTER_s +{ + uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock */ + uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock */ + uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock */ + uint32_t mainplllost : 1; /* Main PLL Lost Lock */ + uint32_t perplllost : 1; /* Peripheral PLL Lost Lock */ + uint32_t sdrplllost : 1; /* SDRAM PLL Lost Lock */ + const uint32_t mainplllocked : 1; /* Main PLL Current Lock Status */ + const uint32_t perplllocked : 1; /* Peripheral PLL Current Lock Status */ + const uint32_t sdrplllocked : 1; /* SDRAM PLL Current Lock Status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_INTER. */ +typedef volatile struct ALT_CLKMGR_INTER_s ALT_CLKMGR_INTER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_INTER register from the beginning of the component. */ +#define ALT_CLKMGR_INTER_OFST 0x8 + +/* + * Register : Interrupt Enable Register - intren + * + * Contain fields that enable the interrupt. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable + * [1] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable + * [2] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable + * [3] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable + * [4] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable + * [5] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Main PLL Achieved Lock Interrupt Enable - mainpllachieved + * + * When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the Main PLL achieved lock bit is not ORed into + * the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0 +/* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_MAINPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Peripheral PLL Achieved Lock Interrupt Enable - perpllachieved + * + * When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock + * Manager interrupt output. When set to 0 the Peripheral PLL achieved lock bit is + * not ORed into the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1 +/* The width in bits of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_PERPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrpllachieved + * + * When set to 1, the SDRAM PLL achieved lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the SDRAM PLL achieved lock bit is not ORed + * into the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_MSB 2 +/* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_SDRPLLACHIEVED field value from a register. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Main PLL Achieved Lock Interrupt Enable - mainplllost + * + * When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the Main PLL lost lock bit is not ORed into the + * Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_MSB 3 +/* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_MAINPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_INTREN_MAINPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Peripheral PLL Achieved Lock Interrupt Enable - perplllost + * + * When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the Peripheral PLL lost lock bit is not ORed + * into the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_MSB 4 +/* The width in bits of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_PERPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_INTREN_PERPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrplllost + * + * When set to 1, the SDRAM PLL lost lock bit is ORed into the Clock Manager + * interrupt output. When set to 0 the SDRAM PLL lost lock bit is not ORed into + * the Clock Manager interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_MSB 5 +/* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_RESET 0x0 +/* Extracts the ALT_CLKMGR_INTREN_SDRPLLLOST field value from a register. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_INTREN_SDRPLLLOST register field value suitable for setting the register. */ +#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_INTREN. + */ +struct ALT_CLKMGR_INTREN_s +{ + uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock Interrupt Enable */ + uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */ + uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */ + uint32_t mainplllost : 1; /* Main PLL Achieved Lock Interrupt Enable */ + uint32_t perplllost : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */ + uint32_t sdrplllost : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_INTREN. */ +typedef volatile struct ALT_CLKMGR_INTREN_s ALT_CLKMGR_INTREN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_INTREN register from the beginning of the component. */ +#define ALT_CLKMGR_INTREN_OFST 0xc + +/* + * Register : Debug clock Control Register - dbctrl + * + * Contains fields that control the debug clocks. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | RW | 0x1 | Debug Clocks Stay on EOSC1_CLK + * [1] | RW | 0x1 | Debug Clocks Enable Safe Mode + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug Clocks Stay on EOSC1_CLK - stayosc1 + * + * When this bit is set the debug root clock (Main PLL C2 output) will always be + * bypassed to the EOSC1_clk independent of any other clock manager settings. + * When clear the debug source will be a function of register settings in the clock + * manager. Clocks affected by this bit are dbg_at_clk, dbg_clk, dbg_trace_clk, + * and dbg_timer_clk. + * + * The reset value for this bit is applied on a cold reset. Warm reset has no + * affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_MSB 0 +/* The width in bits of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_RESET 0x1 +/* Extracts the ALT_CLKMGR_DBCTL_STAYOSC1 field value from a register. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_DBCTL_STAYOSC1 register field value suitable for setting the register. */ +#define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Debug Clocks Enable Safe Mode - ensfmdwr + * + * When this bit is set the debug clocks will be affected by the assertion of Safe + * Mode on a warm reset if Stay OSC1 is not set. + * + * When this bit is clear the debug clocks will not be affected by the assertion of + * Safe Mode on a warm reset. + * + * If Debug Clocks are in Safe Mode they are taken out of Safe Mode when the Safe + * Mode bit is cleared independent of this bit.The reset value of this bit is + * applied on a cold reset; warm reset has no affect on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB 1 +/* The width in bits of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET 0x1 +/* Extracts the ALT_CLKMGR_DBCTL_ENSFMDWR field value from a register. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_DBCTL_ENSFMDWR register field value suitable for setting the register. */ +#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_DBCTL. + */ +struct ALT_CLKMGR_DBCTL_s +{ + uint32_t stayosc1 : 1; /* Debug Clocks Stay on EOSC1_CLK */ + uint32_t ensfmdwr : 1; /* Debug Clocks Enable Safe Mode */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_DBCTL. */ +typedef volatile struct ALT_CLKMGR_DBCTL_s ALT_CLKMGR_DBCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_DBCTL register from the beginning of the component. */ +#define ALT_CLKMGR_DBCTL_OFST 0x10 + +/* + * Register : Status Register - stat + * + * Provides status of Hardware Managed Clock transition State Machine. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | HW Managed Clocks BUSY + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : HW Managed Clocks BUSY - busy + * + * This read only bit indicates that the Hardware Managed clock's state machine is + * active. If the state machine is active, then the clocks are in transition. + * Software should poll this bit after changing the source of internal clocks when + * writing to the BYPASS, CTRL or DBCTRL registers. Immediately following writes + * to any of these registers, SW should wait until this bit is IDLE before + * proceeding with any other register writes in the Clock Manager. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------- + * ALT_CLKMGR_STAT_BUSY_E_IDLE | 0x0 | Clocks stable + * ALT_CLKMGR_STAT_BUSY_E_BUSY | 0x1 | Clocks in transition + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_STAT_BUSY + * + * Clocks stable + */ +#define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_STAT_BUSY + * + * Clocks in transition + */ +#define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_MSB 0 +/* The width in bits of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_STAT_BUSY register field value. */ +#define ALT_CLKMGR_STAT_BUSY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_STAT_BUSY register field value. */ +#define ALT_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_STAT_BUSY register field. */ +#define ALT_CLKMGR_STAT_BUSY_RESET 0x0 +/* Extracts the ALT_CLKMGR_STAT_BUSY field value from a register. */ +#define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_STAT_BUSY register field value suitable for setting the register. */ +#define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_STAT. + */ +struct ALT_CLKMGR_STAT_s +{ + const uint32_t busy : 1; /* HW Managed Clocks BUSY */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_STAT. */ +typedef volatile struct ALT_CLKMGR_STAT_s ALT_CLKMGR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_STAT_OFST 0x14 + +/* + * Register Group : Main PLL Group - ALT_CLKMGR_MAINPLL + * Main PLL Group + * + * Contains registers with settings for the Main PLL. + * + */ +/* + * Register : Main PLL VCO Control Register - vco + * + * Contains settings that control the Main PLL VCO. The VCO output frequency is the + * input frequency multiplied by the numerator (M+1) and divided by the denominator + * (N+1). The VCO input clock source is always eosc1_clk. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [0] | RW | 0x1 | BG PWRDN + * [1] | RW | 0x0 | Enable + * [2] | RW | 0x1 | Power down + * [15:3] | RW | 0x1 | Numerator (M) + * [21:16] | RW | 0x1 | Denominator (N) + * [23:22] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | All Output Counter Reset + * [30:25] | RW | 0x0 | Output Counter Reset + * [31] | RW | 0x1 | External Regulator Input Select + * + */ +/* + * Field : BG PWRDN - bgpwrdn + * + * If '1', powers down bandgap. If '0', bandgap is not power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable - en + * + * If '1', VCO is enabled. If '0', VCO is in reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_EN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_EN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Power down - pwrdn + * + * If '1', power down analog circuitry. If '0', analog circuitry not powered down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_MSB 2 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_PWRDN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Numerator (M) - numer + * + * Numerator in VCO output frequency equation. For incremental frequency change, if + * the new value lead to less than 20% of the frequency change, this value can be + * changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_MSB 15 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_WIDTH 13 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK 0x0000fff8 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK 0xffff0007 +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_NUMER field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_NUMER register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) + +/* + * Field : Denominator (N) - denom + * + * Denominator in VCO output frequency equation. For incremental frequency change, + * if the new value lead to less than 20% of the frequency change, this value can + * be changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_MSB 21 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_DENOM field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_DENOM register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : All Output Counter Reset - outresetall + * + * Before releasing Bypass, All Output Counter Reset must be set and cleared by + * software for correct clock operation. + * + * If '1', Reset phase multiplexer and all output counter state. So that after the + * assertion all the clocks output are start from rising edge align. + * + * If '0', phase multiplexer and output counter state not reset and no change to + * the phase of the clock outputs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_MSB 24 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Output Counter Reset - outreset + * + * Resets the individual PLL output counter. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. + * + * If set to '1', reset output divider, no clock output from counter. + * + * If set to '0', counter is not reset. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_MSB 30 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET_MSK 0x7e000000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK 0x81ffffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRST field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) + +/* + * Field : External Regulator Input Select - regextsel + * + * If set to '1', the external regulator is selected for the PLL. + * + * If set to '0', the internal regulator is slected. + * + * It is strongly recommended to select the external regulator while the PLL is not + * enabled (in reset), and then disable the external regulater once the PLL + * becomes enabled. Software should simulateously update the 'Enable' bit and the + * 'External Regulator Input Select' in the same write access to the VCO register. + * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be + * set, and vice versa. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_MSB 31 +/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL field value from a register. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_VCO. + */ +struct ALT_CLKMGR_MAINPLL_VCO_s +{ + uint32_t bgpwrdn : 1; /* BG PWRDN */ + uint32_t en : 1; /* Enable */ + uint32_t pwrdn : 1; /* Power down */ + uint32_t numer : 13; /* Numerator (M) */ + uint32_t denom : 6; /* Denominator (N) */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t outresetall : 1; /* All Output Counter Reset */ + uint32_t outreset : 6; /* Output Counter Reset */ + uint32_t regextsel : 1; /* External Regulator Input Select */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_VCO. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_VCO_s ALT_CLKMGR_MAINPLL_VCO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_VCO register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_VCO_OFST 0x0 + +/* + * Register : Main PLL VCO Advanced Control Register - misc + * + * Contains VCO control signals and other PLL control signals need to be + * controllable through register. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled + * [12:1] | RW | 0x1 | Loop Bandwidth Adjust + * [13] | RW | 0x0 | Fast Locking Enable + * [14] | RW | 0x1 | Saturation Enable + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Loop Bandwidth Adjust Enabled - bwadjen + * + * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth + * Adjust field. + * + * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 + * value of the VCO Control Register. The M divided by 2 is the upper 12 bits + * (12:1) of the M field in the VCO register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJEN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Loop Bandwidth Adjust - bwadj + * + * Provides Loop Bandwidth Adjust value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_MSB 12 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET_MSK 0x00001ffe +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_CLR_MSK 0xffffe001 +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJ field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) + +/* + * Field : Fast Locking Enable - fasten + * + * Enables fast locking circuit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_MSB 13 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_FASTEN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Saturation Enable - saten + * + * Enables saturation behavior. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_MSB 14 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_MISC_SATEN field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CLKMGR_MAINPLL_MISC_SATEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MISC. + */ +struct ALT_CLKMGR_MAINPLL_MISC_s +{ + uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ + uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ + uint32_t fasten : 1; /* Fast Locking Enable */ + uint32_t saten : 1; /* Saturation Enable */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MISC. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MISC_s ALT_CLKMGR_MAINPLL_MISC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MISC register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MISC_OFST 0x4 + +/* + * Register : Main PLL C0 Control Register for Clock mpu_clk - mpuclk + * + * Contains settings that control clock mpu_clk generated from the C0 output of the + * Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x0 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO/2 frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. + */ +struct ALT_CLKMGR_MAINPLL_MPUCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MPUCLK_s ALT_CLKMGR_MAINPLL_MPUCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MPUCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x8 + +/* + * Register : Main PLL C1 Control Register for Clock main_clk - mainclk + * + * Contains settings that control clock main_clk generated from the C1 output of + * the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x0 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO/4 frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. + */ +struct ALT_CLKMGR_MAINPLL_MAINCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINCLK_s ALT_CLKMGR_MAINPLL_MAINCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_OFST 0xc + +/* + * Register : Main PLL C2 Control Register for Clock dbg_base_clk - dbgatclk + * + * Contains settings that control clock dbg_base_clk generated from the C2 output + * of the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x0 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO/4 frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. + */ +struct ALT_CLKMGR_MAINPLL_DBGATCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_DBGATCLK_s ALT_CLKMGR_MAINPLL_DBGATCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_DBGATCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_OFST 0x10 + +/* + * Register : Main PLL C3 Control Register for Clock main_qspi_clk - mainqspiclk + * + * Contains settings that control clock main_qspi_clk generated from the C3 output + * of the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x3 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_RESET 0x3 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. + */ +struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s ALT_CLKMGR_MAINPLL_MAINQSPICLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST 0x14 + +/* + * Register : Main PLL C4 Control Register for Clock main_nand_sdmmc_clk - mainnandsdmmcclk + * + * Contains settings that control clock main_nand_sdmmc_clk generated from the C4 + * output of the Main PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x3 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_RESET 0x3 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. + */ +struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST 0x18 + +/* + * Register : Main PLL C5 Control Register for Clock cfg_s2f_user0_clk - cfgs2fuser0clk + * + * Contains settings that control clock cfg_s2f_user0_clk generated from the C5 + * output of the Main PLL. + * + * Qsys and user documenation refer to cfg_s2f_user0_clk as cfg_h2f_user0_clk. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0xf | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_RESET 0xf +/* Extracts the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT field value from a register. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. + */ +struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST 0x1c + +/* + * Register : Enable Register - en + * + * Contains fields that control clock enables for clocks derived from the Main PLL. + * + * 1: The clock is enabled. + * + * 0: The clock is disabled. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | l4_main_clk Enable + * [1] | RW | 0x1 | l3_mp_clk Enable + * [2] | RW | 0x1 | l4_mp_clk Enable + * [3] | RW | 0x1 | l4_sp_clk Enable + * [4] | RW | 0x1 | dbg_at_clk Enable + * [5] | RW | 0x1 | dbg_clk Enable + * [6] | RW | 0x1 | dbg_trace_clk Enable + * [7] | RW | 0x1 | dbg_timer_clk Enable + * [8] | RW | 0x1 | cfg_clk Enable + * [9] | RW | 0x1 | s2f_user0_clk Enable + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : l4_main_clk Enable - l4mainclk + * + * Enables clock l4_main_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : l3_mp_clk Enable - l3mpclk + * + * Enables clock l3_mp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L3MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : l4_mp_clk Enable - l4mpclk + * + * Enables clock l4_mp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : l4_sp_clk Enable - l4spclk + * + * Enables clock l4_sp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4SPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : dbg_at_clk Enable - dbgatclk + * + * Enables clock dbg_at_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGATCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : dbg_clk Enable - dbgclk + * + * Enables clock dbg_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : dbg_trace_clk Enable - dbgtraceclk + * + * Enables clock dbg_trace_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : dbg_timer_clk Enable - dbgtimerclk + * + * Enables clock dbg_timer_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : cfg_clk Enable - cfgclk + * + * Enables clock cfg_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_CFGCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : s2f_user0_clk Enable - s2fuser0clk + * + * Enables clock s2f_user0_clk output. + * + * Qsys and user documenation refer to s2f_user0_clk as h2f_user0_clk. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9 +/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_EN. + */ +struct ALT_CLKMGR_MAINPLL_EN_s +{ + uint32_t l4mainclk : 1; /* l4_main_clk Enable */ + uint32_t l3mpclk : 1; /* l3_mp_clk Enable */ + uint32_t l4mpclk : 1; /* l4_mp_clk Enable */ + uint32_t l4spclk : 1; /* l4_sp_clk Enable */ + uint32_t dbgatclk : 1; /* dbg_at_clk Enable */ + uint32_t dbgclk : 1; /* dbg_clk Enable */ + uint32_t dbgtraceclk : 1; /* dbg_trace_clk Enable */ + uint32_t dbgtimerclk : 1; /* dbg_timer_clk Enable */ + uint32_t cfgclk : 1; /* cfg_clk Enable */ + uint32_t s2fuser0clk : 1; /* s2f_user0_clk Enable */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_EN. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_EN_s ALT_CLKMGR_MAINPLL_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_EN register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_EN_OFST 0x20 + +/* + * Register : Main Divide Register - maindiv + * + * Contains fields that control clock dividers for main clocks derived from the + * Main PLL + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [1:0] | RW | 0x0 | L3 MP Clock Divider + * [3:2] | RW | 0x0 | L3 SP Clock Divider + * [6:4] | RW | 0x0 | L4 MP Clock Divider + * [9:7] | RW | 0x0 | L4 SP Clock Divider + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : L3 MP Clock Divider - l3mpclk + * + * The l3_mp_clk is divided down from the l3_main_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 | 0x0 | Divide by 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 | 0x1 | Divide by 2 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK + * + * Divide by 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : L3 SP Clock Divider - l3spclk + * + * The l3_sp_clk is divided down from the l3_mp_clk by the value specified in this + * field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 | 0x0 | Divide by 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 | 0x1 | Divide by 2 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK + * + * Divide by 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : L4 MP Clock Divider - l4mpclk + * + * The l4_mp_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB 6 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK 0x00000070 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK 0xffffff8f +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(value) (((value) & 0x00000070) >> 4) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET(value) (((value) << 4) & 0x00000070) + +/* + * Field : L4 SP Clock Divider - l4spclk + * + * The l4_sp_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9 +/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f +/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7) +/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. + */ +struct ALT_CLKMGR_MAINPLL_MAINDIV_s +{ + uint32_t l3mpclk : 2; /* L3 MP Clock Divider */ + uint32_t l3spclk : 2; /* L3 SP Clock Divider */ + uint32_t l4mpclk : 3; /* L4 MP Clock Divider */ + uint32_t l4spclk : 3; /* L4 SP Clock Divider */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_MAINDIV_s ALT_CLKMGR_MAINPLL_MAINDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINDIV register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24 + +/* + * Register : Debug Divide Register - dbgdiv + * + * Contains fields that control clock dividers for debug clocks derived from the + * Main PLL + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [1:0] | RW | 0x0 | Debug AT Clock Divider + * [3:2] | RW | 0x1 | Debug Clock Divider + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug AT Clock Divider - dbgatclk + * + * The dbg_at_clk is divided down from the C2 output of the Main PLL by the value + * specified in this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 | 0x0 | Divide by 1 + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 | 0x1 | Divide by 2 + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 | 0x2 | Divide by 4 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK + * + * Divide by 1 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK + * + * Divide by 4 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK 0x00000003 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK 0xfffffffc +/* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Debug Clock Divider - dbgclk + * + * The dbg_clk is divided down from the dbg_at_clk by the value specified in this + * field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------ + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 | 0x1 | Divide by 2 + * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 | 0x2 | Divide by 4 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK + * + * Divide by 2 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK + * + * Divide by 4 + */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c +/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. + */ +struct ALT_CLKMGR_MAINPLL_DBGDIV_s +{ + uint32_t dbgatclk : 2; /* Debug AT Clock Divider */ + uint32_t dbgclk : 2; /* Debug Clock Divider */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_DBGDIV_s ALT_CLKMGR_MAINPLL_DBGDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_DBGDIV register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28 + +/* + * Register : Debug Trace Divide Register - tracediv + * + * Contains a field that controls the clock divider for the debug trace clock + * derived from the Main PLL + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [2:0] | RW | 0x0 | Debug Trace Clock Divider + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug Trace Clock Divider - traceclk + * + * The dbg_trace_clk is divided down from the C2 output of the Main PLL by the + * value specified in this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------- + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK + * + * Reserved + */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK 0x00000007 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value) (((value) << 0) & 0x00000007) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. + */ +struct ALT_CLKMGR_MAINPLL_TRACEDIV_s +{ + uint32_t traceclk : 3; /* Debug Trace Clock Divider */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_TRACEDIV_s ALT_CLKMGR_MAINPLL_TRACEDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_TRACEDIV register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST 0x2c + +/* + * Register : L4 MP SP APB Clock Source - l4src + * + * Contains fields that select the clock source for L4 MP and SP APB interconnect + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | l4_mp_clk Source + * [1] | RW | 0x0 | l4_sp_clk Source + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : l4_mp_clk Source - l4mp + * + * Selects the source for l4_mp_clk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------- + * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL | 0x0 | main_clk + * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL | 0x1 | periph_base_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP + * + * main_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP + * + * periph_base_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB 0 +/* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4MP field value from a register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : l4_sp_clk Source - l4sp + * + * Selects the source for l4_sp_clk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------- + * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL | 0x0 | main_clk + * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL | 0x1 | periph_base_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP + * + * main_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP + * + * periph_base_clk + */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB 1 +/* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4SP field value from a register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_L4SRC. + */ +struct ALT_CLKMGR_MAINPLL_L4SRC_s +{ + uint32_t l4mp : 1; /* l4_mp_clk Source */ + uint32_t l4sp : 1; /* l4_sp_clk Source */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_L4SRC. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_L4SRC_s ALT_CLKMGR_MAINPLL_L4SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_L4SRC register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_OFST 0x30 + +/* + * Register : Main PLL Output Counter Reset Ack Status Register - stat + * + * Contains Output Clock Counter Reset acknowledge status. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [5:0] | R | 0x0 | Output Counter Reset Acknowledge + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Output Counter Reset Acknowledge - outresetack + * + * These read only bits per PLL output indicate that the PLL has received the + * Output Reset Counter request and has gracefully stopped the respective PLL + * output clock. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------- + * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle + * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK + * + * Idle + */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK + * + * Output Counter Acknowledge received. + */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_MSB 5 +/* The width in bits of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f +/* The mask used to clear the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_RESET 0x0 +/* Extracts the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK field value from a register. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ +#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_MAINPLL_STAT. + */ +struct ALT_CLKMGR_MAINPLL_STAT_s +{ + const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_MAINPLL_STAT. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_STAT_s ALT_CLKMGR_MAINPLL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_MAINPLL_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_MAINPLL_STAT_OFST 0x34 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR_MAINPLL. + */ +struct ALT_CLKMGR_MAINPLL_s +{ + volatile ALT_CLKMGR_MAINPLL_VCO_t vco; /* ALT_CLKMGR_MAINPLL_VCO */ + volatile ALT_CLKMGR_MAINPLL_MISC_t misc; /* ALT_CLKMGR_MAINPLL_MISC */ + volatile ALT_CLKMGR_MAINPLL_MPUCLK_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */ + volatile ALT_CLKMGR_MAINPLL_MAINCLK_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */ + volatile ALT_CLKMGR_MAINPLL_DBGATCLK_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */ + volatile ALT_CLKMGR_MAINPLL_MAINQSPICLK_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */ + volatile ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */ + volatile ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */ + volatile ALT_CLKMGR_MAINPLL_EN_t en; /* ALT_CLKMGR_MAINPLL_EN */ + volatile ALT_CLKMGR_MAINPLL_MAINDIV_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */ + volatile ALT_CLKMGR_MAINPLL_DBGDIV_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */ + volatile ALT_CLKMGR_MAINPLL_TRACEDIV_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */ + volatile ALT_CLKMGR_MAINPLL_L4SRC_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */ + volatile ALT_CLKMGR_MAINPLL_STAT_t stat; /* ALT_CLKMGR_MAINPLL_STAT */ + volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_CLKMGR_MAINPLL. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_s ALT_CLKMGR_MAINPLL_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */ +struct ALT_CLKMGR_MAINPLL_raw_s +{ + volatile uint32_t vco; /* ALT_CLKMGR_MAINPLL_VCO */ + volatile uint32_t misc; /* ALT_CLKMGR_MAINPLL_MISC */ + volatile uint32_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */ + volatile uint32_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */ + volatile uint32_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */ + volatile uint32_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */ + volatile uint32_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */ + volatile uint32_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */ + volatile uint32_t en; /* ALT_CLKMGR_MAINPLL_EN */ + volatile uint32_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */ + volatile uint32_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */ + volatile uint32_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */ + volatile uint32_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */ + volatile uint32_t stat; /* ALT_CLKMGR_MAINPLL_STAT */ + volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */ +typedef volatile struct ALT_CLKMGR_MAINPLL_raw_s ALT_CLKMGR_MAINPLL_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Peripheral PLL Group - ALT_CLKMGR_PERPLL + * Peripheral PLL Group + * + * Contains registers with settings for the Peripheral PLL. + * + */ +/* + * Register : Peripheral PLL VCO Control Register - vco + * + * Contains settings that control the Peripheral PLL VCO. The VCO output frequency + * is the input frequency multiplied by the numerator (M+1) and divided by the + * denominator (N+1). + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [0] | RW | 0x1 | BG PWRDN + * [1] | RW | 0x0 | Enable + * [2] | RW | 0x1 | Power down + * [15:3] | RW | 0x1 | Numerator (M) + * [21:16] | RW | 0x1 | Denominator (N) + * [23:22] | RW | 0x0 | Clock Source + * [24] | RW | 0x0 | All Output Counter Reset + * [30:25] | RW | 0x0 | Output Counter Reset + * [31] | RW | 0x1 | External Regulator Input Select + * + */ +/* + * Field : BG PWRDN - bgpwrdn + * + * If '1', powers down bandgap. If '0', bandgap is not power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_MSB 0 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_BGPWRDN field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable - en + * + * If '1', VCO is enabled. If '0', VCO is in reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_MSB 1 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_EN field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_PERPLL_VCO_EN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Power down - pwrdn + * + * If '1', power down analog circuitry. If '0', analog circuitry not powered down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_MSB 2 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_PWRDN field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_PERPLL_VCO_PWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Numerator (M) - numer + * + * Numerator in VCO output frequency equation. For incremental frequency change, if + * the new value lead to less than 20% of the frequency change, this value can be + * changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_MSB 15 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_WIDTH 13 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK 0x0000fff8 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK 0xffff0007 +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_NUMER field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) +/* Produces a ALT_CLKMGR_PERPLL_VCO_NUMER register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) + +/* + * Field : Denominator (N) - denom + * + * Denominator in VCO output frequency equation. For incremental frequency change, + * if the new value lead to less than 20% of the frequency change, this value can + * be changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_MSB 21 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_DENOM field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_CLKMGR_PERPLL_VCO_DENOM register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : Clock Source - psrc + * + * Controls the VCO input clock source. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------- + * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 | 0x0 | eosc1_clk + * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 | 0x1 | eosc2_clk + * ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF | 0x2 | f2s_periph_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC + * + * eosc1_clk + */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC + * + * eosc2_clk + */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_MSB 23 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET_MSK 0x00c00000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK 0xff3fffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_PSRC field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_GET(value) (((value) & 0x00c00000) >> 22) +/* Produces a ALT_CLKMGR_PERPLL_VCO_PSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET(value) (((value) << 22) & 0x00c00000) + +/* + * Field : All Output Counter Reset - outresetall + * + * Before releasing Bypass, All Output Counter Reset must be set and cleared by + * software for correct clock operation. + * + * If '1', Reset phase multiplexer and all output counter state. So that after the + * assertion all the clocks output are start from rising edge align. + * + * If '0', phase multiplexer and output counter state not reset and no change to + * the phase of the clock outputs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_MSB 24 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Output Counter Reset - outreset + * + * Resets the individual PLL output counter. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. + * + * If set to '1', reset output divider, no clock output from counter. + * + * If set to '0', counter is not reset. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_MSB 30 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET_MSK 0x7e000000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK 0x81ffffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRST field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) +/* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRST register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) + +/* + * Field : External Regulator Input Select - regextsel + * + * If set to '1', the external regulator is selected for the PLL. + * + * If set to '0', the internal regulator is slected. + * + * It is strongly recommended to select the external regulator while the PLL is not + * enabled (in reset), and then disable the external regulater once the PLL + * becomes enabled. Software should simulateously update the 'Enable' bit and the + * 'External Regulator Input Select' in the same write access to the VCO register. + * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be + * set, and vice versa. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_MSB 31 +/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL field value from a register. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_VCO. + */ +struct ALT_CLKMGR_PERPLL_VCO_s +{ + uint32_t bgpwrdn : 1; /* BG PWRDN */ + uint32_t en : 1; /* Enable */ + uint32_t pwrdn : 1; /* Power down */ + uint32_t numer : 13; /* Numerator (M) */ + uint32_t denom : 6; /* Denominator (N) */ + uint32_t psrc : 2; /* Clock Source */ + uint32_t outresetall : 1; /* All Output Counter Reset */ + uint32_t outreset : 6; /* Output Counter Reset */ + uint32_t regextsel : 1; /* External Regulator Input Select */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_VCO. */ +typedef volatile struct ALT_CLKMGR_PERPLL_VCO_s ALT_CLKMGR_PERPLL_VCO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_VCO register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_VCO_OFST 0x0 + +/* + * Register : Peripheral PLL VCO Advanced Control Register - misc + * + * Contains VCO control signals and other PLL control signals need to be + * controllable through register. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled + * [12:1] | RW | 0x1 | Loop Bandwidth Adjust + * [13] | RW | 0x0 | Fast Locking Enable + * [14] | RW | 0x1 | Saturation Enable + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Loop Bandwidth Adjust Enabled - bwadjen + * + * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth + * Adjust field. + * + * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 + * value of the VCO Control Register. The M divided by 2 is the upper 12 bits + * (12:1) of the M field in the VCO register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_MSB 0 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJEN field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Loop Bandwidth Adjust - bwadj + * + * Provides Loop Bandwidth Adjust value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_MSB 12 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET_MSK 0x00001ffe +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_CLR_MSK 0xffffe001 +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJ field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) +/* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJ register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) + +/* + * Field : Fast Locking Enable - fasten + * + * Enables fast locking circuit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_MSB 13 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_FASTEN field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CLKMGR_PERPLL_MISC_FASTEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Saturation Enable - saten + * + * Enables saturation behavior. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_MSB 14 +/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_MISC_SATEN field value from a register. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CLKMGR_PERPLL_MISC_SATEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_MISC. + */ +struct ALT_CLKMGR_PERPLL_MISC_s +{ + uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ + uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ + uint32_t fasten : 1; /* Fast Locking Enable */ + uint32_t saten : 1; /* Saturation Enable */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_MISC. */ +typedef volatile struct ALT_CLKMGR_PERPLL_MISC_s ALT_CLKMGR_PERPLL_MISC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_MISC register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_MISC_OFST 0x4 + +/* + * Register : Peripheral PLL C0 Control Register for Clock emac0_clk - emac0clk + * + * Contains settings that control clock emac0_clk generated from the C0 output of + * the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. + */ +struct ALT_CLKMGR_PERPLL_EMAC0CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_EMAC0CLK_s ALT_CLKMGR_PERPLL_EMAC0CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_EMAC0CLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST 0x8 + +/* + * Register : Peripheral PLL C1 Control Register for Clock emac1_clk - emac1clk + * + * Contains settings that control clock emac1_clk generated from the C1 output of + * the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. + */ +struct ALT_CLKMGR_PERPLL_EMAC1CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_EMAC1CLK_s ALT_CLKMGR_PERPLL_EMAC1CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_EMAC1CLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_OFST 0xc + +/* + * Register : Peripheral PLL C2 Control Register for Clock periph_qspi_clk - perqspiclk + * + * Contains settings that control clock periph_qspi_clk generated from the C2 + * output of the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. + */ +struct ALT_CLKMGR_PERPLL_PERQSPICLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_PERQSPICLK_s ALT_CLKMGR_PERPLL_PERQSPICLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_PERQSPICLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_OFST 0x10 + +/* + * Register : Peripheral PLL C3 Control Register for Clock periph_nand_sdmmc_clk - pernandsdmmcclk + * + * Contains settings that control clock periph_nand_sdmmc_clk generated from the C3 + * output of the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. + */ +struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST 0x14 + +/* + * Register : Peripheral PLL C4 Control Register for Clock periph_base_clk - perbaseclk + * + * Contains settings that control clock periph_base_clk generated from the C4 + * output of the Peripheral PLL. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_PERBASECLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. + */ +struct ALT_CLKMGR_PERPLL_PERBASECLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_PERBASECLK_s ALT_CLKMGR_PERPLL_PERBASECLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_PERBASECLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_OFST 0x18 + +/* + * Register : Peripheral PLL C5 Control Register for Clock s2f_user1_clk - s2fuser1clk + * + * Contains settings that control clock s2f_user1_clk generated from the C5 output + * of the Peripheral PLL. + * + * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT field value from a register. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. + */ +struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. */ +typedef volatile struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s ALT_CLKMGR_PERPLL_S2FUSER1CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST 0x1c + +/* + * Register : Enable Register - en + * + * Contains fields that control clock enables for clocks derived from the + * Peripheral PLL + * + * 1: The clock is enabled. + * + * 0: The clock is disabled. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | emac0_clk Enable + * [1] | RW | 0x1 | emac1_clk Enable + * [2] | RW | 0x1 | usb_mp_clk Enable + * [3] | RW | 0x1 | spi_m_clk Enable + * [4] | RW | 0x1 | can0_clk Enable + * [5] | RW | 0x1 | can1_clk Enable + * [6] | RW | 0x1 | gpio_clk Enable + * [7] | RW | 0x1 | s2f_user1_clk Enable + * [8] | RW | 0x1 | sdmmc_clk Enable + * [9] | RW | 0x1 | nand_x_clk Enable + * [10] | RW | 0x1 | nand_clk Enable + * [11] | RW | 0x1 | qspi_clk Enable + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_clk Enable - emac0clk + * + * Enables clock emac0_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC0CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : emac1_clk Enable - emac1clk + * + * Enables clock emac1_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : usb_mp_clk Enable - usbclk + * + * Enables clock usb_mp_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_USBCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_PERPLL_EN_USBCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : spi_m_clk Enable - spimclk + * + * Enables clock spi_m_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_SPIMCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : can0_clk Enable - can0clk + * + * Enables clock can0_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef +/* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_CAN0CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : can1_clk Enable - can1clk + * + * Enables clock can1_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_CAN1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : gpio_clk Enable - gpioclk + * + * Enables clock gpio_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_GPIOCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : s2f_user1_clk Enable - s2fuser1clk + * + * Enables clock s2f_user1_clk output. + * + * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f +/* The reset value of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : sdmmc_clk Enable - sdmmcclk + * + * Enables clock sdmmc_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_SDMMCCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : nand_x_clk Enable - nandxclk + * + * Enables clock nand_x_clk output + * + * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and + * the nand_x_clk Enable should always be asserted before the nand_clk Enable is + * asserted. A brief delay is also required between switching the enables (8 * + * nand_clk period). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_NANDXCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : nand_clk Enable - nandclk + * + * Enables clock nand_clk output + * + * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and + * the nand_x_clk Enable should always be asserted before the nand_clk Enable is + * asserted. A brief delay is also required between switching the enables (8 * + * nand_clk period). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_NANDCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_CLKMGR_PERPLL_EN_NANDCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : qspi_clk Enable - qspiclk + * + * Enables clock qspi_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11 +/* The width in bits of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_EN_QSPICLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_CLKMGR_PERPLL_EN_QSPICLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_EN. + */ +struct ALT_CLKMGR_PERPLL_EN_s +{ + uint32_t emac0clk : 1; /* emac0_clk Enable */ + uint32_t emac1clk : 1; /* emac1_clk Enable */ + uint32_t usbclk : 1; /* usb_mp_clk Enable */ + uint32_t spimclk : 1; /* spi_m_clk Enable */ + uint32_t can0clk : 1; /* can0_clk Enable */ + uint32_t can1clk : 1; /* can1_clk Enable */ + uint32_t gpioclk : 1; /* gpio_clk Enable */ + uint32_t s2fuser1clk : 1; /* s2f_user1_clk Enable */ + uint32_t sdmmcclk : 1; /* sdmmc_clk Enable */ + uint32_t nandxclk : 1; /* nand_x_clk Enable */ + uint32_t nandclk : 1; /* nand_clk Enable */ + uint32_t qspiclk : 1; /* qspi_clk Enable */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_EN. */ +typedef volatile struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_EN register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_EN_OFST 0x20 + +/* + * Register : Divide Register - div + * + * Contains fields that control clock dividers for clocks derived from the + * Peripheral PLL + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [2:0] | RW | 0x0 | USB Clock Divider + * [5:3] | RW | 0x0 | SPI Master Clock Divider + * [8:6] | RW | 0x0 | CAN0 Clock Divider + * [11:9] | RW | 0x0 | CAN1 Clock Divider + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB Clock Divider - usbclk + * + * The usb_mp_clk is divided down from the periph_base_clk by the value specified + * in this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK 0x00000007 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_USBCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_DIV_USBCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : SPI Master Clock Divider - spimclk + * + * The spi_m_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7 +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_SPIMCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3) +/* Produces a ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038) + +/* + * Field : CAN0 Clock Divider - can0clk + * + * The can0_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN0CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6) +/* Produces a ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0) + +/* + * Field : CAN1 Clock Divider - can1clk + * + * The can1_clk is divided down from the periph_base_clk by the value specified in + * this field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------- + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 | 0x0 | Divide By 1 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 | 0x1 | Divide By 2 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 | 0x2 | Divide By 4 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 | 0x3 | Divide By 8 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 | 0x4 | Divide By 16 + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 | 0x5 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 | 0x6 | Reserved + * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 | 0x7 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 1 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 2 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 4 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 8 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Divide By 16 + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK + * + * Reserved + */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11 +/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3 +/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00 +/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff +/* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN1CLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9) +/* Produces a ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_DIV. + */ +struct ALT_CLKMGR_PERPLL_DIV_s +{ + uint32_t usbclk : 3; /* USB Clock Divider */ + uint32_t spimclk : 3; /* SPI Master Clock Divider */ + uint32_t can0clk : 3; /* CAN0 Clock Divider */ + uint32_t can1clk : 3; /* CAN1 Clock Divider */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_DIV. */ +typedef volatile struct ALT_CLKMGR_PERPLL_DIV_s ALT_CLKMGR_PERPLL_DIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_DIV register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_DIV_OFST 0x24 + +/* + * Register : GPIO Divide Register - gpiodiv + * + * Contains a field that controls the clock divider for the GPIO De-bounce clock. + * + * Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [23:0] | RW | 0x1 | GPIO De-bounce Clock Divider + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO De-bounce Clock Divider - gpiodbclk + * + * The gpio_db_clk is divided down from the periph_base_clk by the value plus one + * specified in this field. The value 0 (divide by 1) is illegal. A value of 1 + * indicates divide by 2, 2 divide by 3, etc. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 23 +/* The width in bits of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 24 +/* The mask used to set the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x00ffffff +/* The mask used to clear the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xff000000 +/* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK field value from a register. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x00ffffff) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x00ffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_GPIODIV. + */ +struct ALT_CLKMGR_PERPLL_GPIODIV_s +{ + uint32_t gpiodbclk : 24; /* GPIO De-bounce Clock Divider */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_GPIODIV. */ +typedef volatile struct ALT_CLKMGR_PERPLL_GPIODIV_s ALT_CLKMGR_PERPLL_GPIODIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_GPIODIV register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x28 + +/* + * Register : Flash Clock Source Register - src + * + * Contains fields that select the source clocks for the flash controllers. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [1:0] | RW | 0x1 | SDMMC Clock Source + * [3:2] | RW | 0x1 | NAND Clock Source + * [5:4] | RW | 0x1 | QSPI Clock Source + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDMMC Clock Source - sdmmc + * + * Selects the source clock for the SDMMC. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:---------------------- + * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk + * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk + * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC + * + * main_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC + * + * periph_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB 1 +/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK 0x00000003 +/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK 0xfffffffc +/* The reset value of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_SRC_SDMMC field value from a register. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_SRC_SDMMC register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : NAND Clock Source - nand + * + * Selects the source clock for the NAND. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:---------------------- + * ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk + * ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk + * ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND + * + * main_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND + * + * periph_nand_sdmmc_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_MSB 3 +/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK 0x0000000c +/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_SRC_NAND field value from a register. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_CLKMGR_PERPLL_SRC_NAND register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : QSPI Clock Source - qspi + * + * Selects the source clock for the QSPI. + * + * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------- + * ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk + * ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK | 0x1 | main_qspi_clk + * ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK | 0x2 | periph_qspi_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI + * + * f2s_periph_ref_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI + * + * main_qspi_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI + * + * periph_qspi_clk + */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK 0x00000030 +/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK 0xffffffcf +/* The reset value of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET 0x1 +/* Extracts the ALT_CLKMGR_PERPLL_SRC_QSPI field value from a register. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_CLKMGR_PERPLL_SRC_QSPI register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value) (((value) << 4) & 0x00000030) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_SRC. + */ +struct ALT_CLKMGR_PERPLL_SRC_s +{ + uint32_t sdmmc : 2; /* SDMMC Clock Source */ + uint32_t nand : 2; /* NAND Clock Source */ + uint32_t qspi : 2; /* QSPI Clock Source */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_SRC. */ +typedef volatile struct ALT_CLKMGR_PERPLL_SRC_s ALT_CLKMGR_PERPLL_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_SRC register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_SRC_OFST 0x2c + +/* + * Register : Peripheral PLL Output Counter Reset Ack Status Register - stat + * + * Contains Output Clock Counter Reset acknowledge status. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [5:0] | R | 0x0 | Output Counter Reset Acknowledge + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Output Counter Reset Acknowledge - outresetack + * + * These read only bits per PLL output indicate that the PLL has received the + * Output Reset Counter request and has gracefully stopped the respective PLL + * output clock. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------- + * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle + * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK + * + * Idle + */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK + * + * Output Counter Acknowledge received. + */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_MSB 5 +/* The width in bits of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f +/* The mask used to clear the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_RESET 0x0 +/* Extracts the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK field value from a register. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ +#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_PERPLL_STAT. + */ +struct ALT_CLKMGR_PERPLL_STAT_s +{ + const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_PERPLL_STAT. */ +typedef volatile struct ALT_CLKMGR_PERPLL_STAT_s ALT_CLKMGR_PERPLL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_PERPLL_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_PERPLL_STAT_OFST 0x30 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR_PERPLL. + */ +struct ALT_CLKMGR_PERPLL_s +{ + volatile ALT_CLKMGR_PERPLL_VCO_t vco; /* ALT_CLKMGR_PERPLL_VCO */ + volatile ALT_CLKMGR_PERPLL_MISC_t misc; /* ALT_CLKMGR_PERPLL_MISC */ + volatile ALT_CLKMGR_PERPLL_EMAC0CLK_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */ + volatile ALT_CLKMGR_PERPLL_EMAC1CLK_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */ + volatile ALT_CLKMGR_PERPLL_PERQSPICLK_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */ + volatile ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */ + volatile ALT_CLKMGR_PERPLL_PERBASECLK_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */ + volatile ALT_CLKMGR_PERPLL_S2FUSER1CLK_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */ + volatile ALT_CLKMGR_PERPLL_EN_t en; /* ALT_CLKMGR_PERPLL_EN */ + volatile ALT_CLKMGR_PERPLL_DIV_t div; /* ALT_CLKMGR_PERPLL_DIV */ + volatile ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */ + volatile ALT_CLKMGR_PERPLL_SRC_t src; /* ALT_CLKMGR_PERPLL_SRC */ + volatile ALT_CLKMGR_PERPLL_STAT_t stat; /* ALT_CLKMGR_PERPLL_STAT */ + volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_CLKMGR_PERPLL. */ +typedef volatile struct ALT_CLKMGR_PERPLL_s ALT_CLKMGR_PERPLL_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */ +struct ALT_CLKMGR_PERPLL_raw_s +{ + volatile uint32_t vco; /* ALT_CLKMGR_PERPLL_VCO */ + volatile uint32_t misc; /* ALT_CLKMGR_PERPLL_MISC */ + volatile uint32_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */ + volatile uint32_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */ + volatile uint32_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */ + volatile uint32_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */ + volatile uint32_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */ + volatile uint32_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */ + volatile uint32_t en; /* ALT_CLKMGR_PERPLL_EN */ + volatile uint32_t div; /* ALT_CLKMGR_PERPLL_DIV */ + volatile uint32_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */ + volatile uint32_t src; /* ALT_CLKMGR_PERPLL_SRC */ + volatile uint32_t stat; /* ALT_CLKMGR_PERPLL_STAT */ + volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */ +typedef volatile struct ALT_CLKMGR_PERPLL_raw_s ALT_CLKMGR_PERPLL_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : SDRAM PLL Group - ALT_CLKMGR_SDRPLL + * SDRAM PLL Group + * + * Contains registers with settings for the SDRAM PLL. + * + */ +/* + * Register : SDRAM PLL VCO Control Register - vco + * + * Contains settings that control the SDRAM PLL VCO. The VCO output frequency is + * the input frequency multiplied by the numerator (M+1) and divided by the + * denominator (N+1). + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [0] | RW | 0x1 | BG PWRDN + * [1] | RW | 0x0 | Enable + * [2] | RW | 0x1 | Power down + * [15:3] | RW | 0x1 | Numerator (M) + * [21:16] | RW | 0x1 | Denominator (N) + * [23:22] | RW | 0x0 | Clock Source + * [24] | RW | 0x0 | SDRAM All Output Counter Reset + * [30:25] | RW | 0x0 | Output Counter Reset + * [31] | RW | 0x1 | External Regulator Input Select + * + */ +/* + * Field : BG PWRDN - bgpwrdn + * + * If '1', powers down bandgap. If '0', bandgap is not power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable - en + * + * If '1', VCO is enabled. If '0', VCO is in reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_EN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_EN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Power down - pwrdn + * + * If '1', power down analog circuitry. If '0', analog circuitry not powered down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_PWRDN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Numerator (M) - numer + * + * Numerator in VCO output frequency equation. For incremental frequency change, if + * the new value lead to less than 20% of the frequency change, this value can be + * changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007 +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_NUMER field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_NUMER register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) + +/* + * Field : Denominator (N) - denom + * + * Denominator in VCO output frequency equation. For incremental frequency change, + * if the new value lead to less than 20% of the frequency change, this value can + * be changed without resetting the PLL. The Numerator and Denominator can not be + * changed at the same time for incremental frequency changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_DENOM field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_DENOM register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : Clock Source - ssrc + * + * Controls the VCO input clock source. The PLL must by bypassed to eosc1_clk + * before changing this field. + * + * Qsys and user documenation refer to f2s_sdram_ref_clk as f2h_sdram_ref_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------ + * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 | 0x0 | eosc1_clk + * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 | 0x1 | eosc2_clk + * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF | 0x2 | f2s_sdram_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC + * + * eosc1_clk + */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC + * + * eosc2_clk + */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1 +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC + * + * f2s_sdram_ref_clk + */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_SSRC field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_SSRC register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000) + +/* + * Field : SDRAM All Output Counter Reset - outresetall + * + * Before releasing Bypass, All Output Counter Reset must be set and cleared by + * software for correct clock operation. + * + * If '1', Reset phase multiplexer and output counter state. So that after the + * assertion all the clocks output are start from rising edge align. + * + * If '0', phase multiplexer and output counter state not reset and no change to + * the phase of the clock outputs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Output Counter Reset - outreset + * + * Resets the individual PLL output counter. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. + * + * If set to '1', reset output divider, no clock output from counter. + * + * If set to '0', counter is not reset. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRST field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) + +/* + * Field : External Regulator Input Select - regextsel + * + * If set to '1', the external regulator is selected for the PLL. + * + * If set to '0', the internal regulator is slected. + * + * It is strongly recommended to select the external regulator while the PLL is not + * enabled (in reset), and then disable the external regulater once the PLL + * becomes enabled. Software should simulateously update the 'Enable' bit and the + * 'External Regulator Input Select' in the same write access to the VCO register. + * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be + * set, and vice versa. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31 +/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff +/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL field value from a register. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_VCO. + */ +struct ALT_CLKMGR_SDRPLL_VCO_s +{ + uint32_t bgpwrdn : 1; /* BG PWRDN */ + uint32_t en : 1; /* Enable */ + uint32_t pwrdn : 1; /* Power down */ + uint32_t numer : 13; /* Numerator (M) */ + uint32_t denom : 6; /* Denominator (N) */ + uint32_t ssrc : 2; /* Clock Source */ + uint32_t outresetall : 1; /* SDRAM All Output Counter Reset */ + uint32_t outreset : 6; /* Output Counter Reset */ + uint32_t regextsel : 1; /* External Regulator Input Select */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_VCO. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_VCO_s ALT_CLKMGR_SDRPLL_VCO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_VCO register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_VCO_OFST 0x0 + +/* + * Register : SDRAM PLL VCO Advanced Control Register - ctrl + * + * Contains VCO control signals and other PLL control signals need to be + * controllable through register. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled + * [12:1] | RW | 0x1 | Loop Bandwidth Adjust + * [13] | RW | 0x0 | Fast Locking Enable + * [14] | RW | 0x1 | Saturation Enable + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Loop Bandwidth Adjust Enabled - bwadjen + * + * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth + * Adjust field. + * + * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 + * value of the VCO Control Register. The M divided by 2 is the upper 12 bits + * (12:1) of the M field in the VCO register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_MSB 0 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJEN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Loop Bandwidth Adjust - bwadj + * + * Provides Loop Bandwidth Adjust value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_MSB 12 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET_MSK 0x00001ffe +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_CLR_MSK 0xffffe001 +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJ field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) + +/* + * Field : Fast Locking Enable - fasten + * + * Enables fast locking circuit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_MSB 13 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET_MSK 0x00002000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_CLR_MSK 0xffffdfff +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_FASTEN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Saturation Enable - saten + * + * Enables saturation behavior. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_MSB 14 +/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET_MSK 0x00004000 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_CLR_MSK 0xffffbfff +/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_CTL_SATEN field value from a register. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_CLKMGR_SDRPLL_CTL_SATEN register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_CTL. + */ +struct ALT_CLKMGR_SDRPLL_CTL_s +{ + uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ + uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ + uint32_t fasten : 1; /* Fast Locking Enable */ + uint32_t saten : 1; /* Saturation Enable */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_CTL. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_CTL_s ALT_CLKMGR_SDRPLL_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_CTL register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_CTL_OFST 0x4 + +/* + * Register : SDRAM PLL C0 Control Register for Clock ddr_dqs_clk - ddrdqsclk + * + * Contains settings that control clock ddr_dqs_clk generated from the C0 output of + * the SDRAM PLL. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. + */ +struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s ALT_CLKMGR_SDRPLL_DDRDQSCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST 0x8 + +/* + * Register : SDRAM PLL C1 Control Register for Clock ddr_2x_dqs_clk - ddr2xdqsclk + * + * Contains settings that control clock ddr_2x_dqs_clk generated from the C1 output + * of the SDRAM PLL. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. + */ +struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST 0xc + +/* + * Register : SDRAM PLL C2 Control Register for Clock ddr_dq_clk - ddrdqclk + * + * Contains settings that control clock ddr_dq_clk generated from the C2 output of + * the SDRAM PLL. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. + */ +struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s ALT_CLKMGR_SDRPLL_DDRDQCLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQCLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10 + +/* + * Register : SDRAM PLL C5 Control Register for Clock s2f_user2_clk - s2fuser2clk + * + * Contains settings that control clock s2f_user2_clk generated from the C5 output + * of the SDRAM PLL. + * + * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [8:0] | RW | 0x1 | Counter + * [20:9] | RW | 0x0 | Phase Shift + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter - cnt + * + * Divides the VCO frequency by the value+1 in this field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_MSB 8 +/* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_WIDTH 9 +/* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK 0x000001ff +/* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT field value from a register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) + +/* + * Field : Phase Shift - phase + * + * Increment the phase of the VCO output by the value in this field multiplied by + * 45 degrees. The accumulated phase shift is the total shifted amount since the + * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco + * control register. In order to guarantee the phase shift to a known value, 'SDRAM + * clocks output phase align' bit should be asserted before programming this field. + * + * This field is only writeable by SW when it is zero. HW updates this field in + * real time as the phase adjustment is being made. SW may poll this field + * waiting for zero indicating the phase adjustment has completed by HW. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_MSB 20 +/* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_WIDTH 12 +/* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK 0x001ffe00 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_CLR_MSK 0xffe001ff +/* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE field value from a register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) +/* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. + */ +struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s +{ + uint32_t cnt : 9; /* Counter */ + uint32_t phase : 12; /* Phase Shift */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST 0x14 + +/* + * Register : Enable Register - en + * + * Contains fields that control the SDRAM Clock Group enables generated from the + * SDRAM PLL clock outputs. + * + * 1: The clock is enabled. + * + * 0: The clock is disabled. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | RW | 0x1 | ddr_dqs_clk Enable + * [1] | RW | 0x1 | ddr_2x_dqs_clk Enable + * [2] | RW | 0x1 | ddr_dq_clk Enable + * [3] | RW | 0x1 | s2f_user2_clk Enable + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ddr_dqs_clk Enable - ddrdqsclk + * + * Enables clock ddr_dqs_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB 0 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : ddr_2x_dqs_clk Enable - ddr2xdqsclk + * + * Enables clock ddr_2x_dqs_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB 1 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ddr_dq_clk Enable - ddrdqclk + * + * Enables clock ddr_dq_clk output + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB 2 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : s2f_user2_clk Enable - s2fuser2clk + * + * Enables clock s2f_user2_clk output. + * + * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB 3 +/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH 1 +/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET 0x1 +/* Extracts the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_EN. + */ +struct ALT_CLKMGR_SDRPLL_EN_s +{ + uint32_t ddrdqsclk : 1; /* ddr_dqs_clk Enable */ + uint32_t ddr2xdqsclk : 1; /* ddr_2x_dqs_clk Enable */ + uint32_t ddrdqclk : 1; /* ddr_dq_clk Enable */ + uint32_t s2fuser2clk : 1; /* s2f_user2_clk Enable */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_EN. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_EN_s ALT_CLKMGR_SDRPLL_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_EN register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_EN_OFST 0x18 + +/* + * Register : SDRAM PLL Output Counter Reset Ack Status Register - stat + * + * Contains Output Clock Counter Reset acknowledge status. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [5:0] | R | 0x0 | Output Counter Reset Acknowledge + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Output Counter Reset Acknowledge - outresetack + * + * These read only bits per PLL output indicate that the PLL has received the + * Output Reset Counter request and has gracefully stopped the respective PLL + * output clock. + * + * For software to change the PLL output counter without producing glitches on the + * respective clock, SW must set the VCO register respective Output Counter Reset + * bit. Software then polls the respective Output Counter Reset Acknowledge bit in + * the Output Counter Reset Ack Status Register. Software then writes the + * appropriate counter register, and then clears the respective VCO register Output + * Counter Reset bit. + * + * The reset value of this bit is applied on a cold reset; warm reset has no affect + * on this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------- + * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle + * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK + * + * Idle + */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK + * + * Output Counter Acknowledge received. + */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_MSB 5 +/* The width in bits of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_WIDTH 6 +/* The mask used to set the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f +/* The mask used to clear the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_RESET 0x0 +/* Extracts the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK field value from a register. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ +#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_CLKMGR_SDRPLL_STAT. + */ +struct ALT_CLKMGR_SDRPLL_STAT_s +{ + const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_CLKMGR_SDRPLL_STAT. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_STAT_s ALT_CLKMGR_SDRPLL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_CLKMGR_SDRPLL_STAT register from the beginning of the component. */ +#define ALT_CLKMGR_SDRPLL_STAT_OFST 0x1c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR_SDRPLL. + */ +struct ALT_CLKMGR_SDRPLL_s +{ + volatile ALT_CLKMGR_SDRPLL_VCO_t vco; /* ALT_CLKMGR_SDRPLL_VCO */ + volatile ALT_CLKMGR_SDRPLL_CTL_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */ + volatile ALT_CLKMGR_SDRPLL_DDRDQSCLK_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */ + volatile ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */ + volatile ALT_CLKMGR_SDRPLL_DDRDQCLK_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */ + volatile ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */ + volatile ALT_CLKMGR_SDRPLL_EN_t en; /* ALT_CLKMGR_SDRPLL_EN */ + volatile ALT_CLKMGR_SDRPLL_STAT_t stat; /* ALT_CLKMGR_SDRPLL_STAT */ +}; + +/* The typedef declaration for register group ALT_CLKMGR_SDRPLL. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_s ALT_CLKMGR_SDRPLL_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */ +struct ALT_CLKMGR_SDRPLL_raw_s +{ + volatile uint32_t vco; /* ALT_CLKMGR_SDRPLL_VCO */ + volatile uint32_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */ + volatile uint32_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */ + volatile uint32_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */ + volatile uint32_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */ + volatile uint32_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */ + volatile uint32_t en; /* ALT_CLKMGR_SDRPLL_EN */ + volatile uint32_t stat; /* ALT_CLKMGR_SDRPLL_STAT */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */ +typedef volatile struct ALT_CLKMGR_SDRPLL_raw_s ALT_CLKMGR_SDRPLL_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_CLKMGR. + */ +struct ALT_CLKMGR_s +{ + volatile ALT_CLKMGR_CTL_t ctrl; /* ALT_CLKMGR_CTL */ + volatile ALT_CLKMGR_BYPASS_t bypass; /* ALT_CLKMGR_BYPASS */ + volatile ALT_CLKMGR_INTER_t inter; /* ALT_CLKMGR_INTER */ + volatile ALT_CLKMGR_INTREN_t intren; /* ALT_CLKMGR_INTREN */ + volatile ALT_CLKMGR_DBCTL_t dbctrl; /* ALT_CLKMGR_DBCTL */ + volatile ALT_CLKMGR_STAT_t stat; /* ALT_CLKMGR_STAT */ + volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */ + volatile ALT_CLKMGR_MAINPLL_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */ + volatile ALT_CLKMGR_PERPLL_t perpllgrp; /* ALT_CLKMGR_PERPLL */ + volatile ALT_CLKMGR_SDRPLL_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */ + volatile uint32_t _pad_0xe0_0x200[72]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_CLKMGR. */ +typedef volatile struct ALT_CLKMGR_s ALT_CLKMGR_t; +/* The struct declaration for the raw register contents of register group ALT_CLKMGR. */ +struct ALT_CLKMGR_raw_s +{ + volatile uint32_t ctrl; /* ALT_CLKMGR_CTL */ + volatile uint32_t bypass; /* ALT_CLKMGR_BYPASS */ + volatile uint32_t inter; /* ALT_CLKMGR_INTER */ + volatile uint32_t intren; /* ALT_CLKMGR_INTREN */ + volatile uint32_t dbctrl; /* ALT_CLKMGR_DBCTL */ + volatile uint32_t stat; /* ALT_CLKMGR_STAT */ + volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */ + volatile ALT_CLKMGR_MAINPLL_raw_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */ + volatile ALT_CLKMGR_PERPLL_raw_t perpllgrp; /* ALT_CLKMGR_PERPLL */ + volatile ALT_CLKMGR_SDRPLL_raw_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */ + volatile uint32_t _pad_0xe0_0x200[72]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_CLKMGR. */ +typedef volatile struct ALT_CLKMGR_raw_s ALT_CLKMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_CLKMGR_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dap.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dap.h new file mode 100644 index 000000000..fcabb7587 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dap.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DAP */ + +#ifndef __ALTERA_ALT_DAP_H__ +#define __ALTERA_ALT_DAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : DAP Module Address Space - ALT_DAP + * DAP Module Address Space + * + * Address space allocated to the DAP. For detailed information about the use of + * this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/index.html]click + * here[/url] to access the ARM documentation for the DAP. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DAP_REG_FLD register field. */ +#define ALT_DAP_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DAP_REG_FLD register field. */ +#define ALT_DAP_REG_FLD_MSB 31 +/* The width in bits of the ALT_DAP_REG_FLD register field. */ +#define ALT_DAP_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DAP_REG_FLD register field value. */ +#define ALT_DAP_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DAP_REG_FLD register field value. */ +#define ALT_DAP_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DAP_REG_FLD register field is UNKNOWN. */ +#define ALT_DAP_REG_FLD_RESET 0x0 +/* Extracts the ALT_DAP_REG_FLD field value from a register. */ +#define ALT_DAP_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DAP_REG_FLD register field value suitable for setting the register. */ +#define ALT_DAP_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DAP_REG. + */ +struct ALT_DAP_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DAP_REG. */ +typedef volatile struct ALT_DAP_REG_s ALT_DAP_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DAP_REG register from the beginning of the component. */ +#define ALT_DAP_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DAP. + */ +struct ALT_DAP_s +{ + volatile ALT_DAP_REG_t reg; /* ALT_DAP_REG */ +}; + +/* The typedef declaration for register group ALT_DAP. */ +typedef volatile struct ALT_DAP_s ALT_DAP_t; +/* The struct declaration for the raw register contents of register group ALT_DAP. */ +struct ALT_DAP_raw_s +{ + volatile uint32_t reg; /* ALT_DAP_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DAP. */ +typedef volatile struct ALT_DAP_raw_s ALT_DAP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DAP_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dmanonsecure.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dmanonsecure.h new file mode 100644 index 000000000..579d862eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dmanonsecure.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DMANONSECURE */ + +#ifndef __ALTERA_ALT_DMANONSECURE_H__ +#define __ALTERA_ALT_DMANONSECURE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : nonsecure DMA Module Address Space - ALT_DMANONSECURE + * nonsecure DMA Module Address Space + * + * Address space allocated to the nonsecure DMA. For detailed information about the + * use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click + * here[/url] to access the ARM documentation for the DMA-330. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_MSB 31 +/* The width in bits of the ALT_DMANONSECURE_REG_FLD register field. */ +#define ALT_DMANONSECURE_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DMANONSECURE_REG_FLD register field value. */ +#define ALT_DMANONSECURE_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DMANONSECURE_REG_FLD register field value. */ +#define ALT_DMANONSECURE_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DMANONSECURE_REG_FLD register field is UNKNOWN. */ +#define ALT_DMANONSECURE_REG_FLD_RESET 0x0 +/* Extracts the ALT_DMANONSECURE_REG_FLD field value from a register. */ +#define ALT_DMANONSECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DMANONSECURE_REG_FLD register field value suitable for setting the register. */ +#define ALT_DMANONSECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DMANONSECURE_REG. + */ +struct ALT_DMANONSECURE_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DMANONSECURE_REG. */ +typedef volatile struct ALT_DMANONSECURE_REG_s ALT_DMANONSECURE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DMANONSECURE_REG register from the beginning of the component. */ +#define ALT_DMANONSECURE_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DMANONSECURE. + */ +struct ALT_DMANONSECURE_s +{ + volatile ALT_DMANONSECURE_REG_t reg; /* ALT_DMANONSECURE_REG */ +}; + +/* The typedef declaration for register group ALT_DMANONSECURE. */ +typedef volatile struct ALT_DMANONSECURE_s ALT_DMANONSECURE_t; +/* The struct declaration for the raw register contents of register group ALT_DMANONSECURE. */ +struct ALT_DMANONSECURE_raw_s +{ + volatile uint32_t reg; /* ALT_DMANONSECURE_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DMANONSECURE. */ +typedef volatile struct ALT_DMANONSECURE_raw_s ALT_DMANONSECURE_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DMANONSECURE_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dmasecure.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dmasecure.h new file mode 100644 index 000000000..9e8d94549 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_dmasecure.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_DMASECURE */ + +#ifndef __ALTERA_ALT_DMASECURE_H__ +#define __ALTERA_ALT_DMASECURE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : secure DMA Module Address Space - ALT_DMASECURE + * secure DMA Module Address Space + * + * Address space allocated to the secure DMA. For detailed information about the + * use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click + * here[/url] to access the ARM documentation for the DMA-330. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_MSB 31 +/* The width in bits of the ALT_DMASECURE_REG_FLD register field. */ +#define ALT_DMASECURE_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_DMASECURE_REG_FLD register field value. */ +#define ALT_DMASECURE_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_DMASECURE_REG_FLD register field value. */ +#define ALT_DMASECURE_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_DMASECURE_REG_FLD register field is UNKNOWN. */ +#define ALT_DMASECURE_REG_FLD_RESET 0x0 +/* Extracts the ALT_DMASECURE_REG_FLD field value from a register. */ +#define ALT_DMASECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_DMASECURE_REG_FLD register field value suitable for setting the register. */ +#define ALT_DMASECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_DMASECURE_REG. + */ +struct ALT_DMASECURE_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_DMASECURE_REG. */ +typedef volatile struct ALT_DMASECURE_REG_s ALT_DMASECURE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_DMASECURE_REG register from the beginning of the component. */ +#define ALT_DMASECURE_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_DMASECURE. + */ +struct ALT_DMASECURE_s +{ + volatile ALT_DMASECURE_REG_t reg; /* ALT_DMASECURE_REG */ +}; + +/* The typedef declaration for register group ALT_DMASECURE. */ +typedef volatile struct ALT_DMASECURE_s ALT_DMASECURE_t; +/* The struct declaration for the raw register contents of register group ALT_DMASECURE. */ +struct ALT_DMASECURE_raw_s +{ + volatile uint32_t reg; /* ALT_DMASECURE_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_DMASECURE. */ +typedef volatile struct ALT_DMASECURE_raw_s ALT_DMASECURE_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_DMASECURE_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_emac.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_emac.h new file mode 100644 index 000000000..7135ed99f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_emac.h @@ -0,0 +1,103305 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_EMAC */ + +#ifndef __ALTERA_ALT_EMAC_H__ +#define __ALTERA_ALT_EMAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : EMAC Module - ALT_EMAC + * EMAC Module + * + * Registers in the EMAC module. + * + */ +/* + * Register Group : GMAC Register Group - ALT_EMAC_GMAC + * GMAC Register Group + * + * GMAC Register Group + * + */ +/* + * Register : Register 0 (MAC Configuration Register) - MAC_Configuration + * + * The MAC Configuration register establishes receive and transmit operating modes. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------ + * [1:0] | RW | 0x0 | Preamble Length for Transmit Frames + * [2] | RW | 0x0 | Receiver Enable + * [3] | RW | 0x0 | Transmitter Enable + * [4] | RW | 0x0 | Deferral Check + * [6:5] | RW | 0x0 | Back-Off Limit + * [7] | RW | 0x0 | Automatic Pad or CRC Stripping + * [8] | RW | 0x0 | Link Up or Down + * [9] | RW | 0x0 | Disable Retry + * [10] | RW | 0x0 | Checksum Offload + * [11] | RW | 0x0 | Duplex Mode + * [12] | RW | 0x0 | Loopback Mode + * [13] | RW | 0x0 | Disable Receive Own + * [14] | RW | 0x0 | Speed + * [15] | RW | 0x0 | Port Select + * [16] | RW | 0x0 | Disable Carrier Sense During Transmission + * [19:17] | RW | 0x0 | Inter-Frame Gap + * [20] | RW | 0x0 | Jumbo Frame Enable + * [21] | RW | 0x0 | Frame Burst Enable + * [22] | RW | 0x0 | Jabber Disable + * [23] | RW | 0x0 | Watchdog Disable + * [24] | RW | 0x0 | Transmit Configuration in RGMII, SGMII, or SMII + * [25] | RW | 0x0 | CRC Stripping of Type Frames + * [26] | ??? | 0x0 | *UNDEFINED* + * [27] | RW | 0x0 | IEEE 802.3as support for 2K packets Enable + * [31:28] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble Length for Transmit Frames - prelen + * + * These bits control the number of preamble bytes that are added to the beginning + * of every Transmit frame. The preamble reduction occurs only when the MAC is + * operating + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------- + * ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES | 0x0 | Preamble 7 Bytes + * ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES | 0x1 | Preamble 5 Bytes + * ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES | 0x2 | Preamble 3 Bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN + * + * Preamble 7 Bytes + */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN + * + * Preamble 5 Bytes + */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN + * + * Preamble 3 Bytes + */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET_MSK 0x00000003 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_CLR_MSK 0xfffffffc +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_PRELEN field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Receiver Enable - re + * + * When this bit is set, the receiver state machine of the MAC is enabled for + * receiving frames from the GMII or MII. When this bit is reset, the MAC receive + * state machine is disabled after the completion of the reception of the current + * frame, and does not receive any further frames from the GMII or MII. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD | 0x0 | MAC receive state machine disabled + * ALT_EMAC_GMAC_MAC_CFG_RE_E_END | 0x1 | MAC receive state machine enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE + * + * MAC receive state machine disabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE + * + * MAC receive state machine enabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_RE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_RE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_RE_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_RE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_RE register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_RE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_RE register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_RE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_RE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_RE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_RE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_RE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_RE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Transmitter Enable - te + * + * When this bit is set, the transmit state machine of the MAC is enabled for + * transmission on the GMII or MII. When this bit is reset, the MAC transmit state + * machine is disabled after the completion of the transmission of the current + * frame, and does not transmit any further frames. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD | 0x0 | MAC transmit state machine disabled + * ALT_EMAC_GMAC_MAC_CFG_TE_E_END | 0x1 | MAC transmit state machine disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE + * + * MAC transmit state machine disabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE + * + * MAC transmit state machine disabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_TE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TE_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TE register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_TE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TE register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_TE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_TE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_TE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_TE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_TE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Deferral Check - dc + * + * When this bit is set, the deferral check function is enabled in the MAC. The MAC + * issues a Frame Abort status, along with the excessive deferral error bit set in + * the transmit frame status, when the transmit state machine is deferred for more + * than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for + * 1000 Mbps operation, or if the Jumbo frame mode is enabled in the 10 or 100 Mbps + * mode, the threshold for deferral is 155,680 bits times. Deferral begins when the + * transmitter is ready to transmit, but is prevented because of an active carrier + * sense signal (CRS) on GMII or MII. Defer time is not cumulative. When the + * transmitter defers for 10,000 bit times, it transmits, collides, backs off, and + * then defers again after completion of back-off. The deferral timer resets to 0 + * and restarts. + * + * When this bit is reset, the deferral check function is disabled and the MAC + * defers until the CRS signal goes inactive. This bit is applicable only in the + * half-duplex mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------ + * ALT_EMAC_GMAC_MAC_CFG_DC_E_END | 0x1 | Deferral Check Enabled + * ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD | 0x0 | Deferral Check Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC + * + * Deferral Check Enabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_DC_E_END 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC + * + * Deferral Check Disabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DC_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DC_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DC_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DC register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_DC_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DC register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_DC_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DC_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_DC field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_DC_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_DC register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_DC_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Back-Off Limit - bl + * + * The Back-Off limit determines the random integer number (r) of slot time delays + * (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the + * MAC waits before rescheduling a transmission attempt during retries after a + * collision. This bit is applicable only in the half-duplex mode. + * + * * 00: k = min (n, 10) + * + * * 01: k = min (n, 8) + * + * * 10: k = min (n, 4) + * + * * 11: k = min (n, 1) + * + * where n = retransmission attempt. The random integer r takes + * the value in the + * + * range 0 <= r < kth power of 2 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10 | 0x0 | k = min (n, 10) + * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8 | 0x1 | k = min (n, 8) + * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4 | 0x2 | k = min (n, 4) + * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1 | 0x3 | k = min (n, 1) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL + * + * k = min (n, 10) + */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL + * + * k = min (n, 8) + */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL + * + * k = min (n, 4) + */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4 0x2 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL + * + * k = min (n, 1) + */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_MSB 6 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BL register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_SET_MSK 0x00000060 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BL register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_CLR_MSK 0xffffff9f +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_BL field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_GET(value) (((value) & 0x00000060) >> 5) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_BL register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_BL_SET(value) (((value) << 5) & 0x00000060) + +/* + * Field : Automatic Pad or CRC Stripping - acs + * + * When this bit is set, the MAC strips the Pad or FCS field on the incoming frames + * only if the value of the length field is less than 1,536 bytes. All received + * frames with length field greater than or equal to 1,536 bytes are passed to the + * application without stripping the Pad or FCS field. + * + * When this bit is reset, the MAC passes all incoming frames, without modifying + * them, to the Host. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD | 0x0 | Disable Automatic Pad CRC Stripping + * ALT_EMAC_GMAC_MAC_CFG_ACS_E_END | 0x1 | Enable Automatic Pad CRC Stripping + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS + * + * Disable Automatic Pad CRC Stripping + */ +#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS + * + * Enable Automatic Pad CRC Stripping + */ +#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_ACS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_ACS_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_ACS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_ACS register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_ACS register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_ACS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_ACS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_ACS field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_ACS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_ACS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Link Up or Down - lud + * + * This bit indicates whether the link is up or down during the transmission of + * configuration in the RGMII, SGMII, or SMII interface + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD | 0x0 | Link Down + * ALT_EMAC_GMAC_MAC_CFG_LUD_E_END | 0x1 | Link Up + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD + * + * Link Down + */ +#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD + * + * Link Up + */ +#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_LUD_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_LUD_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_LUD_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LUD register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LUD register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_LUD_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_LUD_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_LUD field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_LUD_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_LUD register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Disable Retry - dr + * + * When this bit is set, the MAC attempts only one transmission. When a collision + * occurs on the GMII or MII interface, the MAC ignores the current frame + * transmission and reports a Frame Abort with excessive collision error in the + * transmit frame status. + * + * When this bit is reset, the MAC attempts retries based on the settings of the BL + * field (Bits [6:5]). This bit is applicable only in the half-duplex mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------------- + * ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD | 0x1 | MAC attempts one transmission + * ALT_EMAC_GMAC_MAC_CFG_DR_E_END | 0x0 | MAC attempts retries per bl Field + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR + * + * MAC attempts one transmission + */ +#define ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR + * + * MAC attempts retries per bl Field + */ +#define ALT_EMAC_GMAC_MAC_CFG_DR_E_END 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DR_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DR_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DR register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_DR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DR register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_DR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DR_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_DR field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_DR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_DR register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_DR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Checksum Offload - ipc + * + * When this bit is set, the MAC calculates the 16-bit ones complement of the ones + * complement sum of all received Ethernet frame payloads. It also checks whether + * the IPv4 Header checksum (assumed to be bytes 2526 or 2930 (VLAN-tagged) of the + * received Ethernet frame) is correct for the received frame and gives the status + * in the receive status word. The MAC also appends the 16-bit checksum calculated + * for the IP header datagram payload (bytes after the IPv4 header) and appends it + * to the Ethernet frame transferred to the application (when Type 2 COE is + * deselected). + * + * When this bit is reset, this function is disabled. + * + * When Type 2 COE is selected, this bit, when set, enables the IPv4 header + * checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. + * When this bit is reset, the COE function in the receiver is disabled and the + * corresponding PCE and IP HCE status bits are always cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_EMAC_GMAC_MAC_CFG_IPC_E_END | 0x1 | Checksum Enabled + * ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD | 0x0 | Checksum Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC + * + * Checksum Enabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_END 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC + * + * Checksum Disabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_IPC_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_IPC_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_IPC_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IPC register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IPC register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_IPC_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_IPC_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_IPC field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_IPC_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_IPC register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Duplex Mode - dm + * + * When this bit is set, the MAC operates in the full-duplex mode where it can + * transmit and receive simultaneously. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------- + * ALT_EMAC_GMAC_MAC_CFG_DM_E_END | 0x1 | MAC Full Duplex Enabled + * ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD | 0x0 | MAC Full Duplex Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM + * + * MAC Full Duplex Enabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_DM_E_END 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM + * + * MAC Full Duplex Disabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DM_MSB 11 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DM register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_DM_SET_MSK 0x00000800 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DM register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_DM_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_DM field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_DM_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_DM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_DM_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Loopback Mode - lm + * + * When this bit is set, the MAC operates in the loopback mode at GMII or MII. The + * (G)MII Receive clock input is required for the loopback to work properly, + * because the Transmit clock is not looped-back internally. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------ + * ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD | 0x0 | Disable Loop Back + * ALT_EMAC_GMAC_MAC_CFG_LM_E_END | 0x1 | Enable Loop Back + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM + * + * Disable Loop Back + */ +#define ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM + * + * Enable Loop Back + */ +#define ALT_EMAC_GMAC_MAC_CFG_LM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_LM_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_LM_MSB 12 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_LM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LM register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_LM_SET_MSK 0x00001000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LM register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_LM_CLR_MSK 0xffffefff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_LM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_LM field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_LM_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_LM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_LM_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Disable Receive Own - do + * + * When this bit is set, the MAC disables the reception of frames when the + * gmii_txen_o is asserted in the half-duplex mode. + * + * When this bit is reset, the MAC receives all packets that are given by the PHY + * while transmitting. + * + * This bit is not applicable if the MAC is operating in the full-duplex mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MAC_CFG_DO_E_END | 0x0 | MAC Enables Reception of Frames + * ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD | 0x1 | MAC Disables Reception of Frames + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO + * + * MAC Enables Reception of Frames + */ +#define ALT_EMAC_GMAC_MAC_CFG_DO_E_END 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO + * + * MAC Disables Reception of Frames + */ +#define ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DO_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DO_MSB 13 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DO_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DO register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_DO_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DO register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_DO_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DO_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_DO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_DO_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_DO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_DO_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Speed - fes + * + * This bit selects the speed in the RMII/RGMII interface: + * + * * 0: 10 Mbps + * + * * 1: 100 Mbps + * + * This bit generates link speed encoding when TC (Bit 24) is set in the RGMII, + * SMII, or SGMII mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10 | 0x0 | Speed = 10 Mbps + * ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100 | 0x1 | Speed = 100 Mbps + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES + * + * Speed = 10 Mbps + */ +#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES + * + * Speed = 100 Mbps + */ +#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_FES_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_FES_MSB 14 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_FES_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_FES register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_FES_SET_MSK 0x00004000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_FES register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_FES_CLR_MSK 0xffffbfff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_FES_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_FES field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_FES_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_FES register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_FES_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Port Select - ps + * + * This bit selects between GMII and MII + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL | 0x0 | GMII 1000 Mbps + * ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL | 0x1 | MII 10/100 Mbps + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS + * + * GMII 1000 Mbps + */ +#define ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS + * + * MII 10/100 Mbps + */ +#define ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_PS_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_PS_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_PS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PS register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_PS_SET_MSK 0x00008000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PS register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_PS_CLR_MSK 0xffff7fff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_PS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_PS field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_PS_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_PS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_PS_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Disable Carrier Sense During Transmission - dcrs + * + * When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal + * during frame transmission in the half-duplex mode. This request results in no + * errors generated because of Loss of Carrier or No Carrier during such + * transmission. When this bit is low, the MAC transmitter generates such errors + * because of Carrier Sense and can even abort the transmissions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD | 0x0 | MAC Tx Gen. Err. No Carrier + * ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END | 0x1 | MAC Tx Ignores (G)MII Crs Signal + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS + * + * MAC Tx Gen. Err. No Carrier + */ +#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS + * + * MAC Tx Ignores (G)MII Crs Signal + */ +#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DCRS_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DCRS_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DCRS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_DCRS_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_DCRS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_DCRS field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_DCRS_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_DCRS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Inter-Frame Gap - ifg + * + * These bits control the minimum IFG between frames during transmission. + * + * In the half-duplex mode, the minimum IFG can be configured only for 64 bit times + * (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum + * IFG supported is 80 bit times (and above). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES | 0x0 | Inter Frame Gap 96 bit times + * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES | 0x1 | Inter Frame Gap 88 bit times + * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES | 0x2 | Inter Frame Gap 80 bit times + * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES | 0x3 | Inter Frame Gap 72 bit times + * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES | 0x4 | Inter Frame Gap 64 bit times + * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES | 0x5 | Inter Frame Gap 56 bit times + * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES | 0x6 | Inter Frame Gap 48 bit times + * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES | 0x7 | Inter Frame Gap 40 bit times + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG + * + * Inter Frame Gap 96 bit times + */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG + * + * Inter Frame Gap 88 bit times + */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG + * + * Inter Frame Gap 80 bit times + */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES 0x2 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG + * + * Inter Frame Gap 72 bit times + */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES 0x3 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG + * + * Inter Frame Gap 64 bit times + */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES 0x4 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG + * + * Inter Frame Gap 56 bit times + */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES 0x5 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG + * + * Inter Frame Gap 48 bit times + */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES 0x6 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG + * + * Inter Frame Gap 40 bit times + */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_WIDTH 3 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IFG register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET_MSK 0x000e0000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IFG register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_CLR_MSK 0xfff1ffff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_IFG field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_GET(value) (((value) & 0x000e0000) >> 17) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_IFG register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET(value) (((value) << 17) & 0x000e0000) + +/* + * Field : Jumbo Frame Enable - je + * + * When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes + * for VLAN tagged frames) without reporting a giant frame error in the receive + * frame status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------- + * ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD | 0x0 | Report Jumbo Frame Error + * ALT_EMAC_GMAC_MAC_CFG_JE_E_END | 0x1 | Ignore Jumbo Frame Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE + * + * Report Jumbo Frame Error + */ +#define ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE + * + * Ignore Jumbo Frame Error + */ +#define ALT_EMAC_GMAC_MAC_CFG_JE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_JE_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_JE_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_JE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JE register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_JE_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JE register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_JE_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_JE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_JE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_JE_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_JE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_JE_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Frame Burst Enable - be + * + * When this bit is set, the MAC allows frame bursting during transmission in the + * GMII half-duplex mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------- + * ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD | 0x0 | Frame Burst Enable OFF + * ALT_EMAC_GMAC_MAC_CFG_BE_E_END | 0x1 | Frame Burst Enable ON + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE + * + * Frame Burst Enable OFF + */ +#define ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE + * + * Frame Burst Enable ON + */ +#define ALT_EMAC_GMAC_MAC_CFG_BE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_BE_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_BE_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_BE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BE register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_BE_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BE register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_BE_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_BE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_BE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_BE_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_BE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_BE_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Jabber Disable - jd + * + * When this bit is set, the MAC disables the jabber timer on the transmitter. The + * MAC can transfer frames of up to 16,384 bytes. + * + * When this bit is reset, the MAC cuts off the transmitter if the application + * sends out more than 2,048 bytes of data (10,240 if JE is set high) during + * transmission. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------- + * ALT_EMAC_GMAC_MAC_CFG_JD_E_END | 0x0 | MAC cuts off TX > 2048 + * ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD | 0x1 | Jabber Timer Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD + * + * MAC cuts off TX > 2048 + */ +#define ALT_EMAC_GMAC_MAC_CFG_JD_E_END 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD + * + * Jabber Timer Disabled + */ +#define ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_JD_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_JD_MSB 22 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_JD_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JD register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_JD_SET_MSK 0x00400000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JD register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_JD_CLR_MSK 0xffbfffff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_JD_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_JD field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_JD_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_JD register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_JD_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : Watchdog Disable - wd + * + * When this bit is set, the MAC disables the watchdog timer on the receiver. The + * MAC can receive frames of up to 16,384 bytes. + * + * When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if + * JE is set high) of the frame being received. The MAC cuts off any bytes received + * after 2,048 bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------ + * ALT_EMAC_GMAC_MAC_CFG_WD_E_END | 0x0 | Enable MAC cutoff > 2048Bytes + * ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD | 0x1 | Disable Watchdog + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD + * + * Enable MAC cutoff > 2048Bytes + */ +#define ALT_EMAC_GMAC_MAC_CFG_WD_E_END 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD + * + * Disable Watchdog + */ +#define ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_WD_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_WD_MSB 23 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_WD_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_WD register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_WD_SET_MSK 0x00800000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_WD register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_WD_CLR_MSK 0xff7fffff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_WD_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_WD field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_WD_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_WD register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_WD_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Transmit Configuration in RGMII, SGMII, or SMII - tc + * + * When set, this bit enables the transmission of duplex mode, link speed, and link + * up or down information to the PHY in the RGMII. When this bit is reset, no such + * information is driven to the PHY. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------- + * ALT_EMAC_GMAC_MAC_CFG_TC_E_END | 0x1 | Enables Transmission of duplex + * ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD | 0x0 | Disables Transmission to Phy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC + * + * Enables Transmission of duplex + */ +#define ALT_EMAC_GMAC_MAC_CFG_TC_E_END 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC + * + * Disables Transmission to Phy + */ +#define ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TC_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TC_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TC_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TC register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_TC_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TC register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_TC_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TC_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_TC field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_TC_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_TC register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_TC_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : CRC Stripping of Type Frames - cst + * + * When set, the last 4 bytes (FCS) of all frames of Ether type (type field greater + * than 0x0600) are stripped and dropped before forwarding the frame to the + * application. This function is not valid when the IP Checksum Engine (Type 1) is + * enabled in the MAC receiver. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------- + * ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD | 0x0 | Strip Ether Frames Off + * ALT_EMAC_GMAC_MAC_CFG_CST_E_END | 0x1 | Strip Ether Frames On + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST + * + * Strip Ether Frames Off + */ +#define ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST + * + * Strip Ether Frames On + */ +#define ALT_EMAC_GMAC_MAC_CFG_CST_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_CST_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_CST_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_CST_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_CST register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_CST_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_CST register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_CST_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_CST_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_CST field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_CST_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_CST register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_CST_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : IEEE 802.3as support for 2K packets Enable - twokpe + * + * When set, the MAC considers all frames, with up to 2,000 bytes length, as normal + * packets. When Bit 20 (Jumbo Enable) is not set, the MAC considers all received + * frames of size more than 2K bytes as Giant frames. + * + * When this bit is reset and Bit 20 (Jumbo Enable) is not set, the MAC considers + * all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as + * Giant frames. + * + * When Bit 20 (Jumbo Enable) is set, setting this bit has no effect on Giant Frame + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value. */ +#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */ +#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_CFG_TWOKPE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET(value) (((value) << 27) & 0x08000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_CFG. + */ +struct ALT_EMAC_GMAC_MAC_CFG_s +{ + uint32_t prelen : 2; /* Preamble Length for Transmit Frames */ + uint32_t re : 1; /* Receiver Enable */ + uint32_t te : 1; /* Transmitter Enable */ + uint32_t dc : 1; /* Deferral Check */ + uint32_t bl : 2; /* Back-Off Limit */ + uint32_t acs : 1; /* Automatic Pad or CRC Stripping */ + uint32_t lud : 1; /* Link Up or Down */ + uint32_t dr : 1; /* Disable Retry */ + uint32_t ipc : 1; /* Checksum Offload */ + uint32_t dm : 1; /* Duplex Mode */ + uint32_t lm : 1; /* Loopback Mode */ + uint32_t do_ : 1; /* Disable Receive Own */ + uint32_t fes : 1; /* Speed */ + uint32_t ps : 1; /* Port Select */ + uint32_t dcrs : 1; /* Disable Carrier Sense During Transmission */ + uint32_t ifg : 3; /* Inter-Frame Gap */ + uint32_t je : 1; /* Jumbo Frame Enable */ + uint32_t be : 1; /* Frame Burst Enable */ + uint32_t jd : 1; /* Jabber Disable */ + uint32_t wd : 1; /* Watchdog Disable */ + uint32_t tc : 1; /* Transmit Configuration in RGMII, SGMII, or SMII */ + uint32_t cst : 1; /* CRC Stripping of Type Frames */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t twokpe : 1; /* IEEE 802.3as support for 2K packets Enable */ + uint32_t : 4; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_CFG. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_CFG_s ALT_EMAC_GMAC_MAC_CFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_CFG register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_CFG_OFST 0x0 +/* The address of the ALT_EMAC_GMAC_MAC_CFG register. */ +#define ALT_EMAC_GMAC_MAC_CFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_CFG_OFST)) + +/* + * Register : Register 1 (MAC Frame Filter) - MAC_Frame_Filter + * + * The MAC Frame Filter register contains the filter controls for receiving frames. + * Some of the controls from this register go to the address check block of the + * MAC, which performs the first level of address filtering. The second level of + * filtering is performed on the incoming frame, based on other controls such as + * Pass Bad Frames and Pass Control Frames. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Promiscuous Mode + * [1] | RW | 0x0 | Hash Unicast + * [2] | RW | 0x0 | Hash Multicast + * [3] | RW | 0x0 | DA Inverse Filtering + * [4] | RW | 0x0 | Pass All Multicast + * [5] | RW | 0x0 | Disable Broadcast Frames + * [7:6] | RW | 0x0 | Pass Control Frames + * [8] | RW | 0x0 | SA Inverse Filtering + * [9] | RW | 0x0 | Source Address Filter Enable + * [10] | RW | 0x0 | Hash or Perfect Filter + * [15:11] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | VLAN Tag Filter Enable + * [19:17] | ??? | 0x0 | *UNDEFINED* + * [20] | RW | 0x0 | Layer 3 and Layer 4 Filter Enable + * [21] | RW | 0x0 | Drop non-TCP/UDP over IP Frames + * [30:22] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Receive All + * + */ +/* + * Field : Promiscuous Mode - pr + * + * When this bit is set, the Address Filter block passes all incoming frames + * regardless of its destination or source address. The SA or DA Filter Fails + * status bits of the Receive Status Word are always cleared when PR is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END | 0x1 | All Incoming Frames Passed + * ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD | 0x0 | Clear SA DA Status Bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PR + * + * All Incoming Frames Passed + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PR + * + * Clear SA DA Status Bits + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PR field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Hash Unicast - huc + * + * When set, MAC performs destination address filtering of unicast frames according + * to the hash table. + * + * When reset, the MAC performs a perfect destination address filtering for unicast + * frames, that is, it compares the DA field with the values programmed in DA + * registers. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END | 0x1 | MAC Filters with Hash Table + * ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD | 0x0 | MAC Filters with Compare + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HUC + * + * MAC Filters with Hash Table + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HUC + * + * MAC Filters with Compare + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Hash Multicast - hmc + * + * When set, MAC performs destination address filtering of received multicast + * frames according to the hash table. + * + * When reset, the MAC performs a perfect destination address filtering for + * multicast frames, that is, it compares the DA field with the values programmed + * in DA registers. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD | 0x0 | MAC Filters with Hash Table + * ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END | 0x1 | MAC Filters with Compare + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HMC + * + * MAC Filters with Hash Table + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HMC + * + * MAC Filters with Compare + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DA Inverse Filtering - daif + * + * When this bit is set, the Address Check block operates in inverse filtering mode + * for the DA address comparison for both unicast and multicast frames. + * + * When reset, normal filtering of frames is performed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD | 0x0 | Normal Inverse Filter + * ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END | 0x1 | Address Check Block Inverse Filter + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF + * + * Normal Inverse Filter + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF + * + * Address Check Block Inverse Filter + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Pass All Multicast - pm + * + * When set, this bit indicates that all received frames with a multicast + * destination address (first bit in the destination address field is '1') are + * passed. + * + * When reset, filtering of multicast frame depends on HMC bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD | 0x0 | Allows Filter of MC Frames + * ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END | 0x1 | All Rcvd MC Frames Pass + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PM + * + * Allows Filter of MC Frames + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PM + * + * All Rcvd MC Frames Pass + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PM field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Disable Broadcast Frames - dbf + * + * When this bit is set, the AFM block filters all incoming broadcast frames. In + * addition, it overrides all other filter settings. + * + * When this bit is reset, the AFM block passes all received broadcast frames. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD | 0x0 | Pass All Broadcast Frames + * ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END | 0x1 | Filter All Broadcast Frames + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DBF + * + * Pass All Broadcast Frames + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DBF + * + * Filter All Broadcast Frames + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Pass Control Frames - pcf + * + * These bits control the forwarding of all control frames (including unicast and + * multicast PAUSE frames). + * + * * 00: MAC filters all control frames from reaching the application. + * + * * 01: MAC forwards all control frames except PAUSE control frames to application + * even if they fail the Address filter. + * + * * 10: MAC forwards all control frames to application even if they fail the + * Address Filter. + * + * * 11: MAC forwards control frames that pass the Address Filter. + * + * The following conditions should be true for the PAUSE control frames processing: + * + * * Condition 1: The MAC is in the full-duplex mode and flow control is enabled by + * setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. + * + * * Condition 2: The destination address (DA) of the received frame matches the + * special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register + * 6 (Flow Control Register) is set. + * + * * Condition 3: The Type field of the received frame is 0x8808 and the OPCODE + * field is 0x0001. + * + * This field should be set to 01 only when the Condition 1 is true, that is, the + * MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. + * Otherwise, the PAUSE frame filtering may be inconsistent. When Condition 1 is + * false, the PAUSE frames are considered as generic control frames. Therefore, to + * pass all control frames (including PAUSE control frames) when the full-duplex + * mode and flow control is not enabled, you should set the PCF field to 10 or 11 + * (as required by the application). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:---------------------------------------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR | 0x0 | MAC filters all control frames + * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE | 0x1 | MAC forwards all control frames except PAUSE + * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL | 0x2 | MAC forwards all control frames fail addrflt + * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS | 0x3 | MAC forwards control frames that pass addrflt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF + * + * MAC filters all control frames + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF + * + * MAC forwards all control frames except PAUSE + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF + * + * MAC forwards all control frames fail addrflt + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL 0x2 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF + * + * MAC forwards control frames that pass addrflt + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_CLR_MSK 0xffffff3f +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET(value) (((value) << 6) & 0x000000c0) + +/* + * Field : SA Inverse Filtering - saif + * + * When this bit is set, the Address Check block operates in inverse filtering mode + * for the SA address comparison. The frames whose SA matches the SA registers are + * marked as failing the SA Address filter. + * + * When this bit is reset, frames whose SA does not match the SA registers are + * marked as failing the SA Address filter. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD | 0x0 | SA Nomatch Fail + * ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END | 0x1 | SA Match Fail + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF + * + * SA Nomatch Fail + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF + * + * SA Match Fail + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Source Address Filter Enable - saf + * + * When this bit is set, the MAC compares the SA field of the received frames with + * the values programmed in the enabled SA registers. If the comparison matches, + * then the SA Match bit of RxStatus Word is set high. When this bit is set high + * and the SA filter fails, the MAC drops the frame. + * + * When this bit is reset, the MAC forwards the received frame to the application + * and with the updated SA Match bit of the RxStatus depending on the SA address + * comparison. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD | 0x0 | SA Filter Off + * ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END | 0x1 | SA Filter On + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAF + * + * SA Filter Off + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAF + * + * SA Filter On + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Hash or Perfect Filter - hpf + * + * When this bit is set, it configures the address filter to pass a frame if it + * matches either the perfect filtering or the hash filtering as set by the HMC or + * HUC bits. + * + * When this bit is low and the HUC or HMC bit is set, the frame is passed only if + * it matches the Hash filter. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD | 0x0 | Hash or Perfect Filter off + * ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END | 0x1 | Hash or Perfect Filter on + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HPF + * + * Hash or Perfect Filter off + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HPF + * + * Hash or Perfect Filter on + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : VLAN Tag Filter Enable - vtfe + * + * When set, this bit enables the MAC to drop VLAN tagged frames that do not match + * the VLAN Tag comparison. + * + * When reset, the MAC forwards all frames irrespective of the match status of the + * VLAN Tag. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP | 0x0 | Forward all frames irrespective of the match + * : | | status of the VLAN tag + * ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP | 0x1 | Drop VLAN tagged frames that do not match the + * : | | VLAN Tag comparison + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE + * + * Forward all frames irrespective of the match status of the VLAN tag + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE + * + * Drop VLAN tagged frames that do not match the VLAN Tag comparison + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Layer 3 and Layer 4 Filter Enable - ipfe + * + * When set, this bit enables the MAC to drop frames that do not match the enabled + * Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for + * matching, this bit does not have any effect. + * + * When reset, the MAC forwards all frames irrespective of the match status of the + * Layer 3 and Layer 4 filters. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------ + * ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP | 0x0 | Forward all frames irrespective of the match + * : | | status of Layer 3 and Layer 4 filters + * ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP | 0x1 | Drop frames that do not match the enabled Layer + * : | | 3 and Layer 4 filters + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE + * + * Forward all frames irrespective of the match status of Layer 3 and Layer 4 + * filters + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE + * + * Drop frames that do not match the enabled Layer 3 and Layer 4 filters + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Drop non-TCP/UDP over IP Frames - dntu + * + * When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. + * The MAC forward only those frames that are processed by the Layer 4 filter. + * + * When reset, this bit enables the MAC to forward all non-TCP or UDP over IP + * frames. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------ + * ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP | 0x0 | Forward all non-TCP or UDP over IP frames + * ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP | 0x1 | Drop non-TCP or UDP over IP frames + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU + * + * Forward all non-TCP or UDP over IP frames + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU + * + * Drop non-TCP or UDP over IP frames + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Receive All - ra + * + * When this bit is set, the MAC Receiver block passes all received frames, + * irrespective of whether they pass the address filter or not, to the Application. + * The result of the SA or DA filtering is updated (pass or fail) in the + * corresponding bits in the Receive Status Word. + * + * When this bit is reset, the Receiver block passes only those frames to the + * Application that pass the SA or DA address filter. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD | 0x0 | Receive All off + * ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END | 0x1 | Receive All On + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_RA + * + * Receive All off + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_RA + * + * Receive All On + */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_FRM_FLT. + */ +struct ALT_EMAC_GMAC_MAC_FRM_FLT_s +{ + uint32_t pr : 1; /* Promiscuous Mode */ + uint32_t huc : 1; /* Hash Unicast */ + uint32_t hmc : 1; /* Hash Multicast */ + uint32_t daif : 1; /* DA Inverse Filtering */ + uint32_t pm : 1; /* Pass All Multicast */ + uint32_t dbf : 1; /* Disable Broadcast Frames */ + uint32_t pcf : 2; /* Pass Control Frames */ + uint32_t saif : 1; /* SA Inverse Filtering */ + uint32_t saf : 1; /* Source Address Filter Enable */ + uint32_t hpf : 1; /* Hash or Perfect Filter */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t vtfe : 1; /* VLAN Tag Filter Enable */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t ipfe : 1; /* Layer 3 and Layer 4 Filter Enable */ + uint32_t dntu : 1; /* Drop non-TCP/UDP over IP Frames */ + uint32_t : 9; /* *UNDEFINED* */ + uint32_t ra : 1; /* Receive All */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_FRM_FLT. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_FRM_FLT_s ALT_EMAC_GMAC_MAC_FRM_FLT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_FRM_FLT register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_OFST 0x4 +/* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register. */ +#define ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_FRM_FLT_OFST)) + +/* + * Register : Register 4 (GMII Address Register) - GMII_Address + * + * The GMII Address register controls the management cycles to the external PHY + * through the management interface. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [0] | RW | 0x0 | GMII Busy + * [1] | RW | 0x0 | GMII Write + * [5:2] | RW | 0x0 | CSR Clock Range + * [10:6] | RW | 0x0 | GMII Register + * [15:11] | RW | 0x0 | Physical Layer Address + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GMII Busy - gb + * + * This bit should read logic 0 before writing to Register 4 and Register 5. During + * a PHY or RevMII register access, the software sets this bit to 1'b1 to indicate + * that a Read or Write access is in progress. + * + * The Register 5 is invalid until this bit is cleared by the MAC. Therefore, + * Register 5 (GMII Data) should be kept valid until the MAC clears this bit during + * a PHY Write operation. Similarly for a read operation, the contents of Register + * 5 are not valid until this bit is cleared. + * + * The subsequent read or write operation should happen only after the previous + * operation is complete. Because there is no acknowledgment from the PHY to MAC + * after a read or write operation is completed, there is no change in the + * functionality of this bit even when the PHY is not present. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD | 0x0 | Not Busy + * ALT_EMAC_GMAC_GMII_ADDR_GB_E_END | 0x1 | Busy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GB + * + * Not Busy + */ +#define ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GB + * + * Busy + */ +#define ALT_EMAC_GMAC_GMII_ADDR_GB_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GB_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GB_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GB_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GB register field value. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GB_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GB register field value. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GB_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GB_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GB field value from a register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GB_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_GMII_ADDR_GB register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GB_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : GMII Write - gw + * + * When set, this bit indicates to the PHY or RevMII that this is a Write operation + * using the GMII Data register. If this bit is not set, it indicates that this is + * a Read operation, that is, placing the data in the GMII Data register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------------- + * ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD | 0x0 | Gmii Write Operation + * ALT_EMAC_GMAC_GMII_ADDR_GW_E_END | 0x1 | Gmii Read Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GW + * + * Gmii Write Operation + */ +#define ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GW + * + * Gmii Read Operation + */ +#define ALT_EMAC_GMAC_GMII_ADDR_GW_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GW_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GW_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GW_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GW register field value. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GW_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GW register field value. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GW_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GW_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GW field value from a register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GW_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_GMII_ADDR_GW register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GW_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : CSR Clock Range - cr + * + * The CSR Clock Range selection determines the frequency of the MDC clock + * according to the l3_sp_clk frequency used in your design. The suggested range of + * l3_sp_clk frequency applicable for each value (when Bit[5] = 0) ensures that the + * MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. + * + * When Bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE + * 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower + * value. For example, when l3_sp_clk is of 100 MHz frequency and you program these + * bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the + * limit of IEEE 802.3 specified range. Only use the values larger than 7 if the + * interfacing chips support faster MDC clocks. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42 | 0x0 | l3_sp_clk 60-100Mhz and MDC clock = + * : | | l3_sp_clk/42 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62 | 0x1 | l3_sp_clk 100-150Mhz and MDC clock = + * : | | l3_sp_clk/62 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16 | 0x2 | l3_sp_clk 25-35Mhz and MDC clock = l3_sp_clk/16 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26 | 0x3 | l3_sp_clk 35-60Mhz and MDC clock = l3_sp_clk/26 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102 | 0x4 | l3_sp_clk 150-250Mhz and MDC clock = + * : | | l3_sp_clk/102 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124 | 0x5 | l3_sp_clk 250-300Mhz and MDC clock = + * : | | l3_sp_clk/124 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4 | 0x8 | l3_sp_clk/4 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6 | 0x9 | l3_sp_clk/6 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8 | 0xa | l3_sp_clk/8 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10 | 0xb | l3_sp_clk/10 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12 | 0xc | l3_sp_clk/12 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14 | 0xd | l3_sp_clk/14 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN | 0xe | l3_sp_clk/16 + * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18 | 0xf | l3_sp_clk/18 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk 60-100Mhz and MDC clock = l3_sp_clk/42 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk 100-150Mhz and MDC clock = l3_sp_clk/62 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk 25-35Mhz and MDC clock = l3_sp_clk/16 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16 0x2 +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk 35-60Mhz and MDC clock = l3_sp_clk/26 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26 0x3 +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk 150-250Mhz and MDC clock = l3_sp_clk/102 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102 0x4 +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk 250-300Mhz and MDC clock = l3_sp_clk/124 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124 0x5 +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk/4 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4 0x8 +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk/6 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6 0x9 +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk/8 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8 0xa +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk/10 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10 0xb +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk/12 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12 0xc +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk/14 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14 0xd +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk/16 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN 0xe +/* + * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR + * + * l3_sp_clk/18 + */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18 0xf + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_WIDTH 4 +/* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_CR register field value. */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_SET_MSK 0x0000003c +/* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_CR register field value. */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_CLR_MSK 0xffffffc3 +/* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_GMII_ADDR_CR field value from a register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_GET(value) (((value) & 0x0000003c) >> 2) +/* Produces a ALT_EMAC_GMAC_GMII_ADDR_CR register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_CR_SET(value) (((value) << 2) & 0x0000003c) + +/* + * Field : GMII Register - gr + * + * These bits select the desired GMII register in the selected PHY device. + * + * For RevMII, these bits select the desired CSR register in the RevMII Registers + * set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GR_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GR_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GR_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GR register field value. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GR_SET_MSK 0x000007c0 +/* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GR register field value. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GR_CLR_MSK 0xfffff83f +/* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GR_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GR field value from a register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GR_GET(value) (((value) & 0x000007c0) >> 6) +/* Produces a ALT_EMAC_GMAC_GMII_ADDR_GR register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_GR_SET(value) (((value) << 6) & 0x000007c0) + +/* + * Field : Physical Layer Address - pa + * + * This field indicates which of the 32 possible PHY devices are being accessed. + * + * For RevMII, this field gives the PHY Address of the RevMII block. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_PA_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_PA_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_PA_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_PA register field value. */ +#define ALT_EMAC_GMAC_GMII_ADDR_PA_SET_MSK 0x0000f800 +/* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_PA register field value. */ +#define ALT_EMAC_GMAC_GMII_ADDR_PA_CLR_MSK 0xffff07ff +/* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */ +#define ALT_EMAC_GMAC_GMII_ADDR_PA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_GMII_ADDR_PA field value from a register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_PA_GET(value) (((value) & 0x0000f800) >> 11) +/* Produces a ALT_EMAC_GMAC_GMII_ADDR_PA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_PA_SET(value) (((value) << 11) & 0x0000f800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_GMII_ADDR. + */ +struct ALT_EMAC_GMAC_GMII_ADDR_s +{ + uint32_t gb : 1; /* GMII Busy */ + uint32_t gw : 1; /* GMII Write */ + uint32_t cr : 4; /* CSR Clock Range */ + uint32_t gr : 5; /* GMII Register */ + uint32_t pa : 5; /* Physical Layer Address */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_GMII_ADDR. */ +typedef volatile struct ALT_EMAC_GMAC_GMII_ADDR_s ALT_EMAC_GMAC_GMII_ADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_GMII_ADDR register from the beginning of the component. */ +#define ALT_EMAC_GMAC_GMII_ADDR_OFST 0x10 +/* The address of the ALT_EMAC_GMAC_GMII_ADDR register. */ +#define ALT_EMAC_GMAC_GMII_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GMII_ADDR_OFST)) + +/* + * Register : Register 5 (GMII Data Register) - GMII_Data + * + * The GMII Data register stores Write data to be written to the PHY register + * located at the address specified in Register 4 (GMII Address Register). This + * register also stores the Read data from the PHY register located at the address + * specified by Register 4. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [15:0] | RW | 0x0 | GMII Data + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GMII Data - gd + * + * This field contains the 16-bit data value read from the PHY or RevMII after a + * Management Read operation or the 16-bit data value to be written to the PHY or + * RevMII before a Management Write operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */ +#define ALT_EMAC_GMAC_GMII_DATA_GD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */ +#define ALT_EMAC_GMAC_GMII_DATA_GD_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */ +#define ALT_EMAC_GMAC_GMII_DATA_GD_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_GMII_DATA_GD register field value. */ +#define ALT_EMAC_GMAC_GMII_DATA_GD_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_GMII_DATA_GD register field value. */ +#define ALT_EMAC_GMAC_GMII_DATA_GD_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */ +#define ALT_EMAC_GMAC_GMII_DATA_GD_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_GMII_DATA_GD field value from a register. */ +#define ALT_EMAC_GMAC_GMII_DATA_GD_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_GMII_DATA_GD register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_GMII_DATA_GD_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_GMII_DATA. + */ +struct ALT_EMAC_GMAC_GMII_DATA_s +{ + uint32_t gd : 16; /* GMII Data */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_GMII_DATA. */ +typedef volatile struct ALT_EMAC_GMAC_GMII_DATA_s ALT_EMAC_GMAC_GMII_DATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_GMII_DATA register from the beginning of the component. */ +#define ALT_EMAC_GMAC_GMII_DATA_OFST 0x14 +/* The address of the ALT_EMAC_GMAC_GMII_DATA register. */ +#define ALT_EMAC_GMAC_GMII_DATA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GMII_DATA_OFST)) + +/* + * Register : Register 6 (Flow Control Register) - Flow_Control + * + * The Flow Control register controls the generation and reception of the Control + * (Pause Command) frames by the MAC's Flow control block. A Write to a register + * with the Busy bit set to '1' triggers the Flow Control block to generate a Pause + * Control frame. The fields of the control frame are selected as specified in the + * 802.3x specification, and the Pause Time value from this register is used in the + * Pause Time field of the control frame. The Busy bit remains set until the + * control frame is transferred onto the cable. The Host must make sure that the + * Busy bit is cleared before writing to the register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | Flow Control Busy or Backpressure Activate + * [1] | RW | 0x0 | Transmit Flow Control Enable + * [2] | RW | 0x0 | Receive Flow Control Enable + * [3] | RW | 0x0 | Unicast Pause Frame Detect + * [5:4] | RW | 0x0 | Pause Low Threshold + * [6] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | Disable Zero-Quanta Pause + * [15:8] | ??? | 0x0 | *UNDEFINED* + * [31:16] | RW | 0x0 | Pause Time + * + */ +/* + * Field : Flow Control Busy or Backpressure Activate - fca_bpa + * + * This bit initiates a Pause Control frame in the full-duplex mode and activates + * the backpressure function in the half-duplex mode if the TFE bit is set. + * + * In the full-duplex mode, this bit should be read as 1'b0 before writing to the + * Flow Control register. To initiate a Pause control frame, the Application must + * set this bit to 1'b1. During a transfer of the Control Frame, this bit continues + * to be set to signify that a frame transmission is in progress. After the + * completion of Pause control frame transmission, the MAC resets this bit to 1'b0. + * The Flow Control register should not be written to until this bit is cleared. + * + * In the half-duplex mode, when this bit is set (and TFE is set), then + * backpressure is asserted by the MAC. During backpressure, when the MAC receives + * a new frame, the transmitter starts sending a JAM pattern resulting in a + * collision. This control register bit is logically ORed with the mti_flowctrl_i + * input signal for the backpressure function. When the MAC is configured for the + * full-duplex mode, the BPA is automatically disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------ + * ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD | 0x0 | Pause Ctrl Frame and BPA off + * ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END | 0x1 | Init Pause Ctrl Frame and BPA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA + * + * Pause Ctrl Frame and BPA off + */ +#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA + * + * Init Pause Ctrl Frame and BPA + */ +#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA field value from a register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit Flow Control Enable - tfe + * + * In the full-duplex mode, when this bit is set, the MAC enables the flow control + * operation to transmit Pause frames. When this bit is reset, the flow control + * operation in the MAC is disabled, and the MAC does not transmit any Pause + * frames. + * + * In half-duplex mode, when this bit is set, the MAC enables the back-pressure + * operation. When this bit is reset, the back-pressure feature is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD | 0x0 | Transmit Flow Control Disable + * ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END | 0x1 | Transmit Flow Control Enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE + * + * Transmit Flow Control Disable + */ +#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE + * + * Transmit Flow Control Enable + */ +#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_TFE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_TFE_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_TFE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_TFE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_TFE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_TFE field value from a register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_TFE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_FLOW_CTL_TFE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive Flow Control Enable - rfe + * + * When this bit is set, the MAC decodes the received Pause frame and disables its + * transmitter for a specified (Pause) time. When this bit is reset, the decode + * function of the Pause frame is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------- + * ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD | 0x0 | Decode Func. of Pause Frame Disabled + * ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END | 0x1 | MAC decodes the received Pause + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE + * + * Decode Func. of Pause Frame Disabled + */ +#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE + * + * MAC decodes the received Pause + */ +#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_RFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_RFE_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_RFE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_RFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_RFE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_RFE field value from a register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_RFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_FLOW_CTL_RFE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Unicast Pause Frame Detect - up + * + * When this bit is set, then in addition to the detecting Pause frames with the + * unique multicast address, the MAC detects the Pause frames with the station's + * unicast address specified in the MAC Address0 High Register and MAC Address0 Low + * Register. When this bit is reset, the MAC detects only a Pause frame with the + * unique multicast address specified in the 802.3x standard. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------ + * ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD | 0x0 | MAC Detects Pause MCA + * ALT_EMAC_GMAC_FLOW_CTL_UP_E_END | 0x1 | MAC Detects Pause MCA and UCA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP + * + * MAC Detects Pause MCA + */ +#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP + * + * MAC Detects Pause MCA and UCA + */ +#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_UP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_UP_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_UP_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_UP register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_UP register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_UP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_UP_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_UP field value from a register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_UP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_FLOW_CTL_UP register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Pause Low Threshold - plt + * + * This field configures the threshold of the PAUSE timer at which the input flow + * control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic + * retransmission of PAUSE Frame. + * + * The threshold values should be always less than the Pause Time configured in + * Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a + * second PAUSE frame is automatically transmitted if the mti_flowctrl_i signal is + * asserted at 228 (256 - 28) slot times after the first PAUSE frame is + * transmitted. + * + * The slot time is defined as the time taken to transmit 512 bits (64 bytes) on + * the GMII or MII interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------- + * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4 | 0x0 | Pause time - 4 slot times + * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28 | 0x1 | Pause time - 28 slot times + * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144 | 0x2 | Pause time - 144 slot times + * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256 | 0x3 | Pause time - 256 slot times + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT + * + * Pause time - 4 slot times + */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT + * + * Pause time - 28 slot times + */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT + * + * Pause time - 144 slot times + */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144 0x2 +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT + * + * Pause time - 256 slot times + */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET_MSK 0x00000030 +/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_CLR_MSK 0xffffffcf +/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_PLT field value from a register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_EMAC_GMAC_FLOW_CTL_PLT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET(value) (((value) << 4) & 0x00000030) + +/* + * Field : Disable Zero-Quanta Pause - dzpq + * + * When this bit is set, it disables the automatic generation of the Zero-Quanta + * Pause Control frames on the de-assertion of the flow-control signal from the + * FIFO layer (MTL or external sideband flow control signal + * sbd_flowctrl_i/mti_flowctrl_i). + * + * When this bit is reset, normal operation with automatic Zero-Quanta Pause + * Control frame generation is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------------------------------- + * ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END | 0x1 | Disable Auto Gen. of Zero-Quanta Pause + * ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD | 0x0 | Enable Auto Gen. of Zero-Quanta Pause + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ + * + * Disable Auto Gen. of Zero-Quanta Pause + */ +#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ + * + * Enable Auto Gen. of Zero-Quanta Pause + */ +#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_DZPQ field value from a register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Pause Time - pt + * + * This field holds the value to be used in the Pause Time field in the transmit + * control frame. Because the Pause Time bits are double-synchronized to the (G)MII + * clock domain, then consecutive writes to this register should be performed only + * after at least four clock cycles in the destination clock domain. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PT_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PT register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PT register field value. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PT_CLR_MSK 0x0000ffff +/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_PT field value from a register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PT_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_EMAC_GMAC_FLOW_CTL_PT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_FLOW_CTL. + */ +struct ALT_EMAC_GMAC_FLOW_CTL_s +{ + uint32_t fca_bpa : 1; /* Flow Control Busy or Backpressure Activate */ + uint32_t tfe : 1; /* Transmit Flow Control Enable */ + uint32_t rfe : 1; /* Receive Flow Control Enable */ + uint32_t up : 1; /* Unicast Pause Frame Detect */ + uint32_t plt : 2; /* Pause Low Threshold */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t dzpq : 1; /* Disable Zero-Quanta Pause */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t pt : 16; /* Pause Time */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_FLOW_CTL. */ +typedef volatile struct ALT_EMAC_GMAC_FLOW_CTL_s ALT_EMAC_GMAC_FLOW_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_FLOW_CTL register from the beginning of the component. */ +#define ALT_EMAC_GMAC_FLOW_CTL_OFST 0x18 +/* The address of the ALT_EMAC_GMAC_FLOW_CTL register. */ +#define ALT_EMAC_GMAC_FLOW_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_FLOW_CTL_OFST)) + +/* + * Register : Register 7 (VLAN Tag Register) - VLAN_Tag + * + * The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN + * frames. The MAC compares the 13th and 14th bytes of the receiving frame + * (Length/Type) with 16'h8100, and the following two bytes are compared with the + * VLAN tag. If a match occurs, the MAC sets the received VLAN bit in the receive + * frame status. The legal length of the frame is increased from 1,518 bytes to + * 1,522 bytes. + * + * Because the VLAN Tag register is double-synchronized to the (G)MII clock domain, + * then consecutive writes to these register should be performed only after at + * least four clock cycles in the destination clock domain. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [15:0] | RW | 0x0 | VLAN Tag Identifier for Receive Frames + * [16] | RW | 0x0 | Enable 12-Bit VLAN Tag Comparison + * [17] | RW | 0x0 | VLAN Tag Inverse Match Enable + * [18] | RW | 0x0 | Enable S-VLAN + * [19] | RW | 0x0 | VLAN Tag Hash Table Match Enable + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : VLAN Tag Identifier for Receive Frames - vl + * + * This field contains the 802.1Q VLAN tag to identify the VLAN frames and is + * compared to the 15th and 16th bytes of the frames being received for VLAN + * frames. The following list describes the bits of this field: + * + * * Bits [15:13]: User Priority + * + * * Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) + * + * * Bits[11:0]: VLAN tag's VLAN Identifier (VID) field + * + * When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. + * + * If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the + * fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a + * Type field value of 0x8100 or 0x88a8 as VLAN frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VL_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VL_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VL register field value. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VL register field value. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VL_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VL field value from a register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_VLAN_TAG_VL register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VL_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Enable 12-Bit VLAN Tag Comparison - etv + * + * When this bit is set, a 12-bit VLAN identifier is used for comparing and + * filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are + * compared with the corresponding field in the received VLAN-tagged frame. + * Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are + * used for hash-based VLAN filtering. + * + * When this bit is reset, all 16 bits of the 15th and 16th bytes of the received + * VLAN frame are used for comparison and VLAN hash filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:-------------------------------- + * ALT_EMAC_GMAC_VLAN_TAG_ETV_E_DISD | 0x0 | Disable 12-Bit VLAN Tag Compare + * ALT_EMAC_GMAC_VLAN_TAG_ETV_E_END | 0x1 | Enable 12-Bit VLAN Tag Compare + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_VLAN_TAG_ETV + * + * Disable 12-Bit VLAN Tag Compare + */ +#define ALT_EMAC_GMAC_VLAN_TAG_ETV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_VLAN_TAG_ETV + * + * Enable 12-Bit VLAN Tag Compare + */ +#define ALT_EMAC_GMAC_VLAN_TAG_ETV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ETV_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ETV_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ETV_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_ETV register field value. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ETV_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_ETV register field value. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ETV_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ETV_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_VLAN_TAG_ETV field value from a register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ETV_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_VLAN_TAG_ETV register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ETV_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : VLAN Tag Inverse Match Enable - vtim + * + * When set, this bit enables the VLAN Tag inverse matching. The frames that do not + * have matching VLAN Tag are marked as matched. + * + * When reset, this bit enables the VLAN Tag perfect matching. The frames with + * matched VLAN Tag are marked as matched. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_MSB 17 +/* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_SET_MSK 0x00020000 +/* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_CLR_MSK 0xfffdffff +/* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VTIM field value from a register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Enable S-VLAN - esvl + * + * When this bit is set, the MAC transmitter and receiver also consider the S-VLAN + * (Type = 0x88A8) frames as valid VLAN tagged frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_VLAN_TAG_ESVL field value from a register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : VLAN Tag Hash Table Match Enable - vthm + * + * When set, the most significant four bits of the VLAN tag's CRC are used to index + * the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN + * Hash Table register, corresponding to the index, indicates that the frame + * matched the VLAN hash table. + * + * When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used + * for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used + * for comparison. + * + * When reset, the VLAN Hash Match operation is not performed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VTHM field value from a register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_SET(value) (((value) << 19) & 0x00080000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_VLAN_TAG. + */ +struct ALT_EMAC_GMAC_VLAN_TAG_s +{ + uint32_t vl : 16; /* VLAN Tag Identifier for Receive Frames */ + uint32_t etv : 1; /* Enable 12-Bit VLAN Tag Comparison */ + uint32_t vtim : 1; /* VLAN Tag Inverse Match Enable */ + uint32_t esvl : 1; /* Enable S-VLAN */ + uint32_t vthm : 1; /* VLAN Tag Hash Table Match Enable */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_VLAN_TAG. */ +typedef volatile struct ALT_EMAC_GMAC_VLAN_TAG_s ALT_EMAC_GMAC_VLAN_TAG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_VLAN_TAG register from the beginning of the component. */ +#define ALT_EMAC_GMAC_VLAN_TAG_OFST 0x1c +/* The address of the ALT_EMAC_GMAC_VLAN_TAG register. */ +#define ALT_EMAC_GMAC_VLAN_TAG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_TAG_OFST)) + +/* + * Register : Register 8 (Version Register) - Version + * + * The Version registers identifies the version of the EMAC. This register contains + * two bytes: one specified by Synopsys to identify the core release number, and + * the other specified by Altera. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------- + * [7:0] | R | 0x37 | ALT_EMAC_GMAC_VER_SNPSVER + * [15:8] | R | 0x10 | ALT_EMAC_GMAC_VER_USERVER + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : snpsver + * + * Synopsys-defined Version (3.7) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VER_SNPSVER register field. */ +#define ALT_EMAC_GMAC_VER_SNPSVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VER_SNPSVER register field. */ +#define ALT_EMAC_GMAC_VER_SNPSVER_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_VER_SNPSVER register field. */ +#define ALT_EMAC_GMAC_VER_SNPSVER_WIDTH 8 +/* The mask used to set the ALT_EMAC_GMAC_VER_SNPSVER register field value. */ +#define ALT_EMAC_GMAC_VER_SNPSVER_SET_MSK 0x000000ff +/* The mask used to clear the ALT_EMAC_GMAC_VER_SNPSVER register field value. */ +#define ALT_EMAC_GMAC_VER_SNPSVER_CLR_MSK 0xffffff00 +/* The reset value of the ALT_EMAC_GMAC_VER_SNPSVER register field. */ +#define ALT_EMAC_GMAC_VER_SNPSVER_RESET 0x37 +/* Extracts the ALT_EMAC_GMAC_VER_SNPSVER field value from a register. */ +#define ALT_EMAC_GMAC_VER_SNPSVER_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_EMAC_GMAC_VER_SNPSVER register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VER_SNPSVER_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : userver + * + * Altera-defined Version + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VER_USERVER register field. */ +#define ALT_EMAC_GMAC_VER_USERVER_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VER_USERVER register field. */ +#define ALT_EMAC_GMAC_VER_USERVER_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_VER_USERVER register field. */ +#define ALT_EMAC_GMAC_VER_USERVER_WIDTH 8 +/* The mask used to set the ALT_EMAC_GMAC_VER_USERVER register field value. */ +#define ALT_EMAC_GMAC_VER_USERVER_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_EMAC_GMAC_VER_USERVER register field value. */ +#define ALT_EMAC_GMAC_VER_USERVER_CLR_MSK 0xffff00ff +/* The reset value of the ALT_EMAC_GMAC_VER_USERVER register field. */ +#define ALT_EMAC_GMAC_VER_USERVER_RESET 0x10 +/* Extracts the ALT_EMAC_GMAC_VER_USERVER field value from a register. */ +#define ALT_EMAC_GMAC_VER_USERVER_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_EMAC_GMAC_VER_USERVER register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VER_USERVER_SET(value) (((value) << 8) & 0x0000ff00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_VER. + */ +struct ALT_EMAC_GMAC_VER_s +{ + const uint32_t snpsver : 8; /* ALT_EMAC_GMAC_VER_SNPSVER */ + const uint32_t userver : 8; /* ALT_EMAC_GMAC_VER_USERVER */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_VER. */ +typedef volatile struct ALT_EMAC_GMAC_VER_s ALT_EMAC_GMAC_VER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_VER register from the beginning of the component. */ +#define ALT_EMAC_GMAC_VER_OFST 0x20 +/* The address of the ALT_EMAC_GMAC_VER register. */ +#define ALT_EMAC_GMAC_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VER_OFST)) + +/* + * Register : Register 9 (Debug Register) - Debug + * + * The Debug register gives the status of all main blocks of the transmit and + * receive data-paths and the FIFOs. An all-zero status indicates that the MAC is + * in idle state (and FIFOs are empty) and no activity is going on in the data- + * paths. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------ + * [0] | R | 0x0 | MAC GMII or MII Receive Protocol Engine Status + * [2:1] | R | 0x0 | MAC Receive Frame Controller FIFO Status + * [3] | ??? | 0x0 | *UNDEFINED* + * [4] | R | 0x0 | MTL Rx FIFO Write Controller Active Status + * [6:5] | R | 0x0 | MTL Rx FIFO Read Controller State + * [7] | ??? | 0x0 | *UNDEFINED* + * [9:8] | R | 0x0 | MTL Rx FIFO Fill-level Status + * [15:10] | ??? | 0x0 | *UNDEFINED* + * [16] | R | 0x0 | MAC GMII or MII Transmit Protocol Engine Status + * [18:17] | R | 0x0 | MAC Transmit Frame Controller Status + * [19] | R | 0x0 | MAC transmitter in PAUSE + * [21:20] | R | 0x0 | MTL Tx FIFO Read Controller Status + * [22] | R | 0x0 | MTL Tx FIFO Write Controller Active Status + * [23] | ??? | 0x0 | *UNDEFINED* + * [24] | R | 0x0 | MTL Tx FIFO Not Empty Status + * [25] | R | 0x0 | MTL TxStatus FIFO Full Status + * [31:26] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MAC GMII or MII Receive Protocol Engine Status - rpests + * + * When high, this bit indicates that the MAC GMII or MII receive protocol engine + * is actively receiving data and not in IDLE state. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------- + * ALT_EMAC_GMAC_DBG_RPESTS_E_INACT | 0x0 | Idle State + * ALT_EMAC_GMAC_DBG_RPESTS_E_ACT | 0x1 | Protocol Engine Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RPESTS + * + * Idle State + */ +#define ALT_EMAC_GMAC_DBG_RPESTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RPESTS + * + * Protocol Engine Active + */ +#define ALT_EMAC_GMAC_DBG_RPESTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RPESTS register field. */ +#define ALT_EMAC_GMAC_DBG_RPESTS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RPESTS register field. */ +#define ALT_EMAC_GMAC_DBG_RPESTS_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_DBG_RPESTS register field. */ +#define ALT_EMAC_GMAC_DBG_RPESTS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_DBG_RPESTS register field value. */ +#define ALT_EMAC_GMAC_DBG_RPESTS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_RPESTS register field value. */ +#define ALT_EMAC_GMAC_DBG_RPESTS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_DBG_RPESTS register field. */ +#define ALT_EMAC_GMAC_DBG_RPESTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_RPESTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_RPESTS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_DBG_RPESTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_RPESTS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MAC Receive Frame Controller FIFO Status - rfcfcsts + * + * When high, this field indicates the active state of the small FIFO Read and + * Write controllers of the MAC Receive Frame Controller Module. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------- + * ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT | 0x0 | Disable Active State FIFO Read Write + * ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT | 0x1 | Enable Active State FIFO Read Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RFCFCSTS + * + * Disable Active State FIFO Read Write + */ +#define ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RFCFCSTS + * + * Enable Active State FIFO Read Write + */ +#define ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RFCFCSTS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RFCFCSTS_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RFCFCSTS_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_DBG_RFCFCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_RFCFCSTS_SET_MSK 0x00000006 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_RFCFCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_RFCFCSTS_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RFCFCSTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_RFCFCSTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_RFCFCSTS_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_EMAC_GMAC_DBG_RFCFCSTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_RFCFCSTS_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : MTL Rx FIFO Write Controller Active Status - rwcsts + * + * When high, this bit indicates that the MTL Rx FIFO Write Controller is active + * and is transferring a received frame to the FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------------- + * ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT | 0x0 | MTL Rx Fifo Controller Non-Active Status + * ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT | 0x1 | MTL Rx Fifo Controller Active Status + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RWCSTS + * + * MTL Rx Fifo Controller Non-Active Status + */ +#define ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RWCSTS + * + * MTL Rx Fifo Controller Active Status + */ +#define ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RWCSTS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RWCSTS_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RWCSTS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_DBG_RWCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_RWCSTS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_RWCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_RWCSTS_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RWCSTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_RWCSTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_RWCSTS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_DBG_RWCSTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_RWCSTS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MTL Rx FIFO Read Controller State - rrcsts + * + * This field gives the state of the Rx FIFO read Controller + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE | 0x0 | IDLE State + * ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA | 0x1 | Reading Frame Data + * ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT | 0x2 | Reading Frame Status (or timestamp) + * ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS | 0x3 | Flushing Frame Data and Status + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS + * + * IDLE State + */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS + * + * Reading Frame Data + */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS + * + * Reading Frame Status (or timestamp) + */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT 0x2 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS + * + * Flushing Frame Data and Status + */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_MSB 6 +/* The width in bits of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_DBG_RRCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_SET_MSK 0x00000060 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_RRCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_CLR_MSK 0xffffff9f +/* The reset value of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_RRCSTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_GET(value) (((value) & 0x00000060) >> 5) +/* Produces a ALT_EMAC_GMAC_DBG_RRCSTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_RRCSTS_SET(value) (((value) << 5) & 0x00000060) + +/* + * Field : MTL Rx FIFO Fill-level Status - rxfsts + * + * This field gives the status of the fill-level of the Rx FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY | 0x0 | Rx FIFO Empty + * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL | 0x1 | Rx FIFO fill-level below flow-control deactivate + * : | | thres. + * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL | 0x2 | Rx FIFO fill-level above flow-control activate + * : | | thres. + * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL | 0x3 | Rx FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS + * + * Rx FIFO Empty + */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS + * + * Rx FIFO fill-level below flow-control deactivate thres. + */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS + * + * Rx FIFO fill-level above flow-control activate thres. + */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL 0x2 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS + * + * Rx FIFO Full + */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_DBG_RXFSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_SET_MSK 0x00000300 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_RXFSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_CLR_MSK 0xfffffcff +/* The reset value of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_RXFSTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_EMAC_GMAC_DBG_RXFSTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_RXFSTS_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : MAC GMII or MII Transmit Protocol Engine Status - tpests + * + * When high, this bit indicates that the MAC GMII or MII transmit protocol engine + * is actively transmitting data and is not in the IDLE state. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_DBG_TPESTS_E_DISD | 0x0 | Idle State + * ALT_EMAC_GMAC_DBG_TPESTS_E_END | 0x1 | Actively Transmitting Data + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TPESTS + * + * Idle State + */ +#define ALT_EMAC_GMAC_DBG_TPESTS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TPESTS + * + * Actively Transmitting Data + */ +#define ALT_EMAC_GMAC_DBG_TPESTS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TPESTS register field. */ +#define ALT_EMAC_GMAC_DBG_TPESTS_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TPESTS register field. */ +#define ALT_EMAC_GMAC_DBG_TPESTS_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_DBG_TPESTS register field. */ +#define ALT_EMAC_GMAC_DBG_TPESTS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_DBG_TPESTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TPESTS_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_TPESTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TPESTS_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_DBG_TPESTS register field. */ +#define ALT_EMAC_GMAC_DBG_TPESTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_TPESTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_TPESTS_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_DBG_TPESTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_TPESTS_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MAC Transmit Frame Controller Status - tfcsts + * + * This field indicates the state of the MAC Transmit Frame Controller block + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE | 0x0 | Idle State + * ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG | 0x1 | Waiting Prev. State or IFG + * ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE | 0x2 | Generating Tx Pause + * ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM | 0x3 | Tx Input Frame + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS + * + * Idle State + */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS + * + * Waiting Prev. State or IFG + */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS + * + * Generating Tx Pause + */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE 0x2 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS + * + * Tx Input Frame + */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_DBG_TFCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_SET_MSK 0x00060000 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_TFCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_CLR_MSK 0xfff9ffff +/* The reset value of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_TFCSTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_GET(value) (((value) & 0x00060000) >> 17) +/* Produces a ALT_EMAC_GMAC_DBG_TFCSTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_TFCSTS_SET(value) (((value) << 17) & 0x00060000) + +/* + * Field : MAC transmitter in PAUSE - txpaused + * + * When high, this bit indicates that the MAC transmitter is in the PAUSE condition + * (in the full-duplex only mode) and hence does not schedule any frame for + * transmission. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------------------------- + * ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS | 0x0 | MAC Transmitter Pause Disabled + * ALT_EMAC_GMAC_DBG_TXPAUSED_E_END | 0x1 | MAC Transmitter Pause Condition + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXPAUSED + * + * MAC Transmitter Pause Disabled + */ +#define ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXPAUSED + * + * MAC Transmitter Pause Condition + */ +#define ALT_EMAC_GMAC_DBG_TXPAUSED_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */ +#define ALT_EMAC_GMAC_DBG_TXPAUSED_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */ +#define ALT_EMAC_GMAC_DBG_TXPAUSED_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */ +#define ALT_EMAC_GMAC_DBG_TXPAUSED_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_DBG_TXPAUSED register field value. */ +#define ALT_EMAC_GMAC_DBG_TXPAUSED_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_TXPAUSED register field value. */ +#define ALT_EMAC_GMAC_DBG_TXPAUSED_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */ +#define ALT_EMAC_GMAC_DBG_TXPAUSED_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_TXPAUSED field value from a register. */ +#define ALT_EMAC_GMAC_DBG_TXPAUSED_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_DBG_TXPAUSED register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_TXPAUSED_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MTL Tx FIFO Read Controller Status - trcsts + * + * This field indicates the state of the Tx FIFO Read Controller + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------- + * ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE | 0x0 | Idle State + * ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE | 0x1 | Read State (transferring data to the MAC + * : | | transmitter) + * ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT | 0x2 | Waiting for TxStatus from the MAC transmitter + * ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT | 0x3 | Writing the received TxStatus or flushing the Tx + * : | | FIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS + * + * Idle State + */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS + * + * Read State (transferring data to the MAC transmitter) + */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS + * + * Waiting for TxStatus from the MAC transmitter + */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT 0x2 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS + * + * Writing the received TxStatus or flushing the Tx FIFO + */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_DBG_TRCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_SET_MSK 0x00300000 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_TRCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_CLR_MSK 0xffcfffff +/* The reset value of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_TRCSTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_EMAC_GMAC_DBG_TRCSTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_TRCSTS_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : MTL Tx FIFO Write Controller Active Status - twcsts + * + * When high, this bit indicates that the MTL Tx FIFO Write Controller is active + * and transferring data to the Tx FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT | 0x0 | Tx FIFO Write Ctrl Inactive + * ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT | 0x1 | Tx FIFO Write Ctrl Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TWCSTS + * + * Tx FIFO Write Ctrl Inactive + */ +#define ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TWCSTS + * + * Tx FIFO Write Ctrl Active + */ +#define ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TWCSTS_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TWCSTS_MSB 22 +/* The width in bits of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TWCSTS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_DBG_TWCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TWCSTS_SET_MSK 0x00400000 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_TWCSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TWCSTS_CLR_MSK 0xffbfffff +/* The reset value of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TWCSTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_TWCSTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_TWCSTS_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_EMAC_GMAC_DBG_TWCSTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_TWCSTS_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MTL Tx FIFO Not Empty Status - txfsts + * + * When high, this bit indicates that the MTL Tx FIFO is not empty and some data is + * left for transmission. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------- + * ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT | 0x0 | MTL Tx FIFO Empty + * ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT | 0x1 | MTL Tx FIFO Not Empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXFSTS + * + * MTL Tx FIFO Empty + */ +#define ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXFSTS + * + * MTL Tx FIFO Not Empty + */ +#define ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TXFSTS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TXFSTS_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TXFSTS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_DBG_TXFSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TXFSTS_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_TXFSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TXFSTS_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TXFSTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_TXFSTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_TXFSTS_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_DBG_TXFSTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_TXFSTS_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MTL TxStatus FIFO Full Status - txstsfsts + * + * When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the + * MTL cannot accept any more frames for transmission. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------- + * ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT | 0x0 | MTL TxStatus FIFO Not Full Status + * ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT | 0x1 | MTL TxStatus FIFO Full Status + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXSTSFSTS + * + * MTL TxStatus FIFO Not Full Status + */ +#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXSTSFSTS + * + * MTL TxStatus FIFO Full Status + */ +#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value. */ +#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */ +#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_DBG_TXSTSFSTS field value from a register. */ +#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_DBG. + */ +struct ALT_EMAC_GMAC_DBG_s +{ + const uint32_t rpests : 1; /* MAC GMII or MII Receive Protocol Engine Status */ + const uint32_t rfcfcsts : 2; /* MAC Receive Frame Controller FIFO Status */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t rwcsts : 1; /* MTL Rx FIFO Write Controller Active Status */ + const uint32_t rrcsts : 2; /* MTL Rx FIFO Read Controller State */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t rxfsts : 2; /* MTL Rx FIFO Fill-level Status */ + uint32_t : 6; /* *UNDEFINED* */ + const uint32_t tpests : 1; /* MAC GMII or MII Transmit Protocol Engine Status */ + const uint32_t tfcsts : 2; /* MAC Transmit Frame Controller Status */ + const uint32_t txpaused : 1; /* MAC transmitter in PAUSE */ + const uint32_t trcsts : 2; /* MTL Tx FIFO Read Controller Status */ + const uint32_t twcsts : 1; /* MTL Tx FIFO Write Controller Active Status */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t txfsts : 1; /* MTL Tx FIFO Not Empty Status */ + const uint32_t txstsfsts : 1; /* MTL TxStatus FIFO Full Status */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_DBG. */ +typedef volatile struct ALT_EMAC_GMAC_DBG_s ALT_EMAC_GMAC_DBG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_DBG register from the beginning of the component. */ +#define ALT_EMAC_GMAC_DBG_OFST 0x24 +/* The address of the ALT_EMAC_GMAC_DBG register. */ +#define ALT_EMAC_GMAC_DBG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_DBG_OFST)) + +/* + * Register : Register 12 (LPI Control and Status Register) - LPI_Control_Status + * + * The LPI Control and Status Register controls the LPI functions and provides the + * LPI interrupt status. The status bits are cleared when this register is read. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Transmit LPI Entry + * [1] | R | 0x0 | Transmit LPI Exit + * [2] | R | 0x0 | Receive LPI Entry + * [3] | R | 0x0 | Receive LPI Exit + * [7:4] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | Transmit LPI State + * [9] | R | 0x0 | Receive LPI State + * [15:10] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | LPI Enable + * [17] | RW | 0x0 | PHY Link Status + * [18] | RW | 0x0 | PHY Link Status Enable + * [19] | RW | 0x0 | LPI TX Automate + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit LPI Entry - tlpien + * + * When set, this bit indicates that the MAC Transmitter has entered the LPI state + * because of the setting of the LPIEN bit. This bit is cleared by a read into this + * register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------------------- + * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT | 0x0 | MAC Transmitter Not in LPI State + * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT | 0x1 | MAC Transmitter Entered LPI State + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN + * + * MAC Transmitter Not in LPI State + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN + * + * MAC Transmitter Entered LPI State + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN field value from a register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit LPI Exit - tlpiex + * + * When set, this bit indicates that the MAC transmitter has exited the LPI state + * after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This + * bit is cleared by a read into this register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT | 0x0 | MAC Transmitter Non LPI State + * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT | 0x1 | MAC Transmitter Exited LPI State + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX + * + * MAC Transmitter Non LPI State + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX + * + * MAC Transmitter Exited LPI State + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX field value from a register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive LPI Entry - rlpien + * + * When set, this bit indicates that the MAC Receiver has received an LPI pattern + * and entered the LPI state. This bit is cleared by a read into this register. + * + * Note: + * + * This bit may not get set if the MAC stops receiving the LPI pattern for a very + * short duration, such as, less than 3 clock cycles of l3_sp_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------ + * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT | 0x0 | MAC Receiver Not In LPI State + * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT | 0x1 | MAC Receiver In LPI State + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN + * + * MAC Receiver Not In LPI State + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN + * + * MAC Receiver In LPI State + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN field value from a register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive LPI Exit - rlpiex + * + * When set, this bit indicates that the MAC Receiver has stopped receiving the LPI + * pattern on the GMII or MII interface, exited the LPI state, and resumed the + * normal reception. This bit is cleared by a read into this register. + * + * Note: + * + * This bit may not get set if the MAC stops receiving the LPI pattern for a very + * short duration, such as, less than 3 clock cycles of l3_sp_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT | 0x0 | MAC RX receiving LPI Patterns + * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT | 0x1 | MAC RX Stopped receiving LPI Patterns + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX + * + * MAC RX receiving LPI Patterns + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX + * + * MAC RX Stopped receiving LPI Patterns + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX field value from a register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Transmit LPI State - tlpist + * + * When set, this bit indicates that the MAC is transmitting the LPI pattern on the + * GMII or MII interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT | 0x0 | MAC Transmitting LPI Pattern + * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT | 0x1 | MAC Transmitting LPI Pattern + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST + * + * MAC Transmitting LPI Pattern + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST + * + * MAC Transmitting LPI Pattern + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST field value from a register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Receive LPI State - rlpist + * + * When set, this bit indicates that the MAC is receiving the LPI pattern on the + * GMII or MII interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT | 0x0 | MAC is not receiving LPI Pattern + * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT | 0x1 | MAC receiving LPI Pattern + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST + * + * MAC is not receiving LPI Pattern + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST + * + * MAC receiving LPI Pattern + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST field value from a register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : LPI Enable - lpien + * + * When set, this bit instructs the MAC Transmitter to enter the LPI state. When + * reset, this bit instructs the MAC to exit the LPI state and resume normal + * transmission. + * + * This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state + * because of the arrival of a new packet for transmission. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD | 0x0 | MAC Transmitter exit LPI State + * ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END | 0x1 | MAC Transmitter enters LPI State + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN + * + * MAC Transmitter exit LPI State + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN + * + * MAC Transmitter enters LPI State + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN field value from a register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : PHY Link Status - pls + * + * This bit indicates the link status of the PHY. The MAC Transmitter asserts the + * LPI pattern only when the link status is up (okay) at least for the time + * indicated by the LPI LS TIMER. + * + * When set, the link is considered to be okay (up) and when reset, the link is + * considered to be down. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:--------------- + * ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD | 0x0 | Link Down + * ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END | 0x1 | Link Up (okay) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS + * + * Link Down + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS + * + * Link Up (okay) + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_MSB 17 +/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS field value from a register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : PHY Link Status Enable - plsen + * + * This bit enables the link status received on the RGMII receive paths to be used + * for activating the LPI LS TIMER. + * + * When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII + * Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, + * the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD | 0x0 | MAC Ignores Link Status Bits + * ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END | 0x1 | MAC Uses Link Status Bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN + * + * MAC Ignores Link Status Bits + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN + * + * MAC Uses Link Status Bits + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN field value from a register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : LPI TX Automate - lpitxa + * + * This bit controls the behavior of the MAC when it is entering or coming out of + * the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE + * configuration in which the Tx clock gating is done during the LPI mode. + * + * If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only + * after all outstanding frames (in the core) and pending frames (in the + * application interface) have been transmitted. The MAC comes out of the LPI mode + * when the application sends any frame for transmission or the application issues + * a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit + * when it exits the LPI state. If TX FIFO Flush is set, in Bit 20 of Register 6 + * (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the + * LPI mode. + * + * When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it + * is entering or coming out of the LPI mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------- + * ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD | 0x0 | LPI TX Automate Disabled + * ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END | 0x1 | LPI TX Automate Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA + * + * LPI TX Automate Disabled + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA + * + * LPI TX Automate Enabled + */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA field value from a register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET(value) (((value) << 19) & 0x00080000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT. + */ +struct ALT_EMAC_GMAC_LPI_CTL_STAT_s +{ + const uint32_t tlpien : 1; /* Transmit LPI Entry */ + const uint32_t tlpiex : 1; /* Transmit LPI Exit */ + const uint32_t rlpien : 1; /* Receive LPI Entry */ + const uint32_t rlpiex : 1; /* Receive LPI Exit */ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t tlpist : 1; /* Transmit LPI State */ + const uint32_t rlpist : 1; /* Receive LPI State */ + uint32_t : 6; /* *UNDEFINED* */ + uint32_t lpien : 1; /* LPI Enable */ + uint32_t pls : 1; /* PHY Link Status */ + uint32_t plsen : 1; /* PHY Link Status Enable */ + uint32_t lpitxa : 1; /* LPI TX Automate */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT. */ +typedef volatile struct ALT_EMAC_GMAC_LPI_CTL_STAT_s ALT_EMAC_GMAC_LPI_CTL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LPI_CTL_STAT register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_OFST 0x30 +/* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register. */ +#define ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_CTL_STAT_OFST)) + +/* + * Register : Register 13 (LPI Timers Control Register) - LPI_Timers_Control + * + * The LPI Timers Control register controls the timeout values in the LPI states. + * It specifies the time for which the MAC transmits the LPI pattern and also the + * time for which the MAC waits before resuming the normal transmission. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------- + * [15:0] | RW | 0x0 | LPI TW Timer + * [25:16] | RW | 0x3e8 | LPI LS Timer + * [31:26] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : LPI TW Timer - twt + * + * This field specifies the minimum time (in microseconds) for which the MAC waits + * after it stops transmitting the LPI pattern to the PHY and before it resumes the + * normal transmission. The TLPIEX status bit is set after the expiry of this + * timer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT field value from a register. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : LPI LS Timer - lst + * + * This field specifies the minimum time (in milliseconds) for which the link + * status from the PHY should be up (OKAY) before the LPI pattern can be + * transmitted to the PHY. The MAC does not transmit the LPI pattern even when the + * LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. + * The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE + * standard. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_WIDTH 10 +/* The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET_MSK 0x03ff0000 +/* The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_CLR_MSK 0xfc00ffff +/* The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_RESET 0x3e8 +/* Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST field value from a register. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_GET(value) (((value) & 0x03ff0000) >> 16) +/* Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET(value) (((value) << 16) & 0x03ff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LPI_TMRS_CTL. + */ +struct ALT_EMAC_GMAC_LPI_TMRS_CTL_s +{ + uint32_t twt : 16; /* LPI TW Timer */ + uint32_t lst : 10; /* LPI LS Timer */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LPI_TMRS_CTL. */ +typedef volatile struct ALT_EMAC_GMAC_LPI_TMRS_CTL_s ALT_EMAC_GMAC_LPI_TMRS_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LPI_TMRS_CTL register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST 0x34 +/* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register. */ +#define ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST)) + +/* + * Register : Register 14 (Interrupt Register) - Interrupt_Status + * + * The Interrupt Status register identifies the events in the MAC that can generate + * interrupt. All interrupt events are generated only when the corresponding + * optional feature is enabled. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------- + * [0] | R | 0x0 | RGMII or SMII Interrupt Status + * [1] | R | 0x0 | PCS Link Status Changed + * [2] | R | 0x0 | PCS Auto-Negotiation Complete + * [3] | ??? | 0x0 | *UNDEFINED* + * [4] | R | 0x0 | MMC Interrupt Status + * [5] | R | 0x0 | MMC Receive Interrupt Status + * [6] | R | 0x0 | MMC Transmit Interrupt Status + * [7] | R | 0x0 | MMC Receive Checksum Offload Interrupt Status + * [8] | ??? | 0x0 | *UNDEFINED* + * [9] | R | 0x0 | Timestamp Interrupt Status + * [10] | R | 0x0 | LPI Interrupt Status + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RGMII or SMII Interrupt Status - rgsmiiis + * + * This bit is set because of any change in value of the Link Status of RGMII or + * SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Status Register)). This + * bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Status + * Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT | 0x0 | Link No Change + * ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT | 0x1 | Link Change + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_RGSMIIIS + * + * Link No Change + */ +#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_RGSMIIIS + * + * Link Change + */ +#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS field value from a register. */ +#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : PCS Link Status Changed - pcslchgis + * + * This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII + * PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared + * when you perform a read operation on the AN Status register. + * + * This bit is valid only when you select the SGMII PHY interface during operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS field value from a register. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : PCS Auto-Negotiation Complete - pcsancis + * + * This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or + * SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is + * cleared when you perform a read operation to the AN Status register. + * + * This bit is valid only when you select the SGMII PHY interface during operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_STAT_PCSANCIS field value from a register. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MMC Interrupt Status - mmcis + * + * This bit is set high when any of the Bits [7:5] is set high and cleared only + * when all of these bits are low. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------ + * ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT | 0x0 | MMC Interrupt Status Disabled + * ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT | 0x1 | MMC Interrupt Status Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCIS + * + * MMC Interrupt Status Disabled + */ +#define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCIS + * + * MMC Interrupt Status Enabled + */ +#define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCIS_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCIS field value from a register. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_INT_STAT_MMCIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MMC Receive Interrupt Status - mmcrxis + * + * This bit is set high when an interrupt is generated in the MMC Receive Interrupt + * Register. This bit is cleared when all the bits in this interrupt register are + * cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD | 0x0 | MMC Receive Interrupt Status Disabled + * ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END | 0x1 | MMC Receive Interrupt Status Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIS + * + * MMC Receive Interrupt Status Disabled + */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIS + * + * MMC Receive Interrupt Status Enabled + */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCRXIS field value from a register. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MMC Transmit Interrupt Status - mmctxis + * + * This bit is set high when an interrupt is generated in the MMC Transmit + * Interrupt Register. This bit is cleared when all the bits in this interrupt + * register are cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------------------------- + * ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT | 0x0 | MMC Transmit Interrupt Status Disabled + * ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT | 0x1 | MMC Transmit Interrupt Status Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCTXIS + * + * MMC Transmit Interrupt Status Disabled + */ +#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCTXIS + * + * MMC Transmit Interrupt Status Enabled + */ +#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_MSB 6 +/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCTXIS field value from a register. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MMC Receive Checksum Offload Interrupt Status - mmcrxipis + * + * This bit is set high when an interrupt is generated in the MMC Receive Checksum + * Offload Interrupt Register. This bit is cleared when all the bits in this + * interrupt register are cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------------------------- + * ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT | 0x0 | MMC Receive Checksum Offload Interrupt Status + * : | | Disabled + * ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT | 0x1 | MMC Receive Checksum Offload Interrupt Status + * : | | Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS + * + * MMC Receive Checksum Offload Interrupt Status Disabled + */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS + * + * MMC Receive Checksum Offload Interrupt Status Enabled + */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS field value from a register. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Timestamp Interrupt Status - tsis + * + * This bit is set when any of the following conditions is true: + * + * * The system time value equals or exceeds the value specified in the Target Time + * High and Low registers. + * + * * There is an overflow in the seconds register. + * + * * The Auxiliary snapshot trigger is asserted. + * + * This bit is cleared on reading Bit 0 of the Register 458 (Timestamp Status + * Register). + * + * When set, this bit indicates that the system time value is equal to or exceeds + * the value specified in the Target Time registers. In this mode, this bit is + * cleared after the completion of the read of this bit. In all other modes, this + * bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT | 0x0 | Timestamp Interrupt Status Disabled + * ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT | 0x1 | Timestamp Interrupt Status Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_TSIS + * + * Timestamp Interrupt Status Disabled + */ +#define ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_TSIS + * + * Timestamp Interrupt Status Enabled + */ +#define ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_TSIS_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_TSIS_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_TSIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_TSIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_TSIS_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_TSIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_TSIS_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_TSIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_STAT_TSIS field value from a register. */ +#define ALT_EMAC_GMAC_INT_STAT_TSIS_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_INT_STAT_TSIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_STAT_TSIS_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : LPI Interrupt Status - lpiis + * + * This bit is set for any LPI state entry or exit in the MAC Transmitter or + * Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and + * Status Register). In all other modes, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------ + * ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT | 0x0 | LPI Interrupt Status Disabled + * ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT | 0x1 | LPI Interrupt Status Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_LPIIS + * + * LPI Interrupt Status Disabled + */ +#define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_LPIIS + * + * LPI Interrupt Status Enabled + */ +#define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_LPIIS_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_LPIIS_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_LPIIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_LPIIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_LPIIS register field value. */ +#define ALT_EMAC_GMAC_INT_STAT_LPIIS_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */ +#define ALT_EMAC_GMAC_INT_STAT_LPIIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_STAT_LPIIS field value from a register. */ +#define ALT_EMAC_GMAC_INT_STAT_LPIIS_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_INT_STAT_LPIIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET(value) (((value) << 10) & 0x00000400) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_INT_STAT. + */ +struct ALT_EMAC_GMAC_INT_STAT_s +{ + const uint32_t rgsmiiis : 1; /* RGMII or SMII Interrupt Status */ + const uint32_t pcslchgis : 1; /* PCS Link Status Changed */ + const uint32_t pcsancis : 1; /* PCS Auto-Negotiation Complete */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t mmcis : 1; /* MMC Interrupt Status */ + const uint32_t mmcrxis : 1; /* MMC Receive Interrupt Status */ + const uint32_t mmctxis : 1; /* MMC Transmit Interrupt Status */ + const uint32_t mmcrxipis : 1; /* MMC Receive Checksum Offload Interrupt Status */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t tsis : 1; /* Timestamp Interrupt Status */ + const uint32_t lpiis : 1; /* LPI Interrupt Status */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_INT_STAT. */ +typedef volatile struct ALT_EMAC_GMAC_INT_STAT_s ALT_EMAC_GMAC_INT_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_INT_STAT register from the beginning of the component. */ +#define ALT_EMAC_GMAC_INT_STAT_OFST 0x38 +/* The address of the ALT_EMAC_GMAC_INT_STAT register. */ +#define ALT_EMAC_GMAC_INT_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_STAT_OFST)) + +/* + * Register : Register 15 (Interrupt Mask Register) - Interrupt_Mask + * + * The Interrupt Mask Register bits enable you to mask the interrupt signal because + * of the corresponding event in the Interrupt Status Register. The interrupt + * signal is sbd_intr_o. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------- + * [0] | RW | 0x0 | RGMII or SMII Interrupt Mask + * [1] | R | 0x0 | PCS Link Status Interrupt Mask + * [2] | R | 0x0 | PCS AN Completion Interrupt Mask + * [8:3] | ??? | 0x0 | *UNDEFINED* + * [9] | RW | 0x0 | Timestamp Interrupt Mask + * [10] | RW | 0x0 | LPI Interrupt Mask + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RGMII or SMII Interrupt Mask - rgsmiiim + * + * When set, this bit disables the assertion of the interrupt signal because of the + * setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt + * Status Register). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------- + * ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD | 0x0 | RGMII or SMII Interrupt Mask Disable + * ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END | 0x1 | RGMII or SMII Interrupt Mask Enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM + * + * RGMII or SMII Interrupt Mask Disable + */ +#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM + * + * RGMII or SMII Interrupt Mask Enable + */ +#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value. */ +#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value. */ +#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM field value from a register. */ +#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : PCS Link Status Interrupt Mask - pcslchgim + * + * When set, this bit disables the assertion of the interrupt signal because of the + * setting of the PCS Link-status changed bit in Register 14 (Interrupt Status + * Register). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM field value from a register. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : PCS AN Completion Interrupt Mask - pcsancim + * + * When set, this bit disables the assertion of the interrupt signal because of the + * setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status + * Register). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_MSK_PCSANCIM field value from a register. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timestamp Interrupt Mask - tsim + * + * When set, this bit disables the assertion of the interrupt signal because of the + * setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status + * Register). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------- + * ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD | 0x0 | Timestamp Interrupt Mask Disabled + * ALT_EMAC_GMAC_INT_MSK_TSIM_E_END | 0x1 | Timestamp Interrupt Mask Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM + * + * Timestamp Interrupt Mask Disabled + */ +#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM + * + * Timestamp Interrupt Mask Enabled + */ +#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_TSIM_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_TSIM_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_TSIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_MSK_TSIM register field value. */ +#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_TSIM register field value. */ +#define ALT_EMAC_GMAC_INT_MSK_TSIM_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_TSIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_MSK_TSIM field value from a register. */ +#define ALT_EMAC_GMAC_INT_MSK_TSIM_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_INT_MSK_TSIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : LPI Interrupt Mask - lpiim + * + * When set, this bit disables the assertion of the interrupt signal because of the + * setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status + * Register). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD | 0x0 | LPI Interrupt Mask Disabled + * ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END | 0x1 | LPI Interrupt Mask Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM + * + * LPI Interrupt Mask Disabled + */ +#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM + * + * LPI Interrupt Mask Enabled + */ +#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_LPIIM_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_LPIIM_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_LPIIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value. */ +#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value. */ +#define ALT_EMAC_GMAC_INT_MSK_LPIIM_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */ +#define ALT_EMAC_GMAC_INT_MSK_LPIIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_INT_MSK_LPIIM field value from a register. */ +#define ALT_EMAC_GMAC_INT_MSK_LPIIM_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_INT_MSK_LPIIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET(value) (((value) << 10) & 0x00000400) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_INT_MSK. + */ +struct ALT_EMAC_GMAC_INT_MSK_s +{ + uint32_t rgsmiiim : 1; /* RGMII or SMII Interrupt Mask */ + const uint32_t pcslchgim : 1; /* PCS Link Status Interrupt Mask */ + const uint32_t pcsancim : 1; /* PCS AN Completion Interrupt Mask */ + uint32_t : 6; /* *UNDEFINED* */ + uint32_t tsim : 1; /* Timestamp Interrupt Mask */ + uint32_t lpiim : 1; /* LPI Interrupt Mask */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_INT_MSK. */ +typedef volatile struct ALT_EMAC_GMAC_INT_MSK_s ALT_EMAC_GMAC_INT_MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_INT_MSK register from the beginning of the component. */ +#define ALT_EMAC_GMAC_INT_MSK_OFST 0x3c +/* The address of the ALT_EMAC_GMAC_INT_MSK register. */ +#define ALT_EMAC_GMAC_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_MSK_OFST)) + +/* + * Register : Register 16 (MAC Address0 High Register) - MAC_Address0_High + * + * The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC + * address of the station. The first DA byte that is received on the (G)MII + * interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low + * register. For example, if 0x112233445566 is received (0x11 in lane 0 of the + * first column) on the (G)MII as the destination address, then the MacAddress0 + * Register [47:0] is compared with 0x665544332211. + * + * Because the MAC address registers are double-synchronized to the (G)MII clock + * domains, then the synchronization is triggered only when Bits[31:24] (in little- + * endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register + * are written. For proper synchronization updates, the consecutive writes to this + * Address Low Register should be performed after at least four clock cycles in the + * destination clock domain. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | RW | 0xffff | MAC Address0 [47:32] + * [30:16] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x1 | Address Enable + * + */ +/* + * Field : MAC Address0 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. + * The MAC uses this field for filtering the received frames and inserting the MAC + * address in the Transmit Flow Control (PAUSE) Frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Address Enable - ae + * + * This bit is always set to 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_RESET 0x1 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR0_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR0_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address0 [47:32] */ + uint32_t : 15; /* *UNDEFINED* */ + const uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR0_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR0_HIGH_s ALT_EMAC_GMAC_MAC_ADDR0_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_OFST 0x40 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR0_HIGH_OFST)) + +/* + * Register : Register 17 (MAC Address0 Low Register) - MAC_Address0_Low + * + * The MAC Address0 Low register holds the lower 32 bits of the first 6-byte MAC + * address of the station. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------- + * [31:0] | RW | 0xffffffff | MAC Address0 [31:0] + * + */ +/* + * Field : MAC Address0 [31:0] - addrlo + * + * This field contains the lower 32 bits of the first 6-byte MAC address. This is + * used by the MAC for filtering the received frames and inserting the MAC address + * in the Transmit Flow Control (PAUSE) Frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR0_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR0_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address0 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR0_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR0_LOW_s ALT_EMAC_GMAC_MAC_ADDR0_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_OFST 0x44 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR0_LOW_OFST)) + +/* + * Register : Register 18 (MAC Address1 High Register) - MAC_Address1_High + * + * The MAC Address1 High register holds the upper 16 bits of the 2nd 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address1 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | RW | 0xffff | MAC Address1 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address1 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 2nd 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address1 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address1 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address1 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address1 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address1 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address1 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address1[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address1[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 2nd MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR1_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR1_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address1 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR1_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR1_HIGH_s ALT_EMAC_GMAC_MAC_ADDR1_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_OFST 0x48 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR1_HIGH_OFST)) + +/* + * Register : Register 19 (MAC Address1 Low Register) - MAC_Address1_Low + * + * The MAC Address1 Low register holds the lower 32 bits of the 2nd 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------- + * [31:0] | RW | 0xffffffff | MAC Address1 [31:0] + * + */ +/* + * Field : MAC Address1 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 2nd 6-byte MAC address. The content + * of this field is undefined until loaded by software after the initialization + * process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR1_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR1_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address1 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR1_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR1_LOW_s ALT_EMAC_GMAC_MAC_ADDR1_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_OFST 0x4c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR1_LOW_OFST)) + +/* + * Register : Register 20 (MAC Address2 High Register) - MAC_Address2_High + * + * The MAC Address2 High register holds the upper 16 bits of the 3rd 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address2 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | RW | 0xffff | MAC Address2 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address2 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 3rd 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address2 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address2 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address2 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address2 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address2 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address2 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address2[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address2[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 3rd MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR2_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR2_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address2 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR2_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR2_HIGH_s ALT_EMAC_GMAC_MAC_ADDR2_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_OFST 0x50 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR2_HIGH_OFST)) + +/* + * Register : Register 21 (MAC Address2 Low Register) - MAC_Address2_Low + * + * The MAC Address2 Low register holds the lower 32 bits of the 3rd 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------- + * [31:0] | RW | 0xffffffff | MAC Address2 [31:0] + * + */ +/* + * Field : MAC Address2 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 3rd 6-byte MAC address. The content + * of this field is undefined until loaded by software after the initialization + * process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR2_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR2_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address2 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR2_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR2_LOW_s ALT_EMAC_GMAC_MAC_ADDR2_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_OFST 0x54 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR2_LOW_OFST)) + +/* + * Register : Register 22 (MAC Address3 High Register) - MAC_Address3_High + * + * The MAC Address3 High register holds the upper 16 bits of the 4th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address3 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | RW | 0xffff | MAC Address3 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address3 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 4th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address3 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address3 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address3 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address3 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address3 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address3 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address3[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address3[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 4th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR3_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR3_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address3 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR3_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR3_HIGH_s ALT_EMAC_GMAC_MAC_ADDR3_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_OFST 0x58 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR3_HIGH_OFST)) + +/* + * Register : Register 23 (MAC Address3 Low Register) - MAC_Address3_Low + * + * The MAC Address3 Low register holds the lower 32 bits of the 4th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------- + * [31:0] | RW | 0xffffffff | MAC Address3 [31:0] + * + */ +/* + * Field : MAC Address3 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 4th 6-byte MAC address. The content + * of this field is undefined until loaded by software after the initialization + * process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR3_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR3_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address3 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR3_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR3_LOW_s ALT_EMAC_GMAC_MAC_ADDR3_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_OFST 0x5c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR3_LOW_OFST)) + +/* + * Register : Register 24 (MAC Address4 High Register) - MAC_Address4_High + * + * The MAC Address4 High register holds the upper 16 bits of the 5th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address4 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | RW | 0xffff | MAC Address4 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address4 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 5th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address4 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address4 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address4 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address4 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address4 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address4 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address4[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address4[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 5th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR4_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR4_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address4 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR4_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR4_HIGH_s ALT_EMAC_GMAC_MAC_ADDR4_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_OFST 0x60 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR4_HIGH_OFST)) + +/* + * Register : Register 25 (MAC Address4 Low Register) - MAC_Address4_Low + * + * The MAC Address4 Low register holds the lower 32 bits of the 5th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------- + * [31:0] | RW | 0xffffffff | MAC Address4 [31:0] + * + */ +/* + * Field : MAC Address4 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 5th 6-byte MAC address. The content + * of this field is undefined until loaded by software after the initialization + * process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR4_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR4_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address4 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR4_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR4_LOW_s ALT_EMAC_GMAC_MAC_ADDR4_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_OFST 0x64 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR4_LOW_OFST)) + +/* + * Register : Register 26 (MAC Address5 High Register) - MAC_Address5_High + * + * The MAC Address5 High register holds the upper 16 bits of the 6th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address5 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | RW | 0xffff | MAC Address5 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address5 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 6th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address5 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address5 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address5 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address5 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address5 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address5 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address5[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address5[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 6th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR5_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR5_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address5 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR5_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR5_HIGH_s ALT_EMAC_GMAC_MAC_ADDR5_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_OFST 0x68 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR5_HIGH_OFST)) + +/* + * Register : Register 27 (MAC Address5 Low Register) - MAC_Address5_Low + * + * The MAC Address5 Low register holds the lower 32 bits of the 6th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------- + * [31:0] | RW | 0xffffffff | MAC Address5 [31:0] + * + */ +/* + * Field : MAC Address5 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 6th 6-byte MAC address. The content + * of this field is undefined until loaded by software after the initialization + * process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR5_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR5_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address5 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR5_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR5_LOW_s ALT_EMAC_GMAC_MAC_ADDR5_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_OFST 0x6c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR5_LOW_OFST)) + +/* + * Register : Register 28 (MAC Address6 High Register) - MAC_Address6_High + * + * The MAC Address6 High register holds the upper 16 bits of the 7th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address6 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | RW | 0xffff | MAC Address6 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address6 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 7th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address6 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address6 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address6 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address6 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address6 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address6 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address6[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address6[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 7th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR6_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR6_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address6 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR6_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR6_HIGH_s ALT_EMAC_GMAC_MAC_ADDR6_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_OFST 0x70 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR6_HIGH_OFST)) + +/* + * Register : Register 29 (MAC Address6 Low Register) - MAC_Address6_Low + * + * The MAC Address6 Low register holds the lower 32 bits of the 7th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------- + * [31:0] | RW | 0xffffffff | MAC Address6 [31:0] + * + */ +/* + * Field : MAC Address6 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 7th 6-byte MAC address. The content + * of this field is undefined until loaded by software after the initialization + * process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR6_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR6_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address6 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR6_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR6_LOW_s ALT_EMAC_GMAC_MAC_ADDR6_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_OFST 0x74 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR6_LOW_OFST)) + +/* + * Register : Register 30 (MAC Address7 High Register) - MAC_Address7_High + * + * The MAC Address7 High register holds the upper 16 bits of the 8th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address7 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | RW | 0xffff | MAC Address7 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address7 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 8th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address7 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address7 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address7 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address7 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address7 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address7 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address7[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address7[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 8th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR7_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR7_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address7 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR7_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR7_HIGH_s ALT_EMAC_GMAC_MAC_ADDR7_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_OFST 0x78 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR7_HIGH_OFST)) + +/* + * Register : Register 31 (MAC Address7 Low Register) - MAC_Address7_Low + * + * The MAC Address7 Low register holds the lower 32 bits of the 8th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------- + * [31:0] | RW | 0xffffffff | MAC Address7 [31:0] + * + */ +/* + * Field : MAC Address7 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 8th 6-byte MAC address. The content + * of this field is undefined until loaded by software after the initialization + * process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR7_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR7_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address7 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR7_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR7_LOW_s ALT_EMAC_GMAC_MAC_ADDR7_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_OFST 0x7c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR7_LOW_OFST)) + +/* + * Register : Register 32 (MAC Address8 High Register) - MAC_Address8_High + * + * The MAC Address8 High register holds the upper 16 bits of the 9th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address8 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | RW | 0xffff | MAC Address8 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address8 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 9th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address8 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address8 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address8 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address8 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address8 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address8 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address8[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address8[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 9th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR8_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR8_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address8 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR8_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR8_HIGH_s ALT_EMAC_GMAC_MAC_ADDR8_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_OFST 0x80 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR8_HIGH_OFST)) + +/* + * Register : Register 33 (MAC Address8 Low Register) - MAC_Address8_Low + * + * The MAC Address8 Low register holds the lower 32 bits of the 9th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------- + * [31:0] | RW | 0xffffffff | MAC Address8 [31:0] + * + */ +/* + * Field : MAC Address8 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 9th 6-byte MAC address. The content + * of this field is undefined until loaded by software after the initialization + * process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR8_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR8_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address8 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR8_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR8_LOW_s ALT_EMAC_GMAC_MAC_ADDR8_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_OFST 0x84 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR8_LOW_OFST)) + +/* + * Register : Register 34 (MAC Address9 High Register) - MAC_Address9_High + * + * The MAC Address9 High register holds the upper 16 bits of the 10th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address9 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | RW | 0xffff | MAC Address9 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address9 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 10th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address9 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address9 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address9 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address9 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address9 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address9 high and low registers. Each + * bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address9[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address9[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 10th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR9_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR9_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address9 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR9_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR9_HIGH_s ALT_EMAC_GMAC_MAC_ADDR9_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_OFST 0x88 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR9_HIGH_OFST)) + +/* + * Register : Register 35 (MAC Address9 Low Register) - MAC_Address9_Low + * + * The MAC Address9 Low register holds the lower 32 bits of the 10th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------- + * [31:0] | RW | 0xffffffff | MAC Address9 [31:0] + * + */ +/* + * Field : MAC Address9 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 10th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR9_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR9_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address9 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR9_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR9_LOW_s ALT_EMAC_GMAC_MAC_ADDR9_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_OFST 0x8c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR9_LOW_OFST)) + +/* + * Register : Register 36 (MAC Address10 High Register) - MAC_Address10_High + * + * The MAC Address10 High register holds the upper 16 bits of the 11th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address10 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address10 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address10 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 11th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address10 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address10 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address10 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address10 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address10 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address10 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address10[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address10[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 11th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR10_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR10_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address10 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR10_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR10_HIGH_s ALT_EMAC_GMAC_MAC_ADDR10_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_OFST 0x90 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR10_HIGH_OFST)) + +/* + * Register : Register 37 (MAC Address10 Low Register) - MAC_Address10_Low + * + * The MAC Address10 Low register holds the lower 32 bits of the 11th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address10 [31:0] + * + */ +/* + * Field : MAC Address10 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 11th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR10_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR10_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address10 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR10_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR10_LOW_s ALT_EMAC_GMAC_MAC_ADDR10_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_OFST 0x94 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR10_LOW_OFST)) + +/* + * Register : Register 38 (MAC Address11 High Register) - MAC_Address11_High + * + * The MAC Address11 High register holds the upper 16 bits of the 12th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address11 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address11 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address11 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 12th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address11 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address11 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address11 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address11 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address11 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address11 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address11[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address11[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 12th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR11_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR11_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address11 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR11_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR11_HIGH_s ALT_EMAC_GMAC_MAC_ADDR11_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_OFST 0x98 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR11_HIGH_OFST)) + +/* + * Register : Register 39 (MAC Address11 Low Register) - MAC_Address11_Low + * + * The MAC Address11 Low register holds the lower 32 bits of the 12th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address11 [31:0] + * + */ +/* + * Field : MAC Address11 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 12th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR11_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR11_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address11 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR11_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR11_LOW_s ALT_EMAC_GMAC_MAC_ADDR11_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_OFST 0x9c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR11_LOW_OFST)) + +/* + * Register : Register 40 (MAC Address12 High Register) - MAC_Address12_High + * + * The MAC Address12 High register holds the upper 16 bits of the 13th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address12 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address12 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address12 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 13th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address12 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address12 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address12 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address12 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address12 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address12 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address12[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address12[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 13th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR12_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR12_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address12 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR12_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR12_HIGH_s ALT_EMAC_GMAC_MAC_ADDR12_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_OFST 0xa0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR12_HIGH_OFST)) + +/* + * Register : Register 41 (MAC Address12 Low Register) - MAC_Address12_Low + * + * The MAC Address12 Low register holds the lower 32 bits of the 13th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address12 [31:0] + * + */ +/* + * Field : MAC Address12 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 13th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR12_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR12_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address12 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR12_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR12_LOW_s ALT_EMAC_GMAC_MAC_ADDR12_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_OFST 0xa4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR12_LOW_OFST)) + +/* + * Register : Register 42 (MAC Address13 High Register) - MAC_Address13_High + * + * The MAC Address13 High register holds the upper 16 bits of the 14th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address13 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address13 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address13 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 14th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address13 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address13 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address13 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address13 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address13 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address13 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address13[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address13[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 14th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR13_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR13_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address13 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR13_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR13_HIGH_s ALT_EMAC_GMAC_MAC_ADDR13_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_OFST 0xa8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR13_HIGH_OFST)) + +/* + * Register : Register 43 (MAC Address13 Low Register) - MAC_Address13_Low + * + * The MAC Address13 Low register holds the lower 32 bits of the 14th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address13 [31:0] + * + */ +/* + * Field : MAC Address13 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 14th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR13_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR13_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address13 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR13_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR13_LOW_s ALT_EMAC_GMAC_MAC_ADDR13_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_OFST 0xac +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR13_LOW_OFST)) + +/* + * Register : Register 44 (MAC Address14 High Register) - MAC_Address14_High + * + * The MAC Address14 High register holds the upper 16 bits of the 15th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address14 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address14 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address14 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 15th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address14 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address14 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address14 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address14 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address14 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address14 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address14[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address14[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 15th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR14_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR14_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address14 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR14_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR14_HIGH_s ALT_EMAC_GMAC_MAC_ADDR14_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_OFST 0xb0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR14_HIGH_OFST)) + +/* + * Register : Register 45 (MAC Address14 Low Register) - MAC_Address14_Low + * + * The MAC Address14 Low register holds the lower 32 bits of the 15th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address14 [31:0] + * + */ +/* + * Field : MAC Address14 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 15th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR14_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR14_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address14 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR14_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR14_LOW_s ALT_EMAC_GMAC_MAC_ADDR14_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_OFST 0xb4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR14_LOW_OFST)) + +/* + * Register : Register 46 (MAC Address15 High Register) - MAC_Address15_High + * + * The MAC Address15 High register holds the upper 16 bits of the 16th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address15 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address15 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address15 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 16th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address15 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address15 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address15 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address15 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address15 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address15 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address15[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address15[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 16th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR15_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR15_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address15 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR15_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR15_HIGH_s ALT_EMAC_GMAC_MAC_ADDR15_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_OFST 0xb8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR15_HIGH_OFST)) + +/* + * Register : Register 47 (MAC Address15 Low Register) - MAC_Address15_Low + * + * The MAC Address15 Low register holds the lower 32 bits of the 16th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address15 [31:0] + * + */ +/* + * Field : MAC Address15 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 16th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR15_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR15_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address15 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR15_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR15_LOW_s ALT_EMAC_GMAC_MAC_ADDR15_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_OFST 0xbc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR15_LOW_OFST)) + +/* + * Register : Register 54 (SGMII/RGMII/SMII Status Register) - SGMII_RGMII_SMII_Control_Status + * + * The SGMII/RGMII/SMII Status register indicates the status signals received by + * the RGMII interface (selected at reset) from the PHY. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | R | 0x0 | Link Mode + * [2:1] | R | 0x0 | Link Speed + * [3] | R | 0x0 | Link Status + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Link Mode - lnkmod + * + * This bit indicates the current mode of operation of the link + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP | 0x0 | Half Duplex + * ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP | 0x1 | Full Duplex + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD + * + * Half Duplex + */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD + * + * Full Duplex + */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD field value from a register. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Link Speed - lnkspeed + * + * This bit indicates the current speed of the link. Bit 2 is reserved when the MAC + * is configured for the SMII PHY interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:------------------ + * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ | 0x0 | Link Speed 2.5MHz + * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ | 0x1 | Link Speed 25MHz + * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ | 0x2 | Link Speed 125MHz + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED + * + * Link Speed 2.5MHz + */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED + * + * Link Speed 25MHz + */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ 0x1 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED + * + * Link Speed 125MHz + */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET_MSK 0x00000006 +/* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED field value from a register. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : Link Status - lnksts + * + * This bit indicates whether the link is up (1'b1) or down (1'b0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------ + * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN | 0x0 | Linkdown + * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP | 0x1 | Linkup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS + * + * Linkdown + */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS + * + * Linkup + */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS field value from a register. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MII_CTL_STAT. + */ +struct ALT_EMAC_GMAC_MII_CTL_STAT_s +{ + const uint32_t lnkmod : 1; /* Link Mode */ + const uint32_t lnkspeed : 2; /* Link Speed */ + const uint32_t lnksts : 1; /* Link Status */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MII_CTL_STAT. */ +typedef volatile struct ALT_EMAC_GMAC_MII_CTL_STAT_s ALT_EMAC_GMAC_MII_CTL_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MII_CTL_STAT register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_OFST 0xd8 +/* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register. */ +#define ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MII_CTL_STAT_OFST)) + +/* + * Register : Register 64 (MMC Control Register) - MMC_Control + * + * The MMC Control register establishes the operating mode of the management + * counters. + * + * Note: + * + * The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset). + * Therefore, when the Software tries to set both bits in the same write cycle, all + * counters are cleared and the bit 4 is not set. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------- + * [0] | RW | 0x0 | Counters Reset + * [1] | RW | 0x0 | Counters Stop Rollover + * [2] | RW | 0x0 | Reset on Read + * [3] | RW | 0x0 | MMC Counter Freeze + * [4] | RW | 0x0 | Counters Preset + * [5] | RW | 0x0 | Full-Half Preset + * [7:6] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | Update MMC Counters for Dropped Broadcast Frames + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counters Reset - cntrst + * + * When this bit is set, all counters are reset. This bit is cleared automatically + * after one clock cycle. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_DISD | 0x0 | Auto cleared after 1 clock cycle + * ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_END | 0x1 | All Counters Reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTRST + * + * Auto cleared after 1 clock cycle + */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTRST + * + * All Counters Reset + */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTRST field value from a register. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Counters Stop Rollover - cntstopro + * + * When this bit is set, after reaching maximum value, the counter does not roll + * over to zero. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_DISD | 0x0 | Counter Roll Over + * ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_END | 0x1 | Counter does not Roll Over + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO + * + * Counter Roll Over + */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO + * + * Counter does not Roll Over + */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO field value from a register. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Reset on Read - rstonrd + * + * When this bit is set, the MMC counters are reset to zero after Read (self- + * clearing after reset). The counters are cleared when the least significant byte + * lane (bits[7:0]) is read. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_DISD | 0x0 | No reset after read + * ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_END | 0x1 | Reset after read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_RSTONRD + * + * No reset after read + */ +#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_RSTONRD + * + * Reset after read + */ +#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_CTL_RSTONRD field value from a register. */ +#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MMC Counter Freeze - cntfreez + * + * When this bit is set, it freezes all MMC counters to their current value. Until + * this bit is reset to 0, no MMC counter is updated because of any transmitted or + * received frame. If any MMC counter is read with the Reset on Read bit set, then + * that counter is also cleared in this mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------- + * ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_DISD | 0x0 | Update MMC Counters + * ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_END | 0x1 | Freeze MMC counters to current value + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ + * + * Update MMC Counters + */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ + * + * Freeze MMC counters to current value + */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ field value from a register. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Counters Preset - cntprst + * + * When this bit is set, all counters are initialized or preset to almost full or + * almost half according to bit 5. This bit is cleared automatically after 1 clock + * cycle. This bit, along with bit 5, is useful for debugging and testing the + * assertion of interrupts because of MMC counter becoming half-full or full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------------------- + * ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_DISD | 0x0 | Counters not preset + * ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_END | 0x1 | Counters preset to full or almost full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRST + * + * Counters not preset + */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRST + * + * Counters preset to full or almost full + */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTPRST field value from a register. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Full-Half Preset - cntprstlvl + * + * When low and bit 4 is set, all MMC counters get preset to almost-half value. All + * octet counters get preset to 0x7FFF_F800 (half - 2KBytes) and all frame-counters + * gets preset to 0x7FFF_FFF0 (half - 16). + * + * When this bit is high and bit 4 is set, all MMC counters get preset to almost- + * full value. All octet counters get preset to 0xFFFF_F800 (full - 2KBytes) and + * all frame-counters gets preset to 0xFFFF_FFF0 (full - 16). + * + * For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the + * respective octet and frame counters. Similarly, the almost-full preset values + * for the 16-bit counters are 0xF800 and 0xFFF0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------- + * ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTHALF | 0x0 | Preset All Counters to almost-half + * ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTFULL | 0x1 | Present All Counters almost-full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL + * + * Preset All Counters to almost-half + */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTHALF 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL + * + * Present All Counters almost-full + */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL field value from a register. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Update MMC Counters for Dropped Broadcast Frames - ucdbc + * + * When set, this bit enables MAC to update all the related MMC Counters for + * Broadcast frames dropped due to setting of DBF bit (Disable Broadcast Frames) of + * MAC Filter Register at offset 0x0004. + * + * When reset, MMC Counters are not updated for dropped Broadcast frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value. */ +#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */ +#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_CTL_UCDBC field value from a register. */ +#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MMC_CTL. + */ +struct ALT_EMAC_GMAC_MMC_CTL_s +{ + uint32_t cntrst : 1; /* Counters Reset */ + uint32_t cntstopro : 1; /* Counters Stop Rollover */ + uint32_t rstonrd : 1; /* Reset on Read */ + uint32_t cntfreez : 1; /* MMC Counter Freeze */ + uint32_t cntprst : 1; /* Counters Preset */ + uint32_t cntprstlvl : 1; /* Full-Half Preset */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t ucdbc : 1; /* Update MMC Counters for Dropped Broadcast Frames */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MMC_CTL. */ +typedef volatile struct ALT_EMAC_GMAC_MMC_CTL_s ALT_EMAC_GMAC_MMC_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MMC_CTL register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MMC_CTL_OFST 0x100 +/* The address of the ALT_EMAC_GMAC_MMC_CTL register. */ +#define ALT_EMAC_GMAC_MMC_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_CTL_OFST)) + +/* + * Register : Register 65 (MMC Receive Interrupt Register) - MMC_Receive_Interrupt + * + * The MMC Receive Interrupt register maintains the interrupts that are generated + * when the following happens: + * + * * Receive statistic counters reach half of their maximum values (0x8000_0000 for + * 32-bit counter and 0x8000 for 16-bit counter). + * + * * Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32-bit + * counter and 0xFFFF for 16-bit counter). + * + * When the Counter Stop Rollover is set, then interrupts are set but the counter + * remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide + * register. An interrupt bit is cleared when the respective MMC counter that + * caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the + * respective counter must be read in order to clear the interrupt bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------------------------------------- + * [0] | R | 0x0 | MMC Receive Good Bad Frame Counter Interrupt Status + * [1] | R | 0x0 | MMC Receive Good Bad Octet Counter Interrupt Status + * [2] | R | 0x0 | MMC Receive Good Octet Counter Interrupt Status. + * [3] | R | 0x0 | MMC Receive Broadcast Good Frame Counter Interrupt Status. + * [4] | R | 0x0 | MMC Receive Multicast Good Frame Counter Interrupt Status + * [5] | R | 0x0 | MMC Receive CRC Error Frame Counter Interrupt Status + * [6] | R | 0x0 | MMC Receive Alignment Error Frame Counter Interrupt Status + * [7] | R | 0x0 | MMC Receive Runt Frame Counter Interrupt Status + * [8] | R | 0x0 | MMC Receive Jabber Error Frame Counter Interrupt Status + * [9] | R | 0x0 | MMC Receive Undersize Good Frame Counter Interrupt Status + * [10] | R | 0x0 | MMC Receive Oversize Good Frame Counter Interrupt Status + * [11] | R | 0x0 | MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status + * [12] | R | 0x0 | MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status + * [13] | R | 0x0 | MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status + * [14] | R | 0x0 | MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status + * [15] | R | 0x0 | MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + * [16] | R | 0x0 | MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status + * [17] | R | 0x0 | MMC Receive Unicast Good Frame Counter Interrupt Status + * [18] | R | 0x0 | MMC Receive Length Error Frame Counter Interrupt Status + * [19] | R | 0x0 | MMC Receive Out Of Range Error Frame Counter Interrupt Status + * [20] | R | 0x0 | MMC Receive Pause Frame Counter Interrupt Status + * [21] | R | 0x0 | MMC Receive FIFO Overflow Frame Counter Interrupt Status + * [22] | R | 0x0 | MMC Receive VLAN Good Bad Frame Counter Interrupt Status + * [23] | R | 0x0 | MMC Receive Watchdog Error Frame Counter Interrupt Status + * [24] | R | 0x0 | MMC Receive Error Frame Counter Interrupt Status + * [25] | R | 0x0 | MMC Receive Control Frame Counter Interrupt Status + * [31:26] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MMC Receive Good Bad Frame Counter Interrupt Status - rxgbfrmis + * + * This bit is set when the rxframecount_bg counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF | 0x0 | Preset All Counters to almost-half + * ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL | 0x1 | Present All Counters almost-full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS + * + * Preset All Counters to almost-half + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS + * + * Present All Counters almost-full + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MMC Receive Good Bad Octet Counter Interrupt Status - rxgboctis + * + * This bit is set when the rxoctetcount_bg counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT | 0x0 | Rxoctetcount_bg < half max + * ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT | 0x1 | Rxoctetcount_bg >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS + * + * Rxoctetcount_bg < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS + * + * Rxoctetcount_bg >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MMC Receive Good Octet Counter Interrupt Status. - rxgoctis + * + * This bit is set when the rxoctetcount_g counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT | 0x0 | Rxoctetcount_g < half max + * ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT | 0x1 | Rxoctetcount_g >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS + * + * Rxoctetcount_g < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS + * + * Rxoctetcount_g >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MMC Receive Broadcast Good Frame Counter Interrupt Status. - rxbcgfis + * + * This bit is set when the rxbroadcastframes_g counter reaches half of the maximum + * value or the maximum value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MMC Receive Multicast Good Frame Counter Interrupt Status - rxmcgfis + * + * This bit is set when the rxmulticastframes_g counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT | 0x0 | rxbroadcastframes_g < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT | 0x1 | rxbroadcastframes_g >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS + * + * rxbroadcastframes_g < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS + * + * rxbroadcastframes_g >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MMC Receive CRC Error Frame Counter Interrupt Status - rxcrcerfis + * + * This bit is set when the rxcrcerror counter reaches half of the maximum value or + * the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT | 0x0 | rxcrcerror < half max + * ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT | 0x1 | rxcrcerror >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS + * + * rxcrcerror < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS + * + * rxcrcerror >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MMC Receive Alignment Error Frame Counter Interrupt Status - rxalgnerfis + * + * This bit is set when the rxalignmenterror counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT | 0x0 | rxalignmenterror < half max + * ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT | 0x1 | rxalignmenterror >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS + * + * rxalignmenterror < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS + * + * rxalignmenterror >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_MSB 6 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MMC Receive Runt Frame Counter Interrupt Status - rxruntfis + * + * This bit is set when the rxrunterror counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT | 0x0 | rxrunterror < half max + * ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT | 0x1 | rxrunterror >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS + * + * rxrunterror < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS + * + * rxrunterror >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MMC Receive Jabber Error Frame Counter Interrupt Status - rxjaberfis + * + * This bit is set when the rxjabbererror counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT | 0x0 | rxjabbererror < half max + * ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT | 0x1 | rxjabbererror >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS + * + * rxjabbererror < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS + * + * rxjabbererror >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MMC Receive Undersize Good Frame Counter Interrupt Status - rxusizegfis + * + * This bit is set when the rxundersize_g counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT | 0x0 | rxundersize_g < half max + * ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT | 0x1 | rxundersize_g >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS + * + * rxundersize_g < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS + * + * rxundersize_g >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MMC Receive Oversize Good Frame Counter Interrupt Status - rxosizegfis + * + * This bit is set when the rxoversize_g counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT | 0x0 | rxoversize_g < half max + * ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT | 0x1 | rxoversize_g >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS + * + * rxoversize_g < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS + * + * rxoversize_g >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status - rx64octgbfis + * + * This bit is set when the rx64octets_gb counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT | 0x0 | rx64octets_gb < half max + * ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT | 0x1 | rx64octets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS + * + * rx64octets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS + * + * rx64octets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_MSB 11 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status - rx65t127octgbfis + * + * This is set when the rx65to127octets_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:-------------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT | 0x0 | rx65to127octets_gb < half max + * ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT | 0x1 | rx65to127octets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS + * + * rx65to127octets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS + * + * rx65to127octets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_MSB 12 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET_MSK 0x00001000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_CLR_MSK 0xffffefff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status - rx128t255octgbfis + * + * This bit is set when the rx128to255octets_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT | 0x0 | rx128to255octets_gb < half max + * ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT | 0x1 | rx128to255octets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS + * + * rx128to255octets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS + * + * rx128to255octets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_MSB 13 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status - rx256t511octgbfis + * + * This bit is set when the rx256to511octets_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT | 0x0 | rx256to511octets_gb < half max + * ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT | 0x1 | rx256to511octets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS + * + * rx256to511octets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS + * + * rx256to511octets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_MSB 14 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET_MSK 0x00004000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_CLR_MSK 0xffffbfff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - rx512t1023octgbfis + * + * This bit is set when the rx512to1023octets_gb counter reaches half of the + * maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:---------------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT | 0x0 | rx512to1023octets_gb < half max + * ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT | 0x1 | rx512to1023octets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS + * + * rx512to1023octets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS + * + * rx512to1023octets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET_MSK 0x00008000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_CLR_MSK 0xffff7fff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - rx1024tmaxoctgbfis + * + * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the + * maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:---------------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT | 0x0 | rx1024tomaxoctets_gb < half max + * ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT | 0x1 | rx1024tomaxoctets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS + * + * rx1024tomaxoctets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS + * + * rx1024tomaxoctets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MMC Receive Unicast Good Frame Counter Interrupt Status - rxucgfis + * + * This bit is set when the rxunicastframes_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT | 0x0 | rx1024tomaxoctets_gb < half max + * ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT | 0x1 | rx1024tomaxoctets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS + * + * rx1024tomaxoctets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS + * + * rx1024tomaxoctets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_MSB 17 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : MMC Receive Length Error Frame Counter Interrupt Status - rxlenerfis + * + * This bit is set when the rxlengtherror counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT | 0x0 | rxlengtherror < half max + * ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT | 0x1 | rxlengtherror >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS + * + * rxlengtherror < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS + * + * rxlengtherror >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : MMC Receive Out Of Range Error Frame Counter Interrupt Status - rxorangefis + * + * This bit is set when the rxoutofrangetype counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------ + * ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT | 0x0 | rxoutofrangetype < half max + * ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT | 0x1 | rxoutofrangetype >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS + * + * rxoutofrangetype < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS + * + * rxoutofrangetype >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MMC Receive Pause Frame Counter Interrupt Status - rxpausfis + * + * This bit is set when the rxpauseframe counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT | 0x0 | rxpauseframe < half max + * ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT | 0x1 | rxpauseframe >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS + * + * rxpauseframe < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS + * + * rxpauseframe >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : MMC Receive FIFO Overflow Frame Counter Interrupt Status - rxfovfis + * + * This bit is set when the rxfifooverflow counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT | 0x0 | rxfifooverflow < half max + * ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT | 0x1 | rxfifooverflow >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS + * + * rxfifooverflow < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS + * + * rxfifooverflow >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : MMC Receive VLAN Good Bad Frame Counter Interrupt Status - rxvlangbfis + * + * This bit is set when the rxvlanframes_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT | 0x0 | rxvlanframes_gb < half max + * ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT | 0x1 | rxvlanframes_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS + * + * rxvlanframes_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS + * + * rxvlanframes_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_MSB 22 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET_MSK 0x00400000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_CLR_MSK 0xffbfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MMC Receive Watchdog Error Frame Counter Interrupt Status - rxwdogfis + * + * This bit is set when the rxwatchdogerror counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT | 0x0 | rxwatchdogerror < half max + * ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT | 0x1 | rxwatchdogerror >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS + * + * rxwatchdogerror < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS + * + * rxwatchdogerror >= half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_MSB 23 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET_MSK 0x00800000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_CLR_MSK 0xff7fffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : MMC Receive Error Frame Counter Interrupt Status - rxrcverrfis + * + * This bit is set when the rxrcverror counter reaches half of the maximum value or + * the maximum value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MMC Receive Control Frame Counter Interrupt Status - rxctrlfis + * + * This bit is set when the rxctrlframes_g counter reaches half of the maximum + * value or the maximum value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MMC_RX_INT. + */ +struct ALT_EMAC_GMAC_MMC_RX_INT_s +{ + const uint32_t rxgbfrmis : 1; /* MMC Receive Good Bad Frame Counter Interrupt Status */ + const uint32_t rxgboctis : 1; /* MMC Receive Good Bad Octet Counter Interrupt Status */ + const uint32_t rxgoctis : 1; /* MMC Receive Good Octet Counter Interrupt Status. */ + const uint32_t rxbcgfis : 1; /* MMC Receive Broadcast Good Frame Counter Interrupt Status. */ + const uint32_t rxmcgfis : 1; /* MMC Receive Multicast Good Frame Counter Interrupt Status */ + const uint32_t rxcrcerfis : 1; /* MMC Receive CRC Error Frame Counter Interrupt Status */ + const uint32_t rxalgnerfis : 1; /* MMC Receive Alignment Error Frame Counter Interrupt Status */ + const uint32_t rxruntfis : 1; /* MMC Receive Runt Frame Counter Interrupt Status */ + const uint32_t rxjaberfis : 1; /* MMC Receive Jabber Error Frame Counter Interrupt Status */ + const uint32_t rxusizegfis : 1; /* MMC Receive Undersize Good Frame Counter Interrupt Status */ + const uint32_t rxosizegfis : 1; /* MMC Receive Oversize Good Frame Counter Interrupt Status */ + const uint32_t rx64octgbfis : 1; /* MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t rx65t127octgbfis : 1; /* MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t rx128t255octgbfis : 1; /* MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t rx256t511octgbfis : 1; /* MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t rx512t1023octgbfis : 1; /* MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t rx1024tmaxoctgbfis : 1; /* MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t rxucgfis : 1; /* MMC Receive Unicast Good Frame Counter Interrupt Status */ + const uint32_t rxlenerfis : 1; /* MMC Receive Length Error Frame Counter Interrupt Status */ + const uint32_t rxorangefis : 1; /* MMC Receive Out Of Range Error Frame Counter Interrupt Status */ + const uint32_t rxpausfis : 1; /* MMC Receive Pause Frame Counter Interrupt Status */ + const uint32_t rxfovfis : 1; /* MMC Receive FIFO Overflow Frame Counter Interrupt Status */ + const uint32_t rxvlangbfis : 1; /* MMC Receive VLAN Good Bad Frame Counter Interrupt Status */ + const uint32_t rxwdogfis : 1; /* MMC Receive Watchdog Error Frame Counter Interrupt Status */ + const uint32_t rxrcverrfis : 1; /* MMC Receive Error Frame Counter Interrupt Status */ + const uint32_t rxctrlfis : 1; /* MMC Receive Control Frame Counter Interrupt Status */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MMC_RX_INT. */ +typedef volatile struct ALT_EMAC_GMAC_MMC_RX_INT_s ALT_EMAC_GMAC_MMC_RX_INT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MMC_RX_INT register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_OFST 0x104 +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_OFST)) + +/* + * Register : Register 66 (MMC Transmit Interrupt Register) - MMC_Transmit_Interrupt + * + * The MMC Transmit Interrupt register maintains the interrupts generated when + * transmit statistic counters reach half of their maximum values (0x8000_0000 for + * 32-bit counter and 0x8000 for 16-bit counter), and the maximum values + * (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter + * Stop Rollover is set, then interrupts are set but the counter remains at all- + * ones. The MMC Transmit Interrupt register is a 32-bit wide register. An + * interrupt bit is cleared when the respective MMC counter that caused the + * interrupt is read. The least significant byte lane (Bits[7:0]) of the respective + * counter must be read in order to clear the interrupt bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------------------------------------------- + * [0] | R | 0x0 | MMC Transmit Good Bad Octet Counter Interrupt Status + * [1] | R | 0x0 | MMC Transmit Good Bad Frame Counter Interrupt Status + * [2] | R | 0x0 | MMC Transmit Broadcast Good Frame Counter Interrupt Status + * [3] | R | 0x0 | MMC Transmit Multicast Good Frame Counter Interrupt Status + * [4] | R | 0x0 | MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. + * [5] | R | 0x0 | MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status + * [6] | R | 0x0 | MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status + * [7] | R | 0x0 | MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status + * [8] | R | 0x0 | MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + * [9] | R | 0x0 | MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status + * [10] | R | 0x0 | MMC Transmit Unicast Good Bad Frame Counter Interrupt Status + * [11] | R | 0x0 | MMC Transmit Multicast Good Bad Frame Counter Interrupt Status + * [12] | R | 0x0 | MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status + * [13] | R | 0x0 | MMC Transmit Underflow Error Frame Counter Interrupt Status + * [14] | R | 0x0 | MMC Transmit Single Collision Good Frame Counter Interrupt Status + * [15] | R | 0x0 | MMC Transmit Multiple Collision Good Frame Counter Interrupt Status + * [16] | R | 0x0 | MMC Transmit Deferred Frame Counter Interrupt Status + * [17] | R | 0x0 | MMC Transmit Late Collision Frame Counter Interrupt Status + * [18] | R | 0x0 | MMC Transmit Excessive Collision Frame Counter Interrupt Status + * [19] | R | 0x0 | MMC Transmit Carrier Error Frame Counter Interrupt Status + * [20] | R | 0x0 | MMC Transmit Good Octet Counter Interrupt Status + * [21] | R | 0x0 | MMC Transmit Good Frame Counter Interrupt Status + * [22] | R | 0x0 | MMC Transmit Excessive Deferral Frame Counter Interrupt Status + * [23] | R | 0x0 | MMC Transmit Pause Frame Counter Interrupt Status + * [24] | R | 0x0 | MMC Transmit VLAN Good Frame Counter Interrupt Status + * [25] | R | 0x0 | MMC Transmit Oversize Good Frame Counter Interrupt Status + * [31:26] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MMC Transmit Good Bad Octet Counter Interrupt Status - txgboctis + * + * This bit is set when the txoctetcount_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT | 0x0 | txoctetcount_gb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT | 0x1 | txoctetcount_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS + * + * txoctetcount_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS + * + * txoctetcount_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MMC Transmit Good Bad Frame Counter Interrupt Status - txgbfrmis + * + * This bit is set when the txframecount_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT | 0x0 | txframecount_gb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT | 0x1 | txframecount_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS + * + * txframecount_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS + * + * txframecount_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MMC Transmit Broadcast Good Frame Counter Interrupt Status - txbcgfis + * + * This bit is set when the txbroadcastframes_g counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT | 0x0 | txbroadcastframes_g < half max + * ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT | 0x1 | txbroadcastframes_g >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS + * + * txbroadcastframes_g < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS + * + * txbroadcastframes_g >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MMC Transmit Multicast Good Frame Counter Interrupt Status - txmcgfis + * + * This bit is set when the txmulticastframes_g counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT | 0x0 | txmulticastframes_g < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT | 0x1 | txmulticastframes_g >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS + * + * txmulticastframes_g < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS + * + * txmulticastframes_g >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. - tx64octgbfis + * + * This bit is set when the tx64octets_gb counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD | 0x0 | tx64octets_gb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END | 0x1 | tx64octets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS + * + * tx64octets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS + * + * tx64octets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status - tx65t127octgbfis + * + * This bit is set when the tx65to127octets_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:-------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT | 0x0 | tx65to127octets_gb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT | 0x1 | tx65to127octets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS + * + * tx65to127octets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS + * + * tx65to127octets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status - tx128t255octgbfis + * + * This bit is set when the tx128to255octets_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT | 0x0 | tx128to255octets_gb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT | 0x1 | tx128to255octets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS + * + * tx128to255octets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS + * + * tx128to255octets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_MSB 6 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status - tx256t511octgbfis + * + * This bit is set when the tx256to511octets_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT | 0x0 | tx256to511octets_gb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT | 0x1 | tx256to511octets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS + * + * tx256to511octets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS + * + * tx256to511octets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - tx512t1023octgbfis + * + * This bit is set when the tx512to1023octets_gb counter reaches half of the + * maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:---------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT | 0x0 | tx512to1023octets_gb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT | 0x1 | tx512to1023octets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS + * + * tx512to1023octets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS + * + * tx512to1023octets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - tx1024tmaxoctgbfis + * + * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the + * maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:----------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT | 0x0 | tx1024tomaxoctets_gb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT | 0x1 | tx1024tomaxoctets_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS + * + * tx1024tomaxoctets_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS + * + * tx1024tomaxoctets_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MMC Transmit Unicast Good Bad Frame Counter Interrupt Status - txucgbfis + * + * This bit is set when the txunicastframes_gb counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT | 0x0 | txunicastframes_bb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT | 0x1 | txunicastframes_bb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS + * + * txunicastframes_bb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS + * + * txunicastframes_bb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MMC Transmit Multicast Good Bad Frame Counter Interrupt Status - txmcgbfis + * + * This bit is set when the txmulticastframes_gb counter reaches half of the + * maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT | 0x0 | txmulticastframes_gb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT | 0x1 | txmulticastframes_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS + * + * txmulticastframes_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS + * + * txmulticastframes_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_MSB 11 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status - txbcgbfis + * + * This bit is set when the txbroadcastframes_gb counter reaches half of the + * maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD | 0x0 | txbroadcastframes_gb < half max + * ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END | 0x1 | txbroadcastframes_gb >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS + * + * txbroadcastframes_gb < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS + * + * txbroadcastframes_gb >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_MSB 12 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET_MSK 0x00001000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_CLR_MSK 0xffffefff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MMC Transmit Underflow Error Frame Counter Interrupt Status - txuflowerfis + * + * This bit is set when the txunderflowerror counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:--------------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD | 0x0 | txunderflowerror counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END | 0x1 | txunderflowerror counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS + * + * txunderflowerror counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS + * + * txunderflowerror counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_MSB 13 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MMC Transmit Single Collision Good Frame Counter Interrupt Status - txscolgfis + * + * This bit is set when the txsinglecol_g counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD | 0x0 | txsinglecol_g counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END | 0x1 | txsinglecol_g counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS + * + * txsinglecol_g counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS + * + * txsinglecol_g counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_MSB 14 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET_MSK 0x00004000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_CLR_MSK 0xffffbfff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : MMC Transmit Multiple Collision Good Frame Counter Interrupt Status - txmcolgfis + * + * This bit is set when the txmulticol_g counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD | 0x0 | txmulticol_g counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END | 0x1 | txmulticol_g counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS + * + * txmulticol_g counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS + * + * txmulticol_g counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET_MSK 0x00008000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_CLR_MSK 0xffff7fff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : MMC Transmit Deferred Frame Counter Interrupt Status - txdeffis + * + * This bit is set when the txdeferred counter reaches half of the maximum value or + * the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD | 0x0 | txdeferred counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END | 0x1 | txdeferred counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS + * + * txdeferred counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS + * + * txdeferred counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MMC Transmit Late Collision Frame Counter Interrupt Status - txlatcolfis + * + * This bit is set when the txlatecol counter reaches half of the maximum value or + * the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD | 0x0 | txlatecol counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END | 0x1 | txlatecol counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS + * + * txlatecol counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS + * + * txlatecol counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_MSB 17 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : MMC Transmit Excessive Collision Frame Counter Interrupt Status - txexcolfis + * + * This bit is set when the txexcesscol counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD | 0x0 | txexesscol counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END | 0x1 | txexesscol counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS + * + * txexesscol counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS + * + * txexesscol counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : MMC Transmit Carrier Error Frame Counter Interrupt Status - txcarerfis + * + * This bit is set when the txcarriererror counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD | 0x0 | txcarriererror counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END | 0x1 | txcarriererror counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS + * + * txcarriererror counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS + * + * txcarriererror counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MMC Transmit Good Octet Counter Interrupt Status - txgoctis + * + * This bit is set when the txoctetcount_g counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD | 0x0 | txoctetcount_g counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END | 0x1 | txoctetcount_g counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS + * + * txoctetcount_g counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS + * + * txoctetcount_g counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : MMC Transmit Good Frame Counter Interrupt Status - txgfrmis + * + * This bit is set when the txframecount_g counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD | 0x0 | txframecount_g counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END | 0x1 | txframecount_g counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS + * + * txframecount_g counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS + * + * txframecount_g counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : MMC Transmit Excessive Deferral Frame Counter Interrupt Status - txexdeffis + * + * This bit is set when the txexcessdef counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD | 0x0 | txoexcessdef counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END | 0x1 | txoexcessdef counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS + * + * txoexcessdef counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS + * + * txoexcessdef counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_MSB 22 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET_MSK 0x00400000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_CLR_MSK 0xffbfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MMC Transmit Pause Frame Counter Interrupt Status - txpausfis + * + * This bit is set when the txpauseframeserror counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD | 0x0 | txpauseframeserror counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END | 0x1 | txpauseframeserror counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS + * + * txpauseframeserror counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS + * + * txpauseframeserror counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_MSB 23 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET_MSK 0x00800000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_CLR_MSK 0xff7fffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : MMC Transmit VLAN Good Frame Counter Interrupt Status - txvlangfis + * + * This bit is set when the txvlanframes_g counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD | 0x0 | txvlanframes_g counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END | 0x1 | txvlanframes_g counter >= half max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS + * + * txvlanframes_g counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS + * + * txvlanframes_g counter >= half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MMC Transmit Oversize Good Frame Counter Interrupt Status - txosizegfis + * + * This bit is set when the txoversize_g counter reaches half of the maximum value + * or the maximum value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MMC_TX_INT. + */ +struct ALT_EMAC_GMAC_MMC_TX_INT_s +{ + const uint32_t txgboctis : 1; /* MMC Transmit Good Bad Octet Counter Interrupt Status */ + const uint32_t txgbfrmis : 1; /* MMC Transmit Good Bad Frame Counter Interrupt Status */ + const uint32_t txbcgfis : 1; /* MMC Transmit Broadcast Good Frame Counter Interrupt Status */ + const uint32_t txmcgfis : 1; /* MMC Transmit Multicast Good Frame Counter Interrupt Status */ + const uint32_t tx64octgbfis : 1; /* MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. */ + const uint32_t tx65t127octgbfis : 1; /* MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t tx128t255octgbfis : 1; /* MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t tx256t511octgbfis : 1; /* MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t tx512t1023octgbfis : 1; /* MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t tx1024tmaxoctgbfis : 1; /* MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status */ + const uint32_t txucgbfis : 1; /* MMC Transmit Unicast Good Bad Frame Counter Interrupt Status */ + const uint32_t txmcgbfis : 1; /* MMC Transmit Multicast Good Bad Frame Counter Interrupt Status */ + const uint32_t txbcgbfis : 1; /* MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status */ + const uint32_t txuflowerfis : 1; /* MMC Transmit Underflow Error Frame Counter Interrupt Status */ + const uint32_t txscolgfis : 1; /* MMC Transmit Single Collision Good Frame Counter Interrupt Status */ + const uint32_t txmcolgfis : 1; /* MMC Transmit Multiple Collision Good Frame Counter Interrupt Status */ + const uint32_t txdeffis : 1; /* MMC Transmit Deferred Frame Counter Interrupt Status */ + const uint32_t txlatcolfis : 1; /* MMC Transmit Late Collision Frame Counter Interrupt Status */ + const uint32_t txexcolfis : 1; /* MMC Transmit Excessive Collision Frame Counter Interrupt Status */ + const uint32_t txcarerfis : 1; /* MMC Transmit Carrier Error Frame Counter Interrupt Status */ + const uint32_t txgoctis : 1; /* MMC Transmit Good Octet Counter Interrupt Status */ + const uint32_t txgfrmis : 1; /* MMC Transmit Good Frame Counter Interrupt Status */ + const uint32_t txexdeffis : 1; /* MMC Transmit Excessive Deferral Frame Counter Interrupt Status */ + const uint32_t txpausfis : 1; /* MMC Transmit Pause Frame Counter Interrupt Status */ + const uint32_t txvlangfis : 1; /* MMC Transmit VLAN Good Frame Counter Interrupt Status */ + const uint32_t txosizegfis : 1; /* MMC Transmit Oversize Good Frame Counter Interrupt Status */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MMC_TX_INT. */ +typedef volatile struct ALT_EMAC_GMAC_MMC_TX_INT_s ALT_EMAC_GMAC_MMC_TX_INT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MMC_TX_INT register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_OFST 0x108 +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_OFST)) + +/* + * Register : Register 67 (MMC Receive Interrupt Mask Register) - MMC_Receive_Interrupt_Mask + * + * The MMC Receive Interrupt Mask register maintains the masks for the interrupts + * generated when the receive statistic counters reach half of their maximum value, + * or maximum value. This register is 32-bits wide. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------------ + * [0] | RW | 0x0 | MMC Receive Good Bad Frame Counter Interrupt Mask + * [1] | RW | 0x0 | MMC Receive Good Bad Octet Counter Interrupt Mask + * [2] | RW | 0x0 | MMC Receive Good Octet Counter Interrupt Mask + * [3] | RW | 0x0 | MMC Receive Broadcast Good Frame Counter Interrupt Mask + * [4] | RW | 0x0 | MMC Receive Multicast Good Frame Counter Interrupt Mask + * [5] | RW | 0x0 | MMC Receive CRC Error Frame Counter Interrupt Mask + * [6] | RW | 0x0 | MMC Receive Alignment Error Frame Counter Interrupt Mask + * [7] | RW | 0x0 | MMC Receive Runt Frame Counter Interrupt Mask + * [8] | RW | 0x0 | MMC Receive Jabber Error Frame Counter Interrupt Mask + * [9] | RW | 0x0 | MMC Receive Undersize Good Frame Counter Interrupt Mask + * [10] | RW | 0x0 | MMC Receive Oversize Good Frame Counter Interrupt Mask + * [11] | RW | 0x0 | MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask + * [12] | RW | 0x0 | MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + * [13] | RW | 0x0 | MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + * [14] | RW | 0x0 | MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + * [15] | RW | 0x0 | MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + * [16] | RW | 0x0 | MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + * [17] | RW | 0x0 | MMC Receive Unicast Good Frame Counter Interrupt Mask + * [18] | RW | 0x0 | MMC Receive Length Error Frame Counter Interrupt Mask + * [19] | RW | 0x0 | MMC Receive Out Of Range Error Frame Counter Interrupt Mask + * [20] | RW | 0x0 | MMC Receive Pause Frame Counter Interrupt Mask + * [21] | RW | 0x0 | MMC Receive FIFO Overflow Frame Counter Interrupt Mask + * [22] | RW | 0x0 | MMC Receive VLAN Good Bad Frame Counter Interrupt Mask + * [23] | RW | 0x0 | MMC Receive Watchdog Error Frame Counter Interrupt Mask + * [24] | RW | 0x0 | MMC Receive Error Frame Counter Interrupt Mask + * [25] | RW | 0x0 | MMC Receive Control Frame Counter Interrupt Mask + * [31:26] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MMC Receive Good Bad Frame Counter Interrupt Mask - rxgbfrmim + * + * Setting this bit masks the interrupt when the rxframecount_gb counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MMC Receive Good Bad Octet Counter Interrupt Mask - rxgboctim + * + * Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MMC Receive Good Octet Counter Interrupt Mask - rxgoctim + * + * Setting this bit masks the interrupt when the rxoctetcount_g counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MMC Receive Broadcast Good Frame Counter Interrupt Mask - rxbcgfim + * + * Setting this bit masks the interrupt when the rxbroadcastframes_g counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MMC Receive Multicast Good Frame Counter Interrupt Mask - rxmcgfim + * + * Setting this bit masks the interrupt when the rxmulticastframes_g counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MMC Receive CRC Error Frame Counter Interrupt Mask - rxcrcerfim + * + * Setting this bit masks the interrupt when the rxcrcerror counter reaches half of + * the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MMC Receive Alignment Error Frame Counter Interrupt Mask - rxalgnerfim + * + * Setting this bit masks the interrupt when the rxalignmenterror counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_MSB 6 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MMC Receive Runt Frame Counter Interrupt Mask - rxruntfim + * + * Setting this bit masks the interrupt when the rxrunterror counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MMC Receive Jabber Error Frame Counter Interrupt Mask - rxjaberfim + * + * Setting this bit masks the interrupt when the rxjabbererror counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MMC Receive Undersize Good Frame Counter Interrupt Mask - rxusizegfim + * + * Setting this bit masks the interrupt when the rxundersize_g counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MMC Receive Oversize Good Frame Counter Interrupt Mask - rxosizegfim + * + * Setting this bit masks the interrupt when the rxoversize_g counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask - rx64octgbfim + * + * Setting this bit masks the interrupt when the rx64octets_gb counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_MSB 11 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET_MSK 0x00000800 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - rx65t127octgbfim + * + * Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_MSB 12 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET_MSK 0x00001000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_CLR_MSK 0xffffefff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - rx128t255octgbfim + * + * Setting this bit masks the interrupt when the rx128to255octets_gb counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_MSB 13 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - rx256t511octgbfim + * + * Setting this bit masks the interrupt when the rx256to511octets_gb counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_MSB 14 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET_MSK 0x00004000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_CLR_MSK 0xffffbfff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - rx512t1023octgbfim + * + * Setting this bit masks the interrupt when the rx512to1023octets_gb counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET_MSK 0x00008000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_CLR_MSK 0xffff7fff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - rx1024tmaxoctgbfim + * + * Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MMC Receive Unicast Good Frame Counter Interrupt Mask - rxucgfim + * + * Setting this bit masks the interrupt when the rxunicastframes_g counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_MSB 17 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET_MSK 0x00020000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_CLR_MSK 0xfffdffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : MMC Receive Length Error Frame Counter Interrupt Mask - rxlenerfim + * + * Setting this bit masks the interrupt when the rxlengtherror counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : MMC Receive Out Of Range Error Frame Counter Interrupt Mask - rxorangefim + * + * Setting this bit masks the interrupt when the rxoutofrangetype counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MMC Receive Pause Frame Counter Interrupt Mask - rxpausfim + * + * Setting this bit masks the interrupt when the rxpauseframes counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : MMC Receive FIFO Overflow Frame Counter Interrupt Mask - rxfovfim + * + * Setting this bit masks the interrupt when the rxfifooverflow counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : MMC Receive VLAN Good Bad Frame Counter Interrupt Mask - rxvlangbfim + * + * Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_MSB 22 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET_MSK 0x00400000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_CLR_MSK 0xffbfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MMC Receive Watchdog Error Frame Counter Interrupt Mask - rxwdogfim + * + * Setting this bit masks the interrupt when the rxwatchdog counter reaches half of + * the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_MSB 23 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET_MSK 0x00800000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_CLR_MSK 0xff7fffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : MMC Receive Error Frame Counter Interrupt Mask - rxrcverrfim + * + * Setting this bit masks the interrupt when the rxrcverror error counter reaches + * half the maximum value, and also when it reaches the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MMC Receive Control Frame Counter Interrupt Mask - rxctrlfim + * + * Setting this bit masks the interrupt when the rxctrlframes counter reaches half + * the maximum value, and also when it reaches the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MMC_RX_INT_MSK. + */ +struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s +{ + uint32_t rxgbfrmim : 1; /* MMC Receive Good Bad Frame Counter Interrupt Mask */ + uint32_t rxgboctim : 1; /* MMC Receive Good Bad Octet Counter Interrupt Mask */ + uint32_t rxgoctim : 1; /* MMC Receive Good Octet Counter Interrupt Mask */ + uint32_t rxbcgfim : 1; /* MMC Receive Broadcast Good Frame Counter Interrupt Mask */ + uint32_t rxmcgfim : 1; /* MMC Receive Multicast Good Frame Counter Interrupt Mask */ + uint32_t rxcrcerfim : 1; /* MMC Receive CRC Error Frame Counter Interrupt Mask */ + uint32_t rxalgnerfim : 1; /* MMC Receive Alignment Error Frame Counter Interrupt Mask */ + uint32_t rxruntfim : 1; /* MMC Receive Runt Frame Counter Interrupt Mask */ + uint32_t rxjaberfim : 1; /* MMC Receive Jabber Error Frame Counter Interrupt Mask */ + uint32_t rxusizegfim : 1; /* MMC Receive Undersize Good Frame Counter Interrupt Mask */ + uint32_t rxosizegfim : 1; /* MMC Receive Oversize Good Frame Counter Interrupt Mask */ + uint32_t rx64octgbfim : 1; /* MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t rx65t127octgbfim : 1; /* MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t rx128t255octgbfim : 1; /* MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t rx256t511octgbfim : 1; /* MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t rx512t1023octgbfim : 1; /* MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t rx1024tmaxoctgbfim : 1; /* MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t rxucgfim : 1; /* MMC Receive Unicast Good Frame Counter Interrupt Mask */ + uint32_t rxlenerfim : 1; /* MMC Receive Length Error Frame Counter Interrupt Mask */ + uint32_t rxorangefim : 1; /* MMC Receive Out Of Range Error Frame Counter Interrupt Mask */ + uint32_t rxpausfim : 1; /* MMC Receive Pause Frame Counter Interrupt Mask */ + uint32_t rxfovfim : 1; /* MMC Receive FIFO Overflow Frame Counter Interrupt Mask */ + uint32_t rxvlangbfim : 1; /* MMC Receive VLAN Good Bad Frame Counter Interrupt Mask */ + uint32_t rxwdogfim : 1; /* MMC Receive Watchdog Error Frame Counter Interrupt Mask */ + uint32_t rxrcverrfim : 1; /* MMC Receive Error Frame Counter Interrupt Mask */ + uint32_t rxctrlfim : 1; /* MMC Receive Control Frame Counter Interrupt Mask */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MMC_RX_INT_MSK. */ +typedef volatile struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s ALT_EMAC_GMAC_MMC_RX_INT_MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST 0x10c +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register. */ +#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST)) + +/* + * Register : Register 68 (MMC Transmit Interrupt Mask Register) - MMC_Transmit_Interrupt_Mask + * + * The MMC Transmit Interrupt Mask register maintains the masks for the interrupts + * generated when the transmit statistic counters reach half of their maximum value + * or maximum value. This register is 32-bits wide. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------------- + * [0] | RW | 0x0 | MMC Transmit Good Bad Octet Counter Interrupt Mask + * [1] | RW | 0x0 | MMC Transmit Good Bad Frame Counter Interrupt Mask + * [2] | RW | 0x0 | MMC Transmit Broadcast Good Frame Counter Interrupt Mask + * [3] | RW | 0x0 | MMC Transmit Multicast Good Frame Counter Interrupt Mask + * [4] | RW | 0x0 | MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask + * [5] | RW | 0x0 | MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + * [6] | RW | 0x0 | MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + * [7] | RW | 0x0 | MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + * [8] | RW | 0x0 | MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + * [9] | RW | 0x0 | MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + * [10] | RW | 0x0 | MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask + * [11] | RW | 0x0 | MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask + * [12] | RW | 0x0 | MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask + * [13] | RW | 0x0 | MMC Transmit Underflow Error Frame Counter Interrupt Mask + * [14] | RW | 0x0 | MMC Transmit Single Collision Good Frame Counter Interrupt Mask + * [15] | RW | 0x0 | MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask + * [16] | RW | 0x0 | MMC Transmit Deferred Frame Counter Interrupt Mask + * [17] | RW | 0x0 | MMC Transmit Late Collision Frame Counter Interrupt Mask + * [18] | RW | 0x0 | MMC Transmit Excessive Collision Frame Counter Interrupt Mask + * [19] | RW | 0x0 | MMC Transmit Carrier Error Frame Counter Interrupt Mask + * [20] | RW | 0x0 | MMC Transmit Good Octet Counter Interrupt Mask + * [21] | RW | 0x0 | MMC Transmit Good Frame Counter Interrupt Mask + * [22] | RW | 0x0 | MMC Transmit Excessive Deferral Frame Counter Interrupt Mask + * [23] | RW | 0x0 | MMC Transmit Pause Frame Counter Interrupt Mask + * [24] | RW | 0x0 | MMC Transmit VLAN Good Frame Counter Interrupt Mask + * [25] | RW | 0x0 | MMC Transmit Oversize Good Frame Counter Interrupt Mask + * [31:26] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MMC Transmit Good Bad Octet Counter Interrupt Mask - txgboctim + * + * Setting this bit masks the interrupt when the txoctetcount_gb counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MMC Transmit Good Bad Frame Counter Interrupt Mask - txgbfrmim + * + * Setting this bit masks the interrupt when the txframecount_gb counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MMC Transmit Broadcast Good Frame Counter Interrupt Mask - txbcgfim + * + * Setting this bit masks the interrupt when the txbroadcastframes_g counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MMC Transmit Multicast Good Frame Counter Interrupt Mask - txmcgfim + * + * Setting this bit masks the interrupt when the txmulticastframes_g counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask - tx64octgbfim + * + * Setting this bit masks the interrupt when the tx64octets_gb counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - tx65t127octgbfim + * + * Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - tx128t255octgbfim + * + * Setting this bit masks the interrupt when the tx128to255octets_gb counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_MSB 6 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - tx256t511octgbfim + * + * Setting this bit masks the interrupt when the tx256to511octets_gb counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - tx512t1023octgbfim + * + * Setting this bit masks the interrupt when the tx512to1023octets_gb counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - tx1024tmaxoctgbfim + * + * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask - txucgbfim + * + * Setting this bit masks the interrupt when the txunicastframes_gb counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask - txmcgbfim + * + * Setting this bit masks the interrupt when the txmulticastframes_gb counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_MSB 11 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET_MSK 0x00000800 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask - txbcgbfim + * + * Setting this bit masks the interrupt when the txbroadcastframes_gb counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_MSB 12 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET_MSK 0x00001000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_CLR_MSK 0xffffefff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MMC Transmit Underflow Error Frame Counter Interrupt Mask - txuflowerfim + * + * Setting this bit masks the interrupt when the txunderflowerror counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_MSB 13 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MMC Transmit Single Collision Good Frame Counter Interrupt Mask - txscolgfim + * + * Setting this bit masks the interrupt when the txsinglecol_g counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_MSB 14 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET_MSK 0x00004000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_CLR_MSK 0xffffbfff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask - txmcolgfim + * + * Setting this bit masks the interrupt when the txmulticol_g counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET_MSK 0x00008000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_CLR_MSK 0xffff7fff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : MMC Transmit Deferred Frame Counter Interrupt Mask - txdeffim + * + * Setting this bit masks the interrupt when the txdeferred counter reaches half of + * the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MMC Transmit Late Collision Frame Counter Interrupt Mask - txlatcolfim + * + * Setting this bit masks the interrupt when the txlatecol counter reaches half of + * the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_MSB 17 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET_MSK 0x00020000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_CLR_MSK 0xfffdffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : MMC Transmit Excessive Collision Frame Counter Interrupt Mask - txexcolfim + * + * Setting this bit masks the interrupt when the txexcesscol counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : MMC Transmit Carrier Error Frame Counter Interrupt Mask - txcarerfim + * + * Setting this bit masks the interrupt when the txcarriererror counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MMC Transmit Good Octet Counter Interrupt Mask - txgoctim + * + * Setting this bit masks the interrupt when the txoctetcount_g counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : MMC Transmit Good Frame Counter Interrupt Mask - txgfrmim + * + * Setting this bit masks the interrupt when the txframecount_g counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : MMC Transmit Excessive Deferral Frame Counter Interrupt Mask - txexdeffim + * + * Setting this bit masks the interrupt when the txexcessdef counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_MSB 22 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET_MSK 0x00400000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_CLR_MSK 0xffbfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MMC Transmit Pause Frame Counter Interrupt Mask - txpausfim + * + * Setting this bit masks the interrupt when the txpauseframes counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_MSB 23 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET_MSK 0x00800000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_CLR_MSK 0xff7fffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : MMC Transmit VLAN Good Frame Counter Interrupt Mask - txvlangfim + * + * Setting this bit masks the interrupt when the txvlanframes_g counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MMC Transmit Oversize Good Frame Counter Interrupt Mask - txosizegfim + * + * Setting this bit masks the interrupt when the txoversize_g counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:--------------------------- + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MMC_TX_INT_MSK. + */ +struct ALT_EMAC_GMAC_MMC_TX_INT_MSK_s +{ + uint32_t txgboctim : 1; /* MMC Transmit Good Bad Octet Counter Interrupt Mask */ + uint32_t txgbfrmim : 1; /* MMC Transmit Good Bad Frame Counter Interrupt Mask */ + uint32_t txbcgfim : 1; /* MMC Transmit Broadcast Good Frame Counter Interrupt Mask */ + uint32_t txmcgfim : 1; /* MMC Transmit Multicast Good Frame Counter Interrupt Mask */ + uint32_t tx64octgbfim : 1; /* MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t tx65t127octgbfim : 1; /* MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t tx128t255octgbfim : 1; /* MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t tx256t511octgbfim : 1; /* MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t tx512t1023octgbfim : 1; /* MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t tx1024tmaxoctgbfim : 1; /* MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask */ + uint32_t txucgbfim : 1; /* MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask */ + uint32_t txmcgbfim : 1; /* MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask */ + uint32_t txbcgbfim : 1; /* MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask */ + uint32_t txuflowerfim : 1; /* MMC Transmit Underflow Error Frame Counter Interrupt Mask */ + uint32_t txscolgfim : 1; /* MMC Transmit Single Collision Good Frame Counter Interrupt Mask */ + uint32_t txmcolgfim : 1; /* MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask */ + uint32_t txdeffim : 1; /* MMC Transmit Deferred Frame Counter Interrupt Mask */ + uint32_t txlatcolfim : 1; /* MMC Transmit Late Collision Frame Counter Interrupt Mask */ + uint32_t txexcolfim : 1; /* MMC Transmit Excessive Collision Frame Counter Interrupt Mask */ + uint32_t txcarerfim : 1; /* MMC Transmit Carrier Error Frame Counter Interrupt Mask */ + uint32_t txgoctim : 1; /* MMC Transmit Good Octet Counter Interrupt Mask */ + uint32_t txgfrmim : 1; /* MMC Transmit Good Frame Counter Interrupt Mask */ + uint32_t txexdeffim : 1; /* MMC Transmit Excessive Deferral Frame Counter Interrupt Mask */ + uint32_t txpausfim : 1; /* MMC Transmit Pause Frame Counter Interrupt Mask */ + uint32_t txvlangfim : 1; /* MMC Transmit VLAN Good Frame Counter Interrupt Mask */ + uint32_t txosizegfim : 1; /* MMC Transmit Oversize Good Frame Counter Interrupt Mask */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MMC_TX_INT_MSK. */ +typedef volatile struct ALT_EMAC_GMAC_MMC_TX_INT_MSK_s ALT_EMAC_GMAC_MMC_TX_INT_MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST 0x110 +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register. */ +#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST)) + +/* + * Register : Register 69 (txoctetcount_gb Register) - txoctetcount_gb + * + * Number of bytes transmitted, exclusive of preamble and retried bytes, in good + * and bad frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | R | 0x0 | txoctetcount_gb + * + */ +/* + * Field : txoctetcount_gb - cnt + * + * Number of bytes transmitted, exclusive of preamble and retried bytes, in good + * and bad frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXOCTETCOUNT_GB. + */ +struct ALT_EMAC_GMAC_TXOCTETCOUNT_GB_s +{ + const uint32_t cnt : 32; /* txoctetcount_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXOCTETCOUNT_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TXOCTETCOUNT_GB_s ALT_EMAC_GMAC_TXOCTETCOUNT_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_OFST 0x114 +/* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register. */ +#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOCTETCOUNT_GB_OFST)) + +/* + * Register : Register 70 (txframecount_gb Register) - txframecount_gb + * + * Number of good and bad frames transmitted, exclusive of retried frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | R | 0x0 | txframecount_gb + * + */ +/* + * Field : txframecount_gb - cnt + * + * Number of good and bad frames transmitted, exclusive of retried frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_GB. + */ +struct ALT_EMAC_GMAC_TXFRMCOUNT_GB_s +{ + const uint32_t cnt : 32; /* txframecount_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TXFRMCOUNT_GB_s ALT_EMAC_GMAC_TXFRMCOUNT_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_OFST 0x118 +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXFRMCOUNT_GB_OFST)) + +/* + * Register : Register 71 (txbroadcastframes_g Register) - txbroadcastframes_g + * + * Number of good broadcast frames transmitted + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | txbroadcastframes_g + * + */ +/* + * Field : txbroadcastframes_g - cnt + * + * Number of good broadcast frames transmitted + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_G. + */ +struct ALT_EMAC_GMAC_TXBCASTFRMS_G_s +{ + const uint32_t cnt : 32; /* txbroadcastframes_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_G. */ +typedef volatile struct ALT_EMAC_GMAC_TXBCASTFRMS_G_s ALT_EMAC_GMAC_TXBCASTFRMS_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXBCASTFRMS_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_G_OFST 0x11c +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXBCASTFRMS_G_OFST)) + +/* + * Register : Register 72 (txmulticastframes_g Register) - txmulticastframes_g + * + * Number of good multicast frames transmitted + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | txmulticastframes_g + * + */ +/* + * Field : txmulticastframes_g - cnt + * + * Number of good multicast frames transmitted + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_G. + */ +struct ALT_EMAC_GMAC_TXMCASTFRMS_G_s +{ + const uint32_t cnt : 32; /* txmulticastframes_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_G. */ +typedef volatile struct ALT_EMAC_GMAC_TXMCASTFRMS_G_s ALT_EMAC_GMAC_TXMCASTFRMS_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXMCASTFRMS_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_G_OFST 0x120 +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMCASTFRMS_G_OFST)) + +/* + * Register : Register 73 (tx64octets_gb Register) - tx64octets_gb + * + * Number of good and bad frames transmitted with length 64 bytes, exclusive of + * preamble and retried frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | tx64octets_gb + * + */ +/* + * Field : tx64octets_gb - cnt + * + * Number of good and bad frames transmitted with length 64 bytes, exclusive of + * preamble and retried frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TX64OCTETS_GB. + */ +struct ALT_EMAC_GMAC_TX64OCTETS_GB_s +{ + const uint32_t cnt : 32; /* tx64octets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TX64OCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TX64OCTETS_GB_s ALT_EMAC_GMAC_TX64OCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TX64OCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TX64OCTETS_GB_OFST 0x124 +/* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register. */ +#define ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX64OCTETS_GB_OFST)) + +/* + * Register : Register 74 (tx65to127octets_gb Register) - tx65to127octets_gb + * + * Number of good and bad frames transmitted with length between 65 and 127 + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [31:0] | R | 0x0 | tx65to127octets_gb + * + */ +/* + * Field : tx65to127octets_gb - cnt + * + * Number of good and bad frames transmitted with length between 65 and 127 + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TX65TO127OCTETS_GB. + */ +struct ALT_EMAC_GMAC_TX65TO127OCTETS_GB_s +{ + const uint32_t cnt : 32; /* tx65to127octets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TX65TO127OCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TX65TO127OCTETS_GB_s ALT_EMAC_GMAC_TX65TO127OCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_OFST 0x128 +/* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register. */ +#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX65TO127OCTETS_GB_OFST)) + +/* + * Register : Register 75 (tx128to255octets_gb Register) - tx128to255octets_gb + * + * Number of good and bad frames transmitted with length between 128 and 255 + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | tx128to255octets_gb + * + */ +/* + * Field : tx128to255octets_gb - cnt + * + * Number of good and bad frames transmitted with length between 128 and 255 + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TX128TO255OCTETS_GB. + */ +struct ALT_EMAC_GMAC_TX128TO255OCTETS_GB_s +{ + const uint32_t cnt : 32; /* tx128to255octets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TX128TO255OCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TX128TO255OCTETS_GB_s ALT_EMAC_GMAC_TX128TO255OCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_OFST 0x12c +/* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register. */ +#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX128TO255OCTETS_GB_OFST)) + +/* + * Register : Register 76 (tx256to511octets_gb Register) - tx256to511octets_gb + * + * Number of good and bad frames transmitted with length between 256 and 511 + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | tx256to511octets_gb + * + */ +/* + * Field : tx256to511octets_gb - cnt + * + * Number of good and bad frames transmitted with length between 256 and 511 + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TX256TO511OCTETS_GB. + */ +struct ALT_EMAC_GMAC_TX256TO511OCTETS_GB_s +{ + const uint32_t cnt : 32; /* tx256to511octets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TX256TO511OCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TX256TO511OCTETS_GB_s ALT_EMAC_GMAC_TX256TO511OCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_OFST 0x130 +/* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register. */ +#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX256TO511OCTETS_GB_OFST)) + +/* + * Register : Register 77 (tx512to1023octets_gb Register) - tx512to1023octets_gb + * + * Number of good and bad frames transmitted with length between 512 and 1,023 + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | R | 0x0 | tx512to1023octets_gb + * + */ +/* + * Field : tx512to1023octets_gb - cnt + * + * Number of good and bad frames transmitted with length between 512 and 1,023 + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TX512TO1023OCTETS_GB. + */ +struct ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_s +{ + const uint32_t cnt : 32; /* tx512to1023octets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TX512TO1023OCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_s ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_OFST 0x134 +/* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register. */ +#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_OFST)) + +/* + * Register : Register 78 (tx1024tomaxoctets_gb Register) - tx1024tomaxoctets_gb + * + * Number of good and bad frames transmitted with length between 1,024 and maxsize + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | R | 0x0 | tx1024tomaxoctets_gb + * + */ +/* + * Field : tx1024tomaxoctets_gb - cnt + * + * Number of good and bad frames transmitted with length between 1,024 and maxsize + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB. + */ +struct ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_s +{ + const uint32_t cnt : 32; /* tx1024tomaxoctets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_s ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_OFST 0x138 +/* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register. */ +#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_OFST)) + +/* + * Register : Register 79 (txunicastframes_gb Register) - txunicastframes_gb + * + * Number of good and bad unicast frames transmitted + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [31:0] | R | 0x0 | txunicastframes_gb + * + */ +/* + * Field : txunicastframes_gb - cnt + * + * Number of good and bad unicast frames transmitted + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXUNICASTFRMS_GB. + */ +struct ALT_EMAC_GMAC_TXUNICASTFRMS_GB_s +{ + const uint32_t cnt : 32; /* txunicastframes_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXUNICASTFRMS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TXUNICASTFRMS_GB_s ALT_EMAC_GMAC_TXUNICASTFRMS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_OFST 0x13c +/* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register. */ +#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXUNICASTFRMS_GB_OFST)) + +/* + * Register : Register 80 (txmulticastframes_gb Register) - txmulticastframes_gb + * + * Number of good and bad multicast frames transmitted + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | R | 0x0 | txmulticastframes_gb + * + */ +/* + * Field : txmulticastframes_gb - cnt + * + * Number of good and bad multicast frames transmitted + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_GB. + */ +struct ALT_EMAC_GMAC_TXMCASTFRMS_GB_s +{ + const uint32_t cnt : 32; /* txmulticastframes_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TXMCASTFRMS_GB_s ALT_EMAC_GMAC_TXMCASTFRMS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_OFST 0x140 +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register. */ +#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMCASTFRMS_GB_OFST)) + +/* + * Register : Register 81 (txbroadcastframes_gb Register) - txbroadcastframes_gb + * + * Number of good and bad broadcast frames transmitted + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | R | 0x0 | txbroadcastframes_gb + * + */ +/* + * Field : txbroadcastframes_gb - cnt + * + * Number of good and bad broadcast frames transmitted + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_GB. + */ +struct ALT_EMAC_GMAC_TXBCASTFRMS_GB_s +{ + const uint32_t cnt : 32; /* txbroadcastframes_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_TXBCASTFRMS_GB_s ALT_EMAC_GMAC_TXBCASTFRMS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_OFST 0x144 +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register. */ +#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXBCASTFRMS_GB_OFST)) + +/* + * Register : Register 82 (txunderflowerror Register) - txunderflowerror + * + * Number of frames aborted due to frame underflow error + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | R | 0x0 | txunderflowerror + * + */ +/* + * Field : txunderflowerror - cnt + * + * Number of frames aborted due to frame underflow error + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */ +#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */ +#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */ +#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */ +#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXUNDERFLOWERROR. + */ +struct ALT_EMAC_GMAC_TXUNDERFLOWERROR_s +{ + const uint32_t cnt : 32; /* txunderflowerror */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXUNDERFLOWERROR. */ +typedef volatile struct ALT_EMAC_GMAC_TXUNDERFLOWERROR_s ALT_EMAC_GMAC_TXUNDERFLOWERROR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_OFST 0x148 +/* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register. */ +#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXUNDERFLOWERROR_OFST)) + +/* + * Register : Register 83 (txsinglecol_g Register) - txsinglecol_g + * + * Number of successfully transmitted frames after a single collision in Half- + * duplex mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | txsinglecol_g + * + */ +/* + * Field : txsinglecol_g - cnt + * + * Number of successfully transmitted frames after a single collision in Half- + * duplex mode + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXSINGLECOL_G. + */ +struct ALT_EMAC_GMAC_TXSINGLECOL_G_s +{ + const uint32_t cnt : 32; /* txsinglecol_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXSINGLECOL_G. */ +typedef volatile struct ALT_EMAC_GMAC_TXSINGLECOL_G_s ALT_EMAC_GMAC_TXSINGLECOL_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXSINGLECOL_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXSINGLECOL_G_OFST 0x14c +/* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register. */ +#define ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXSINGLECOL_G_OFST)) + +/* + * Register : Register 84 (txmulticol_g Register) - txmulticol_g + * + * Number of successfully transmitted frames after more than a single collision in + * Half-duplex mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | R | 0x0 | txmulticol_g + * + */ +/* + * Field : txmulticol_g - cnt + * + * Number of successfully transmitted frames after more than a single collision in + * Half-duplex mode + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXMULTICOL_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXMULTICOL_G. + */ +struct ALT_EMAC_GMAC_TXMULTICOL_G_s +{ + const uint32_t cnt : 32; /* txmulticol_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXMULTICOL_G. */ +typedef volatile struct ALT_EMAC_GMAC_TXMULTICOL_G_s ALT_EMAC_GMAC_TXMULTICOL_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXMULTICOL_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXMULTICOL_G_OFST 0x150 +/* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register. */ +#define ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMULTICOL_G_OFST)) + +/* + * Register : Register 85 (txdeferred Register) - txdeferred + * + * Number of successfully transmitted frames after a deferral in Halfduplex mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | txdeferred + * + */ +/* + * Field : txdeferred - cnt + * + * Number of successfully transmitted frames after a deferral in Halfduplex mode + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */ +#define ALT_EMAC_GMAC_TXDEFERRED_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */ +#define ALT_EMAC_GMAC_TXDEFERRED_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */ +#define ALT_EMAC_GMAC_TXDEFERRED_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXDEFERRED_CNT register field value. */ +#define ALT_EMAC_GMAC_TXDEFERRED_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXDEFERRED_CNT register field value. */ +#define ALT_EMAC_GMAC_TXDEFERRED_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */ +#define ALT_EMAC_GMAC_TXDEFERRED_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXDEFERRED_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXDEFERRED_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXDEFERRED_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXDEFERRED_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXDEFERRED. + */ +struct ALT_EMAC_GMAC_TXDEFERRED_s +{ + const uint32_t cnt : 32; /* txdeferred */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXDEFERRED. */ +typedef volatile struct ALT_EMAC_GMAC_TXDEFERRED_s ALT_EMAC_GMAC_TXDEFERRED_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXDEFERRED register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXDEFERRED_OFST 0x154 +/* The address of the ALT_EMAC_GMAC_TXDEFERRED register. */ +#define ALT_EMAC_GMAC_TXDEFERRED_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXDEFERRED_OFST)) + +/* + * Register : Register 86 (txlatecol Register) - txlatecol + * + * Number of frames aborted due to late collision error + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | txlatecol + * + */ +/* + * Field : txlatecol - cnt + * + * Number of frames aborted due to late collision error + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */ +#define ALT_EMAC_GMAC_TXLATECOL_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */ +#define ALT_EMAC_GMAC_TXLATECOL_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */ +#define ALT_EMAC_GMAC_TXLATECOL_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXLATECOL_CNT register field value. */ +#define ALT_EMAC_GMAC_TXLATECOL_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXLATECOL_CNT register field value. */ +#define ALT_EMAC_GMAC_TXLATECOL_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */ +#define ALT_EMAC_GMAC_TXLATECOL_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXLATECOL_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXLATECOL_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXLATECOL_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXLATECOL_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXLATECOL. + */ +struct ALT_EMAC_GMAC_TXLATECOL_s +{ + const uint32_t cnt : 32; /* txlatecol */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXLATECOL. */ +typedef volatile struct ALT_EMAC_GMAC_TXLATECOL_s ALT_EMAC_GMAC_TXLATECOL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXLATECOL register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXLATECOL_OFST 0x158 +/* The address of the ALT_EMAC_GMAC_TXLATECOL register. */ +#define ALT_EMAC_GMAC_TXLATECOL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXLATECOL_OFST)) + +/* + * Register : Register 87 (txexesscol Register) - txexesscol + * + * Number of frames aborted due to excessive (16) collision errors + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | txexesscol + * + */ +/* + * Field : txexesscol - cnt + * + * Number of frames aborted due to excessive (16) collision errors + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */ +#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */ +#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */ +#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value. */ +#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value. */ +#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */ +#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXEXESSCOL_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXEXESSCOL. + */ +struct ALT_EMAC_GMAC_TXEXESSCOL_s +{ + const uint32_t cnt : 32; /* txexesscol */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXEXESSCOL. */ +typedef volatile struct ALT_EMAC_GMAC_TXEXESSCOL_s ALT_EMAC_GMAC_TXEXESSCOL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXEXESSCOL register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXEXESSCOL_OFST 0x15c +/* The address of the ALT_EMAC_GMAC_TXEXESSCOL register. */ +#define ALT_EMAC_GMAC_TXEXESSCOL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXEXESSCOL_OFST)) + +/* + * Register : Register 88 (txcarriererror Register) - txcarriererr + * + * Number of frames aborted due to carrier sense error (no carrier or loss of + * carrier) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | txcarriererror + * + */ +/* + * Field : txcarriererror - cnt + * + * Number of frames aborted due to carrier sense error (no carrier or loss of + * carrier) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */ +#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */ +#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */ +#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value. */ +#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value. */ +#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */ +#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXCARRIERERR_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXCARRIERERR. + */ +struct ALT_EMAC_GMAC_TXCARRIERERR_s +{ + const uint32_t cnt : 32; /* txcarriererror */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXCARRIERERR. */ +typedef volatile struct ALT_EMAC_GMAC_TXCARRIERERR_s ALT_EMAC_GMAC_TXCARRIERERR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXCARRIERERR register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXCARRIERERR_OFST 0x160 +/* The address of the ALT_EMAC_GMAC_TXCARRIERERR register. */ +#define ALT_EMAC_GMAC_TXCARRIERERR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXCARRIERERR_OFST)) + +/* + * Register : Register 89 (txoctetcount_g Register) - txoctetcnt + * + * Number of bytes transmitted, exclusive of preamble, in good frames only + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | txoctetcount_g + * + */ +/* + * Field : txoctetcount_g - txoctetcount_g + * + * Number of bytes transmitted, exclusive of preamble, in good frames only + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */ +#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */ +#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */ +#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value. */ +#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value. */ +#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */ +#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G field value from a register. */ +#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXOCTETCNT. + */ +struct ALT_EMAC_GMAC_TXOCTETCNT_s +{ + const uint32_t txoctetcount_g : 32; /* txoctetcount_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXOCTETCNT. */ +typedef volatile struct ALT_EMAC_GMAC_TXOCTETCNT_s ALT_EMAC_GMAC_TXOCTETCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXOCTETCNT register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXOCTETCNT_OFST 0x164 +/* The address of the ALT_EMAC_GMAC_TXOCTETCNT register. */ +#define ALT_EMAC_GMAC_TXOCTETCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOCTETCNT_OFST)) + +/* + * Register : Register 90 (txframecount_g Register) - txframecount_g + * + * Number of good frames transmitted + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | txframecount_g + * + */ +/* + * Field : txframecount_g - cnt + * + * Number of good frames transmitted + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_G. + */ +struct ALT_EMAC_GMAC_TXFRMCOUNT_G_s +{ + const uint32_t cnt : 32; /* txframecount_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_G. */ +typedef volatile struct ALT_EMAC_GMAC_TXFRMCOUNT_G_s ALT_EMAC_GMAC_TXFRMCOUNT_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXFRMCOUNT_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_G_OFST 0x168 +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register. */ +#define ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXFRMCOUNT_G_OFST)) + +/* + * Register : Register 91 (txexcessdef Register) - txexcessdef + * + * Number of frames aborted due to excessive deferral error (deferred for more than + * two max-sized frame times) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | txexcessdef + * + */ +/* + * Field : txexcessdef - cnt + * + * Number of frames aborted due to excessive deferral error (deferred for more than + * two max-sized frame times) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */ +#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */ +#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */ +#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value. */ +#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value. */ +#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */ +#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXEXCESSDEF_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXEXCESSDEF. + */ +struct ALT_EMAC_GMAC_TXEXCESSDEF_s +{ + const uint32_t cnt : 32; /* txexcessdef */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXEXCESSDEF. */ +typedef volatile struct ALT_EMAC_GMAC_TXEXCESSDEF_s ALT_EMAC_GMAC_TXEXCESSDEF_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXEXCESSDEF register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXEXCESSDEF_OFST 0x16c +/* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register. */ +#define ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXEXCESSDEF_OFST)) + +/* + * Register : Register 92 (txpauseframes Register) - txpauseframes + * + * Number of good PAUSE frames transmitted + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | txpauseframes + * + */ +/* + * Field : txpauseframes - cnt + * + * Number of good PAUSE frames transmitted + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */ +#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */ +#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */ +#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */ +#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXPAUSEFRMS. + */ +struct ALT_EMAC_GMAC_TXPAUSEFRMS_s +{ + const uint32_t cnt : 32; /* txpauseframes */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXPAUSEFRMS. */ +typedef volatile struct ALT_EMAC_GMAC_TXPAUSEFRMS_s ALT_EMAC_GMAC_TXPAUSEFRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXPAUSEFRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXPAUSEFRMS_OFST 0x170 +/* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register. */ +#define ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXPAUSEFRMS_OFST)) + +/* + * Register : Register 93 (txvlanframes_g Register) - txvlanframes_g + * + * Number of good VLAN frames transmitted, exclusive of retried frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | txvlanframes_g + * + */ +/* + * Field : txvlanframes_g - cnt + * + * Number of good VLAN frames transmitted, exclusive of retried frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXVLANFRMS_G. + */ +struct ALT_EMAC_GMAC_TXVLANFRMS_G_s +{ + const uint32_t cnt : 32; /* txvlanframes_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXVLANFRMS_G. */ +typedef volatile struct ALT_EMAC_GMAC_TXVLANFRMS_G_s ALT_EMAC_GMAC_TXVLANFRMS_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXVLANFRMS_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXVLANFRMS_G_OFST 0x174 +/* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register. */ +#define ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXVLANFRMS_G_OFST)) + +/* + * Register : Register 94 (txoversize_g Register) - txoversize_g + * + * Number of good and bad frames received + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | R | 0x0 | txoversize_g + * + */ +/* + * Field : txoversize_g - cnt + * + * Number of good and bad frames received + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value. */ +#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TXOVERSIZE_G. + */ +struct ALT_EMAC_GMAC_TXOVERSIZE_G_s +{ + const uint32_t cnt : 32; /* txoversize_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TXOVERSIZE_G. */ +typedef volatile struct ALT_EMAC_GMAC_TXOVERSIZE_G_s ALT_EMAC_GMAC_TXOVERSIZE_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TXOVERSIZE_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TXOVERSIZE_G_OFST 0x178 +/* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register. */ +#define ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOVERSIZE_G_OFST)) + +/* + * Register : Register 95 (rxframecount_gb Register) - rxframecount_gb + * + * Number of good and bad frames received + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT + * + */ +/* + * Field : cnt + * + * Number of good and bad frames received + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXFRMCOUNT_GB. + */ +struct ALT_EMAC_GMAC_RXFRMCOUNT_GB_s +{ + const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXFRMCOUNT_GB. */ +typedef volatile struct ALT_EMAC_GMAC_RXFRMCOUNT_GB_s ALT_EMAC_GMAC_RXFRMCOUNT_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_OFST 0x180 +/* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register. */ +#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXFRMCOUNT_GB_OFST)) + +/* + * Register : Register 97 (rxoctetcount_gb Register) - rxoctetcount_gb + * + * Number of bytes received, exclusive of preamble, in good and bad frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | R | 0x0 | rxoctetcount_gb + * + */ +/* + * Field : rxoctetcount_gb - cnt + * + * Number of bytes received, exclusive of preamble, in good and bad frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_GB. + */ +struct ALT_EMAC_GMAC_RXOCTETCOUNT_GB_s +{ + const uint32_t cnt : 32; /* rxoctetcount_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_GB. */ +typedef volatile struct ALT_EMAC_GMAC_RXOCTETCOUNT_GB_s ALT_EMAC_GMAC_RXOCTETCOUNT_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_OFST 0x184 +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOCTETCOUNT_GB_OFST)) + +/* + * Register : Register 98 (rxoctetcount_g Register) - rxoctetcount_g + * + * Number of bytes received, exclusive of preamble, only in good frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | rxoctetcount_g + * + */ +/* + * Field : rxoctetcount_g - cnt + * + * Number of bytes received, exclusive of preamble, only in good frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_G. + */ +struct ALT_EMAC_GMAC_RXOCTETCOUNT_G_s +{ + const uint32_t cnt : 32; /* rxoctetcount_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_G. */ +typedef volatile struct ALT_EMAC_GMAC_RXOCTETCOUNT_G_s ALT_EMAC_GMAC_RXOCTETCOUNT_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_OFST 0x188 +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register. */ +#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOCTETCOUNT_G_OFST)) + +/* + * Register : Register 99 (rxbroadcastframes_g Register) - rxbroadcastframes_g + * + * Number of good broadcast frames received + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | rxbroadcastframes_g + * + */ +/* + * Field : rxbroadcastframes_g - cnt + * + * Number of good broadcast frames received + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXBCASTFRMS_G. + */ +struct ALT_EMAC_GMAC_RXBCASTFRMS_G_s +{ + const uint32_t cnt : 32; /* rxbroadcastframes_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXBCASTFRMS_G. */ +typedef volatile struct ALT_EMAC_GMAC_RXBCASTFRMS_G_s ALT_EMAC_GMAC_RXBCASTFRMS_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXBCASTFRMS_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXBCASTFRMS_G_OFST 0x18c +/* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register. */ +#define ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXBCASTFRMS_G_OFST)) + +/* + * Register : Register 100 (rxmulticastframes_g Register) - rxmulticastframes_g + * + * Number of good multicast frames received + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | rxmulticastframes_g + * + */ +/* + * Field : rxmulticastframes_g - cnt + * + * Number of good multicast frames received + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXMCASTFRMS_G. + */ +struct ALT_EMAC_GMAC_RXMCASTFRMS_G_s +{ + const uint32_t cnt : 32; /* rxmulticastframes_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXMCASTFRMS_G. */ +typedef volatile struct ALT_EMAC_GMAC_RXMCASTFRMS_G_s ALT_EMAC_GMAC_RXMCASTFRMS_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXMCASTFRMS_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXMCASTFRMS_G_OFST 0x190 +/* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register. */ +#define ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXMCASTFRMS_G_OFST)) + +/* + * Register : Register 101 (rxcrcerror Register) - rxcrcerror + * + * Number of frames received with CRC error + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | rxcrcerror + * + */ +/* + * Field : rxcrcerror - cnt + * + * Number of frames received with CRC error + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXCRCERROR_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXCRCERROR_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXCRCERROR_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXCRCERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXCRCERROR_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXCRCERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXCRCERROR_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXCRCERROR_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXCRCERROR_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXCRCERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXCRCERROR_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXCRCERROR_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXCRCERROR. + */ +struct ALT_EMAC_GMAC_RXCRCERROR_s +{ + const uint32_t cnt : 32; /* rxcrcerror */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXCRCERROR. */ +typedef volatile struct ALT_EMAC_GMAC_RXCRCERROR_s ALT_EMAC_GMAC_RXCRCERROR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXCRCERROR register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXCRCERROR_OFST 0x194 +/* The address of the ALT_EMAC_GMAC_RXCRCERROR register. */ +#define ALT_EMAC_GMAC_RXCRCERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXCRCERROR_OFST)) + +/* + * Register : Register 102 (rxalignmenterror Register) - rxalignmenterror + * + * Number of frames received with alignment (dribble) error. Valid only in 10/100 + * mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | R | 0x0 | rxalignmenterror + * + */ +/* + * Field : rxalignmenterror - cnt + * + * Number of frames received with alignment (dribble) error. Valid only in 10/100 + * mode + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXALIGNMENTERROR. + */ +struct ALT_EMAC_GMAC_RXALIGNMENTERROR_s +{ + const uint32_t cnt : 32; /* rxalignmenterror */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXALIGNMENTERROR. */ +typedef volatile struct ALT_EMAC_GMAC_RXALIGNMENTERROR_s ALT_EMAC_GMAC_RXALIGNMENTERROR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXALIGNMENTERROR register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXALIGNMENTERROR_OFST 0x198 +/* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register. */ +#define ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXALIGNMENTERROR_OFST)) + +/* + * Register : Register 103 (rxrunterror Register) - rxrunterror + * + * Number of frames received with runt (<64 bytes and CRC error) error + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | rxrunterror + * + */ +/* + * Field : rxrunterror - cnt + * + * Number of frames received with runt (<64 bytes and CRC error) error + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXRUNTERROR_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXRUNTERROR. + */ +struct ALT_EMAC_GMAC_RXRUNTERROR_s +{ + const uint32_t cnt : 32; /* rxrunterror */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXRUNTERROR. */ +typedef volatile struct ALT_EMAC_GMAC_RXRUNTERROR_s ALT_EMAC_GMAC_RXRUNTERROR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXRUNTERROR register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXRUNTERROR_OFST 0x19c +/* The address of the ALT_EMAC_GMAC_RXRUNTERROR register. */ +#define ALT_EMAC_GMAC_RXRUNTERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXRUNTERROR_OFST)) + +/* + * Register : Register 104 (rxjabbererror Register) - rxjabbererror + * + * Number of giant frames received with length (including CRC) greater than 1,518 + * bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is + * enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) + * are considered as giant frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | rxjabbererror + * + */ +/* + * Field : rxjabbererror - cnt + * + * Number of giant frames received with length (including CRC) greater than 1,518 + * bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is + * enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) + * are considered as giant frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXJABBERERROR_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXJABBERERROR. + */ +struct ALT_EMAC_GMAC_RXJABBERERROR_s +{ + const uint32_t cnt : 32; /* rxjabbererror */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXJABBERERROR. */ +typedef volatile struct ALT_EMAC_GMAC_RXJABBERERROR_s ALT_EMAC_GMAC_RXJABBERERROR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXJABBERERROR register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXJABBERERROR_OFST 0x1a0 +/* The address of the ALT_EMAC_GMAC_RXJABBERERROR register. */ +#define ALT_EMAC_GMAC_RXJABBERERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXJABBERERROR_OFST)) + +/* + * Register : Register 105 (rxundersize_g Register) - rxundersize_g + * + * Number of frames received with length less than 64 bytes, without any errors + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | rxundersize_g + * + */ +/* + * Field : rxundersize_g - cnt + * + * Number of frames received with length less than 64 bytes, without any errors + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXUNDERSIZE_G. + */ +struct ALT_EMAC_GMAC_RXUNDERSIZE_G_s +{ + const uint32_t cnt : 32; /* rxundersize_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXUNDERSIZE_G. */ +typedef volatile struct ALT_EMAC_GMAC_RXUNDERSIZE_G_s ALT_EMAC_GMAC_RXUNDERSIZE_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXUNDERSIZE_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXUNDERSIZE_G_OFST 0x1a4 +/* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register. */ +#define ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUNDERSIZE_G_OFST)) + +/* + * Register : Register 106 (rxoversize_g Register) - rxoversize_g + * + * Number of frames received with length greater than the maxsize (1,518 or 1,522 + * for VLAN tagged frames), without errors + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | R | 0x0 | rxoversize_g + * + */ +/* + * Field : rxoversize_g - cnt + * + * Number of frames received with length greater than the maxsize (1,518 or 1,522 + * for VLAN tagged frames), without errors + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXOVERSIZE_G. + */ +struct ALT_EMAC_GMAC_RXOVERSIZE_G_s +{ + const uint32_t cnt : 32; /* rxoversize_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXOVERSIZE_G. */ +typedef volatile struct ALT_EMAC_GMAC_RXOVERSIZE_G_s ALT_EMAC_GMAC_RXOVERSIZE_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXOVERSIZE_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXOVERSIZE_G_OFST 0x1a8 +/* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register. */ +#define ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOVERSIZE_G_OFST)) + +/* + * Register : Register 107 (rx64octets_gb Register) - rx64octets_gb + * + * Number of good and bad frames received with length 64 bytes, exclusive of + * preamble + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | rx64octets_gb + * + */ +/* + * Field : rx64octets_gb - cnt + * + * Number of good and bad frames received with length 64 bytes, exclusive of + * preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RX64OCTETS_GB. + */ +struct ALT_EMAC_GMAC_RX64OCTETS_GB_s +{ + const uint32_t cnt : 32; /* rx64octets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RX64OCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_RX64OCTETS_GB_s ALT_EMAC_GMAC_RX64OCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RX64OCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RX64OCTETS_GB_OFST 0x1ac +/* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register. */ +#define ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX64OCTETS_GB_OFST)) + +/* + * Register : Register 108 (rx65to127octets_gb Register) - rx65to127octets_gb + * + * Number of good and bad frames received with length between 65 and 127 + * (inclusive) bytes, exclusive of preamble + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [31:0] | R | 0x0 | rx65to127octets_gb + * + */ +/* + * Field : rx65to127octets_gb - cnt + * + * Number of good and bad frames received with length between 65 and 127 + * (inclusive) bytes, exclusive of preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RX65TO127OCTETS_GB. + */ +struct ALT_EMAC_GMAC_RX65TO127OCTETS_GB_s +{ + const uint32_t cnt : 32; /* rx65to127octets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RX65TO127OCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_RX65TO127OCTETS_GB_s ALT_EMAC_GMAC_RX65TO127OCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_OFST 0x1b0 +/* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register. */ +#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX65TO127OCTETS_GB_OFST)) + +/* + * Register : Register 109 (rx128to255octets_gb Register) - rx128to255octets_gb + * + * Number of good and bad frames received with length between 128 and 255 + * (inclusive) bytes, exclusive of preamble + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | rx128to255octets_gb + * + */ +/* + * Field : rx128to255octets_gb - cnt + * + * Number of good and bad frames received with length between 128 and 255 + * (inclusive) bytes, exclusive of preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RX128TO255OCTETS_GB. + */ +struct ALT_EMAC_GMAC_RX128TO255OCTETS_GB_s +{ + const uint32_t cnt : 32; /* rx128to255octets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RX128TO255OCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_RX128TO255OCTETS_GB_s ALT_EMAC_GMAC_RX128TO255OCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_OFST 0x1b4 +/* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register. */ +#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX128TO255OCTETS_GB_OFST)) + +/* + * Register : Register 110 (rx256to511octets_gb Register) - rx256to511octets_gb + * + * Number of good and bad frames received with length between 256 and 511 + * (inclusive) bytes, exclusive of preamble + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | rx256to511octets_gb + * + */ +/* + * Field : rx256to511octets_gb - cnt + * + * Number of good and bad frames received with length between 256 and 511 + * (inclusive) bytes, exclusive of preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RX256TO511OCTETS_GB. + */ +struct ALT_EMAC_GMAC_RX256TO511OCTETS_GB_s +{ + const uint32_t cnt : 32; /* rx256to511octets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RX256TO511OCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_RX256TO511OCTETS_GB_s ALT_EMAC_GMAC_RX256TO511OCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_OFST 0x1b8 +/* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register. */ +#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX256TO511OCTETS_GB_OFST)) + +/* + * Register : Register 111 (rx512to1023octets_gb Register) - rx512to1023octets_gb + * + * Number of good and bad frames received with length between 512 and 1,023 + * (inclusive) bytes, exclusive of preamble + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | R | 0x0 | rx512to1023octets_gb + * + */ +/* + * Field : rx512to1023octets_gb - cnt + * + * Number of good and bad frames received with length between 512 and 1,023 + * (inclusive) bytes, exclusive of preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RX512TO1023OCTETS_GB. + */ +struct ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_s +{ + const uint32_t cnt : 32; /* rx512to1023octets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RX512TO1023OCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_s ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_OFST 0x1bc +/* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register. */ +#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_OFST)) + +/* + * Register : Register 112 (rx1024tomaxoctets_gb Register) - rx1024tomaxoctets_gb + * + * Number of good and bad frames received with length between 1,024 and maxsize + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | R | 0x0 | rx1024tomaxoctets_gb + * + */ +/* + * Field : rx1024tomaxoctets_gb - cnt + * + * Number of good and bad frames received with length between 1,024 and maxsize + * (inclusive) bytes, exclusive of preamble and retried frames + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB. + */ +struct ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_s +{ + const uint32_t cnt : 32; /* rx1024tomaxoctets_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_s ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_OFST 0x1c0 +/* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register. */ +#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_OFST)) + +/* + * Register : Register 113 (rxunicastframes_g Register) - rxunicastframes_g + * + * Number of good unicast frames received + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [31:0] | R | 0x0 | rxunicastframes_g + * + */ +/* + * Field : rxunicastframes_g - cnt + * + * Number of good unicast frames received + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXUNICASTFRMS_G. + */ +struct ALT_EMAC_GMAC_RXUNICASTFRMS_G_s +{ + const uint32_t cnt : 32; /* rxunicastframes_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXUNICASTFRMS_G. */ +typedef volatile struct ALT_EMAC_GMAC_RXUNICASTFRMS_G_s ALT_EMAC_GMAC_RXUNICASTFRMS_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_OFST 0x1c4 +/* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register. */ +#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUNICASTFRMS_G_OFST)) + +/* + * Register : Register 114 (rxlengtherror Register) - rxlengtherror + * + * Number of frames received with length error (length type field not equal to + * frame size), for all frames with valid length field + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | rxlengtherror + * + */ +/* + * Field : rxlengtherror - cnt + * + * Number of frames received with length error (length type field not equal to + * frame size), for all frames with valid length field + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXLENERROR_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXLENERROR_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXLENERROR_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXLENERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXLENERROR_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXLENERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXLENERROR_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXLENERROR_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXLENERROR_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXLENERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXLENERROR_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXLENERROR_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXLENERROR. + */ +struct ALT_EMAC_GMAC_RXLENERROR_s +{ + const uint32_t cnt : 32; /* rxlengtherror */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXLENERROR. */ +typedef volatile struct ALT_EMAC_GMAC_RXLENERROR_s ALT_EMAC_GMAC_RXLENERROR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXLENERROR register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXLENERROR_OFST 0x1c8 +/* The address of the ALT_EMAC_GMAC_RXLENERROR register. */ +#define ALT_EMAC_GMAC_RXLENERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXLENERROR_OFST)) + +/* + * Register : Register 115 (rxoutofrangetype Register) - rxoutofrangetype + * + * Number of frames received with length field not equal to the valid frame size + * (greater than 1,500 but less than 1,536) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | R | 0x0 | rxoutofrangetype + * + */ +/* + * Field : rxoutofrangetype - cnt + * + * Number of frames received with length field not equal to the valid frame size + * (greater than 1,500 but less than 1,536) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */ +#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */ +#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */ +#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value. */ +#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value. */ +#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */ +#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXOUTOFRANGETYPE. + */ +struct ALT_EMAC_GMAC_RXOUTOFRANGETYPE_s +{ + const uint32_t cnt : 32; /* rxoutofrangetype */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXOUTOFRANGETYPE. */ +typedef volatile struct ALT_EMAC_GMAC_RXOUTOFRANGETYPE_s ALT_EMAC_GMAC_RXOUTOFRANGETYPE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_OFST 0x1cc +/* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register. */ +#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOUTOFRANGETYPE_OFST)) + +/* + * Register : Register 116 (rxpauseframes Register) - rxpauseframes + * + * Number of good and valid PAUSE frames received + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | rxpauseframes + * + */ +/* + * Field : rxpauseframes - cnt + * + * Number of good and valid PAUSE frames received + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXPAUSEFRMS. + */ +struct ALT_EMAC_GMAC_RXPAUSEFRMS_s +{ + const uint32_t cnt : 32; /* rxpauseframes */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXPAUSEFRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXPAUSEFRMS_s ALT_EMAC_GMAC_RXPAUSEFRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXPAUSEFRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXPAUSEFRMS_OFST 0x1d0 +/* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register. */ +#define ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXPAUSEFRMS_OFST)) + +/* + * Register : Register 117 (rxfifooverflow Register) - rxfifooverflow + * + * Number of missed received frames due to FIFO overflow + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | rxfifooverflow + * + */ +/* + * Field : rxfifooverflow - cnt + * + * Number of missed received frames due to FIFO overflow + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */ +#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */ +#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */ +#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value. */ +#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value. */ +#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */ +#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXFIFOOVF_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXFIFOOVF. + */ +struct ALT_EMAC_GMAC_RXFIFOOVF_s +{ + const uint32_t cnt : 32; /* rxfifooverflow */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXFIFOOVF. */ +typedef volatile struct ALT_EMAC_GMAC_RXFIFOOVF_s ALT_EMAC_GMAC_RXFIFOOVF_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXFIFOOVF register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXFIFOOVF_OFST 0x1d4 +/* The address of the ALT_EMAC_GMAC_RXFIFOOVF register. */ +#define ALT_EMAC_GMAC_RXFIFOOVF_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXFIFOOVF_OFST)) + +/* + * Register : Register 118 (rxvlanframes_gb Register) - rxvlanframes_gb + * + * Number of good and bad VLAN frames received + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | R | 0x0 | rxvlanframes_gb + * + */ +/* + * Field : rxvlanframes_gb - cnt + * + * Number of good and bad VLAN frames received + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value. */ +#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */ +#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXVLANFRMS_GB. + */ +struct ALT_EMAC_GMAC_RXVLANFRMS_GB_s +{ + const uint32_t cnt : 32; /* rxvlanframes_gb */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXVLANFRMS_GB. */ +typedef volatile struct ALT_EMAC_GMAC_RXVLANFRMS_GB_s ALT_EMAC_GMAC_RXVLANFRMS_GB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXVLANFRMS_GB register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXVLANFRMS_GB_OFST 0x1d8 +/* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register. */ +#define ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXVLANFRMS_GB_OFST)) + +/* + * Register : Register 119 (rxwatchdogerror Register) - rxwatchdogerror + * + * Number of frames received with error due to watchdog timeout error (frames with + * a data load larger than 2,048 bytes) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | R | 0x0 | rxwatchdogerror + * + */ +/* + * Field : rxwatchdogerror - cnt + * + * Number of frames received with error due to watchdog timeout error (frames with + * a data load larger than 2,048 bytes) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXWDERROR_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXWDERROR_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXWDERROR_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXWDERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXWDERROR_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXWDERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXWDERROR_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXWDERROR_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXWDERROR_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXWDERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXWDERROR_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXWDERROR_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXWDERROR. + */ +struct ALT_EMAC_GMAC_RXWDERROR_s +{ + const uint32_t cnt : 32; /* rxwatchdogerror */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXWDERROR. */ +typedef volatile struct ALT_EMAC_GMAC_RXWDERROR_s ALT_EMAC_GMAC_RXWDERROR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXWDERROR register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXWDERROR_OFST 0x1dc +/* The address of the ALT_EMAC_GMAC_RXWDERROR register. */ +#define ALT_EMAC_GMAC_RXWDERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXWDERROR_OFST)) + +/* + * Register : Register 120 (rxrcverror Register) - rxrcverror + * + * Number of frames received with Receive error or Frame Extension error on the + * GMII or MII interface. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | rxrcverror + * + */ +/* + * Field : rxrcverror - cnt + * + * Number of frames received with Receive error or Frame Extension error on the + * GMII or MII interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXRCVERROR_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXRCVERROR_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXRCVERROR_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXRCVERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXRCVERROR_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXRCVERROR_CNT register field value. */ +#define ALT_EMAC_GMAC_RXRCVERROR_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */ +#define ALT_EMAC_GMAC_RXRCVERROR_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXRCVERROR_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXRCVERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXRCVERROR_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXRCVERROR_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXRCVERROR. + */ +struct ALT_EMAC_GMAC_RXRCVERROR_s +{ + const uint32_t cnt : 32; /* rxrcverror */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXRCVERROR. */ +typedef volatile struct ALT_EMAC_GMAC_RXRCVERROR_s ALT_EMAC_GMAC_RXRCVERROR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXRCVERROR register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXRCVERROR_OFST 0x1e0 +/* The address of the ALT_EMAC_GMAC_RXRCVERROR register. */ +#define ALT_EMAC_GMAC_RXRCVERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXRCVERROR_OFST)) + +/* + * Register : Register 121 (rxctrlframes_g Register) - rxctrlframes_g + * + * Number of received good control frames. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | rxctrlframes_g + * + */ +/* + * Field : rxctrlframes_g - cnt + * + * Number of received good control frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value. */ +#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */ +#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXCTLFRMS_G. + */ +struct ALT_EMAC_GMAC_RXCTLFRMS_G_s +{ + const uint32_t cnt : 32; /* rxctrlframes_g */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXCTLFRMS_G. */ +typedef volatile struct ALT_EMAC_GMAC_RXCTLFRMS_G_s ALT_EMAC_GMAC_RXCTLFRMS_G_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXCTLFRMS_G register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXCTLFRMS_G_OFST 0x1e4 +/* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register. */ +#define ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXCTLFRMS_G_OFST)) + +/* + * Register : Register 128 (MMC Receive Checksum Offload Interrupt Mask Register) - MMC_IPC_Receive_Interrupt_Mask + * + * This register maintains the mask for the interrupt generated from the receive + * IPC statistic + * + * counters. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------------------------------- + * [0] | RW | 0x0 | MMC Receive IPV4 Good Frame Counter Interrupt Mask + * [1] | RW | 0x0 | MMC Receive IPV4 Header Error Frame Counter Interrupt Mask + * [2] | RW | 0x0 | MMC Receive IPV4 No Payload Frame Counter Interrupt Mask + * [3] | RW | 0x0 | MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask + * [4] | RW | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask + * [5] | RW | 0x0 | MMC Receive IPV6 Good Frame Counter Interrupt Mask + * [6] | RW | 0x0 | MMC Receive IPV6 Header Error Frame Counter Interrupt Mask + * [7] | RW | 0x0 | MMC Receive IPV6 No Payload Frame Counter Interrupt Mask + * [8] | RW | 0x0 | MMC Receive UDP Good Frame Counter Interrupt Mask + * [9] | RW | 0x0 | MMC Receive UDP Error Frame Counter Interrupt Mask + * [10] | RW | 0x0 | MMC Receive TCP Good Frame Counter Interrupt Mask + * [11] | RW | 0x0 | MMC Receive TCP Error Frame Counter Interrupt Mask + * [12] | RW | 0x0 | MMC Receive ICMP Good Frame Counter Interrupt Mask + * [13] | RW | 0x0 | MMC Receive ICMP Error Frame Counter Interrupt Mask + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | MMC Receive IPV4 Good Octet Counter Interrupt Mask + * [17] | RW | 0x0 | MMC Receive IPV4 Header Error Octet Counter Interrupt Mask + * [18] | RW | 0x0 | MMC Receive IPV4 No Payload Octet Counter Interrupt Mask + * [19] | RW | 0x0 | MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask + * [20] | RW | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask + * [21] | RW | 0x0 | MMC Receive IPV6 Good Octet Counter Interrupt Mask + * [22] | RW | 0x0 | MMC Receive IPV6 Header Error Octet Counter Interrupt Mask + * [23] | RW | 0x0 | MMC Receive IPV6 No Payload Octet Counter Interrupt Mask + * [24] | RW | 0x0 | MMC Receive UDP Good Octet Counter Interrupt Mask + * [25] | RW | 0x0 | MMC Receive UDP Error Octet Counter Interrupt Mask + * [26] | RW | 0x0 | MMC Receive TCP Good Octet Counter Interrupt Mask + * [27] | RW | 0x0 | MMC Receive TCP Error Octet Counter Interrupt Mask + * [28] | RW | 0x0 | MMC Receive ICMP Good Octet Counter Interrupt Mask + * [29] | RW | 0x0 | MMC Receive ICMP Error Octet Counter Interrupt Mask + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MMC Receive IPV4 Good Frame Counter Interrupt Mask - rxipv4gfim + * + * Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - rxipv4herfim + * + * Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - rxipv4nopayfim + * + * Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - rxipv4fragfim + * + * Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - rxipv4udsblfim + * + * Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MMC Receive IPV6 Good Frame Counter Interrupt Mask - rxipv6gfim + * + * Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - rxipv6herfim + * + * Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_MSB 6 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - rxipv6nopayfim + * + * Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MMC Receive UDP Good Frame Counter Interrupt Mask - rxudpgfim + * + * Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MMC Receive UDP Error Frame Counter Interrupt Mask - rxudperfim + * + * Setting this bit masks the interrupt when the rxudp_err_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MMC Receive TCP Good Frame Counter Interrupt Mask - rxtcpgfim + * + * Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half + * of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MMC Receive TCP Error Frame Counter Interrupt Mask - rxtcperfim + * + * Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_MSB 11 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET_MSK 0x00000800 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MMC Receive ICMP Good Frame Counter Interrupt Mask - rxicmpgfim + * + * Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_MSB 12 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET_MSK 0x00001000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_CLR_MSK 0xffffefff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MMC Receive ICMP Error Frame Counter Interrupt Mask - rxicmperfim + * + * Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_MSB 13 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MMC Receive IPV4 Good Octet Counter Interrupt Mask - rxipv4goim + * + * Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - rxipv4heroim + * + * Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_MSB 17 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET_MSK 0x00020000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_CLR_MSK 0xfffdffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - rxipv4nopayoim + * + * Setting this bit masks the interrupt when the rxipv4_nopay_octets counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - rxipv4fragoim + * + * Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - rxipv4udsbloim + * + * Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : MMC Receive IPV6 Good Octet Counter Interrupt Mask - rxipv6goim + * + * Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - rxipv6heroim + * + * Setting this bit masks interrupt when the rxipv6_hdrerr_octets counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_MSB 22 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET_MSK 0x00400000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_CLR_MSK 0xffbfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - rxipv6nopayoim + * + * Setting this bit masks the interrupt when the rxipv6_nopay_octets counter + * reaches half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_MSB 23 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET_MSK 0x00800000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_CLR_MSK 0xff7fffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : MMC Receive UDP Good Octet Counter Interrupt Mask - rxudpgoim + * + * Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MMC Receive UDP Error Octet Counter Interrupt Mask - rxudperoim + * + * Setting this bit masks the interrupt when the rxudp_err_octets counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : MMC Receive TCP Good Octet Counter Interrupt Mask - rxtcpgoim + * + * Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : MMC Receive TCP Error Octet Counter Interrupt Mask - rxtcperoim + * + * Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : MMC Receive ICMP Good Octet Counter Interrupt Mask - rxicmpgoim + * + * Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : MMC Receive ICMP Error Octet Counter Interrupt Mask - rxicmperoim + * + * Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches + * half of the maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET(value) (((value) << 29) & 0x20000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK. + */ +struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s +{ + uint32_t rxipv4gfim : 1; /* MMC Receive IPV4 Good Frame Counter Interrupt Mask */ + uint32_t rxipv4herfim : 1; /* MMC Receive IPV4 Header Error Frame Counter Interrupt Mask */ + uint32_t rxipv4nopayfim : 1; /* MMC Receive IPV4 No Payload Frame Counter Interrupt Mask */ + uint32_t rxipv4fragfim : 1; /* MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask */ + uint32_t rxipv4udsblfim : 1; /* MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask */ + uint32_t rxipv6gfim : 1; /* MMC Receive IPV6 Good Frame Counter Interrupt Mask */ + uint32_t rxipv6herfim : 1; /* MMC Receive IPV6 Header Error Frame Counter Interrupt Mask */ + uint32_t rxipv6nopayfim : 1; /* MMC Receive IPV6 No Payload Frame Counter Interrupt Mask */ + uint32_t rxudpgfim : 1; /* MMC Receive UDP Good Frame Counter Interrupt Mask */ + uint32_t rxudperfim : 1; /* MMC Receive UDP Error Frame Counter Interrupt Mask */ + uint32_t rxtcpgfim : 1; /* MMC Receive TCP Good Frame Counter Interrupt Mask */ + uint32_t rxtcperfim : 1; /* MMC Receive TCP Error Frame Counter Interrupt Mask */ + uint32_t rxicmpgfim : 1; /* MMC Receive ICMP Good Frame Counter Interrupt Mask */ + uint32_t rxicmperfim : 1; /* MMC Receive ICMP Error Frame Counter Interrupt Mask */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t rxipv4goim : 1; /* MMC Receive IPV4 Good Octet Counter Interrupt Mask */ + uint32_t rxipv4heroim : 1; /* MMC Receive IPV4 Header Error Octet Counter Interrupt Mask */ + uint32_t rxipv4nopayoim : 1; /* MMC Receive IPV4 No Payload Octet Counter Interrupt Mask */ + uint32_t rxipv4fragoim : 1; /* MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask */ + uint32_t rxipv4udsbloim : 1; /* MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask */ + uint32_t rxipv6goim : 1; /* MMC Receive IPV6 Good Octet Counter Interrupt Mask */ + uint32_t rxipv6heroim : 1; /* MMC Receive IPV6 Header Error Octet Counter Interrupt Mask */ + uint32_t rxipv6nopayoim : 1; /* MMC Receive IPV6 No Payload Octet Counter Interrupt Mask */ + uint32_t rxudpgoim : 1; /* MMC Receive UDP Good Octet Counter Interrupt Mask */ + uint32_t rxudperoim : 1; /* MMC Receive UDP Error Octet Counter Interrupt Mask */ + uint32_t rxtcpgoim : 1; /* MMC Receive TCP Good Octet Counter Interrupt Mask */ + uint32_t rxtcperoim : 1; /* MMC Receive TCP Error Octet Counter Interrupt Mask */ + uint32_t rxicmpgoim : 1; /* MMC Receive ICMP Good Octet Counter Interrupt Mask */ + uint32_t rxicmperoim : 1; /* MMC Receive ICMP Error Octet Counter Interrupt Mask */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK. */ +typedef volatile struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST 0x200 +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST)) + +/* + * Register : Register 130 (MMC Receive Checksum Offload Interrupt Register) - MMC_IPC_Receive_Interrupt + * + * This register maintains the interrupts generated when receive IPC statistic + * counters reach half their maximum values (0x8000_0000 for 32-bit counter and + * 0x8000 for 16-bit counter), and when they cross their maximum values + * (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter + * Stop Rollover is set, then interrupts are set but the counter remains at all- + * ones. The MMC Receive Checksum Offload Interrupt register is 32-bits wide. When + * the MMC IPC counter that caused the interrupt is read, its corresponding + * interrupt bit is cleared. The counter's least-significant byte lane (bits[7:0]) + * must be read to clear the interrupt bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------------------------------- + * [0] | R | 0x0 | MMC Receive IPV4 Good Frame Counter Interrupt Status + * [1] | R | 0x0 | MMC Receive IPV4 Header Error Frame Counter Interrupt Status + * [2] | R | 0x0 | MMC Receive IPV4 No Payload Frame Counter Interrupt Status + * [3] | R | 0x0 | MMC Receive IPV4 Fragmented Frame Counter Interrupt Status + * [4] | R | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status + * [5] | R | 0x0 | MMC Receive IPV6 Good Frame Counter Interrupt Status + * [6] | R | 0x0 | MMC Receive IPV6 Header Error Frame Counter Interrupt Status + * [7] | R | 0x0 | MMC Receive IPV6 No Payload Frame Counter Interrupt Status + * [8] | R | 0x0 | MMC Receive UDP Good Frame Counter Interrupt Status + * [9] | R | 0x0 | MMC Receive UDP Error Frame Counter Interrupt Status + * [10] | R | 0x0 | MMC Receive TCP Good Frame Counter Interrupt Status + * [11] | R | 0x0 | MMC Receive TCP Error Frame Counter Interrupt Status + * [12] | R | 0x0 | MMC Receive ICMP Good Frame Counter Interrupt Status + * [13] | R | 0x0 | MMC Receive ICMP Error Frame Counter Interrupt Status + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [16] | R | 0x0 | MMC Receive IPV4 Good Octet Counter Interrupt Status + * [17] | R | 0x0 | MMC Receive IPV4 Header Error Octet Counter Interrupt Status + * [18] | R | 0x0 | MMC Receive IPV4 No Payload Octet Counter Interrupt Status + * [19] | R | 0x0 | MMC Receive IPV4 Fragmented Octet Counter Interrupt Status + * [20] | R | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status + * [21] | R | 0x0 | MMC Receive IPV6 Good Octet Counter Interrupt Status + * [22] | R | 0x0 | MMC Receive IPV6 Header Error Octet Counter Interrupt Status + * [23] | R | 0x0 | MMC Receive IPV6 No Payload Octet Counter Interrupt Status + * [24] | R | 0x0 | MMC Receive UDP Good Octet Counter Interrupt Status + * [25] | R | 0x0 | MMC Receive UDP Error Octet Counter Interrupt Status + * [26] | R | 0x0 | MMC Receive TCP Good Octet Counter Interrupt Status + * [27] | R | 0x0 | MMC Receive TCP Error Octet Counter Interrupt Status + * [28] | R | 0x0 | MMC Receive ICMP Good Octet Counter Interrupt Status + * [29] | R | 0x0 | MMC Receive ICMP Error Octet Counter Interrupt Status + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MMC Receive IPV4 Good Frame Counter Interrupt Status - rxipv4gfis + * + * This bit is set when the rxipv4_gd_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : MMC Receive IPV4 Header Error Frame Counter Interrupt Status - rxipv4herfis + * + * This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : MMC Receive IPV4 No Payload Frame Counter Interrupt Status - rxipv4nopayfis + * + * This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - rxipv4fragfis + * + * This bit is set when the rxipv4_frag_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - rxipv4udsblfis + * + * This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : MMC Receive IPV6 Good Frame Counter Interrupt Status - rxipv6gfis + * + * This bit is set when the rxipv6_gd_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : MMC Receive IPV6 Header Error Frame Counter Interrupt Status - rxipv6herfis + * + * This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_MSB 6 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : MMC Receive IPV6 No Payload Frame Counter Interrupt Status - rxipv6nopayfis + * + * This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : MMC Receive UDP Good Frame Counter Interrupt Status - rxudpgfis + * + * This bit is set when the rxudp_gd_frms counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : MMC Receive UDP Error Frame Counter Interrupt Status - rxudperfis + * + * This bit is set when the rxudp_err_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MMC Receive TCP Good Frame Counter Interrupt Status - rxtcpgfis + * + * This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MMC Receive TCP Error Frame Counter Interrupt Status - rxtcperfis + * + * This bit is set when the rxtcp_err_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_MSB 11 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : MMC Receive ICMP Good Frame Counter Interrupt Status - rxicmpgfis + * + * This bit is set when the rxicmp_gd_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_MSB 12 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET_MSK 0x00001000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_CLR_MSK 0xffffefff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MMC Receive ICMP Error Frame Counter Interrupt Status - rxicmperfis + * + * This bit is set when the rxicmp_err_frms counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_MSB 13 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : MMC Receive IPV4 Good Octet Counter Interrupt Status - rxipv4gois + * + * This bit is set when the rxipv4_gd_octets counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : MMC Receive IPV4 Header Error Octet Counter Interrupt Status - rxipv4herois + * + * This bit is set when the rxipv4_hdrerr_octets counter reaches half of the + * maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_MSB 17 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : MMC Receive IPV4 No Payload Octet Counter Interrupt Status - rxipv4nopayois + * + * This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - rxipv4fragois + * + * This bit is set when the rxipv4_frag_octets counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - rxipv4udsblois + * + * This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : MMC Receive IPV6 Good Octet Counter Interrupt Status - rxipv6gois + * + * This bit is set when the rxipv6_gd_octets counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : MMC Receive IPV6 Header Error Octet Counter Interrupt Status - rxipv6herois + * + * This bit is set when the rxipv6_hdrerr_octets counter reaches half of the + * maximum value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_MSB 22 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET_MSK 0x00400000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_CLR_MSK 0xffbfffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : MMC Receive IPV6 No Payload Octet Counter Interrupt Status - rxipv6nopayois + * + * This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_MSB 23 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET_MSK 0x00800000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_CLR_MSK 0xff7fffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : MMC Receive UDP Good Octet Counter Interrupt Status - rxudpgois + * + * This bit is set when the rxudp_gd_octets counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : MMC Receive UDP Error Octet Counter Interrupt Status - rxudperois + * + * This bit is set when the rxudp_err_octets counter reaches half the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : MMC Receive TCP Good Octet Counter Interrupt Status - rxtcpgois + * + * This bit is set when the rxtcp_gd_octets counter reaches half the maximum value + * or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : MMC Receive TCP Error Octet Counter Interrupt Status - rxtcperois + * + * This bit is set when the rxtcp_err_octets counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : MMC Receive ICMP Good Octet Counter Interrupt Status - rxicmpgois + * + * This bit is set when the rxicmp_gd_octets counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : MMC Receive ICMP Error Octet Counter Interrupt Status - rxicmperois + * + * This bit is set when the rxicmp_err_octets counter reaches half of the maximum + * value or the maximum value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_NOINT | 0x0 | counter < half max + * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_INTERR | 0x1 | counter >= half max or max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS + * + * counter < half max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_NOINT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS + * + * counter >= half max or max + */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_INTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS field value from a register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET(value) (((value) << 29) & 0x20000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT. + */ +struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s +{ + const uint32_t rxipv4gfis : 1; /* MMC Receive IPV4 Good Frame Counter Interrupt Status */ + const uint32_t rxipv4herfis : 1; /* MMC Receive IPV4 Header Error Frame Counter Interrupt Status */ + const uint32_t rxipv4nopayfis : 1; /* MMC Receive IPV4 No Payload Frame Counter Interrupt Status */ + const uint32_t rxipv4fragfis : 1; /* MMC Receive IPV4 Fragmented Frame Counter Interrupt Status */ + const uint32_t rxipv4udsblfis : 1; /* MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status */ + const uint32_t rxipv6gfis : 1; /* MMC Receive IPV6 Good Frame Counter Interrupt Status */ + const uint32_t rxipv6herfis : 1; /* MMC Receive IPV6 Header Error Frame Counter Interrupt Status */ + const uint32_t rxipv6nopayfis : 1; /* MMC Receive IPV6 No Payload Frame Counter Interrupt Status */ + const uint32_t rxudpgfis : 1; /* MMC Receive UDP Good Frame Counter Interrupt Status */ + const uint32_t rxudperfis : 1; /* MMC Receive UDP Error Frame Counter Interrupt Status */ + const uint32_t rxtcpgfis : 1; /* MMC Receive TCP Good Frame Counter Interrupt Status */ + const uint32_t rxtcperfis : 1; /* MMC Receive TCP Error Frame Counter Interrupt Status */ + const uint32_t rxicmpgfis : 1; /* MMC Receive ICMP Good Frame Counter Interrupt Status */ + const uint32_t rxicmperfis : 1; /* MMC Receive ICMP Error Frame Counter Interrupt Status */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t rxipv4gois : 1; /* MMC Receive IPV4 Good Octet Counter Interrupt Status */ + const uint32_t rxipv4herois : 1; /* MMC Receive IPV4 Header Error Octet Counter Interrupt Status */ + const uint32_t rxipv4nopayois : 1; /* MMC Receive IPV4 No Payload Octet Counter Interrupt Status */ + const uint32_t rxipv4fragois : 1; /* MMC Receive IPV4 Fragmented Octet Counter Interrupt Status */ + const uint32_t rxipv4udsblois : 1; /* MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status */ + const uint32_t rxipv6gois : 1; /* MMC Receive IPV6 Good Octet Counter Interrupt Status */ + const uint32_t rxipv6herois : 1; /* MMC Receive IPV6 Header Error Octet Counter Interrupt Status */ + const uint32_t rxipv6nopayois : 1; /* MMC Receive IPV6 No Payload Octet Counter Interrupt Status */ + const uint32_t rxudpgois : 1; /* MMC Receive UDP Good Octet Counter Interrupt Status */ + const uint32_t rxudperois : 1; /* MMC Receive UDP Error Octet Counter Interrupt Status */ + const uint32_t rxtcpgois : 1; /* MMC Receive TCP Good Octet Counter Interrupt Status */ + const uint32_t rxtcperois : 1; /* MMC Receive TCP Error Octet Counter Interrupt Status */ + const uint32_t rxicmpgois : 1; /* MMC Receive ICMP Good Octet Counter Interrupt Status */ + const uint32_t rxicmperois : 1; /* MMC Receive ICMP Error Octet Counter Interrupt Status */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT. */ +typedef volatile struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s ALT_EMAC_GMAC_MMC_IPC_RX_INT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST 0x208 +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register. */ +#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST)) + +/* + * Register : Register 132 (rxipv4_gd_frms Register) - rxipv4_gd_frms + * + * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | rxipv4_gd_frms + * + */ +/* + * Field : rxipv4_gd_frms - cnt + * + * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_GD_FRMS. + */ +struct ALT_EMAC_GMAC_RXIPV4_GD_FRMS_s +{ + const uint32_t cnt : 32; /* rxipv4_gd_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_GD_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV4_GD_FRMS_s ALT_EMAC_GMAC_RXIPV4_GD_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_OFST 0x210 +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_GD_FRMS_OFST)) + +/* + * Register : Register 133 (rxipv4_hdrerr_frms Register) - rxipv4_hdrerr_frms + * + * Number of IPv4 datagrams received with header (checksum, length, or version + * mismatch) errors + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [31:0] | R | 0x0 | rxipv4_hdrerr_frms + * + */ +/* + * Field : rxipv4_hdrerr_frms - cnt + * + * Number of IPv4 datagrams received with header (checksum, length, or version + * mismatch) errors + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS. + */ +struct ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_s +{ + const uint32_t cnt : 32; /* rxipv4_hdrerr_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_s ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_OFST 0x214 +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_OFST)) + +/* + * Register : Register 134 (rxipv4_nopay_frms Register) - rxipv4_nopay_frms + * + * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP + * payload processed by the Checksum engine + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [31:0] | R | 0x0 | rxipv4_nopay_frms + * + */ +/* + * Field : rxipv4_nopay_frms - cnt + * + * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP + * payload processed by the Checksum engine + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS. + */ +struct ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_s +{ + const uint32_t cnt : 32; /* rxipv4_nopay_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_s ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_OFST 0x218 +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_OFST)) + +/* + * Register : Register 135 (rxipv4_frag_frms Register) - rxipv4_frag_frms + * + * Number of good IPv4 datagrams with fragmentation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | R | 0x0 | rxipv4_frag_frms + * + */ +/* + * Field : rxipv4_frag_frms - cnt + * + * Number of good IPv4 datagrams with fragmentation + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS. + */ +struct ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_s +{ + const uint32_t cnt : 32; /* rxipv4_frag_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_s ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_OFST 0x21c +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_OFST)) + +/* + * Register : Register 136 (rxipv4_udsbl_frms Register) - rxipv4_udsbl_frms + * + * Number of good IPv4 datagrams received that had a UDP payload with checksum + * disabled + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [31:0] | R | 0x0 | rxipv4_udsbl_frms + * + */ +/* + * Field : rxipv4_udsbl_frms - cnt + * + * Number of good IPv4 datagrams received that had a UDP payload with checksum + * disabled + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS. + */ +struct ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_s +{ + const uint32_t cnt : 32; /* rxipv4_udsbl_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_s ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_OFST 0x220 +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_OFST)) + +/* + * Register : Register 137 (rxipv6_gd_frms Register) - rxipv6_gd_frms + * + * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | rxipv6_gd_frms + * + */ +/* + * Field : rxipv6_gd_frms - cnt + * + * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_GD_FRMS. + */ +struct ALT_EMAC_GMAC_RXIPV6_GD_FRMS_s +{ + const uint32_t cnt : 32; /* rxipv6_gd_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_GD_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV6_GD_FRMS_s ALT_EMAC_GMAC_RXIPV6_GD_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_OFST 0x224 +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_GD_FRMS_OFST)) + +/* + * Register : Register 138 (rxipv6_hdrerr_frms Register) - rxipv6_hdrerr_frms + * + * Number of IPv6 datagrams received with header errors (length or version + * mismatch) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [31:0] | R | 0x0 | rxipv6_hdrerr_frms + * + */ +/* + * Field : rxipv6_hdrerr_frms - cnt + * + * Number of IPv6 datagrams received with header errors (length or version + * mismatch) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS. + */ +struct ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_s +{ + const uint32_t cnt : 32; /* rxipv6_hdrerr_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_s ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_OFST 0x228 +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_OFST)) + +/* + * Register : Register 139 (rxipv6_nopay_frms) - rxipv6_nopay_frms + * + * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP + * payload. This includes all IPv6 datagrams with fragmentation or security + * extension headers + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [31:0] | R | 0x0 | rxipv6_nopay_frms + * + */ +/* + * Field : rxipv6_nopay_frms - cnt + * + * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP + * payload. This includes all IPv6 datagrams with fragmentation or security + * extension headers + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS. + */ +struct ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_s +{ + const uint32_t cnt : 32; /* rxipv6_nopay_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_s ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_OFST 0x22c +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_OFST)) + +/* + * Register : Register 140 (rxudp_gd_frms Register) - rxudp_gd_frms + * + * Number of good IP datagrams with a good UDP payload. This counter is not updated + * when the counter is incremented + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | rxudp_gd_frms + * + */ +/* + * Field : rxudp_gd_frms - cnt + * + * Number of good IP datagrams with a good UDP payload. This counter is not updated + * when the counter is incremented + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXUDP_GD_FRMS. + */ +struct ALT_EMAC_GMAC_RXUDP_GD_FRMS_s +{ + const uint32_t cnt : 32; /* rxudp_gd_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_GD_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXUDP_GD_FRMS_s ALT_EMAC_GMAC_RXUDP_GD_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_OFST 0x230 +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register. */ +#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_GD_FRMS_OFST)) + +/* + * Register : Register 141 (rxudp_err_frms Register) - rxudp_err_frms + * + * Number of good IP datagrams whose UDP payload has a checksum error + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | rxudp_err_frms + * + */ +/* + * Field : rxudp_err_frms - cnt + * + * Number of good IP datagrams whose UDP payload has a checksum error + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXUDP_ERR_FRMS. + */ +struct ALT_EMAC_GMAC_RXUDP_ERR_FRMS_s +{ + const uint32_t cnt : 32; /* rxudp_err_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_ERR_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXUDP_ERR_FRMS_s ALT_EMAC_GMAC_RXUDP_ERR_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_OFST 0x234 +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_ERR_FRMS_OFST)) + +/* + * Register : Register 142 (rxtcp_gd_frms Register) - rxtcp_gd_frms + * + * Number of good IP datagrams with a good TCP payload + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [31:0] | R | 0x0 | rxtcp_gd_frms Register + * + */ +/* + * Field : rxtcp_gd_frms Register - cnt + * + * Number of good IP datagrams with a good TCP payload + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXTCP_GD_FRMS. + */ +struct ALT_EMAC_GMAC_RXTCP_GD_FRMS_s +{ + const uint32_t cnt : 32; /* rxtcp_gd_frms Register */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_GD_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXTCP_GD_FRMS_s ALT_EMAC_GMAC_RXTCP_GD_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_OFST 0x238 +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register. */ +#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_GD_FRMS_OFST)) + +/* + * Register : Register 143 (rxtcp_err_frms Register) - rxtcp_err_frms + * + * Number of good IP datagrams whose TCP payload has a checksum error + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | rxtcp_err_frms + * + */ +/* + * Field : rxtcp_err_frms - cnt + * + * Number of good IP datagrams whose TCP payload has a checksum error + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXTCP_ERR_FRMS. + */ +struct ALT_EMAC_GMAC_RXTCP_ERR_FRMS_s +{ + const uint32_t cnt : 32; /* rxtcp_err_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_ERR_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXTCP_ERR_FRMS_s ALT_EMAC_GMAC_RXTCP_ERR_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_OFST 0x23c +/* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register. */ +#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_ERR_FRMS_OFST)) + +/* + * Register : Register 144 (rxicmp_gd_frms Register) - rxicmp_gd_frms + * + * Number of good IP datagrams with a good ICMP payload + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | R | 0x0 | rxicmp_gd_frms + * + */ +/* + * Field : rxicmp_gd_frms - cnt + * + * Number of good IP datagrams with a good ICMP payload + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXICMP_GD_FRMS. + */ +struct ALT_EMAC_GMAC_RXICMP_GD_FRMS_s +{ + const uint32_t cnt : 32; /* rxicmp_gd_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_GD_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXICMP_GD_FRMS_s ALT_EMAC_GMAC_RXICMP_GD_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_OFST 0x240 +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register. */ +#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_GD_FRMS_OFST)) + +/* + * Register : Register 145 (rxicmp_err_frms Register) - rxicmp_err_frms + * + * Number of good IP datagrams whose ICMP payload has a checksum error + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | R | 0x0 | rxicmp_err_frms + * + */ +/* + * Field : rxicmp_err_frms - cnt + * + * Number of good IP datagrams whose ICMP payload has a checksum error + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXICMP_ERR_FRMS. + */ +struct ALT_EMAC_GMAC_RXICMP_ERR_FRMS_s +{ + const uint32_t cnt : 32; /* rxicmp_err_frms */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_ERR_FRMS. */ +typedef volatile struct ALT_EMAC_GMAC_RXICMP_ERR_FRMS_s ALT_EMAC_GMAC_RXICMP_ERR_FRMS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_OFST 0x244 +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_ERR_FRMS_OFST)) + +/* + * Register : Register 148 (rxipv4_gd_octets Register) - rxipv4_gd_octets + * + * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP + * data + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | R | 0x0 | rxipv4_gd_octets + * + */ +/* + * Field : rxipv4_gd_octets - cnt + * + * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP + * data + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_GD_OCTETS. + */ +struct ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_s +{ + const uint32_t cnt : 32; /* rxipv4_gd_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_GD_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_s ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_OFST 0x250 +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register. */ +#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_OFST)) + +/* + * Register : Register 149 (rxipv4_hdrerr_octets) - rxipv4_hdrerr_octets + * + * Number of bytes received in IPv4 datagrams with header errors (checksum, length, + * version mismatch). The value in the Length field of IPv4 header is used to + * update this counter + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | R | 0x0 | rxipv4_hdrerr_octets Register + * + */ +/* + * Field : rxipv4_hdrerr_octets Register - cnt + * + * Number of bytes received in IPv4 datagrams with header errors (checksum, length, + * version mismatch). The value in the Length field of IPv4 header is used to + * update this counter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS. + */ +struct ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_s +{ + const uint32_t cnt : 32; /* rxipv4_hdrerr_octets Register */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_s ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_OFST 0x254 +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register. */ +#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_OFST)) + +/* + * Register : Register 150 (rxipv4_nopay_octets Register) - rxipv4_nopay_octets + * + * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP + * payload. The value in the IPv4 headers Length field is used to update this + * counter + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | rxipv4_nopay_octets + * + */ +/* + * Field : rxipv4_nopay_octets - cnt + * + * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP + * payload. The value in the IPv4 headers Length field is used to update this + * counter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS. + */ +struct ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_s +{ + const uint32_t cnt : 32; /* rxipv4_nopay_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_s ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_OFST 0x258 +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register. */ +#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_OFST)) + +/* + * Register : Register 151 (rxipv4_frag_octets Register) - rxipv4_frag_octets + * + * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 + * headers Length field is used to update this counter + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [31:0] | R | 0x0 | rxipv4_frag_octets + * + */ +/* + * Field : rxipv4_frag_octets - cnt + * + * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 + * headers Length field is used to update this counter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS. + */ +struct ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_s +{ + const uint32_t cnt : 32; /* rxipv4_frag_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_s ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_OFST 0x25c +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register. */ +#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_OFST)) + +/* + * Register : Register 152 (rxipv4_udsbl_octets Register) - rxipv4_udsbl_octets + * + * Number of bytes received in a UDP segment that had the UDP checksum disabled. + * This counter does not count IP Header bytes + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | rxipv4_udsbl_octets + * + */ +/* + * Field : rxipv4_udsbl_octets - cnt + * + * Number of bytes received in a UDP segment that had the UDP checksum disabled. + * This counter does not count IP Header bytes + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS. + */ +struct ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_s +{ + const uint32_t cnt : 32; /* rxipv4_udsbl_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_s ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_OFST 0x260 +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register. */ +#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_OFST)) + +/* + * Register : Register 153 (rxipv6_gd_octets Register) - rxipv6_gd_octets + * + * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 + * data + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | R | 0x0 | rxipv6_gd_octets + * + */ +/* + * Field : rxipv6_gd_octets - cnt + * + * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 + * data + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_GD_OCTETS. + */ +struct ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_s +{ + const uint32_t cnt : 32; /* rxipv6_gd_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_GD_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_s ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_OFST 0x264 +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register. */ +#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_OFST)) + +/* + * Register : Register 154 (rxipv6_hdrerr_octets Register) - rxipv6_hdrerr_octets + * + * Number of bytes received in IPv6 datagrams with header errors (length, version + * mismatch). The value in the IPv6 headers Length field is used to update this + * counter + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | R | 0x0 | rxipv6_hdrerr_octets + * + */ +/* + * Field : rxipv6_hdrerr_octets - cnt + * + * Number of bytes received in IPv6 datagrams with header errors (length, version + * mismatch). The value in the IPv6 headers Length field is used to update this + * counter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS. + */ +struct ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_s +{ + const uint32_t cnt : 32; /* rxipv6_hdrerr_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_s ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_OFST 0x268 +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register. */ +#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_OFST)) + +/* + * Register : Register 155 (rxipv6_nopay_octets Register) - rxipv6_nopay_octets + * + * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP + * payload. The value in the IPv6 headers Length field is used to update this + * counter + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | R | 0x0 | rxipv6_nopay_octets + * + */ +/* + * Field : rxipv6_nopay_octets - cnt + * + * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP + * payload. The value in the IPv6 headers Length field is used to update this + * counter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS. + */ +struct ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_s +{ + const uint32_t cnt : 32; /* rxipv6_nopay_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_s ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_OFST 0x26c +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register. */ +#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_OFST)) + +/* + * Register : Register 156 (rxudp_gd_octets Register) - rxudp_gd_octets + * + * Number of bytes received in a good UDP segment. This counter does not count IP + * header bytes + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | R | 0x0 | rxudp_gd_octets + * + */ +/* + * Field : rxudp_gd_octets - cnt + * + * Number of bytes received in a good UDP segment. This counter does not count IP + * header bytes + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXUDP_GD_OCTETS. + */ +struct ALT_EMAC_GMAC_RXUDP_GD_OCTETS_s +{ + const uint32_t cnt : 32; /* rxudp_gd_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_GD_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXUDP_GD_OCTETS_s ALT_EMAC_GMAC_RXUDP_GD_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_OFST 0x270 +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register. */ +#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_GD_OCTETS_OFST)) + +/* + * Register : Register 157 (rxudp_err_octets Register) - rxudp_err_octets + * + * Number of bytes received in a UDP segment that had checksum errors + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | R | 0x0 | rxudp_err_octets + * + */ +/* + * Field : rxudp_err_octets - cnt + * + * Number of bytes received in a UDP segment that had checksum errors + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXUDP_ERR_OCTETS. + */ +struct ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_s +{ + const uint32_t cnt : 32; /* rxudp_err_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_ERR_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_s ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_OFST 0x274 +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register. */ +#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_OFST)) + +/* + * Register : Register 158 (rxtcp_gd_octets Register) - rxtcp_gd_octets + * + * Number of bytes received in a good TCP segment + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | R | 0x0 | rxtcp_gd_octets + * + */ +/* + * Field : rxtcp_gd_octets - cnt + * + * Number of bytes received in a good TCP segment + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXTCP_GD_OCTETS. + */ +struct ALT_EMAC_GMAC_RXTCP_GD_OCTETS_s +{ + const uint32_t cnt : 32; /* rxtcp_gd_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_GD_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXTCP_GD_OCTETS_s ALT_EMAC_GMAC_RXTCP_GD_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_OFST 0x278 +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register. */ +#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_GD_OCTETS_OFST)) + +/* + * Register : Register 159 (rxtcp_err_octets Register) - rxtcperroctets + * + * Number of bytes received in a TCP segment with checksum errors + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | R | 0x0 | rxtcp_err_octets + * + */ +/* + * Field : rxtcp_err_octets - rxtcp_err_octets + * + * Number of bytes received in a TCP segment with checksum errors + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */ +#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */ +#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */ +#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value. */ +#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value. */ +#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */ +#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS field value from a register. */ +#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXTCPERROCTETS. + */ +struct ALT_EMAC_GMAC_RXTCPERROCTETS_s +{ + const uint32_t rxtcp_err_octets : 32; /* rxtcp_err_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXTCPERROCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXTCPERROCTETS_s ALT_EMAC_GMAC_RXTCPERROCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXTCPERROCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXTCPERROCTETS_OFST 0x27c +/* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register. */ +#define ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCPERROCTETS_OFST)) + +/* + * Register : Register 160 (rxicmp_gd_octets Register) - rxicmp_gd_octets + * + * Number of bytes received in a good ICMP segment + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | R | 0x0 | rxicmp_gd_octets + * + */ +/* + * Field : rxicmp_gd_octets - cnt + * + * Number of bytes received in a good ICMP segment + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXICMP_GD_OCTETS. + */ +struct ALT_EMAC_GMAC_RXICMP_GD_OCTETS_s +{ + const uint32_t cnt : 32; /* rxicmp_gd_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_GD_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXICMP_GD_OCTETS_s ALT_EMAC_GMAC_RXICMP_GD_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_OFST 0x280 +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register. */ +#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_GD_OCTETS_OFST)) + +/* + * Register : Register 161 (rxicmp_err_octets Register) - rxicmp_err_octets + * + * Number of bytes received in an ICMP segment with checksum errors + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [31:0] | R | 0x0 | rxicmp_err_octets + * + */ +/* + * Field : rxicmp_err_octets - cnt + * + * Number of bytes received in an ICMP segment with checksum errors + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT field value from a register. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_RXICMP_ERR_OCTETS. + */ +struct ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_s +{ + const uint32_t cnt : 32; /* rxicmp_err_octets */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_ERR_OCTETS. */ +typedef volatile struct ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_s ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_OFST 0x284 +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register. */ +#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_OFST)) + +/* + * Register : Register 256 (Layer 3 and Layer 4 Control Register 0) - L3_L4_Control0 + * + * This register controls the operations of the filter 0 of Layer 3 and Layer 4. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | Layer 3 Protocol Enable + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | Layer 3 IP SA Match Enable + * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable + * [4] | RW | 0x0 | Layer 3 IP DA Match Enable + * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable + * [10:6] | RW | 0x0 | Layer 3 IP SA Higher Bits Match + * [15:11] | RW | 0x0 | Layer 3 IP DA Higher Bits Match + * [16] | RW | 0x0 | Layer 4 Protocol Enable + * [17] | ??? | 0x0 | *UNDEFINED* + * [18] | RW | 0x0 | Layer 4 Source Port Match Enable + * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable + * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable + * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable + * [31:22] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Layer 3 Protocol Enable - l3pen0 + * + * When set, this bit indicates that the Layer 3 IP Source or Destination Address + * matching is enabled for the IPv6 frames. When reset, this bit indicates that the + * Layer 3 IP Source or Destination Address matching is enabled for the IPv4 + * frames. + * + * The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Layer 3 IP SA Match Enable - l3sam0 + * + * When set, this bit indicates that the Layer 3 IP Source Address field is enabled + * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field + * for matching. + * + * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 4 + * (L3DAM0) because either IPv6 SA or DA can be checked for filtering. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Layer 3 IP SA Inverse Match Enable - l3saim0 + * + * When set, this bit indicates that the Layer 3 IP Source Address field is enabled + * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source + * Address field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Layer 3 IP DA Match Enable - l3dam0 + * + * When set, this bit indicates that Layer 3 IP Destination Address field is + * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination + * Address field for matching. + * + * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 + * (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Layer 3 IP DA Inverse Match Enable - l3daim0 + * + * When set, this bit indicates that the Layer 3 IP Destination Address field is + * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP + * Destination Address field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Layer 3 IP SA Higher Bits Match - l3hsbm0 + * + * IPv4 Frames: + * + * This field contains the number of lower bits of IP Source Address that are + * masked for matching in the IPv4 frames. The following list describes the values + * of this field: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 31: All bits except MSb are masked. + * + * IPv6 Frames: + * + * This field contains Bits [4:0] of the field that indicates the number of higher + * bits of IP Source or Destination Address matched in the IPv6 frames. + * + * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET_MSK 0x000007c0 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_CLR_MSK 0xfffff83f +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_GET(value) (((value) & 0x000007c0) >> 6) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET(value) (((value) << 6) & 0x000007c0) + +/* + * Field : Layer 3 IP DA Higher Bits Match - l3hdbm0 + * + * IPv4 Frames: + * + * This field contains the number of higher bits of IP Destination Address that are + * matched in the IPv4 frames. The following list describes the values of this + * field: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 31: All bits except MSb are masked. + * + * IPv6 Frames: + * + * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate + * the number of lower bits of IP Source or Destination Address that are masked in + * the IPv6 frames. The following list describes the concatenated values of the + * L3HDBM0[1:0] and L3HSBM0 bits: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 127: All bits except MSb are masked. + * + * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET_MSK 0x0000f800 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_CLR_MSK 0xffff07ff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_GET(value) (((value) & 0x0000f800) >> 11) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET(value) (((value) << 11) & 0x0000f800) + +/* + * Field : Layer 4 Protocol Enable - l4pen0 + * + * When set, this bit indicates that the Source and Destination Port number fields + * for UDP frames are used for matching. When reset, this bit indicates that the + * Source and Destination Port number fields for TCP frames are used for matching. + * + * The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Layer 4 Source Port Match Enable - l4spm0 + * + * When set, this bit indicates that the Layer 4 Source Port number field is + * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number + * field for matching. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Layer 4 Source Port Inverse Match Enable - l4spim0 + * + * When set, this bit indicates that the Layer 4 Source Port number field is + * enabled for inverse matching. When reset, this bit indicates that the Layer 4 + * Source Port number field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Layer 4 Destination Port Match Enable - l4dpm0 + * + * When set, this bit indicates that the Layer 4 Destination Port number field is + * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port + * number field for matching. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim0 + * + * When set, this bit indicates that the Layer 4 Destination Port number field is + * enabled for inverse matching. When reset, this bit indicates that the Layer 4 + * Destination Port number field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET(value) (((value) << 21) & 0x00200000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL0. + */ +struct ALT_EMAC_GMAC_L3_L4_CTL0_s +{ + uint32_t l3pen0 : 1; /* Layer 3 Protocol Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t l3sam0 : 1; /* Layer 3 IP SA Match Enable */ + uint32_t l3saim0 : 1; /* Layer 3 IP SA Inverse Match Enable */ + uint32_t l3dam0 : 1; /* Layer 3 IP DA Match Enable */ + uint32_t l3daim0 : 1; /* Layer 3 IP DA Inverse Match Enable */ + uint32_t l3hsbm0 : 5; /* Layer 3 IP SA Higher Bits Match */ + uint32_t l3hdbm0 : 5; /* Layer 3 IP DA Higher Bits Match */ + uint32_t l4pen0 : 1; /* Layer 4 Protocol Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t l4spm0 : 1; /* Layer 4 Source Port Match Enable */ + uint32_t l4spim0 : 1; /* Layer 4 Source Port Inverse Match Enable */ + uint32_t l4dpm0 : 1; /* Layer 4 Destination Port Match Enable */ + uint32_t l4dpim0 : 1; /* Layer 4 Destination Port Inverse Match Enable */ + uint32_t : 10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL0. */ +typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL0_s ALT_EMAC_GMAC_L3_L4_CTL0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL0 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_OFST 0x400 +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL0_OFST)) + +/* + * Register : Register 257 (Layer 4 Address Register 0) - Layer4_Address0 + * + * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the + * Rx clock domains, then the synchronization is triggered only when Bits[31:24] + * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and + * Layer 4 Address Registers are written. For proper synchronization updates, you + * should perform the consecutive writes to the same Layer 3 and Layer 4 Address + * Registers after at least four clock cycles delay of the destination clock. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field + * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field + * + */ +/* + * Field : Layer 4 Source Port Number Field - l4sp0 + * + * Layer 4 Source Port Number Field + * + * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer + * 3 and Layer 4 Control Register 0), this field contains the value to be matched + * with the TCP Source Port Number field in the IPv4 or IPv6 frames. + * + * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 0), this field contains the value to be matched with + * the UDP Source Port Number field in the IPv4 or IPv6 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 field value from a register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Layer 4 Destination Port Number Field - l4dp0 + * + * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer + * 3 and Layer 4 Control Register 0), this field contains the value to be matched + * with the TCP Destination Port Number field in the IPv4 or IPv6 frames. + * + * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 0), this field contains the value to be matched with + * the UDP Destination Port Number field in the IPv4 or IPv6 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_CLR_MSK 0x0000ffff +/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 field value from a register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR0. + */ +struct ALT_EMAC_GMAC_LYR4_ADDR0_s +{ + uint32_t l4sp0 : 16; /* Layer 4 Source Port Number Field */ + uint32_t l4dp0 : 16; /* Layer 4 Destination Port Number Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR0. */ +typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR0_s ALT_EMAC_GMAC_LYR4_ADDR0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR0 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_OFST 0x404 +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR0_OFST)) + +/* + * Register : Register 260 (Layer 3 Address 0 Register 0) - Layer3_Addr0_Reg0 + * + * For IPv4 frames, the Layer 3 Address 0 Register 0 contains the 32-bit IP Source + * Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source + * Address or Destination Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 0 Field + * + */ +/* + * Field : Layer 3 Address 0 Field - l3a00 + * + * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 0), this field contains the value to be matched with + * Bits[31:0] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 0), this field contains the value to be matched with + * Bits [31:0] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 + * and Layer 4 Control Register 0), this field contains the value to be matched + * with the IP Source Address field in the IPv4 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG0. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s +{ + uint32_t l3a00 : 32; /* Layer 3 Address 0 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG0. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s ALT_EMAC_GMAC_LYR3_ADDR0_REG0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST 0x410 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST)) + +/* + * Register : Register 261 (Layer 3 Address 1 Register 0) - Layer3_Addr1_Reg0 + * + * For IPv4 frames, the Layer 3 Address 1 Register 0 contains the 32-bit IP + * Destination Address field. For IPv6 frames, it contains Bits[63:32] of the + * 128-bit IP Source Address or Destination Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 1 Field + * + */ +/* + * Field : Layer 3 Address 1 Field - l3a10 + * + * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 0), this field contains the value to be matched with + * Bits [63:32] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 0), this field contains the value to be matched with + * Bits [63:32] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 + * and Layer 4 Control Register 0), this field contains the value to be matched + * with the IP Destination Address field in the IPv4 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG0. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR1_REG0_s +{ + uint32_t l3a10 : 32; /* Layer 3 Address 1 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG0. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG0_s ALT_EMAC_GMAC_LYR3_ADDR1_REG0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_OFST 0x414 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG0_OFST)) + +/* + * Register : Register 262 (Layer 3 Address 2 Register 0) - Layer3_Addr2_Reg0 + * + * For IPv4 frames, the Layer 3 Address 2 Register 0 is reserved. For IPv6 frames, + * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 2 Field + * + */ +/* + * Field : Layer 3 Address 2 Field - l3a20 + * + * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 0), this field contains the value to be matched with + * Bits [95:64] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 0), this field contains value to be matched with Bits + * [95:64] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control + * Register 0), this register is not used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG0. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR2_REG0_s +{ + uint32_t l3a20 : 32; /* Layer 3 Address 2 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG0. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG0_s ALT_EMAC_GMAC_LYR3_ADDR2_REG0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_OFST 0x418 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG0_OFST)) + +/* + * Register : Register 263 (Layer 3 Address 3 Register 0) - Layer3_Addr3_Reg0 + * + * For IPv4 frames, the Layer 3 Address 3 Register 0 is reserved. For IPv6 frames, + * it contains Bits [127:96] of the 128-bit IP Source Address or Destination + * Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 3 Field + * + */ +/* + * Field : Layer 3 Address 3 Field - l3a30 + * + * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 0), this field contains the value to be matched with + * Bits [127:96] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 0), this field contains the value to be matched with + * Bits [127:96] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control + * Register 0), this register is not used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG0. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR3_REG0_s +{ + uint32_t l3a30 : 32; /* Layer 3 Address 3 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG0. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG0_s ALT_EMAC_GMAC_LYR3_ADDR3_REG0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_OFST 0x41c +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG0_OFST)) + +/* + * Register : Register 268 (Layer 3 and Layer 4 Control Register 1) - L3_L4_Control1 + * + * This register controls the operations of the filter 0 of Layer 3 and Layer 4. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | Layer 3 Protocol Enable + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | Layer 3 IP SA Match Enable + * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable + * [4] | RW | 0x0 | Layer 3 IP DA Match Enable + * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable + * [10:6] | RW | 0x0 | Layer 3 IP SA Higher Bits Match + * [15:11] | RW | 0x0 | Layer 3 IP DA Higher Bits Match + * [16] | RW | 0x0 | Layer 4 Protocol Enable + * [17] | ??? | 0x0 | *UNDEFINED* + * [18] | RW | 0x0 | Layer 4 Source Port Match Enable + * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable + * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable + * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable + * [31:22] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Layer 3 Protocol Enable - l3pen1 + * + * When set, this bit indicates that the Layer 3 IP Source or Destination Address + * matching is enabled for the IPv6 frames. When reset, this bit indicates that the + * Layer 3 IP Source or Destination Address matching is enabled for the IPv4 + * frames. + * + * The Layer 3 matching is done only when either L3SAM1 or L3DAM1 bit is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Layer 3 IP SA Match Enable - l3sam1 + * + * When set, this bit indicates that the Layer 3 IP Source Address field is enabled + * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field + * for matching. + * + * Note: When Bit 0 (L3PEN1) is set, you should set either this bit or Bit 4 + * (L3DAM1) because either IPv6 SA or DA can be checked for filtering. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Layer 3 IP SA Inverse Match Enable - l3saim1 + * + * When set, this bit indicates that the Layer 3 IP Source Address field is enabled + * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source + * Address field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 2 (L3SAM1) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Layer 3 IP DA Match Enable - l3dam1 + * + * When set, this bit indicates that Layer 3 IP Destination Address field is + * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination + * Address field for matching. + * + * Note: When Bit 1 (L3PEN1) is set, you should set either this bit or Bit 2 + * (L3SAM1) because either IPv6 DA or SA can be checked for filtering. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Layer 3 IP DA Inverse Match Enable - l3daim1 + * + * When set, this bit indicates that the Layer 3 IP Destination Address field is + * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP + * Destination Address field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 4 (L3DAM1) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Layer 3 IP SA Higher Bits Match - l3hsbm1 + * + * IPv4 Frames: + * + * This field contains the number of lower bits of IP Source Address that are + * masked for matching in the IPv4 frames. The following list describes the values + * of this field: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 31: All bits except MSb are masked. + * + * IPv6 Frames: + * + * This field contains Bits [4:0] of the field that indicates the number of higher + * bits of IP Source or Destination Address matched in the IPv6 frames. + * + * This field is valid and applicable only if L3DAM1 or L3SAM1 is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_SET_MSK 0x000007c0 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_CLR_MSK 0xfffff83f +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_GET(value) (((value) & 0x000007c0) >> 6) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_SET(value) (((value) << 6) & 0x000007c0) + +/* + * Field : Layer 3 IP DA Higher Bits Match - l3hdbm1 + * + * IPv4 Frames: + * + * This field contains the number of higher bits of IP Destination Address that are + * matched in the IPv4 frames. The following list describes the values of this + * field: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 31: All bits except MSb are masked. + * + * IPv6 Frames: + * + * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM1, which indicate + * the number of lower bits of IP Source or Destination Address that are masked in + * the IPv6 frames. The following list describes the concatenated values of the + * L3HDBM1[1:0] and L3HSBM1 bits: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 127: All bits except MSb are masked. + * + * This field is valid and applicable only if L3DAM1 or L3SAM1 is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_SET_MSK 0x0000f800 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_CLR_MSK 0xffff07ff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_GET(value) (((value) & 0x0000f800) >> 11) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_SET(value) (((value) << 11) & 0x0000f800) + +/* + * Field : Layer 4 Protocol Enable - l4pen1 + * + * When set, this bit indicates that the Source and Destination Port number fields + * for UDP frames are used for matching. When reset, this bit indicates that the + * Source and Destination Port number fields for TCP frames are used for matching. + * + * The Layer 4 matching is done only when either L4SPM1 or L4DPM1 bit is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Layer 4 Source Port Match Enable - l4spm1 + * + * When set, this bit indicates that the Layer 4 Source Port number field is + * enabled for matching. + * + * When reset, the MAC ignores the Layer 4 Source Port number field for matching. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Layer 4 Source Port Inverse Match Enable - l4spim1 + * + * When set, this bit indicates that the Layer 4 Source Port number field is + * enabled for inverse matching. + * + * When reset, this bit indicates that the Layer 4 Source Port number field is + * enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 18 (L4SPM1) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Layer 4 Destination Port Match Enable - l4dpm1 + * + * When set, this bit indicates that the Layer 4 Destination Port number field is + * enabled for matching. + * + * When reset, the MAC ignores the Layer 4 Destination Port number field for + * matching. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim1 + * + * When set, this bit indicates that the Layer 4 Destination Port number field is + * enabled for inverse matching. + * + * When reset, this bit indicates that the Layer 4 Destination Port number field is + * enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 20 (L4DPM1) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_SET(value) (((value) << 21) & 0x00200000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL1. + */ +struct ALT_EMAC_GMAC_L3_L4_CTL1_s +{ + uint32_t l3pen1 : 1; /* Layer 3 Protocol Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t l3sam1 : 1; /* Layer 3 IP SA Match Enable */ + uint32_t l3saim1 : 1; /* Layer 3 IP SA Inverse Match Enable */ + uint32_t l3dam1 : 1; /* Layer 3 IP DA Match Enable */ + uint32_t l3daim1 : 1; /* Layer 3 IP DA Inverse Match Enable */ + uint32_t l3hsbm1 : 5; /* Layer 3 IP SA Higher Bits Match */ + uint32_t l3hdbm1 : 5; /* Layer 3 IP DA Higher Bits Match */ + uint32_t l4pen1 : 1; /* Layer 4 Protocol Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t l4spm1 : 1; /* Layer 4 Source Port Match Enable */ + uint32_t l4spim1 : 1; /* Layer 4 Source Port Inverse Match Enable */ + uint32_t l4dpm1 : 1; /* Layer 4 Destination Port Match Enable */ + uint32_t l4dpim1 : 1; /* Layer 4 Destination Port Inverse Match Enable */ + uint32_t : 10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL1. */ +typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL1_s ALT_EMAC_GMAC_L3_L4_CTL1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL1 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_OFST 0x430 +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL1_OFST)) + +/* + * Register : Register 269 (Layer 4 Address Register 1) - Layer4_Address1 + * + * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the + * Rx clock domains, then the synchronization is triggered only when Bits[31:24] + * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and + * Layer 4 Address Registers are written. For proper synchronization updates, you + * should perform the consecutive writes to the same Layer 3 and Layer 4 Address + * Registers after at least four clock cycles delay of the destination clock. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field + * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field + * + */ +/* + * Field : Layer 4 Source Port Number Field - l4sp1 + * + * When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer + * 3 and Layer 4 Control Register 1), this field contains the value to be matched + * with the TCP Source Port Number field in the IPv4 or IPv6 frames. + * + * When Bit 16 (L4PEN1) and Bit 20 (L4DPM1) are set in Register 268 (Layer 3 and + * Layer 4 Control Register 1), this field contains the value to be matched with + * the UDP Source Port Number field in the IPv4 or IPv6 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 field value from a register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Layer 4 Destination Port Number Field - l4dp1 + * + * When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer + * 3 and Layer 4 Control Register 0), this field contains the value to be matched + * with the TCP Destination Port Number field in the IPv4 or IPv6 frames. + * + * When Bit 16 (L4PEN1) and Bit 20 (L4DPM1) are set in Register 268 (Layer 3 and + * Layer 4 Control Register 1), this field contains the value to be matched with + * the UDP Destination Port Number field in the IPv4 or IPv6 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_CLR_MSK 0x0000ffff +/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 field value from a register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR1. + */ +struct ALT_EMAC_GMAC_LYR4_ADDR1_s +{ + uint32_t l4sp1 : 16; /* Layer 4 Source Port Number Field */ + uint32_t l4dp1 : 16; /* Layer 4 Destination Port Number Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR1. */ +typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR1_s ALT_EMAC_GMAC_LYR4_ADDR1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR1 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_OFST 0x434 +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR1_OFST)) + +/* + * Register : Register 272 (Layer 3 Address 0 Register 1) - Layer3_Addr0_Reg1 + * + * For IPv4 frames, the Layer 3 Address 0 Register 1 contains the 32-bit IP Source + * Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source + * Address or Destination Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 0 Field + * + */ +/* + * Field : Layer 3 Address 0 Field - l3a01 + * + * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and + * Layer 4 Control Register 1), this field contains the value to be matched with + * Bits[31:0] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and + * Layer 4 Control Register 1), this field contains the value to be matched with + * Bits [31:0] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN1) is reset and Bit 2 (L3SAM1) is set in Register 268 (Layer 3 + * and Layer 4 Control Register 1), this field contains the value to be matched + * with the IP Source Address field in the IPv4 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG1. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR0_REG1_s +{ + uint32_t l3a01 : 32; /* Layer 3 Address 0 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG1. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG1_s ALT_EMAC_GMAC_LYR3_ADDR0_REG1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_OFST 0x440 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG1_OFST)) + +/* + * Register : Register 273 (Layer 3 Address 1 Register 1) - Layer3_Addr1_Reg1 + * + * For IPv4 frames, the Layer 3 Address 1 Register 1 contains the 32-bit IP + * Destination Address field. For IPv6 frames, it contains Bits[63:32] of the + * 128-bit IP Source Address or Destination Address field + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 1 Field + * + */ +/* + * Field : Layer 3 Address 1 Field - l3a11 + * + * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and + * Layer 4 Control Register 1), this field contains the value to be matched with + * Bits [63:32] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and + * Layer 4 Control Register 1), this field contains the value to be matched with + * Bits [63:32] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN1) is reset and Bit 4 (L3DAM1) is set in Register 268 (Layer 3 + * and Layer 4 Control Register 1), this field contains the value to be matched + * with the IP Destination Address field in the IPv4 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG1. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR1_REG1_s +{ + uint32_t l3a11 : 32; /* Layer 3 Address 1 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG1. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG1_s ALT_EMAC_GMAC_LYR3_ADDR1_REG1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_OFST 0x444 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG1_OFST)) + +/* + * Register : Register 274 (Layer 3 Address 2 Register 1) - Layer3_Addr2_Reg1 + * + * For IPv4 frames, the Layer 3 Address 2 Register 1 is reserved. For IPv6 frames, + * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 2 Field + * + */ +/* + * Field : Layer 3 Address 2 Field - l3a21 + * + * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and + * Layer 4 Control Register 1), this field contains the value to be matched with + * Bits [95:64] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and + * Layer 4 Control Register 1), this field contains value to be matched with Bits + * [95:64] of the IP Destination Address field in the IPv6 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG1. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR2_REG1_s +{ + uint32_t l3a21 : 32; /* Layer 3 Address 2 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG1. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG1_s ALT_EMAC_GMAC_LYR3_ADDR2_REG1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_OFST 0x448 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG1_OFST)) + +/* + * Register : Register 275 (Layer 3 Address 3 Register 1) - Layer3_Addr3_Reg1 + * + * For IPv4 frames, the Layer 3 Address 3 Register 1 is reserved. For IPv6 frames, + * it contains Bits [127:96] of the 128-bit IP Source Address or Destination + * Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 3 Field + * + */ +/* + * Field : Layer 3 Address 3 Field - l3a31 + * + * When Bit 1 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and + * Layer 4 Control Register 1), this field contains the value to be matched with + * Bits [127:96] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and + * Layer 4 Control Register 1), this field contains the value to be matched with + * Bits [127:96] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN1) is reset in Register 268 (Layer 3 and Layer 4 Control + * Register 1), this register is not used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG1. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR3_REG1_s +{ + uint32_t l3a31 : 32; /* Layer 3 Address 3 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG1. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG1_s ALT_EMAC_GMAC_LYR3_ADDR3_REG1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_OFST 0x44c +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG1_OFST)) + +/* + * Register : Register 280 (Layer 3 and Layer 4 Control Register 2) - L3_L4_Control2 + * + * This register controls the operations of the filter 2 of Layer 3 and Layer 4. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | Layer 3 Protocol Enable + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | Layer 3 IP SA Match Enable + * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable + * [4] | RW | 0x0 | Layer 3 IP DA Match Enable + * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable + * [10:6] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 + * [15:11] | RW | 0x0 | Layer 3 IP DA Higher Bits Match + * [16] | RW | 0x0 | Layer 4 Protocol Enable + * [17] | ??? | 0x0 | *UNDEFINED* + * [18] | RW | 0x0 | Layer 4 Source Port Match Enable + * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable + * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable + * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable + * [31:22] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Layer 3 Protocol Enable - l3pen2 + * + * When set, this bit indicates that the Layer 3 IP Source or Destination Address + * matching is enabled for the IPv6 frames. When reset, this bit indicates that the + * Layer 3 IP Source or Destination Address matching is enabled for the IPv4 + * frames. + * + * The Layer 3 matching is done only when either L3SAM2 or L3DAM2 bit is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Layer 3 IP SA Match Enable - l3sam2 + * + * When set, this bit indicates that the Layer 3 IP Source Address field is enabled + * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field + * for matching. + * + * Note: When Bit 0 (L3PEN2) is set, you should set either this bit or Bit 4 + * (L3DAM2) because either IPv6 SA or DA can be checked for filtering. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Layer 3 IP SA Inverse Match Enable - l3saim2 + * + * When set, this bit indicates that the Layer 3 IP Source Address field is enabled + * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source + * Address field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 2 (L3SAM2) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Layer 3 IP DA Match Enable - l3dam2 + * + * When set, this bit indicates that Layer 3 IP Destination Address field is + * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination + * Address field for matching. + * + * Note: When Bit 0 (L3PEN2) is set, you should set either this bit or Bit 2 + * (L3SAM2) because either IPv6 DA or SA can be checked for filtering. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Layer 3 IP DA Inverse Match Enable - l3daim2 + * + * When set, this bit indicates that the Layer 3 IP Destination Address field is + * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP + * Destination Address field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 4 (L3DAM2) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : l3hsbm2 + * + * Layer 3 IP SA Higher Bits Match + * + * IPv4 Frames: + * + * This field contains the number of lower bits of IP Source Address that are + * masked for matching in the IPv4 frames. The following list describes the values + * of this field: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 31: All bits except MSb are masked. + * + * IPv6 Frames: + * + * This field contains Bits [4:0] of the field that indicates the number of higher + * bits of IP Source or Destination Address matched in the IPv6 frames. + * + * This field is valid and applicable only if L3DAM2 or L3SAM2 is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET_MSK 0x000007c0 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_CLR_MSK 0xfffff83f +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_GET(value) (((value) & 0x000007c0) >> 6) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET(value) (((value) << 6) & 0x000007c0) + +/* + * Field : Layer 3 IP DA Higher Bits Match - l3hdbm2 + * + * IPv4 Frames: + * + * This field contains the number of higher bits of IP Destination Address that are + * matched in the IPv4 frames. The following list describes the values of this + * field: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 31: All bits except MSb are masked. + * + * IPv6 Frames: + * + * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM2, which indicate + * the number of lower bits of IP Source or Destination Address that are masked in + * the IPv6 frames. The following list describes the concatenated values of the + * L3HDBM2[1:0] and L3HSBM2 bits: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 127: All bits except MSb are masked. + * + * This field is valid and applicable only if L3DAM2 or L3SAM2 is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET_MSK 0x0000f800 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_CLR_MSK 0xffff07ff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_GET(value) (((value) & 0x0000f800) >> 11) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET(value) (((value) << 11) & 0x0000f800) + +/* + * Field : Layer 4 Protocol Enable - l4pen2 + * + * When set, this bit indicates that the Source and Destination Port number fields + * for UDP frames are used for matching. When reset, this bit indicates that the + * Source and Destination Port number fields for TCP frames are used for matching. + * + * The Layer 4 matching is done only when either L4SPM2 or L4DPM2 bit is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Layer 4 Source Port Match Enable - l4spm2 + * + * When set, this bit indicates that the Layer 4 Source Port number field is + * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number + * field for matching. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Layer 4 Source Port Inverse Match Enable - l4spim2 + * + * When set, this bit indicates that the Layer 4 Source Port number field is + * enabled for inverse matching. When reset, this bit indicates that the Layer 4 + * Source Port number field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 18 (L4SPM2) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Layer 4 Destination Port Match Enable - l4dpm2 + * + * When set, this bit indicates that the Layer 4 Destination Port number field is + * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port + * number field for matching. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim2 + * + * When set, this bit indicates that the Layer 4 Destination Port number field is + * enabled for inverse matching. When reset, this bit indicates that the Layer 4 + * Destination Port number field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET(value) (((value) << 21) & 0x00200000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL2. + */ +struct ALT_EMAC_GMAC_L3_L4_CTL2_s +{ + uint32_t l3pen2 : 1; /* Layer 3 Protocol Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t l3sam2 : 1; /* Layer 3 IP SA Match Enable */ + uint32_t l3saim2 : 1; /* Layer 3 IP SA Inverse Match Enable */ + uint32_t l3dam2 : 1; /* Layer 3 IP DA Match Enable */ + uint32_t l3daim2 : 1; /* Layer 3 IP DA Inverse Match Enable */ + uint32_t l3hsbm2 : 5; /* ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 */ + uint32_t l3hdbm2 : 5; /* Layer 3 IP DA Higher Bits Match */ + uint32_t l4pen2 : 1; /* Layer 4 Protocol Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t l4spm2 : 1; /* Layer 4 Source Port Match Enable */ + uint32_t l4spim2 : 1; /* Layer 4 Source Port Inverse Match Enable */ + uint32_t l4dpm2 : 1; /* Layer 4 Destination Port Match Enable */ + uint32_t l4dpim2 : 1; /* Layer 4 Destination Port Inverse Match Enable */ + uint32_t : 10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL2. */ +typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL2_s ALT_EMAC_GMAC_L3_L4_CTL2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL2 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_OFST 0x460 +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL2_OFST)) + +/* + * Register : Register 281 (Layer 4 Address Register 2) - Layer4_Address2 + * + * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the + * Rx clock domains, then the synchronization is triggered only when Bits[31:24] + * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and + * Layer 4 Address Registers are written. For proper synchronization updates, you + * should perform the consecutive writes to the same Layer 3 and Layer 4 Address + * Registers after at least four clock cycles delay of the destination clock. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field + * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field + * + */ +/* + * Field : Layer 4 Source Port Number Field - l4sp2 + * + * When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer + * 3 and Layer 4 Control Register 2), this field contains the value to be matched + * with the TCP Source Port Number field in the IPv4 or IPv6 frames. + * + * When Bit 16 (L4PEN2) and Bit 20 (L4DPM2) are set in Register 280 (Layer 3 and + * Layer 4 Control Register 2), this field contains the value to be matched with + * the UDP Source Port Number field in the IPv4 or IPv6 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 field value from a register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Layer 4 Destination Port Number Field - l4dp2 + * + * When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer + * 3 and Layer 4 Control Register 2), this field contains the value to be matched + * with the TCP Destination Port Number field in the IPv4 or IPv6 frames. + * + * When Bit 16 (L4PEN2) and Bit 20 (L4DPM2) are set in Register 280 (Layer 3 and + * Layer 4 Control Register 2), this field contains the value to be matched with + * the UDP Destination Port Number field in the IPv4 or IPv6 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_CLR_MSK 0x0000ffff +/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 field value from a register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR2. + */ +struct ALT_EMAC_GMAC_LYR4_ADDR2_s +{ + uint32_t l4sp2 : 16; /* Layer 4 Source Port Number Field */ + uint32_t l4dp2 : 16; /* Layer 4 Destination Port Number Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR2. */ +typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR2_s ALT_EMAC_GMAC_LYR4_ADDR2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR2 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_OFST 0x464 +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR2_OFST)) + +/* + * Register : Register 284 (Layer 3 Address 0 Register 2) - Layer3_Addr0_Reg2 + * + * For IPv4 frames, the Layer 3 Address 0 Register 2 contains the 32-bit IP Source + * Address field. For IPv6 frames, it contains Bits [31:0] of the 128-bit IP Source + * Address or Destination Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 0 Field + * + */ +/* + * Field : Layer 3 Address 0 Field - l3a02 + * + * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and + * Layer 4 Control Register 2), this field contains the value to be matched with + * Bits [31:0] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and + * Layer 4 Control Register 2), this field contains the value to be matched with + * Bits [31:0] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN2) is reset and Bit 2 (L3SAM2) is set in Register 280 (Layer 3 + * and Layer 4 Control Register 2), this field contains the value to be matched + * with the IP Source Address field in the IPv4 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG2. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR0_REG2_s +{ + uint32_t l3a02 : 32; /* Layer 3 Address 0 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG2. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG2_s ALT_EMAC_GMAC_LYR3_ADDR0_REG2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_OFST 0x470 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG2_OFST)) + +/* + * Register : Register 285 (Layer 3 Address 1 Register 2) - Layer3_Addr1_Reg2 + * + * For IPv4 frames, the Layer 3 Address 1 Register 2 contains the 32-bit IP + * Destination Address field. For IPv6 frames, it contains Bits [63:32] of the + * 128-bit IP Source Address or Destination Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 1 Field + * + */ +/* + * Field : Layer 3 Address 1 Field - l3a12 + * + * Layer 3 Address 1 Field + * + * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and + * Layer 4 Control Register 2), this field contains the value to be matched with + * Bits [63:32] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and + * Layer 4 Control Register 2), this field contains the value to be matched with + * Bits [63:32] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN2) is reset and Bit 4 (L3DAM2) is set in Register 280 (Layer 3 + * and Layer 4 Control Register 2), this field contains the value to be matched + * with the IP Destination Address field in the IPv4 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG2. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR1_REG2_s +{ + uint32_t l3a12 : 32; /* Layer 3 Address 1 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG2. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG2_s ALT_EMAC_GMAC_LYR3_ADDR1_REG2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_OFST 0x474 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG2_OFST)) + +/* + * Register : Register 286 (Layer 3 Address 2 Register 2) - Layer3_Addr2_Reg2 + * + * For IPv4 frames, the Layer 3 Address 2 Register 2 is reserved. For IPv6 frames, + * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 2 Field + * + */ +/* + * Field : Layer 3 Address 2 Field - l3a22 + * + * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and + * Layer 4 Control Register 2), this field contains the value to be matched with + * Bits [95:64] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 256 (Layer 3 and + * Layer 4 Control Register 2), this field contains value to be matched with Bits + * [95:64] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN2) is reset in Register 280 (Layer 3 and Layer 4 Control + * Register 2), this register is not used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG2. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR2_REG2_s +{ + uint32_t l3a22 : 32; /* Layer 3 Address 2 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG2. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG2_s ALT_EMAC_GMAC_LYR3_ADDR2_REG2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_OFST 0x478 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG2_OFST)) + +/* + * Register : Register 287 (Layer 3 Address 3 Register 2) - Layer3_Addr3_Reg2 + * + * For IPv4 frames, the Layer 3 Address 3 Register 2 is reserved. For IPv6 frames, + * it contains Bits [127:96] of the 128-bit IP Source Address or Destination + * Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 3 Field + * + */ +/* + * Field : Layer 3 Address 3 Field - l3a32 + * + * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and + * Layer 4 Control Register 2), this field contains the value to be matched with + * Bits [127:96] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and + * Layer 4 Control Register 2), this field contains the value to be matched with + * Bits [127:96] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN2) is reset in Register 280 (Layer 3 and Layer 4 Control + * Register 2), this register is not used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG2. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR3_REG2_s +{ + uint32_t l3a32 : 32; /* Layer 3 Address 3 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG2. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG2_s ALT_EMAC_GMAC_LYR3_ADDR3_REG2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_OFST 0x47c +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG2_OFST)) + +/* + * Register : Register 292 (Layer 3 and Layer 4 Control Register 3) - L3_L4_Control3 + * + * This register controls the operations of the filter 0 of Layer 3 and Layer 4. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | Layer 3 Protocol Enable + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | Layer 3 IP SA Match Enable + * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable + * [4] | RW | 0x0 | Layer 3 IP DA Match Enable + * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable + * [10:6] | RW | 0x0 | Layer 3 IP SA Higher Bits Match + * [15:11] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 + * [16] | RW | 0x0 | Layer 4 Protocol Enable + * [17] | ??? | 0x0 | *UNDEFINED* + * [18] | RW | 0x0 | Layer 4 Source Port Match Enable + * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable + * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable + * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable + * [31:22] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Layer 3 Protocol Enable - l3pen3 + * + * When set, this bit indicates that the Layer 3 IP Source or Destination Address + * matching is enabled for the IPv6 frames. When reset, this bit indicates that the + * Layer 3 IP Source or Destination Address matching is enabled for the IPv4 + * frames. + * + * The Layer 3 matching is done only when either L3SAM3 or L3DAM3 bit is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Layer 3 IP SA Match Enable - l3sam3 + * + * When set, this bit indicates that the Layer 3 IP Source Address field is enabled + * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field + * for matching. + * + * Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 4 + * (L3DAM3) because either IPv6 SA or DA can be checked for filtering. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Layer 3 IP SA Inverse Match Enable - l3saim3 + * + * When set, this bit indicates that the Layer 3 IP Source Address field is enabled + * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source + * Address field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 2 (L3SAM3) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Layer 3 IP DA Match Enable - l3dam3 + * + * When set, this bit indicates that Layer 3 IP Destination Address field is + * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination + * Address field for matching. + * + * Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 2 + * (L3SAM3) because either IPv6 DA or SA can be checked for filtering. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Layer 3 IP DA Inverse Match Enable - l3daim3 + * + * When set, this bit indicates that the Layer 3 IP Destination Address field is + * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP + * Destination Address field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 4 (L3DAM3) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Layer 3 IP SA Higher Bits Match - l3hsbm3 + * + * IPv4 Frames: + * + * This field contains the number of lower bits of IP Source Address that are + * masked for matching in the IPv4 frames. The following list describes the values + * of this field: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 31: All bits except MSb are masked. + * + * IPv6 Frames: + * + * This field contains Bits [4:0] of the field that indicates the number of higher + * bits of IP Source or Destination Address matched in the IPv6 frames. + * + * This field is valid and applicable only if L3DAM3 or L3SAM3 is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET_MSK 0x000007c0 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_CLR_MSK 0xfffff83f +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_GET(value) (((value) & 0x000007c0) >> 6) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET(value) (((value) << 6) & 0x000007c0) + +/* + * Field : l3hdbm3 + * + * Layer 3 IP DA Higher Bits Match + * + * IPv4 Frames: + * + * This field contains the number of higher bits of IP Destination Address that are + * matched in the IPv4 frames. The following list describes the values of this + * field: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 31: All bits except MSb are masked. + * + * IPv6 Frames: + * + * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM3, which indicate + * the number of lower bits of IP Source or Destination Address that are masked in + * the IPv6 frames. The following list describes the concatenated values of the + * L3HDBM3[1:0] and L3HSBM3 bits: + * + * * 0: No bits are masked. + * + * * 1: LSb[0] is masked. + * + * * 2: Two LSbs [1:0] are masked. + * + * * ... + * + * * 127: All bits except MSb are masked. + * + * This field is valid and applicable only if L3DAM3 or L3SAM3 is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET_MSK 0x0000f800 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_CLR_MSK 0xffff07ff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_GET(value) (((value) & 0x0000f800) >> 11) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET(value) (((value) << 11) & 0x0000f800) + +/* + * Field : Layer 4 Protocol Enable - l4pen3 + * + * When set, this bit indicates that the Source and Destination Port number fields + * for UDP frames are used for matching. When reset, this bit indicates that the + * Source and Destination Port number fields for TCP frames are used for matching. + * + * The Layer 4 matching is done only when either L4SPM3 or L4DPM3 bit is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_MSB 16 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Layer 4 Source Port Match Enable - l4spm3 + * + * When set, this bit indicates that the Layer 4 Source Port number field is + * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number + * field for matching. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Layer 4 Source Port Inverse Match Enable - l4spim3 + * + * When set, this bit indicates that the Layer 4 Source Port number field is + * enabled for inverse matching. When reset, this bit indicates that the Layer 4 + * Source Port number field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 18 (L4SPM3) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Layer 4 Destination Port Match Enable - l4dpm3 + * + * When set, this bit indicates that the Layer 4 Destination Port number field is + * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port + * number field for matching. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_MSB 20 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim3 + * + * When set, this bit indicates that the Layer 4 Destination Port number field is + * enabled for inverse matching. When reset, this bit indicates that the Layer 4 + * Destination Port number field is enabled for perfect matching. + * + * This bit is valid and applicable only when Bit 20 (L4DPM3) is set high. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_MSB 21 +/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 field value from a register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET(value) (((value) << 21) & 0x00200000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL3. + */ +struct ALT_EMAC_GMAC_L3_L4_CTL3_s +{ + uint32_t l3pen3 : 1; /* Layer 3 Protocol Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t l3sam3 : 1; /* Layer 3 IP SA Match Enable */ + uint32_t l3saim3 : 1; /* Layer 3 IP SA Inverse Match Enable */ + uint32_t l3dam3 : 1; /* Layer 3 IP DA Match Enable */ + uint32_t l3daim3 : 1; /* Layer 3 IP DA Inverse Match Enable */ + uint32_t l3hsbm3 : 5; /* Layer 3 IP SA Higher Bits Match */ + uint32_t l3hdbm3 : 5; /* ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 */ + uint32_t l4pen3 : 1; /* Layer 4 Protocol Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t l4spm3 : 1; /* Layer 4 Source Port Match Enable */ + uint32_t l4spim3 : 1; /* Layer 4 Source Port Inverse Match Enable */ + uint32_t l4dpm3 : 1; /* Layer 4 Destination Port Match Enable */ + uint32_t l4dpim3 : 1; /* Layer 4 Destination Port Inverse Match Enable */ + uint32_t : 10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL3. */ +typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL3_s ALT_EMAC_GMAC_L3_L4_CTL3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL3 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_OFST 0x490 +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register. */ +#define ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL3_OFST)) + +/* + * Register : Register 293 (Layer 4 Address Register 3) - Layer4_Address3 + * + * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the + * Rx clock domains, then the synchronization is triggered only when Bits[31:24] + * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and + * Layer 4 Address Registers are written. For proper synchronization updates, you + * should perform the consecutive writes to the same Layer 3 and Layer 4 Address + * Registers after at least four clock cycles delay of the destination clock. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field + * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field + * + */ +/* + * Field : Layer 4 Source Port Number Field - l4sp3 + * + * When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer + * 3 and Layer 4 Control Register 3), this field contains the value to be matched + * with the TCP Source Port Number field in the IPv4 or IPv6 frames. + * + * When Bit 16 (L4PEN3) and Bit 20 (L4DPM3) are set in Register 292 (Layer 3 and + * Layer 4 Control Register 3), this field contains the value to be matched with + * the UDP Source Port Number field in the IPv4 or IPv6 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 field value from a register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Layer 4 Destination Port Number Field - l4dp3 + * + * When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer + * 3 and Layer 4 Control Register 3), this field contains the value to be matched + * with the TCP Destination Port Number field in the IPv4 or IPv6 frames. + * + * When Bit 16 (L4PEN3) and Bit 20 (L4DPM3) are set in Register 292 (Layer 3 and + * Layer 4 Control Register 3), this field contains the value to be matched with + * the UDP Destination Port Number field in the IPv4 or IPv6 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_CLR_MSK 0x0000ffff +/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 field value from a register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR3. + */ +struct ALT_EMAC_GMAC_LYR4_ADDR3_s +{ + uint32_t l4sp3 : 16; /* Layer 4 Source Port Number Field */ + uint32_t l4dp3 : 16; /* Layer 4 Destination Port Number Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR3. */ +typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR3_s ALT_EMAC_GMAC_LYR4_ADDR3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR3 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_OFST 0x494 +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register. */ +#define ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR3_OFST)) + +/* + * Register : Register 296 (Layer 3 Address 0 Register 3) - Layer3_Addr0_Reg3 + * + * For IPv4 frames, the Layer 3 Address 0 Register 3 contains the 32-bit IP Source + * Address field. For IPv6 frames, it contains Bits [31:0] of the 128-bit IP Source + * Address or Destination Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 0 Field + * + */ +/* + * Field : Layer 3 Address 0 Field - l3a03 + * + * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and + * Layer 4 Control Register 3), this field contains the value to be matched with + * Bits [31:0] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and + * Layer 4 Control Register 3), this field contains the value to be matched with + * Bits [31:0] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN3) is reset and Bit 2 (L3SAM3) is set in Register 292 (Layer 3 + * and Layer 4 Control Register 3), this field contains the value to be matched + * with the IP Source Address field in the IPv4 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG3. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR0_REG3_s +{ + uint32_t l3a03 : 32; /* Layer 3 Address 0 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG3. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG3_s ALT_EMAC_GMAC_LYR3_ADDR0_REG3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_OFST 0x4a0 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG3_OFST)) + +/* + * Register : Register 297 (Layer 3 Address 1 Register 3) - Layer3_Addr1_Reg3 + * + * For IPv4 frames, the Layer 3 Address 1 Register 3 contains the 32-bit IP + * Destination Address field. For IPv6 frames, it contains Bits [63:32] of the + * 128-bit IP Source Address or Destination Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 1 Field + * + */ +/* + * Field : Layer 3 Address 1 Field - l3a13 + * + * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and + * Layer 4 Control Register 3), this field contains the value to be matched with + * Bits [63:32] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and + * Layer 4 Control Register 3), this field contains the value to be matched with + * Bits [63:32] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN3) is reset and Bit 4 (L3DAM3) is set in Register 292 (Layer 3 + * and Layer 4 Control Register 3), this field contains the value to be matched + * with the IP Destination Address field in the IPv4 frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG3. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR1_REG3_s +{ + uint32_t l3a13 : 32; /* Layer 3 Address 1 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG3. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG3_s ALT_EMAC_GMAC_LYR3_ADDR1_REG3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_OFST 0x4a4 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG3_OFST)) + +/* + * Register : Register 298 (Layer 3 Address 2 Register 3) - Layer3_Addr2_Reg3 + * + * For IPv4 frames, the Layer 3 Address 2 Register 3 is reserved. For IPv6 frames, + * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 2 Field + * + */ +/* + * Field : Layer 3 Address 2 Field - l3a23 + * + * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and + * Layer 4 Control Register 3), this field contains the value to be matched with + * Bits [95:64] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and + * Layer 4 Control Register 3), this field contains value to be matched with Bits + * [95:64] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN3) is reset in Register 292 (Layer 3 and Layer 4 Control + * Register 3), this register is not used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG3. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR2_REG3_s +{ + uint32_t l3a23 : 32; /* Layer 3 Address 2 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG3. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG3_s ALT_EMAC_GMAC_LYR3_ADDR2_REG3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_OFST 0x4a8 +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG3_OFST)) + +/* + * Register : Register 299 (Layer 3 Address 3 Register 3) - Layer3_Addr3_Reg3 + * + * For IPv4 frames, the Layer 3 Address 3 Register 3 is reserved. For IPv6 frames, + * it contains Bits [127:96] of the 128-bit IP Source Address or Destination + * Address field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Layer 3 Address 3 Field + * + */ +/* + * Field : Layer 3 Address 3 Field - l3a33 + * + * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and + * Layer 4 Control Register 3), this field contains the value to be matched with + * Bits [127:96] of the IP Source Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and + * Layer 4 Control Register 3), this field contains the value to be matched with + * Bits [127:96] of the IP Destination Address field in the IPv6 frames. + * + * When Bit 0 (L3PEN3) is reset in Register 292 (Layer 3 and Layer 4 Control + * Register 3), this register is not used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 field value from a register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG3. + */ +struct ALT_EMAC_GMAC_LYR3_ADDR3_REG3_s +{ + uint32_t l3a33 : 32; /* Layer 3 Address 3 Field */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG3. */ +typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG3_s ALT_EMAC_GMAC_LYR3_ADDR3_REG3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_OFST 0x4ac +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register. */ +#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG3_OFST)) + +/* + * Register : Register 320 (Hash Table Register 0) - Hash_Table_Reg0 + * + * This register contains the first 32 bits of the hash table. + * + * The 256-bit Hash table is used for group address filtering. For hash filtering, + * the content of the destination address in the incoming frame is passed through + * the CRC logic and the upper eight bits of the CRC register are used to index the + * content of the Hash table. The most significant bits determines the register to + * be used (Hash Table Register X), and the least significant five bits determine + * the bit within the register. For example, a hash value of 8b'10111111 selects + * Bit 31 of the Hash Table Register 5. + * + * The hash value of the destination address is calculated in the following way: + * + * 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the + * steps to calculate CRC32). + * + * 2. Perform bitwise reversal for the value obtained in Step 1. + * + * 3. Take the upper 8 bits from the value obtained in Step 2. + * + * If the corresponding bit value of the register is 1'b1, the frame is accepted. + * Otherwise, it is rejected. If the Bit 1 (Pass All Multicast) is set in Register + * 1 (MAC Frame Filter), then all multicast frames are accepted regardless of the + * multicast hash values. + * + * Because the Hash Table register is double-synchronized to the (G)MII clock + * domain, the synchronization is triggered only when Bits[31:24] (in little-endian + * mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers + * are written. + * + * Note: Because of double-synchronization, consecutive writes to this register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [31:0] | RW | 0x0 | First 32 bits of Hash Table + * + */ +/* + * Field : First 32 bits of Hash Table - ht31t0 + * + * This field contains the first 32 Bits (31:0) of the Hash table. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 field value from a register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG0. + */ +struct ALT_EMAC_GMAC_HASH_TABLE_REG0_s +{ + uint32_t ht31t0 : 32; /* First 32 bits of Hash Table */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG0. */ +typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG0_s ALT_EMAC_GMAC_HASH_TABLE_REG0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST 0x500 +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST)) + +/* + * Register : Register 321 (Hash Table Register 1) - Hash_Table_Reg1 + * + * This register contains the second 32 bits of the hash table. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [31:0] | RW | 0x0 | Second 32 bits of Hash Table + * + */ +/* + * Field : Second 32 bits of Hash Table - ht63t32 + * + * This field contains the second 32 Bits (63:32) of the Hash table. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 field value from a register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG1. + */ +struct ALT_EMAC_GMAC_HASH_TABLE_REG1_s +{ + uint32_t ht63t32 : 32; /* Second 32 bits of Hash Table */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG1. */ +typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG1_s ALT_EMAC_GMAC_HASH_TABLE_REG1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG1_OFST 0x504 +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG1_OFST)) + +/* + * Register : Register 322 (Hash Table Register 2) - Hash_Table_Reg2 + * + * This register contains the third 32 bits of the hash table. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [31:0] | RW | 0x0 | Third 32 bits of Hash Table + * + */ +/* + * Field : Third 32 bits of Hash Table - ht95t64 + * + * This field contains the third 32 Bits (95:64) of the Hash table. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 field value from a register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG2. + */ +struct ALT_EMAC_GMAC_HASH_TABLE_REG2_s +{ + uint32_t ht95t64 : 32; /* Third 32 bits of Hash Table */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG2. */ +typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG2_s ALT_EMAC_GMAC_HASH_TABLE_REG2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG2_OFST 0x508 +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG2_OFST)) + +/* + * Register : Register 323 (Hash Table Register 3) - Hash_Table_Reg3 + * + * This register contains the fourth 32 bits of the hash table. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [31:0] | RW | 0x0 | Fourth 32 bits of Hash Table + * + */ +/* + * Field : Fourth 32 bits of Hash Table - ht127t96 + * + * This field contains the fourth 32 Bits (127:96) of the Hash table. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 field value from a register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG3. + */ +struct ALT_EMAC_GMAC_HASH_TABLE_REG3_s +{ + uint32_t ht127t96 : 32; /* Fourth 32 bits of Hash Table */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG3. */ +typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG3_s ALT_EMAC_GMAC_HASH_TABLE_REG3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG3_OFST 0x50c +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG3_OFST)) + +/* + * Register : Register 324 (Hash Table Register 4) - Hash_Table_Reg4 + * + * This register contains the fifth 32 bits of the hash table. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [31:0] | RW | 0x0 | Fifth 32 bits of Hash Table + * + */ +/* + * Field : Fifth 32 bits of Hash Table - ht159t128 + * + * This field contains the fifth 32 Bits (159:128) of the Hash table. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 field value from a register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG4. + */ +struct ALT_EMAC_GMAC_HASH_TABLE_REG4_s +{ + uint32_t ht159t128 : 32; /* Fifth 32 bits of Hash Table */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG4. */ +typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG4_s ALT_EMAC_GMAC_HASH_TABLE_REG4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG4_OFST 0x510 +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG4_OFST)) + +/* + * Register : Register 325 (Hash Table Register 5) - Hash_Table_Reg5 + * + * This register contains the sixth 32 bits of the hash table. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [31:0] | RW | 0x0 | Sixth 32 bits of Hash Table + * + */ +/* + * Field : Sixth 32 bits of Hash Table - ht191t160 + * + * This field contains the sixth 32 Bits (191:160) of the Hash table. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 field value from a register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG5. + */ +struct ALT_EMAC_GMAC_HASH_TABLE_REG5_s +{ + uint32_t ht191t160 : 32; /* Sixth 32 bits of Hash Table */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG5. */ +typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG5_s ALT_EMAC_GMAC_HASH_TABLE_REG5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG5_OFST 0x514 +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG5_OFST)) + +/* + * Register : Register 326 (Hash Table Register 6) - Hash_Table_Reg6 + * + * This register contains the seventh 32 bits of the hash table. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | Seventh 32 bits of Hash Table + * + */ +/* + * Field : Seventh 32 bits of Hash Table - ht223t196 + * + * This field contains the seventh 32 Bits (223:196) of the Hash table. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 field value from a register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG6. + */ +struct ALT_EMAC_GMAC_HASH_TABLE_REG6_s +{ + uint32_t ht223t196 : 32; /* Seventh 32 bits of Hash Table */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG6. */ +typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG6_s ALT_EMAC_GMAC_HASH_TABLE_REG6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG6_OFST 0x518 +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG6_OFST)) + +/* + * Register : Register 327 (Hash Table Register 7) - Hash_Table_Reg7 + * + * This register contains the eighth 32 bits of the hash table. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [31:0] | RW | 0x0 | Eighth 32 bits of Hash Table + * + */ +/* + * Field : Eighth 32 bits of Hash Table - ht255t224 + * + * This field contains the eighth 32 Bits (255:224) of the Hash table. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 field value from a register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG7. + */ +struct ALT_EMAC_GMAC_HASH_TABLE_REG7_s +{ + uint32_t ht255t224 : 32; /* Eighth 32 bits of Hash Table */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG7. */ +typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG7_s ALT_EMAC_GMAC_HASH_TABLE_REG7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register from the beginning of the component. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG7_OFST 0x51c +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register. */ +#define ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG7_OFST)) + +/* + * Register : Register 353 (VLAN Tag Inclusion or Replacement Register) - VLAN_Incl_Reg + * + * The VLAN Tag Inclusion or Replacement register contains the VLAN tag for + * insertion or replacement in the transmit frames. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------------------ + * [15:0] | RW | Unknown | VLAN Tag for Transmit Frames + * [17:16] | RW | Unknown | VLAN Tag Control in Transmit Frames + * [18] | RW | Unknown | VLAN Priority Control + * [19] | RW | Unknown | C-VLAN or S-VLAN + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : VLAN Tag for Transmit Frames - vlt + * + * This field contains the value of the VLAN tag to be inserted or replaced. The + * value must only be changed when the transmit lines are inactive or during the + * initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, + * and Bits[11:0] are the VLAN tag's VID field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field is UNKNOWN. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT field value from a register. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : VLAN Tag Control in Transmit Frames - vlc + * + * * 2'b00: No VLAN tag deletion, insertion, or replacement + * + * * 2'b01: VLAN tag deletion + * + * The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) + * of all transmitted frames with VLAN tags. + * + * * 2'b10: VLAN tag insertion + * + * The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type + * value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all + * transmitted frames, irrespective of whether they already have a VLAN tag. + * + * * 2'b11: VLAN tag replacement + * + * The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames + * (Bytes 13 and 14 are 0x8100/0x88a8). + * + * Note: Changes to this field take effect only on the start of a frame. If you + * write this register field when a frame is being transmitted, only the subsequent + * frame can use the updated value, that is, the current frame does not use the + * updated value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_MSB 17 +/* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_SET_MSK 0x00030000 +/* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_CLR_MSK 0xfffcffff +/* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field is UNKNOWN. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC field value from a register. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : VLAN Priority Control - vlp + * + * When this bit is set, the control Bits [17:16] are used for VLAN deletion, + * insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control + * input is used, and Bits [17:16] are ignored. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field is UNKNOWN. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP field value from a register. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : C-VLAN or S-VLAN - csvl + * + * When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th + * and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type + * (0x8100) is inserted or replaced in the transmitted frames. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field is UNKNOWN. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL field value from a register. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_SET(value) (((value) << 19) & 0x00080000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_VLAN_INCL_REG. + */ +struct ALT_EMAC_GMAC_VLAN_INCL_REG_s +{ + uint32_t vlt : 16; /* VLAN Tag for Transmit Frames */ + uint32_t vlc : 2; /* VLAN Tag Control in Transmit Frames */ + uint32_t vlp : 1; /* VLAN Priority Control */ + uint32_t csvl : 1; /* C-VLAN or S-VLAN */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_VLAN_INCL_REG. */ +typedef volatile struct ALT_EMAC_GMAC_VLAN_INCL_REG_s ALT_EMAC_GMAC_VLAN_INCL_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_VLAN_INCL_REG register from the beginning of the component. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_OFST 0x584 +/* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register. */ +#define ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_INCL_REG_OFST)) + +/* + * Register : Register 354 (VLAN Hash Table Register) - VLAN_Hash_Table_Reg + * + * The 16-bit Hash table is used for group address filtering based on VLAN tag when + * Bit 18 (VTHM) of Register 7 (VLAN Tag Register) is set. For hash filtering, the + * content of the 16-bit VLAN tag or 12-bit VLAN ID (based on Bit 16 (ETV) of VLAN + * Tag Register) in the incoming frame is passed through the CRC logic and the + * upper four bits of the calculated CRC are used to index the contents of the VLAN + * Hash table. For example, a hash value of 4b'1000 selects Bit 8 of the VLAN Hash + * table. + * + * The hash value of the destination address is calculated in the following way: + * + * 1. Calculate the 32-bit CRC for the VLAN tag or ID (See IEEE 802.3, Section + * 3.2.8 for the steps to calculate CRC32). + * + * 2. Perform bitwise reversal for the value obtained in Step 1. + * + * 3. Take the upper four bits from the value obtained in Step 2. + * + * If the corresponding bit value of the register is 1'b1, the frame is accepted. + * Otherwise, it is rejected. Because the Hash Table register is double- + * synchronized to the (G)MII clock domain, the synchronization is triggered only + * when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of + * this register are written. + * + * Notes: + * + * * Because of double-synchronization, consecutive writes to this register should + * be performed after at least four clock cycles in the destination clock domain. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------- + * [15:0] | RW | 0x0 | VLAN Hash Table + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : VLAN Hash Table - vlht + * + * This field contains the 16-bit VLAN Hash Table. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */ +#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */ +#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */ +#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value. */ +#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value. */ +#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */ +#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT field value from a register. */ +#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG. + */ +struct ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_s +{ + uint32_t vlht : 16; /* VLAN Hash Table */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG. */ +typedef volatile struct ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_s ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register from the beginning of the component. */ +#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_OFST 0x588 +/* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register. */ +#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_OFST)) + +/* + * Register : Register 448 (Timestamp Control Register) - Timestamp_Control + * + * This register controls the operation of the System Time generator and the + * processing of PTP packets for timestamping in the Receiver. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------------------- + * [0] | RW | 0x0 | Timestamp Enable + * [1] | RW | 0x0 | Timestamp Fine or Coarse Update + * [2] | RW | 0x0 | Timestamp Initialize + * [3] | RW | 0x0 | Timestamp Update + * [4] | RW | 0x0 | Timestamp Interrupt Trigger Enable + * [5] | RW | 0x0 | Addend Reg Update + * [7:6] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | Enable Timestamp for All Frames + * [9] | RW | 0x0 | Timestamp Digital or Binary Rollover Control + * [10] | RW | 0x0 | Enable PTP packet Processing for Version 2 Format + * [11] | RW | 0x0 | Enable Processing of PTP over Ethernet Frames + * [12] | RW | 0x0 | Enable Processing of PTP Frames Sent Over IPv6-UDP + * [13] | RW | 0x1 | Enable Processing of PTP Frames Sent over IPv4-UDP + * [14] | RW | 0x0 | Enable Timestamp Snapshot for Event Messages + * [15] | RW | 0x0 | Enable Snapshot for Messages Relevant to Master + * [17:16] | RW | 0x0 | Select PTP packets for Taking Snapshots + * [18] | RW | 0x0 | Enable MAC address for PTP Frame Filtering + * [23:19] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Auxiliary Snapshot FIFO Clear + * [25] | RW | 0x0 | Auxiliary Snapshot 0 Enable + * [31:26] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timestamp Enable - tsena + * + * When set, the timestamp is added for the transmit and receive frames. When + * disabled, timestamp is not added for the transmit and receive frames and the + * Timestamp Generator is also suspended. You need to initialize the Timestamp + * (system time) after enabling this mode. + * + * On the receive side, the MAC processes the 1588 frames only if this bit is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS | 0x0 | Timestamp not added + * ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS | 0x1 | Timestamp added for transmit and receive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA + * + * Timestamp not added + */ +#define ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA + * + * Timestamp added for transmit and receive + */ +#define ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENA_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENA_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENA_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENA field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENA_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSENA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENA_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Timestamp Fine or Coarse Update - tscfupdt + * + * When set, this bit indicates that the system times update should be done using + * the fine update method. When reset, it indicates the system timestamp update + * should be done using the Coarse method. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------- + * ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE | 0x0 | Timestamp Coarse + * ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE | 0x1 | Timestamp Fine + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT + * + * Timestamp Coarse + */ +#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT + * + * Timestamp Fine + */ +#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Timestamp Initialize - tsinit + * + * When set, the system time is initialized (overwritten) with the value specified + * in the Register 452 (System Time - Seconds Update Register) and Register 453 + * (System Time - Nanoseconds Update Register). + * + * This bit should be read zero before updating it. This bit is reset when the + * initialization is complete. The Timestamp Higher Word register can only be + * initialized. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT | 0x0 | Timestamp not initialized (overwritten) by + * : | | values in Register 452 and Register 453 + * ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT | 0x1 | Timestamp initialized (overwritten) by values in + * : | | Register 452 and Register 453 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT + * + * Timestamp not initialized (overwritten) by values in Register 452 and Register + * 453 + */ +#define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT + * + * Timestamp initialized (overwritten) by values in Register 452 and Register 453 + */ +#define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSINIT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSINIT_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSINIT_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSINIT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSINIT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSINIT field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSINIT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSINIT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timestamp Update - tsupdt + * + * When set, the system time is updated (added or subtracted) with the value + * specified in Register 452 (System Time - Seconds Update Register) and Register + * 453 (System Time - Nanoseconds Update Register). + * + * This bit should be read zero before updating it. This bit is reset when the + * update is completed in hardware. The Timestamp Higher Word register is not + * updated. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED | 0x0 | Timestamp not updated (added or subtracted) with + * : | | values in Register 452 and Register 453 + * ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED | 0x1 | Timestamp updated (added or subtracted) with + * : | | values in Register 452 and Register 453 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT + * + * Timestamp not updated (added or subtracted) with values in Register 452 and + * Register 453 + */ +#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT + * + * Timestamp updated (added or subtracted) with values in Register 452 and Register + * 453 + */ +#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSUPDT field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Timestamp Interrupt Trigger Enable - tstrig + * + * When set, the timestamp interrupt is generated when the System Time becomes + * greater than the value written in the Target Time register. This bit is reset + * after the generation of the Timestamp Trigger Interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------ + * ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN | 0x0 | Timestamp not generated + * ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN | 0x1 | Timestamp generated + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG + * + * Timestamp not generated + */ +#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG + * + * Timestamp generated + */ +#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSTRIG field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Addend Reg Update - tsaddreg + * + * When set, the content of the Timestamp Addend register is updated in the PTP + * block for fine correction. This is cleared when the update is completed. This + * register bit should be zero before setting it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:----------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED | 0x0 | Timestamp Addend register is not updated + * ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED | 0x1 | Timestamp Addend register is updated + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG + * + * Timestamp Addend register is not updated + */ +#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG + * + * Timestamp Addend register is updated + */ +#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_MSB 5 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSADDREG field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Enable Timestamp for All Frames - tsenall + * + * When set, the timestamp snapshot is enabled for all frames received by the MAC. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD | 0x0 | Timestamp snapshot disabled + * ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END | 0x1 | Timestamp snapshot enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL + * + * Timestamp snapshot disabled + */ +#define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL + * + * Timestamp snapshot enabled + */ +#define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENALL_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENALL_MSB 8 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENALL_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENALL_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENALL_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENALL field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENALL_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSENALL register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Timestamp Digital or Binary Rollover Control - tsctrlssr + * + * When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that + * is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When + * reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second + * increment has to be programmed correctly depending on the PTP reference clock + * frequency and the value of this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:------------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX | 0x0 | Timestamp Low register rolls over at 0x7FFF_FFFF + * ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS | 0x1 | Timestamp Low register rolls over at 1ns + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR + * + * Timestamp Low register rolls over at 0x7FFF_FFFF + */ +#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR + * + * Timestamp Low register rolls over at 1ns + */ +#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_MSB 9 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Enable PTP packet Processing for Version 2 Format - tsver2ena + * + * When set, the PTP packets are processed using the 1588 version 2 format. + * Otherwise, the PTP packets are processed using the version 1 format. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 | 0x0 | PTP packets processed with 1588 version 1 format + * ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 | 0x1 | PTP packets processed with 1588 version 2 format + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA + * + * PTP packets processed with 1588 version 1 format + */ +#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA + * + * PTP packets processed with 1588 version 2 format + */ +#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_MSB 10 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Enable Processing of PTP over Ethernet Frames - tsipena + * + * When set, the MAC receiver processes the PTP packets encapsulated directly in + * the Ethernet frames. When this bit is clear, the MAC ignores the PTP over + * Ethernet packets. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP | 0x0 | Don't process PTP packets in Ethernet frames + * ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP | 0x1 | Process PTP packets in Ethernet frames + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA + * + * Don't process PTP packets in Ethernet frames + */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA + * + * Process PTP packets in Ethernet frames + */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_MSB 11 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET_MSK 0x00000800 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPENA field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Enable Processing of PTP Frames Sent Over IPv6-UDP - tsipv6ena + * + * When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 + * packets. When this bit is clear, the MAC ignores the PTP transported over UDP- + * IPv6 packets. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP | 0x0 | Don't process PTP packets in UDP over IPv6 + * ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP | 0x1 | Process PTP packets in UDP over IPv6 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA + * + * Don't process PTP packets in UDP over IPv6 + */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA + * + * Process PTP packets in UDP over IPv6 + */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_MSB 12 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET_MSK 0x00001000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_CLR_MSK 0xffffefff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Enable Processing of PTP Frames Sent over IPv4-UDP - tsipv4ena + * + * When set, the MAC receiver processes the PTP packets encapsulated in UDP over + * IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over + * UDP-IPv4 packets. This bit is set by default. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP | 0x0 | Don't process PTP packets in UDP over IPv4 + * ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP | 0x1 | Process PTP packets in UDP over IPv4 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA + * + * Don't process PTP packets in UDP over IPv4 + */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA + * + * Process PTP packets in UDP over IPv4 + */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_MSB 13 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_RESET 0x1 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Enable Timestamp Snapshot for Event Messages - tsevntena + * + * When set, the timestamp snapshot is taken only for event messages (SYNC, + * Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for + * all messages except Announce, Management, and Signaling. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD | 0x0 | Timestamp snapshot disabled for event messages + * ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END | 0x1 | Timestamp snapshot only for event messages + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA + * + * Timestamp snapshot disabled for event messages + */ +#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA + * + * Timestamp snapshot only for event messages + */ +#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_MSB 14 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET_MSK 0x00004000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_CLR_MSK 0xffffbfff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Enable Snapshot for Messages Relevant to Master - tsmstrena + * + * When set, the snapshot is taken only for the messages relevant to the master + * node. Otherwise, the snapshot is taken for the messages relevant to the slave + * node. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV | 0x0 | Timestamp snapshot taken for messages relevant + * : | | to slave node + * ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST | 0x1 | Timestamp snapshot taken for messages relevant + * : | | to master node + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA + * + * Timestamp snapshot taken for messages relevant to slave node + */ +#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA + * + * Timestamp snapshot taken for messages relevant to master node + */ +#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Select PTP packets for Taking Snapshots - snaptypsel + * + * These bits along with Bits 15 and 14 decide the set of PTP packet types for + * which snapshot needs to be taken. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */ +#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */ +#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_MSB 17 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */ +#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET_MSK 0x00030000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_CLR_MSK 0xfffcffff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */ +#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Enable MAC address for PTP Frame Filtering - tsenmacaddr + * + * When set, the DA MAC address (that matches any MAC Address register) is used to + * filter the PTP frames when PTP is directly sent over Ethernet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD | 0x0 | DA MAC address doesn't filter PTP frames + * ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END | 0x1 | DA MAC address filters PTP frames + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR + * + * DA MAC address doesn't filter PTP frames + */ +#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR + * + * DA MAC address filters PTP frames + */ +#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_MSB 18 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Auxiliary Snapshot FIFO Clear - atsfc + * + * When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is + * cleared when the pointers are reset and the FIFO is empty. When this bit is + * high, auxiliary snapshots get stored in the FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD | 0x0 | Don't reset Auxiliary Snapshot FIFO pointers + * ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END | 0x1 | Reset Auxiliary Snapshot FIFO pointers + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC + * + * Don't reset Auxiliary Snapshot FIFO pointers + */ +#define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC + * + * Reset Auxiliary Snapshot FIFO pointers + */ +#define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSFC_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSFC_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSFC_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSFC_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSFC_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSFC field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSFC_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_TS_CTL_ATSFC register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Auxiliary Snapshot 0 Enable - atsen0 + * + * This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is + * set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When + * this bit is reset, the events on this input are ignored. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD | 0x0 | Auxiliary snapshot of event on ptp_aux_trig_i[0] + * : | | input is disabled. + * ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END | 0x1 | Auxiliary snapshot of event on ptp_aux_trig_i[0] + * : | | input is enabled. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0 + * + * Auxiliary snapshot of event on ptp_aux_trig_i[0] input is disabled. + */ +#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0 + * + * Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. + */ +#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN0 field value from a register. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TS_CTL. + */ +struct ALT_EMAC_GMAC_TS_CTL_s +{ + uint32_t tsena : 1; /* Timestamp Enable */ + uint32_t tscfupdt : 1; /* Timestamp Fine or Coarse Update */ + uint32_t tsinit : 1; /* Timestamp Initialize */ + uint32_t tsupdt : 1; /* Timestamp Update */ + uint32_t tstrig : 1; /* Timestamp Interrupt Trigger Enable */ + uint32_t tsaddreg : 1; /* Addend Reg Update */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t tsenall : 1; /* Enable Timestamp for All Frames */ + uint32_t tsctrlssr : 1; /* Timestamp Digital or Binary Rollover Control */ + uint32_t tsver2ena : 1; /* Enable PTP packet Processing for Version 2 Format */ + uint32_t tsipena : 1; /* Enable Processing of PTP over Ethernet Frames */ + uint32_t tsipv6ena : 1; /* Enable Processing of PTP Frames Sent Over IPv6-UDP */ + uint32_t tsipv4ena : 1; /* Enable Processing of PTP Frames Sent over IPv4-UDP */ + uint32_t tsevntena : 1; /* Enable Timestamp Snapshot for Event Messages */ + uint32_t tsmstrena : 1; /* Enable Snapshot for Messages Relevant to Master */ + uint32_t snaptypsel : 2; /* Select PTP packets for Taking Snapshots */ + uint32_t tsenmacaddr : 1; /* Enable MAC address for PTP Frame Filtering */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t atsfc : 1; /* Auxiliary Snapshot FIFO Clear */ + uint32_t atsen0 : 1; /* Auxiliary Snapshot 0 Enable */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TS_CTL. */ +typedef volatile struct ALT_EMAC_GMAC_TS_CTL_s ALT_EMAC_GMAC_TS_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TS_CTL register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TS_CTL_OFST 0x700 +/* The address of the ALT_EMAC_GMAC_TS_CTL register. */ +#define ALT_EMAC_GMAC_TS_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_CTL_OFST)) + +/* + * Register : Register 449 (Sub-Second Increment Register) - Sub_Second_Increment + * + * In the Coarse Update mode (TSCFUPDT bit in Register 448), the value in this + * register is added to the system time every clock cycle of clk_ptp_ref_i. In the + * Fine Update mode, the value in this register is added to the system time + * whenever the Accumulator gets an overflow. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [7:0] | RW | 0x0 | Sub-second Increment Value + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Sub-second Increment Value - ssinc + * + * The value programmed in this field is accumulated every clock cycle (of + * clk_ptp_i) with the contents of the sub-second register. For example, when PTP + * clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System + * Time-Nanoseconds register has an accuracy of 1 ns (TSCTRLSSR bit is set). When + * TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In + * this case, you should program a value of 43 (0x2B) that is derived by + * 20ns/0.465. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */ +#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */ +#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_MSB 7 +/* The width in bits of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */ +#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_WIDTH 8 +/* The mask used to set the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value. */ +#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET_MSK 0x000000ff +/* The mask used to clear the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value. */ +#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_CLR_MSK 0xffffff00 +/* The reset value of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */ +#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC field value from a register. */ +#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_SUB_SEC_INCREMENT. + */ +struct ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s +{ + uint32_t ssinc : 8; /* Sub-second Increment Value */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_SUB_SEC_INCREMENT. */ +typedef volatile struct ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s ALT_EMAC_GMAC_SUB_SEC_INCREMENT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register from the beginning of the component. */ +#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST 0x704 +/* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register. */ +#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST)) + +/* + * Register : Register 450 (System Time - Seconds Register) - System_Time_Seconds + * + * The System Time -Seconds register, along with System-TimeNanoseconds register, + * indicates the current value of the system time maintained by the MAC. Though it + * is updated on a continuous basis, there is some delay from the actual time + * because of clock domain transfer latencies (from clk_ptp_ref_i to l3_sp_clk). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | R | 0x0 | Timestamp Second + * + */ +/* + * Field : Timestamp Second - tss + * + * The value in this field indicates the current value in seconds of the System + * Time maintained by the MAC. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS field value from a register. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS. + */ +struct ALT_EMAC_GMAC_SYS_TIME_SECS_s +{ + const uint32_t tss : 32; /* Timestamp Second */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS. */ +typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_SECS_s ALT_EMAC_GMAC_SYS_TIME_SECS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_SECS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_OFST 0x708 +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_SECS_OFST)) + +/* + * Register : Register 451 (System Time - Nanoseconds Register) - System_Time_Nanoseconds + * + * The value in this field has the sub second representation of time, with an + * accuracy of 0.46 ns. When TSCTRLSSR is set, each bit represents 1 ns and the + * maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [30:0] | R | 0x0 | Timestamp Sub Seconds + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timestamp Sub Seconds - tsss + * + * The value in this field has the sub second representation of time, with an + * accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp + * Control Register), each bit represents 1 ns and the maximum value is + * 0x3B9A_C9FF, after which it rolls-over to zero. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_WIDTH 31 +/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_SET_MSK 0x7fffffff +/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_CLR_MSK 0x80000000 +/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS field value from a register. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_GET(value) (((value) & 0x7fffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_SET(value) (((value) << 0) & 0x7fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS. + */ +struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_s +{ + const uint32_t tsss : 31; /* Timestamp Sub Seconds */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS. */ +typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_s ALT_EMAC_GMAC_SYS_TIME_NANOSECS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_OFST 0x70c +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_NANOSECS_OFST)) + +/* + * Register : Register 452 (System Time - Seconds Update Register) - System_Time_Seconds_Update + * + * The System Time - Seconds Update register, along with the System Time - + * Nanoseconds Update register, initializes or updates the system time maintained + * by the MAC. You must write both of these registers before setting the TSINIT or + * TSUPDT bits in the Timestamp Control register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [31:0] | RW | 0x0 | Timestamp Second + * + */ +/* + * Field : Timestamp Second - tss + * + * The value in this field indicates the time in seconds to be initialized or added + * to the system time. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS field value from a register. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE. + */ +struct ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_s +{ + uint32_t tss : 32; /* Timestamp Second */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE. */ +typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_s ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register from the beginning of the component. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_OFST 0x710 +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register. */ +#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_OFST)) + +/* + * Register : Register 453 (System Time - Nanoseconds Update Register) - System_Time_Nanoseconds_Update + * + * Update system time + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [30:0] | RW | 0x0 | Timestamp Sub Second + * [31] | RW | 0x0 | Add or subtract time + * + */ +/* + * Field : Timestamp Sub Second - tsss + * + * The value in this field has the sub second representation of time, with an + * accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp + * Control Register), each bit represents 1 ns and the programmed value should not + * exceed 0x3B9A_C9FF. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_WIDTH 31 +/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_SET_MSK 0x7fffffff +/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_CLR_MSK 0x80000000 +/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS field value from a register. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_GET(value) (((value) & 0x7fffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_SET(value) (((value) << 0) & 0x7fffffff) + +/* + * Field : Add or subtract time - addsub + * + * When this bit is set, the time value is subtracted with the contents of the + * update register. When this bit is reset, the time value is added with the + * contents of the update register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:---------------------------------- + * ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_DISD | 0x0 | Add Time Value from update reg + * ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_END | 0x1 | Subtract Time Value of update reg + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB + * + * Add Time Value from update reg + */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB + * + * Subtract Time Value of update reg + */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB field value from a register. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE. + */ +struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_s +{ + uint32_t tsss : 31; /* Timestamp Sub Second */ + uint32_t addsub : 1; /* Add or subtract time */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE. */ +typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_s ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register from the beginning of the component. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_OFST 0x714 +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register. */ +#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_OFST)) + +/* + * Register : Register 454 (Timestamp Addend Register) - Timestamp_Addend + * + * This register value is used only when the system time is configured for Fine + * Update mode (TSCFUPDT bit in Register 448). This register content is added to a + * 32-bit accumulator in every clock cycle (of clk_ptp_ref_i) and the system time + * is updated whenever the accumulator overflows. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [31:0] | RW | 0x0 | Timestamp Addend Register + * + */ +/* + * Field : Timestamp Addend Register - tsar + * + * This field indicates the 32-bit time value to be added to the Accumulator + * register to achieve time synchronization. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */ +#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */ +#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */ +#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value. */ +#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value. */ +#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */ +#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_ADDEND_TSAR field value from a register. */ +#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TS_ADDEND. + */ +struct ALT_EMAC_GMAC_TS_ADDEND_s +{ + uint32_t tsar : 32; /* Timestamp Addend Register */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TS_ADDEND. */ +typedef volatile struct ALT_EMAC_GMAC_TS_ADDEND_s ALT_EMAC_GMAC_TS_ADDEND_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TS_ADDEND register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TS_ADDEND_OFST 0x718 +/* The address of the ALT_EMAC_GMAC_TS_ADDEND register. */ +#define ALT_EMAC_GMAC_TS_ADDEND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_ADDEND_OFST)) + +/* + * Register : Register 455 (Target Time Seconds Register) - Target_Time_Seconds + * + * The Target Time Seconds register, along with Target Time Nanoseconds register, + * is used to schedule an interrupt event (Register 458[1] when Advanced + * Timestamping is enabled; otherwise, TS interrupt bit in Register14[9]) when the + * system time exceeds the value programmed in these registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [31:0] | RW | 0x0 | Target Time Seconds Register + * + */ +/* + * Field : Target Time Seconds Register - tstr + * + * This register stores the time in seconds. When the timestamp value matches or + * exceeds both Target Timestamp registers, then based on Bits [6:5] of Register + * 459 (PPS Control Register), the MAC starts or stops the PPS signal output and + * generates an interrupt (if enabled). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value. */ +#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value. */ +#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR field value from a register. */ +#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TGT_TIME_SECS. + */ +struct ALT_EMAC_GMAC_TGT_TIME_SECS_s +{ + uint32_t tstr : 32; /* Target Time Seconds Register */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TGT_TIME_SECS. */ +typedef volatile struct ALT_EMAC_GMAC_TGT_TIME_SECS_s ALT_EMAC_GMAC_TGT_TIME_SECS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TGT_TIME_SECS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TGT_TIME_SECS_OFST 0x71c +/* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register. */ +#define ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TGT_TIME_SECS_OFST)) + +/* + * Register : Register 456 (Target Time Nanoseconds Register) - Target_Time_Nanoseconds + * + * Target time + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [30:0] | RW | 0x0 | Target Timestamp Low Register + * [31] | R | 0x0 | Target Time Register Busy + * + */ +/* + * Field : Target Timestamp Low Register - ttslo + * + * This register stores the time in (signed) nanoseconds. When the value of the + * timestamp matches the both Target Timestamp registers, then based on the + * TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC + * starts or stops the PPS signal output and generates an interrupt (if enabled). + * + * This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Timestamp + * control register. The actual start or stop time of the PPS signal output may + * have an error margin up to one unit of sub-second increment value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_WIDTH 31 +/* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET_MSK 0x7fffffff +/* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_CLR_MSK 0x80000000 +/* The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO field value from a register. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_GET(value) (((value) & 0x7fffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET(value) (((value) << 0) & 0x7fffffff) + +/* + * Field : Target Time Register Busy - trgtbusy + * + * The MAC sets this bit when the PPSCMD field (Bits[3:0]) in Register 459 (PPS + * Control Register) is programmed to 010 or 011. Programming the PPSCMD field to + * 010 or 011, instructs the MAC to synchronize the Target Time Registers to the + * PTP clock domain. + * + * The MAC clears this bit after synchronizing the Target Time Registers to the PTP + * clock domain The application must not update the Target Time Registers when this + * bit is read as 1. Otherwise, the synchronization of the previous programmed time + * gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second + * Output feature is not selected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY field value from a register. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TGT_TIME_NANOSECS. + */ +struct ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s +{ + uint32_t ttslo : 31; /* Target Timestamp Low Register */ + const uint32_t trgtbusy : 1; /* Target Time Register Busy */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TGT_TIME_NANOSECS. */ +typedef volatile struct ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s ALT_EMAC_GMAC_TGT_TIME_NANOSECS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST 0x720 +/* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register. */ +#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST)) + +/* + * Register : Register 457 (System Time - Higher Word Seconds Register) - System_Time_Higher_Word_Seconds + * + * System time higher word + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------- + * [15:0] | RW | 0x0 | Timestamp Higher Word Register + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timestamp Higher Word Register - tshwr + * + * This field contains the most significant 16-bits of the timestamp seconds value. + * The register is directly written to initialize the value. This register is + * incremented when there is an overflow from the 32-bits of the System Time - + * Seconds register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value. */ +#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */ +#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR field value from a register. */ +#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS. + */ +struct ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_s +{ + uint32_t tshwr : 16; /* Timestamp Higher Word Register */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS. */ +typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_s ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_OFST 0x724 +/* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register. */ +#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_OFST)) + +/* + * Register : Register 458 (Timestamp Status Register) - Timestamp_Status + * + * Timestamp status. All bits except Bits[27:25] get cleared when the host reads + * this register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------ + * [0] | R | 0x0 | Timestamp Seconds Overflow + * [1] | R | 0x0 | Timestamp Target Time Reached + * [2] | R | 0x0 | Auxiliary Timestamp Trigger Snapshot + * [3] | R | 0x0 | Timestamp Target Time Error + * [15:4] | ??? | 0x0 | *UNDEFINED* + * [19:16] | R | 0x0 | Auxiliary Timestamp Snapshot Trigger Identifier + * [23:20] | ??? | 0x0 | *UNDEFINED* + * [24] | R | 0x0 | Auxiliary Timestamp Snapshot Trigger Missed + * [29:25] | R | 0x0 | Number of Auxiliary Timestamp Snapshots + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timestamp Seconds Overflow - tssovf + * + * When set, this bit indicates that the seconds value of the timestamp (when + * supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------- + * ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_RST | 0x0 | No Overflow + * ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_SET | 0x1 | Seconds Overflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSSOVF + * + * No Overflow + */ +#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_RST 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSSOVF + * + * Seconds Overflow + */ +#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_MSB 0 +/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_STAT_TSSOVF field value from a register. */ +#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Timestamp Target Time Reached - tstargt + * + * When set, this bit indicates that the value of system time is greater or equal + * to the value specified in the Register 455 (Target Time Seconds Register) and + * Register 456 (Target Time Nanoseconds Register). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_RST | 0x0 | System Time + * ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_SET | 0x1 | System Time is >= Reg455 and Reg456 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTARGT + * + * System Time + */ +#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_RST 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTARGT + * + * System Time is >= Reg455 and Reg456 + */ +#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_MSB 1 +/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_STAT_TSTARGT field value from a register. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Auxiliary Timestamp Trigger Snapshot - auxtstrig + * + * This bit is set high when the auxiliary snapshot is written to the FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_RST | 0x0 | System Time + * ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_SET | 0x1 | System Time is >= Reg455 and Reg456 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG + * + * System Time + */ +#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_RST 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG + * + * System Time is >= Reg455 and Reg456 + */ +#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */ +#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */ +#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_MSB 2 +/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */ +#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */ +#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG field value from a register. */ +#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timestamp Target Time Error - tstrgterr + * + * This bit is set when the target time, being programmed in Target Time Registers, + * is already elapsed. This bit is cleared when read by the application. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:--------------------------------------- + * ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_RST | 0x0 | When Read resets + * ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_SET | 0x1 | Target Time Elapsed -Reg455 and Reg456 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTRGTERR + * + * When Read resets + */ +#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_RST 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTRGTERR + * + * Target Time Elapsed -Reg455 and Reg456 + */ +#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR field value from a register. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Auxiliary Timestamp Snapshot Trigger Identifier - atsstn + * + * These bits identify the Auxiliary trigger inputs for which the timestamp + * available in the Auxiliary Snapshot Register is applicable. When more than one + * bit is set at the same time, it means that corresponding auxiliary triggers were + * sampled at the same clock. These bits are applicable only if the number of + * Auxiliary snapshots is more than one. One bit is assigned for each trigger as + * shown in the following list: + * + * * Bit 16: Auxiliary trigger 0 + * + * * Bit 17: Auxiliary trigger 1 + * + * * Bit 18: Auxiliary trigger 2 + * + * * Bit 19: Auxiliary trigger 3 + * + * The software can read this register to find the triggers that are set when the + * timestamp is taken. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_MSB 19 +/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_WIDTH 4 +/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_SET_MSK 0x000f0000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_CLR_MSK 0xfff0ffff +/* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSSTN field value from a register. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_GET(value) (((value) & 0x000f0000) >> 16) +/* Produces a ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_SET(value) (((value) << 16) & 0x000f0000) + +/* + * Field : Auxiliary Timestamp Snapshot Trigger Missed - atsstm + * + * This bit is set when the Auxiliary timestamp snapshot FIFO is full and external + * trigger was set. This indicates that the latest snapshot is not stored in the + * FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_NOTFULL | 0x0 | Not Active + * ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_FULL | 0x1 | Aux timestamp snapshot full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_ATSSTM + * + * Not Active + */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_ATSSTM + * + * Aux timestamp snapshot full + */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSSTM field value from a register. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Number of Auxiliary Timestamp Snapshots - atsns + * + * This field indicates the number of Snapshots available in the FIFO. A value of + * 16 (equal to the depth of the FIFO) indicates that the Auxiliary Snapshot FIFO + * is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO + * clear bit is set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSNS_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSNS_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSNS_WIDTH 5 +/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSNS register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSNS_SET_MSK 0x3e000000 +/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSNS register field value. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSNS_CLR_MSK 0xc1ffffff +/* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSNS_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSNS field value from a register. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSNS_GET(value) (((value) & 0x3e000000) >> 25) +/* Produces a ALT_EMAC_GMAC_TS_STAT_ATSNS register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_TS_STAT_ATSNS_SET(value) (((value) << 25) & 0x3e000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_TS_STAT. + */ +struct ALT_EMAC_GMAC_TS_STAT_s +{ + const uint32_t tssovf : 1; /* Timestamp Seconds Overflow */ + const uint32_t tstargt : 1; /* Timestamp Target Time Reached */ + const uint32_t auxtstrig : 1; /* Auxiliary Timestamp Trigger Snapshot */ + const uint32_t tstrgterr : 1; /* Timestamp Target Time Error */ + uint32_t : 12; /* *UNDEFINED* */ + const uint32_t atsstn : 4; /* Auxiliary Timestamp Snapshot Trigger Identifier */ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t atsstm : 1; /* Auxiliary Timestamp Snapshot Trigger Missed */ + const uint32_t atsns : 5; /* Number of Auxiliary Timestamp Snapshots */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_TS_STAT. */ +typedef volatile struct ALT_EMAC_GMAC_TS_STAT_s ALT_EMAC_GMAC_TS_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_TS_STAT register from the beginning of the component. */ +#define ALT_EMAC_GMAC_TS_STAT_OFST 0x728 +/* The address of the ALT_EMAC_GMAC_TS_STAT register. */ +#define ALT_EMAC_GMAC_TS_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_STAT_OFST)) + +/* + * Register : Register 459 (PPS Control Register) - PPS_Control + * + * Controls timestamp Pulse-Per-Second output + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------ + * [3:0] | RW | 0x0 | PPSCTRL0 or PPSCMD0 + * [4] | RW | 0x0 | Flexible PPS Output Mode Enable + * [6:5] | RW | 0x0 | Target Time Register Mode for PPS0 Output + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : PPSCTRL0 or PPSCMD0 - ppsctrl_ppscmd + * + * PPSCTRL0: PPS0 Output Frequency Control + * + * This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The + * default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width + * clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a + * generated clock of following frequencies: + * + * * 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. + * + * * 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. + * + * * 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. + * + * * 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. + * + * * ... + * + * * 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 + * KHz. + * + * Note: + * + * In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 + * percent with these frequencies. + * + * In the digital rollover mode, the PPS output frequency is an average number. The + * actual clock is of different frequency that gets synchronized every second. For + * example: + * + * - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high + * period of 463 ms + * + * - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: + * + * * One clock of 50 percent duty cycle and 537 ms period + * + * * Second clock of 463 ms period (268 ms low and 195 ms high) + * + * - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: + * + * * Three clocks of 50 percent duty cycle and 268 ms period + * + * * Fourth clock of 195 ms period (134 ms low and 61 ms high) + * + * This behavior is because of the non-linear toggling of bits in the digital + * rollover mode in Register 451 (System Time - Nanoseconds Register). + * + * Flexible PPS0 Output (ptp_pps_o[0]) Control + * + * Programming these bits with a non-zero value instructs the MAC to initiate an + * event. Once the command is transferred or synchronized to the PTP clock domain, + * these bits get cleared automatically. The Software should ensure that these bits + * are programmed only when they are all-zero. The following list describes the + * values of PPSCMD0: + * + * - 0000: No Command + * + * - 0001: START Single Pulse + * + * This command generates single pulse rising at the start point defined in Target + * Time Registers (register 455 and 456) and of a duration defined in the PPS0 + * Width Register. + * + * - 0010: START Pulse Train + * + * This command generates the train of pulses rising at the start point defined in + * the Target Time Registers and of a duration defined in the PPS0 Width Register + * and repeated at interval defined in the PPS Interval Register. By default, the + * PPS pulse train is free-running unless stopped by 'STOP Pulse train at time' or + * 'STOP Pulse Train immediately' commands. + * + * - 0011: Cancel START + * + * This command cancels the START Single Pulse and START Pulse Train commands if + * the system time has not crossed the programmed start time. + * + * - 0100: STOP Pulse train at time + * + * This command stops the train of pulses initiated by the START Pulse Train + * command (PPSCMD = 0010) after the time programmed in the Target Time registers + * elapses. + * + * - 0101: STOP Pulse Train immediately + * + * This command immediately stops the train of pulses initiated by the START Pulse + * Train command (PPSCMD = 0010). + * + * - 0110: Cancel STOP Pulse train + * + * This command cancels the STOP pulse train at time command if the programmed stop + * time has not elapsed. The PPS pulse train becomes free-running on the successful + * execution of this command. + * + * - 0111-1111: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_MSB 3 +/* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_WIDTH 4 +/* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET_MSK 0x0000000f +/* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD field value from a register. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Flexible PPS Output Mode Enable - ppsen0 + * + * When set low, Bits[3:0] function as PPSCTRL (backward compatible). When set + * high, Bits[3:0] function as PPSCMD. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------- + * ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL | 0x0 | Bits[3:0] function as ppsctrl0 + * ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD | 0x1 | Bits[3:0] function as ppscmd + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_PPSEN0 + * + * Bits[3:0] function as ppsctrl0 + */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_PPSEN0 + * + * Bits[3:0] function as ppscmd + */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_MSB 4 +/* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 field value from a register. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Target Time Register Mode for PPS0 Output - trgtmodsel0 + * + * This field indicates the Target Time registers (register 455 and 456) mode for + * PPS0 output signal + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:--------------------------------------------- + * ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY | 0x0 | Target Time regs generate interrupt event. + * ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0 | 0x2 | Target Time gen. interr event and sig pps0 + * ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER | 0x3 | Target Time No inter just start and stop sig + * : | | pps0 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 + * + * Target Time regs generate interrupt event. + */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 + * + * Target Time gen. interr event and sig pps0 + */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0 0x2 +/* + * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 + * + * Target Time No inter just start and stop sig pps0 + */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_MSB 6 +/* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_WIDTH 2 +/* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value. */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET_MSK 0x00000060 +/* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value. */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_CLR_MSK 0xffffff9f +/* The reset value of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 field value from a register. */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_GET(value) (((value) & 0x00000060) >> 5) +/* Produces a ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET(value) (((value) << 5) & 0x00000060) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_PPS_CTL. + */ +struct ALT_EMAC_GMAC_PPS_CTL_s +{ + uint32_t ppsctrl_ppscmd : 4; /* PPSCTRL0 or PPSCMD0 */ + uint32_t ppsen0 : 1; /* Flexible PPS Output Mode Enable */ + uint32_t trgtmodsel0 : 2; /* Target Time Register Mode for PPS0 Output */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_PPS_CTL. */ +typedef volatile struct ALT_EMAC_GMAC_PPS_CTL_s ALT_EMAC_GMAC_PPS_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_PPS_CTL register from the beginning of the component. */ +#define ALT_EMAC_GMAC_PPS_CTL_OFST 0x72c +/* The address of the ALT_EMAC_GMAC_PPS_CTL register. */ +#define ALT_EMAC_GMAC_PPS_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS_CTL_OFST)) + +/* + * Register : Register 460 (Auxiliary Timestamp - Nanoseconds Register) - Auxiliary_Timestamp_Nanoseconds + * + * This register, along with Register 461 (Auxiliary Timestamp Seconds Register), + * gives the 64-bit timestamp stored as auxiliary snapshot. The two registers + * together form the read port of a 64-bit wide FIFO with a depth of 16. Multiple + * snapshots can be stored in this FIFO. The ATSNS bits in the Timestamp Status + * register indicate the fill-level of this FIFO. The top of the FIFO is removed + * only when the last byte of Register 461 (Auxiliary Timestamp - Seconds Register) + * is read. In the little-endian mode, this means when Bits[31:24] are read. In + * big-endian mode, it corresponds to the reading of Bits[7:0] of Register 461 + * (Auxiliary Timestamp - Seconds Register). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------- + * [30:0] | R | 0x0 | ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : auxtslo + * + * Contains the lower 32 bits (nano-seconds field) of the auxiliary timestamp. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */ +#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */ +#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */ +#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_WIDTH 31 +/* The mask used to set the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value. */ +#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_SET_MSK 0x7fffffff +/* The mask used to clear the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value. */ +#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_CLR_MSK 0x80000000 +/* The reset value of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */ +#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO field value from a register. */ +#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_GET(value) (((value) & 0x7fffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_SET(value) (((value) << 0) & 0x7fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_AUX_TS_NANOSECS. + */ +struct ALT_EMAC_GMAC_AUX_TS_NANOSECS_s +{ + const uint32_t auxtslo : 31; /* ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_AUX_TS_NANOSECS. */ +typedef volatile struct ALT_EMAC_GMAC_AUX_TS_NANOSECS_s ALT_EMAC_GMAC_AUX_TS_NANOSECS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_OFST 0x730 +/* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register. */ +#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_AUX_TS_NANOSECS_OFST)) + +/* + * Register : Register 461 (Auxiliary Timestamp - Seconds Register) - Auxiliary_Timestamp_Seconds + * + * Contains the higher 32 bits (Seconds field) of the auxiliary timestamp. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | R | 0x0 | ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI + * + */ +/* + * Field : auxtshi + * + * Contains the higher 32 bits (Seconds field) of the auxiliary timestamp. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */ +#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */ +#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */ +#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value. */ +#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value. */ +#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */ +#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI field value from a register. */ +#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_AUX_TS_SECS. + */ +struct ALT_EMAC_GMAC_AUX_TS_SECS_s +{ + const uint32_t auxtshi : 32; /* ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_AUX_TS_SECS. */ +typedef volatile struct ALT_EMAC_GMAC_AUX_TS_SECS_s ALT_EMAC_GMAC_AUX_TS_SECS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_AUX_TS_SECS register from the beginning of the component. */ +#define ALT_EMAC_GMAC_AUX_TS_SECS_OFST 0x734 +/* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register. */ +#define ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_AUX_TS_SECS_OFST)) + +/* + * Register : Register 472 (PPS0 Interval Register) - PPS0_Interval + * + * The PPS0 Interval register contains the number of units of sub-second increment + * value between the rising edges of PPS0 signal output (ptp_pps_o[0]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [31:0] | RW | 0x0 | PPS0 Output Signal Interval + * + */ +/* + * Field : PPS0 Output Signal Interval - ppsint + * + * These bits store the interval between the rising edges of PPS0 signal output in + * terms of units of sub-second increment value. + * + * You need to program one value less than the required interval. For example, if + * the PTP reference clock is 50 MHz (period of 20ns), and desired interval between + * rising edges of PPS0 signal output is 100ns (that is, five units of sub-second + * increment value), then you should program value 4 (5 -1) in this register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */ +#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */ +#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */ +#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value. */ +#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value. */ +#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */ +#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT field value from a register. */ +#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_PPS0_INTERVAL. + */ +struct ALT_EMAC_GMAC_PPS0_INTERVAL_s +{ + uint32_t ppsint : 32; /* PPS0 Output Signal Interval */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_PPS0_INTERVAL. */ +typedef volatile struct ALT_EMAC_GMAC_PPS0_INTERVAL_s ALT_EMAC_GMAC_PPS0_INTERVAL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_PPS0_INTERVAL register from the beginning of the component. */ +#define ALT_EMAC_GMAC_PPS0_INTERVAL_OFST 0x760 +/* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register. */ +#define ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS0_INTERVAL_OFST)) + +/* + * Register : Register 473 (PPS0 Width Register) - PPS0_Width + * + * The PPS0 Width register contains the number of units of sub-second increment + * value between the rising and corresponding falling edges of the PPS0 signal + * output (ptp_pps_o[0]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | PPS0 Output Signal Width + * + */ +/* + * Field : PPS0 Output Signal Width - ppswidth + * + * These bits store the width between the rising edge and corresponding falling + * edge of the PPS0 signal output in terms of units of sub-second increment value. + * + * You need to program one value less than the required interval. For example, if + * PTP reference clock is 50 MHz (period of 20ns), and desired width between the + * rising and corresponding falling edges of PPS0 signal output is 80ns (that is, + * four units of sub-second increment value), then you should program value 3 (4-1) + * in this register. + * + * Note: + * + * The value programmed in this register must be lesser than the value programmed + * in Register 472 (PPS0 Interval Register). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */ +#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */ +#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */ +#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value. */ +#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value. */ +#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */ +#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH field value from a register. */ +#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_PPS0_WIDTH. + */ +struct ALT_EMAC_GMAC_PPS0_WIDTH_s +{ + uint32_t ppswidth : 32; /* PPS0 Output Signal Width */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_PPS0_WIDTH. */ +typedef volatile struct ALT_EMAC_GMAC_PPS0_WIDTH_s ALT_EMAC_GMAC_PPS0_WIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_PPS0_WIDTH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_PPS0_WIDTH_OFST 0x764 +/* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register. */ +#define ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS0_WIDTH_OFST)) + +/* + * Register : Register 512 (MAC Address16 High Register) - MAC_Address16_High + * + * The MAC Address16 High register holds the upper 16 bits of the 17th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address16 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address16 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address16 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 17th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address16 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address16 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address16 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address16 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address16 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address16 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address16[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address16[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 17th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR16_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR16_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address16 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR16_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR16_HIGH_s ALT_EMAC_GMAC_MAC_ADDR16_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_OFST 0x800 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR16_HIGH_OFST)) + +/* + * Register : Register 513 (MAC Address16 Low Register) - MAC_Address16_Low + * + * The MAC Address16 Low register holds the lower 32 bits of the 17th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address16 [31:0] + * + */ +/* + * Field : MAC Address16 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 17th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR16_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR16_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address16 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR16_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR16_LOW_s ALT_EMAC_GMAC_MAC_ADDR16_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_OFST 0x804 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR16_LOW_OFST)) + +/* + * Register : Register 514 (MAC Address17 High Register) - MAC_Address17_High + * + * The MAC Address17 High register holds the upper 16 bits of the 18th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address17 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address17 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address17 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 18th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address17 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address17 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address17 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address17 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address17 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address17 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address17[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address17[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 18th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR17_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR17_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address17 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR17_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR17_HIGH_s ALT_EMAC_GMAC_MAC_ADDR17_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_OFST 0x808 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR17_HIGH_OFST)) + +/* + * Register : Register 515 (MAC Address17 Low Register) - MAC_Address17_Low + * + * The MAC Address17 Low register holds the lower 32 bits of the 18th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address17 [31:0] + * + */ +/* + * Field : MAC Address17 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 18th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR17_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR17_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address17 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR17_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR17_LOW_s ALT_EMAC_GMAC_MAC_ADDR17_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_OFST 0x80c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR17_LOW_OFST)) + +/* + * Register : Register 516 (MAC Address18 High Register) - MAC_Address18_High + * + * The MAC Address18 High register holds the upper 16 bits of the 19th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address18 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address18 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address18 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 19th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address18 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address18 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address18 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address18 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address18 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address18 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address18[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address18[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 19th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR18_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR18_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address18 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR18_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR18_HIGH_s ALT_EMAC_GMAC_MAC_ADDR18_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_OFST 0x810 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR18_HIGH_OFST)) + +/* + * Register : Register 517 (MAC Address18 Low Register) - MAC_Address18_Low + * + * The MAC Address18 Low register holds the lower 32 bits of the 19th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address18 [31:0] + * + */ +/* + * Field : MAC Address18 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 19th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR18_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR18_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address18 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR18_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR18_LOW_s ALT_EMAC_GMAC_MAC_ADDR18_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_OFST 0x814 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR18_LOW_OFST)) + +/* + * Register : Register 518 (MAC Address19 High Register) - MAC_Address19_High + * + * The MAC Address19 High register holds the upper 16 bits of the 20th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address19 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address19 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address19 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 20th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address19 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address19 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address19 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address19 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address19 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address19 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address19[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address19[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 20th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR19_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR19_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address19 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR19_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR19_HIGH_s ALT_EMAC_GMAC_MAC_ADDR19_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_OFST 0x818 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR19_HIGH_OFST)) + +/* + * Register : Register 519 (MAC Address19 Low Register) - MAC_Address19_Low + * + * The MAC Address19 Low register holds the lower 32 bits of the 20th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address19 [31:0] + * + */ +/* + * Field : MAC Address19 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 20th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR19_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR19_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address19 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR19_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR19_LOW_s ALT_EMAC_GMAC_MAC_ADDR19_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_OFST 0x81c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR19_LOW_OFST)) + +/* + * Register : Register 520 (MAC Address20 High Register) - MAC_Address20_High + * + * The MAC Address20 High register holds the upper 16 bits of the 21th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address20 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address20 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address20 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 21th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address20 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address20 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address20 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address20 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address20 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address20 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address20[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address20[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 21th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR20_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR20_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address20 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR20_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR20_HIGH_s ALT_EMAC_GMAC_MAC_ADDR20_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_OFST 0x820 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR20_HIGH_OFST)) + +/* + * Register : Register 521 (MAC Address20 Low Register) - MAC_Address20_Low + * + * The MAC Address20 Low register holds the lower 32 bits of the 21th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address20 [31:0] + * + */ +/* + * Field : MAC Address20 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 21th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR20_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR20_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address20 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR20_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR20_LOW_s ALT_EMAC_GMAC_MAC_ADDR20_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_OFST 0x824 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR20_LOW_OFST)) + +/* + * Register : Register 522 (MAC Address21 High Register) - MAC_Address21_High + * + * The MAC Address21 High register holds the upper 16 bits of the 22th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address21 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address21 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address21 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 22th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address21 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address21 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address21 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address21 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address21 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address21 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address21[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address21[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 22th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR21_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR21_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address21 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR21_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR21_HIGH_s ALT_EMAC_GMAC_MAC_ADDR21_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_OFST 0x828 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR21_HIGH_OFST)) + +/* + * Register : Register 523 (MAC Address21 Low Register) - MAC_Address21_Low + * + * The MAC Address21 Low register holds the lower 32 bits of the 22th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address21 [31:0] + * + */ +/* + * Field : MAC Address21 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 22th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR21_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR21_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address21 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR21_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR21_LOW_s ALT_EMAC_GMAC_MAC_ADDR21_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_OFST 0x82c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR21_LOW_OFST)) + +/* + * Register : Register 524 (MAC Address22 High Register) - MAC_Address22_High + * + * The MAC Address22 High register holds the upper 16 bits of the 23th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address22 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address22 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address22 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 23th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address22 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address22 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address22 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address22 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address22 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address22 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address22[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address22[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 23th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR22_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR22_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address22 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR22_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR22_HIGH_s ALT_EMAC_GMAC_MAC_ADDR22_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_OFST 0x830 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR22_HIGH_OFST)) + +/* + * Register : Register 525 (MAC Address22 Low Register) - MAC_Address22_Low + * + * The MAC Address22 Low register holds the lower 32 bits of the 23th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address22 [31:0] + * + */ +/* + * Field : MAC Address22 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 23th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR22_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR22_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address22 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR22_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR22_LOW_s ALT_EMAC_GMAC_MAC_ADDR22_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_OFST 0x834 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR22_LOW_OFST)) + +/* + * Register : Register 526 (MAC Address23 High Register) - MAC_Address23_High + * + * The MAC Address23 High register holds the upper 16 bits of the 24th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address23 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address23 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address23 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 24th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address23 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address23 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address23 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address23 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address23 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address23 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address23[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address23[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 24th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR23_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR23_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address23 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR23_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR23_HIGH_s ALT_EMAC_GMAC_MAC_ADDR23_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_OFST 0x838 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR23_HIGH_OFST)) + +/* + * Register : Register 527 (MAC Address23 Low Register) - MAC_Address23_Low + * + * The MAC Address23 Low register holds the lower 32 bits of the 24th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address23 [31:0] + * + */ +/* + * Field : MAC Address23 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 24th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR23_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR23_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address23 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR23_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR23_LOW_s ALT_EMAC_GMAC_MAC_ADDR23_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_OFST 0x83c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR23_LOW_OFST)) + +/* + * Register : Register 528 (MAC Address24 High Register) - MAC_Address24_High + * + * The MAC Address24 High register holds the upper 16 bits of the 25th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address24 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address24 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address24 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 25th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address24 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address24 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address24 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address24 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address24 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address24 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address24[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address24[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 25th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR24_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR24_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address24 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR24_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR24_HIGH_s ALT_EMAC_GMAC_MAC_ADDR24_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_OFST 0x840 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR24_HIGH_OFST)) + +/* + * Register : Register 529 (MAC Address24 Low Register) - MAC_Address24_Low + * + * The MAC Address24 Low register holds the lower 32 bits of the 25th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address24 [31:0] + * + */ +/* + * Field : MAC Address24 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 25th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR24_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR24_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address24 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR24_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR24_LOW_s ALT_EMAC_GMAC_MAC_ADDR24_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_OFST 0x844 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR24_LOW_OFST)) + +/* + * Register : Register 530 (MAC Address25 High Register) - MAC_Address25_High + * + * The MAC Address25 High register holds the upper 16 bits of the 26th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address25 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address25 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address25 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 26th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address25 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address25 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address25 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address25 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address25 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address25 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address25[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address25[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 26th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR25_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR25_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address25 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR25_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR25_HIGH_s ALT_EMAC_GMAC_MAC_ADDR25_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_OFST 0x848 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR25_HIGH_OFST)) + +/* + * Register : Register 531 (MAC Address25 Low Register) - MAC_Address25_Low + * + * The MAC Address25 Low register holds the lower 32 bits of the 26th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address25 [31:0] + * + */ +/* + * Field : MAC Address25 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 26th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR25_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR25_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address25 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR25_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR25_LOW_s ALT_EMAC_GMAC_MAC_ADDR25_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_OFST 0x84c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR25_LOW_OFST)) + +/* + * Register : Register 532 (MAC Address26 High Register) - MAC_Address26_High + * + * The MAC Address26 High register holds the upper 16 bits of the 27th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address26 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address26 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address26 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 27th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address26 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address26 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address26 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address26 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address26 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address26 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address26[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address26[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 27th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR26_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR26_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address26 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR26_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR26_HIGH_s ALT_EMAC_GMAC_MAC_ADDR26_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_OFST 0x850 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR26_HIGH_OFST)) + +/* + * Register : Register 533 (MAC Address26 Low Register) - MAC_Address26_Low + * + * The MAC Address26 Low register holds the lower 32 bits of the 27th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address26 [31:0] + * + */ +/* + * Field : MAC Address26 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 27th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR26_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR26_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address26 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR26_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR26_LOW_s ALT_EMAC_GMAC_MAC_ADDR26_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_OFST 0x854 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR26_LOW_OFST)) + +/* + * Register : Register 534 (MAC Address27 High Register) - MAC_Address27_High + * + * The MAC Address27 High register holds the upper 16 bits of the 28th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address27 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address27 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address27 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 28th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address27 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address27 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address27 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address27 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address27 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address27 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address27[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address27[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 28th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR27_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR27_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address27 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR27_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR27_HIGH_s ALT_EMAC_GMAC_MAC_ADDR27_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_OFST 0x858 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR27_HIGH_OFST)) + +/* + * Register : Register 535 (MAC Address27 Low Register) - MAC_Address27_Low + * + * The MAC Address27 Low register holds the lower 32 bits of the 28th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address27 [31:0] + * + */ +/* + * Field : MAC Address27 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 28th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR27_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR27_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address27 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR27_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR27_LOW_s ALT_EMAC_GMAC_MAC_ADDR27_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_OFST 0x85c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR27_LOW_OFST)) + +/* + * Register : Register 536 (MAC Address28 High Register) - MAC_Address28_High + * + * The MAC Address28 High register holds the upper 16 bits of the 29th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address28 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address28 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address28 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 29th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address28 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address28 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address28 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address28 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address28 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address28 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address28[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address28[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 29th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR28_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR28_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address28 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR28_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR28_HIGH_s ALT_EMAC_GMAC_MAC_ADDR28_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_OFST 0x860 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR28_HIGH_OFST)) + +/* + * Register : Register 537 (MAC Address28 Low Register) - MAC_Address28_Low + * + * The MAC Address28 Low register holds the lower 32 bits of the 29th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address28 [31:0] + * + */ +/* + * Field : MAC Address28 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 29th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR28_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR28_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address28 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR28_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR28_LOW_s ALT_EMAC_GMAC_MAC_ADDR28_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_OFST 0x864 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR28_LOW_OFST)) + +/* + * Register : Register 538 (MAC Address29 High Register) - MAC_Address29_High + * + * The MAC Address29 High register holds the upper 16 bits of the 30th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address29 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address29 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address29 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 30th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address29 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address29 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address29 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address29 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address29 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address29 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address29[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address29[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 30th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR29_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR29_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address29 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR29_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR29_HIGH_s ALT_EMAC_GMAC_MAC_ADDR29_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_OFST 0x868 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR29_HIGH_OFST)) + +/* + * Register : Register 539 (MAC Address29 Low Register) - MAC_Address29_Low + * + * The MAC Address29 Low register holds the lower 32 bits of the 30th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address29 [31:0] + * + */ +/* + * Field : MAC Address29 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 30th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR29_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR29_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address29 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR29_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR29_LOW_s ALT_EMAC_GMAC_MAC_ADDR29_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_OFST 0x86c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR29_LOW_OFST)) + +/* + * Register : Register 540 (MAC Address30 High Register) - MAC_Address30_High + * + * The MAC Address30 High register holds the upper 16 bits of the 31th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address30 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address30 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address30 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 31th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address30 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address30 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address30 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address30 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address30 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address30 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address30[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address30[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 31th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR30_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR30_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address30 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR30_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR30_HIGH_s ALT_EMAC_GMAC_MAC_ADDR30_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_OFST 0x870 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR30_HIGH_OFST)) + +/* + * Register : Register 541 (MAC Address30 Low Register) - MAC_Address30_Low + * + * The MAC Address30 Low register holds the lower 32 bits of the 31th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address30 [31:0] + * + */ +/* + * Field : MAC Address30 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 31th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR30_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR30_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address30 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR30_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR30_LOW_s ALT_EMAC_GMAC_MAC_ADDR30_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_OFST 0x874 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR30_LOW_OFST)) + +/* + * Register : Register 542 (MAC Address31 High Register) - MAC_Address31_High + * + * The MAC Address31 High register holds the upper 16 bits of the 32th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address31 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address31 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address31 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 32th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address31 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address31 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address31 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address31 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address31 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address31 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address31[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address31[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 32th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR31_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR31_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address31 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR31_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR31_HIGH_s ALT_EMAC_GMAC_MAC_ADDR31_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_OFST 0x878 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR31_HIGH_OFST)) + +/* + * Register : Register 543 (MAC Address31 Low Register) - MAC_Address31_Low + * + * The MAC Address31 Low register holds the lower 32 bits of the 32th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address31 [31:0] + * + */ +/* + * Field : MAC Address31 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 32th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR31_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR31_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address31 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR31_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR31_LOW_s ALT_EMAC_GMAC_MAC_ADDR31_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_OFST 0x87c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR31_LOW_OFST)) + +/* + * Register : Register 544 (MAC Address32 High Register) - MAC_Address32_High + * + * The MAC Address32 High register holds the upper 16 bits of the 33th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address32 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address32 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address32 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 33th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address32 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address32 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address32 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address32 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address32 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address32 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address32[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address32[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 33th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR32_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR32_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address32 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR32_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR32_HIGH_s ALT_EMAC_GMAC_MAC_ADDR32_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_OFST 0x880 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR32_HIGH_OFST)) + +/* + * Register : Register 545 (MAC Address32 Low Register) - MAC_Address32_Low + * + * The MAC Address32 Low register holds the lower 32 bits of the 33th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address32 [31:0] + * + */ +/* + * Field : MAC Address32 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 33th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR32_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR32_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address32 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR32_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR32_LOW_s ALT_EMAC_GMAC_MAC_ADDR32_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_OFST 0x884 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR32_LOW_OFST)) + +/* + * Register : Register 546 (MAC Address33 High Register) - MAC_Address33_High + * + * The MAC Address33 High register holds the upper 16 bits of the 34th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address33 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address33 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address33 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 34th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address33 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address33 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address33 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address33 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address33 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address33 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address33[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address33[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 34th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR33_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR33_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address33 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR33_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR33_HIGH_s ALT_EMAC_GMAC_MAC_ADDR33_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_OFST 0x888 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR33_HIGH_OFST)) + +/* + * Register : Register 547 (MAC Address33 Low Register) - MAC_Address33_Low + * + * The MAC Address33 Low register holds the lower 32 bits of the 34th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address33 [31:0] + * + */ +/* + * Field : MAC Address33 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 34th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR33_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR33_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address33 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR33_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR33_LOW_s ALT_EMAC_GMAC_MAC_ADDR33_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_OFST 0x88c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR33_LOW_OFST)) + +/* + * Register : Register 548 (MAC Address34 High Register) - MAC_Address34_High + * + * The MAC Address34 High register holds the upper 16 bits of the 35th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address34 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address34 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address34 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 35th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address34 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address34 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address34 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address34 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address34 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address34 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address34[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address34[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 35th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR34_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR34_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address34 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR34_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR34_HIGH_s ALT_EMAC_GMAC_MAC_ADDR34_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_OFST 0x890 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR34_HIGH_OFST)) + +/* + * Register : Register 549 (MAC Address34 Low Register) - MAC_Address34_Low + * + * The MAC Address34 Low register holds the lower 32 bits of the 35th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address34 [31:0] + * + */ +/* + * Field : MAC Address34 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 35th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR34_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR34_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address34 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR34_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR34_LOW_s ALT_EMAC_GMAC_MAC_ADDR34_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_OFST 0x894 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR34_LOW_OFST)) + +/* + * Register : Register 550 (MAC Address35 High Register) - MAC_Address35_High + * + * The MAC Address35 High register holds the upper 16 bits of the 36th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address35 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address35 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address35 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 36th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address35 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address35 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address35 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address35 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address35 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address35 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address35[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address35[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 36th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR35_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR35_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address35 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR35_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR35_HIGH_s ALT_EMAC_GMAC_MAC_ADDR35_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_OFST 0x898 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR35_HIGH_OFST)) + +/* + * Register : Register 551 (MAC Address35 Low Register) - MAC_Address35_Low + * + * The MAC Address35 Low register holds the lower 32 bits of the 36th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address35 [31:0] + * + */ +/* + * Field : MAC Address35 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 36th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR35_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR35_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address35 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR35_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR35_LOW_s ALT_EMAC_GMAC_MAC_ADDR35_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_OFST 0x89c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR35_LOW_OFST)) + +/* + * Register : Register 552 (MAC Address36 High Register) - MAC_Address36_High + * + * The MAC Address36 High register holds the upper 16 bits of the 37th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address36 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address36 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address36 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 37th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address36 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address36 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address36 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address36 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address36 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address36 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address36[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address36[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 37th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR36_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR36_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address36 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR36_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR36_HIGH_s ALT_EMAC_GMAC_MAC_ADDR36_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_OFST 0x8a0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR36_HIGH_OFST)) + +/* + * Register : Register 553 (MAC Address36 Low Register) - MAC_Address36_Low + * + * The MAC Address36 Low register holds the lower 32 bits of the 37th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address36 [31:0] + * + */ +/* + * Field : MAC Address36 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 37th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR36_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR36_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address36 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR36_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR36_LOW_s ALT_EMAC_GMAC_MAC_ADDR36_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_OFST 0x8a4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR36_LOW_OFST)) + +/* + * Register : Register 554 (MAC Address37 High Register) - MAC_Address37_High + * + * The MAC Address37 High register holds the upper 16 bits of the 38th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address37 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address37 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address37 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 38th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address37 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address37 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address37 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address37 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address37 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address37 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address37[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address37[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 38th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR37_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR37_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address37 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR37_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR37_HIGH_s ALT_EMAC_GMAC_MAC_ADDR37_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_OFST 0x8a8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR37_HIGH_OFST)) + +/* + * Register : Register 555 (MAC Address37 Low Register) - MAC_Address37_Low + * + * The MAC Address37 Low register holds the lower 32 bits of the 38th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address37 [31:0] + * + */ +/* + * Field : MAC Address37 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 38th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR37_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR37_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address37 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR37_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR37_LOW_s ALT_EMAC_GMAC_MAC_ADDR37_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_OFST 0x8ac +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR37_LOW_OFST)) + +/* + * Register : Register 556 (MAC Address38 High Register) - MAC_Address38_High + * + * The MAC Address38 High register holds the upper 16 bits of the 39th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address38 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address38 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address38 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 39th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address38 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address38 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address38 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address38 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address38 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address38 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address38[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address38[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 39th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR38_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR38_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address38 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR38_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR38_HIGH_s ALT_EMAC_GMAC_MAC_ADDR38_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_OFST 0x8b0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR38_HIGH_OFST)) + +/* + * Register : Register 557 (MAC Address38 Low Register) - MAC_Address38_Low + * + * The MAC Address38 Low register holds the lower 32 bits of the 39th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address38 [31:0] + * + */ +/* + * Field : MAC Address38 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 39th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR38_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR38_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address38 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR38_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR38_LOW_s ALT_EMAC_GMAC_MAC_ADDR38_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_OFST 0x8b4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR38_LOW_OFST)) + +/* + * Register : Register 558 (MAC Address39 High Register) - MAC_Address39_High + * + * The MAC Address39 High register holds the upper 16 bits of the 40th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address39 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address39 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address39 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 40th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address39 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address39 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address39 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address39 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address39 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address39 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address39[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address39[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 40th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR39_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR39_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address39 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR39_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR39_HIGH_s ALT_EMAC_GMAC_MAC_ADDR39_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_OFST 0x8b8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR39_HIGH_OFST)) + +/* + * Register : Register 559 (MAC Address39 Low Register) - MAC_Address39_Low + * + * The MAC Address39 Low register holds the lower 32 bits of the 40th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address39 [31:0] + * + */ +/* + * Field : MAC Address39 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 40th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR39_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR39_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address39 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR39_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR39_LOW_s ALT_EMAC_GMAC_MAC_ADDR39_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_OFST 0x8bc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR39_LOW_OFST)) + +/* + * Register : Register 560 (MAC Address40 High Register) - MAC_Address40_High + * + * The MAC Address40 High register holds the upper 16 bits of the 41th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address40 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address40 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address40 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 41th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address40 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address40 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address40 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address40 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address40 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address40 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address40[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address40[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 41th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR40_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR40_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address40 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR40_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR40_HIGH_s ALT_EMAC_GMAC_MAC_ADDR40_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_OFST 0x8c0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR40_HIGH_OFST)) + +/* + * Register : Register 561 (MAC Address40 Low Register) - MAC_Address40_Low + * + * The MAC Address40 Low register holds the lower 32 bits of the 41th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address40 [31:0] + * + */ +/* + * Field : MAC Address40 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 41th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR40_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR40_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address40 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR40_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR40_LOW_s ALT_EMAC_GMAC_MAC_ADDR40_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_OFST 0x8c4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR40_LOW_OFST)) + +/* + * Register : Register 562 (MAC Address41 High Register) - MAC_Address41_High + * + * The MAC Address41 High register holds the upper 16 bits of the 42th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address41 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address41 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address41 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 42th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address41 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address41 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address41 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address41 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address41 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address41 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address41[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address41[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 42th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR41_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR41_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address41 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR41_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR41_HIGH_s ALT_EMAC_GMAC_MAC_ADDR41_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_OFST 0x8c8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR41_HIGH_OFST)) + +/* + * Register : Register 563 (MAC Address41 Low Register) - MAC_Address41_Low + * + * The MAC Address41 Low register holds the lower 32 bits of the 42th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address41 [31:0] + * + */ +/* + * Field : MAC Address41 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 42th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR41_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR41_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address41 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR41_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR41_LOW_s ALT_EMAC_GMAC_MAC_ADDR41_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_OFST 0x8cc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR41_LOW_OFST)) + +/* + * Register : Register 564 (MAC Address42 High Register) - MAC_Address42_High + * + * The MAC Address42 High register holds the upper 16 bits of the 43th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address42 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address42 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address42 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 43th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address42 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address42 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address42 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address42 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address42 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address42 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address42[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address42[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 43th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR42_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR42_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address42 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR42_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR42_HIGH_s ALT_EMAC_GMAC_MAC_ADDR42_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_OFST 0x8d0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR42_HIGH_OFST)) + +/* + * Register : Register 565 (MAC Address42 Low Register) - MAC_Address42_Low + * + * The MAC Address42 Low register holds the lower 32 bits of the 43th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address42 [31:0] + * + */ +/* + * Field : MAC Address42 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 43th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR42_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR42_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address42 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR42_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR42_LOW_s ALT_EMAC_GMAC_MAC_ADDR42_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_OFST 0x8d4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR42_LOW_OFST)) + +/* + * Register : Register 566 (MAC Address43 High Register) - MAC_Address43_High + * + * The MAC Address43 High register holds the upper 16 bits of the 44th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address43 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address43 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address43 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 44th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address43 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address43 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address43 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address43 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address43 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address43 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address43[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address43[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 44th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR43_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR43_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address43 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR43_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR43_HIGH_s ALT_EMAC_GMAC_MAC_ADDR43_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_OFST 0x8d8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR43_HIGH_OFST)) + +/* + * Register : Register 567 (MAC Address43 Low Register) - MAC_Address43_Low + * + * The MAC Address43 Low register holds the lower 32 bits of the 44th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address43 [31:0] + * + */ +/* + * Field : MAC Address43 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 44th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR43_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR43_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address43 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR43_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR43_LOW_s ALT_EMAC_GMAC_MAC_ADDR43_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_OFST 0x8dc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR43_LOW_OFST)) + +/* + * Register : Register 568 (MAC Address44 High Register) - MAC_Address44_High + * + * The MAC Address44 High register holds the upper 16 bits of the 45th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address44 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address44 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address44 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 45th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address44 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address44 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address44 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address44 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address44 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address44 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address44[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address44[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 45th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR44_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR44_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address44 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR44_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR44_HIGH_s ALT_EMAC_GMAC_MAC_ADDR44_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_OFST 0x8e0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR44_HIGH_OFST)) + +/* + * Register : Register 569 (MAC Address44 Low Register) - MAC_Address44_Low + * + * The MAC Address44 Low register holds the lower 32 bits of the 45th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address44 [31:0] + * + */ +/* + * Field : MAC Address44 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 45th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR44_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR44_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address44 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR44_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR44_LOW_s ALT_EMAC_GMAC_MAC_ADDR44_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_OFST 0x8e4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR44_LOW_OFST)) + +/* + * Register : Register 570 (MAC Address45 High Register) - MAC_Address45_High + * + * The MAC Address45 High register holds the upper 16 bits of the 46th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address45 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address45 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address45 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 46th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address45 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address45 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address45 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address45 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address45 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address45 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address45[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address45[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 46th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR45_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR45_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address45 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR45_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR45_HIGH_s ALT_EMAC_GMAC_MAC_ADDR45_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_OFST 0x8e8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR45_HIGH_OFST)) + +/* + * Register : Register 571 (MAC Address45 Low Register) - MAC_Address45_Low + * + * The MAC Address45 Low register holds the lower 32 bits of the 46th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address45 [31:0] + * + */ +/* + * Field : MAC Address45 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 46th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR45_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR45_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address45 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR45_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR45_LOW_s ALT_EMAC_GMAC_MAC_ADDR45_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_OFST 0x8ec +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR45_LOW_OFST)) + +/* + * Register : Register 572 (MAC Address46 High Register) - MAC_Address46_High + * + * The MAC Address46 High register holds the upper 16 bits of the 47th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address46 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address46 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address46 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 47th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address46 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address46 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address46 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address46 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address46 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address46 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address46[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address46[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 47th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR46_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR46_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address46 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR46_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR46_HIGH_s ALT_EMAC_GMAC_MAC_ADDR46_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_OFST 0x8f0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR46_HIGH_OFST)) + +/* + * Register : Register 573 (MAC Address46 Low Register) - MAC_Address46_Low + * + * The MAC Address46 Low register holds the lower 32 bits of the 47th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address46 [31:0] + * + */ +/* + * Field : MAC Address46 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 47th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR46_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR46_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address46 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR46_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR46_LOW_s ALT_EMAC_GMAC_MAC_ADDR46_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_OFST 0x8f4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR46_LOW_OFST)) + +/* + * Register : Register 574 (MAC Address47 High Register) - MAC_Address47_High + * + * The MAC Address47 High register holds the upper 16 bits of the 48th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address47 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address47 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address47 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 48th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address47 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address47 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address47 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address47 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address47 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address47 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address47[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address47[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 48th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR47_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR47_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address47 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR47_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR47_HIGH_s ALT_EMAC_GMAC_MAC_ADDR47_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_OFST 0x8f8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR47_HIGH_OFST)) + +/* + * Register : Register 575 (MAC Address47 Low Register) - MAC_Address47_Low + * + * The MAC Address47 Low register holds the lower 32 bits of the 48th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address47 [31:0] + * + */ +/* + * Field : MAC Address47 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 48th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR47_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR47_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address47 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR47_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR47_LOW_s ALT_EMAC_GMAC_MAC_ADDR47_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_OFST 0x8fc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR47_LOW_OFST)) + +/* + * Register : Register 576 (MAC Address48 High Register) - MAC_Address48_High + * + * The MAC Address48 High register holds the upper 16 bits of the 49th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address48 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address48 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address48 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 49th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address48 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address48 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address48 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address48 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address48 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address48 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address48[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address48[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 49th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR48_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR48_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address48 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR48_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR48_HIGH_s ALT_EMAC_GMAC_MAC_ADDR48_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_OFST 0x900 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR48_HIGH_OFST)) + +/* + * Register : Register 577 (MAC Address48 Low Register) - MAC_Address48_Low + * + * The MAC Address48 Low register holds the lower 32 bits of the 49th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address48 [31:0] + * + */ +/* + * Field : MAC Address48 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 49th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR48_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR48_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address48 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR48_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR48_LOW_s ALT_EMAC_GMAC_MAC_ADDR48_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_OFST 0x904 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR48_LOW_OFST)) + +/* + * Register : Register 578 (MAC Address49 High Register) - MAC_Address49_High + * + * The MAC Address49 High register holds the upper 16 bits of the 50th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address49 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address49 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address49 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 50th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address49 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address49 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address49 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address49 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address49 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address49 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address49[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address49[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 50th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR49_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR49_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address49 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR49_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR49_HIGH_s ALT_EMAC_GMAC_MAC_ADDR49_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_OFST 0x908 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR49_HIGH_OFST)) + +/* + * Register : Register 579 (MAC Address49 Low Register) - MAC_Address49_Low + * + * The MAC Address49 Low register holds the lower 32 bits of the 50th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address49 [31:0] + * + */ +/* + * Field : MAC Address49 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 50th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR49_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR49_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address49 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR49_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR49_LOW_s ALT_EMAC_GMAC_MAC_ADDR49_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_OFST 0x90c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR49_LOW_OFST)) + +/* + * Register : Register 580 (MAC Address50 High Register) - MAC_Address50_High + * + * The MAC Address50 High register holds the upper 16 bits of the 51th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address50 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address50 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address50 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 51th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address50 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address50 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address50 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address50 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address50 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address50 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address50[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address50[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 51th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR50_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR50_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address50 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR50_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR50_HIGH_s ALT_EMAC_GMAC_MAC_ADDR50_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_OFST 0x910 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR50_HIGH_OFST)) + +/* + * Register : Register 581 (MAC Address50 Low Register) - MAC_Address50_Low + * + * The MAC Address50 Low register holds the lower 32 bits of the 51th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address50 [31:0] + * + */ +/* + * Field : MAC Address50 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 51th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR50_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR50_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address50 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR50_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR50_LOW_s ALT_EMAC_GMAC_MAC_ADDR50_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_OFST 0x914 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR50_LOW_OFST)) + +/* + * Register : Register 582 (MAC Address51 High Register) - MAC_Address51_High + * + * The MAC Address51 High register holds the upper 16 bits of the 52th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address51 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address51 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address51 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 52th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address51 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address51 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address51 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address51 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address51 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address51 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address51[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address51[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 52th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR51_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR51_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address51 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR51_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR51_HIGH_s ALT_EMAC_GMAC_MAC_ADDR51_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_OFST 0x918 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR51_HIGH_OFST)) + +/* + * Register : Register 583 (MAC Address51 Low Register) - MAC_Address51_Low + * + * The MAC Address51 Low register holds the lower 32 bits of the 52th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address51 [31:0] + * + */ +/* + * Field : MAC Address51 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 52th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR51_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR51_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address51 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR51_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR51_LOW_s ALT_EMAC_GMAC_MAC_ADDR51_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_OFST 0x91c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR51_LOW_OFST)) + +/* + * Register : Register 584 (MAC Address52 High Register) - MAC_Address52_High + * + * The MAC Address52 High register holds the upper 16 bits of the 53th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address52 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address52 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address52 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 53th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address52 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address52 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address52 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address52 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address52 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address52 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address52[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address52[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 53th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR52_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR52_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address52 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR52_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR52_HIGH_s ALT_EMAC_GMAC_MAC_ADDR52_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_OFST 0x920 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR52_HIGH_OFST)) + +/* + * Register : Register 585 (MAC Address52 Low Register) - MAC_Address52_Low + * + * The MAC Address52 Low register holds the lower 32 bits of the 53th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address52 [31:0] + * + */ +/* + * Field : MAC Address52 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 53th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR52_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR52_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address52 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR52_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR52_LOW_s ALT_EMAC_GMAC_MAC_ADDR52_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_OFST 0x924 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR52_LOW_OFST)) + +/* + * Register : Register 586 (MAC Address53 High Register) - MAC_Address53_High + * + * The MAC Address53 High register holds the upper 16 bits of the 54th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address53 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address53 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address53 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 54th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address53 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address53 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address53 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address53 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address53 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address53 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address53[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address53[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 54th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR53_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR53_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address53 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR53_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR53_HIGH_s ALT_EMAC_GMAC_MAC_ADDR53_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_OFST 0x928 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR53_HIGH_OFST)) + +/* + * Register : Register 587 (MAC Address53 Low Register) - MAC_Address53_Low + * + * The MAC Address53 Low register holds the lower 32 bits of the 54th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address53 [31:0] + * + */ +/* + * Field : MAC Address53 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 54th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR53_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR53_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address53 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR53_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR53_LOW_s ALT_EMAC_GMAC_MAC_ADDR53_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_OFST 0x92c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR53_LOW_OFST)) + +/* + * Register : Register 588 (MAC Address54 High Register) - MAC_Address54_High + * + * The MAC Address54 High register holds the upper 16 bits of the 55th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address54 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address54 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address54 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 55th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address54 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address54 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address54 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address54 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address54 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address54 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address54[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address54[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 55th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR54_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR54_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address54 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR54_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR54_HIGH_s ALT_EMAC_GMAC_MAC_ADDR54_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_OFST 0x930 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR54_HIGH_OFST)) + +/* + * Register : Register 589 (MAC Address54 Low Register) - MAC_Address54_Low + * + * The MAC Address54 Low register holds the lower 32 bits of the 55th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address54 [31:0] + * + */ +/* + * Field : MAC Address54 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 55th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR54_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR54_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address54 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR54_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR54_LOW_s ALT_EMAC_GMAC_MAC_ADDR54_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_OFST 0x934 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR54_LOW_OFST)) + +/* + * Register : Register 590 (MAC Address55 High Register) - MAC_Address55_High + * + * The MAC Address55 High register holds the upper 16 bits of the 56th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address55 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address55 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address55 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 56th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address55 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address55 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address55 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address55 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address55 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address55 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address55[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address55[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 56th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR55_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR55_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address55 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR55_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR55_HIGH_s ALT_EMAC_GMAC_MAC_ADDR55_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_OFST 0x938 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR55_HIGH_OFST)) + +/* + * Register : Register 591 (MAC Address55 Low Register) - MAC_Address55_Low + * + * The MAC Address55 Low register holds the lower 32 bits of the 56th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address55 [31:0] + * + */ +/* + * Field : MAC Address55 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 56th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR55_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR55_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address55 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR55_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR55_LOW_s ALT_EMAC_GMAC_MAC_ADDR55_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_OFST 0x93c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR55_LOW_OFST)) + +/* + * Register : Register 592 (MAC Address56 High Register) - MAC_Address56_High + * + * The MAC Address56 High register holds the upper 16 bits of the 57th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address56 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address56 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address56 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 57th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address56 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address56 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address56 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address56 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address56 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address56 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address56[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address56[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 57th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR56_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR56_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address56 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR56_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR56_HIGH_s ALT_EMAC_GMAC_MAC_ADDR56_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_OFST 0x940 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR56_HIGH_OFST)) + +/* + * Register : Register 593 (MAC Address56 Low Register) - MAC_Address56_Low + * + * The MAC Address56 Low register holds the lower 32 bits of the 57th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address56 [31:0] + * + */ +/* + * Field : MAC Address56 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 57th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR56_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR56_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address56 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR56_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR56_LOW_s ALT_EMAC_GMAC_MAC_ADDR56_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_OFST 0x944 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR56_LOW_OFST)) + +/* + * Register : Register 594 (MAC Address57 High Register) - MAC_Address57_High + * + * The MAC Address57 High register holds the upper 16 bits of the 58th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address57 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address57 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address57 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 58th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address57 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address57 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address57 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address57 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address57 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address57 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address57[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address57[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 58th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR57_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR57_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address57 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR57_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR57_HIGH_s ALT_EMAC_GMAC_MAC_ADDR57_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_OFST 0x948 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR57_HIGH_OFST)) + +/* + * Register : Register 595 (MAC Address57 Low Register) - MAC_Address57_Low + * + * The MAC Address57 Low register holds the lower 32 bits of the 58th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address57 [31:0] + * + */ +/* + * Field : MAC Address57 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 58th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR57_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR57_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address57 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR57_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR57_LOW_s ALT_EMAC_GMAC_MAC_ADDR57_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_OFST 0x94c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR57_LOW_OFST)) + +/* + * Register : Register 596 (MAC Address58 High Register) - MAC_Address58_High + * + * The MAC Address58 High register holds the upper 16 bits of the 59th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address58 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address58 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address58 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 59th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address58 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address58 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address58 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address58 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address58 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address58 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address58[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address58[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 59th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR58_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR58_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address58 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR58_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR58_HIGH_s ALT_EMAC_GMAC_MAC_ADDR58_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_OFST 0x950 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR58_HIGH_OFST)) + +/* + * Register : Register 597 (MAC Address58 Low Register) - MAC_Address58_Low + * + * The MAC Address58 Low register holds the lower 32 bits of the 59th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address58 [31:0] + * + */ +/* + * Field : MAC Address58 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 59th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR58_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR58_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address58 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR58_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR58_LOW_s ALT_EMAC_GMAC_MAC_ADDR58_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_OFST 0x954 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR58_LOW_OFST)) + +/* + * Register : Register 598 (MAC Address59 High Register) - MAC_Address59_High + * + * The MAC Address59 High register holds the upper 16 bits of the 60th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address59 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address59 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address59 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 60th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address59 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address59 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address59 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address59 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address59 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address59 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address59[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address59[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 60th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR59_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR59_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address59 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR59_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR59_HIGH_s ALT_EMAC_GMAC_MAC_ADDR59_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_OFST 0x958 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR59_HIGH_OFST)) + +/* + * Register : Register 599 (MAC Address59 Low Register) - MAC_Address59_Low + * + * The MAC Address59 Low register holds the lower 32 bits of the 60th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address59 [31:0] + * + */ +/* + * Field : MAC Address59 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 60th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR59_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR59_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address59 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR59_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR59_LOW_s ALT_EMAC_GMAC_MAC_ADDR59_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_OFST 0x95c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR59_LOW_OFST)) + +/* + * Register : Register 600 (MAC Address60 High Register) - MAC_Address60_High + * + * The MAC Address60 High register holds the upper 16 bits of the 61th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address60 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address60 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address60 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 61th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address60 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address60 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address60 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address60 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address60 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address60 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address60[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address60[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 61th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR60_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR60_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address60 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR60_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR60_HIGH_s ALT_EMAC_GMAC_MAC_ADDR60_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_OFST 0x960 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR60_HIGH_OFST)) + +/* + * Register : Register 601 (MAC Address60 Low Register) - MAC_Address60_Low + * + * The MAC Address60 Low register holds the lower 32 bits of the 61th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address60 [31:0] + * + */ +/* + * Field : MAC Address60 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 61th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR60_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR60_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address60 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR60_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR60_LOW_s ALT_EMAC_GMAC_MAC_ADDR60_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_OFST 0x964 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR60_LOW_OFST)) + +/* + * Register : Register 602 (MAC Address61 High Register) - MAC_Address61_High + * + * The MAC Address61 High register holds the upper 16 bits of the 62th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address61 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address61 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address61 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 62th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address61 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address61 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address61 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address61 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address61 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address61 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address61[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address61[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 62th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR61_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR61_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address61 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR61_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR61_HIGH_s ALT_EMAC_GMAC_MAC_ADDR61_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_OFST 0x968 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR61_HIGH_OFST)) + +/* + * Register : Register 603 (MAC Address61 Low Register) - MAC_Address61_Low + * + * The MAC Address61 Low register holds the lower 32 bits of the 62th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address61 [31:0] + * + */ +/* + * Field : MAC Address61 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 62th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR61_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR61_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address61 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR61_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR61_LOW_s ALT_EMAC_GMAC_MAC_ADDR61_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_OFST 0x96c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR61_LOW_OFST)) + +/* + * Register : Register 604 (MAC Address62 High Register) - MAC_Address62_High + * + * The MAC Address62 High register holds the upper 16 bits of the 63th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address62 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address62 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address62 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 63th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address62 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address62 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address62 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address62 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address62 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address62 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address62[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address62[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 63th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR62_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR62_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address62 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR62_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR62_HIGH_s ALT_EMAC_GMAC_MAC_ADDR62_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_OFST 0x970 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR62_HIGH_OFST)) + +/* + * Register : Register 605 (MAC Address62 Low Register) - MAC_Address62_Low + * + * The MAC Address62 Low register holds the lower 32 bits of the 63th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address62 [31:0] + * + */ +/* + * Field : MAC Address62 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 63th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR62_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR62_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address62 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR62_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR62_LOW_s ALT_EMAC_GMAC_MAC_ADDR62_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_OFST 0x974 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR62_LOW_OFST)) + +/* + * Register : Register 606 (MAC Address63 High Register) - MAC_Address63_High + * + * The MAC Address63 High register holds the upper 16 bits of the 64th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address63 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address63 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address63 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 64th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address63 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address63 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address63 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address63 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address63 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address63 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address63[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address63[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 64th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR63_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR63_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address63 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR63_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR63_HIGH_s ALT_EMAC_GMAC_MAC_ADDR63_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_OFST 0x978 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR63_HIGH_OFST)) + +/* + * Register : Register 607 (MAC Address63 Low Register) - MAC_Address63_Low + * + * The MAC Address63 Low register holds the lower 32 bits of the 64th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address63 [31:0] + * + */ +/* + * Field : MAC Address63 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 64th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR63_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR63_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address63 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR63_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR63_LOW_s ALT_EMAC_GMAC_MAC_ADDR63_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_OFST 0x97c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR63_LOW_OFST)) + +/* + * Register : Register 608 (MAC Address64 High Register) - MAC_Address64_High + * + * The MAC Address64 High register holds the upper 16 bits of the 65th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address64 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address64 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address64 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 65th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address64 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address64 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address64 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address64 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address64 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address64 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address64[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address64[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 65th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR64_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR64_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address64 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR64_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR64_HIGH_s ALT_EMAC_GMAC_MAC_ADDR64_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_OFST 0x980 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR64_HIGH_OFST)) + +/* + * Register : Register 609 (MAC Address64 Low Register) - MAC_Address64_Low + * + * The MAC Address64 Low register holds the lower 32 bits of the 65th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address64 [31:0] + * + */ +/* + * Field : MAC Address64 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 65th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR64_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR64_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address64 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR64_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR64_LOW_s ALT_EMAC_GMAC_MAC_ADDR64_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_OFST 0x984 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR64_LOW_OFST)) + +/* + * Register : Register 610 (MAC Address65 High Register) - MAC_Address65_High + * + * The MAC Address65 High register holds the upper 16 bits of the 66th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address65 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address65 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address65 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 66th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address65 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address65 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address65 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address65 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address65 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address65 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address65[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address65[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 66th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR65_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR65_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address65 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR65_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR65_HIGH_s ALT_EMAC_GMAC_MAC_ADDR65_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_OFST 0x988 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR65_HIGH_OFST)) + +/* + * Register : Register 611 (MAC Address65 Low Register) - MAC_Address65_Low + * + * The MAC Address65 Low register holds the lower 32 bits of the 66th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address65 [31:0] + * + */ +/* + * Field : MAC Address65 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 66th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR65_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR65_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address65 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR65_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR65_LOW_s ALT_EMAC_GMAC_MAC_ADDR65_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_OFST 0x98c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR65_LOW_OFST)) + +/* + * Register : Register 612 (MAC Address66 High Register) - MAC_Address66_High + * + * The MAC Address66 High register holds the upper 16 bits of the 67th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address66 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address66 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address66 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 67th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address66 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address66 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address66 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address66 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address66 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address66 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address66[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address66[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 67th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR66_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR66_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address66 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR66_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR66_HIGH_s ALT_EMAC_GMAC_MAC_ADDR66_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_OFST 0x990 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR66_HIGH_OFST)) + +/* + * Register : Register 613 (MAC Address66 Low Register) - MAC_Address66_Low + * + * The MAC Address66 Low register holds the lower 32 bits of the 67th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address66 [31:0] + * + */ +/* + * Field : MAC Address66 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 67th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR66_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR66_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address66 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR66_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR66_LOW_s ALT_EMAC_GMAC_MAC_ADDR66_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_OFST 0x994 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR66_LOW_OFST)) + +/* + * Register : Register 614 (MAC Address67 High Register) - MAC_Address67_High + * + * The MAC Address67 High register holds the upper 16 bits of the 68th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address67 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address67 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address67 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 68th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address67 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address67 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address67 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address67 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address67 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address67 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address67[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address67[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 68th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR67_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR67_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address67 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR67_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR67_HIGH_s ALT_EMAC_GMAC_MAC_ADDR67_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_OFST 0x998 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR67_HIGH_OFST)) + +/* + * Register : Register 615 (MAC Address67 Low Register) - MAC_Address67_Low + * + * The MAC Address67 Low register holds the lower 32 bits of the 68th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address67 [31:0] + * + */ +/* + * Field : MAC Address67 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 68th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR67_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR67_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address67 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR67_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR67_LOW_s ALT_EMAC_GMAC_MAC_ADDR67_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_OFST 0x99c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR67_LOW_OFST)) + +/* + * Register : Register 616 (MAC Address68 High Register) - MAC_Address68_High + * + * The MAC Address68 High register holds the upper 16 bits of the 69th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address68 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address68 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address68 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 69th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address68 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address68 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address68 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address68 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address68 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address68 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address68[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address68[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 69th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR68_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR68_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address68 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR68_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR68_HIGH_s ALT_EMAC_GMAC_MAC_ADDR68_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_OFST 0x9a0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR68_HIGH_OFST)) + +/* + * Register : Register 617 (MAC Address68 Low Register) - MAC_Address68_Low + * + * The MAC Address68 Low register holds the lower 32 bits of the 69th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address68 [31:0] + * + */ +/* + * Field : MAC Address68 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 69th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR68_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR68_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address68 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR68_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR68_LOW_s ALT_EMAC_GMAC_MAC_ADDR68_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_OFST 0x9a4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR68_LOW_OFST)) + +/* + * Register : Register 618 (MAC Address69 High Register) - MAC_Address69_High + * + * The MAC Address69 High register holds the upper 16 bits of the 70th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address69 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address69 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address69 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 70th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address69 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address69 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address69 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address69 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address69 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address69 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address69[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address69[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 70th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR69_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR69_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address69 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR69_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR69_HIGH_s ALT_EMAC_GMAC_MAC_ADDR69_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_OFST 0x9a8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR69_HIGH_OFST)) + +/* + * Register : Register 619 (MAC Address69 Low Register) - MAC_Address69_Low + * + * The MAC Address69 Low register holds the lower 32 bits of the 70th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address69 [31:0] + * + */ +/* + * Field : MAC Address69 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 70th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR69_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR69_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address69 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR69_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR69_LOW_s ALT_EMAC_GMAC_MAC_ADDR69_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_OFST 0x9ac +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR69_LOW_OFST)) + +/* + * Register : Register 620 (MAC Address70 High Register) - MAC_Address70_High + * + * The MAC Address70 High register holds the upper 16 bits of the 71th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address70 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address70 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address70 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 71th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address70 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address70 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address70 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address70 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address70 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address70 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address70[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address70[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 71th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR70_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR70_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address70 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR70_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR70_HIGH_s ALT_EMAC_GMAC_MAC_ADDR70_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_OFST 0x9b0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR70_HIGH_OFST)) + +/* + * Register : Register 621 (MAC Address70 Low Register) - MAC_Address70_Low + * + * The MAC Address70 Low register holds the lower 32 bits of the 71th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address70 [31:0] + * + */ +/* + * Field : MAC Address70 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 71th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR70_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR70_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address70 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR70_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR70_LOW_s ALT_EMAC_GMAC_MAC_ADDR70_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_OFST 0x9b4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR70_LOW_OFST)) + +/* + * Register : Register 622 (MAC Address71 High Register) - MAC_Address71_High + * + * The MAC Address71 High register holds the upper 16 bits of the 72th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address71 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address71 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address71 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 72th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address71 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address71 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address71 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address71 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address71 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address71 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address71[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address71[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 72th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR71_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR71_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address71 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR71_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR71_HIGH_s ALT_EMAC_GMAC_MAC_ADDR71_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_OFST 0x9b8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR71_HIGH_OFST)) + +/* + * Register : Register 623 (MAC Address71 Low Register) - MAC_Address71_Low + * + * The MAC Address71 Low register holds the lower 32 bits of the 72th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address71 [31:0] + * + */ +/* + * Field : MAC Address71 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 72th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR71_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR71_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address71 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR71_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR71_LOW_s ALT_EMAC_GMAC_MAC_ADDR71_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_OFST 0x9bc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR71_LOW_OFST)) + +/* + * Register : Register 624 (MAC Address72 High Register) - MAC_Address72_High + * + * The MAC Address72 High register holds the upper 16 bits of the 73th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address72 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address72 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address72 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 73th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address72 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address72 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address72 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address72 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address72 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address72 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address72[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address72[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 73th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR72_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR72_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address72 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR72_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR72_HIGH_s ALT_EMAC_GMAC_MAC_ADDR72_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_OFST 0x9c0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR72_HIGH_OFST)) + +/* + * Register : Register 625 (MAC Address72 Low Register) - MAC_Address72_Low + * + * The MAC Address72 Low register holds the lower 32 bits of the 73th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address72 [31:0] + * + */ +/* + * Field : MAC Address72 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 73th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR72_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR72_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address72 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR72_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR72_LOW_s ALT_EMAC_GMAC_MAC_ADDR72_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_OFST 0x9c4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR72_LOW_OFST)) + +/* + * Register : Register 626 (MAC Address73 High Register) - MAC_Address73_High + * + * The MAC Address73 High register holds the upper 16 bits of the 74th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address73 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address73 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address73 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 74th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address73 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address73 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address73 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address73 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address73 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address73 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address73[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address73[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 74th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR73_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR73_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address73 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR73_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR73_HIGH_s ALT_EMAC_GMAC_MAC_ADDR73_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_OFST 0x9c8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR73_HIGH_OFST)) + +/* + * Register : Register 627 (MAC Address73 Low Register) - MAC_Address73_Low + * + * The MAC Address73 Low register holds the lower 32 bits of the 74th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address73 [31:0] + * + */ +/* + * Field : MAC Address73 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 74th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR73_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR73_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address73 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR73_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR73_LOW_s ALT_EMAC_GMAC_MAC_ADDR73_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_OFST 0x9cc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR73_LOW_OFST)) + +/* + * Register : Register 628 (MAC Address74 High Register) - MAC_Address74_High + * + * The MAC Address74 High register holds the upper 16 bits of the 75th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address74 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address74 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address74 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 75th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address74 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address74 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address74 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address74 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address74 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address74 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address74[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address74[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 75th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR74_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR74_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address74 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR74_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR74_HIGH_s ALT_EMAC_GMAC_MAC_ADDR74_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_OFST 0x9d0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR74_HIGH_OFST)) + +/* + * Register : Register 629 (MAC Address74 Low Register) - MAC_Address74_Low + * + * The MAC Address74 Low register holds the lower 32 bits of the 75th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address74 [31:0] + * + */ +/* + * Field : MAC Address74 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 75th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR74_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR74_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address74 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR74_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR74_LOW_s ALT_EMAC_GMAC_MAC_ADDR74_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_OFST 0x9d4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR74_LOW_OFST)) + +/* + * Register : Register 630 (MAC Address75 High Register) - MAC_Address75_High + * + * The MAC Address75 High register holds the upper 16 bits of the 76th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address75 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address75 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address75 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 76th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address75 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address75 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address75 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address75 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address75 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address75 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address75[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address75[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 76th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR75_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR75_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address75 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR75_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR75_HIGH_s ALT_EMAC_GMAC_MAC_ADDR75_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_OFST 0x9d8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR75_HIGH_OFST)) + +/* + * Register : Register 631 (MAC Address75 Low Register) - MAC_Address75_Low + * + * The MAC Address75 Low register holds the lower 32 bits of the 76th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address75 [31:0] + * + */ +/* + * Field : MAC Address75 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 76th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR75_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR75_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address75 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR75_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR75_LOW_s ALT_EMAC_GMAC_MAC_ADDR75_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_OFST 0x9dc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR75_LOW_OFST)) + +/* + * Register : Register 632 (MAC Address76 High Register) - MAC_Address76_High + * + * The MAC Address76 High register holds the upper 16 bits of the 77th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address76 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address76 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address76 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 77th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address76 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address76 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address76 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address76 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address76 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address76 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address76[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address76[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 77th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR76_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR76_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address76 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR76_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR76_HIGH_s ALT_EMAC_GMAC_MAC_ADDR76_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_OFST 0x9e0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR76_HIGH_OFST)) + +/* + * Register : Register 633 (MAC Address76 Low Register) - MAC_Address76_Low + * + * The MAC Address76 Low register holds the lower 32 bits of the 77th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address76 [31:0] + * + */ +/* + * Field : MAC Address76 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 77th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR76_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR76_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address76 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR76_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR76_LOW_s ALT_EMAC_GMAC_MAC_ADDR76_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_OFST 0x9e4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR76_LOW_OFST)) + +/* + * Register : Register 634 (MAC Address77 High Register) - MAC_Address77_High + * + * The MAC Address77 High register holds the upper 16 bits of the 78th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address77 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address77 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address77 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 78th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address77 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address77 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address77 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address77 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address77 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address77 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address77[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address77[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 78th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR77_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR77_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address77 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR77_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR77_HIGH_s ALT_EMAC_GMAC_MAC_ADDR77_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_OFST 0x9e8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR77_HIGH_OFST)) + +/* + * Register : Register 635 (MAC Address77 Low Register) - MAC_Address77_Low + * + * The MAC Address77 Low register holds the lower 32 bits of the 78th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address77 [31:0] + * + */ +/* + * Field : MAC Address77 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 78th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR77_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR77_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address77 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR77_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR77_LOW_s ALT_EMAC_GMAC_MAC_ADDR77_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_OFST 0x9ec +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR77_LOW_OFST)) + +/* + * Register : Register 636 (MAC Address78 High Register) - MAC_Address78_High + * + * The MAC Address78 High register holds the upper 16 bits of the 79th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address78 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address78 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address78 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 79th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address78 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address78 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address78 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address78 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address78 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address78 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address78[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address78[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 79th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR78_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR78_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address78 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR78_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR78_HIGH_s ALT_EMAC_GMAC_MAC_ADDR78_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_OFST 0x9f0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR78_HIGH_OFST)) + +/* + * Register : Register 637 (MAC Address78 Low Register) - MAC_Address78_Low + * + * The MAC Address78 Low register holds the lower 32 bits of the 79th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address78 [31:0] + * + */ +/* + * Field : MAC Address78 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 79th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR78_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR78_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address78 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR78_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR78_LOW_s ALT_EMAC_GMAC_MAC_ADDR78_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_OFST 0x9f4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR78_LOW_OFST)) + +/* + * Register : Register 638 (MAC Address79 High Register) - MAC_Address79_High + * + * The MAC Address79 High register holds the upper 16 bits of the 80th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address79 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address79 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address79 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 80th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address79 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address79 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address79 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address79 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address79 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address79 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address79[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address79[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 80th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR79_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR79_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address79 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR79_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR79_HIGH_s ALT_EMAC_GMAC_MAC_ADDR79_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_OFST 0x9f8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR79_HIGH_OFST)) + +/* + * Register : Register 639 (MAC Address79 Low Register) - MAC_Address79_Low + * + * The MAC Address79 Low register holds the lower 32 bits of the 80th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address79 [31:0] + * + */ +/* + * Field : MAC Address79 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 80th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR79_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR79_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address79 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR79_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR79_LOW_s ALT_EMAC_GMAC_MAC_ADDR79_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_OFST 0x9fc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR79_LOW_OFST)) + +/* + * Register : Register 640 (MAC Address80 High Register) - MAC_Address80_High + * + * The MAC Address80 High register holds the upper 16 bits of the 81th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address80 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address80 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address80 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 81th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address80 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address80 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address80 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address80 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address80 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address80 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address80[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address80[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 81th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR80_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR80_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address80 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR80_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR80_HIGH_s ALT_EMAC_GMAC_MAC_ADDR80_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_OFST 0xa00 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR80_HIGH_OFST)) + +/* + * Register : Register 641 (MAC Address80 Low Register) - MAC_Address80_Low + * + * The MAC Address80 Low register holds the lower 32 bits of the 81th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address80 [31:0] + * + */ +/* + * Field : MAC Address80 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 81th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR80_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR80_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address80 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR80_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR80_LOW_s ALT_EMAC_GMAC_MAC_ADDR80_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_OFST 0xa04 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR80_LOW_OFST)) + +/* + * Register : Register 642 (MAC Address81 High Register) - MAC_Address81_High + * + * The MAC Address81 High register holds the upper 16 bits of the 82th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address81 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address81 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address81 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 82th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address81 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address81 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address81 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address81 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address81 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address81 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address81[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address81[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 82th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR81_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR81_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address81 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR81_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR81_HIGH_s ALT_EMAC_GMAC_MAC_ADDR81_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_OFST 0xa08 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR81_HIGH_OFST)) + +/* + * Register : Register 643 (MAC Address81 Low Register) - MAC_Address81_Low + * + * The MAC Address81 Low register holds the lower 32 bits of the 82th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address81 [31:0] + * + */ +/* + * Field : MAC Address81 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 82th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR81_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR81_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address81 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR81_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR81_LOW_s ALT_EMAC_GMAC_MAC_ADDR81_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_OFST 0xa0c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR81_LOW_OFST)) + +/* + * Register : Register 644 (MAC Address82 High Register) - MAC_Address82_High + * + * The MAC Address82 High register holds the upper 16 bits of the 83th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address82 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address82 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address82 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 83th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address82 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address82 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address82 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address82 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address82 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address82 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address82[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address82[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 83th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR82_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR82_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address82 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR82_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR82_HIGH_s ALT_EMAC_GMAC_MAC_ADDR82_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_OFST 0xa10 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR82_HIGH_OFST)) + +/* + * Register : Register 645 (MAC Address82 Low Register) - MAC_Address82_Low + * + * The MAC Address82 Low register holds the lower 32 bits of the 83th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address82 [31:0] + * + */ +/* + * Field : MAC Address82 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 83th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR82_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR82_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address82 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR82_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR82_LOW_s ALT_EMAC_GMAC_MAC_ADDR82_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_OFST 0xa14 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR82_LOW_OFST)) + +/* + * Register : Register 646 (MAC Address83 High Register) - MAC_Address83_High + * + * The MAC Address83 High register holds the upper 16 bits of the 84th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address83 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address83 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address83 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 84th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address83 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address83 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address83 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address83 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address83 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address83 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address83[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address83[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 84th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR83_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR83_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address83 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR83_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR83_HIGH_s ALT_EMAC_GMAC_MAC_ADDR83_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_OFST 0xa18 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR83_HIGH_OFST)) + +/* + * Register : Register 647 (MAC Address83 Low Register) - MAC_Address83_Low + * + * The MAC Address83 Low register holds the lower 32 bits of the 84th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address83 [31:0] + * + */ +/* + * Field : MAC Address83 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 84th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR83_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR83_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address83 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR83_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR83_LOW_s ALT_EMAC_GMAC_MAC_ADDR83_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_OFST 0xa1c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR83_LOW_OFST)) + +/* + * Register : Register 648 (MAC Address84 High Register) - MAC_Address84_High + * + * The MAC Address84 High register holds the upper 16 bits of the 85th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address84 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address84 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address84 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 85th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address84 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address84 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address84 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address84 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address84 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address84 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address84[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address84[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 85th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR84_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR84_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address84 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR84_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR84_HIGH_s ALT_EMAC_GMAC_MAC_ADDR84_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_OFST 0xa20 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR84_HIGH_OFST)) + +/* + * Register : Register 649 (MAC Address84 Low Register) - MAC_Address84_Low + * + * The MAC Address84 Low register holds the lower 32 bits of the 85th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address84 [31:0] + * + */ +/* + * Field : MAC Address84 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 85th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR84_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR84_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address84 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR84_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR84_LOW_s ALT_EMAC_GMAC_MAC_ADDR84_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_OFST 0xa24 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR84_LOW_OFST)) + +/* + * Register : Register 650 (MAC Address85 High Register) - MAC_Address85_High + * + * The MAC Address85 High register holds the upper 16 bits of the 86th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address85 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address85 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address85 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 86th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address85 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address85 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address85 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address85 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address85 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address85 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address85[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address85[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 86th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR85_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR85_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address85 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR85_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR85_HIGH_s ALT_EMAC_GMAC_MAC_ADDR85_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_OFST 0xa28 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR85_HIGH_OFST)) + +/* + * Register : Register 651 (MAC Address85 Low Register) - MAC_Address85_Low + * + * The MAC Address85 Low register holds the lower 32 bits of the 86th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address85 [31:0] + * + */ +/* + * Field : MAC Address85 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 86th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR85_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR85_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address85 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR85_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR85_LOW_s ALT_EMAC_GMAC_MAC_ADDR85_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_OFST 0xa2c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR85_LOW_OFST)) + +/* + * Register : Register 652 (MAC Address86 High Register) - MAC_Address86_High + * + * The MAC Address86 High register holds the upper 16 bits of the 87th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address86 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address86 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address86 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 87th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address86 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address86 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address86 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address86 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address86 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address86 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address86[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address86[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 87th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR86_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR86_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address86 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR86_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR86_HIGH_s ALT_EMAC_GMAC_MAC_ADDR86_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_OFST 0xa30 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR86_HIGH_OFST)) + +/* + * Register : Register 653 (MAC Address86 Low Register) - MAC_Address86_Low + * + * The MAC Address86 Low register holds the lower 32 bits of the 87th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address86 [31:0] + * + */ +/* + * Field : MAC Address86 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 87th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR86_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR86_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address86 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR86_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR86_LOW_s ALT_EMAC_GMAC_MAC_ADDR86_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_OFST 0xa34 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR86_LOW_OFST)) + +/* + * Register : Register 654 (MAC Address87 High Register) - MAC_Address87_High + * + * The MAC Address87 High register holds the upper 16 bits of the 88th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address87 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address87 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address87 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 88th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address87 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address87 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address87 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address87 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address87 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address87 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address87[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address87[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 88th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR87_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR87_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address87 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR87_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR87_HIGH_s ALT_EMAC_GMAC_MAC_ADDR87_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_OFST 0xa38 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR87_HIGH_OFST)) + +/* + * Register : Register 655 (MAC Address87 Low Register) - MAC_Address87_Low + * + * The MAC Address87 Low register holds the lower 32 bits of the 88th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address87 [31:0] + * + */ +/* + * Field : MAC Address87 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 88th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR87_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR87_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address87 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR87_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR87_LOW_s ALT_EMAC_GMAC_MAC_ADDR87_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_OFST 0xa3c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR87_LOW_OFST)) + +/* + * Register : Register 656 (MAC Address88 High Register) - MAC_Address88_High + * + * The MAC Address88 High register holds the upper 16 bits of the 89th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address88 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address88 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address88 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 89th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address88 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address88 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address88 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address88 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address88 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address88 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address88[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address88[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 89th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR88_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR88_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address88 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR88_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR88_HIGH_s ALT_EMAC_GMAC_MAC_ADDR88_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_OFST 0xa40 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR88_HIGH_OFST)) + +/* + * Register : Register 657 (MAC Address88 Low Register) - MAC_Address88_Low + * + * The MAC Address88 Low register holds the lower 32 bits of the 89th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address88 [31:0] + * + */ +/* + * Field : MAC Address88 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 89th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR88_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR88_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address88 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR88_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR88_LOW_s ALT_EMAC_GMAC_MAC_ADDR88_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_OFST 0xa44 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR88_LOW_OFST)) + +/* + * Register : Register 658 (MAC Address89 High Register) - MAC_Address89_High + * + * The MAC Address89 High register holds the upper 16 bits of the 90th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address89 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address89 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address89 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 90th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address89 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address89 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address89 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address89 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address89 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address89 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address89[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address89[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 90th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR89_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR89_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address89 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR89_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR89_HIGH_s ALT_EMAC_GMAC_MAC_ADDR89_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_OFST 0xa48 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR89_HIGH_OFST)) + +/* + * Register : Register 659 (MAC Address89 Low Register) - MAC_Address89_Low + * + * The MAC Address89 Low register holds the lower 32 bits of the 90th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address89 [31:0] + * + */ +/* + * Field : MAC Address89 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 90th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR89_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR89_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address89 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR89_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR89_LOW_s ALT_EMAC_GMAC_MAC_ADDR89_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_OFST 0xa4c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR89_LOW_OFST)) + +/* + * Register : Register 660 (MAC Address90 High Register) - MAC_Address90_High + * + * The MAC Address90 High register holds the upper 16 bits of the 91th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address90 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address90 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address90 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 91th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address90 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address90 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address90 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address90 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address90 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address90 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address90[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address90[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 91th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR90_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR90_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address90 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR90_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR90_HIGH_s ALT_EMAC_GMAC_MAC_ADDR90_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_OFST 0xa50 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR90_HIGH_OFST)) + +/* + * Register : Register 661 (MAC Address90 Low Register) - MAC_Address90_Low + * + * The MAC Address90 Low register holds the lower 32 bits of the 91th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address90 [31:0] + * + */ +/* + * Field : MAC Address90 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 91th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR90_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR90_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address90 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR90_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR90_LOW_s ALT_EMAC_GMAC_MAC_ADDR90_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_OFST 0xa54 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR90_LOW_OFST)) + +/* + * Register : Register 662 (MAC Address91 High Register) - MAC_Address91_High + * + * The MAC Address91 High register holds the upper 16 bits of the 92th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address91 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address91 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address91 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 92th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address91 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address91 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address91 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address91 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address91 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address91 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address91[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address91[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 92th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR91_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR91_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address91 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR91_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR91_HIGH_s ALT_EMAC_GMAC_MAC_ADDR91_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_OFST 0xa58 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR91_HIGH_OFST)) + +/* + * Register : Register 663 (MAC Address91 Low Register) - MAC_Address91_Low + * + * The MAC Address91 Low register holds the lower 32 bits of the 92th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address91 [31:0] + * + */ +/* + * Field : MAC Address91 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 92th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR91_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR91_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address91 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR91_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR91_LOW_s ALT_EMAC_GMAC_MAC_ADDR91_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_OFST 0xa5c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR91_LOW_OFST)) + +/* + * Register : Register 664 (MAC Address92 High Register) - MAC_Address92_High + * + * The MAC Address92 High register holds the upper 16 bits of the 93th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address92 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address92 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address92 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 93th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address92 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address92 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address92 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address92 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address92 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address92 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address92[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address92[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 93th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR92_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR92_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address92 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR92_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR92_HIGH_s ALT_EMAC_GMAC_MAC_ADDR92_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_OFST 0xa60 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR92_HIGH_OFST)) + +/* + * Register : Register 665 (MAC Address92 Low Register) - MAC_Address92_Low + * + * The MAC Address92 Low register holds the lower 32 bits of the 93th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address92 [31:0] + * + */ +/* + * Field : MAC Address92 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 93th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR92_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR92_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address92 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR92_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR92_LOW_s ALT_EMAC_GMAC_MAC_ADDR92_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_OFST 0xa64 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR92_LOW_OFST)) + +/* + * Register : Register 666 (MAC Address93 High Register) - MAC_Address93_High + * + * The MAC Address93 High register holds the upper 16 bits of the 94th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address93 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address93 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address93 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 94th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address93 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address93 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address93 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address93 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address93 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address93 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address93[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address93[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 94th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR93_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR93_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address93 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR93_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR93_HIGH_s ALT_EMAC_GMAC_MAC_ADDR93_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_OFST 0xa68 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR93_HIGH_OFST)) + +/* + * Register : Register 667 (MAC Address93 Low Register) - MAC_Address93_Low + * + * The MAC Address93 Low register holds the lower 32 bits of the 94th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address93 [31:0] + * + */ +/* + * Field : MAC Address93 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 94th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR93_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR93_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address93 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR93_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR93_LOW_s ALT_EMAC_GMAC_MAC_ADDR93_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_OFST 0xa6c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR93_LOW_OFST)) + +/* + * Register : Register 668 (MAC Address94 High Register) - MAC_Address94_High + * + * The MAC Address94 High register holds the upper 16 bits of the 95th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address94 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address94 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address94 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 95th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address94 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address94 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address94 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address94 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address94 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address94 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address94[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address94[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 95th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR94_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR94_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address94 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR94_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR94_HIGH_s ALT_EMAC_GMAC_MAC_ADDR94_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_OFST 0xa70 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR94_HIGH_OFST)) + +/* + * Register : Register 669 (MAC Address94 Low Register) - MAC_Address94_Low + * + * The MAC Address94 Low register holds the lower 32 bits of the 95th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address94 [31:0] + * + */ +/* + * Field : MAC Address94 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 95th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR94_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR94_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address94 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR94_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR94_LOW_s ALT_EMAC_GMAC_MAC_ADDR94_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_OFST 0xa74 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR94_LOW_OFST)) + +/* + * Register : Register 670 (MAC Address95 High Register) - MAC_Address95_High + * + * The MAC Address95 High register holds the upper 16 bits of the 96th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address95 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address95 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address95 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 96th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address95 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address95 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address95 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address95 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address95 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address95 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address95[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address95[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 96th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR95_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR95_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address95 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR95_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR95_HIGH_s ALT_EMAC_GMAC_MAC_ADDR95_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_OFST 0xa78 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR95_HIGH_OFST)) + +/* + * Register : Register 671 (MAC Address95 Low Register) - MAC_Address95_Low + * + * The MAC Address95 Low register holds the lower 32 bits of the 96th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address95 [31:0] + * + */ +/* + * Field : MAC Address95 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 96th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR95_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR95_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address95 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR95_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR95_LOW_s ALT_EMAC_GMAC_MAC_ADDR95_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_OFST 0xa7c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR95_LOW_OFST)) + +/* + * Register : Register 672 (MAC Address96 High Register) - MAC_Address96_High + * + * The MAC Address96 High register holds the upper 16 bits of the 97th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address96 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address96 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address96 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 97th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address96 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address96 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address96 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address96 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address96 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address96 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address96[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address96[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 97th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR96_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR96_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address96 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR96_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR96_HIGH_s ALT_EMAC_GMAC_MAC_ADDR96_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_OFST 0xa80 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR96_HIGH_OFST)) + +/* + * Register : Register 673 (MAC Address96 Low Register) - MAC_Address96_Low + * + * The MAC Address96 Low register holds the lower 32 bits of the 97th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address96 [31:0] + * + */ +/* + * Field : MAC Address96 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 97th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR96_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR96_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address96 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR96_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR96_LOW_s ALT_EMAC_GMAC_MAC_ADDR96_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_OFST 0xa84 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR96_LOW_OFST)) + +/* + * Register : Register 674 (MAC Address97 High Register) - MAC_Address97_High + * + * The MAC Address97 High register holds the upper 16 bits of the 98th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address97 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address97 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address97 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 98th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address97 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address97 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address97 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address97 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address97 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address97 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address97[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address97[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 98th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR97_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR97_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address97 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR97_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR97_HIGH_s ALT_EMAC_GMAC_MAC_ADDR97_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_OFST 0xa88 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR97_HIGH_OFST)) + +/* + * Register : Register 675 (MAC Address97 Low Register) - MAC_Address97_Low + * + * The MAC Address97 Low register holds the lower 32 bits of the 98th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address97 [31:0] + * + */ +/* + * Field : MAC Address97 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 98th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR97_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR97_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address97 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR97_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR97_LOW_s ALT_EMAC_GMAC_MAC_ADDR97_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_OFST 0xa8c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR97_LOW_OFST)) + +/* + * Register : Register 676 (MAC Address98 High Register) - MAC_Address98_High + * + * The MAC Address98 High register holds the upper 16 bits of the 99th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address98 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address98 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address98 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 99th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address98 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address98 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address98 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address98 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address98 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address98 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address98[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address98[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 99th MAC address for + * perfect filtering. When this bit is disabled, the address filter block ignores + * the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR98_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR98_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address98 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR98_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR98_HIGH_s ALT_EMAC_GMAC_MAC_ADDR98_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_OFST 0xa90 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR98_HIGH_OFST)) + +/* + * Register : Register 677 (MAC Address98 Low Register) - MAC_Address98_Low + * + * The MAC Address98 Low register holds the lower 32 bits of the 99th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address98 [31:0] + * + */ +/* + * Field : MAC Address98 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 99th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR98_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR98_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address98 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR98_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR98_LOW_s ALT_EMAC_GMAC_MAC_ADDR98_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_OFST 0xa94 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR98_LOW_OFST)) + +/* + * Register : Register 678 (MAC Address99 High Register) - MAC_Address99_High + * + * The MAC Address99 High register holds the upper 16 bits of the 100th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address99 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------- + * [15:0] | RW | 0xffff | MAC Address99 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address99 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 100th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address99 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address99 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address99 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address99 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address99 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address99 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address99[47:0] is used to compare with the SA + * fields of the received frame. When this bit is disabled, the MAC Address99[47:0] + * is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 100th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR99_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR99_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address99 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR99_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR99_HIGH_s ALT_EMAC_GMAC_MAC_ADDR99_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_OFST 0xa98 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR99_HIGH_OFST)) + +/* + * Register : Register 679 (MAC Address99 Low Register) - MAC_Address99_Low + * + * The MAC Address99 Low register holds the lower 32 bits of the 100th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------------- + * [31:0] | RW | 0xffffffff | MAC Address99 [31:0] + * + */ +/* + * Field : MAC Address99 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 100th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR99_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR99_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address99 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR99_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR99_LOW_s ALT_EMAC_GMAC_MAC_ADDR99_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_OFST 0xa9c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR99_LOW_OFST)) + +/* + * Register : Register 680 (MAC Address100 High Register) - MAC_Address100_High + * + * The MAC Address100 High register holds the upper 16 bits of the 101th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address100 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address100 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address100 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 101th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address100 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address100 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address100 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address100 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address100 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address100 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address100[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address100[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 101th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR100_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR100_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address100 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR100_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR100_HIGH_s ALT_EMAC_GMAC_MAC_ADDR100_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_OFST 0xaa0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR100_HIGH_OFST)) + +/* + * Register : Register 681 (MAC Address100 Low Register) - MAC_Address100_Low + * + * The MAC Address100 Low register holds the lower 32 bits of the 101th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address100 [31:0] + * + */ +/* + * Field : MAC Address100 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 101th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR100_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR100_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address100 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR100_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR100_LOW_s ALT_EMAC_GMAC_MAC_ADDR100_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_OFST 0xaa4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR100_LOW_OFST)) + +/* + * Register : Register 682 (MAC Address101 High Register) - MAC_Address101_High + * + * The MAC Address101 High register holds the upper 16 bits of the 102th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address101 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address101 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address101 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 102th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address101 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address101 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address101 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address101 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address101 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address101 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address101[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address101[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 102th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR101_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR101_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address101 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR101_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR101_HIGH_s ALT_EMAC_GMAC_MAC_ADDR101_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_OFST 0xaa8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR101_HIGH_OFST)) + +/* + * Register : Register 683 (MAC Address101 Low Register) - MAC_Address101_Low + * + * The MAC Address101 Low register holds the lower 32 bits of the 102th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address101 [31:0] + * + */ +/* + * Field : MAC Address101 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 102th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR101_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR101_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address101 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR101_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR101_LOW_s ALT_EMAC_GMAC_MAC_ADDR101_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_OFST 0xaac +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR101_LOW_OFST)) + +/* + * Register : Register 684 (MAC Address102 High Register) - MAC_Address102_High + * + * The MAC Address102 High register holds the upper 16 bits of the 103th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address102 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address102 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address102 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 103th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address102 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address102 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address102 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address102 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address102 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address102 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address102[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address102[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 103th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR102_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR102_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address102 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR102_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR102_HIGH_s ALT_EMAC_GMAC_MAC_ADDR102_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_OFST 0xab0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR102_HIGH_OFST)) + +/* + * Register : Register 685 (MAC Address102 Low Register) - MAC_Address102_Low + * + * The MAC Address102 Low register holds the lower 32 bits of the 103th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address102 [31:0] + * + */ +/* + * Field : MAC Address102 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 103th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR102_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR102_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address102 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR102_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR102_LOW_s ALT_EMAC_GMAC_MAC_ADDR102_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_OFST 0xab4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR102_LOW_OFST)) + +/* + * Register : Register 686 (MAC Address103 High Register) - MAC_Address103_High + * + * The MAC Address103 High register holds the upper 16 bits of the 104th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address103 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address103 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address103 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 104th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address103 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address103 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address103 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address103 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address103 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address103 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address103[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address103[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 104th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR103_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR103_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address103 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR103_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR103_HIGH_s ALT_EMAC_GMAC_MAC_ADDR103_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_OFST 0xab8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR103_HIGH_OFST)) + +/* + * Register : Register 687 (MAC Address103 Low Register) - MAC_Address103_Low + * + * The MAC Address103 Low register holds the lower 32 bits of the 104th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address103 [31:0] + * + */ +/* + * Field : MAC Address103 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 104th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR103_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR103_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address103 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR103_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR103_LOW_s ALT_EMAC_GMAC_MAC_ADDR103_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_OFST 0xabc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR103_LOW_OFST)) + +/* + * Register : Register 688 (MAC Address104 High Register) - MAC_Address104_High + * + * The MAC Address104 High register holds the upper 16 bits of the 105th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address104 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address104 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address104 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 105th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address104 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address104 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address104 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address104 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address104 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address104 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address104[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address104[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 105th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR104_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR104_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address104 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR104_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR104_HIGH_s ALT_EMAC_GMAC_MAC_ADDR104_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_OFST 0xac0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR104_HIGH_OFST)) + +/* + * Register : Register 689 (MAC Address104 Low Register) - MAC_Address104_Low + * + * The MAC Address104 Low register holds the lower 32 bits of the 105th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address104 [31:0] + * + */ +/* + * Field : MAC Address104 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 105th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR104_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR104_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address104 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR104_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR104_LOW_s ALT_EMAC_GMAC_MAC_ADDR104_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_OFST 0xac4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR104_LOW_OFST)) + +/* + * Register : Register 690 (MAC Address105 High Register) - MAC_Address105_High + * + * The MAC Address105 High register holds the upper 16 bits of the 106th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address105 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address105 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address105 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 106th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address105 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address105 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address105 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address105 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address105 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address105 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address105[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address105[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 106th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR105_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR105_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address105 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR105_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR105_HIGH_s ALT_EMAC_GMAC_MAC_ADDR105_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_OFST 0xac8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR105_HIGH_OFST)) + +/* + * Register : Register 691 (MAC Address105 Low Register) - MAC_Address105_Low + * + * The MAC Address105 Low register holds the lower 32 bits of the 106th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address105 [31:0] + * + */ +/* + * Field : MAC Address105 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 106th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR105_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR105_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address105 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR105_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR105_LOW_s ALT_EMAC_GMAC_MAC_ADDR105_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_OFST 0xacc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR105_LOW_OFST)) + +/* + * Register : Register 692 (MAC Address106 High Register) - MAC_Address106_High + * + * The MAC Address106 High register holds the upper 16 bits of the 107th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address106 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address106 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address106 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 107th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address106 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address106 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address106 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address106 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address106 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address106 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address106[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address106[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 107th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR106_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR106_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address106 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR106_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR106_HIGH_s ALT_EMAC_GMAC_MAC_ADDR106_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_OFST 0xad0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR106_HIGH_OFST)) + +/* + * Register : Register 693 (MAC Address106 Low Register) - MAC_Address106_Low + * + * The MAC Address106 Low register holds the lower 32 bits of the 107th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address106 [31:0] + * + */ +/* + * Field : MAC Address106 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 107th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR106_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR106_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address106 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR106_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR106_LOW_s ALT_EMAC_GMAC_MAC_ADDR106_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_OFST 0xad4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR106_LOW_OFST)) + +/* + * Register : Register 694 (MAC Address107 High Register) - MAC_Address107_High + * + * The MAC Address107 High register holds the upper 16 bits of the 108th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address107 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address107 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address107 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 108th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address107 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address107 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address107 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address107 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address107 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address107 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address107[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address107[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 108th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR107_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR107_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address107 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR107_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR107_HIGH_s ALT_EMAC_GMAC_MAC_ADDR107_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_OFST 0xad8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR107_HIGH_OFST)) + +/* + * Register : Register 695 (MAC Address107 Low Register) - MAC_Address107_Low + * + * The MAC Address107 Low register holds the lower 32 bits of the 108th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address107 [31:0] + * + */ +/* + * Field : MAC Address107 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 108th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR107_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR107_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address107 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR107_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR107_LOW_s ALT_EMAC_GMAC_MAC_ADDR107_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_OFST 0xadc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR107_LOW_OFST)) + +/* + * Register : Register 696 (MAC Address108 High Register) - MAC_Address108_High + * + * The MAC Address108 High register holds the upper 16 bits of the 109th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address108 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address108 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address108 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 109th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address108 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address108 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address108 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address108 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address108 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address108 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address108[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address108[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 109th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR108_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR108_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address108 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR108_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR108_HIGH_s ALT_EMAC_GMAC_MAC_ADDR108_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_OFST 0xae0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR108_HIGH_OFST)) + +/* + * Register : Register 697 (MAC Address108 Low Register) - MAC_Address108_Low + * + * The MAC Address108 Low register holds the lower 32 bits of the 109th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address108 [31:0] + * + */ +/* + * Field : MAC Address108 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 109th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR108_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR108_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address108 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR108_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR108_LOW_s ALT_EMAC_GMAC_MAC_ADDR108_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_OFST 0xae4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR108_LOW_OFST)) + +/* + * Register : Register 698 (MAC Address109 High Register) - MAC_Address109_High + * + * The MAC Address109 High register holds the upper 16 bits of the 110th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address109 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address109 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address109 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 110th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address109 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address109 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address109 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address109 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address109 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address109 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address109[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address109[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 110th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR109_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR109_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address109 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR109_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR109_HIGH_s ALT_EMAC_GMAC_MAC_ADDR109_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_OFST 0xae8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR109_HIGH_OFST)) + +/* + * Register : Register 699 (MAC Address109 Low Register) - MAC_Address109_Low + * + * The MAC Address109 Low register holds the lower 32 bits of the 110th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address109 [31:0] + * + */ +/* + * Field : MAC Address109 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 110th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR109_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR109_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address109 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR109_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR109_LOW_s ALT_EMAC_GMAC_MAC_ADDR109_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_OFST 0xaec +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR109_LOW_OFST)) + +/* + * Register : Register 700 (MAC Address110 High Register) - MAC_Address110_High + * + * The MAC Address110 High register holds the upper 16 bits of the 111th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address110 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address110 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address110 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 111th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address110 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address110 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address110 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address110 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address110 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address110 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address110[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address110[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 111th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR110_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR110_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address110 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR110_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR110_HIGH_s ALT_EMAC_GMAC_MAC_ADDR110_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_OFST 0xaf0 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR110_HIGH_OFST)) + +/* + * Register : Register 701 (MAC Address110 Low Register) - MAC_Address110_Low + * + * The MAC Address110 Low register holds the lower 32 bits of the 111th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address110 [31:0] + * + */ +/* + * Field : MAC Address110 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 111th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR110_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR110_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address110 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR110_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR110_LOW_s ALT_EMAC_GMAC_MAC_ADDR110_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_OFST 0xaf4 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR110_LOW_OFST)) + +/* + * Register : Register 702 (MAC Address111 High Register) - MAC_Address111_High + * + * The MAC Address111 High register holds the upper 16 bits of the 112th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address111 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address111 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address111 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 112th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address111 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address111 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address111 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address111 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address111 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address111 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address111[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address111[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 112th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR111_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR111_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address111 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR111_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR111_HIGH_s ALT_EMAC_GMAC_MAC_ADDR111_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_OFST 0xaf8 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR111_HIGH_OFST)) + +/* + * Register : Register 703 (MAC Address111 Low Register) - MAC_Address111_Low + * + * The MAC Address111 Low register holds the lower 32 bits of the 112th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address111 [31:0] + * + */ +/* + * Field : MAC Address111 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 112th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR111_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR111_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address111 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR111_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR111_LOW_s ALT_EMAC_GMAC_MAC_ADDR111_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_OFST 0xafc +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR111_LOW_OFST)) + +/* + * Register : Register 704 (MAC Address112 High Register) - MAC_Address112_High + * + * The MAC Address112 High register holds the upper 16 bits of the 113th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address112 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address112 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address112 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 113th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address112 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address112 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address112 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address112 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address112 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address112 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address112[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address112[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 113th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR112_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR112_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address112 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR112_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR112_HIGH_s ALT_EMAC_GMAC_MAC_ADDR112_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_OFST 0xb00 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR112_HIGH_OFST)) + +/* + * Register : Register 705 (MAC Address112 Low Register) - MAC_Address112_Low + * + * The MAC Address112 Low register holds the lower 32 bits of the 113th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address112 [31:0] + * + */ +/* + * Field : MAC Address112 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 113th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR112_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR112_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address112 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR112_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR112_LOW_s ALT_EMAC_GMAC_MAC_ADDR112_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_OFST 0xb04 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR112_LOW_OFST)) + +/* + * Register : Register 706 (MAC Address113 High Register) - MAC_Address113_High + * + * The MAC Address113 High register holds the upper 16 bits of the 114th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address113 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address113 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address113 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 114th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address113 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address113 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address113 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address113 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address113 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address113 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address113[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address113[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 114th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR113_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR113_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address113 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR113_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR113_HIGH_s ALT_EMAC_GMAC_MAC_ADDR113_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_OFST 0xb08 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR113_HIGH_OFST)) + +/* + * Register : Register 707 (MAC Address113 Low Register) - MAC_Address113_Low + * + * The MAC Address113 Low register holds the lower 32 bits of the 114th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address113 [31:0] + * + */ +/* + * Field : MAC Address113 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 114th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR113_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR113_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address113 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR113_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR113_LOW_s ALT_EMAC_GMAC_MAC_ADDR113_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_OFST 0xb0c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR113_LOW_OFST)) + +/* + * Register : Register 708 (MAC Address114 High Register) - MAC_Address114_High + * + * The MAC Address114 High register holds the upper 16 bits of the 115th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address114 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address114 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address114 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 115th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address114 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address114 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address114 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address114 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address114 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address114 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address114[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address114[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 115th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR114_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR114_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address114 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR114_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR114_HIGH_s ALT_EMAC_GMAC_MAC_ADDR114_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_OFST 0xb10 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR114_HIGH_OFST)) + +/* + * Register : Register 709 (MAC Address114 Low Register) - MAC_Address114_Low + * + * The MAC Address114 Low register holds the lower 32 bits of the 115th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address114 [31:0] + * + */ +/* + * Field : MAC Address114 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 115th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR114_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR114_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address114 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR114_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR114_LOW_s ALT_EMAC_GMAC_MAC_ADDR114_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_OFST 0xb14 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR114_LOW_OFST)) + +/* + * Register : Register 710 (MAC Address115 High Register) - MAC_Address115_High + * + * The MAC Address115 High register holds the upper 16 bits of the 116th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address115 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address115 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address115 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 116th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address115 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address115 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address115 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address115 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address115 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address115 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address115[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address115[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 116th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR115_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR115_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address115 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR115_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR115_HIGH_s ALT_EMAC_GMAC_MAC_ADDR115_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_OFST 0xb18 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR115_HIGH_OFST)) + +/* + * Register : Register 711 (MAC Address115 Low Register) - MAC_Address115_Low + * + * The MAC Address115 Low register holds the lower 32 bits of the 116th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address115 [31:0] + * + */ +/* + * Field : MAC Address115 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 116th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR115_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR115_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address115 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR115_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR115_LOW_s ALT_EMAC_GMAC_MAC_ADDR115_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_OFST 0xb1c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR115_LOW_OFST)) + +/* + * Register : Register 712 (MAC Address116 High Register) - MAC_Address116_High + * + * The MAC Address116 High register holds the upper 16 bits of the 117th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address116 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address116 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address116 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 117th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address116 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address116 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address116 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address116 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address116 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address116 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address116[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address116[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 117th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR116_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR116_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address116 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR116_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR116_HIGH_s ALT_EMAC_GMAC_MAC_ADDR116_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_OFST 0xb20 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR116_HIGH_OFST)) + +/* + * Register : Register 713 (MAC Address116 Low Register) - MAC_Address116_Low + * + * The MAC Address116 Low register holds the lower 32 bits of the 117th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address116 [31:0] + * + */ +/* + * Field : MAC Address116 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 117th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR116_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR116_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address116 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR116_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR116_LOW_s ALT_EMAC_GMAC_MAC_ADDR116_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_OFST 0xb24 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR116_LOW_OFST)) + +/* + * Register : Register 714 (MAC Address117 High Register) - MAC_Address117_High + * + * The MAC Address117 High register holds the upper 16 bits of the 118th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address117 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address117 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address117 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 118th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address117 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address117 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address117 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address117 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address117 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address117 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address117[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address117[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 118th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR117_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR117_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address117 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR117_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR117_HIGH_s ALT_EMAC_GMAC_MAC_ADDR117_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_OFST 0xb28 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR117_HIGH_OFST)) + +/* + * Register : Register 715 (MAC Address117 Low Register) - MAC_Address117_Low + * + * The MAC Address117 Low register holds the lower 32 bits of the 118th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address117 [31:0] + * + */ +/* + * Field : MAC Address117 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 118th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR117_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR117_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address117 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR117_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR117_LOW_s ALT_EMAC_GMAC_MAC_ADDR117_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_OFST 0xb2c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR117_LOW_OFST)) + +/* + * Register : Register 716 (MAC Address118 High Register) - MAC_Address118_High + * + * The MAC Address118 High register holds the upper 16 bits of the 119th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address118 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address118 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address118 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 119th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address118 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address118 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address118 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address118 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address118 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address118 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address118[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address118[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 119th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR118_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR118_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address118 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR118_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR118_HIGH_s ALT_EMAC_GMAC_MAC_ADDR118_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_OFST 0xb30 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR118_HIGH_OFST)) + +/* + * Register : Register 717 (MAC Address118 Low Register) - MAC_Address118_Low + * + * The MAC Address118 Low register holds the lower 32 bits of the 119th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address118 [31:0] + * + */ +/* + * Field : MAC Address118 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 119th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR118_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR118_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address118 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR118_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR118_LOW_s ALT_EMAC_GMAC_MAC_ADDR118_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_OFST 0xb34 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR118_LOW_OFST)) + +/* + * Register : Register 718 (MAC Address119 High Register) - MAC_Address119_High + * + * The MAC Address119 High register holds the upper 16 bits of the 120th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address119 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address119 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address119 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 120th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address119 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address119 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address119 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address119 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address119 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address119 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address119[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address119[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 120th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR119_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR119_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address119 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR119_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR119_HIGH_s ALT_EMAC_GMAC_MAC_ADDR119_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_OFST 0xb38 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR119_HIGH_OFST)) + +/* + * Register : Register 719 (MAC Address119 Low Register) - MAC_Address119_Low + * + * The MAC Address119 Low register holds the lower 32 bits of the 120th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address119 [31:0] + * + */ +/* + * Field : MAC Address119 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 120th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR119_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR119_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address119 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR119_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR119_LOW_s ALT_EMAC_GMAC_MAC_ADDR119_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_OFST 0xb3c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR119_LOW_OFST)) + +/* + * Register : Register 720 (MAC Address120 High Register) - MAC_Address120_High + * + * The MAC Address120 High register holds the upper 16 bits of the 121th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address120 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address120 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address120 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 121th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address120 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address120 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address120 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address120 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address120 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address120 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address120[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address120[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 121th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR120_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR120_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address120 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR120_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR120_HIGH_s ALT_EMAC_GMAC_MAC_ADDR120_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_OFST 0xb40 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR120_HIGH_OFST)) + +/* + * Register : Register 721 (MAC Address120 Low Register) - MAC_Address120_Low + * + * The MAC Address120 Low register holds the lower 32 bits of the 121th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address120 [31:0] + * + */ +/* + * Field : MAC Address120 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 121th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR120_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR120_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address120 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR120_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR120_LOW_s ALT_EMAC_GMAC_MAC_ADDR120_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_OFST 0xb44 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR120_LOW_OFST)) + +/* + * Register : Register 722 (MAC Address121 High Register) - MAC_Address121_High + * + * The MAC Address121 High register holds the upper 16 bits of the 122th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address121 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address121 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address121 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 122th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address121 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address121 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address121 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address121 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address121 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address121 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address121[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address121[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 122th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR121_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR121_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address121 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR121_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR121_HIGH_s ALT_EMAC_GMAC_MAC_ADDR121_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_OFST 0xb48 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR121_HIGH_OFST)) + +/* + * Register : Register 723 (MAC Address121 Low Register) - MAC_Address121_Low + * + * The MAC Address121 Low register holds the lower 32 bits of the 122th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address121 [31:0] + * + */ +/* + * Field : MAC Address121 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 122th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR121_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR121_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address121 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR121_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR121_LOW_s ALT_EMAC_GMAC_MAC_ADDR121_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_OFST 0xb4c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR121_LOW_OFST)) + +/* + * Register : Register 724 (MAC Address122 High Register) - MAC_Address122_High + * + * The MAC Address122 High register holds the upper 16 bits of the 123th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address122 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address122 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address122 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 123th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address122 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address122 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address122 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address122 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address122 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address122 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address122[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address122[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 123th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR122_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR122_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address122 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR122_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR122_HIGH_s ALT_EMAC_GMAC_MAC_ADDR122_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_OFST 0xb50 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR122_HIGH_OFST)) + +/* + * Register : Register 725 (MAC Address122 Low Register) - MAC_Address122_Low + * + * The MAC Address122 Low register holds the lower 32 bits of the 123th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address122 [31:0] + * + */ +/* + * Field : MAC Address122 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 123th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR122_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR122_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address122 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR122_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR122_LOW_s ALT_EMAC_GMAC_MAC_ADDR122_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_OFST 0xb54 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR122_LOW_OFST)) + +/* + * Register : Register 726 (MAC Address123 High Register) - MAC_Address123_High + * + * The MAC Address123 High register holds the upper 16 bits of the 124th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address123 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address123 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address123 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 124th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address123 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address123 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address123 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address123 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address123 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address123 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address123[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address123[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 124th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR123_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR123_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address123 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR123_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR123_HIGH_s ALT_EMAC_GMAC_MAC_ADDR123_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_OFST 0xb58 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR123_HIGH_OFST)) + +/* + * Register : Register 727 (MAC Address123 Low Register) - MAC_Address123_Low + * + * The MAC Address123 Low register holds the lower 32 bits of the 124th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address123 [31:0] + * + */ +/* + * Field : MAC Address123 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 124th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR123_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR123_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address123 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR123_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR123_LOW_s ALT_EMAC_GMAC_MAC_ADDR123_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_OFST 0xb5c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR123_LOW_OFST)) + +/* + * Register : Register 728 (MAC Address124 High Register) - MAC_Address124_High + * + * The MAC Address124 High register holds the upper 16 bits of the 125th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address124 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address124 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address124 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 125th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address124 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address124 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address124 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address124 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address124 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address124 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address124[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address124[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 125th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR124_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR124_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address124 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR124_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR124_HIGH_s ALT_EMAC_GMAC_MAC_ADDR124_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_OFST 0xb60 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR124_HIGH_OFST)) + +/* + * Register : Register 729 (MAC Address124 Low Register) - MAC_Address124_Low + * + * The MAC Address124 Low register holds the lower 32 bits of the 125th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address124 [31:0] + * + */ +/* + * Field : MAC Address124 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 125th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR124_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR124_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address124 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR124_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR124_LOW_s ALT_EMAC_GMAC_MAC_ADDR124_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_OFST 0xb64 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR124_LOW_OFST)) + +/* + * Register : Register 730 (MAC Address125 High Register) - MAC_Address125_High + * + * The MAC Address125 High register holds the upper 16 bits of the 126th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address125 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address125 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address125 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 126th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address125 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address125 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address125 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address125 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address125 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address125 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address125[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address125[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 126th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR125_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR125_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address125 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR125_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR125_HIGH_s ALT_EMAC_GMAC_MAC_ADDR125_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_OFST 0xb68 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR125_HIGH_OFST)) + +/* + * Register : Register 731 (MAC Address125 Low Register) - MAC_Address125_Low + * + * The MAC Address125 Low register holds the lower 32 bits of the 126th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address125 [31:0] + * + */ +/* + * Field : MAC Address125 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 126th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR125_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR125_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address125 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR125_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR125_LOW_s ALT_EMAC_GMAC_MAC_ADDR125_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_OFST 0xb6c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR125_LOW_OFST)) + +/* + * Register : Register 732 (MAC Address126 High Register) - MAC_Address126_High + * + * The MAC Address126 High register holds the upper 16 bits of the 127th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address126 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address126 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address126 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 127th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address126 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address126 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address126 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address126 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address126 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address126 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address126[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address126[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 127th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR126_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR126_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address126 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR126_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR126_HIGH_s ALT_EMAC_GMAC_MAC_ADDR126_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_OFST 0xb70 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR126_HIGH_OFST)) + +/* + * Register : Register 733 (MAC Address126 Low Register) - MAC_Address126_Low + * + * The MAC Address126 Low register holds the lower 32 bits of the 127th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address126 [31:0] + * + */ +/* + * Field : MAC Address126 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 127th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR126_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR126_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address126 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR126_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR126_LOW_s ALT_EMAC_GMAC_MAC_ADDR126_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_OFST 0xb74 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR126_LOW_OFST)) + +/* + * Register : Register 734 (MAC Address127 High Register) - MAC_Address127_High + * + * The MAC Address127 High register holds the upper 16 bits of the 128th 6-byte MAC + * address of the station. Because the MAC address registers are configured to be + * double-synchronized to the (G)MII clock domains, the synchronization is + * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big- + * endian mode) of the MAC Address127 Low Register are written. For proper + * synchronization updates, the consecutive writes to this Address Low Register + * should be performed after at least four clock cycles in the destination clock + * domain. + * + * Note that all MAC Address High registers (except MAC Address0 High) have the + * same format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------- + * [15:0] | RW | 0xffff | MAC Address127 [47:32] + * [23:16] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Mask Byte Control + * [25] | RW | 0x0 | Mask Byte Control + * [26] | RW | 0x0 | Mask Byte Control + * [27] | RW | 0x0 | Mask Byte Control + * [28] | RW | 0x0 | Mask Byte Control + * [29] | RW | 0x0 | Mask Byte Control + * [30] | RW | 0x0 | Source Address + * [31] | RW | 0x0 | Address Enable + * + */ +/* + * Field : MAC Address127 [47:32] - addrhi + * + * This field contains the upper 16 bits (47:32) of the 128th 6-byte MAC address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_MSB 15 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_WIDTH 16 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_RESET 0xffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Mask Byte Control - mbc_0 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address127 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_MSB 24 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Mask Byte Control - mbc_1 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address127 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_MSB 25 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Mask Byte Control - mbc_2 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address127 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_MSB 26 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mask Byte Control - mbc_3 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address127 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_MSB 27 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Mask Byte Control - mbc_4 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address127 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_MSB 28 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Mask Byte Control - mbc_5 + * + * This array of bits are mask control bits for comparison of each of the MAC + * Address bytes. When masked, the MAC does not compare the corresponding byte of + * received DA or SA with the contents of MAC Address127 high and low registers. + * Each bit controls the masking of the bytes. You can filter a group of addresses + * (known as group address filtering) by masking one or more bytes of the address. + * + * The array index corresponds to the byte (e.g. index 0 is for bits 7:0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------------------ + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared) + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 + * + * Byte is unmasked (i.e. is compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_UNMSKED 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 + * + * Byte is masked (i.e. not compared) + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_MSB 29 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Source Address - sa + * + * When this bit is enabled, the MAC Address127[47:0] is used to compare with the + * SA fields of the received frame. When this bit is disabled, the MAC + * Address127[47:0] is used to compare with the DA fields of the received frame. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------- + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_END | 0x1 | MAC address compare enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA + * + * MAC address compare disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA + * + * MAC address compare enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_MSB 30 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Address Enable - ae + * + * When this bit is enabled, the address filter block uses the 128th MAC address + * for perfect filtering. When this bit is disabled, the address filter block + * ignores the address for filtering. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------- + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled + * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE + * + * Second MAC address filtering disabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE + * + * Second MAC address filtering enabled + */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_WIDTH 1 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_RESET 0x0 +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR127_HIGH. + */ +struct ALT_EMAC_GMAC_MAC_ADDR127_HIGH_s +{ + uint32_t addrhi : 16; /* MAC Address127 [47:32] */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t mbc_0 : 1; /* Mask Byte Control */ + uint32_t mbc_1 : 1; /* Mask Byte Control */ + uint32_t mbc_2 : 1; /* Mask Byte Control */ + uint32_t mbc_3 : 1; /* Mask Byte Control */ + uint32_t mbc_4 : 1; /* Mask Byte Control */ + uint32_t mbc_5 : 1; /* Mask Byte Control */ + uint32_t sa : 1; /* Source Address */ + uint32_t ae : 1; /* Address Enable */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR127_HIGH. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR127_HIGH_s ALT_EMAC_GMAC_MAC_ADDR127_HIGH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_OFST 0xb78 +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR127_HIGH_OFST)) + +/* + * Register : Register 735 (MAC Address127 Low Register) - MAC_Address127_Low + * + * The MAC Address127 Low register holds the lower 32 bits of the 128th 6-byte MAC + * address of the station. + * + * Note that all MAC Address Low registers (except MAC Address0 Low) have the same + * format. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | RW | 0xffffffff | MAC Address127 [31:0] + * + */ +/* + * Field : MAC Address127 [31:0] - addrlo + * + * This field contains the lower 32 bits of the 128th 6-byte MAC address. The + * content of this field is undefined until loaded by software after the + * initialization process. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_MSB 31 +/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_WIDTH 32 +/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_RESET 0xffffffff +/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO field value from a register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value suitable for setting the register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR127_LOW. + */ +struct ALT_EMAC_GMAC_MAC_ADDR127_LOW_s +{ + uint32_t addrlo : 32; /* MAC Address127 [31:0] */ +}; + +/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR127_LOW. */ +typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR127_LOW_s ALT_EMAC_GMAC_MAC_ADDR127_LOW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register from the beginning of the component. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_OFST 0xb7c +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register. */ +#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR127_LOW_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_EMAC_GMAC. + */ +struct ALT_EMAC_GMAC_s +{ + volatile ALT_EMAC_GMAC_MAC_CFG_t MAC_Configuration; /* ALT_EMAC_GMAC_MAC_CFG */ + volatile ALT_EMAC_GMAC_MAC_FRM_FLT_t MAC_Frame_Filter; /* ALT_EMAC_GMAC_MAC_FRM_FLT */ + volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_GMII_ADDR_t GMII_Address; /* ALT_EMAC_GMAC_GMII_ADDR */ + volatile ALT_EMAC_GMAC_GMII_DATA_t GMII_Data; /* ALT_EMAC_GMAC_GMII_DATA */ + volatile ALT_EMAC_GMAC_FLOW_CTL_t Flow_Control; /* ALT_EMAC_GMAC_FLOW_CTL */ + volatile ALT_EMAC_GMAC_VLAN_TAG_t VLAN_Tag; /* ALT_EMAC_GMAC_VLAN_TAG */ + volatile ALT_EMAC_GMAC_VER_t Version; /* ALT_EMAC_GMAC_VER */ + volatile ALT_EMAC_GMAC_DBG_t Debug; /* ALT_EMAC_GMAC_DBG */ + volatile uint32_t _pad_0x28_0x2f[2]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_LPI_CTL_STAT_t LPI_Control_Status; /* ALT_EMAC_GMAC_LPI_CTL_STAT */ + volatile ALT_EMAC_GMAC_LPI_TMRS_CTL_t LPI_Timers_Control; /* ALT_EMAC_GMAC_LPI_TMRS_CTL */ + volatile ALT_EMAC_GMAC_INT_STAT_t Interrupt_Status; /* ALT_EMAC_GMAC_INT_STAT */ + volatile ALT_EMAC_GMAC_INT_MSK_t Interrupt_Mask; /* ALT_EMAC_GMAC_INT_MSK */ + volatile ALT_EMAC_GMAC_MAC_ADDR0_HIGH_t MAC_Address0_High; /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR0_LOW_t MAC_Address0_Low; /* ALT_EMAC_GMAC_MAC_ADDR0_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR1_HIGH_t MAC_Address1_High; /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR1_LOW_t MAC_Address1_Low; /* ALT_EMAC_GMAC_MAC_ADDR1_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR2_HIGH_t MAC_Address2_High; /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR2_LOW_t MAC_Address2_Low; /* ALT_EMAC_GMAC_MAC_ADDR2_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR3_HIGH_t MAC_Address3_High; /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR3_LOW_t MAC_Address3_Low; /* ALT_EMAC_GMAC_MAC_ADDR3_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR4_HIGH_t MAC_Address4_High; /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR4_LOW_t MAC_Address4_Low; /* ALT_EMAC_GMAC_MAC_ADDR4_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR5_HIGH_t MAC_Address5_High; /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR5_LOW_t MAC_Address5_Low; /* ALT_EMAC_GMAC_MAC_ADDR5_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR6_HIGH_t MAC_Address6_High; /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR6_LOW_t MAC_Address6_Low; /* ALT_EMAC_GMAC_MAC_ADDR6_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR7_HIGH_t MAC_Address7_High; /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR7_LOW_t MAC_Address7_Low; /* ALT_EMAC_GMAC_MAC_ADDR7_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR8_HIGH_t MAC_Address8_High; /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR8_LOW_t MAC_Address8_Low; /* ALT_EMAC_GMAC_MAC_ADDR8_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR9_HIGH_t MAC_Address9_High; /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR9_LOW_t MAC_Address9_Low; /* ALT_EMAC_GMAC_MAC_ADDR9_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR10_HIGH_t MAC_Address10_High; /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR10_LOW_t MAC_Address10_Low; /* ALT_EMAC_GMAC_MAC_ADDR10_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR11_HIGH_t MAC_Address11_High; /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR11_LOW_t MAC_Address11_Low; /* ALT_EMAC_GMAC_MAC_ADDR11_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR12_HIGH_t MAC_Address12_High; /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR12_LOW_t MAC_Address12_Low; /* ALT_EMAC_GMAC_MAC_ADDR12_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR13_HIGH_t MAC_Address13_High; /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR13_LOW_t MAC_Address13_Low; /* ALT_EMAC_GMAC_MAC_ADDR13_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR14_HIGH_t MAC_Address14_High; /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR14_LOW_t MAC_Address14_Low; /* ALT_EMAC_GMAC_MAC_ADDR14_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR15_HIGH_t MAC_Address15_High; /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR15_LOW_t MAC_Address15_Low; /* ALT_EMAC_GMAC_MAC_ADDR15_LOW */ + volatile uint32_t _pad_0xc0_0xd7[6]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_MII_CTL_STAT_t SGMII_RGMII_SMII_Control_Status; /* ALT_EMAC_GMAC_MII_CTL_STAT */ + volatile uint32_t _pad_0xdc_0xff[9]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_MMC_CTL_t MMC_Control; /* ALT_EMAC_GMAC_MMC_CTL */ + volatile ALT_EMAC_GMAC_MMC_RX_INT_t MMC_Receive_Interrupt; /* ALT_EMAC_GMAC_MMC_RX_INT */ + volatile ALT_EMAC_GMAC_MMC_TX_INT_t MMC_Transmit_Interrupt; /* ALT_EMAC_GMAC_MMC_TX_INT */ + volatile ALT_EMAC_GMAC_MMC_RX_INT_MSK_t MMC_Receive_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK */ + volatile ALT_EMAC_GMAC_MMC_TX_INT_MSK_t MMC_Transmit_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK */ + volatile ALT_EMAC_GMAC_TXOCTETCOUNT_GB_t txoctetcount_gb; /* ALT_EMAC_GMAC_TXOCTETCOUNT_GB */ + volatile ALT_EMAC_GMAC_TXFRMCOUNT_GB_t txframecount_gb; /* ALT_EMAC_GMAC_TXFRMCOUNT_GB */ + volatile ALT_EMAC_GMAC_TXBCASTFRMS_G_t txbroadcastframes_g; /* ALT_EMAC_GMAC_TXBCASTFRMS_G */ + volatile ALT_EMAC_GMAC_TXMCASTFRMS_G_t txmulticastframes_g; /* ALT_EMAC_GMAC_TXMCASTFRMS_G */ + volatile ALT_EMAC_GMAC_TX64OCTETS_GB_t tx64octets_gb; /* ALT_EMAC_GMAC_TX64OCTETS_GB */ + volatile ALT_EMAC_GMAC_TX65TO127OCTETS_GB_t tx65to127octets_gb; /* ALT_EMAC_GMAC_TX65TO127OCTETS_GB */ + volatile ALT_EMAC_GMAC_TX128TO255OCTETS_GB_t tx128to255octets_gb; /* ALT_EMAC_GMAC_TX128TO255OCTETS_GB */ + volatile ALT_EMAC_GMAC_TX256TO511OCTETS_GB_t tx256to511octets_gb; /* ALT_EMAC_GMAC_TX256TO511OCTETS_GB */ + volatile ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_t tx512to1023octets_gb; /* ALT_EMAC_GMAC_TX512TO1023OCTETS_GB */ + volatile ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_t tx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB */ + volatile ALT_EMAC_GMAC_TXUNICASTFRMS_GB_t txunicastframes_gb; /* ALT_EMAC_GMAC_TXUNICASTFRMS_GB */ + volatile ALT_EMAC_GMAC_TXMCASTFRMS_GB_t txmulticastframes_gb; /* ALT_EMAC_GMAC_TXMCASTFRMS_GB */ + volatile ALT_EMAC_GMAC_TXBCASTFRMS_GB_t txbroadcastframes_gb; /* ALT_EMAC_GMAC_TXBCASTFRMS_GB */ + volatile ALT_EMAC_GMAC_TXUNDERFLOWERROR_t txunderflowerror; /* ALT_EMAC_GMAC_TXUNDERFLOWERROR */ + volatile ALT_EMAC_GMAC_TXSINGLECOL_G_t txsinglecol_g; /* ALT_EMAC_GMAC_TXSINGLECOL_G */ + volatile ALT_EMAC_GMAC_TXMULTICOL_G_t txmulticol_g; /* ALT_EMAC_GMAC_TXMULTICOL_G */ + volatile ALT_EMAC_GMAC_TXDEFERRED_t txdeferred; /* ALT_EMAC_GMAC_TXDEFERRED */ + volatile ALT_EMAC_GMAC_TXLATECOL_t txlatecol; /* ALT_EMAC_GMAC_TXLATECOL */ + volatile ALT_EMAC_GMAC_TXEXESSCOL_t txexesscol; /* ALT_EMAC_GMAC_TXEXESSCOL */ + volatile ALT_EMAC_GMAC_TXCARRIERERR_t txcarriererr; /* ALT_EMAC_GMAC_TXCARRIERERR */ + volatile ALT_EMAC_GMAC_TXOCTETCNT_t txoctetcnt; /* ALT_EMAC_GMAC_TXOCTETCNT */ + volatile ALT_EMAC_GMAC_TXFRMCOUNT_G_t txframecount_g; /* ALT_EMAC_GMAC_TXFRMCOUNT_G */ + volatile ALT_EMAC_GMAC_TXEXCESSDEF_t txexcessdef; /* ALT_EMAC_GMAC_TXEXCESSDEF */ + volatile ALT_EMAC_GMAC_TXPAUSEFRMS_t txpauseframes; /* ALT_EMAC_GMAC_TXPAUSEFRMS */ + volatile ALT_EMAC_GMAC_TXVLANFRMS_G_t txvlanframes_g; /* ALT_EMAC_GMAC_TXVLANFRMS_G */ + volatile ALT_EMAC_GMAC_TXOVERSIZE_G_t txoversize_g; /* ALT_EMAC_GMAC_TXOVERSIZE_G */ + volatile uint32_t _pad_0x17c_0x17f; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_RXFRMCOUNT_GB_t rxframecount_gb; /* ALT_EMAC_GMAC_RXFRMCOUNT_GB */ + volatile ALT_EMAC_GMAC_RXOCTETCOUNT_GB_t rxoctetcount_gb; /* ALT_EMAC_GMAC_RXOCTETCOUNT_GB */ + volatile ALT_EMAC_GMAC_RXOCTETCOUNT_G_t rxoctetcount_g; /* ALT_EMAC_GMAC_RXOCTETCOUNT_G */ + volatile ALT_EMAC_GMAC_RXBCASTFRMS_G_t rxbroadcastframes_g; /* ALT_EMAC_GMAC_RXBCASTFRMS_G */ + volatile ALT_EMAC_GMAC_RXMCASTFRMS_G_t rxmulticastframes_g; /* ALT_EMAC_GMAC_RXMCASTFRMS_G */ + volatile ALT_EMAC_GMAC_RXCRCERROR_t rxcrcerror; /* ALT_EMAC_GMAC_RXCRCERROR */ + volatile ALT_EMAC_GMAC_RXALIGNMENTERROR_t rxalignmenterror; /* ALT_EMAC_GMAC_RXALIGNMENTERROR */ + volatile ALT_EMAC_GMAC_RXRUNTERROR_t rxrunterror; /* ALT_EMAC_GMAC_RXRUNTERROR */ + volatile ALT_EMAC_GMAC_RXJABBERERROR_t rxjabbererror; /* ALT_EMAC_GMAC_RXJABBERERROR */ + volatile ALT_EMAC_GMAC_RXUNDERSIZE_G_t rxundersize_g; /* ALT_EMAC_GMAC_RXUNDERSIZE_G */ + volatile ALT_EMAC_GMAC_RXOVERSIZE_G_t rxoversize_g; /* ALT_EMAC_GMAC_RXOVERSIZE_G */ + volatile ALT_EMAC_GMAC_RX64OCTETS_GB_t rx64octets_gb; /* ALT_EMAC_GMAC_RX64OCTETS_GB */ + volatile ALT_EMAC_GMAC_RX65TO127OCTETS_GB_t rx65to127octets_gb; /* ALT_EMAC_GMAC_RX65TO127OCTETS_GB */ + volatile ALT_EMAC_GMAC_RX128TO255OCTETS_GB_t rx128to255octets_gb; /* ALT_EMAC_GMAC_RX128TO255OCTETS_GB */ + volatile ALT_EMAC_GMAC_RX256TO511OCTETS_GB_t rx256to511octets_gb; /* ALT_EMAC_GMAC_RX256TO511OCTETS_GB */ + volatile ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_t rx512to1023octets_gb; /* ALT_EMAC_GMAC_RX512TO1023OCTETS_GB */ + volatile ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_t rx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB */ + volatile ALT_EMAC_GMAC_RXUNICASTFRMS_G_t rxunicastframes_g; /* ALT_EMAC_GMAC_RXUNICASTFRMS_G */ + volatile ALT_EMAC_GMAC_RXLENERROR_t rxlengtherror; /* ALT_EMAC_GMAC_RXLENERROR */ + volatile ALT_EMAC_GMAC_RXOUTOFRANGETYPE_t rxoutofrangetype; /* ALT_EMAC_GMAC_RXOUTOFRANGETYPE */ + volatile ALT_EMAC_GMAC_RXPAUSEFRMS_t rxpauseframes; /* ALT_EMAC_GMAC_RXPAUSEFRMS */ + volatile ALT_EMAC_GMAC_RXFIFOOVF_t rxfifooverflow; /* ALT_EMAC_GMAC_RXFIFOOVF */ + volatile ALT_EMAC_GMAC_RXVLANFRMS_GB_t rxvlanframes_gb; /* ALT_EMAC_GMAC_RXVLANFRMS_GB */ + volatile ALT_EMAC_GMAC_RXWDERROR_t rxwatchdogerror; /* ALT_EMAC_GMAC_RXWDERROR */ + volatile ALT_EMAC_GMAC_RXRCVERROR_t rxrcverror; /* ALT_EMAC_GMAC_RXRCVERROR */ + volatile ALT_EMAC_GMAC_RXCTLFRMS_G_t rxctrlframes_g; /* ALT_EMAC_GMAC_RXCTLFRMS_G */ + volatile uint32_t _pad_0x1e8_0x1ff[6]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_t MMC_IPC_Receive_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK */ + volatile uint32_t _pad_0x204_0x207; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_MMC_IPC_RX_INT_t MMC_IPC_Receive_Interrupt; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT */ + volatile uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_RXIPV4_GD_FRMS_t rxipv4_gd_frms; /* ALT_EMAC_GMAC_RXIPV4_GD_FRMS */ + volatile ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_t rxipv4_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS */ + volatile ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_t rxipv4_nopay_frms; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS */ + volatile ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_t rxipv4_frag_frms; /* ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS */ + volatile ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_t rxipv4_udsbl_frms; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS */ + volatile ALT_EMAC_GMAC_RXIPV6_GD_FRMS_t rxipv6_gd_frms; /* ALT_EMAC_GMAC_RXIPV6_GD_FRMS */ + volatile ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_t rxipv6_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS */ + volatile ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_t rxipv6_nopay_frms; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS */ + volatile ALT_EMAC_GMAC_RXUDP_GD_FRMS_t rxudp_gd_frms; /* ALT_EMAC_GMAC_RXUDP_GD_FRMS */ + volatile ALT_EMAC_GMAC_RXUDP_ERR_FRMS_t rxudp_err_frms; /* ALT_EMAC_GMAC_RXUDP_ERR_FRMS */ + volatile ALT_EMAC_GMAC_RXTCP_GD_FRMS_t rxtcp_gd_frms; /* ALT_EMAC_GMAC_RXTCP_GD_FRMS */ + volatile ALT_EMAC_GMAC_RXTCP_ERR_FRMS_t rxtcp_err_frms; /* ALT_EMAC_GMAC_RXTCP_ERR_FRMS */ + volatile ALT_EMAC_GMAC_RXICMP_GD_FRMS_t rxicmp_gd_frms; /* ALT_EMAC_GMAC_RXICMP_GD_FRMS */ + volatile ALT_EMAC_GMAC_RXICMP_ERR_FRMS_t rxicmp_err_frms; /* ALT_EMAC_GMAC_RXICMP_ERR_FRMS */ + volatile uint32_t _pad_0x248_0x24f[2]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_t rxipv4_gd_octets; /* ALT_EMAC_GMAC_RXIPV4_GD_OCTETS */ + volatile ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_t rxipv4_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS */ + volatile ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_t rxipv4_nopay_octets; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS */ + volatile ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_t rxipv4_frag_octets; /* ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS */ + volatile ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_t rxipv4_udsbl_octets; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS */ + volatile ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_t rxipv6_gd_octets; /* ALT_EMAC_GMAC_RXIPV6_GD_OCTETS */ + volatile ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_t rxipv6_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS */ + volatile ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_t rxipv6_nopay_octets; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS */ + volatile ALT_EMAC_GMAC_RXUDP_GD_OCTETS_t rxudp_gd_octets; /* ALT_EMAC_GMAC_RXUDP_GD_OCTETS */ + volatile ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_t rxudp_err_octets; /* ALT_EMAC_GMAC_RXUDP_ERR_OCTETS */ + volatile ALT_EMAC_GMAC_RXTCP_GD_OCTETS_t rxtcp_gd_octets; /* ALT_EMAC_GMAC_RXTCP_GD_OCTETS */ + volatile ALT_EMAC_GMAC_RXTCPERROCTETS_t rxtcperroctets; /* ALT_EMAC_GMAC_RXTCPERROCTETS */ + volatile ALT_EMAC_GMAC_RXICMP_GD_OCTETS_t rxicmp_gd_octets; /* ALT_EMAC_GMAC_RXICMP_GD_OCTETS */ + volatile ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_t rxicmp_err_octets; /* ALT_EMAC_GMAC_RXICMP_ERR_OCTETS */ + volatile uint32_t _pad_0x288_0x3ff[94]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_L3_L4_CTL0_t L3_L4_Control0; /* ALT_EMAC_GMAC_L3_L4_CTL0 */ + volatile ALT_EMAC_GMAC_LYR4_ADDR0_t Layer4_Address0; /* ALT_EMAC_GMAC_LYR4_ADDR0 */ + volatile uint32_t _pad_0x408_0x40f[2]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_LYR3_ADDR0_REG0_t Layer3_Addr0_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG0 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR1_REG0_t Layer3_Addr1_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG0 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR2_REG0_t Layer3_Addr2_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG0 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR3_REG0_t Layer3_Addr3_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG0 */ + volatile uint32_t _pad_0x420_0x42f[4]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_L3_L4_CTL1_t L3_L4_Control1; /* ALT_EMAC_GMAC_L3_L4_CTL1 */ + volatile ALT_EMAC_GMAC_LYR4_ADDR1_t Layer4_Address1; /* ALT_EMAC_GMAC_LYR4_ADDR1 */ + volatile uint32_t _pad_0x438_0x43f[2]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_LYR3_ADDR0_REG1_t Layer3_Addr0_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG1 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR1_REG1_t Layer3_Addr1_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG1 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR2_REG1_t Layer3_Addr2_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG1 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR3_REG1_t Layer3_Addr3_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG1 */ + volatile uint32_t _pad_0x450_0x45f[4]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_L3_L4_CTL2_t L3_L4_Control2; /* ALT_EMAC_GMAC_L3_L4_CTL2 */ + volatile ALT_EMAC_GMAC_LYR4_ADDR2_t Layer4_Address2; /* ALT_EMAC_GMAC_LYR4_ADDR2 */ + volatile uint32_t _pad_0x468_0x46f[2]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_LYR3_ADDR0_REG2_t Layer3_Addr0_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG2 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR1_REG2_t Layer3_Addr1_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG2 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR2_REG2_t Layer3_Addr2_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG2 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR3_REG2_t Layer3_Addr3_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG2 */ + volatile uint32_t _pad_0x480_0x48f[4]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_L3_L4_CTL3_t L3_L4_Control3; /* ALT_EMAC_GMAC_L3_L4_CTL3 */ + volatile ALT_EMAC_GMAC_LYR4_ADDR3_t Layer4_Address3; /* ALT_EMAC_GMAC_LYR4_ADDR3 */ + volatile uint32_t _pad_0x498_0x49f[2]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_LYR3_ADDR0_REG3_t Layer3_Addr0_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG3 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR1_REG3_t Layer3_Addr1_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG3 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR2_REG3_t Layer3_Addr2_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG3 */ + volatile ALT_EMAC_GMAC_LYR3_ADDR3_REG3_t Layer3_Addr3_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG3 */ + volatile uint32_t _pad_0x4b0_0x4ff[20]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_HASH_TABLE_REG0_t Hash_Table_Reg0; /* ALT_EMAC_GMAC_HASH_TABLE_REG0 */ + volatile ALT_EMAC_GMAC_HASH_TABLE_REG1_t Hash_Table_Reg1; /* ALT_EMAC_GMAC_HASH_TABLE_REG1 */ + volatile ALT_EMAC_GMAC_HASH_TABLE_REG2_t Hash_Table_Reg2; /* ALT_EMAC_GMAC_HASH_TABLE_REG2 */ + volatile ALT_EMAC_GMAC_HASH_TABLE_REG3_t Hash_Table_Reg3; /* ALT_EMAC_GMAC_HASH_TABLE_REG3 */ + volatile ALT_EMAC_GMAC_HASH_TABLE_REG4_t Hash_Table_Reg4; /* ALT_EMAC_GMAC_HASH_TABLE_REG4 */ + volatile ALT_EMAC_GMAC_HASH_TABLE_REG5_t Hash_Table_Reg5; /* ALT_EMAC_GMAC_HASH_TABLE_REG5 */ + volatile ALT_EMAC_GMAC_HASH_TABLE_REG6_t Hash_Table_Reg6; /* ALT_EMAC_GMAC_HASH_TABLE_REG6 */ + volatile ALT_EMAC_GMAC_HASH_TABLE_REG7_t Hash_Table_Reg7; /* ALT_EMAC_GMAC_HASH_TABLE_REG7 */ + volatile uint32_t _pad_0x520_0x583[25]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_VLAN_INCL_REG_t VLAN_Incl_Reg; /* ALT_EMAC_GMAC_VLAN_INCL_REG */ + volatile ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_t VLAN_Hash_Table_Reg; /* ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG */ + volatile uint32_t _pad_0x58c_0x6ff[93]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_TS_CTL_t Timestamp_Control; /* ALT_EMAC_GMAC_TS_CTL */ + volatile ALT_EMAC_GMAC_SUB_SEC_INCREMENT_t Sub_Second_Increment; /* ALT_EMAC_GMAC_SUB_SEC_INCREMENT */ + volatile ALT_EMAC_GMAC_SYS_TIME_SECS_t System_Time_Seconds; /* ALT_EMAC_GMAC_SYS_TIME_SECS */ + volatile ALT_EMAC_GMAC_SYS_TIME_NANOSECS_t System_Time_Nanoseconds; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS */ + volatile ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_t System_Time_Seconds_Update; /* ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE */ + volatile ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_t System_Time_Nanoseconds_Update; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE */ + volatile ALT_EMAC_GMAC_TS_ADDEND_t Timestamp_Addend; /* ALT_EMAC_GMAC_TS_ADDEND */ + volatile ALT_EMAC_GMAC_TGT_TIME_SECS_t Target_Time_Seconds; /* ALT_EMAC_GMAC_TGT_TIME_SECS */ + volatile ALT_EMAC_GMAC_TGT_TIME_NANOSECS_t Target_Time_Nanoseconds; /* ALT_EMAC_GMAC_TGT_TIME_NANOSECS */ + volatile ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_t System_Time_Higher_Word_Seconds; /* ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS */ + volatile ALT_EMAC_GMAC_TS_STAT_t Timestamp_Status; /* ALT_EMAC_GMAC_TS_STAT */ + volatile ALT_EMAC_GMAC_PPS_CTL_t PPS_Control; /* ALT_EMAC_GMAC_PPS_CTL */ + volatile ALT_EMAC_GMAC_AUX_TS_NANOSECS_t Auxiliary_Timestamp_Nanoseconds; /* ALT_EMAC_GMAC_AUX_TS_NANOSECS */ + volatile ALT_EMAC_GMAC_AUX_TS_SECS_t Auxiliary_Timestamp_Seconds; /* ALT_EMAC_GMAC_AUX_TS_SECS */ + volatile uint32_t _pad_0x738_0x75f[10]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_PPS0_INTERVAL_t PPS0_Interval; /* ALT_EMAC_GMAC_PPS0_INTERVAL */ + volatile ALT_EMAC_GMAC_PPS0_WIDTH_t PPS0_Width; /* ALT_EMAC_GMAC_PPS0_WIDTH */ + volatile uint32_t _pad_0x768_0x7ff[38]; /* *UNDEFINED* */ + volatile ALT_EMAC_GMAC_MAC_ADDR16_HIGH_t MAC_Address16_High; /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR16_LOW_t MAC_Address16_Low; /* ALT_EMAC_GMAC_MAC_ADDR16_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR17_HIGH_t MAC_Address17_High; /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR17_LOW_t MAC_Address17_Low; /* ALT_EMAC_GMAC_MAC_ADDR17_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR18_HIGH_t MAC_Address18_High; /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR18_LOW_t MAC_Address18_Low; /* ALT_EMAC_GMAC_MAC_ADDR18_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR19_HIGH_t MAC_Address19_High; /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR19_LOW_t MAC_Address19_Low; /* ALT_EMAC_GMAC_MAC_ADDR19_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR20_HIGH_t MAC_Address20_High; /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR20_LOW_t MAC_Address20_Low; /* ALT_EMAC_GMAC_MAC_ADDR20_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR21_HIGH_t MAC_Address21_High; /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR21_LOW_t MAC_Address21_Low; /* ALT_EMAC_GMAC_MAC_ADDR21_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR22_HIGH_t MAC_Address22_High; /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR22_LOW_t MAC_Address22_Low; /* ALT_EMAC_GMAC_MAC_ADDR22_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR23_HIGH_t MAC_Address23_High; /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR23_LOW_t MAC_Address23_Low; /* ALT_EMAC_GMAC_MAC_ADDR23_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR24_HIGH_t MAC_Address24_High; /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR24_LOW_t MAC_Address24_Low; /* ALT_EMAC_GMAC_MAC_ADDR24_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR25_HIGH_t MAC_Address25_High; /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR25_LOW_t MAC_Address25_Low; /* ALT_EMAC_GMAC_MAC_ADDR25_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR26_HIGH_t MAC_Address26_High; /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR26_LOW_t MAC_Address26_Low; /* ALT_EMAC_GMAC_MAC_ADDR26_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR27_HIGH_t MAC_Address27_High; /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR27_LOW_t MAC_Address27_Low; /* ALT_EMAC_GMAC_MAC_ADDR27_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR28_HIGH_t MAC_Address28_High; /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR28_LOW_t MAC_Address28_Low; /* ALT_EMAC_GMAC_MAC_ADDR28_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR29_HIGH_t MAC_Address29_High; /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR29_LOW_t MAC_Address29_Low; /* ALT_EMAC_GMAC_MAC_ADDR29_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR30_HIGH_t MAC_Address30_High; /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR30_LOW_t MAC_Address30_Low; /* ALT_EMAC_GMAC_MAC_ADDR30_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR31_HIGH_t MAC_Address31_High; /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR31_LOW_t MAC_Address31_Low; /* ALT_EMAC_GMAC_MAC_ADDR31_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR32_HIGH_t MAC_Address32_High; /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR32_LOW_t MAC_Address32_Low; /* ALT_EMAC_GMAC_MAC_ADDR32_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR33_HIGH_t MAC_Address33_High; /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR33_LOW_t MAC_Address33_Low; /* ALT_EMAC_GMAC_MAC_ADDR33_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR34_HIGH_t MAC_Address34_High; /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR34_LOW_t MAC_Address34_Low; /* ALT_EMAC_GMAC_MAC_ADDR34_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR35_HIGH_t MAC_Address35_High; /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR35_LOW_t MAC_Address35_Low; /* ALT_EMAC_GMAC_MAC_ADDR35_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR36_HIGH_t MAC_Address36_High; /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR36_LOW_t MAC_Address36_Low; /* ALT_EMAC_GMAC_MAC_ADDR36_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR37_HIGH_t MAC_Address37_High; /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR37_LOW_t MAC_Address37_Low; /* ALT_EMAC_GMAC_MAC_ADDR37_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR38_HIGH_t MAC_Address38_High; /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR38_LOW_t MAC_Address38_Low; /* ALT_EMAC_GMAC_MAC_ADDR38_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR39_HIGH_t MAC_Address39_High; /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR39_LOW_t MAC_Address39_Low; /* ALT_EMAC_GMAC_MAC_ADDR39_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR40_HIGH_t MAC_Address40_High; /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR40_LOW_t MAC_Address40_Low; /* ALT_EMAC_GMAC_MAC_ADDR40_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR41_HIGH_t MAC_Address41_High; /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR41_LOW_t MAC_Address41_Low; /* ALT_EMAC_GMAC_MAC_ADDR41_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR42_HIGH_t MAC_Address42_High; /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR42_LOW_t MAC_Address42_Low; /* ALT_EMAC_GMAC_MAC_ADDR42_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR43_HIGH_t MAC_Address43_High; /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR43_LOW_t MAC_Address43_Low; /* ALT_EMAC_GMAC_MAC_ADDR43_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR44_HIGH_t MAC_Address44_High; /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR44_LOW_t MAC_Address44_Low; /* ALT_EMAC_GMAC_MAC_ADDR44_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR45_HIGH_t MAC_Address45_High; /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR45_LOW_t MAC_Address45_Low; /* ALT_EMAC_GMAC_MAC_ADDR45_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR46_HIGH_t MAC_Address46_High; /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR46_LOW_t MAC_Address46_Low; /* ALT_EMAC_GMAC_MAC_ADDR46_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR47_HIGH_t MAC_Address47_High; /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR47_LOW_t MAC_Address47_Low; /* ALT_EMAC_GMAC_MAC_ADDR47_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR48_HIGH_t MAC_Address48_High; /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR48_LOW_t MAC_Address48_Low; /* ALT_EMAC_GMAC_MAC_ADDR48_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR49_HIGH_t MAC_Address49_High; /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR49_LOW_t MAC_Address49_Low; /* ALT_EMAC_GMAC_MAC_ADDR49_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR50_HIGH_t MAC_Address50_High; /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR50_LOW_t MAC_Address50_Low; /* ALT_EMAC_GMAC_MAC_ADDR50_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR51_HIGH_t MAC_Address51_High; /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR51_LOW_t MAC_Address51_Low; /* ALT_EMAC_GMAC_MAC_ADDR51_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR52_HIGH_t MAC_Address52_High; /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR52_LOW_t MAC_Address52_Low; /* ALT_EMAC_GMAC_MAC_ADDR52_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR53_HIGH_t MAC_Address53_High; /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR53_LOW_t MAC_Address53_Low; /* ALT_EMAC_GMAC_MAC_ADDR53_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR54_HIGH_t MAC_Address54_High; /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR54_LOW_t MAC_Address54_Low; /* ALT_EMAC_GMAC_MAC_ADDR54_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR55_HIGH_t MAC_Address55_High; /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR55_LOW_t MAC_Address55_Low; /* ALT_EMAC_GMAC_MAC_ADDR55_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR56_HIGH_t MAC_Address56_High; /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR56_LOW_t MAC_Address56_Low; /* ALT_EMAC_GMAC_MAC_ADDR56_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR57_HIGH_t MAC_Address57_High; /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR57_LOW_t MAC_Address57_Low; /* ALT_EMAC_GMAC_MAC_ADDR57_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR58_HIGH_t MAC_Address58_High; /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR58_LOW_t MAC_Address58_Low; /* ALT_EMAC_GMAC_MAC_ADDR58_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR59_HIGH_t MAC_Address59_High; /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR59_LOW_t MAC_Address59_Low; /* ALT_EMAC_GMAC_MAC_ADDR59_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR60_HIGH_t MAC_Address60_High; /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR60_LOW_t MAC_Address60_Low; /* ALT_EMAC_GMAC_MAC_ADDR60_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR61_HIGH_t MAC_Address61_High; /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR61_LOW_t MAC_Address61_Low; /* ALT_EMAC_GMAC_MAC_ADDR61_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR62_HIGH_t MAC_Address62_High; /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR62_LOW_t MAC_Address62_Low; /* ALT_EMAC_GMAC_MAC_ADDR62_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR63_HIGH_t MAC_Address63_High; /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR63_LOW_t MAC_Address63_Low; /* ALT_EMAC_GMAC_MAC_ADDR63_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR64_HIGH_t MAC_Address64_High; /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR64_LOW_t MAC_Address64_Low; /* ALT_EMAC_GMAC_MAC_ADDR64_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR65_HIGH_t MAC_Address65_High; /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR65_LOW_t MAC_Address65_Low; /* ALT_EMAC_GMAC_MAC_ADDR65_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR66_HIGH_t MAC_Address66_High; /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR66_LOW_t MAC_Address66_Low; /* ALT_EMAC_GMAC_MAC_ADDR66_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR67_HIGH_t MAC_Address67_High; /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR67_LOW_t MAC_Address67_Low; /* ALT_EMAC_GMAC_MAC_ADDR67_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR68_HIGH_t MAC_Address68_High; /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR68_LOW_t MAC_Address68_Low; /* ALT_EMAC_GMAC_MAC_ADDR68_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR69_HIGH_t MAC_Address69_High; /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR69_LOW_t MAC_Address69_Low; /* ALT_EMAC_GMAC_MAC_ADDR69_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR70_HIGH_t MAC_Address70_High; /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR70_LOW_t MAC_Address70_Low; /* ALT_EMAC_GMAC_MAC_ADDR70_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR71_HIGH_t MAC_Address71_High; /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR71_LOW_t MAC_Address71_Low; /* ALT_EMAC_GMAC_MAC_ADDR71_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR72_HIGH_t MAC_Address72_High; /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR72_LOW_t MAC_Address72_Low; /* ALT_EMAC_GMAC_MAC_ADDR72_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR73_HIGH_t MAC_Address73_High; /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR73_LOW_t MAC_Address73_Low; /* ALT_EMAC_GMAC_MAC_ADDR73_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR74_HIGH_t MAC_Address74_High; /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR74_LOW_t MAC_Address74_Low; /* ALT_EMAC_GMAC_MAC_ADDR74_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR75_HIGH_t MAC_Address75_High; /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR75_LOW_t MAC_Address75_Low; /* ALT_EMAC_GMAC_MAC_ADDR75_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR76_HIGH_t MAC_Address76_High; /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR76_LOW_t MAC_Address76_Low; /* ALT_EMAC_GMAC_MAC_ADDR76_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR77_HIGH_t MAC_Address77_High; /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR77_LOW_t MAC_Address77_Low; /* ALT_EMAC_GMAC_MAC_ADDR77_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR78_HIGH_t MAC_Address78_High; /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR78_LOW_t MAC_Address78_Low; /* ALT_EMAC_GMAC_MAC_ADDR78_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR79_HIGH_t MAC_Address79_High; /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR79_LOW_t MAC_Address79_Low; /* ALT_EMAC_GMAC_MAC_ADDR79_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR80_HIGH_t MAC_Address80_High; /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR80_LOW_t MAC_Address80_Low; /* ALT_EMAC_GMAC_MAC_ADDR80_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR81_HIGH_t MAC_Address81_High; /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR81_LOW_t MAC_Address81_Low; /* ALT_EMAC_GMAC_MAC_ADDR81_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR82_HIGH_t MAC_Address82_High; /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR82_LOW_t MAC_Address82_Low; /* ALT_EMAC_GMAC_MAC_ADDR82_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR83_HIGH_t MAC_Address83_High; /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR83_LOW_t MAC_Address83_Low; /* ALT_EMAC_GMAC_MAC_ADDR83_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR84_HIGH_t MAC_Address84_High; /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR84_LOW_t MAC_Address84_Low; /* ALT_EMAC_GMAC_MAC_ADDR84_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR85_HIGH_t MAC_Address85_High; /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR85_LOW_t MAC_Address85_Low; /* ALT_EMAC_GMAC_MAC_ADDR85_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR86_HIGH_t MAC_Address86_High; /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR86_LOW_t MAC_Address86_Low; /* ALT_EMAC_GMAC_MAC_ADDR86_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR87_HIGH_t MAC_Address87_High; /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR87_LOW_t MAC_Address87_Low; /* ALT_EMAC_GMAC_MAC_ADDR87_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR88_HIGH_t MAC_Address88_High; /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR88_LOW_t MAC_Address88_Low; /* ALT_EMAC_GMAC_MAC_ADDR88_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR89_HIGH_t MAC_Address89_High; /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR89_LOW_t MAC_Address89_Low; /* ALT_EMAC_GMAC_MAC_ADDR89_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR90_HIGH_t MAC_Address90_High; /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR90_LOW_t MAC_Address90_Low; /* ALT_EMAC_GMAC_MAC_ADDR90_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR91_HIGH_t MAC_Address91_High; /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR91_LOW_t MAC_Address91_Low; /* ALT_EMAC_GMAC_MAC_ADDR91_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR92_HIGH_t MAC_Address92_High; /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR92_LOW_t MAC_Address92_Low; /* ALT_EMAC_GMAC_MAC_ADDR92_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR93_HIGH_t MAC_Address93_High; /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR93_LOW_t MAC_Address93_Low; /* ALT_EMAC_GMAC_MAC_ADDR93_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR94_HIGH_t MAC_Address94_High; /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR94_LOW_t MAC_Address94_Low; /* ALT_EMAC_GMAC_MAC_ADDR94_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR95_HIGH_t MAC_Address95_High; /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR95_LOW_t MAC_Address95_Low; /* ALT_EMAC_GMAC_MAC_ADDR95_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR96_HIGH_t MAC_Address96_High; /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR96_LOW_t MAC_Address96_Low; /* ALT_EMAC_GMAC_MAC_ADDR96_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR97_HIGH_t MAC_Address97_High; /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR97_LOW_t MAC_Address97_Low; /* ALT_EMAC_GMAC_MAC_ADDR97_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR98_HIGH_t MAC_Address98_High; /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR98_LOW_t MAC_Address98_Low; /* ALT_EMAC_GMAC_MAC_ADDR98_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR99_HIGH_t MAC_Address99_High; /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR99_LOW_t MAC_Address99_Low; /* ALT_EMAC_GMAC_MAC_ADDR99_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR100_HIGH_t MAC_Address100_High; /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR100_LOW_t MAC_Address100_Low; /* ALT_EMAC_GMAC_MAC_ADDR100_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR101_HIGH_t MAC_Address101_High; /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR101_LOW_t MAC_Address101_Low; /* ALT_EMAC_GMAC_MAC_ADDR101_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR102_HIGH_t MAC_Address102_High; /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR102_LOW_t MAC_Address102_Low; /* ALT_EMAC_GMAC_MAC_ADDR102_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR103_HIGH_t MAC_Address103_High; /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR103_LOW_t MAC_Address103_Low; /* ALT_EMAC_GMAC_MAC_ADDR103_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR104_HIGH_t MAC_Address104_High; /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR104_LOW_t MAC_Address104_Low; /* ALT_EMAC_GMAC_MAC_ADDR104_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR105_HIGH_t MAC_Address105_High; /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR105_LOW_t MAC_Address105_Low; /* ALT_EMAC_GMAC_MAC_ADDR105_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR106_HIGH_t MAC_Address106_High; /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR106_LOW_t MAC_Address106_Low; /* ALT_EMAC_GMAC_MAC_ADDR106_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR107_HIGH_t MAC_Address107_High; /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR107_LOW_t MAC_Address107_Low; /* ALT_EMAC_GMAC_MAC_ADDR107_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR108_HIGH_t MAC_Address108_High; /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR108_LOW_t MAC_Address108_Low; /* ALT_EMAC_GMAC_MAC_ADDR108_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR109_HIGH_t MAC_Address109_High; /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR109_LOW_t MAC_Address109_Low; /* ALT_EMAC_GMAC_MAC_ADDR109_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR110_HIGH_t MAC_Address110_High; /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR110_LOW_t MAC_Address110_Low; /* ALT_EMAC_GMAC_MAC_ADDR110_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR111_HIGH_t MAC_Address111_High; /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR111_LOW_t MAC_Address111_Low; /* ALT_EMAC_GMAC_MAC_ADDR111_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR112_HIGH_t MAC_Address112_High; /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR112_LOW_t MAC_Address112_Low; /* ALT_EMAC_GMAC_MAC_ADDR112_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR113_HIGH_t MAC_Address113_High; /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR113_LOW_t MAC_Address113_Low; /* ALT_EMAC_GMAC_MAC_ADDR113_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR114_HIGH_t MAC_Address114_High; /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR114_LOW_t MAC_Address114_Low; /* ALT_EMAC_GMAC_MAC_ADDR114_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR115_HIGH_t MAC_Address115_High; /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR115_LOW_t MAC_Address115_Low; /* ALT_EMAC_GMAC_MAC_ADDR115_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR116_HIGH_t MAC_Address116_High; /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR116_LOW_t MAC_Address116_Low; /* ALT_EMAC_GMAC_MAC_ADDR116_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR117_HIGH_t MAC_Address117_High; /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR117_LOW_t MAC_Address117_Low; /* ALT_EMAC_GMAC_MAC_ADDR117_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR118_HIGH_t MAC_Address118_High; /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR118_LOW_t MAC_Address118_Low; /* ALT_EMAC_GMAC_MAC_ADDR118_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR119_HIGH_t MAC_Address119_High; /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR119_LOW_t MAC_Address119_Low; /* ALT_EMAC_GMAC_MAC_ADDR119_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR120_HIGH_t MAC_Address120_High; /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR120_LOW_t MAC_Address120_Low; /* ALT_EMAC_GMAC_MAC_ADDR120_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR121_HIGH_t MAC_Address121_High; /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR121_LOW_t MAC_Address121_Low; /* ALT_EMAC_GMAC_MAC_ADDR121_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR122_HIGH_t MAC_Address122_High; /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR122_LOW_t MAC_Address122_Low; /* ALT_EMAC_GMAC_MAC_ADDR122_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR123_HIGH_t MAC_Address123_High; /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR123_LOW_t MAC_Address123_Low; /* ALT_EMAC_GMAC_MAC_ADDR123_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR124_HIGH_t MAC_Address124_High; /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR124_LOW_t MAC_Address124_Low; /* ALT_EMAC_GMAC_MAC_ADDR124_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR125_HIGH_t MAC_Address125_High; /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR125_LOW_t MAC_Address125_Low; /* ALT_EMAC_GMAC_MAC_ADDR125_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR126_HIGH_t MAC_Address126_High; /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR126_LOW_t MAC_Address126_Low; /* ALT_EMAC_GMAC_MAC_ADDR126_LOW */ + volatile ALT_EMAC_GMAC_MAC_ADDR127_HIGH_t MAC_Address127_High; /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH */ + volatile ALT_EMAC_GMAC_MAC_ADDR127_LOW_t MAC_Address127_Low; /* ALT_EMAC_GMAC_MAC_ADDR127_LOW */ +}; + +/* The typedef declaration for register group ALT_EMAC_GMAC. */ +typedef volatile struct ALT_EMAC_GMAC_s ALT_EMAC_GMAC_t; +/* The struct declaration for the raw register contents of register group ALT_EMAC_GMAC. */ +struct ALT_EMAC_GMAC_raw_s +{ + volatile uint32_t MAC_Configuration; /* ALT_EMAC_GMAC_MAC_CFG */ + volatile uint32_t MAC_Frame_Filter; /* ALT_EMAC_GMAC_MAC_FRM_FLT */ + volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ + volatile uint32_t GMII_Address; /* ALT_EMAC_GMAC_GMII_ADDR */ + volatile uint32_t GMII_Data; /* ALT_EMAC_GMAC_GMII_DATA */ + volatile uint32_t Flow_Control; /* ALT_EMAC_GMAC_FLOW_CTL */ + volatile uint32_t VLAN_Tag; /* ALT_EMAC_GMAC_VLAN_TAG */ + volatile uint32_t Version; /* ALT_EMAC_GMAC_VER */ + volatile uint32_t Debug; /* ALT_EMAC_GMAC_DBG */ + volatile uint32_t _pad_0x28_0x2f[2]; /* *UNDEFINED* */ + volatile uint32_t LPI_Control_Status; /* ALT_EMAC_GMAC_LPI_CTL_STAT */ + volatile uint32_t LPI_Timers_Control; /* ALT_EMAC_GMAC_LPI_TMRS_CTL */ + volatile uint32_t Interrupt_Status; /* ALT_EMAC_GMAC_INT_STAT */ + volatile uint32_t Interrupt_Mask; /* ALT_EMAC_GMAC_INT_MSK */ + volatile uint32_t MAC_Address0_High; /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH */ + volatile uint32_t MAC_Address0_Low; /* ALT_EMAC_GMAC_MAC_ADDR0_LOW */ + volatile uint32_t MAC_Address1_High; /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH */ + volatile uint32_t MAC_Address1_Low; /* ALT_EMAC_GMAC_MAC_ADDR1_LOW */ + volatile uint32_t MAC_Address2_High; /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH */ + volatile uint32_t MAC_Address2_Low; /* ALT_EMAC_GMAC_MAC_ADDR2_LOW */ + volatile uint32_t MAC_Address3_High; /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH */ + volatile uint32_t MAC_Address3_Low; /* ALT_EMAC_GMAC_MAC_ADDR3_LOW */ + volatile uint32_t MAC_Address4_High; /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH */ + volatile uint32_t MAC_Address4_Low; /* ALT_EMAC_GMAC_MAC_ADDR4_LOW */ + volatile uint32_t MAC_Address5_High; /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH */ + volatile uint32_t MAC_Address5_Low; /* ALT_EMAC_GMAC_MAC_ADDR5_LOW */ + volatile uint32_t MAC_Address6_High; /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH */ + volatile uint32_t MAC_Address6_Low; /* ALT_EMAC_GMAC_MAC_ADDR6_LOW */ + volatile uint32_t MAC_Address7_High; /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH */ + volatile uint32_t MAC_Address7_Low; /* ALT_EMAC_GMAC_MAC_ADDR7_LOW */ + volatile uint32_t MAC_Address8_High; /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH */ + volatile uint32_t MAC_Address8_Low; /* ALT_EMAC_GMAC_MAC_ADDR8_LOW */ + volatile uint32_t MAC_Address9_High; /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH */ + volatile uint32_t MAC_Address9_Low; /* ALT_EMAC_GMAC_MAC_ADDR9_LOW */ + volatile uint32_t MAC_Address10_High; /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH */ + volatile uint32_t MAC_Address10_Low; /* ALT_EMAC_GMAC_MAC_ADDR10_LOW */ + volatile uint32_t MAC_Address11_High; /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH */ + volatile uint32_t MAC_Address11_Low; /* ALT_EMAC_GMAC_MAC_ADDR11_LOW */ + volatile uint32_t MAC_Address12_High; /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH */ + volatile uint32_t MAC_Address12_Low; /* ALT_EMAC_GMAC_MAC_ADDR12_LOW */ + volatile uint32_t MAC_Address13_High; /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH */ + volatile uint32_t MAC_Address13_Low; /* ALT_EMAC_GMAC_MAC_ADDR13_LOW */ + volatile uint32_t MAC_Address14_High; /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH */ + volatile uint32_t MAC_Address14_Low; /* ALT_EMAC_GMAC_MAC_ADDR14_LOW */ + volatile uint32_t MAC_Address15_High; /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH */ + volatile uint32_t MAC_Address15_Low; /* ALT_EMAC_GMAC_MAC_ADDR15_LOW */ + volatile uint32_t _pad_0xc0_0xd7[6]; /* *UNDEFINED* */ + volatile uint32_t SGMII_RGMII_SMII_Control_Status; /* ALT_EMAC_GMAC_MII_CTL_STAT */ + volatile uint32_t _pad_0xdc_0xff[9]; /* *UNDEFINED* */ + volatile uint32_t MMC_Control; /* ALT_EMAC_GMAC_MMC_CTL */ + volatile uint32_t MMC_Receive_Interrupt; /* ALT_EMAC_GMAC_MMC_RX_INT */ + volatile uint32_t MMC_Transmit_Interrupt; /* ALT_EMAC_GMAC_MMC_TX_INT */ + volatile uint32_t MMC_Receive_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK */ + volatile uint32_t MMC_Transmit_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK */ + volatile uint32_t txoctetcount_gb; /* ALT_EMAC_GMAC_TXOCTETCOUNT_GB */ + volatile uint32_t txframecount_gb; /* ALT_EMAC_GMAC_TXFRMCOUNT_GB */ + volatile uint32_t txbroadcastframes_g; /* ALT_EMAC_GMAC_TXBCASTFRMS_G */ + volatile uint32_t txmulticastframes_g; /* ALT_EMAC_GMAC_TXMCASTFRMS_G */ + volatile uint32_t tx64octets_gb; /* ALT_EMAC_GMAC_TX64OCTETS_GB */ + volatile uint32_t tx65to127octets_gb; /* ALT_EMAC_GMAC_TX65TO127OCTETS_GB */ + volatile uint32_t tx128to255octets_gb; /* ALT_EMAC_GMAC_TX128TO255OCTETS_GB */ + volatile uint32_t tx256to511octets_gb; /* ALT_EMAC_GMAC_TX256TO511OCTETS_GB */ + volatile uint32_t tx512to1023octets_gb; /* ALT_EMAC_GMAC_TX512TO1023OCTETS_GB */ + volatile uint32_t tx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB */ + volatile uint32_t txunicastframes_gb; /* ALT_EMAC_GMAC_TXUNICASTFRMS_GB */ + volatile uint32_t txmulticastframes_gb; /* ALT_EMAC_GMAC_TXMCASTFRMS_GB */ + volatile uint32_t txbroadcastframes_gb; /* ALT_EMAC_GMAC_TXBCASTFRMS_GB */ + volatile uint32_t txunderflowerror; /* ALT_EMAC_GMAC_TXUNDERFLOWERROR */ + volatile uint32_t txsinglecol_g; /* ALT_EMAC_GMAC_TXSINGLECOL_G */ + volatile uint32_t txmulticol_g; /* ALT_EMAC_GMAC_TXMULTICOL_G */ + volatile uint32_t txdeferred; /* ALT_EMAC_GMAC_TXDEFERRED */ + volatile uint32_t txlatecol; /* ALT_EMAC_GMAC_TXLATECOL */ + volatile uint32_t txexesscol; /* ALT_EMAC_GMAC_TXEXESSCOL */ + volatile uint32_t txcarriererr; /* ALT_EMAC_GMAC_TXCARRIERERR */ + volatile uint32_t txoctetcnt; /* ALT_EMAC_GMAC_TXOCTETCNT */ + volatile uint32_t txframecount_g; /* ALT_EMAC_GMAC_TXFRMCOUNT_G */ + volatile uint32_t txexcessdef; /* ALT_EMAC_GMAC_TXEXCESSDEF */ + volatile uint32_t txpauseframes; /* ALT_EMAC_GMAC_TXPAUSEFRMS */ + volatile uint32_t txvlanframes_g; /* ALT_EMAC_GMAC_TXVLANFRMS_G */ + volatile uint32_t txoversize_g; /* ALT_EMAC_GMAC_TXOVERSIZE_G */ + volatile uint32_t _pad_0x17c_0x17f; /* *UNDEFINED* */ + volatile uint32_t rxframecount_gb; /* ALT_EMAC_GMAC_RXFRMCOUNT_GB */ + volatile uint32_t rxoctetcount_gb; /* ALT_EMAC_GMAC_RXOCTETCOUNT_GB */ + volatile uint32_t rxoctetcount_g; /* ALT_EMAC_GMAC_RXOCTETCOUNT_G */ + volatile uint32_t rxbroadcastframes_g; /* ALT_EMAC_GMAC_RXBCASTFRMS_G */ + volatile uint32_t rxmulticastframes_g; /* ALT_EMAC_GMAC_RXMCASTFRMS_G */ + volatile uint32_t rxcrcerror; /* ALT_EMAC_GMAC_RXCRCERROR */ + volatile uint32_t rxalignmenterror; /* ALT_EMAC_GMAC_RXALIGNMENTERROR */ + volatile uint32_t rxrunterror; /* ALT_EMAC_GMAC_RXRUNTERROR */ + volatile uint32_t rxjabbererror; /* ALT_EMAC_GMAC_RXJABBERERROR */ + volatile uint32_t rxundersize_g; /* ALT_EMAC_GMAC_RXUNDERSIZE_G */ + volatile uint32_t rxoversize_g; /* ALT_EMAC_GMAC_RXOVERSIZE_G */ + volatile uint32_t rx64octets_gb; /* ALT_EMAC_GMAC_RX64OCTETS_GB */ + volatile uint32_t rx65to127octets_gb; /* ALT_EMAC_GMAC_RX65TO127OCTETS_GB */ + volatile uint32_t rx128to255octets_gb; /* ALT_EMAC_GMAC_RX128TO255OCTETS_GB */ + volatile uint32_t rx256to511octets_gb; /* ALT_EMAC_GMAC_RX256TO511OCTETS_GB */ + volatile uint32_t rx512to1023octets_gb; /* ALT_EMAC_GMAC_RX512TO1023OCTETS_GB */ + volatile uint32_t rx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB */ + volatile uint32_t rxunicastframes_g; /* ALT_EMAC_GMAC_RXUNICASTFRMS_G */ + volatile uint32_t rxlengtherror; /* ALT_EMAC_GMAC_RXLENERROR */ + volatile uint32_t rxoutofrangetype; /* ALT_EMAC_GMAC_RXOUTOFRANGETYPE */ + volatile uint32_t rxpauseframes; /* ALT_EMAC_GMAC_RXPAUSEFRMS */ + volatile uint32_t rxfifooverflow; /* ALT_EMAC_GMAC_RXFIFOOVF */ + volatile uint32_t rxvlanframes_gb; /* ALT_EMAC_GMAC_RXVLANFRMS_GB */ + volatile uint32_t rxwatchdogerror; /* ALT_EMAC_GMAC_RXWDERROR */ + volatile uint32_t rxrcverror; /* ALT_EMAC_GMAC_RXRCVERROR */ + volatile uint32_t rxctrlframes_g; /* ALT_EMAC_GMAC_RXCTLFRMS_G */ + volatile uint32_t _pad_0x1e8_0x1ff[6]; /* *UNDEFINED* */ + volatile uint32_t MMC_IPC_Receive_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK */ + volatile uint32_t _pad_0x204_0x207; /* *UNDEFINED* */ + volatile uint32_t MMC_IPC_Receive_Interrupt; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT */ + volatile uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */ + volatile uint32_t rxipv4_gd_frms; /* ALT_EMAC_GMAC_RXIPV4_GD_FRMS */ + volatile uint32_t rxipv4_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS */ + volatile uint32_t rxipv4_nopay_frms; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS */ + volatile uint32_t rxipv4_frag_frms; /* ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS */ + volatile uint32_t rxipv4_udsbl_frms; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS */ + volatile uint32_t rxipv6_gd_frms; /* ALT_EMAC_GMAC_RXIPV6_GD_FRMS */ + volatile uint32_t rxipv6_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS */ + volatile uint32_t rxipv6_nopay_frms; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS */ + volatile uint32_t rxudp_gd_frms; /* ALT_EMAC_GMAC_RXUDP_GD_FRMS */ + volatile uint32_t rxudp_err_frms; /* ALT_EMAC_GMAC_RXUDP_ERR_FRMS */ + volatile uint32_t rxtcp_gd_frms; /* ALT_EMAC_GMAC_RXTCP_GD_FRMS */ + volatile uint32_t rxtcp_err_frms; /* ALT_EMAC_GMAC_RXTCP_ERR_FRMS */ + volatile uint32_t rxicmp_gd_frms; /* ALT_EMAC_GMAC_RXICMP_GD_FRMS */ + volatile uint32_t rxicmp_err_frms; /* ALT_EMAC_GMAC_RXICMP_ERR_FRMS */ + volatile uint32_t _pad_0x248_0x24f[2]; /* *UNDEFINED* */ + volatile uint32_t rxipv4_gd_octets; /* ALT_EMAC_GMAC_RXIPV4_GD_OCTETS */ + volatile uint32_t rxipv4_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS */ + volatile uint32_t rxipv4_nopay_octets; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS */ + volatile uint32_t rxipv4_frag_octets; /* ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS */ + volatile uint32_t rxipv4_udsbl_octets; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS */ + volatile uint32_t rxipv6_gd_octets; /* ALT_EMAC_GMAC_RXIPV6_GD_OCTETS */ + volatile uint32_t rxipv6_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS */ + volatile uint32_t rxipv6_nopay_octets; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS */ + volatile uint32_t rxudp_gd_octets; /* ALT_EMAC_GMAC_RXUDP_GD_OCTETS */ + volatile uint32_t rxudp_err_octets; /* ALT_EMAC_GMAC_RXUDP_ERR_OCTETS */ + volatile uint32_t rxtcp_gd_octets; /* ALT_EMAC_GMAC_RXTCP_GD_OCTETS */ + volatile uint32_t rxtcperroctets; /* ALT_EMAC_GMAC_RXTCPERROCTETS */ + volatile uint32_t rxicmp_gd_octets; /* ALT_EMAC_GMAC_RXICMP_GD_OCTETS */ + volatile uint32_t rxicmp_err_octets; /* ALT_EMAC_GMAC_RXICMP_ERR_OCTETS */ + volatile uint32_t _pad_0x288_0x3ff[94]; /* *UNDEFINED* */ + volatile uint32_t L3_L4_Control0; /* ALT_EMAC_GMAC_L3_L4_CTL0 */ + volatile uint32_t Layer4_Address0; /* ALT_EMAC_GMAC_LYR4_ADDR0 */ + volatile uint32_t _pad_0x408_0x40f[2]; /* *UNDEFINED* */ + volatile uint32_t Layer3_Addr0_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG0 */ + volatile uint32_t Layer3_Addr1_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG0 */ + volatile uint32_t Layer3_Addr2_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG0 */ + volatile uint32_t Layer3_Addr3_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG0 */ + volatile uint32_t _pad_0x420_0x42f[4]; /* *UNDEFINED* */ + volatile uint32_t L3_L4_Control1; /* ALT_EMAC_GMAC_L3_L4_CTL1 */ + volatile uint32_t Layer4_Address1; /* ALT_EMAC_GMAC_LYR4_ADDR1 */ + volatile uint32_t _pad_0x438_0x43f[2]; /* *UNDEFINED* */ + volatile uint32_t Layer3_Addr0_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG1 */ + volatile uint32_t Layer3_Addr1_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG1 */ + volatile uint32_t Layer3_Addr2_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG1 */ + volatile uint32_t Layer3_Addr3_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG1 */ + volatile uint32_t _pad_0x450_0x45f[4]; /* *UNDEFINED* */ + volatile uint32_t L3_L4_Control2; /* ALT_EMAC_GMAC_L3_L4_CTL2 */ + volatile uint32_t Layer4_Address2; /* ALT_EMAC_GMAC_LYR4_ADDR2 */ + volatile uint32_t _pad_0x468_0x46f[2]; /* *UNDEFINED* */ + volatile uint32_t Layer3_Addr0_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG2 */ + volatile uint32_t Layer3_Addr1_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG2 */ + volatile uint32_t Layer3_Addr2_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG2 */ + volatile uint32_t Layer3_Addr3_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG2 */ + volatile uint32_t _pad_0x480_0x48f[4]; /* *UNDEFINED* */ + volatile uint32_t L3_L4_Control3; /* ALT_EMAC_GMAC_L3_L4_CTL3 */ + volatile uint32_t Layer4_Address3; /* ALT_EMAC_GMAC_LYR4_ADDR3 */ + volatile uint32_t _pad_0x498_0x49f[2]; /* *UNDEFINED* */ + volatile uint32_t Layer3_Addr0_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG3 */ + volatile uint32_t Layer3_Addr1_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG3 */ + volatile uint32_t Layer3_Addr2_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG3 */ + volatile uint32_t Layer3_Addr3_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG3 */ + volatile uint32_t _pad_0x4b0_0x4ff[20]; /* *UNDEFINED* */ + volatile uint32_t Hash_Table_Reg0; /* ALT_EMAC_GMAC_HASH_TABLE_REG0 */ + volatile uint32_t Hash_Table_Reg1; /* ALT_EMAC_GMAC_HASH_TABLE_REG1 */ + volatile uint32_t Hash_Table_Reg2; /* ALT_EMAC_GMAC_HASH_TABLE_REG2 */ + volatile uint32_t Hash_Table_Reg3; /* ALT_EMAC_GMAC_HASH_TABLE_REG3 */ + volatile uint32_t Hash_Table_Reg4; /* ALT_EMAC_GMAC_HASH_TABLE_REG4 */ + volatile uint32_t Hash_Table_Reg5; /* ALT_EMAC_GMAC_HASH_TABLE_REG5 */ + volatile uint32_t Hash_Table_Reg6; /* ALT_EMAC_GMAC_HASH_TABLE_REG6 */ + volatile uint32_t Hash_Table_Reg7; /* ALT_EMAC_GMAC_HASH_TABLE_REG7 */ + volatile uint32_t _pad_0x520_0x583[25]; /* *UNDEFINED* */ + volatile uint32_t VLAN_Incl_Reg; /* ALT_EMAC_GMAC_VLAN_INCL_REG */ + volatile uint32_t VLAN_Hash_Table_Reg; /* ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG */ + volatile uint32_t _pad_0x58c_0x6ff[93]; /* *UNDEFINED* */ + volatile uint32_t Timestamp_Control; /* ALT_EMAC_GMAC_TS_CTL */ + volatile uint32_t Sub_Second_Increment; /* ALT_EMAC_GMAC_SUB_SEC_INCREMENT */ + volatile uint32_t System_Time_Seconds; /* ALT_EMAC_GMAC_SYS_TIME_SECS */ + volatile uint32_t System_Time_Nanoseconds; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS */ + volatile uint32_t System_Time_Seconds_Update; /* ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE */ + volatile uint32_t System_Time_Nanoseconds_Update; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE */ + volatile uint32_t Timestamp_Addend; /* ALT_EMAC_GMAC_TS_ADDEND */ + volatile uint32_t Target_Time_Seconds; /* ALT_EMAC_GMAC_TGT_TIME_SECS */ + volatile uint32_t Target_Time_Nanoseconds; /* ALT_EMAC_GMAC_TGT_TIME_NANOSECS */ + volatile uint32_t System_Time_Higher_Word_Seconds; /* ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS */ + volatile uint32_t Timestamp_Status; /* ALT_EMAC_GMAC_TS_STAT */ + volatile uint32_t PPS_Control; /* ALT_EMAC_GMAC_PPS_CTL */ + volatile uint32_t Auxiliary_Timestamp_Nanoseconds; /* ALT_EMAC_GMAC_AUX_TS_NANOSECS */ + volatile uint32_t Auxiliary_Timestamp_Seconds; /* ALT_EMAC_GMAC_AUX_TS_SECS */ + volatile uint32_t _pad_0x738_0x75f[10]; /* *UNDEFINED* */ + volatile uint32_t PPS0_Interval; /* ALT_EMAC_GMAC_PPS0_INTERVAL */ + volatile uint32_t PPS0_Width; /* ALT_EMAC_GMAC_PPS0_WIDTH */ + volatile uint32_t _pad_0x768_0x7ff[38]; /* *UNDEFINED* */ + volatile uint32_t MAC_Address16_High; /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH */ + volatile uint32_t MAC_Address16_Low; /* ALT_EMAC_GMAC_MAC_ADDR16_LOW */ + volatile uint32_t MAC_Address17_High; /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH */ + volatile uint32_t MAC_Address17_Low; /* ALT_EMAC_GMAC_MAC_ADDR17_LOW */ + volatile uint32_t MAC_Address18_High; /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH */ + volatile uint32_t MAC_Address18_Low; /* ALT_EMAC_GMAC_MAC_ADDR18_LOW */ + volatile uint32_t MAC_Address19_High; /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH */ + volatile uint32_t MAC_Address19_Low; /* ALT_EMAC_GMAC_MAC_ADDR19_LOW */ + volatile uint32_t MAC_Address20_High; /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH */ + volatile uint32_t MAC_Address20_Low; /* ALT_EMAC_GMAC_MAC_ADDR20_LOW */ + volatile uint32_t MAC_Address21_High; /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH */ + volatile uint32_t MAC_Address21_Low; /* ALT_EMAC_GMAC_MAC_ADDR21_LOW */ + volatile uint32_t MAC_Address22_High; /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH */ + volatile uint32_t MAC_Address22_Low; /* ALT_EMAC_GMAC_MAC_ADDR22_LOW */ + volatile uint32_t MAC_Address23_High; /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH */ + volatile uint32_t MAC_Address23_Low; /* ALT_EMAC_GMAC_MAC_ADDR23_LOW */ + volatile uint32_t MAC_Address24_High; /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH */ + volatile uint32_t MAC_Address24_Low; /* ALT_EMAC_GMAC_MAC_ADDR24_LOW */ + volatile uint32_t MAC_Address25_High; /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH */ + volatile uint32_t MAC_Address25_Low; /* ALT_EMAC_GMAC_MAC_ADDR25_LOW */ + volatile uint32_t MAC_Address26_High; /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH */ + volatile uint32_t MAC_Address26_Low; /* ALT_EMAC_GMAC_MAC_ADDR26_LOW */ + volatile uint32_t MAC_Address27_High; /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH */ + volatile uint32_t MAC_Address27_Low; /* ALT_EMAC_GMAC_MAC_ADDR27_LOW */ + volatile uint32_t MAC_Address28_High; /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH */ + volatile uint32_t MAC_Address28_Low; /* ALT_EMAC_GMAC_MAC_ADDR28_LOW */ + volatile uint32_t MAC_Address29_High; /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH */ + volatile uint32_t MAC_Address29_Low; /* ALT_EMAC_GMAC_MAC_ADDR29_LOW */ + volatile uint32_t MAC_Address30_High; /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH */ + volatile uint32_t MAC_Address30_Low; /* ALT_EMAC_GMAC_MAC_ADDR30_LOW */ + volatile uint32_t MAC_Address31_High; /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH */ + volatile uint32_t MAC_Address31_Low; /* ALT_EMAC_GMAC_MAC_ADDR31_LOW */ + volatile uint32_t MAC_Address32_High; /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH */ + volatile uint32_t MAC_Address32_Low; /* ALT_EMAC_GMAC_MAC_ADDR32_LOW */ + volatile uint32_t MAC_Address33_High; /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH */ + volatile uint32_t MAC_Address33_Low; /* ALT_EMAC_GMAC_MAC_ADDR33_LOW */ + volatile uint32_t MAC_Address34_High; /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH */ + volatile uint32_t MAC_Address34_Low; /* ALT_EMAC_GMAC_MAC_ADDR34_LOW */ + volatile uint32_t MAC_Address35_High; /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH */ + volatile uint32_t MAC_Address35_Low; /* ALT_EMAC_GMAC_MAC_ADDR35_LOW */ + volatile uint32_t MAC_Address36_High; /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH */ + volatile uint32_t MAC_Address36_Low; /* ALT_EMAC_GMAC_MAC_ADDR36_LOW */ + volatile uint32_t MAC_Address37_High; /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH */ + volatile uint32_t MAC_Address37_Low; /* ALT_EMAC_GMAC_MAC_ADDR37_LOW */ + volatile uint32_t MAC_Address38_High; /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH */ + volatile uint32_t MAC_Address38_Low; /* ALT_EMAC_GMAC_MAC_ADDR38_LOW */ + volatile uint32_t MAC_Address39_High; /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH */ + volatile uint32_t MAC_Address39_Low; /* ALT_EMAC_GMAC_MAC_ADDR39_LOW */ + volatile uint32_t MAC_Address40_High; /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH */ + volatile uint32_t MAC_Address40_Low; /* ALT_EMAC_GMAC_MAC_ADDR40_LOW */ + volatile uint32_t MAC_Address41_High; /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH */ + volatile uint32_t MAC_Address41_Low; /* ALT_EMAC_GMAC_MAC_ADDR41_LOW */ + volatile uint32_t MAC_Address42_High; /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH */ + volatile uint32_t MAC_Address42_Low; /* ALT_EMAC_GMAC_MAC_ADDR42_LOW */ + volatile uint32_t MAC_Address43_High; /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH */ + volatile uint32_t MAC_Address43_Low; /* ALT_EMAC_GMAC_MAC_ADDR43_LOW */ + volatile uint32_t MAC_Address44_High; /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH */ + volatile uint32_t MAC_Address44_Low; /* ALT_EMAC_GMAC_MAC_ADDR44_LOW */ + volatile uint32_t MAC_Address45_High; /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH */ + volatile uint32_t MAC_Address45_Low; /* ALT_EMAC_GMAC_MAC_ADDR45_LOW */ + volatile uint32_t MAC_Address46_High; /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH */ + volatile uint32_t MAC_Address46_Low; /* ALT_EMAC_GMAC_MAC_ADDR46_LOW */ + volatile uint32_t MAC_Address47_High; /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH */ + volatile uint32_t MAC_Address47_Low; /* ALT_EMAC_GMAC_MAC_ADDR47_LOW */ + volatile uint32_t MAC_Address48_High; /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH */ + volatile uint32_t MAC_Address48_Low; /* ALT_EMAC_GMAC_MAC_ADDR48_LOW */ + volatile uint32_t MAC_Address49_High; /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH */ + volatile uint32_t MAC_Address49_Low; /* ALT_EMAC_GMAC_MAC_ADDR49_LOW */ + volatile uint32_t MAC_Address50_High; /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH */ + volatile uint32_t MAC_Address50_Low; /* ALT_EMAC_GMAC_MAC_ADDR50_LOW */ + volatile uint32_t MAC_Address51_High; /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH */ + volatile uint32_t MAC_Address51_Low; /* ALT_EMAC_GMAC_MAC_ADDR51_LOW */ + volatile uint32_t MAC_Address52_High; /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH */ + volatile uint32_t MAC_Address52_Low; /* ALT_EMAC_GMAC_MAC_ADDR52_LOW */ + volatile uint32_t MAC_Address53_High; /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH */ + volatile uint32_t MAC_Address53_Low; /* ALT_EMAC_GMAC_MAC_ADDR53_LOW */ + volatile uint32_t MAC_Address54_High; /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH */ + volatile uint32_t MAC_Address54_Low; /* ALT_EMAC_GMAC_MAC_ADDR54_LOW */ + volatile uint32_t MAC_Address55_High; /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH */ + volatile uint32_t MAC_Address55_Low; /* ALT_EMAC_GMAC_MAC_ADDR55_LOW */ + volatile uint32_t MAC_Address56_High; /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH */ + volatile uint32_t MAC_Address56_Low; /* ALT_EMAC_GMAC_MAC_ADDR56_LOW */ + volatile uint32_t MAC_Address57_High; /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH */ + volatile uint32_t MAC_Address57_Low; /* ALT_EMAC_GMAC_MAC_ADDR57_LOW */ + volatile uint32_t MAC_Address58_High; /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH */ + volatile uint32_t MAC_Address58_Low; /* ALT_EMAC_GMAC_MAC_ADDR58_LOW */ + volatile uint32_t MAC_Address59_High; /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH */ + volatile uint32_t MAC_Address59_Low; /* ALT_EMAC_GMAC_MAC_ADDR59_LOW */ + volatile uint32_t MAC_Address60_High; /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH */ + volatile uint32_t MAC_Address60_Low; /* ALT_EMAC_GMAC_MAC_ADDR60_LOW */ + volatile uint32_t MAC_Address61_High; /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH */ + volatile uint32_t MAC_Address61_Low; /* ALT_EMAC_GMAC_MAC_ADDR61_LOW */ + volatile uint32_t MAC_Address62_High; /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH */ + volatile uint32_t MAC_Address62_Low; /* ALT_EMAC_GMAC_MAC_ADDR62_LOW */ + volatile uint32_t MAC_Address63_High; /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH */ + volatile uint32_t MAC_Address63_Low; /* ALT_EMAC_GMAC_MAC_ADDR63_LOW */ + volatile uint32_t MAC_Address64_High; /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH */ + volatile uint32_t MAC_Address64_Low; /* ALT_EMAC_GMAC_MAC_ADDR64_LOW */ + volatile uint32_t MAC_Address65_High; /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH */ + volatile uint32_t MAC_Address65_Low; /* ALT_EMAC_GMAC_MAC_ADDR65_LOW */ + volatile uint32_t MAC_Address66_High; /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH */ + volatile uint32_t MAC_Address66_Low; /* ALT_EMAC_GMAC_MAC_ADDR66_LOW */ + volatile uint32_t MAC_Address67_High; /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH */ + volatile uint32_t MAC_Address67_Low; /* ALT_EMAC_GMAC_MAC_ADDR67_LOW */ + volatile uint32_t MAC_Address68_High; /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH */ + volatile uint32_t MAC_Address68_Low; /* ALT_EMAC_GMAC_MAC_ADDR68_LOW */ + volatile uint32_t MAC_Address69_High; /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH */ + volatile uint32_t MAC_Address69_Low; /* ALT_EMAC_GMAC_MAC_ADDR69_LOW */ + volatile uint32_t MAC_Address70_High; /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH */ + volatile uint32_t MAC_Address70_Low; /* ALT_EMAC_GMAC_MAC_ADDR70_LOW */ + volatile uint32_t MAC_Address71_High; /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH */ + volatile uint32_t MAC_Address71_Low; /* ALT_EMAC_GMAC_MAC_ADDR71_LOW */ + volatile uint32_t MAC_Address72_High; /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH */ + volatile uint32_t MAC_Address72_Low; /* ALT_EMAC_GMAC_MAC_ADDR72_LOW */ + volatile uint32_t MAC_Address73_High; /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH */ + volatile uint32_t MAC_Address73_Low; /* ALT_EMAC_GMAC_MAC_ADDR73_LOW */ + volatile uint32_t MAC_Address74_High; /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH */ + volatile uint32_t MAC_Address74_Low; /* ALT_EMAC_GMAC_MAC_ADDR74_LOW */ + volatile uint32_t MAC_Address75_High; /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH */ + volatile uint32_t MAC_Address75_Low; /* ALT_EMAC_GMAC_MAC_ADDR75_LOW */ + volatile uint32_t MAC_Address76_High; /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH */ + volatile uint32_t MAC_Address76_Low; /* ALT_EMAC_GMAC_MAC_ADDR76_LOW */ + volatile uint32_t MAC_Address77_High; /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH */ + volatile uint32_t MAC_Address77_Low; /* ALT_EMAC_GMAC_MAC_ADDR77_LOW */ + volatile uint32_t MAC_Address78_High; /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH */ + volatile uint32_t MAC_Address78_Low; /* ALT_EMAC_GMAC_MAC_ADDR78_LOW */ + volatile uint32_t MAC_Address79_High; /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH */ + volatile uint32_t MAC_Address79_Low; /* ALT_EMAC_GMAC_MAC_ADDR79_LOW */ + volatile uint32_t MAC_Address80_High; /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH */ + volatile uint32_t MAC_Address80_Low; /* ALT_EMAC_GMAC_MAC_ADDR80_LOW */ + volatile uint32_t MAC_Address81_High; /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH */ + volatile uint32_t MAC_Address81_Low; /* ALT_EMAC_GMAC_MAC_ADDR81_LOW */ + volatile uint32_t MAC_Address82_High; /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH */ + volatile uint32_t MAC_Address82_Low; /* ALT_EMAC_GMAC_MAC_ADDR82_LOW */ + volatile uint32_t MAC_Address83_High; /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH */ + volatile uint32_t MAC_Address83_Low; /* ALT_EMAC_GMAC_MAC_ADDR83_LOW */ + volatile uint32_t MAC_Address84_High; /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH */ + volatile uint32_t MAC_Address84_Low; /* ALT_EMAC_GMAC_MAC_ADDR84_LOW */ + volatile uint32_t MAC_Address85_High; /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH */ + volatile uint32_t MAC_Address85_Low; /* ALT_EMAC_GMAC_MAC_ADDR85_LOW */ + volatile uint32_t MAC_Address86_High; /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH */ + volatile uint32_t MAC_Address86_Low; /* ALT_EMAC_GMAC_MAC_ADDR86_LOW */ + volatile uint32_t MAC_Address87_High; /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH */ + volatile uint32_t MAC_Address87_Low; /* ALT_EMAC_GMAC_MAC_ADDR87_LOW */ + volatile uint32_t MAC_Address88_High; /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH */ + volatile uint32_t MAC_Address88_Low; /* ALT_EMAC_GMAC_MAC_ADDR88_LOW */ + volatile uint32_t MAC_Address89_High; /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH */ + volatile uint32_t MAC_Address89_Low; /* ALT_EMAC_GMAC_MAC_ADDR89_LOW */ + volatile uint32_t MAC_Address90_High; /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH */ + volatile uint32_t MAC_Address90_Low; /* ALT_EMAC_GMAC_MAC_ADDR90_LOW */ + volatile uint32_t MAC_Address91_High; /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH */ + volatile uint32_t MAC_Address91_Low; /* ALT_EMAC_GMAC_MAC_ADDR91_LOW */ + volatile uint32_t MAC_Address92_High; /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH */ + volatile uint32_t MAC_Address92_Low; /* ALT_EMAC_GMAC_MAC_ADDR92_LOW */ + volatile uint32_t MAC_Address93_High; /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH */ + volatile uint32_t MAC_Address93_Low; /* ALT_EMAC_GMAC_MAC_ADDR93_LOW */ + volatile uint32_t MAC_Address94_High; /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH */ + volatile uint32_t MAC_Address94_Low; /* ALT_EMAC_GMAC_MAC_ADDR94_LOW */ + volatile uint32_t MAC_Address95_High; /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH */ + volatile uint32_t MAC_Address95_Low; /* ALT_EMAC_GMAC_MAC_ADDR95_LOW */ + volatile uint32_t MAC_Address96_High; /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH */ + volatile uint32_t MAC_Address96_Low; /* ALT_EMAC_GMAC_MAC_ADDR96_LOW */ + volatile uint32_t MAC_Address97_High; /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH */ + volatile uint32_t MAC_Address97_Low; /* ALT_EMAC_GMAC_MAC_ADDR97_LOW */ + volatile uint32_t MAC_Address98_High; /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH */ + volatile uint32_t MAC_Address98_Low; /* ALT_EMAC_GMAC_MAC_ADDR98_LOW */ + volatile uint32_t MAC_Address99_High; /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH */ + volatile uint32_t MAC_Address99_Low; /* ALT_EMAC_GMAC_MAC_ADDR99_LOW */ + volatile uint32_t MAC_Address100_High; /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH */ + volatile uint32_t MAC_Address100_Low; /* ALT_EMAC_GMAC_MAC_ADDR100_LOW */ + volatile uint32_t MAC_Address101_High; /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH */ + volatile uint32_t MAC_Address101_Low; /* ALT_EMAC_GMAC_MAC_ADDR101_LOW */ + volatile uint32_t MAC_Address102_High; /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH */ + volatile uint32_t MAC_Address102_Low; /* ALT_EMAC_GMAC_MAC_ADDR102_LOW */ + volatile uint32_t MAC_Address103_High; /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH */ + volatile uint32_t MAC_Address103_Low; /* ALT_EMAC_GMAC_MAC_ADDR103_LOW */ + volatile uint32_t MAC_Address104_High; /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH */ + volatile uint32_t MAC_Address104_Low; /* ALT_EMAC_GMAC_MAC_ADDR104_LOW */ + volatile uint32_t MAC_Address105_High; /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH */ + volatile uint32_t MAC_Address105_Low; /* ALT_EMAC_GMAC_MAC_ADDR105_LOW */ + volatile uint32_t MAC_Address106_High; /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH */ + volatile uint32_t MAC_Address106_Low; /* ALT_EMAC_GMAC_MAC_ADDR106_LOW */ + volatile uint32_t MAC_Address107_High; /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH */ + volatile uint32_t MAC_Address107_Low; /* ALT_EMAC_GMAC_MAC_ADDR107_LOW */ + volatile uint32_t MAC_Address108_High; /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH */ + volatile uint32_t MAC_Address108_Low; /* ALT_EMAC_GMAC_MAC_ADDR108_LOW */ + volatile uint32_t MAC_Address109_High; /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH */ + volatile uint32_t MAC_Address109_Low; /* ALT_EMAC_GMAC_MAC_ADDR109_LOW */ + volatile uint32_t MAC_Address110_High; /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH */ + volatile uint32_t MAC_Address110_Low; /* ALT_EMAC_GMAC_MAC_ADDR110_LOW */ + volatile uint32_t MAC_Address111_High; /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH */ + volatile uint32_t MAC_Address111_Low; /* ALT_EMAC_GMAC_MAC_ADDR111_LOW */ + volatile uint32_t MAC_Address112_High; /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH */ + volatile uint32_t MAC_Address112_Low; /* ALT_EMAC_GMAC_MAC_ADDR112_LOW */ + volatile uint32_t MAC_Address113_High; /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH */ + volatile uint32_t MAC_Address113_Low; /* ALT_EMAC_GMAC_MAC_ADDR113_LOW */ + volatile uint32_t MAC_Address114_High; /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH */ + volatile uint32_t MAC_Address114_Low; /* ALT_EMAC_GMAC_MAC_ADDR114_LOW */ + volatile uint32_t MAC_Address115_High; /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH */ + volatile uint32_t MAC_Address115_Low; /* ALT_EMAC_GMAC_MAC_ADDR115_LOW */ + volatile uint32_t MAC_Address116_High; /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH */ + volatile uint32_t MAC_Address116_Low; /* ALT_EMAC_GMAC_MAC_ADDR116_LOW */ + volatile uint32_t MAC_Address117_High; /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH */ + volatile uint32_t MAC_Address117_Low; /* ALT_EMAC_GMAC_MAC_ADDR117_LOW */ + volatile uint32_t MAC_Address118_High; /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH */ + volatile uint32_t MAC_Address118_Low; /* ALT_EMAC_GMAC_MAC_ADDR118_LOW */ + volatile uint32_t MAC_Address119_High; /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH */ + volatile uint32_t MAC_Address119_Low; /* ALT_EMAC_GMAC_MAC_ADDR119_LOW */ + volatile uint32_t MAC_Address120_High; /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH */ + volatile uint32_t MAC_Address120_Low; /* ALT_EMAC_GMAC_MAC_ADDR120_LOW */ + volatile uint32_t MAC_Address121_High; /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH */ + volatile uint32_t MAC_Address121_Low; /* ALT_EMAC_GMAC_MAC_ADDR121_LOW */ + volatile uint32_t MAC_Address122_High; /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH */ + volatile uint32_t MAC_Address122_Low; /* ALT_EMAC_GMAC_MAC_ADDR122_LOW */ + volatile uint32_t MAC_Address123_High; /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH */ + volatile uint32_t MAC_Address123_Low; /* ALT_EMAC_GMAC_MAC_ADDR123_LOW */ + volatile uint32_t MAC_Address124_High; /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH */ + volatile uint32_t MAC_Address124_Low; /* ALT_EMAC_GMAC_MAC_ADDR124_LOW */ + volatile uint32_t MAC_Address125_High; /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH */ + volatile uint32_t MAC_Address125_Low; /* ALT_EMAC_GMAC_MAC_ADDR125_LOW */ + volatile uint32_t MAC_Address126_High; /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH */ + volatile uint32_t MAC_Address126_Low; /* ALT_EMAC_GMAC_MAC_ADDR126_LOW */ + volatile uint32_t MAC_Address127_High; /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH */ + volatile uint32_t MAC_Address127_Low; /* ALT_EMAC_GMAC_MAC_ADDR127_LOW */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_EMAC_GMAC. */ +typedef volatile struct ALT_EMAC_GMAC_raw_s ALT_EMAC_GMAC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : DMA Register Group - ALT_EMAC_DMA + * DMA Register Group + * + * DMA Register Group + * + */ +/* + * Register : Register 0 (Bus Mode Register) - Bus_Mode + * + * The Bus Mode register establishes the bus operating modes for the DMA. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------- + * [0] | RW | 0x1 | Software Reset + * [1] | ??? | 0x0 | *UNDEFINED* + * [6:2] | RW | 0x0 | Descriptor Skip Length + * [7] | RW | 0x0 | Alternate Descriptor Size + * [13:8] | RW | 0x1 | Programmable Burst Length + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | Fixed Burst + * [22:17] | RW | 0x1 | Rx DMA PBL + * [23] | RW | 0x0 | Use Separate PBL + * [24] | RW | 0x0 | 8xPBL Mode + * [25] | RW | 0x0 | Address Aligned Beats + * [31:26] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Software Reset - swr + * + * When this bit is set, the MAC DMA Controller resets the logic and all internal + * registers of the MAC. It is cleared automatically after the reset operation has + * completed in all of the EMAC clock domains. Before reprogramming any register of + * the EMAC, you should read a zero (0) value in this bit . + * + * Note: + * + * * The Software reset function is driven only by this bit. Bit 0 of Register 64 + * (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) + * has no impact on the Software reset function. + * + * * The reset operation is completed only when all resets in all active clock + * domains are de-asserted. Therefore, it is essential that all the PHY inputs + * clocks (applicable for the selected PHY interface) are present for the + * software reset completion. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:-------------------------------- + * ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST | 0x0 | MAC DMA Controller Clears Logic + * ALT_EMAC_DMA_BUS_MOD_SWR_E_RST | 0x1 | MAC DMA Controller Resets Logic + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR + * + * MAC DMA Controller Clears Logic + */ +#define ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR + * + * MAC DMA Controller Resets Logic + */ +#define ALT_EMAC_DMA_BUS_MOD_SWR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */ +#define ALT_EMAC_DMA_BUS_MOD_SWR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */ +#define ALT_EMAC_DMA_BUS_MOD_SWR_MSB 0 +/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */ +#define ALT_EMAC_DMA_BUS_MOD_SWR_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_SWR register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_SWR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_SWR register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_SWR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */ +#define ALT_EMAC_DMA_BUS_MOD_SWR_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_BUS_MOD_SWR field value from a register. */ +#define ALT_EMAC_DMA_BUS_MOD_SWR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_DMA_BUS_MOD_SWR register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_BUS_MOD_SWR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Descriptor Skip Length - dsl + * + * This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, + * 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address + * skipping starts from the end of current descriptor to the start of next + * descriptor. When the DSL value is equal to zero, then the descriptor table is + * taken as contiguous by the DMA in Ring mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_DSL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_DSL_MSB 6 +/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_DSL_WIDTH 5 +/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_DSL register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_DSL_SET_MSK 0x0000007c +/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_DSL register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_DSL_CLR_MSK 0xffffff83 +/* The reset value of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_DSL_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_BUS_MOD_DSL field value from a register. */ +#define ALT_EMAC_DMA_BUS_MOD_DSL_GET(value) (((value) & 0x0000007c) >> 2) +/* Produces a ALT_EMAC_DMA_BUS_MOD_DSL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_BUS_MOD_DSL_SET(value) (((value) << 2) & 0x0000007c) + +/* + * Field : Alternate Descriptor Size - atds + * + * When set, the size of the alternate descriptor increases to 32 bytes (8 DWORDS). + * This is required when the Advanced Timestamp feature or the IPC Full Offload + * Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not + * required if the Advanced Timestamp and IPC Full Checksum Offload (Type 2) + * features are not enabled. In such cases, you can use the 16 bytes descriptor to + * save 4 bytes of memory. + * + * When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). + * + * This bit preserves the backward compatibility for the descriptor size. In + * versions prior to 3.50a, the descriptor size is 16 bytes for both normal and + * enhanced descriptor. In version 3.50a, descriptor size is increased to 32 bytes + * because of the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) + * features. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST | 0x0 | MAC DMA Controller Clears Logic + * ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST | 0x1 | MAC DMA Controller Resets Logic + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS + * + * MAC DMA Controller Clears Logic + */ +#define ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS + * + * MAC DMA Controller Resets Logic + */ +#define ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */ +#define ALT_EMAC_DMA_BUS_MOD_ATDS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */ +#define ALT_EMAC_DMA_BUS_MOD_ATDS_MSB 7 +/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */ +#define ALT_EMAC_DMA_BUS_MOD_ATDS_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_ATDS register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_ATDS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_ATDS register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_ATDS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */ +#define ALT_EMAC_DMA_BUS_MOD_ATDS_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_BUS_MOD_ATDS field value from a register. */ +#define ALT_EMAC_DMA_BUS_MOD_ATDS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_DMA_BUS_MOD_ATDS register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_BUS_MOD_ATDS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Programmable Burst Length - pbl + * + * These bits indicate the maximum number of beats to be transferred in one DMA + * transaction. This is the maximum value that is used in a single block Read or + * Write. The DMA always attempts to burst as specified in PBL each time it starts + * a Burst transfer on the host bus. PBL can be programmed with permissible values + * of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When + * USP is set high, this PBL value is applicable only for Tx DMA transactions. + * + * If the number of beats to be transferred is more than 32, then perform the + * following steps: + * + * 1. Set the 8xPBL mode. + * + * 2. Set the PBL. + * + * For example, if the maximum number of beats to be transferred is 64, then first + * set 8xPBL to 1 and then set PBL to 8. The PBL values have the following + * limitation: The maximum number of possible beats (PBL) is limited by the size of + * the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The + * FIFO has a constraint that the maximum beat supported is half the depth of the + * FIFO, except when specified. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_PBL_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_PBL_MSB 13 +/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_PBL_WIDTH 6 +/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_PBL register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_PBL_SET_MSK 0x00003f00 +/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_PBL register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_PBL_CLR_MSK 0xffffc0ff +/* The reset value of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_PBL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_BUS_MOD_PBL field value from a register. */ +#define ALT_EMAC_DMA_BUS_MOD_PBL_GET(value) (((value) & 0x00003f00) >> 8) +/* Produces a ALT_EMAC_DMA_BUS_MOD_PBL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_BUS_MOD_PBL_SET(value) (((value) << 8) & 0x00003f00) + +/* + * Field : Fixed Burst - fb + * + * This bit controls whether the AXI Master interface performs fixed burst + * transfers or not. When set, the AXI interface uses FIXED bursts during the start + * of the normal burst transfers. When reset, the AXI interface uses SINGLE and + * INCR burst transfer operations. + * + * For more information, see Bit 0 (UNDEFINED) of the AXI Bus Mode register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------- + * ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB | 0x0 | SINGLE or INCR Burst + * ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 | 0x1 | FIXED Burst (1, 4, 8, or 16) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB + * + * SINGLE or INCR Burst + */ +#define ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB + * + * FIXED Burst (1, 4, 8, or 16) + */ +#define ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field. */ +#define ALT_EMAC_DMA_BUS_MOD_FB_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field. */ +#define ALT_EMAC_DMA_BUS_MOD_FB_MSB 16 +/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_FB register field. */ +#define ALT_EMAC_DMA_BUS_MOD_FB_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_FB register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_FB_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_FB register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_FB_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_DMA_BUS_MOD_FB register field. */ +#define ALT_EMAC_DMA_BUS_MOD_FB_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_BUS_MOD_FB field value from a register. */ +#define ALT_EMAC_DMA_BUS_MOD_FB_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_DMA_BUS_MOD_FB register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_BUS_MOD_FB_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Rx DMA PBL - rpbl + * + * This field indicates the maximum number of beats to be transferred in one Rx DMA + * transaction. This is the maximum value that is used in a single block Read or + * Write. + * + * The Rx DMA always attempts to burst as specified in the RPBL bit each time it + * starts a Burst transfer on the host bus. You can program RPBL with values of 1, + * 2, 4, 8, 16, and 32. Any other value results in undefined behavior. + * + * This field is valid and applicable only when USP is set high. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------------------------- + * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1 | 0x1 | Beats Trans. in one Rx DMA Transaction + * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2 | 0x2 | Beats Trans. in one Rx DMA Transaction + * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4 | 0x4 | Beats Trans. in one Rx DMA Transaction + * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8 | 0x8 | Beats Trans. in one Rx DMA Transaction + * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6 | 0x10 | Beats Trans. in one Rx DMA Transaction + * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 | 0x20 | Beats Trans. in one Rx DMA Transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL + * + * Beats Trans. in one Rx DMA Transaction + */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1 0x1 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL + * + * Beats Trans. in one Rx DMA Transaction + */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2 0x2 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL + * + * Beats Trans. in one Rx DMA Transaction + */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4 0x4 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL + * + * Beats Trans. in one Rx DMA Transaction + */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8 0x8 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL + * + * Beats Trans. in one Rx DMA Transaction + */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6 0x10 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL + * + * Beats Trans. in one Rx DMA Transaction + */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 0x20 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_MSB 22 +/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_WIDTH 6 +/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_RPBL register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_SET_MSK 0x007e0000 +/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_RPBL register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_CLR_MSK 0xff81ffff +/* The reset value of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_BUS_MOD_RPBL field value from a register. */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_GET(value) (((value) & 0x007e0000) >> 17) +/* Produces a ALT_EMAC_DMA_BUS_MOD_RPBL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_BUS_MOD_RPBL_SET(value) (((value) << 17) & 0x007e0000) + +/* + * Field : Use Separate PBL - usp + * + * When set high, this bit configures the Rx DMA to use the value configured in + * Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA + * operations. + * + * When reset to low, the PBL value in Bits[13:8] is applicable for both DMA + * engines. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------- + * ALT_EMAC_DMA_BUS_MOD_USP_E_DISD | 0x0 | Configures TX RX DMA to PBL + * ALT_EMAC_DMA_BUS_MOD_USP_E_END | 0x1 | Configures TX DMA to PBL + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP + * + * Configures TX RX DMA to PBL + */ +#define ALT_EMAC_DMA_BUS_MOD_USP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP + * + * Configures TX DMA to PBL + */ +#define ALT_EMAC_DMA_BUS_MOD_USP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field. */ +#define ALT_EMAC_DMA_BUS_MOD_USP_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field. */ +#define ALT_EMAC_DMA_BUS_MOD_USP_MSB 23 +/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_USP register field. */ +#define ALT_EMAC_DMA_BUS_MOD_USP_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_USP register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_USP_SET_MSK 0x00800000 +/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_USP register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_USP_CLR_MSK 0xff7fffff +/* The reset value of the ALT_EMAC_DMA_BUS_MOD_USP register field. */ +#define ALT_EMAC_DMA_BUS_MOD_USP_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_BUS_MOD_USP field value from a register. */ +#define ALT_EMAC_DMA_BUS_MOD_USP_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_EMAC_DMA_BUS_MOD_USP register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_BUS_MOD_USP_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : 8xPBL Mode - eightxpbl + * + * When set high, this bit multiplies the programmed PBL value (Bits[22:17] and + * Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, + * 128, and 256 beats depending on the PBL value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------------- + * ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD | 0x0 | Non Multiply Mode + * ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END | 0x1 | Multiplies PBL value by 8 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL + * + * Non Multiply Mode + */ +#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL + * + * Multiplies PBL value by 8 + */ +#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_MSB 24 +/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL field value from a register. */ +#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Address Aligned Beats - aal + * + * When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface + * generates all bursts aligned to the start address LS bits. If the FB bit is + * equal to 0, the first burst (accessing the data buffer's start address) is not + * aligned, but subsequent bursts are aligned to the address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------------------- + * ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD | 0x0 | No Address-Aligned Beats + * ALT_EMAC_DMA_BUS_MOD_AAL_E_END | 0x1 | Address-Aligned Beats (dependent on FB) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL + * + * No Address-Aligned Beats + */ +#define ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL + * + * Address-Aligned Beats (dependent on FB) + */ +#define ALT_EMAC_DMA_BUS_MOD_AAL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_AAL_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_AAL_MSB 25 +/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_AAL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_AAL register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_AAL_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_AAL register field value. */ +#define ALT_EMAC_DMA_BUS_MOD_AAL_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */ +#define ALT_EMAC_DMA_BUS_MOD_AAL_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_BUS_MOD_AAL field value from a register. */ +#define ALT_EMAC_DMA_BUS_MOD_AAL_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_DMA_BUS_MOD_AAL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_BUS_MOD_AAL_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_BUS_MOD. + */ +struct ALT_EMAC_DMA_BUS_MOD_s +{ + uint32_t swr : 1; /* Software Reset */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t dsl : 5; /* Descriptor Skip Length */ + uint32_t atds : 1; /* Alternate Descriptor Size */ + uint32_t pbl : 6; /* Programmable Burst Length */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t fb : 1; /* Fixed Burst */ + uint32_t rpbl : 6; /* Rx DMA PBL */ + uint32_t usp : 1; /* Use Separate PBL */ + uint32_t eightxpbl : 1; /* 8xPBL Mode */ + uint32_t aal : 1; /* Address Aligned Beats */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_BUS_MOD. */ +typedef volatile struct ALT_EMAC_DMA_BUS_MOD_s ALT_EMAC_DMA_BUS_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_BUS_MOD register from the beginning of the component. */ +#define ALT_EMAC_DMA_BUS_MOD_OFST 0x0 +/* The address of the ALT_EMAC_DMA_BUS_MOD register. */ +#define ALT_EMAC_DMA_BUS_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_BUS_MOD_OFST)) + +/* + * Register : Register 1 (Transmit Poll Demand Register) - Transmit_Poll_Demand + * + * The Transmit Poll Demand register enables the Tx DMA to check whether or not the + * DMA owns the current descriptor. The Transmit Poll Demand command is given to + * wake up the Tx DMA if it is in the Suspend mode. The Tx DMA can go into the + * Suspend mode because of an Underflow error in a transmitted frame or the + * unavailability of descriptors owned by it. You can give this command anytime and + * the Tx DMA resets this command when it again starts fetching the current + * descriptor from host memory. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | RW | 0x0 | Transmit Poll Demand + * + */ +/* + * Field : Transmit Poll Demand - tpd + * + * When these bits are written with any value, the DMA reads the current descriptor + * pointed to by Register 18 (Current Host Transmit Descriptor Register). If that + * descriptor is not available (owned by the Host), the transmission returns to the + * Suspend state and the Bit 2 (TU) of Register 5 (Status Register) is asserted. If + * the descriptor is available, the transmission resumes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */ +#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */ +#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_MSB 31 +/* The width in bits of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */ +#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_WIDTH 32 +/* The mask used to set the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value. */ +#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value. */ +#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */ +#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD field value from a register. */ +#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_TX_POLL_DEMAND. + */ +struct ALT_EMAC_DMA_TX_POLL_DEMAND_s +{ + uint32_t tpd : 32; /* Transmit Poll Demand */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_TX_POLL_DEMAND. */ +typedef volatile struct ALT_EMAC_DMA_TX_POLL_DEMAND_s ALT_EMAC_DMA_TX_POLL_DEMAND_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_TX_POLL_DEMAND register from the beginning of the component. */ +#define ALT_EMAC_DMA_TX_POLL_DEMAND_OFST 0x4 +/* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register. */ +#define ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TX_POLL_DEMAND_OFST)) + +/* + * Register : Register 2 (Receive Poll Demand Register) - Receive_Poll_Demand + * + * The Receive Poll Demand register enables the receive DMA to check for new + * descriptors. This command is used to wake up the Rx DMA from the SUSPEND state. + * The RxDMA can go into the SUSPEND state only because of the unavailability of + * descriptors it owns. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [31:0] | RW | 0x0 | Receive Poll Demand + * + */ +/* + * Field : Receive Poll Demand - rpd + * + * When these bits are written with any value, the DMA reads the current descriptor + * pointed to by Register 19 (Current Host Receive Descriptor Register). If that + * descriptor is not available (owned by the Host), the reception returns to the + * Suspended state and the Bit 7 (RU) of Register 5 (Status Register) is not + * asserted. If the descriptor is available, the Rx DMA returns to the active + * state. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */ +#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */ +#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_MSB 31 +/* The width in bits of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */ +#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_WIDTH 32 +/* The mask used to set the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value. */ +#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value. */ +#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */ +#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD field value from a register. */ +#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_RX_POLL_DEMAND. + */ +struct ALT_EMAC_DMA_RX_POLL_DEMAND_s +{ + uint32_t rpd : 32; /* Receive Poll Demand */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_RX_POLL_DEMAND. */ +typedef volatile struct ALT_EMAC_DMA_RX_POLL_DEMAND_s ALT_EMAC_DMA_RX_POLL_DEMAND_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_RX_POLL_DEMAND register from the beginning of the component. */ +#define ALT_EMAC_DMA_RX_POLL_DEMAND_OFST 0x8 +/* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register. */ +#define ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_POLL_DEMAND_OFST)) + +/* + * Register : Register 3 (Receive Descriptor List Address Register) - Receive_Descriptor_List_Address + * + * The Receive Descriptor List Address register points to the start of the Receive + * Descriptor List. The descriptor lists reside in the host's physical memory space + * and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data + * bus). The DMA internally converts it to bus width aligned address by making the + * corresponding LS bits low. Writing to this register is permitted only when + * reception is stopped. When stopped, this register must be written to before the + * receive Start command is given. + * + * You can write to this register only when Rx DMA has stopped, that is, Bit 1 (SR) + * is set to zero in Register 6 (Operation Mode Register). When stopped, this + * register can be written with a new descriptor list address. When you set the SR + * bit to 1, the DMA takes the newly programmed descriptor base address. + * + * If this register is not changed when the SR bit is set to 0, then the DMA takes + * the descriptor address where it was stopped earlier. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [1:0] | ??? | 0x0 | *UNDEFINED* + * [31:2] | RW | 0x0 | Start of Receive List + * + */ +/* + * Field : Start of Receive List - rdesla_32bit + * + * This field contains the base address of the first descriptor in the Receive + * Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and internally + * taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */ +#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */ +#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_MSB 31 +/* The width in bits of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */ +#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_WIDTH 30 +/* The mask used to set the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value. */ +#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_SET_MSK 0xfffffffc +/* The mask used to clear the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value. */ +#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_CLR_MSK 0x00000003 +/* The reset value of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */ +#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT field value from a register. */ +#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2) +/* Produces a ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_RX_DESC_LIST_ADDR. + */ +struct ALT_EMAC_DMA_RX_DESC_LIST_ADDR_s +{ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t rdesla_32bit : 30; /* Start of Receive List */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_RX_DESC_LIST_ADDR. */ +typedef volatile struct ALT_EMAC_DMA_RX_DESC_LIST_ADDR_s ALT_EMAC_DMA_RX_DESC_LIST_ADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register from the beginning of the component. */ +#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_OFST 0xc +/* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register. */ +#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_DESC_LIST_ADDR_OFST)) + +/* + * Register : Register 4 (Transmit Descriptor List Address Register) - Transmit_Descriptor_List_Address + * + * The Transmit Descriptor List Address register points to the start of the + * Transmit Descriptor List. The descriptor lists reside in the host's physical + * memory space and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or + * 128-bit data bus). The DMA internally converts it to bus width aligned address + * by making the corresponding LSB to low. + * + * You can write to this register only when the Tx DMA has stopped, that is, Bit 13 + * (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this + * register can be written with a new descriptor list address. When you set the ST + * bit to 1, the DMA takes the newly programmed descriptor base address. + * + * If this register is not changed when the ST bit is set to 0, then the DMA takes + * the descriptor address where it was stopped earlier. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [1:0] | ??? | 0x0 | *UNDEFINED* + * [31:2] | RW | 0x0 | Start of Transmit List + * + */ +/* + * Field : Start of Transmit List - tdesla_32bit + * + * This field contains the base address of the first descriptor in the Transmit + * Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and are + * internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only + * (RO). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */ +#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */ +#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_MSB 31 +/* The width in bits of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */ +#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_WIDTH 30 +/* The mask used to set the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value. */ +#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_SET_MSK 0xfffffffc +/* The mask used to clear the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value. */ +#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_CLR_MSK 0x00000003 +/* The reset value of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */ +#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT field value from a register. */ +#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2) +/* Produces a ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_TX_DESC_LIST_ADDR. + */ +struct ALT_EMAC_DMA_TX_DESC_LIST_ADDR_s +{ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t tdesla_32bit : 30; /* Start of Transmit List */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_TX_DESC_LIST_ADDR. */ +typedef volatile struct ALT_EMAC_DMA_TX_DESC_LIST_ADDR_s ALT_EMAC_DMA_TX_DESC_LIST_ADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register from the beginning of the component. */ +#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_OFST 0x10 +/* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register. */ +#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TX_DESC_LIST_ADDR_OFST)) + +/* + * Register : Register 5 (Status Register) - Status + * + * The Status register contains all status bits that the DMA reports to the host. + * The software driver reads this register during an interrupt service routine or + * polling. Most of the fields in this register cause the host to be interrupted. + * The bits of this register are not cleared when read. Writing 1'b1 to + * (unreserved) Bits[16:0] of this register clears these bits and writing 1'b0 has + * no effect. Each field (Bits[16:0]) can be masked by masking the appropriate bit + * in Register 7 (Interrupt Enable Register). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | Transmit Interrupt + * [1] | RW | 0x0 | Transmit Process Stopped + * [2] | RW | 0x0 | Transmit Buffer Unavailable + * [3] | RW | 0x0 | Transmit Jabber Timeout + * [4] | RW | 0x0 | Receive Overflow + * [5] | RW | 0x0 | Transmit Underflow + * [6] | RW | 0x0 | Receive Interrupt + * [7] | RW | 0x0 | Receive Buffer Unavailable + * [8] | RW | 0x0 | Receive Process Stopped + * [9] | RW | 0x0 | Receive Watchdog Timeout + * [10] | RW | 0x0 | Early Transmit Interrupt + * [12:11] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Fatal Bus Error Interrupt + * [14] | RW | 0x0 | Early Receive Interrupt + * [15] | RW | 0x0 | Abnormal Interrupt Summary + * [16] | RW | 0x0 | Normal Interrupt Summary + * [19:17] | R | 0x0 | Received Process State + * [22:20] | R | 0x0 | Transmit Process State + * [25:23] | R | 0x0 | Error Bits + * [26] | R | 0x0 | GMAC Line Interface Interrupt + * [27] | R | 0x0 | GMAC MMC Interrupt + * [28] | ??? | 0x0 | *UNDEFINED* + * [29] | R | 0x0 | Timestamp Trigger Interrupt + * [30] | R | 0x0 | GMAC LPI Interrupt (for Channel 0) + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit Interrupt - ti + * + * This bit indicates that the frame transmission is complete. When transmission is + * complete, the Bit 31 (Interrupt on Completion) of TDES1 is reset in the first + * descriptor, and the specific frame status information is updated in the + * descriptor. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TI register field. */ +#define ALT_EMAC_DMA_STAT_TI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TI register field. */ +#define ALT_EMAC_DMA_STAT_TI_MSB 0 +/* The width in bits of the ALT_EMAC_DMA_STAT_TI register field. */ +#define ALT_EMAC_DMA_STAT_TI_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_TI register field value. */ +#define ALT_EMAC_DMA_STAT_TI_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_DMA_STAT_TI register field value. */ +#define ALT_EMAC_DMA_STAT_TI_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_DMA_STAT_TI register field. */ +#define ALT_EMAC_DMA_STAT_TI_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_TI field value from a register. */ +#define ALT_EMAC_DMA_STAT_TI_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_DMA_STAT_TI register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_TI_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit Process Stopped - tps + * + * This bit is set when the transmission is stopped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TPS register field. */ +#define ALT_EMAC_DMA_STAT_TPS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TPS register field. */ +#define ALT_EMAC_DMA_STAT_TPS_MSB 1 +/* The width in bits of the ALT_EMAC_DMA_STAT_TPS register field. */ +#define ALT_EMAC_DMA_STAT_TPS_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_TPS register field value. */ +#define ALT_EMAC_DMA_STAT_TPS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_DMA_STAT_TPS register field value. */ +#define ALT_EMAC_DMA_STAT_TPS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_DMA_STAT_TPS register field. */ +#define ALT_EMAC_DMA_STAT_TPS_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_TPS field value from a register. */ +#define ALT_EMAC_DMA_STAT_TPS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_DMA_STAT_TPS register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_TPS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Transmit Buffer Unavailable - tu + * + * This bit indicates that the host owns the Next Descriptor in the Transmit List + * and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain + * the Transmit Process state transitions. + * + * To resume processing Transmit descriptors, the host should change the ownership + * of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand + * command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TU register field. */ +#define ALT_EMAC_DMA_STAT_TU_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TU register field. */ +#define ALT_EMAC_DMA_STAT_TU_MSB 2 +/* The width in bits of the ALT_EMAC_DMA_STAT_TU register field. */ +#define ALT_EMAC_DMA_STAT_TU_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_TU register field value. */ +#define ALT_EMAC_DMA_STAT_TU_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_DMA_STAT_TU register field value. */ +#define ALT_EMAC_DMA_STAT_TU_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_DMA_STAT_TU register field. */ +#define ALT_EMAC_DMA_STAT_TU_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_TU field value from a register. */ +#define ALT_EMAC_DMA_STAT_TU_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_DMA_STAT_TU register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_TU_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Transmit Jabber Timeout - tjt + * + * This bit indicates that the Transmit Jabber Timer expired, which happens when + * the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). + * When the Jabber Timeout occurs, the transmission process is aborted and placed + * in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to + * assert. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TJT register field. */ +#define ALT_EMAC_DMA_STAT_TJT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TJT register field. */ +#define ALT_EMAC_DMA_STAT_TJT_MSB 3 +/* The width in bits of the ALT_EMAC_DMA_STAT_TJT register field. */ +#define ALT_EMAC_DMA_STAT_TJT_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_TJT register field value. */ +#define ALT_EMAC_DMA_STAT_TJT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_DMA_STAT_TJT register field value. */ +#define ALT_EMAC_DMA_STAT_TJT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_DMA_STAT_TJT register field. */ +#define ALT_EMAC_DMA_STAT_TJT_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_TJT field value from a register. */ +#define ALT_EMAC_DMA_STAT_TJT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_DMA_STAT_TJT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_TJT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive Overflow - ovf + * + * This bit indicates that the Receive Buffer had an Overflow during frame + * reception. If the partial frame is transferred to the application, the overflow + * status is set in RDES0[11]. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_OVF register field. */ +#define ALT_EMAC_DMA_STAT_OVF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_OVF register field. */ +#define ALT_EMAC_DMA_STAT_OVF_MSB 4 +/* The width in bits of the ALT_EMAC_DMA_STAT_OVF register field. */ +#define ALT_EMAC_DMA_STAT_OVF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_OVF register field value. */ +#define ALT_EMAC_DMA_STAT_OVF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_DMA_STAT_OVF register field value. */ +#define ALT_EMAC_DMA_STAT_OVF_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_DMA_STAT_OVF register field. */ +#define ALT_EMAC_DMA_STAT_OVF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_OVF field value from a register. */ +#define ALT_EMAC_DMA_STAT_OVF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_DMA_STAT_OVF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_OVF_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Transmit Underflow - unf + * + * This bit indicates that the Transmit Buffer had an Underflow during frame + * transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_UNF register field. */ +#define ALT_EMAC_DMA_STAT_UNF_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_UNF register field. */ +#define ALT_EMAC_DMA_STAT_UNF_MSB 5 +/* The width in bits of the ALT_EMAC_DMA_STAT_UNF register field. */ +#define ALT_EMAC_DMA_STAT_UNF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_UNF register field value. */ +#define ALT_EMAC_DMA_STAT_UNF_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_DMA_STAT_UNF register field value. */ +#define ALT_EMAC_DMA_STAT_UNF_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_DMA_STAT_UNF register field. */ +#define ALT_EMAC_DMA_STAT_UNF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_UNF field value from a register. */ +#define ALT_EMAC_DMA_STAT_UNF_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_DMA_STAT_UNF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_UNF_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Receive Interrupt - ri + * + * This bit indicates that the frame reception is complete. When reception is + * complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the + * last Descriptor, and the specific frame status information is updated in the + * descriptor. + * + * The reception remains in the Running state. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RI register field. */ +#define ALT_EMAC_DMA_STAT_RI_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RI register field. */ +#define ALT_EMAC_DMA_STAT_RI_MSB 6 +/* The width in bits of the ALT_EMAC_DMA_STAT_RI register field. */ +#define ALT_EMAC_DMA_STAT_RI_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_RI register field value. */ +#define ALT_EMAC_DMA_STAT_RI_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_DMA_STAT_RI register field value. */ +#define ALT_EMAC_DMA_STAT_RI_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_DMA_STAT_RI register field. */ +#define ALT_EMAC_DMA_STAT_RI_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_RI field value from a register. */ +#define ALT_EMAC_DMA_STAT_RI_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_DMA_STAT_RI register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_RI_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Buffer Unavailable - ru + * + * This bit indicates that the host owns the Next Descriptor in the Receive List + * and the DMA cannot acquire it. The Receive Process is suspended. To resume + * processing Receive descriptors, the host should change the ownership of the + * descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is + * issued, the Receive Process resumes when the next recognized incoming frame is + * received. This bit is set only when the previous Receive Descriptor is owned by + * the DMA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RU register field. */ +#define ALT_EMAC_DMA_STAT_RU_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RU register field. */ +#define ALT_EMAC_DMA_STAT_RU_MSB 7 +/* The width in bits of the ALT_EMAC_DMA_STAT_RU register field. */ +#define ALT_EMAC_DMA_STAT_RU_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_RU register field value. */ +#define ALT_EMAC_DMA_STAT_RU_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_DMA_STAT_RU register field value. */ +#define ALT_EMAC_DMA_STAT_RU_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_DMA_STAT_RU register field. */ +#define ALT_EMAC_DMA_STAT_RU_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_RU field value from a register. */ +#define ALT_EMAC_DMA_STAT_RU_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_DMA_STAT_RU register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_RU_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Receive Process Stopped - rps + * + * This bit is asserted when the Receive Process enters the Stopped state. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RPS register field. */ +#define ALT_EMAC_DMA_STAT_RPS_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RPS register field. */ +#define ALT_EMAC_DMA_STAT_RPS_MSB 8 +/* The width in bits of the ALT_EMAC_DMA_STAT_RPS register field. */ +#define ALT_EMAC_DMA_STAT_RPS_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_RPS register field value. */ +#define ALT_EMAC_DMA_STAT_RPS_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_DMA_STAT_RPS register field value. */ +#define ALT_EMAC_DMA_STAT_RPS_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_DMA_STAT_RPS register field. */ +#define ALT_EMAC_DMA_STAT_RPS_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_RPS field value from a register. */ +#define ALT_EMAC_DMA_STAT_RPS_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_DMA_STAT_RPS register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_RPS_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Receive Watchdog Timeout - rwt + * + * This bit is asserted when a frame with length greater than 2,048 bytes is + * received (10, 240 when Jumbo Frame mode is enabled). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RWT register field. */ +#define ALT_EMAC_DMA_STAT_RWT_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RWT register field. */ +#define ALT_EMAC_DMA_STAT_RWT_MSB 9 +/* The width in bits of the ALT_EMAC_DMA_STAT_RWT register field. */ +#define ALT_EMAC_DMA_STAT_RWT_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_RWT register field value. */ +#define ALT_EMAC_DMA_STAT_RWT_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_DMA_STAT_RWT register field value. */ +#define ALT_EMAC_DMA_STAT_RWT_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_DMA_STAT_RWT register field. */ +#define ALT_EMAC_DMA_STAT_RWT_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_RWT field value from a register. */ +#define ALT_EMAC_DMA_STAT_RWT_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_DMA_STAT_RWT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_RWT_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Early Transmit Interrupt - eti + * + * This bit indicates that the frame to be transmitted is fully transferred to the + * MTL Transmit FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_ETI register field. */ +#define ALT_EMAC_DMA_STAT_ETI_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_ETI register field. */ +#define ALT_EMAC_DMA_STAT_ETI_MSB 10 +/* The width in bits of the ALT_EMAC_DMA_STAT_ETI register field. */ +#define ALT_EMAC_DMA_STAT_ETI_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_ETI register field value. */ +#define ALT_EMAC_DMA_STAT_ETI_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_DMA_STAT_ETI register field value. */ +#define ALT_EMAC_DMA_STAT_ETI_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_DMA_STAT_ETI register field. */ +#define ALT_EMAC_DMA_STAT_ETI_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_ETI field value from a register. */ +#define ALT_EMAC_DMA_STAT_ETI_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_DMA_STAT_ETI register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_ETI_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Fatal Bus Error Interrupt - fbi + * + * This bit indicates that a bus error occurred, as described in Bits[25:23]. When + * this bit is set, the corresponding DMA engine disables all of its bus accesses. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_FBI register field. */ +#define ALT_EMAC_DMA_STAT_FBI_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_FBI register field. */ +#define ALT_EMAC_DMA_STAT_FBI_MSB 13 +/* The width in bits of the ALT_EMAC_DMA_STAT_FBI register field. */ +#define ALT_EMAC_DMA_STAT_FBI_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_FBI register field value. */ +#define ALT_EMAC_DMA_STAT_FBI_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_FBI register field value. */ +#define ALT_EMAC_DMA_STAT_FBI_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_DMA_STAT_FBI register field. */ +#define ALT_EMAC_DMA_STAT_FBI_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_FBI field value from a register. */ +#define ALT_EMAC_DMA_STAT_FBI_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_DMA_STAT_FBI register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_FBI_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Early Receive Interrupt - eri + * + * This bit indicates that the DMA had filled the first data buffer of the packet. + * Bit 6 (RI) of this register automatically clears this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_ERI register field. */ +#define ALT_EMAC_DMA_STAT_ERI_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_ERI register field. */ +#define ALT_EMAC_DMA_STAT_ERI_MSB 14 +/* The width in bits of the ALT_EMAC_DMA_STAT_ERI register field. */ +#define ALT_EMAC_DMA_STAT_ERI_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_ERI register field value. */ +#define ALT_EMAC_DMA_STAT_ERI_SET_MSK 0x00004000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_ERI register field value. */ +#define ALT_EMAC_DMA_STAT_ERI_CLR_MSK 0xffffbfff +/* The reset value of the ALT_EMAC_DMA_STAT_ERI register field. */ +#define ALT_EMAC_DMA_STAT_ERI_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_ERI field value from a register. */ +#define ALT_EMAC_DMA_STAT_ERI_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_EMAC_DMA_STAT_ERI register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_ERI_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Abnormal Interrupt Summary - ais + * + * Abnormal Interrupt Summary bit value is the logical OR of the following when the + * corresponding interrupt bits are enabled in Register 7 (Interrupt Enable + * Register): + * + * * Register 5[1]: Transmit Process Stopped + * + * * Register 5[3]: Transmit Jabber Timeout + * + * * Register 5[4]: Receive FIFO Overflow + * + * * Register 5[5]: Transmit Underflow + * + * * Register 5[7]: Receive Buffer Unavailable + * + * * Register 5[8]: Receive Process Stopped + * + * * Register 5[9]: Receive Watchdog Timeout + * + * * Register 5[10]: Early Transmit Interrupt + * + * * Register 5[13]: Fatal Bus Error + * + * Only unmasked bits affect the Abnormal Interrupt Summary bit. + * + * This is a sticky bit and must be cleared each time a corresponding bit, which + * causes AIS to be set, is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_AIS register field. */ +#define ALT_EMAC_DMA_STAT_AIS_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_AIS register field. */ +#define ALT_EMAC_DMA_STAT_AIS_MSB 15 +/* The width in bits of the ALT_EMAC_DMA_STAT_AIS register field. */ +#define ALT_EMAC_DMA_STAT_AIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_AIS register field value. */ +#define ALT_EMAC_DMA_STAT_AIS_SET_MSK 0x00008000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_AIS register field value. */ +#define ALT_EMAC_DMA_STAT_AIS_CLR_MSK 0xffff7fff +/* The reset value of the ALT_EMAC_DMA_STAT_AIS register field. */ +#define ALT_EMAC_DMA_STAT_AIS_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_AIS field value from a register. */ +#define ALT_EMAC_DMA_STAT_AIS_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_EMAC_DMA_STAT_AIS register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_AIS_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Normal Interrupt Summary - nis + * + * Normal Interrupt Summary bit value is the logical OR of the following when the + * corresponding interrupt bits are enabled in Register 7 (Interrupt Enable + * Register): + * + * * Register 5[0]: Transmit Interrupt + * + * * Register 5[2]: Transmit Buffer Unavailable + * + * * Register 5[6]: Receive Interrupt + * + * * Register 5[14]: Early Receive Interrupt + * + * Only unmasked bits (interrupts for which interrupt enable is set in Register 7) + * affect the Normal Interrupt Summary bit. + * + * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a + * corresponding bit, which causes NIS to be set, is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_NIS register field. */ +#define ALT_EMAC_DMA_STAT_NIS_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_NIS register field. */ +#define ALT_EMAC_DMA_STAT_NIS_MSB 16 +/* The width in bits of the ALT_EMAC_DMA_STAT_NIS register field. */ +#define ALT_EMAC_DMA_STAT_NIS_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_NIS register field value. */ +#define ALT_EMAC_DMA_STAT_NIS_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_NIS register field value. */ +#define ALT_EMAC_DMA_STAT_NIS_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_DMA_STAT_NIS register field. */ +#define ALT_EMAC_DMA_STAT_NIS_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_NIS field value from a register. */ +#define ALT_EMAC_DMA_STAT_NIS_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_DMA_STAT_NIS register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_NIS_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Received Process State - rs + * + * This field indicates the Receive DMA FSM state. This field does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_EMAC_DMA_STAT_RS_E_STOPPED | 0x0 | Stopped Reset or Stop Receive Command issued + * ALT_EMAC_DMA_STAT_RS_E_RUNFETCH | 0x1 | Running: Fetching Receive Transfer Descriptor + * ALT_EMAC_DMA_STAT_RS_E_RESERVE | 0x2 | Reserved for future use + * ALT_EMAC_DMA_STAT_RS_E_RUNWAIT | 0x3 | Running: Waiting for receive packet + * ALT_EMAC_DMA_STAT_RS_E_SUSPEND | 0x4 | Suspended: Receive Descriptor Unavailable + * ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE | 0x5 | Running: Closing Receive Descriptor + * ALT_EMAC_DMA_STAT_RS_E_TIMESTMP | 0x6 | TIME_STAMP write state + * ALT_EMAC_DMA_STAT_RS_E_RUNTRANS | 0x7 | Transferring rcv packet data from receive buffer + * : | | to host memory + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_RS + * + * Stopped Reset or Stop Receive Command issued + */ +#define ALT_EMAC_DMA_STAT_RS_E_STOPPED 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_RS + * + * Running: Fetching Receive Transfer Descriptor + */ +#define ALT_EMAC_DMA_STAT_RS_E_RUNFETCH 0x1 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_RS + * + * Reserved for future use + */ +#define ALT_EMAC_DMA_STAT_RS_E_RESERVE 0x2 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_RS + * + * Running: Waiting for receive packet + */ +#define ALT_EMAC_DMA_STAT_RS_E_RUNWAIT 0x3 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_RS + * + * Suspended: Receive Descriptor Unavailable + */ +#define ALT_EMAC_DMA_STAT_RS_E_SUSPEND 0x4 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_RS + * + * Running: Closing Receive Descriptor + */ +#define ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE 0x5 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_RS + * + * TIME_STAMP write state + */ +#define ALT_EMAC_DMA_STAT_RS_E_TIMESTMP 0x6 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_RS + * + * Transferring rcv packet data from receive buffer to host memory + */ +#define ALT_EMAC_DMA_STAT_RS_E_RUNTRANS 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RS register field. */ +#define ALT_EMAC_DMA_STAT_RS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RS register field. */ +#define ALT_EMAC_DMA_STAT_RS_MSB 19 +/* The width in bits of the ALT_EMAC_DMA_STAT_RS register field. */ +#define ALT_EMAC_DMA_STAT_RS_WIDTH 3 +/* The mask used to set the ALT_EMAC_DMA_STAT_RS register field value. */ +#define ALT_EMAC_DMA_STAT_RS_SET_MSK 0x000e0000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_RS register field value. */ +#define ALT_EMAC_DMA_STAT_RS_CLR_MSK 0xfff1ffff +/* The reset value of the ALT_EMAC_DMA_STAT_RS register field. */ +#define ALT_EMAC_DMA_STAT_RS_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_RS field value from a register. */ +#define ALT_EMAC_DMA_STAT_RS_GET(value) (((value) & 0x000e0000) >> 17) +/* Produces a ALT_EMAC_DMA_STAT_RS register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_RS_SET(value) (((value) << 17) & 0x000e0000) + +/* + * Field : Transmit Process State - ts + * + * This field indicates the Transmit DMA FSM state. This field does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------------------------- + * ALT_EMAC_DMA_STAT_TS_E_STOPPED | 0x0 | Stopped Reset or Stop Transmit Command + * ALT_EMAC_DMA_STAT_TS_E_RUNFETCH | 0x1 | Running: Fetching Tranmit Transfer Descriptor + * ALT_EMAC_DMA_STAT_TS_E_RUNWAIT | 0x2 | Running; Waiting for status + * ALT_EMAC_DMA_STAT_TS_E_RUNRD | 0x3 | Running; Reading Data host memory buffer and + * : | | queuing it to transmit buffer (Tx FIFO) + * ALT_EMAC_DMA_STAT_TS_E_TIMESTMP | 0x4 | TIME_STAMP write state + * ALT_EMAC_DMA_STAT_TS_E_RESERVE | 0x5 | Reserved for future use + * ALT_EMAC_DMA_STAT_TS_E_SUSPTX | 0x6 | Suspended; Transmit Descriptor Unavailable or + * : | | Transmit Buffer Underflow + * ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE | 0x7 | Running; Closing Transmit Descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_TS + * + * Stopped Reset or Stop Transmit Command + */ +#define ALT_EMAC_DMA_STAT_TS_E_STOPPED 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_TS + * + * Running: Fetching Tranmit Transfer Descriptor + */ +#define ALT_EMAC_DMA_STAT_TS_E_RUNFETCH 0x1 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_TS + * + * Running; Waiting for status + */ +#define ALT_EMAC_DMA_STAT_TS_E_RUNWAIT 0x2 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_TS + * + * Running; Reading Data host memory buffer and queuing it to transmit buffer (Tx + * FIFO) + */ +#define ALT_EMAC_DMA_STAT_TS_E_RUNRD 0x3 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_TS + * + * TIME_STAMP write state + */ +#define ALT_EMAC_DMA_STAT_TS_E_TIMESTMP 0x4 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_TS + * + * Reserved for future use + */ +#define ALT_EMAC_DMA_STAT_TS_E_RESERVE 0x5 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_TS + * + * Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow + */ +#define ALT_EMAC_DMA_STAT_TS_E_SUSPTX 0x6 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_TS + * + * Running; Closing Transmit Descriptor + */ +#define ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TS register field. */ +#define ALT_EMAC_DMA_STAT_TS_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TS register field. */ +#define ALT_EMAC_DMA_STAT_TS_MSB 22 +/* The width in bits of the ALT_EMAC_DMA_STAT_TS register field. */ +#define ALT_EMAC_DMA_STAT_TS_WIDTH 3 +/* The mask used to set the ALT_EMAC_DMA_STAT_TS register field value. */ +#define ALT_EMAC_DMA_STAT_TS_SET_MSK 0x00700000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_TS register field value. */ +#define ALT_EMAC_DMA_STAT_TS_CLR_MSK 0xff8fffff +/* The reset value of the ALT_EMAC_DMA_STAT_TS register field. */ +#define ALT_EMAC_DMA_STAT_TS_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_TS field value from a register. */ +#define ALT_EMAC_DMA_STAT_TS_GET(value) (((value) & 0x00700000) >> 20) +/* Produces a ALT_EMAC_DMA_STAT_TS register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_TS_SET(value) (((value) << 20) & 0x00700000) + +/* + * Field : Error Bits - eb + * + * This field indicates the type of error that caused a Bus Error, for example, + * error response on the AHB or AXI interface. This field is valid only when Bit 13 + * (FBI) is set. This field does not generate an interrupt. + * + * * Bit 23 + * + * - 1'b1: Error during data transfer by the Tx DMA + * + * - 1'b0: Error during data transfer by the Rx DMA + * + * * Bit 24 + * + * - 1'b1: Error during read transfer + * + * - 1'b0: Error during write transfer + * + * * Bit 25 + * + * - 1'b1: Error during descriptor access + * + * - 1'b0: Error during data buffer access + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_EB register field. */ +#define ALT_EMAC_DMA_STAT_EB_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_EB register field. */ +#define ALT_EMAC_DMA_STAT_EB_MSB 25 +/* The width in bits of the ALT_EMAC_DMA_STAT_EB register field. */ +#define ALT_EMAC_DMA_STAT_EB_WIDTH 3 +/* The mask used to set the ALT_EMAC_DMA_STAT_EB register field value. */ +#define ALT_EMAC_DMA_STAT_EB_SET_MSK 0x03800000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_EB register field value. */ +#define ALT_EMAC_DMA_STAT_EB_CLR_MSK 0xfc7fffff +/* The reset value of the ALT_EMAC_DMA_STAT_EB register field. */ +#define ALT_EMAC_DMA_STAT_EB_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_EB field value from a register. */ +#define ALT_EMAC_DMA_STAT_EB_GET(value) (((value) & 0x03800000) >> 23) +/* Produces a ALT_EMAC_DMA_STAT_EB register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_EB_SET(value) (((value) << 23) & 0x03800000) + +/* + * Field : GMAC Line Interface Interrupt - gli + * + * This bit reflects an interrupt event in the PCS (link change and AN complete), + * SMII (link change), or RGMII (link change) interface block of the EMAC. The + * software must read the corresponding registers (Register 49 for PCS or Register + * 54 for SMII or RGMII) in the EMAC to get the exact cause of the interrupt and + * clear the source of interrupt to make this bit as 1'b0. The interrupt signal + * from the EMAC subsystem (sbd_intr_o) is high when this bit is high. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP | 0x0 | No Interrupt + * ALT_EMAC_DMA_STAT_GLI_E_INTERRUP | 0x1 | GMAC Line Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_GLI + * + * No Interrupt + */ +#define ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_GLI + * + * GMAC Line Interrupt + */ +#define ALT_EMAC_DMA_STAT_GLI_E_INTERRUP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GLI register field. */ +#define ALT_EMAC_DMA_STAT_GLI_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GLI register field. */ +#define ALT_EMAC_DMA_STAT_GLI_MSB 26 +/* The width in bits of the ALT_EMAC_DMA_STAT_GLI register field. */ +#define ALT_EMAC_DMA_STAT_GLI_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_GLI register field value. */ +#define ALT_EMAC_DMA_STAT_GLI_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_GLI register field value. */ +#define ALT_EMAC_DMA_STAT_GLI_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_DMA_STAT_GLI register field. */ +#define ALT_EMAC_DMA_STAT_GLI_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_GLI field value from a register. */ +#define ALT_EMAC_DMA_STAT_GLI_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_DMA_STAT_GLI register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_GLI_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : GMAC MMC Interrupt - gmi + * + * This bit reflects an interrupt event in the MMC block of the EMAC. The software + * must read the corresponding registers in the EMAC to get the exact cause of + * interrupt and clear the source of interrupt to make this bit as 1'b0. The + * interrupt signal from the EMAC subsystem (sbd_intr_o) is high when this bit is + * high. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP | 0x0 | No Interrupt + * ALT_EMAC_DMA_STAT_GMI_E_INTERRUP | 0x1 | GMAC MMC Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_GMI + * + * No Interrupt + */ +#define ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_GMI + * + * GMAC MMC Interrupt + */ +#define ALT_EMAC_DMA_STAT_GMI_E_INTERRUP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GMI register field. */ +#define ALT_EMAC_DMA_STAT_GMI_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GMI register field. */ +#define ALT_EMAC_DMA_STAT_GMI_MSB 27 +/* The width in bits of the ALT_EMAC_DMA_STAT_GMI register field. */ +#define ALT_EMAC_DMA_STAT_GMI_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_GMI register field value. */ +#define ALT_EMAC_DMA_STAT_GMI_SET_MSK 0x08000000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_GMI register field value. */ +#define ALT_EMAC_DMA_STAT_GMI_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_EMAC_DMA_STAT_GMI register field. */ +#define ALT_EMAC_DMA_STAT_GMI_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_GMI field value from a register. */ +#define ALT_EMAC_DMA_STAT_GMI_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_EMAC_DMA_STAT_GMI register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_GMI_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Timestamp Trigger Interrupt - tti + * + * This bit indicates an interrupt event in the Timestamp Generator block of EMAC. + * The software must read the corresponding registers in the EMAC to get the exact + * cause of interrupt and clear its source to reset this bit to 1'b0. When this bit + * is high, the interrupt signal from the EMAC subsystem (sbd_intr_o) is high. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP | 0x0 | No Interrupt + * ALT_EMAC_DMA_STAT_TTI_E_INTERRUP | 0x1 | Timestamp Trigger Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_TTI + * + * No Interrupt + */ +#define ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_TTI + * + * Timestamp Trigger Interrupt + */ +#define ALT_EMAC_DMA_STAT_TTI_E_INTERRUP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TTI register field. */ +#define ALT_EMAC_DMA_STAT_TTI_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TTI register field. */ +#define ALT_EMAC_DMA_STAT_TTI_MSB 29 +/* The width in bits of the ALT_EMAC_DMA_STAT_TTI register field. */ +#define ALT_EMAC_DMA_STAT_TTI_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_TTI register field value. */ +#define ALT_EMAC_DMA_STAT_TTI_SET_MSK 0x20000000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_TTI register field value. */ +#define ALT_EMAC_DMA_STAT_TTI_CLR_MSK 0xdfffffff +/* The reset value of the ALT_EMAC_DMA_STAT_TTI register field. */ +#define ALT_EMAC_DMA_STAT_TTI_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_TTI field value from a register. */ +#define ALT_EMAC_DMA_STAT_TTI_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_EMAC_DMA_STAT_TTI register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_TTI_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : GMAC LPI Interrupt (for Channel 0) - glpii + * + * This bit indicates an interrupt event in the LPI logic of the EMAC. To reset + * this bit to 1'b0, the software must read the corresponding registers in the EMAC + * to get the exact cause of the interrupt and clear its source. + * + * When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------- + * ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP | 0x0 | No Interrupt + * ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP | 0x1 | GMAC LPI Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_GLPII + * + * No Interrupt + */ +#define ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_STAT_GLPII + * + * GMAC LPI Interrupt + */ +#define ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GLPII register field. */ +#define ALT_EMAC_DMA_STAT_GLPII_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GLPII register field. */ +#define ALT_EMAC_DMA_STAT_GLPII_MSB 30 +/* The width in bits of the ALT_EMAC_DMA_STAT_GLPII register field. */ +#define ALT_EMAC_DMA_STAT_GLPII_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_STAT_GLPII register field value. */ +#define ALT_EMAC_DMA_STAT_GLPII_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_DMA_STAT_GLPII register field value. */ +#define ALT_EMAC_DMA_STAT_GLPII_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_DMA_STAT_GLPII register field. */ +#define ALT_EMAC_DMA_STAT_GLPII_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_STAT_GLPII field value from a register. */ +#define ALT_EMAC_DMA_STAT_GLPII_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_DMA_STAT_GLPII register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_STAT_GLPII_SET(value) (((value) << 30) & 0x40000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_STAT. + */ +struct ALT_EMAC_DMA_STAT_s +{ + uint32_t ti : 1; /* Transmit Interrupt */ + uint32_t tps : 1; /* Transmit Process Stopped */ + uint32_t tu : 1; /* Transmit Buffer Unavailable */ + uint32_t tjt : 1; /* Transmit Jabber Timeout */ + uint32_t ovf : 1; /* Receive Overflow */ + uint32_t unf : 1; /* Transmit Underflow */ + uint32_t ri : 1; /* Receive Interrupt */ + uint32_t ru : 1; /* Receive Buffer Unavailable */ + uint32_t rps : 1; /* Receive Process Stopped */ + uint32_t rwt : 1; /* Receive Watchdog Timeout */ + uint32_t eti : 1; /* Early Transmit Interrupt */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t fbi : 1; /* Fatal Bus Error Interrupt */ + uint32_t eri : 1; /* Early Receive Interrupt */ + uint32_t ais : 1; /* Abnormal Interrupt Summary */ + uint32_t nis : 1; /* Normal Interrupt Summary */ + const uint32_t rs : 3; /* Received Process State */ + const uint32_t ts : 3; /* Transmit Process State */ + const uint32_t eb : 3; /* Error Bits */ + const uint32_t gli : 1; /* GMAC Line Interface Interrupt */ + const uint32_t gmi : 1; /* GMAC MMC Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t tti : 1; /* Timestamp Trigger Interrupt */ + const uint32_t glpii : 1; /* GMAC LPI Interrupt (for Channel 0) */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_STAT. */ +typedef volatile struct ALT_EMAC_DMA_STAT_s ALT_EMAC_DMA_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_STAT register from the beginning of the component. */ +#define ALT_EMAC_DMA_STAT_OFST 0x14 +/* The address of the ALT_EMAC_DMA_STAT register. */ +#define ALT_EMAC_DMA_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_STAT_OFST)) + +/* + * Register : Register 6 (Operation Mode Register) - Operation_Mode + * + * The Operation Mode register establishes the Transmit and Receive operating modes + * and commands. This register should be the last CSR to be written as part of the + * DMA initialization. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Start or Stop Receive + * [2] | RW | 0x0 | Operate on Second Frame + * [4:3] | RW | 0x0 | Receive Threshold Control + * [5] | ??? | 0x0 | *UNDEFINED* + * [6] | RW | 0x0 | Forward Undersized Good Frames + * [7] | RW | 0x0 | Forward Error Frames + * [8] | RW | 0x0 | Enable HW Flow Control + * [10:9] | RW | 0x0 | Threshold for Activating Flow Control (in half-duplex and full-duplex) + * [12:11] | RW | 0x0 | Threshold for Deactivating Flow Control (in half-duplex and full-duplex) + * [13] | RW | 0x0 | Start or Stop Transmission Command + * [16:14] | RW | 0x0 | Transmit Threshold Control + * [19:17] | ??? | 0x0 | *UNDEFINED* + * [20] | RW | 0x0 | Flush Transmit FIFO + * [21] | RW | 0x0 | Transmit Store and Forward + * [23:22] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | Disable Flushing of Received Frames + * [25] | RW | 0x0 | Receive Store and Forward + * [26] | RW | 0x0 | Disable Dropping of TCP/IP Checksum Error Frames + * [31:27] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start or Stop Receive - sr + * + * When this bit is set, the Receive process is placed in the Running state. The + * DMA attempts to acquire the descriptor from the Receive list and processes the + * incoming frames. The descriptor acquisition is attempted from the current + * position in the list, which is the address set by Register 3 (Receive Descriptor + * List Address Register) or the position retained when the Receive process was + * previously stopped. If the DMA does not own the descriptor, reception is + * suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) + * is set. The Start Receive command is effective only when the reception has + * stopped. If the command is issued before setting Register 3 (Receive Descriptor + * List Address Register), the DMA behavior is unpredictable. + * + * When this bit is cleared, the Rx DMA operation is stopped after the transfer of + * the current frame. The next descriptor position in the Receive list is saved and + * becomes the current position after the Receive process is restarted. The Stop + * Receive command is effective only when the Receive process is in either the + * Running (waiting for receive packet) or in the Suspended state. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------- + * ALT_EMAC_DMA_OP_MOD_SR_E_DISD | 0x0 | Rx DMA operation is stopped + * ALT_EMAC_DMA_OP_MOD_SR_E_END | 0x1 | Rx DMA operation is started + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR + * + * Rx DMA operation is stopped + */ +#define ALT_EMAC_DMA_OP_MOD_SR_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR + * + * Rx DMA operation is started + */ +#define ALT_EMAC_DMA_OP_MOD_SR_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field. */ +#define ALT_EMAC_DMA_OP_MOD_SR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field. */ +#define ALT_EMAC_DMA_OP_MOD_SR_MSB 1 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_SR register field. */ +#define ALT_EMAC_DMA_OP_MOD_SR_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_SR register field value. */ +#define ALT_EMAC_DMA_OP_MOD_SR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_SR register field value. */ +#define ALT_EMAC_DMA_OP_MOD_SR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_DMA_OP_MOD_SR register field. */ +#define ALT_EMAC_DMA_OP_MOD_SR_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_SR field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_SR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_DMA_OP_MOD_SR register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_SR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Operate on Second Frame - osf + * + * When this bit is set, it instructs the DMA to process the second frame of the + * Transmit data even before the status for the first frame is obtained. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------- + * ALT_EMAC_DMA_OP_MOD_OSF_E_DISD | 0x0 | DMA Does Not Process second frame + * ALT_EMAC_DMA_OP_MOD_OSF_E_END | 0x1 | DMA Processes second frame + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF + * + * DMA Does Not Process second frame + */ +#define ALT_EMAC_DMA_OP_MOD_OSF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF + * + * DMA Processes second frame + */ +#define ALT_EMAC_DMA_OP_MOD_OSF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_OSF_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_OSF_MSB 2 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_OSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_OSF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_OSF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_OSF_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_OSF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_OSF_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_DMA_OP_MOD_OSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_OSF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_OSF field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_OSF_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_DMA_OP_MOD_OSF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_OSF_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive Threshold Control - rtc + * + * These two bits control the threshold level of the MTL Receive FIFO. Transfer + * (request) to DMA starts when the frame size within the MTL Receive FIFO is + * larger than the threshold. In addition, full frames with length less than the + * threshold are transferred automatically. + * + * These bits are valid only when the RSF bit is zero, and are ignored when the RSF + * bit is set to 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------------- + * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64 | 0x0 | MTL Rcv Fifo threshold level 64 + * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32 | 0x1 | MTL Rcv Fifo threshold level 32 + * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96 | 0x2 | MTL Rcv Fifo threshold level 96 + * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128 | 0x3 | MTL Rcv Fifo threshold level 128 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC + * + * MTL Rcv Fifo threshold level 64 + */ +#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC + * + * MTL Rcv Fifo threshold level 32 + */ +#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32 0x1 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC + * + * MTL Rcv Fifo threshold level 96 + */ +#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96 0x2 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC + * + * MTL Rcv Fifo threshold level 128 + */ +#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field. */ +#define ALT_EMAC_DMA_OP_MOD_RTC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field. */ +#define ALT_EMAC_DMA_OP_MOD_RTC_MSB 4 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_RTC register field. */ +#define ALT_EMAC_DMA_OP_MOD_RTC_WIDTH 2 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_RTC register field value. */ +#define ALT_EMAC_DMA_OP_MOD_RTC_SET_MSK 0x00000018 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RTC register field value. */ +#define ALT_EMAC_DMA_OP_MOD_RTC_CLR_MSK 0xffffffe7 +/* The reset value of the ALT_EMAC_DMA_OP_MOD_RTC register field. */ +#define ALT_EMAC_DMA_OP_MOD_RTC_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_RTC field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_RTC_GET(value) (((value) & 0x00000018) >> 3) +/* Produces a ALT_EMAC_DMA_OP_MOD_RTC register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_RTC_SET(value) (((value) << 3) & 0x00000018) + +/* + * Field : Forward Undersized Good Frames - fuf + * + * When set, the Rx FIFO forwards Undersized frames (frames with no Error and + * length less than 64 bytes) including pad-bytes and CRC. + * + * When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame + * is already transferred because of the lower value of Receive Threshold, for + * example, RTC = 01. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------- + * ALT_EMAC_DMA_OP_MOD_FUF_E_DISD | 0x0 | Drops Frames less than 64Bytes + * ALT_EMAC_DMA_OP_MOD_FUF_E_END | 0x1 | Forward Frames with no errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF + * + * Drops Frames less than 64Bytes + */ +#define ALT_EMAC_DMA_OP_MOD_FUF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF + * + * Forward Frames with no errors + */ +#define ALT_EMAC_DMA_OP_MOD_FUF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FUF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FUF_MSB 6 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_FUF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FUF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_FUF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_FUF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FUF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_FUF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_DMA_OP_MOD_FUF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FUF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_FUF field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_FUF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_DMA_OP_MOD_FUF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_FUF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Forward Error Frames - fef + * + * When this bit is reset, the Rx FIFO drops frames with error status (CRC error, + * collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, + * if the start byte (write) pointer of a frame is already transferred to the read + * controller side (in Threshold mode), then the frame is not dropped. + * + * When the FEF bit is set, all frames except runt error frames are forwarded to + * the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial + * frame is written, then the frame is dropped irrespective of the FEF bit setting. + * However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial + * frame is written, then a partial frame may be forwarded to the DMA. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:-------------------------------- + * ALT_EMAC_DMA_OP_MOD_FEF_E_DISD | 0x0 | Drops Frames with error status + * ALT_EMAC_DMA_OP_MOD_FEF_E_END | 0x1 | Forward all Frames(except runt) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF + * + * Drops Frames with error status + */ +#define ALT_EMAC_DMA_OP_MOD_FEF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF + * + * Forward all Frames(except runt) + */ +#define ALT_EMAC_DMA_OP_MOD_FEF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FEF_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FEF_MSB 7 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_FEF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FEF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_FEF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_FEF_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FEF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_FEF_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_DMA_OP_MOD_FEF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FEF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_FEF field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_FEF_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_DMA_OP_MOD_FEF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_FEF_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Enable HW Flow Control - efc + * + * When this bit is set, the flow control signal operation based on the fill-level + * of Rx FIFO is enabled. When reset, the flow control operation is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:-------------------------------- + * ALT_EMAC_DMA_OP_MOD_EFC_E_DISD | 0x0 | Rx FIFO Fill Level Disabled + * ALT_EMAC_DMA_OP_MOD_EFC_E_END | 0x1 | Rx FIFO Fill Level Enabled Ctrl + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC + * + * Rx FIFO Fill Level Disabled + */ +#define ALT_EMAC_DMA_OP_MOD_EFC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC + * + * Rx FIFO Fill Level Enabled Ctrl + */ +#define ALT_EMAC_DMA_OP_MOD_EFC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field. */ +#define ALT_EMAC_DMA_OP_MOD_EFC_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field. */ +#define ALT_EMAC_DMA_OP_MOD_EFC_MSB 8 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_EFC register field. */ +#define ALT_EMAC_DMA_OP_MOD_EFC_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_EFC register field value. */ +#define ALT_EMAC_DMA_OP_MOD_EFC_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_EFC register field value. */ +#define ALT_EMAC_DMA_OP_MOD_EFC_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_DMA_OP_MOD_EFC register field. */ +#define ALT_EMAC_DMA_OP_MOD_EFC_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_EFC field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_EFC_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_DMA_OP_MOD_EFC register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_EFC_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Threshold for Activating Flow Control (in half-duplex and full-duplex) - rfa + * + * These bits control the threshold (Fill level of Rx FIFO) at which the flow + * control is activated. + * + * These values only apply to the Rx FIFO when the EFC bit is set high. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------- + * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K | 0x0 | Full minus 1 KB + * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K | 0x1 | Full minus 2 KB + * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K | 0x2 | Full minus 3 KB + * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K | 0x3 | Full minus 4 KB + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA + * + * Full minus 1 KB + */ +#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA + * + * Full minus 2 KB + */ +#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K 0x1 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA + * + * Full minus 3 KB + */ +#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K 0x2 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA + * + * Full minus 4 KB + */ +#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field. */ +#define ALT_EMAC_DMA_OP_MOD_RFA_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field. */ +#define ALT_EMAC_DMA_OP_MOD_RFA_MSB 10 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_RFA register field. */ +#define ALT_EMAC_DMA_OP_MOD_RFA_WIDTH 2 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_RFA register field value. */ +#define ALT_EMAC_DMA_OP_MOD_RFA_SET_MSK 0x00000600 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFA register field value. */ +#define ALT_EMAC_DMA_OP_MOD_RFA_CLR_MSK 0xfffff9ff +/* The reset value of the ALT_EMAC_DMA_OP_MOD_RFA register field. */ +#define ALT_EMAC_DMA_OP_MOD_RFA_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_RFA field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_RFA_GET(value) (((value) & 0x00000600) >> 9) +/* Produces a ALT_EMAC_DMA_OP_MOD_RFA register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_RFA_SET(value) (((value) << 9) & 0x00000600) + +/* + * Field : Threshold for Deactivating Flow Control (in half-duplex and full-duplex) - rfd + * + * These bits control the threshold (Fill-level of Rx FIFO) at which the flow + * control is de-asserted after activation. + * + * The de-assertion is effective only after flow control is asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------- + * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K | 0x0 | Full minus 1 KB + * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K | 0x1 | Full minus 2 KB + * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K | 0x2 | Full minus 3 KB + * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K | 0x3 | Full minus 4 KB + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD + * + * Full minus 1 KB + */ +#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD + * + * Full minus 2 KB + */ +#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K 0x1 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD + * + * Full minus 3 KB + */ +#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K 0x2 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD + * + * Full minus 4 KB + */ +#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field. */ +#define ALT_EMAC_DMA_OP_MOD_RFD_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field. */ +#define ALT_EMAC_DMA_OP_MOD_RFD_MSB 12 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_RFD register field. */ +#define ALT_EMAC_DMA_OP_MOD_RFD_WIDTH 2 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_RFD register field value. */ +#define ALT_EMAC_DMA_OP_MOD_RFD_SET_MSK 0x00001800 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFD register field value. */ +#define ALT_EMAC_DMA_OP_MOD_RFD_CLR_MSK 0xffffe7ff +/* The reset value of the ALT_EMAC_DMA_OP_MOD_RFD register field. */ +#define ALT_EMAC_DMA_OP_MOD_RFD_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_RFD field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_RFD_GET(value) (((value) & 0x00001800) >> 11) +/* Produces a ALT_EMAC_DMA_OP_MOD_RFD register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_RFD_SET(value) (((value) << 11) & 0x00001800) + +/* + * Field : Start or Stop Transmission Command - st + * + * When this bit is set, transmission is placed in the Running state, and the DMA + * checks the Transmit List at the current position for a frame to be transmitted. + * Descriptor acquisition is attempted either from the current position in the + * list, which is the Transmit List Base Address set by Register 4 (Transmit + * Descriptor List Address Register), or from the position retained when + * transmission was stopped previously. If the DMA does not own the current + * descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer + * Unavailable) of Register 5 (Status Register) is set. The Start Transmission + * command is effective only when transmission is stopped. If the command is issued + * before setting Register 4 (Transmit Descriptor List Address Register), then the + * DMA behavior is unpredictable. + * + * When this bit is reset, the transmission process is placed in the Stopped state + * after completing the transmission of the current frame. The Next Descriptor + * position in the Transmit List is saved, and it becomes the current position when + * transmission is restarted. To change the list address, you need to program + * Register 4 (Transmit Descriptor List Address Register) with a new value when + * this bit is reset. The new value is considered when this bit is set again. The + * stop transmission command is effective only when the transmission of the current + * frame is complete or the transmission is in the Suspended state. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:--------------------------- + * ALT_EMAC_DMA_OP_MOD_ST_E_DISD | 0x0 | Transmission Stopped State + * ALT_EMAC_DMA_OP_MOD_ST_E_END | 0x1 | Transmission in Run State + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST + * + * Transmission Stopped State + */ +#define ALT_EMAC_DMA_OP_MOD_ST_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST + * + * Transmission in Run State + */ +#define ALT_EMAC_DMA_OP_MOD_ST_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field. */ +#define ALT_EMAC_DMA_OP_MOD_ST_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field. */ +#define ALT_EMAC_DMA_OP_MOD_ST_MSB 13 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_ST register field. */ +#define ALT_EMAC_DMA_OP_MOD_ST_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_ST register field value. */ +#define ALT_EMAC_DMA_OP_MOD_ST_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_ST register field value. */ +#define ALT_EMAC_DMA_OP_MOD_ST_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_DMA_OP_MOD_ST register field. */ +#define ALT_EMAC_DMA_OP_MOD_ST_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_ST field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_ST_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_DMA_OP_MOD_ST register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_ST_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Transmit Threshold Control - ttc + * + * These bits control the threshold level of the MTL Transmit FIFO. Transmission + * starts when the frame size within the MTL Transmit FIFO is larger than the + * threshold. In addition, full frames with a length less than the threshold are + * also transmitted. These bits are used only when Bit 21 (TSF) is reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------------------- + * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64 | 0x0 | MTL Transmit FIFO Threshold 64 + * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128 | 0x1 | MTL Transmit FIFO Threshold 128 + * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192 | 0x2 | MTL Transmit FIFO Threshold 192 + * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256 | 0x3 | MTL Transmit FIFO Threshold 256 + * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40 | 0x4 | MTL Transmit FIFO Threshold 40 + * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32 | 0x5 | MTL Transmit FIFO Threshold 32 + * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24 | 0x6 | MTL Transmit FIFO Threshold 24 + * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16 | 0x7 | MTL Transmit FIFO Threshold 16 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC + * + * MTL Transmit FIFO Threshold 64 + */ +#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC + * + * MTL Transmit FIFO Threshold 128 + */ +#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128 0x1 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC + * + * MTL Transmit FIFO Threshold 192 + */ +#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192 0x2 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC + * + * MTL Transmit FIFO Threshold 256 + */ +#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256 0x3 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC + * + * MTL Transmit FIFO Threshold 40 + */ +#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40 0x4 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC + * + * MTL Transmit FIFO Threshold 32 + */ +#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32 0x5 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC + * + * MTL Transmit FIFO Threshold 24 + */ +#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24 0x6 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC + * + * MTL Transmit FIFO Threshold 16 + */ +#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field. */ +#define ALT_EMAC_DMA_OP_MOD_TTC_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field. */ +#define ALT_EMAC_DMA_OP_MOD_TTC_MSB 16 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_TTC register field. */ +#define ALT_EMAC_DMA_OP_MOD_TTC_WIDTH 3 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_TTC register field value. */ +#define ALT_EMAC_DMA_OP_MOD_TTC_SET_MSK 0x0001c000 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_TTC register field value. */ +#define ALT_EMAC_DMA_OP_MOD_TTC_CLR_MSK 0xfffe3fff +/* The reset value of the ALT_EMAC_DMA_OP_MOD_TTC register field. */ +#define ALT_EMAC_DMA_OP_MOD_TTC_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_TTC field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_TTC_GET(value) (((value) & 0x0001c000) >> 14) +/* Produces a ALT_EMAC_DMA_OP_MOD_TTC register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_TTC_SET(value) (((value) << 14) & 0x0001c000) + +/* + * Field : Flush Transmit FIFO - ftf + * + * When this bit is set, the transmit FIFO controller logic is reset to its default + * values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared + * internally when the flushing operation is completed. The Operation Mode register + * should not be written to until this bit is cleared. The data which is already + * accepted by the MAC transmitter is not flushed. It is scheduled for transmission + * and results in underflow and runt frame transmission. + * + * Note: The flush operation is complete only when the Tx FIFO is emptied of its + * contents and all the pending Transmit Status of the transmitted frames are + * accepted by the host. To complete this flush operation, the PHY transmit clock + * is required to be active. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------- + * ALT_EMAC_DMA_OP_MOD_FTF_E_DISD | 0x0 | Tx FIFO Data not Flushed + * ALT_EMAC_DMA_OP_MOD_FTF_E_END | 0x1 | TX FIFO Data Flushed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF + * + * Tx FIFO Data not Flushed + */ +#define ALT_EMAC_DMA_OP_MOD_FTF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF + * + * TX FIFO Data Flushed + */ +#define ALT_EMAC_DMA_OP_MOD_FTF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FTF_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FTF_MSB 20 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_FTF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FTF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_FTF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_FTF_SET_MSK 0x00100000 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FTF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_FTF_CLR_MSK 0xffefffff +/* The reset value of the ALT_EMAC_DMA_OP_MOD_FTF register field. */ +#define ALT_EMAC_DMA_OP_MOD_FTF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_FTF field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_FTF_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_EMAC_DMA_OP_MOD_FTF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_FTF_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Transmit Store and Forward - tsf + * + * When this bit is set, transmission starts when a full frame resides in the MTL + * Transmit FIFO. When this bit is set, the TTC values specified in Bits[16:14] are + * ignored. This bit should be changed only when the transmission is stopped. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------- + * ALT_EMAC_DMA_OP_MOD_TSF_E_DISD | 0x0 | Tx Does not Start with Full Frame + * ALT_EMAC_DMA_OP_MOD_TSF_E_END | 0x1 | Tx Start with Full Frame + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF + * + * Tx Does not Start with Full Frame + */ +#define ALT_EMAC_DMA_OP_MOD_TSF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF + * + * Tx Start with Full Frame + */ +#define ALT_EMAC_DMA_OP_MOD_TSF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_TSF_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_TSF_MSB 21 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_TSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_TSF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_TSF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_TSF_SET_MSK 0x00200000 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_TSF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_TSF_CLR_MSK 0xffdfffff +/* The reset value of the ALT_EMAC_DMA_OP_MOD_TSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_TSF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_TSF field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_TSF_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_EMAC_DMA_OP_MOD_TSF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_TSF_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Disable Flushing of Received Frames - dff + * + * When this bit is set, the Rx DMA does not flush any frames because of the + * unavailability of receive descriptors or buffers as it does normally when this + * bit is reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------- + * ALT_EMAC_DMA_OP_MOD_DFF_E_DISD | 0x0 | Rx DMA Flushed + * ALT_EMAC_DMA_OP_MOD_DFF_E_END | 0x1 | Rx DMA not Flushed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF + * + * Rx DMA Flushed + */ +#define ALT_EMAC_DMA_OP_MOD_DFF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF + * + * Rx DMA not Flushed + */ +#define ALT_EMAC_DMA_OP_MOD_DFF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field. */ +#define ALT_EMAC_DMA_OP_MOD_DFF_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field. */ +#define ALT_EMAC_DMA_OP_MOD_DFF_MSB 24 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_DFF register field. */ +#define ALT_EMAC_DMA_OP_MOD_DFF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_DFF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_DFF_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_DFF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_DFF_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_DMA_OP_MOD_DFF register field. */ +#define ALT_EMAC_DMA_OP_MOD_DFF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_DFF field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_DFF_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_DMA_OP_MOD_DFF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_DFF_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Receive Store and Forward - rsf + * + * When this bit is set, the MTL reads a frame from the Rx FIFO only after the + * complete frame has been written to it, ignoring the RTC bits. When this bit is + * reset, the Rx FIFO operates in the cut-through mode, subject to the threshold + * specified by the RTC bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:--------------------------------------- + * ALT_EMAC_DMA_OP_MOD_RSF_E_DISD | 0x0 | Rx Fifo cut-through mode + * ALT_EMAC_DMA_OP_MOD_RSF_E_END | 0x1 | Read Rx FIFO only after complete frame + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF + * + * Rx Fifo cut-through mode + */ +#define ALT_EMAC_DMA_OP_MOD_RSF_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF + * + * Read Rx FIFO only after complete frame + */ +#define ALT_EMAC_DMA_OP_MOD_RSF_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_RSF_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_RSF_MSB 25 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_RSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_RSF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_RSF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_RSF_SET_MSK 0x02000000 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSF register field value. */ +#define ALT_EMAC_DMA_OP_MOD_RSF_CLR_MSK 0xfdffffff +/* The reset value of the ALT_EMAC_DMA_OP_MOD_RSF register field. */ +#define ALT_EMAC_DMA_OP_MOD_RSF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_RSF field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_RSF_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_EMAC_DMA_OP_MOD_RSF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_RSF_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Disable Dropping of TCP/IP Checksum Error Frames - dt + * + * When this bit is set, the MAC does not drop the frames which only have errors + * detected by the Receive Checksum Offload engine. Such frames do not have any + * errors (including FCS error) in the Ethernet frame received by the MAC but have + * errors only in the encapsulated payload. When this bit is reset, all error + * frames are dropped if the FEF bit is reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------ + * ALT_EMAC_DMA_OP_MOD_DT_E_DISD | 0x0 | All Error Frames Dropped + * ALT_EMAC_DMA_OP_MOD_DT_E_END | 0x1 | MAC does not drop frame with errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT + * + * All Error Frames Dropped + */ +#define ALT_EMAC_DMA_OP_MOD_DT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT + * + * MAC does not drop frame with errors + */ +#define ALT_EMAC_DMA_OP_MOD_DT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field. */ +#define ALT_EMAC_DMA_OP_MOD_DT_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field. */ +#define ALT_EMAC_DMA_OP_MOD_DT_MSB 26 +/* The width in bits of the ALT_EMAC_DMA_OP_MOD_DT register field. */ +#define ALT_EMAC_DMA_OP_MOD_DT_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_OP_MOD_DT register field value. */ +#define ALT_EMAC_DMA_OP_MOD_DT_SET_MSK 0x04000000 +/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_DT register field value. */ +#define ALT_EMAC_DMA_OP_MOD_DT_CLR_MSK 0xfbffffff +/* The reset value of the ALT_EMAC_DMA_OP_MOD_DT register field. */ +#define ALT_EMAC_DMA_OP_MOD_DT_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_OP_MOD_DT field value from a register. */ +#define ALT_EMAC_DMA_OP_MOD_DT_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_EMAC_DMA_OP_MOD_DT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_OP_MOD_DT_SET(value) (((value) << 26) & 0x04000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_OP_MOD. + */ +struct ALT_EMAC_DMA_OP_MOD_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t sr : 1; /* Start or Stop Receive */ + uint32_t osf : 1; /* Operate on Second Frame */ + uint32_t rtc : 2; /* Receive Threshold Control */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t fuf : 1; /* Forward Undersized Good Frames */ + uint32_t fef : 1; /* Forward Error Frames */ + uint32_t efc : 1; /* Enable HW Flow Control */ + uint32_t rfa : 2; /* Threshold for Activating Flow Control (in half-duplex and full-duplex) */ + uint32_t rfd : 2; /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex) */ + uint32_t st : 1; /* Start or Stop Transmission Command */ + uint32_t ttc : 3; /* Transmit Threshold Control */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t ftf : 1; /* Flush Transmit FIFO */ + uint32_t tsf : 1; /* Transmit Store and Forward */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t dff : 1; /* Disable Flushing of Received Frames */ + uint32_t rsf : 1; /* Receive Store and Forward */ + uint32_t dt : 1; /* Disable Dropping of TCP/IP Checksum Error Frames */ + uint32_t : 5; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_OP_MOD. */ +typedef volatile struct ALT_EMAC_DMA_OP_MOD_s ALT_EMAC_DMA_OP_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_OP_MOD register from the beginning of the component. */ +#define ALT_EMAC_DMA_OP_MOD_OFST 0x18 +/* The address of the ALT_EMAC_DMA_OP_MOD register. */ +#define ALT_EMAC_DMA_OP_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_OP_MOD_OFST)) + +/* + * Register : Register 7 (Interrupt Enable Register) - Interrupt_Enable + * + * The Interrupt Enable register enables the interrupts reported by Register 5 + * (Status Register). Setting a bit to 1'b1 enables a corresponding interrupt. + * After a hardware or software reset, all interrupts are disabled. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transmit Interrupt Enable + * [1] | RW | 0x0 | Transmit Stopped Enable + * [2] | RW | 0x0 | Transmit Buffer Unvailable Enable + * [3] | RW | 0x0 | Transmit Jabber Timeout Enable + * [4] | RW | 0x0 | Overflow Interrupt Enable + * [5] | RW | 0x0 | Underflow Interrupt Enable + * [6] | RW | 0x0 | Receive Interrupt Enable + * [7] | RW | 0x0 | Receive Buffer Unavailable Enable + * [8] | RW | 0x0 | Receive Stopped Enable + * [9] | RW | 0x0 | Receive Watchdog Timeout Enable + * [10] | RW | 0x0 | Early Transmit Interrupt Enable + * [12:11] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Fatal Bus Error Enable + * [14] | RW | 0x0 | Early Receive Interrupt Enable + * [15] | RW | 0x0 | Abnormal Interrupt Summary Enable + * [16] | RW | 0x0 | Normal Interrupt Summary Enable + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit Interrupt Enable - tie + * + * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit + * Interrupt is enabled. When this bit is reset, the Transmit Interrupt is + * disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------- + * ALT_EMAC_DMA_INT_EN_TIE_E_DISD | 0x0 | Transmit Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_TIE_E_END | 0x1 | Transmit Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TIE + * + * Transmit Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_TIE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TIE + * + * Transmit Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_TIE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TIE register field. */ +#define ALT_EMAC_DMA_INT_EN_TIE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TIE register field. */ +#define ALT_EMAC_DMA_INT_EN_TIE_MSB 0 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_TIE register field. */ +#define ALT_EMAC_DMA_INT_EN_TIE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_TIE register field value. */ +#define ALT_EMAC_DMA_INT_EN_TIE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_TIE register field value. */ +#define ALT_EMAC_DMA_INT_EN_TIE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_DMA_INT_EN_TIE register field. */ +#define ALT_EMAC_DMA_INT_EN_TIE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_TIE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_TIE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_DMA_INT_EN_TIE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_TIE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit Stopped Enable - tse + * + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the + * Transmission Stopped Interrupt is enabled. When this bit is reset, the + * Transmission Stopped Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------ + * ALT_EMAC_DMA_INT_EN_TSE_E_DISD | 0x0 | Transmit Stopped Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_TSE_E_END | 0x1 | Transmit Stopped Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TSE + * + * Transmit Stopped Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_TSE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TSE + * + * Transmit Stopped Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_TSE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TSE register field. */ +#define ALT_EMAC_DMA_INT_EN_TSE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TSE register field. */ +#define ALT_EMAC_DMA_INT_EN_TSE_MSB 1 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_TSE register field. */ +#define ALT_EMAC_DMA_INT_EN_TSE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_TSE register field value. */ +#define ALT_EMAC_DMA_INT_EN_TSE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_TSE register field value. */ +#define ALT_EMAC_DMA_INT_EN_TSE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_DMA_INT_EN_TSE register field. */ +#define ALT_EMAC_DMA_INT_EN_TSE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_TSE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_TSE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_DMA_INT_EN_TSE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_TSE_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Transmit Buffer Unvailable Enable - tue + * + * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit + * Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit + * Buffer Unavailable Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------------------------------- + * ALT_EMAC_DMA_INT_EN_TUE_E_DISD | 0x0 | Transmit Buffer Unavailable Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_TUE_E_END | 0x1 | Transmit Buffer Unavailable Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TUE + * + * Transmit Buffer Unavailable Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_TUE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TUE + * + * Transmit Buffer Unavailable Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_TUE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TUE register field. */ +#define ALT_EMAC_DMA_INT_EN_TUE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TUE register field. */ +#define ALT_EMAC_DMA_INT_EN_TUE_MSB 2 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_TUE register field. */ +#define ALT_EMAC_DMA_INT_EN_TUE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_TUE register field value. */ +#define ALT_EMAC_DMA_INT_EN_TUE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_TUE register field value. */ +#define ALT_EMAC_DMA_INT_EN_TUE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_DMA_INT_EN_TUE register field. */ +#define ALT_EMAC_DMA_INT_EN_TUE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_TUE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_TUE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_DMA_INT_EN_TUE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_TUE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Transmit Jabber Timeout Enable - tje + * + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the + * Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the + * Transmit Jabber Timeout Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------------- + * ALT_EMAC_DMA_INT_EN_TJE_E_DISD | 0x0 | Transmit Jabber Timeout Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_TJE_E_END | 0x1 | Transmit Jabber Timeout Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TJE + * + * Transmit Jabber Timeout Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_TJE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TJE + * + * Transmit Jabber Timeout Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_TJE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TJE register field. */ +#define ALT_EMAC_DMA_INT_EN_TJE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TJE register field. */ +#define ALT_EMAC_DMA_INT_EN_TJE_MSB 3 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_TJE register field. */ +#define ALT_EMAC_DMA_INT_EN_TJE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_TJE register field value. */ +#define ALT_EMAC_DMA_INT_EN_TJE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_TJE register field value. */ +#define ALT_EMAC_DMA_INT_EN_TJE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_DMA_INT_EN_TJE register field. */ +#define ALT_EMAC_DMA_INT_EN_TJE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_TJE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_TJE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_DMA_INT_EN_TJE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_TJE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Overflow Interrupt Enable - ove + * + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the + * Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow + * Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------- + * ALT_EMAC_DMA_INT_EN_OVE_E_DISD | 0x0 | Transmit Overflow Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_OVE_E_END | 0x1 | Transmit Overflow Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_OVE + * + * Transmit Overflow Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_OVE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_OVE + * + * Transmit Overflow Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_OVE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_OVE register field. */ +#define ALT_EMAC_DMA_INT_EN_OVE_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_OVE register field. */ +#define ALT_EMAC_DMA_INT_EN_OVE_MSB 4 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_OVE register field. */ +#define ALT_EMAC_DMA_INT_EN_OVE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_OVE register field value. */ +#define ALT_EMAC_DMA_INT_EN_OVE_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_OVE register field value. */ +#define ALT_EMAC_DMA_INT_EN_OVE_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_DMA_INT_EN_OVE register field. */ +#define ALT_EMAC_DMA_INT_EN_OVE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_OVE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_OVE_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_DMA_INT_EN_OVE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_OVE_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Underflow Interrupt Enable - une + * + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the + * Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow + * Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------------- + * ALT_EMAC_DMA_INT_EN_UNE_E_DISD | 0x0 | Underflow Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_UNE_E_END | 0x1 | Underflow Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_UNE + * + * Underflow Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_UNE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_UNE + * + * Underflow Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_UNE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_UNE register field. */ +#define ALT_EMAC_DMA_INT_EN_UNE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_UNE register field. */ +#define ALT_EMAC_DMA_INT_EN_UNE_MSB 5 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_UNE register field. */ +#define ALT_EMAC_DMA_INT_EN_UNE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_UNE register field value. */ +#define ALT_EMAC_DMA_INT_EN_UNE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_UNE register field value. */ +#define ALT_EMAC_DMA_INT_EN_UNE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_DMA_INT_EN_UNE register field. */ +#define ALT_EMAC_DMA_INT_EN_UNE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_UNE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_UNE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_DMA_INT_EN_UNE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_UNE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Receive Interrupt Enable - rie + * + * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive + * Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:--------------------------- + * ALT_EMAC_DMA_INT_EN_RIE_E_DISD | 0x0 | Receive Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_RIE_E_END | 0x1 | Receive Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RIE + * + * Receive Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_RIE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RIE + * + * Receive Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_RIE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RIE register field. */ +#define ALT_EMAC_DMA_INT_EN_RIE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RIE register field. */ +#define ALT_EMAC_DMA_INT_EN_RIE_MSB 6 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_RIE register field. */ +#define ALT_EMAC_DMA_INT_EN_RIE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_RIE register field value. */ +#define ALT_EMAC_DMA_INT_EN_RIE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_RIE register field value. */ +#define ALT_EMAC_DMA_INT_EN_RIE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_DMA_INT_EN_RIE register field. */ +#define ALT_EMAC_DMA_INT_EN_RIE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_RIE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_RIE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_DMA_INT_EN_RIE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_RIE_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Buffer Unavailable Enable - rue + * + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the + * Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the + * Receive Buffer Unavailable Interrupt is disabled. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RUE register field. */ +#define ALT_EMAC_DMA_INT_EN_RUE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RUE register field. */ +#define ALT_EMAC_DMA_INT_EN_RUE_MSB 7 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_RUE register field. */ +#define ALT_EMAC_DMA_INT_EN_RUE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_RUE register field value. */ +#define ALT_EMAC_DMA_INT_EN_RUE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_RUE register field value. */ +#define ALT_EMAC_DMA_INT_EN_RUE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_EMAC_DMA_INT_EN_RUE register field. */ +#define ALT_EMAC_DMA_INT_EN_RUE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_RUE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_RUE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_EMAC_DMA_INT_EN_RUE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_RUE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Receive Stopped Enable - rse + * + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the + * Receive Stopped Interrupt is enabled. When this bit is reset, the Receive + * Stopped Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------------------- + * ALT_EMAC_DMA_INT_EN_RSE_E_DISD | 0x0 | Receive Stopped Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_RSE_E_END | 0x1 | Receive Stopped Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RSE + * + * Receive Stopped Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_RSE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RSE + * + * Receive Stopped Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_RSE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RSE register field. */ +#define ALT_EMAC_DMA_INT_EN_RSE_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RSE register field. */ +#define ALT_EMAC_DMA_INT_EN_RSE_MSB 8 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_RSE register field. */ +#define ALT_EMAC_DMA_INT_EN_RSE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_RSE register field value. */ +#define ALT_EMAC_DMA_INT_EN_RSE_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_RSE register field value. */ +#define ALT_EMAC_DMA_INT_EN_RSE_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_DMA_INT_EN_RSE register field. */ +#define ALT_EMAC_DMA_INT_EN_RSE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_RSE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_RSE_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_DMA_INT_EN_RSE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_RSE_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Receive Watchdog Timeout Enable - rwe + * + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the + * Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the + * Receive Watchdog Timeout Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:-------------------------------------------- + * ALT_EMAC_DMA_INT_EN_RWE_E_DISD | 0x0 | Receive Watchdog Timeout Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_RWE_E_END | 0x1 | Receive Watchdog Timeout Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RWE + * + * Receive Watchdog Timeout Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_RWE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RWE + * + * Receive Watchdog Timeout Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_RWE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RWE register field. */ +#define ALT_EMAC_DMA_INT_EN_RWE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RWE register field. */ +#define ALT_EMAC_DMA_INT_EN_RWE_MSB 9 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_RWE register field. */ +#define ALT_EMAC_DMA_INT_EN_RWE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_RWE register field value. */ +#define ALT_EMAC_DMA_INT_EN_RWE_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_RWE register field value. */ +#define ALT_EMAC_DMA_INT_EN_RWE_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_DMA_INT_EN_RWE register field. */ +#define ALT_EMAC_DMA_INT_EN_RWE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_RWE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_RWE_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_DMA_INT_EN_RWE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_RWE_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Early Transmit Interrupt Enable - ete + * + * When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the + * Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit + * Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------- + * ALT_EMAC_DMA_INT_EN_ETE_E_DISD | 0x0 | Early Transmit Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_ETE_E_END | 0x1 | Early Transmit Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ETE + * + * Early Transmit Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_ETE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ETE + * + * Early Transmit Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_ETE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_ETE register field. */ +#define ALT_EMAC_DMA_INT_EN_ETE_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_ETE register field. */ +#define ALT_EMAC_DMA_INT_EN_ETE_MSB 10 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_ETE register field. */ +#define ALT_EMAC_DMA_INT_EN_ETE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_ETE register field value. */ +#define ALT_EMAC_DMA_INT_EN_ETE_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_ETE register field value. */ +#define ALT_EMAC_DMA_INT_EN_ETE_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_DMA_INT_EN_ETE register field. */ +#define ALT_EMAC_DMA_INT_EN_ETE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_ETE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_ETE_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_DMA_INT_EN_ETE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_ETE_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Fatal Bus Error Enable - fbe + * + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal + * Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error + * Enable Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------------------- + * ALT_EMAC_DMA_INT_EN_FBE_E_DISD | 0x0 | Fatal Bus Error Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_FBE_E_END | 0x1 | Fatal Bus Error Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_FBE + * + * Fatal Bus Error Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_FBE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_FBE + * + * Fatal Bus Error Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_FBE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_FBE register field. */ +#define ALT_EMAC_DMA_INT_EN_FBE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_FBE register field. */ +#define ALT_EMAC_DMA_INT_EN_FBE_MSB 13 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_FBE register field. */ +#define ALT_EMAC_DMA_INT_EN_FBE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_FBE register field value. */ +#define ALT_EMAC_DMA_INT_EN_FBE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_FBE register field value. */ +#define ALT_EMAC_DMA_INT_EN_FBE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_DMA_INT_EN_FBE register field. */ +#define ALT_EMAC_DMA_INT_EN_FBE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_FBE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_FBE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_DMA_INT_EN_FBE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_FBE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Early Receive Interrupt Enable - ere + * + * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early + * Receive Interrupt is enabled. When this bit is reset, the Early Receive + * Interrupt is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:--------------------------------- + * ALT_EMAC_DMA_INT_EN_ERE_E_DISD | 0x0 | Early Receive Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_ERE_E_END | 0x1 | Early Receive Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ERE + * + * Early Receive Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_ERE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ERE + * + * Early Receive Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_ERE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_ERE register field. */ +#define ALT_EMAC_DMA_INT_EN_ERE_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_ERE register field. */ +#define ALT_EMAC_DMA_INT_EN_ERE_MSB 14 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_ERE register field. */ +#define ALT_EMAC_DMA_INT_EN_ERE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_ERE register field value. */ +#define ALT_EMAC_DMA_INT_EN_ERE_SET_MSK 0x00004000 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_ERE register field value. */ +#define ALT_EMAC_DMA_INT_EN_ERE_CLR_MSK 0xffffbfff +/* The reset value of the ALT_EMAC_DMA_INT_EN_ERE register field. */ +#define ALT_EMAC_DMA_INT_EN_ERE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_ERE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_ERE_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_EMAC_DMA_INT_EN_ERE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_ERE_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Abnormal Interrupt Summary Enable - aie + * + * When this bit is set, abnormal interrupt summary is enabled. When this bit is + * reset, the abnormal interrupt summary is disabled. This bit enables the + * following interrupts in Register 5 (Status Register): + * + * * Register 5[1]: Transmit Process Stopped + * + * * Register 5[3]: Transmit Jabber Timeout + * + * * Register 5[4]: Receive Overflow + * + * * Register 5[5]: Transmit Underflow + * + * * Register 5[7]: Receive Buffer Unavailable + * + * * Register 5[8]: Receive Process Stopped + * + * * Register 5[9]: Receive Watchdog Timeout + * + * * Register 5[10]: Early Transmit Interrupt + * + * * Register 5[13]: Fatal Bus Error + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------------------- + * ALT_EMAC_DMA_INT_EN_AIE_E_DISD | 0x0 | Abnormal Interrupt Summary Interrupt Disabled + * ALT_EMAC_DMA_INT_EN_AIE_E_END | 0x1 | Abnormal Interrupt Summary Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_AIE + * + * Abnormal Interrupt Summary Interrupt Disabled + */ +#define ALT_EMAC_DMA_INT_EN_AIE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_AIE + * + * Abnormal Interrupt Summary Interrupt Enabled + */ +#define ALT_EMAC_DMA_INT_EN_AIE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_AIE register field. */ +#define ALT_EMAC_DMA_INT_EN_AIE_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_AIE register field. */ +#define ALT_EMAC_DMA_INT_EN_AIE_MSB 15 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_AIE register field. */ +#define ALT_EMAC_DMA_INT_EN_AIE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_AIE register field value. */ +#define ALT_EMAC_DMA_INT_EN_AIE_SET_MSK 0x00008000 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_AIE register field value. */ +#define ALT_EMAC_DMA_INT_EN_AIE_CLR_MSK 0xffff7fff +/* The reset value of the ALT_EMAC_DMA_INT_EN_AIE register field. */ +#define ALT_EMAC_DMA_INT_EN_AIE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_AIE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_AIE_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_EMAC_DMA_INT_EN_AIE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_AIE_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Normal Interrupt Summary Enable - nie + * + * When this bit is set, normal interrupt summary is enabled. When this bit is + * reset, normal interrupt summary is disabled. This bit enables the following + * interrupts in Register 5 (Status Register): + * + * * Register 5[0]: Transmit Interrupt + * + * * Register 5[2]: Transmit Buffer Unavailable + * + * * Register 5[6]: Receive Interrupt + * + * * Register 5[14]: Early Receive Interrupt + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------- + * ALT_EMAC_DMA_INT_EN_NIE_E_DISD | 0x0 | Normal Interrupt Summary Disabled + * ALT_EMAC_DMA_INT_EN_NIE_E_END | 0x1 | Normal Interrupt Summary Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_NIE + * + * Normal Interrupt Summary Disabled + */ +#define ALT_EMAC_DMA_INT_EN_NIE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_INT_EN_NIE + * + * Normal Interrupt Summary Enabled + */ +#define ALT_EMAC_DMA_INT_EN_NIE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_NIE register field. */ +#define ALT_EMAC_DMA_INT_EN_NIE_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_NIE register field. */ +#define ALT_EMAC_DMA_INT_EN_NIE_MSB 16 +/* The width in bits of the ALT_EMAC_DMA_INT_EN_NIE register field. */ +#define ALT_EMAC_DMA_INT_EN_NIE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_INT_EN_NIE register field value. */ +#define ALT_EMAC_DMA_INT_EN_NIE_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_DMA_INT_EN_NIE register field value. */ +#define ALT_EMAC_DMA_INT_EN_NIE_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_DMA_INT_EN_NIE register field. */ +#define ALT_EMAC_DMA_INT_EN_NIE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_INT_EN_NIE field value from a register. */ +#define ALT_EMAC_DMA_INT_EN_NIE_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_DMA_INT_EN_NIE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_INT_EN_NIE_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_INT_EN. + */ +struct ALT_EMAC_DMA_INT_EN_s +{ + uint32_t tie : 1; /* Transmit Interrupt Enable */ + uint32_t tse : 1; /* Transmit Stopped Enable */ + uint32_t tue : 1; /* Transmit Buffer Unvailable Enable */ + uint32_t tje : 1; /* Transmit Jabber Timeout Enable */ + uint32_t ove : 1; /* Overflow Interrupt Enable */ + uint32_t une : 1; /* Underflow Interrupt Enable */ + uint32_t rie : 1; /* Receive Interrupt Enable */ + uint32_t rue : 1; /* Receive Buffer Unavailable Enable */ + uint32_t rse : 1; /* Receive Stopped Enable */ + uint32_t rwe : 1; /* Receive Watchdog Timeout Enable */ + uint32_t ete : 1; /* Early Transmit Interrupt Enable */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t fbe : 1; /* Fatal Bus Error Enable */ + uint32_t ere : 1; /* Early Receive Interrupt Enable */ + uint32_t aie : 1; /* Abnormal Interrupt Summary Enable */ + uint32_t nie : 1; /* Normal Interrupt Summary Enable */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_INT_EN. */ +typedef volatile struct ALT_EMAC_DMA_INT_EN_s ALT_EMAC_DMA_INT_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_INT_EN register from the beginning of the component. */ +#define ALT_EMAC_DMA_INT_EN_OFST 0x1c +/* The address of the ALT_EMAC_DMA_INT_EN register. */ +#define ALT_EMAC_DMA_INT_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_INT_EN_OFST)) + +/* + * Register : Register 8 (Missed Frame and Buffer Overflow Counter Register) - Missed_Frame_And_Buffer_Overflow_Counter + * + * The DMA maintains two counters to track the number of frames missed during + * reception. This register reports the current value of the counter. The counter + * is used for diagnostic purposes. Bits[15:0] indicate missed frames because of + * the host buffer being unavailable. Bits[27:17] indicate missed frames because of + * buffer overflow conditions (MTL and MAC) and runt frames (good frames of less + * than 64 bytes) dropped by the MTL. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------- + * [15:0] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT + * [16] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF + * [27:17] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT + * [28] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : misfrmcnt + * + * This field indicates the number of frames missed by the controller because of + * the Host Receive Buffer being unavailable. This counter is incremented each time + * the DMA discards an incoming frame. The counter is cleared when this register is + * read with mci_be_i[0] at 1'b1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_MSB 15 +/* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_WIDTH 16 +/* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT field value from a register. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : miscntovf + * + * Overflow bit for Missed Frame Counter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_MSB 16 +/* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF field value from a register. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : ovffrmcnt + * + * This field indicates the number of frames missed by the application. This + * counter is incremented each time the MTL asserts the sideband signal + * mtl_rxoverflow_o. The counter is cleared when this register is read with + * mci_be_i[2] at 1'b1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_MSB 27 +/* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_WIDTH 11 +/* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET_MSK 0x0ffe0000 +/* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_CLR_MSK 0xf001ffff +/* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT field value from a register. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_GET(value) (((value) & 0x0ffe0000) >> 17) +/* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET(value) (((value) << 17) & 0x0ffe0000) + +/* + * Field : ovfcntovf + * + * Overflow bit for FIFO Overflow Counter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_MSB 28 +/* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET_MSK 0x10000000 +/* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_CLR_MSK 0xefffffff +/* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF field value from a register. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET(value) (((value) << 28) & 0x10000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR. + */ +struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s +{ + const uint32_t misfrmcnt : 16; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT */ + const uint32_t miscntovf : 1; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF */ + const uint32_t ovffrmcnt : 11; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT */ + const uint32_t ovfcntovf : 1; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR. */ +typedef volatile struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register from the beginning of the component. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST 0x20 +/* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register. */ +#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST)) + +/* + * Register : Register 9 (Receive Interrupt Watchdog Timer Register) - Receive_Interrupt_Watchdog_Timer + * + * This register, when written with non-zero value, enables the watchdog timer for + * the Receive Interrupt (Bit 6) of Register 5 (Status Register) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [7:0] | RW | 0x0 | RI Watchdog Timer Count + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RI Watchdog Timer Count - riwt + * + * This bit indicates the number of system clock cycles multiplied by 256 for which + * the watchdog timer is set. The watchdog timer gets triggered with the programmed + * value after the Rx DMA completes the transfer of a frame for which the RI status + * bit is not set because of the setting in the corresponding descriptor RDES1[31]. + * When the watchdog timer runs out, the RI bit is set and the timer is stopped. + * The watchdog timer is reset when the RI bit is set high because of automatic + * setting of RI as per RDES1[31] of any received frame. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */ +#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */ +#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_MSB 7 +/* The width in bits of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */ +#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_WIDTH 8 +/* The mask used to set the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value. */ +#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value. */ +#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */ +#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_RX_INT_WDT_RIWT field value from a register. */ +#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_RX_INT_WDT. + */ +struct ALT_EMAC_DMA_RX_INT_WDT_s +{ + uint32_t riwt : 8; /* RI Watchdog Timer Count */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_RX_INT_WDT. */ +typedef volatile struct ALT_EMAC_DMA_RX_INT_WDT_s ALT_EMAC_DMA_RX_INT_WDT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_RX_INT_WDT register from the beginning of the component. */ +#define ALT_EMAC_DMA_RX_INT_WDT_OFST 0x24 +/* The address of the ALT_EMAC_DMA_RX_INT_WDT register. */ +#define ALT_EMAC_DMA_RX_INT_WDT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_INT_WDT_OFST)) + +/* + * Register : Register 10 (AXI Bus Mode Register) - AXI_Bus_Mode + * + * The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly + * used to control the burst splitting and the number of outstanding requests. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | R | 0x1 | AXI Undefined Burst Length + * [1] | RW | 0x0 | AXI Burst Length 4 + * [2] | RW | 0x0 | AXI Burst Length 8 + * [3] | RW | 0x0 | AXI Burst Length 16 + * [11:4] | ??? | 0x0 | *UNDEFINED* + * [12] | R | 0x0 | Address-Aligned Beats + * [13] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [19:16] | RW | 0x1 | AXI Maximum Read OutStanding Request Limit + * [23:20] | RW | 0x1 | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT + * [29:24] | ??? | 0x0 | *UNDEFINED* + * [30] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM + * [31] | RW | 0x0 | Enable Low Power Interface (LPI) + * + */ +/* + * Field : AXI Undefined Burst Length - undefined + * + * This bit is read-only bit and indicates the complement (invert) value of Bit 16 + * (FB) in Register 0 (Bus Mode Register[16]). + * + * * When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length + * equal to or below the maximum allowed burst length programmed in Bits[7:1]. + * + * * When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst + * lengths as indicated by BLEN16, BLEN8, or BLEN4, or a burst length of 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------------- + * ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_DISD | 0x0 | Fixed Burst Lengths 4 to 32 + * ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_END | 0x1 | Any Burst Length up to max + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED + * + * Fixed Burst Lengths 4 to 32 + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED + * + * Any Burst Length up to max + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_MSB 0 +/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED field value from a register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : AXI Burst Length 4 - blen4 + * + * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 + * on the AXI Master interface. + * + * Setting this bit has no effect when UNDEFINED is set to 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------- + * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_DISD | 0x0 | AXI No Fixed Busrts + * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_END | 0x1 | AXI Fixed Burst BLEN = 4 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 + * + * AXI No Fixed Busrts + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 + * + * AXI Fixed Burst BLEN = 4 + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_MSB 1 +/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 field value from a register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AXI Burst Length 8 - blen8 + * + * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 + * on the AXI Master interface. + * + * Setting this bit has no effect when UNDEFINED is set to 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------- + * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_DISD | 0x0 | AXI No Fixed Busrts + * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_END | 0x1 | AXI Fixed Burst BLEN = 8 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 + * + * AXI No Fixed Busrts + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 + * + * AXI Fixed Burst BLEN = 8 + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_MSB 2 +/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 field value from a register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : AXI Burst Length 16 - blen16 + * + * When this bit is set to 1 or UNDEFINED is set to 1, the GMAC-AXI is allowed to + * select a burst length of 16 on the AXI Master interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------- + * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_DISD | 0x0 | AXI No Fixed Busrts + * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_END | 0x1 | AXI Fixed Burst BLEN = 16 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 + * + * AXI No Fixed Busrts + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 + * + * AXI Fixed Burst BLEN = 16 + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_MSB 3 +/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET_MSK 0x00000008 +/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 field value from a register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Address-Aligned Beats - axi_aal + * + * This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode + * Register). + * + * When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers + * on both read and write channels. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------- + * ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_DISD | 0x0 | No Address-Alignment Bursts + * ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_END | 0x1 | Address-Alignmnet Bursts + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL + * + * No Address-Alignment Bursts + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL + * + * Address-Alignmnet Bursts + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_MSB 12 +/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_CLR_MSK 0xffffefff +/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL field value from a register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : onekbbe + * + * 1 KB Boundary Crossing Enable for the GMAC-AXI Master + * + * When set, the GMAC-AXI Master performs burst transfers that do not cross 1 KB + * boundary. When reset, the GMAC-AXI Master performs burst transfers that do not + * cross 4 KB boundary. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_FOUR_K_BOUNDARY | 0x0 | 4K boundary + * ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_ONE_K_BOUNDARY | 0x1 | 1K boundary + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE + * + * 4K boundary + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_FOUR_K_BOUNDARY 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE + * + * 1K boundary + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_ONE_K_BOUNDARY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_MSB 13 +/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE field value from a register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : AXI Maximum Read OutStanding Request Limit - rd_osr_lmt + * + * This value limits the maximum outstanding request on the AXI read interface. + * + * Maximum outstanding requests = RD_OSR_LMT+1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_MSB 19 +/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_WIDTH 4 +/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET_MSK 0x000f0000 +/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_CLR_MSK 0xfff0ffff +/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT field value from a register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_GET(value) (((value) & 0x000f0000) >> 16) +/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET(value) (((value) << 16) & 0x000f0000) + +/* + * Field : wr_osr_lmt + * + * AXI Maximum Write OutStanding Request Limit + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_MSB 23 +/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_WIDTH 4 +/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET_MSK 0x00f00000 +/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_CLR_MSK 0xff0fffff +/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT field value from a register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_GET(value) (((value) & 0x00f00000) >> 20) +/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET(value) (((value) << 20) & 0x00f00000) + +/* + * Field : lpi_xit_frm + * + * When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only + * when the Magic Packet or Remote Wake Up Packet is received. + * + * When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any + * frame is received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_DISD | 0x0 | Do Not exit LPI Mode with Magic Packet + * ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_END | 0x1 | Exit LPI Mode with Magic Packet + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM + * + * Do Not exit LPI Mode with Magic Packet + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM + * + * Exit LPI Mode with Magic Packet + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_MSB 30 +/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET_MSK 0x40000000 +/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_CLR_MSK 0xbfffffff +/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM field value from a register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Enable Low Power Interface (LPI) - en_lpi + * + * When set to 1, this bit enables the LPI mode supported by the AXI master and + * accepts the LPI request from the AXI System Clock controller. + * + * When set to 0, this bit disables the LPI mode and always denies the LPI request + * from the AXI System Clock controller. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------- + * ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_DISD | 0x0 | Disable LPI Mode + * ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_END | 0x1 | Enable LPI Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI + * + * Disable LPI Mode + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI + * + * Enable LPI Mode + */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_MSB 31 +/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET_MSK 0x80000000 +/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_CLR_MSK 0x7fffffff +/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI field value from a register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_AXI_BUS_MOD. + */ +struct ALT_EMAC_DMA_AXI_BUS_MOD_s +{ + const uint32_t undefined : 1; /* AXI Undefined Burst Length */ + uint32_t blen4 : 1; /* AXI Burst Length 4 */ + uint32_t blen8 : 1; /* AXI Burst Length 8 */ + uint32_t blen16 : 1; /* AXI Burst Length 16 */ + uint32_t : 8; /* *UNDEFINED* */ + const uint32_t axi_aal : 1; /* Address-Aligned Beats */ + uint32_t onekbbe : 1; /* ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t rd_osr_lmt : 4; /* AXI Maximum Read OutStanding Request Limit */ + uint32_t wr_osr_lmt : 4; /* ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT */ + uint32_t : 6; /* *UNDEFINED* */ + uint32_t lpi_xit_frm : 1; /* ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM */ + uint32_t en_lpi : 1; /* Enable Low Power Interface (LPI) */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_AXI_BUS_MOD. */ +typedef volatile struct ALT_EMAC_DMA_AXI_BUS_MOD_s ALT_EMAC_DMA_AXI_BUS_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_AXI_BUS_MOD register from the beginning of the component. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_OFST 0x28 +/* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register. */ +#define ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AXI_BUS_MOD_OFST)) + +/* + * Register : Register 11 (AHB or AXI Status Register) - AHB_or_AXI_Status + * + * This register provides the active status of the AXI interface's read and write + * channels. This register is useful for debugging purposes. In addition, this + * register is valid only in the Channel 0 DMA when multiple channels are present + * in the AV mode. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [0] | R | 0x0 | AXI Master Write Channel Status + * [1] | R | 0x0 | AXI Master Read Channel Status + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : AXI Master Write Channel Status - axwhsts + * + * When high, it indicates that AXI Master's write channel is active and + * transferring data + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_MSB 0 +/* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS field value from a register. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : AXI Master Read Channel Status - axirdsts + * + * When high, it indicates that AXI Master's read channel is active and + * transferring data. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_MSB 1 +/* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS field value from a register. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STAT. + */ +struct ALT_EMAC_DMA_AHB_OR_AXI_STAT_s +{ + const uint32_t axwhsts : 1; /* AXI Master Write Channel Status */ + const uint32_t axirdsts : 1; /* AXI Master Read Channel Status */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STAT. */ +typedef volatile struct ALT_EMAC_DMA_AHB_OR_AXI_STAT_s ALT_EMAC_DMA_AHB_OR_AXI_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register from the beginning of the component. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST 0x2c +/* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register. */ +#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST)) + +/* + * Register : Register 18 (Current Host Transmit Descriptor Register) - Current_Host_Transmit_Descriptor + * + * The Current Host Transmit Descriptor register points to the start address of the + * current Transmit Descriptor read by the DMA. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [31:0] | R | 0x0 | Host Transmit Descriptor Address Pointer + * + */ +/* + * Field : Host Transmit Descriptor Address Pointer - curtdesaptr + * + * Cleared on Reset. Pointer updated by the DMA during operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_MSB 31 +/* The width in bits of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_WIDTH 32 +/* The mask used to set the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR field value from a register. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_TX_DESC. + */ +struct ALT_EMAC_DMA_CUR_HOST_TX_DESC_s +{ + const uint32_t curtdesaptr : 32; /* Host Transmit Descriptor Address Pointer */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_TX_DESC. */ +typedef volatile struct ALT_EMAC_DMA_CUR_HOST_TX_DESC_s ALT_EMAC_DMA_CUR_HOST_TX_DESC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register from the beginning of the component. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_OFST 0x48 +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_TX_DESC_OFST)) + +/* + * Register : Register 19 (Current Host Receive Descriptor Register) - Current_Host_Receive_Descriptor + * + * The Current Host Receive Descriptor register points to the start address of the + * current Receive Descriptor read by the DMA. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [31:0] | R | 0x0 | Host Receive Descriptor Address Pointer + * + */ +/* + * Field : Host Receive Descriptor Address Pointer - currdesaptr + * + * Cleared on Reset. Pointer updated by the DMA during operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_MSB 31 +/* The width in bits of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_WIDTH 32 +/* The mask used to set the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR field value from a register. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_RX_DESC. + */ +struct ALT_EMAC_DMA_CUR_HOST_RX_DESC_s +{ + const uint32_t currdesaptr : 32; /* Host Receive Descriptor Address Pointer */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_RX_DESC. */ +typedef volatile struct ALT_EMAC_DMA_CUR_HOST_RX_DESC_s ALT_EMAC_DMA_CUR_HOST_RX_DESC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register from the beginning of the component. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_OFST 0x4c +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_RX_DESC_OFST)) + +/* + * Register : Register 20 (Current Host Transmit Buffer Address Register) - Current_Host_Transmit_Buffer_Address + * + * The Current Host Transmit Buffer Address register points to the current Transmit + * Buffer Address being read by the DMA. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------- + * [31:0] | R | 0x0 | Host Transmit Buffer Address Pointer + * + */ +/* + * Field : Host Transmit Buffer Address Pointer - curtbufaptr + * + * Cleared on Reset. Pointer updated by the DMA during operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_MSB 31 +/* The width in bits of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_WIDTH 32 +/* The mask used to set the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR field value from a register. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR. + */ +struct ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_s +{ + const uint32_t curtbufaptr : 32; /* Host Transmit Buffer Address Pointer */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR. */ +typedef volatile struct ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_s ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register from the beginning of the component. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_OFST 0x50 +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register. */ +#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_OFST)) + +/* + * Register : Register 21 (Current Host Receive Buffer Address Register) - Current_Host_Receive_Buffer_Address + * + * The Current Host Receive Buffer Address register points to the current Receive + * Buffer address being read by the DMA. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [31:0] | R | 0x0 | Host Receive Buffer Address Pointer + * + */ +/* + * Field : Host Receive Buffer Address Pointer - currbufaptr + * + * Cleared on Reset. Pointer updated by the DMA during operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_MSB 31 +/* The width in bits of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_WIDTH 32 +/* The mask used to set the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_CLR_MSK 0x00000000 +/* The reset value of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR field value from a register. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR. + */ +struct ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_s +{ + const uint32_t currbufaptr : 32; /* Host Receive Buffer Address Pointer */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR. */ +typedef volatile struct ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_s ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register from the beginning of the component. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_OFST 0x54 +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register. */ +#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_OFST)) + +/* + * Register : Register 22 (HW Feature Register) - HW_Feature + * + * This register indicates the presence of the optional features or functions of + * the gmac. The software driver can use this register to dynamically enable or + * disable the programs related to the optional blocks. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | R | 0x1 | MII Selection + * [1] | R | 0x1 | GMII Selection + * [2] | R | 0x1 | Half Duplex Selection + * [3] | ??? | 0x0 | *UNDEFINED* + * [4] | R | 0x1 | Hash Filter + * [5] | R | 0x1 | Multiple MAC Address Register + * [6] | R | 0x0 | PCS Select + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x1 | SMA Select + * [9] | R | 0x1 | RWK Select + * [10] | R | 0x1 | MGK Select + * [11] | R | 0x1 | MMC Select + * [12] | R | 0x1 | TS Version1 Select + * [13] | R | 0x1 | TS Version2 Select + * [14] | R | 0x1 | Energy Efficient Ethernet + * [15] | R | 0x0 | AV Select + * [16] | R | 0x1 | Tx Offload Checksum + * [17] | R | 0x0 | Rx Type 1 Checksum Offload + * [18] | R | 0x1 | Rx Type 2 Checksum Offload + * [19] | R | 0x1 | Rx FIFO Size + * [21:20] | R | 0x0 | Rx Channel Count + * [23:22] | R | 0x0 | Tx Channel Count + * [24] | R | 0x1 | Enhanced Descriptor Select + * [27:25] | ??? | 0x0 | *UNDEFINED* + * [30:28] | R | 0x0 | Selected PHY Interface + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MII Selection - miisel + * + * 10/100 Mbps support + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD | 0x0 | 10 Mbps or 100 Mbps disabled + * ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END | 0x1 | 10 Mbps or 100 Mbps enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MIISEL + * + * 10 Mbps or 100 Mbps disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MIISEL + * + * 10 Mbps or 100 Mbps enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_MSB 0 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_MIISEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : GMII Selection - gmiisel + * + * 1000 Mbps support + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------- + * ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD | 0x0 | 1000 Mbps disabled + * ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END | 0x1 | 1000 Mbps enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_GMIISEL + * + * 1000 Mbps disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_GMIISEL + * + * 1000 Mbps enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_MSB 1 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_GMIISEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Half Duplex Selection - hdsel + * + * Half-Duplex support + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD | 0x0 | Half Duplex disabled + * ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END | 0x1 | Half Duplex enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HDSEL + * + * Half Duplex disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HDSEL + * + * Half Duplex enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_MSB 2 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_HDSEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Hash Filter - hashsel + * + * HASH Filter support + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD | 0x0 | Hash Filter disabled + * ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END | 0x1 | Hash Filter enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HASHSEL + * + * Hash Filter disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HASHSEL + * + * Hash Filter enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_MSB 4 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_CLR_MSK 0xffffffef +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_HASHSEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Multiple MAC Address Register - addmacadrsel + * + * Multiple MAC Address Registers support + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:---------------------------------------- + * ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD | 0x0 | Multiple MAC Address registers disabled + * ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END | 0x1 | Multiple MAC Address registers enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL + * + * Multiple MAC Address registers disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL + * + * Multiple MAC Address registers enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_MSB 5 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : PCS Select - pcssel + * + * TBI/SGMII/RTBI PHY interface support + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:--------------------- + * ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD | 0x0 | PCS Support disabled + * ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END | 0x1 | PCS Support enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_PCSSEL + * + * PCS Support disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_PCSSEL + * + * PCS Support enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_MSB 6 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_PCSSEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : SMA Select - smasel + * + * SMA (MDIO) Interface support + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------- + * ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD | 0x0 | SMA Interface Support disabled + * ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END | 0x1 | SMA Interface Support enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_SMASEL + * + * SMA Interface Support disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_SMASEL + * + * SMA Interface Support enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_MSB 8 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET_MSK 0x00000100 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_CLR_MSK 0xfffffeff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_SMASEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : RWK Select - rwksel + * + * PMT Remote Wakeup support + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD | 0x0 | PMT Remote Wake Up disabled + * ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END | 0x1 | PMT Remote Wake Up enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RWKSEL + * + * PMT Remote Wake Up disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RWKSEL + * + * PMT Remote Wake Up enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_MSB 9 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_RWKSEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : MGK Select - mgksel + * + * PMT Magic Packet + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------------- + * ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD | 0x0 | PMT Magic Packet disabled + * ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END | 0x1 | PMT Magic Packet enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MGKSEL + * + * PMT Magic Packet disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MGKSEL + * + * PMT Magic Packet enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_MSB 10 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET_MSK 0x00000400 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_CLR_MSK 0xfffffbff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_MGKSEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MMC Select - mmcsel + * + * RMON block + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD | 0x0 | Rmon block disabled + * ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END | 0x1 | Rmon block enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MMCSEL + * + * Rmon block disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MMCSEL + * + * Rmon block enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_MSB 11 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_MMCSEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : TS Version1 Select - tsver1sel + * + * Only IEEE 1588-2002 Timestamp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD | 0x0 | TS Version1 Select disabled + * ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END | 0x1 | TS Version1 Select enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL + * + * TS Version1 Select disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL + * + * TS Version1 Select enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_MSB 12 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_CLR_MSK 0xffffefff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : TS Version2 Select - tsver2sel + * + * IEEE 1588-2008 Advanced Timestamp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD | 0x0 | TS Version2 Select disabled + * ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END | 0x1 | TS Version2 Select enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL + * + * TS Version2 Select disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL + * + * TS Version2 Select enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_MSB 13 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET_MSK 0x00002000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_CLR_MSK 0xffffdfff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Energy Efficient Ethernet - eeesel + * + * Energy Efficient Ethernet Feature + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------- + * ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD | 0x0 | Energy Efficient Ethernet disabled + * ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END | 0x1 | Energy Efficient Ethernet enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_EEESEL + * + * Energy Efficient Ethernet disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_EEESEL + * + * Energy Efficient Ethernet enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_MSB 14 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET_MSK 0x00004000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_CLR_MSK 0xffffbfff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_EEESEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : AV Select - avsel + * + * AV Feature + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------- + * ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD | 0x0 | AV Select disabled + * ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END | 0x1 | AV Select enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_AVSEL + * + * AV Select disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_AVSEL + * + * AV Select enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_MSB 15 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET_MSK 0x00008000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_CLR_MSK 0xffff7fff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_AVSEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Tx Offload Checksum - txoesel + * + * Checksum Offload in Tx + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD | 0x0 | Tx Offload Checksum disabled + * ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END | 0x1 | Tx Offload Checksum enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXOESEL + * + * Tx Offload Checksum disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXOESEL + * + * Tx Offload Checksum enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_MSB 16 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET_MSK 0x00010000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_CLR_MSK 0xfffeffff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_TXOESEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Rx Type 1 Checksum Offload - rxtyp1coe + * + * IP Checksum Offload (Type 1) in Rx + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------ + * ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD | 0x0 | Rx Type 1 Checksum Offload disabled + * ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END | 0x1 | Rx Type 1 Checksum Offload enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE + * + * Rx Type 1 Checksum Offload disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE + * + * Rx Type 1 Checksum Offload enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_MSB 17 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET_MSK 0x00020000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_CLR_MSK 0xfffdffff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Rx Type 2 Checksum Offload - rxtyp2coe + * + * IP Checksum Offload (Type 2) in Rx + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------ + * ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD | 0x0 | Rx Type 2 Checksum Offload disabled + * ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END | 0x1 | Rx Type 2 Checksum Offload enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE + * + * Rx Type 2 Checksum Offload disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE + * + * Rx Type 2 Checksum Offload enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_MSB 18 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET_MSK 0x00040000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_CLR_MSK 0xfffbffff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Rx FIFO Size - rxfifosize + * + * RxFIFO > 2048 Bytes + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------- + * ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD | 0x0 | RxFIFO > 2048 bytes disabled + * ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END | 0x1 | RxFIFO > 2048 bytes enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE + * + * RxFIFO > 2048 bytes disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE + * + * RxFIFO > 2048 bytes enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_MSB 19 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET_MSK 0x00080000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Rx Channel Count - rxchcnt + * + * Number of additional Rx channels + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------- + * ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD | 0x0 | Rx Channel Count disabled + * ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END | 0x1 | Rx Channel Count enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXCHCNT + * + * Rx Channel Count disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXCHCNT + * + * Rx Channel Count enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_MSB 21 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_WIDTH 2 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET_MSK 0x00300000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_CLR_MSK 0xffcfffff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Tx Channel Count - txchcnt + * + * Number of additional Tx channels + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------- + * ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD | 0x0 | Tx Channel Count disabled + * ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END | 0x1 | Tx Channel Count enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXCHCNT + * + * Tx Channel Count disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXCHCNT + * + * Tx Channel Count enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_MSB 23 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_WIDTH 2 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET_MSK 0x00c00000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_CLR_MSK 0xff3fffff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_GET(value) (((value) & 0x00c00000) >> 22) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET(value) (((value) << 22) & 0x00c00000) + +/* + * Field : Enhanced Descriptor Select - enhdessel + * + * Alternate (Enhanced Descriptor) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------ + * ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD | 0x0 | Enhanced Descriptor Select disabled + * ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END | 0x1 | Enhanced Descriptor Select enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL + * + * Enhanced Descriptor Select disabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL + * + * Enhanced Descriptor Select enabled + */ +#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_MSB 24 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_WIDTH 1 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET_MSK 0x01000000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_CLR_MSK 0xfeffffff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_RESET 0x1 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Selected PHY Interface - actphyif + * + * When you have multiple PHY interfaces in your configuration, this field + * indicates the sampled value of emacx_phy_if_selduring reset de-assertion. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:-------------------------- + * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0 | 0x0 | Sampled Value GMII or MII + * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1 | 0x1 | Sampled Value RGMII + * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2 | 0x2 | Sampled Value SGMII + * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3 | 0x3 | Sampled Value TBI + * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4 | 0x4 | Sampled Value RMII + * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5 | 0x5 | Sampled Value RTBI + * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6 | 0x6 | Sampled Value SMII + * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7 | 0x7 | Sampled Value RevMII + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF + * + * Sampled Value GMII or MII + */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0 0x0 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF + * + * Sampled Value RGMII + */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1 0x1 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF + * + * Sampled Value SGMII + */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2 0x2 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF + * + * Sampled Value TBI + */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3 0x3 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF + * + * Sampled Value RMII + */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4 0x4 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF + * + * Sampled Value RTBI + */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5 0x5 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF + * + * Sampled Value SMII + */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6 0x6 +/* + * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF + * + * Sampled Value RevMII + */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_MSB 30 +/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_WIDTH 3 +/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET_MSK 0x70000000 +/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value. */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_CLR_MSK 0x8fffffff +/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_RESET 0x0 +/* Extracts the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF field value from a register. */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_GET(value) (((value) & 0x70000000) >> 28) +/* Produces a ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value suitable for setting the register. */ +#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET(value) (((value) << 28) & 0x70000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_EMAC_DMA_HW_FEATURE. + */ +struct ALT_EMAC_DMA_HW_FEATURE_s +{ + const uint32_t miisel : 1; /* MII Selection */ + const uint32_t gmiisel : 1; /* GMII Selection */ + const uint32_t hdsel : 1; /* Half Duplex Selection */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t hashsel : 1; /* Hash Filter */ + const uint32_t addmacadrsel : 1; /* Multiple MAC Address Register */ + const uint32_t pcssel : 1; /* PCS Select */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t smasel : 1; /* SMA Select */ + const uint32_t rwksel : 1; /* RWK Select */ + const uint32_t mgksel : 1; /* MGK Select */ + const uint32_t mmcsel : 1; /* MMC Select */ + const uint32_t tsver1sel : 1; /* TS Version1 Select */ + const uint32_t tsver2sel : 1; /* TS Version2 Select */ + const uint32_t eeesel : 1; /* Energy Efficient Ethernet */ + const uint32_t avsel : 1; /* AV Select */ + const uint32_t txoesel : 1; /* Tx Offload Checksum */ + const uint32_t rxtyp1coe : 1; /* Rx Type 1 Checksum Offload */ + const uint32_t rxtyp2coe : 1; /* Rx Type 2 Checksum Offload */ + const uint32_t rxfifosize : 1; /* Rx FIFO Size */ + const uint32_t rxchcnt : 2; /* Rx Channel Count */ + const uint32_t txchcnt : 2; /* Tx Channel Count */ + const uint32_t enhdessel : 1; /* Enhanced Descriptor Select */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t actphyif : 3; /* Selected PHY Interface */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_EMAC_DMA_HW_FEATURE. */ +typedef volatile struct ALT_EMAC_DMA_HW_FEATURE_s ALT_EMAC_DMA_HW_FEATURE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_EMAC_DMA_HW_FEATURE register from the beginning of the component. */ +#define ALT_EMAC_DMA_HW_FEATURE_OFST 0x58 +/* The address of the ALT_EMAC_DMA_HW_FEATURE register. */ +#define ALT_EMAC_DMA_HW_FEATURE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_HW_FEATURE_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_EMAC_DMA. + */ +struct ALT_EMAC_DMA_s +{ + volatile ALT_EMAC_DMA_BUS_MOD_t Bus_Mode; /* ALT_EMAC_DMA_BUS_MOD */ + volatile ALT_EMAC_DMA_TX_POLL_DEMAND_t Transmit_Poll_Demand; /* ALT_EMAC_DMA_TX_POLL_DEMAND */ + volatile ALT_EMAC_DMA_RX_POLL_DEMAND_t Receive_Poll_Demand; /* ALT_EMAC_DMA_RX_POLL_DEMAND */ + volatile ALT_EMAC_DMA_RX_DESC_LIST_ADDR_t Receive_Descriptor_List_Address; /* ALT_EMAC_DMA_RX_DESC_LIST_ADDR */ + volatile ALT_EMAC_DMA_TX_DESC_LIST_ADDR_t Transmit_Descriptor_List_Address; /* ALT_EMAC_DMA_TX_DESC_LIST_ADDR */ + volatile ALT_EMAC_DMA_STAT_t Status; /* ALT_EMAC_DMA_STAT */ + volatile ALT_EMAC_DMA_OP_MOD_t Operation_Mode; /* ALT_EMAC_DMA_OP_MOD */ + volatile ALT_EMAC_DMA_INT_EN_t Interrupt_Enable; /* ALT_EMAC_DMA_INT_EN */ + volatile ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_t Missed_Frame_And_Buffer_Overflow_Counter; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR */ + volatile ALT_EMAC_DMA_RX_INT_WDT_t Receive_Interrupt_Watchdog_Timer; /* ALT_EMAC_DMA_RX_INT_WDT */ + volatile ALT_EMAC_DMA_AXI_BUS_MOD_t AXI_Bus_Mode; /* ALT_EMAC_DMA_AXI_BUS_MOD */ + volatile ALT_EMAC_DMA_AHB_OR_AXI_STAT_t AHB_or_AXI_Status; /* ALT_EMAC_DMA_AHB_OR_AXI_STAT */ + volatile uint32_t _pad_0x30_0x47[6]; /* *UNDEFINED* */ + volatile ALT_EMAC_DMA_CUR_HOST_TX_DESC_t Current_Host_Transmit_Descriptor; /* ALT_EMAC_DMA_CUR_HOST_TX_DESC */ + volatile ALT_EMAC_DMA_CUR_HOST_RX_DESC_t Current_Host_Receive_Descriptor; /* ALT_EMAC_DMA_CUR_HOST_RX_DESC */ + volatile ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_t Current_Host_Transmit_Buffer_Address; /* ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR */ + volatile ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_t Current_Host_Receive_Buffer_Address; /* ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR */ + volatile ALT_EMAC_DMA_HW_FEATURE_t HW_Feature; /* ALT_EMAC_DMA_HW_FEATURE */ +}; + +/* The typedef declaration for register group ALT_EMAC_DMA. */ +typedef volatile struct ALT_EMAC_DMA_s ALT_EMAC_DMA_t; +/* The struct declaration for the raw register contents of register group ALT_EMAC_DMA. */ +struct ALT_EMAC_DMA_raw_s +{ + volatile uint32_t Bus_Mode; /* ALT_EMAC_DMA_BUS_MOD */ + volatile uint32_t Transmit_Poll_Demand; /* ALT_EMAC_DMA_TX_POLL_DEMAND */ + volatile uint32_t Receive_Poll_Demand; /* ALT_EMAC_DMA_RX_POLL_DEMAND */ + volatile uint32_t Receive_Descriptor_List_Address; /* ALT_EMAC_DMA_RX_DESC_LIST_ADDR */ + volatile uint32_t Transmit_Descriptor_List_Address; /* ALT_EMAC_DMA_TX_DESC_LIST_ADDR */ + volatile uint32_t Status; /* ALT_EMAC_DMA_STAT */ + volatile uint32_t Operation_Mode; /* ALT_EMAC_DMA_OP_MOD */ + volatile uint32_t Interrupt_Enable; /* ALT_EMAC_DMA_INT_EN */ + volatile uint32_t Missed_Frame_And_Buffer_Overflow_Counter; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR */ + volatile uint32_t Receive_Interrupt_Watchdog_Timer; /* ALT_EMAC_DMA_RX_INT_WDT */ + volatile uint32_t AXI_Bus_Mode; /* ALT_EMAC_DMA_AXI_BUS_MOD */ + volatile uint32_t AHB_or_AXI_Status; /* ALT_EMAC_DMA_AHB_OR_AXI_STAT */ + volatile uint32_t _pad_0x30_0x47[6]; /* *UNDEFINED* */ + volatile uint32_t Current_Host_Transmit_Descriptor; /* ALT_EMAC_DMA_CUR_HOST_TX_DESC */ + volatile uint32_t Current_Host_Receive_Descriptor; /* ALT_EMAC_DMA_CUR_HOST_RX_DESC */ + volatile uint32_t Current_Host_Transmit_Buffer_Address; /* ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR */ + volatile uint32_t Current_Host_Receive_Buffer_Address; /* ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR */ + volatile uint32_t HW_Feature; /* ALT_EMAC_DMA_HW_FEATURE */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_EMAC_DMA. */ +typedef volatile struct ALT_EMAC_DMA_raw_s ALT_EMAC_DMA_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_EMAC. + */ +struct ALT_EMAC_s +{ + volatile ALT_EMAC_GMAC_t gmacgrp; /* ALT_EMAC_GMAC */ + volatile uint32_t _pad_0xb80_0xfff[288]; /* *UNDEFINED* */ + volatile ALT_EMAC_DMA_t dmagrp; /* ALT_EMAC_DMA */ + volatile uint32_t _pad_0x105c_0x2000[1001]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_EMAC. */ +typedef volatile struct ALT_EMAC_s ALT_EMAC_t; +/* The struct declaration for the raw register contents of register group ALT_EMAC. */ +struct ALT_EMAC_raw_s +{ + volatile ALT_EMAC_GMAC_raw_t gmacgrp; /* ALT_EMAC_GMAC */ + volatile uint32_t _pad_0xb80_0xfff[288]; /* *UNDEFINED* */ + volatile ALT_EMAC_DMA_raw_t dmagrp; /* ALT_EMAC_DMA */ + volatile uint32_t _pad_0x105c_0x2000[1001]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_EMAC. */ +typedef volatile struct ALT_EMAC_raw_s ALT_EMAC_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_EMAC_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_f2h.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_f2h.h new file mode 100644 index 000000000..febf9e6ba --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_f2h.h @@ -0,0 +1,1075 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_F2H */ + +#ifndef __ALTERA_ALT_F2H_H__ +#define __ALTERA_ALT_F2H_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : FPGA2HPS AXI Bridge Module - ALT_F2H + * FPGA2HPS AXI Bridge Module + * + * Registers in the FPGA2HPS AXI Bridge Module. + * + */ +/* + * Register Group : ID Register Group - ALT_F2H_IDGRP + * ID Register Group + * + * Contains registers that identify the ARM NIC-301 IP Core. + * + */ +/* + * Register : Peripheral ID4 Register - periph_id_4 + * + * JEP106 continuation code + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [7:0] | R | 0x4 | Peripheral ID4 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Peripheral ID4 - periph_id_4 + * + * JEP106 continuation code + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7 +/* The width in bits of the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8 +/* The mask used to set the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4 +/* Extracts the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */ +#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */ +#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_ID_PERIPH_ID_4. + */ +struct ALT_F2H_ID_PERIPH_ID_4_s +{ + const uint32_t periph_id_4 : 8; /* Peripheral ID4 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_ID_PERIPH_ID_4. */ +typedef volatile struct ALT_F2H_ID_PERIPH_ID_4_s ALT_F2H_ID_PERIPH_ID_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_ID_PERIPH_ID_4 register from the beginning of the component. */ +#define ALT_F2H_ID_PERIPH_ID_4_OFST 0xfd0 + +/* + * Register : Peripheral ID0 Register - periph_id_0 + * + * Peripheral ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [7:0] | R | 0x1 | Part Number [7:0] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Part Number [7:0] - pn7to0 + * + * Part Number [7:0] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_MSB 7 +/* The width in bits of the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_WIDTH 8 +/* The mask used to set the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff +/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00 +/* The reset value of the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_RESET 0x1 +/* Extracts the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 field value from a register. */ +#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */ +#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_ID_PERIPH_ID_0. + */ +struct ALT_F2H_ID_PERIPH_ID_0_s +{ + const uint32_t pn7to0 : 8; /* Part Number [7:0] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_ID_PERIPH_ID_0. */ +typedef volatile struct ALT_F2H_ID_PERIPH_ID_0_s ALT_F2H_ID_PERIPH_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_ID_PERIPH_ID_0 register from the beginning of the component. */ +#define ALT_F2H_ID_PERIPH_ID_0_OFST 0xfe0 + +/* + * Register : Peripheral ID1 Register - periph_id_1 + * + * Peripheral ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8 + * + * JEP106[3:0], Part Number [11:8] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7 +/* The width in bits of the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8 +/* The mask used to set the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff +/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00 +/* The reset value of the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3 +/* Extracts the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */ +#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */ +#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_ID_PERIPH_ID_1. + */ +struct ALT_F2H_ID_PERIPH_ID_1_s +{ + const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_ID_PERIPH_ID_1. */ +typedef volatile struct ALT_F2H_ID_PERIPH_ID_1_s ALT_F2H_ID_PERIPH_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_ID_PERIPH_ID_1 register from the beginning of the component. */ +#define ALT_F2H_ID_PERIPH_ID_1_OFST 0xfe4 + +/* + * Register : Peripheral ID2 Register - periph_id_2 + * + * Peripheral ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4 + * + * Revision, JEP106 code flag, JEP106[6:4] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7 +/* The width in bits of the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8 +/* The mask used to set the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b +/* Extracts the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */ +#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */ +#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_ID_PERIPH_ID_2. + */ +struct ALT_F2H_ID_PERIPH_ID_2_s +{ + const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_ID_PERIPH_ID_2. */ +typedef volatile struct ALT_F2H_ID_PERIPH_ID_2_s ALT_F2H_ID_PERIPH_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_ID_PERIPH_ID_2 register from the beginning of the component. */ +#define ALT_F2H_ID_PERIPH_ID_2_OFST 0xfe8 + +/* + * Register : Peripheral ID3 Register - periph_id_3 + * + * Peripheral ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [3:0] | R | 0x0 | Customer Model Number + * [7:4] | R | 0x0 | Revision + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Customer Model Number - cust_mod_num + * + * Customer Model Number + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3 +/* The width in bits of the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4 +/* The mask used to set the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f +/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0 +/* Extracts the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */ +#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */ +#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Revision - rev_and + * + * Revision + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_MSB 7 +/* The width in bits of the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_WIDTH 4 +/* The mask used to set the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f +/* The reset value of the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_RESET 0x0 +/* Extracts the ALT_F2H_ID_PERIPH_ID_3_REV_AND field value from a register. */ +#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_F2H_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */ +#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_ID_PERIPH_ID_3. + */ +struct ALT_F2H_ID_PERIPH_ID_3_s +{ + const uint32_t cust_mod_num : 4; /* Customer Model Number */ + const uint32_t rev_and : 4; /* Revision */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_ID_PERIPH_ID_3. */ +typedef volatile struct ALT_F2H_ID_PERIPH_ID_3_s ALT_F2H_ID_PERIPH_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_ID_PERIPH_ID_3 register from the beginning of the component. */ +#define ALT_F2H_ID_PERIPH_ID_3_OFST 0xfec + +/* + * Register : Component ID0 Register - comp_id_0 + * + * Component ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xd | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_MSB 7 +/* The width in bits of the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_RESET 0xd +/* Extracts the ALT_F2H_ID_COMP_ID_0_PREAMBLE field value from a register. */ +#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_F2H_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */ +#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_ID_COMP_ID_0. + */ +struct ALT_F2H_ID_COMP_ID_0_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_ID_COMP_ID_0. */ +typedef volatile struct ALT_F2H_ID_COMP_ID_0_s ALT_F2H_ID_COMP_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_ID_COMP_ID_0 register from the beginning of the component. */ +#define ALT_F2H_ID_COMP_ID_0_OFST 0xff0 + +/* + * Register : Component ID1 Register - comp_id_1 + * + * Component ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------- + * [7:0] | R | 0xf0 | Generic IP component class, Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generic IP component class, Preamble - genipcompcls_preamble + * + * Generic IP component class, Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7 +/* The width in bits of the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0 +/* Extracts the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */ +#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */ +#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_ID_COMP_ID_1. + */ +struct ALT_F2H_ID_COMP_ID_1_s +{ + const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_ID_COMP_ID_1. */ +typedef volatile struct ALT_F2H_ID_COMP_ID_1_s ALT_F2H_ID_COMP_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_ID_COMP_ID_1 register from the beginning of the component. */ +#define ALT_F2H_ID_COMP_ID_1_OFST 0xff4 + +/* + * Register : Component ID2 Register - comp_id_2 + * + * Component ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0x5 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_MSB 7 +/* The width in bits of the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_RESET 0x5 +/* Extracts the ALT_F2H_ID_COMP_ID_2_PREAMBLE field value from a register. */ +#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_F2H_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */ +#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_ID_COMP_ID_2. + */ +struct ALT_F2H_ID_COMP_ID_2_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_ID_COMP_ID_2. */ +typedef volatile struct ALT_F2H_ID_COMP_ID_2_s ALT_F2H_ID_COMP_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_ID_COMP_ID_2 register from the beginning of the component. */ +#define ALT_F2H_ID_COMP_ID_2_OFST 0xff8 + +/* + * Register : Component ID3 Register - comp_id_3 + * + * Component ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xb1 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_MSB 7 +/* The width in bits of the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_RESET 0xb1 +/* Extracts the ALT_F2H_ID_COMP_ID_3_PREAMBLE field value from a register. */ +#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_F2H_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */ +#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_ID_COMP_ID_3. + */ +struct ALT_F2H_ID_COMP_ID_3_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_ID_COMP_ID_3. */ +typedef volatile struct ALT_F2H_ID_COMP_ID_3_s ALT_F2H_ID_COMP_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_ID_COMP_ID_3 register from the beginning of the component. */ +#define ALT_F2H_ID_COMP_ID_3_OFST 0xffc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_F2H_IDGRP. + */ +struct ALT_F2H_IDGRP_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile ALT_F2H_ID_PERIPH_ID_4_t periph_id_4; /* ALT_F2H_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile ALT_F2H_ID_PERIPH_ID_0_t periph_id_0; /* ALT_F2H_ID_PERIPH_ID_0 */ + volatile ALT_F2H_ID_PERIPH_ID_1_t periph_id_1; /* ALT_F2H_ID_PERIPH_ID_1 */ + volatile ALT_F2H_ID_PERIPH_ID_2_t periph_id_2; /* ALT_F2H_ID_PERIPH_ID_2 */ + volatile ALT_F2H_ID_PERIPH_ID_3_t periph_id_3; /* ALT_F2H_ID_PERIPH_ID_3 */ + volatile ALT_F2H_ID_COMP_ID_0_t comp_id_0; /* ALT_F2H_ID_COMP_ID_0 */ + volatile ALT_F2H_ID_COMP_ID_1_t comp_id_1; /* ALT_F2H_ID_COMP_ID_1 */ + volatile ALT_F2H_ID_COMP_ID_2_t comp_id_2; /* ALT_F2H_ID_COMP_ID_2 */ + volatile ALT_F2H_ID_COMP_ID_3_t comp_id_3; /* ALT_F2H_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for register group ALT_F2H_IDGRP. */ +typedef volatile struct ALT_F2H_IDGRP_s ALT_F2H_IDGRP_t; +/* The struct declaration for the raw register contents of register group ALT_F2H_IDGRP. */ +struct ALT_F2H_IDGRP_raw_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile uint32_t periph_id_4; /* ALT_F2H_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile uint32_t periph_id_0; /* ALT_F2H_ID_PERIPH_ID_0 */ + volatile uint32_t periph_id_1; /* ALT_F2H_ID_PERIPH_ID_1 */ + volatile uint32_t periph_id_2; /* ALT_F2H_ID_PERIPH_ID_2 */ + volatile uint32_t periph_id_3; /* ALT_F2H_ID_PERIPH_ID_3 */ + volatile uint32_t comp_id_0; /* ALT_F2H_ID_COMP_ID_0 */ + volatile uint32_t comp_id_1; /* ALT_F2H_ID_COMP_ID_1 */ + volatile uint32_t comp_id_2; /* ALT_F2H_ID_COMP_ID_2 */ + volatile uint32_t comp_id_3; /* ALT_F2H_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_F2H_IDGRP. */ +typedef volatile struct ALT_F2H_IDGRP_raw_s ALT_F2H_IDGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Slave Register Group - ALT_F2H_SLVGRP + * Slave Register Group + * + * Registers associated with slave interfaces. + * + */ +/* + * Register Group : 32-bit Slave - ALT_F2H_SLV_B32 + * 32-bit Slave + * + * Registers associated with the 32-bit AXI slave interface. + * + * These registers are only active when the FPGA2HPS AXI Bridge is configured with + * a 32-bit FPGA AXI slave interface. + * + */ +/* + * Register : Functionality Modification 2 Register - fn_mod2 + * + * Controls bypass merge of upsizing/downsizing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Bypass Merge + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bypass Merge - bypass_merge + * + * Controls bypass merge of upsizing/downsizing. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------- + * ALT_F2H_FN_MOD2_BYPASS_MERGE_E_ALTER | 0x0 | The network can alter transactions. + * ALT_F2H_FN_MOD2_BYPASS_MERGE_E_NOALTER | 0x1 | The network does not alter any transactions that + * : | | could pass through the upsizer legally without + * : | | alteration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_F2H_FN_MOD2_BYPASS_MERGE + * + * The network can alter transactions. + */ +#define ALT_F2H_FN_MOD2_BYPASS_MERGE_E_ALTER 0x0 +/* + * Enumerated value for register field ALT_F2H_FN_MOD2_BYPASS_MERGE + * + * The network does not alter any transactions that could pass through the upsizer + * legally without alteration. + */ +#define ALT_F2H_FN_MOD2_BYPASS_MERGE_E_NOALTER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_F2H_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_F2H_FN_MOD2_BYPASS_MERGE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_F2H_FN_MOD2_BYPASS_MERGE_MSB 0 +/* The width in bits of the ALT_F2H_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_F2H_FN_MOD2_BYPASS_MERGE_WIDTH 1 +/* The mask used to set the ALT_F2H_FN_MOD2_BYPASS_MERGE register field value. */ +#define ALT_F2H_FN_MOD2_BYPASS_MERGE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_F2H_FN_MOD2_BYPASS_MERGE register field value. */ +#define ALT_F2H_FN_MOD2_BYPASS_MERGE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_F2H_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_F2H_FN_MOD2_BYPASS_MERGE_RESET 0x0 +/* Extracts the ALT_F2H_FN_MOD2_BYPASS_MERGE field value from a register. */ +#define ALT_F2H_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_F2H_FN_MOD2_BYPASS_MERGE register field value suitable for setting the register. */ +#define ALT_F2H_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_FN_MOD2. + */ +struct ALT_F2H_FN_MOD2_s +{ + uint32_t bypass_merge : 1; /* Bypass Merge */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_FN_MOD2. */ +typedef volatile struct ALT_F2H_FN_MOD2_s ALT_F2H_FN_MOD2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_FN_MOD2 register from the beginning of the component. */ +#define ALT_F2H_FN_MOD2_OFST 0x24 +/* The address of the ALT_F2H_FN_MOD2 register. */ +#define ALT_F2H_FN_MOD2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_F2H_FN_MOD2_OFST)) + +/* + * Register : Issuing Functionality Modification Register - fn_mod + * + * Sets the block issuing capability to multiple or single outstanding + * transactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [0] | RW | 0x0 | ALT_F2H_FN_MOD_RD + * [1] | RW | 0x0 | ALT_F2H_FN_MOD_WR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : rd + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------------------------------------- + * ALT_F2H_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions + * ALT_F2H_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_F2H_FN_MOD_RD + * + * Multiple outstanding read transactions + */ +#define ALT_F2H_FN_MOD_RD_E_MULT 0x0 +/* + * Enumerated value for register field ALT_F2H_FN_MOD_RD + * + * Only a single outstanding read transaction + */ +#define ALT_F2H_FN_MOD_RD_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_F2H_FN_MOD_RD register field. */ +#define ALT_F2H_FN_MOD_RD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_F2H_FN_MOD_RD register field. */ +#define ALT_F2H_FN_MOD_RD_MSB 0 +/* The width in bits of the ALT_F2H_FN_MOD_RD register field. */ +#define ALT_F2H_FN_MOD_RD_WIDTH 1 +/* The mask used to set the ALT_F2H_FN_MOD_RD register field value. */ +#define ALT_F2H_FN_MOD_RD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_F2H_FN_MOD_RD register field value. */ +#define ALT_F2H_FN_MOD_RD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_F2H_FN_MOD_RD register field. */ +#define ALT_F2H_FN_MOD_RD_RESET 0x0 +/* Extracts the ALT_F2H_FN_MOD_RD field value from a register. */ +#define ALT_F2H_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_F2H_FN_MOD_RD register field value suitable for setting the register. */ +#define ALT_F2H_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : wr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_F2H_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions + * ALT_F2H_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_F2H_FN_MOD_WR + * + * Multiple outstanding write transactions + */ +#define ALT_F2H_FN_MOD_WR_E_MULT 0x0 +/* + * Enumerated value for register field ALT_F2H_FN_MOD_WR + * + * Only a single outstanding write transaction + */ +#define ALT_F2H_FN_MOD_WR_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_F2H_FN_MOD_WR register field. */ +#define ALT_F2H_FN_MOD_WR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_F2H_FN_MOD_WR register field. */ +#define ALT_F2H_FN_MOD_WR_MSB 1 +/* The width in bits of the ALT_F2H_FN_MOD_WR register field. */ +#define ALT_F2H_FN_MOD_WR_WIDTH 1 +/* The mask used to set the ALT_F2H_FN_MOD_WR register field value. */ +#define ALT_F2H_FN_MOD_WR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_F2H_FN_MOD_WR register field value. */ +#define ALT_F2H_FN_MOD_WR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_F2H_FN_MOD_WR register field. */ +#define ALT_F2H_FN_MOD_WR_RESET 0x0 +/* Extracts the ALT_F2H_FN_MOD_WR field value from a register. */ +#define ALT_F2H_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_F2H_FN_MOD_WR register field value suitable for setting the register. */ +#define ALT_F2H_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_F2H_FN_MOD. + */ +struct ALT_F2H_FN_MOD_s +{ + uint32_t rd : 1; /* ALT_F2H_FN_MOD_RD */ + uint32_t wr : 1; /* ALT_F2H_FN_MOD_WR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_F2H_FN_MOD. */ +typedef volatile struct ALT_F2H_FN_MOD_s ALT_F2H_FN_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_F2H_FN_MOD register from the beginning of the component. */ +#define ALT_F2H_FN_MOD_OFST 0x108 +/* The address of the ALT_F2H_FN_MOD register. */ +#define ALT_F2H_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_F2H_FN_MOD_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_F2H_SLV_B32. + */ +struct ALT_F2H_SLV_B32_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile ALT_F2H_FN_MOD2_t fn_mod2; /* ALT_F2H_FN_MOD2 */ + volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */ + volatile ALT_F2H_FN_MOD_t fn_mod; /* ALT_F2H_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_F2H_SLV_B32. */ +typedef volatile struct ALT_F2H_SLV_B32_s ALT_F2H_SLV_B32_t; +/* The struct declaration for the raw register contents of register group ALT_F2H_SLV_B32. */ +struct ALT_F2H_SLV_B32_raw_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile uint32_t fn_mod2; /* ALT_F2H_FN_MOD2 */ + volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_F2H_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_F2H_SLV_B32. */ +typedef volatile struct ALT_F2H_SLV_B32_raw_s ALT_F2H_SLV_B32_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : 128-bit Slave - ALT_F2H_SLV_B128 + * 128-bit Slave + * + * Registers associated with the 128-bit AXI slave interface. + * + * These registers are only active when the FPGA2HPS AXI Bridge is configured with + * a 128-bit FPGA AXI slave interface. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_F2H_SLV_B128. + */ +struct ALT_F2H_SLV_B128_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile ALT_F2H_FN_MOD2_t fn_mod2; /* ALT_F2H_FN_MOD2 */ + volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */ + volatile ALT_F2H_FN_MOD_t fn_mod; /* ALT_F2H_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_F2H_SLV_B128. */ +typedef volatile struct ALT_F2H_SLV_B128_s ALT_F2H_SLV_B128_t; +/* The struct declaration for the raw register contents of register group ALT_F2H_SLV_B128. */ +struct ALT_F2H_SLV_B128_raw_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile uint32_t fn_mod2; /* ALT_F2H_FN_MOD2 */ + volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_F2H_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_F2H_SLV_B128. */ +typedef volatile struct ALT_F2H_SLV_B128_raw_s ALT_F2H_SLV_B128_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_F2H_SLVGRP. + */ +struct ALT_F2H_SLVGRP_s +{ + volatile ALT_F2H_SLV_B32_t slavegrp_b32; /* ALT_F2H_SLV_B32 */ + volatile uint32_t _pad_0x10c_0x1fff[1981]; /* *UNDEFINED* */ + volatile ALT_F2H_SLV_B128_t slavegrp_b128; /* ALT_F2H_SLV_B128 */ +}; + +/* The typedef declaration for register group ALT_F2H_SLVGRP. */ +typedef volatile struct ALT_F2H_SLVGRP_s ALT_F2H_SLVGRP_t; +/* The struct declaration for the raw register contents of register group ALT_F2H_SLVGRP. */ +struct ALT_F2H_SLVGRP_raw_s +{ + volatile ALT_F2H_SLV_B32_raw_t slavegrp_b32; /* ALT_F2H_SLV_B32 */ + volatile uint32_t _pad_0x10c_0x1fff[1981]; /* *UNDEFINED* */ + volatile ALT_F2H_SLV_B128_raw_t slavegrp_b128; /* ALT_F2H_SLV_B128 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_F2H_SLVGRP. */ +typedef volatile struct ALT_F2H_SLVGRP_raw_s ALT_F2H_SLVGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_F2H. + */ +struct ALT_F2H_s +{ + volatile uint32_t _pad_0x0_0xfff[1024]; /* *UNDEFINED* */ + volatile ALT_F2H_IDGRP_t idgrp; /* ALT_F2H_IDGRP */ + volatile uint32_t _pad_0x2000_0x41fff[65536]; /* *UNDEFINED* */ + volatile ALT_F2H_SLVGRP_t slavegrp; /* ALT_F2H_SLVGRP */ + volatile uint32_t _pad_0x4410c_0x80000[61373]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_F2H. */ +typedef volatile struct ALT_F2H_s ALT_F2H_t; +/* The struct declaration for the raw register contents of register group ALT_F2H. */ +struct ALT_F2H_raw_s +{ + volatile uint32_t _pad_0x0_0xfff[1024]; /* *UNDEFINED* */ + volatile ALT_F2H_IDGRP_raw_t idgrp; /* ALT_F2H_IDGRP */ + volatile uint32_t _pad_0x2000_0x41fff[65536]; /* *UNDEFINED* */ + volatile ALT_F2H_SLVGRP_raw_t slavegrp; /* ALT_F2H_SLVGRP */ + volatile uint32_t _pad_0x4410c_0x80000[61373]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_F2H. */ +typedef volatile struct ALT_F2H_raw_s ALT_F2H_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_F2H_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_fpgamgr.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_fpgamgr.h new file mode 100644 index 000000000..3b2d79152 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_fpgamgr.h @@ -0,0 +1,7090 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_FPGAMGR */ + +#ifndef __ALTERA_ALT_FPGAMGR_H__ +#define __ALTERA_ALT_FPGAMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : FPGA Manager Module - ALT_FPGAMGR + * FPGA Manager Module + * + * Registers in the FPGA Manager module accessible via its APB slave + * + */ +/* + * Register : Status Register - stat + * + * Provides status fields for software for the FPGA Manager. + * + * The Mode field tells software what configuration phase the FPGA currently is in. + * For regular configuration through the PINs or through the HPS, these states map + * directly to customer configuration documentation. + * + * For Configuration Via PCI Express (CVP), the IOCSR configuration is done through + * the PINS or through HPS. Then the complete configuration is done through the + * PCI Express Bus. When CVP is being done, InitPhase indicates only IOCSR + * configuration has completed. CVP_CONF_DONE is available in the CB Monitor for + * observation by software. + * + * The MSEL field provides a read only register for software to read the MSEL value + * driven from the external pins. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [2:0] | RW | 0x5 | Mode + * [7:3] | R | 0x8 | MSEL + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mode - mode + * + * Reports FPGA state + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:--------------------------------------------- + * ALT_FPGAMGR_STAT_MOD_E_FPGAOFF | 0x0 | FPGA Powered Off + * ALT_FPGAMGR_STAT_MOD_E_RSTPHASE | 0x1 | FPGA in Reset Phase + * ALT_FPGAMGR_STAT_MOD_E_CFGPHASE | 0x2 | FPGA in Configuration Phase + * ALT_FPGAMGR_STAT_MOD_E_INITPHASE | 0x3 | FPGA in Initialization Phase. In CVP + * : | | configuration, this state indicates IO + * : | | configuration has completed. + * ALT_FPGAMGR_STAT_MOD_E_USERMOD | 0x4 | FPGA in User Mode + * ALT_FPGAMGR_STAT_MOD_E_UNKNOWN | 0x5 | FPGA state has not yet been determined. This + * : | | only occurs briefly after reset. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MOD + * + * FPGA Powered Off + */ +#define ALT_FPGAMGR_STAT_MOD_E_FPGAOFF 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MOD + * + * FPGA in Reset Phase + */ +#define ALT_FPGAMGR_STAT_MOD_E_RSTPHASE 0x1 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MOD + * + * FPGA in Configuration Phase + */ +#define ALT_FPGAMGR_STAT_MOD_E_CFGPHASE 0x2 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MOD + * + * FPGA in Initialization Phase. In CVP configuration, this state indicates IO + * configuration has completed. + */ +#define ALT_FPGAMGR_STAT_MOD_E_INITPHASE 0x3 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MOD + * + * FPGA in User Mode + */ +#define ALT_FPGAMGR_STAT_MOD_E_USERMOD 0x4 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MOD + * + * FPGA state has not yet been determined. This only occurs briefly after reset. + */ +#define ALT_FPGAMGR_STAT_MOD_E_UNKNOWN 0x5 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_STAT_MOD register field. */ +#define ALT_FPGAMGR_STAT_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_STAT_MOD register field. */ +#define ALT_FPGAMGR_STAT_MOD_MSB 2 +/* The width in bits of the ALT_FPGAMGR_STAT_MOD register field. */ +#define ALT_FPGAMGR_STAT_MOD_WIDTH 3 +/* The mask used to set the ALT_FPGAMGR_STAT_MOD register field value. */ +#define ALT_FPGAMGR_STAT_MOD_SET_MSK 0x00000007 +/* The mask used to clear the ALT_FPGAMGR_STAT_MOD register field value. */ +#define ALT_FPGAMGR_STAT_MOD_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_FPGAMGR_STAT_MOD register field. */ +#define ALT_FPGAMGR_STAT_MOD_RESET 0x5 +/* Extracts the ALT_FPGAMGR_STAT_MOD field value from a register. */ +#define ALT_FPGAMGR_STAT_MOD_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_FPGAMGR_STAT_MOD register field value suitable for setting the register. */ +#define ALT_FPGAMGR_STAT_MOD_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : MSEL - msel + * + * This read-only field allows software to observe the MSEL inputs from the device + * pins. The MSEL pins define the FPGA configuration mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_NOAES_NODC | 0x0 | 16-bit Passive Parallel with Fast Power on Reset + * : | | Delay; No AES Encryption; No Data Compression. + * : | | CDRATIO must be programmed to x1 + * ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AES_NODC | 0x1 | 16-bit Passive Parallel with Fast Power on Reset + * : | | Delay; With AES Encryption; No Data Compression. + * : | | CDRATIO must be programmed to x4 + * ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AESOPT_DC | 0x2 | 16-bit Passive Parallel with Fast Power on Reset + * : | | Delay; AES Optional; With Data Compression. + * : | | CDRATIO must be programmed to x8 + * ALT_FPGAMGR_STAT_MSEL_E_RSVD3 | 0x3 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_NOAES_NODC | 0x4 | 16-bit Passive Parallel with Slow Power on Reset + * : | | Delay; No AES Encryption; No Data Compression. + * : | | CDRATIO must be programmed to x1 + * ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AES_NODC | 0x5 | 16-bit Passive Parallel with Slow Power on Reset + * : | | Delay; With AES Encryption; No Data Compression. + * : | | CDRATIO must be programmed to x4 + * ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AESOPT_DC | 0x6 | 16-bit Passive Parallel with Slow Power on Reset + * : | | Delay; AES Optional; With Data Compression. + * : | | CDRATIO must be programmed to x8 + * ALT_FPGAMGR_STAT_MSEL_E_RSVD7 | 0x7 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_NOAES_NODC | 0x8 | 32-bit Passive Parallel with Fast Power on Reset + * : | | Delay; No AES Encryption; No Data Compression. + * : | | CDRATIO must be programmed to x1 + * ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AES_NODC | 0x9 | 32-bit Passive Parallel with Fast Power on Reset + * : | | Delay; With AES Encryption; No Data Compression. + * : | | CDRATIO must be programmed to x4 + * ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AESOPT_DC | 0xa | 32-bit Passive Parallel with Fast Power on Reset + * : | | Delay; AES Optional; With Data Compression. + * : | | CDRATIO must be programmed to x8 + * ALT_FPGAMGR_STAT_MSEL_E_RSVD11 | 0xb | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_NOAES_NODC | 0xc | 32-bit Passive Parallel with Slow Power on Reset + * : | | Delay; No AES Encryption; No Data Compression. + * : | | CDRATIO must be programmed to x1 + * ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AES_NODC | 0xd | 32-bit Passive Parallel with Slow Power on Reset + * : | | Delay; With AES Encryption; No Data Compression. + * : | | CDRATIO must be programmed to x4 + * ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AESOPT_DC | 0xe | 32-bit Passive Parallel with Slow Power on Reset + * : | | Delay; AES Optional; With Data Compression. + * : | | CDRATIO must be programmed to x8 + * ALT_FPGAMGR_STAT_MSEL_E_RSVD15 | 0xf | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD16 | 0x10 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD17 | 0x11 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD18 | 0x12 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD19 | 0x13 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD20 | 0x14 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD21 | 0x15 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD22 | 0x16 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD23 | 0x17 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD24 | 0x18 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD25 | 0x19 | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD26 | 0x1a | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD27 | 0x1b | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD28 | 0x1c | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD29 | 0x1d | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD30 | 0x1e | Reserved + * ALT_FPGAMGR_STAT_MSEL_E_RSVD31 | 0x1f | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 16-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No + * Data Compression. + * + * CDRATIO must be programmed to x1 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_NOAES_NODC 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 16-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No + * Data Compression. + * + * CDRATIO must be programmed to x4 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AES_NODC 0x1 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 16-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data + * Compression. + * + * CDRATIO must be programmed to x8 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AESOPT_DC 0x2 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD3 0x3 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 16-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No + * Data Compression. + * + * CDRATIO must be programmed to x1 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_NOAES_NODC 0x4 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 16-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No + * Data Compression. + * + * CDRATIO must be programmed to x4 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AES_NODC 0x5 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 16-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data + * Compression. + * + * CDRATIO must be programmed to x8 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AESOPT_DC 0x6 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD7 0x7 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 32-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No + * Data Compression. + * + * CDRATIO must be programmed to x1 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_NOAES_NODC 0x8 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 32-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No + * Data Compression. + * + * CDRATIO must be programmed to x4 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AES_NODC 0x9 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 32-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data + * Compression. + * + * CDRATIO must be programmed to x8 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AESOPT_DC 0xa +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD11 0xb +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 32-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No + * Data Compression. + * + * CDRATIO must be programmed to x1 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_NOAES_NODC 0xc +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 32-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No + * Data Compression. + * + * CDRATIO must be programmed to x4 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AES_NODC 0xd +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * 32-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data + * Compression. + * + * CDRATIO must be programmed to x8 + */ +#define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AESOPT_DC 0xe +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD15 0xf +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD16 0x10 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD17 0x11 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD18 0x12 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD19 0x13 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD20 0x14 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD21 0x15 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD22 0x16 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD23 0x17 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD24 0x18 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD25 0x19 +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD26 0x1a +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD27 0x1b +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD28 0x1c +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD29 0x1d +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD30 0x1e +/* + * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL + * + * Reserved + */ +#define ALT_FPGAMGR_STAT_MSEL_E_RSVD31 0x1f + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_STAT_MSEL register field. */ +#define ALT_FPGAMGR_STAT_MSEL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_STAT_MSEL register field. */ +#define ALT_FPGAMGR_STAT_MSEL_MSB 7 +/* The width in bits of the ALT_FPGAMGR_STAT_MSEL register field. */ +#define ALT_FPGAMGR_STAT_MSEL_WIDTH 5 +/* The mask used to set the ALT_FPGAMGR_STAT_MSEL register field value. */ +#define ALT_FPGAMGR_STAT_MSEL_SET_MSK 0x000000f8 +/* The mask used to clear the ALT_FPGAMGR_STAT_MSEL register field value. */ +#define ALT_FPGAMGR_STAT_MSEL_CLR_MSK 0xffffff07 +/* The reset value of the ALT_FPGAMGR_STAT_MSEL register field. */ +#define ALT_FPGAMGR_STAT_MSEL_RESET 0x8 +/* Extracts the ALT_FPGAMGR_STAT_MSEL field value from a register. */ +#define ALT_FPGAMGR_STAT_MSEL_GET(value) (((value) & 0x000000f8) >> 3) +/* Produces a ALT_FPGAMGR_STAT_MSEL register field value suitable for setting the register. */ +#define ALT_FPGAMGR_STAT_MSEL_SET(value) (((value) << 3) & 0x000000f8) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_FPGAMGR_STAT. + */ +struct ALT_FPGAMGR_STAT_s +{ + uint32_t mode : 3; /* Mode */ + const uint32_t msel : 5; /* MSEL */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_FPGAMGR_STAT. */ +typedef volatile struct ALT_FPGAMGR_STAT_s ALT_FPGAMGR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_FPGAMGR_STAT register from the beginning of the component. */ +#define ALT_FPGAMGR_STAT_OFST 0x0 + +/* + * Register : Control Register - ctrl + * + * Allows HPS to control FPGA configuration. + * + * The NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields drive signals to the FPGA + * Control Block that are logically ORed into their respective pins. These signals + * are always driven independent of the value of EN. The polarity of the + * NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields is inverted relative to their + * associated pins. + * + * The MSEL (external pins), CDRATIO and CFGWDTH signals determine the mode of + * operation for Normal Configuration. For Partial Reconfiguration, CDRATIO is used + * to set the appropriate clock to data ratio, and CFGWDTH should always be set to + * 16-bit Passive Parallel. + * + * AXICFGEN is used to enable transfer of configuration data by enabling or + * disabling DCLK during data transfers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | RW | 0x0 | Enable + * [1] | RW | 0x0 | nCE + * [2] | RW | 0x0 | nCONFIG Pull-Down + * [3] | RW | 0x0 | nSTATUS Pull-Down + * [4] | RW | 0x0 | CONF_DONE Pull-Down + * [5] | RW | 0x0 | Partial Reconfiguration + * [7:6] | RW | 0x0 | CD Ratio + * [8] | RW | 0x0 | AXI Configuration Enable + * [9] | RW | 0x1 | Configuration Data Width + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable - en + * + * Controls whether the FPGA configuration pins or HPS FPGA Manager drive + * configuration inputs to the CB. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_FPGAMGR_CTL_EN_E_FPGA_PINS_CTL_CFG | 0x0 | FPGA configuration pins drive configuration + * : | | inputs to the CB. Used when FPGA is configured + * : | | by means other than the HPS. + * ALT_FPGAMGR_CTL_EN_E_FPGAMGR_CTLS_CFG | 0x1 | FPGA Manager drives configuration inputs to the + * : | | CB. Used when HPS configures the FPGA. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_EN + * + * FPGA configuration pins drive configuration inputs to the CB. Used when FPGA is + * configured by means other than the HPS. + */ +#define ALT_FPGAMGR_CTL_EN_E_FPGA_PINS_CTL_CFG 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_EN + * + * FPGA Manager drives configuration inputs to the CB. Used when HPS configures the + * FPGA. + */ +#define ALT_FPGAMGR_CTL_EN_E_FPGAMGR_CTLS_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_EN register field. */ +#define ALT_FPGAMGR_CTL_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_EN register field. */ +#define ALT_FPGAMGR_CTL_EN_MSB 0 +/* The width in bits of the ALT_FPGAMGR_CTL_EN register field. */ +#define ALT_FPGAMGR_CTL_EN_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_CTL_EN register field value. */ +#define ALT_FPGAMGR_CTL_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_FPGAMGR_CTL_EN register field value. */ +#define ALT_FPGAMGR_CTL_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_FPGAMGR_CTL_EN register field. */ +#define ALT_FPGAMGR_CTL_EN_RESET 0x0 +/* Extracts the ALT_FPGAMGR_CTL_EN field value from a register. */ +#define ALT_FPGAMGR_CTL_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_FPGAMGR_CTL_EN register field value suitable for setting the register. */ +#define ALT_FPGAMGR_CTL_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : nCE - nce + * + * This field drives the active-low Chip Enable (nCE) signal to the CB. It should + * be set to 0 (configuration enabled) before CTRL.EN is set. + * + * This field only effects the FPGA if CTRL.EN is 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------------------ + * ALT_FPGAMGR_CTL_NCE_E_CFG_END | 0x0 | Configuration is enabled. The nCE to the CB is + * : | | driven to 0. + * ALT_FPGAMGR_CTL_NCE_E_CFG_DISD | 0x1 | Configuration is disabled. The nCE to the CB is + * : | | driven to 1. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_NCE + * + * Configuration is enabled. The nCE to the CB is driven to 0. + */ +#define ALT_FPGAMGR_CTL_NCE_E_CFG_END 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_NCE + * + * Configuration is disabled. The nCE to the CB is driven to 1. + */ +#define ALT_FPGAMGR_CTL_NCE_E_CFG_DISD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_NCE register field. */ +#define ALT_FPGAMGR_CTL_NCE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_NCE register field. */ +#define ALT_FPGAMGR_CTL_NCE_MSB 1 +/* The width in bits of the ALT_FPGAMGR_CTL_NCE register field. */ +#define ALT_FPGAMGR_CTL_NCE_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_CTL_NCE register field value. */ +#define ALT_FPGAMGR_CTL_NCE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_FPGAMGR_CTL_NCE register field value. */ +#define ALT_FPGAMGR_CTL_NCE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_FPGAMGR_CTL_NCE register field. */ +#define ALT_FPGAMGR_CTL_NCE_RESET 0x0 +/* Extracts the ALT_FPGAMGR_CTL_NCE field value from a register. */ +#define ALT_FPGAMGR_CTL_NCE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_FPGAMGR_CTL_NCE register field value suitable for setting the register. */ +#define ALT_FPGAMGR_CTL_NCE_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : nCONFIG Pull-Down - nconfigpull + * + * The nCONFIG input is used to put the FPGA into its reset phase. If the FPGA was + * configured, its operation stops and it will have to be configured again to start + * operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------- + * ALT_FPGAMGR_CTL_NCFGPULL_E_DONT_PULLDOWN | 0x0 | Don't pull-down nCONFIG input to the CB. + * ALT_FPGAMGR_CTL_NCFGPULL_E_PULLDOWN | 0x1 | Pull-down nCONFIG input to the CB. This puts the + * : | | FPGA in reset phase and restarts configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_NCFGPULL + * + * Don't pull-down nCONFIG input to the CB. + */ +#define ALT_FPGAMGR_CTL_NCFGPULL_E_DONT_PULLDOWN 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_NCFGPULL + * + * Pull-down nCONFIG input to the CB. This puts the FPGA in reset phase and + * restarts configuration. + */ +#define ALT_FPGAMGR_CTL_NCFGPULL_E_PULLDOWN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_NCFGPULL register field. */ +#define ALT_FPGAMGR_CTL_NCFGPULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_NCFGPULL register field. */ +#define ALT_FPGAMGR_CTL_NCFGPULL_MSB 2 +/* The width in bits of the ALT_FPGAMGR_CTL_NCFGPULL register field. */ +#define ALT_FPGAMGR_CTL_NCFGPULL_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_CTL_NCFGPULL register field value. */ +#define ALT_FPGAMGR_CTL_NCFGPULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_FPGAMGR_CTL_NCFGPULL register field value. */ +#define ALT_FPGAMGR_CTL_NCFGPULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_FPGAMGR_CTL_NCFGPULL register field. */ +#define ALT_FPGAMGR_CTL_NCFGPULL_RESET 0x0 +/* Extracts the ALT_FPGAMGR_CTL_NCFGPULL field value from a register. */ +#define ALT_FPGAMGR_CTL_NCFGPULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_FPGAMGR_CTL_NCFGPULL register field value suitable for setting the register. */ +#define ALT_FPGAMGR_CTL_NCFGPULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : nSTATUS Pull-Down - nstatuspull + * + * Pulls down nSTATUS input to the CB + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------------------- + * ALT_FPGAMGR_CTL_NSTATPULL_E_DONT_PULLDOWN | 0x0 | Don't pull-down nSTATUS input to the CB. + * ALT_FPGAMGR_CTL_NSTATPULL_E_PULLDOWN | 0x1 | Pull-down nSTATUS input to the CB. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_NSTATPULL + * + * Don't pull-down nSTATUS input to the CB. + */ +#define ALT_FPGAMGR_CTL_NSTATPULL_E_DONT_PULLDOWN 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_NSTATPULL + * + * Pull-down nSTATUS input to the CB. + */ +#define ALT_FPGAMGR_CTL_NSTATPULL_E_PULLDOWN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_NSTATPULL register field. */ +#define ALT_FPGAMGR_CTL_NSTATPULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_NSTATPULL register field. */ +#define ALT_FPGAMGR_CTL_NSTATPULL_MSB 3 +/* The width in bits of the ALT_FPGAMGR_CTL_NSTATPULL register field. */ +#define ALT_FPGAMGR_CTL_NSTATPULL_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_CTL_NSTATPULL register field value. */ +#define ALT_FPGAMGR_CTL_NSTATPULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_FPGAMGR_CTL_NSTATPULL register field value. */ +#define ALT_FPGAMGR_CTL_NSTATPULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_FPGAMGR_CTL_NSTATPULL register field. */ +#define ALT_FPGAMGR_CTL_NSTATPULL_RESET 0x0 +/* Extracts the ALT_FPGAMGR_CTL_NSTATPULL field value from a register. */ +#define ALT_FPGAMGR_CTL_NSTATPULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_FPGAMGR_CTL_NSTATPULL register field value suitable for setting the register. */ +#define ALT_FPGAMGR_CTL_NSTATPULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : CONF_DONE Pull-Down - confdonepull + * + * Pulls down CONF_DONE input to the CB + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_FPGAMGR_CTL_CONFDONEPULL_E_DONT_PULLDOWN | 0x0 | Don't pull-down CONF_DONE input to the CB. + * ALT_FPGAMGR_CTL_CONFDONEPULL_E_PULLDOWN | 0x1 | Pull-down CONF_DONE input to the CB. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_CONFDONEPULL + * + * Don't pull-down CONF_DONE input to the CB. + */ +#define ALT_FPGAMGR_CTL_CONFDONEPULL_E_DONT_PULLDOWN 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_CONFDONEPULL + * + * Pull-down CONF_DONE input to the CB. + */ +#define ALT_FPGAMGR_CTL_CONFDONEPULL_E_PULLDOWN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_CONFDONEPULL register field. */ +#define ALT_FPGAMGR_CTL_CONFDONEPULL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_CONFDONEPULL register field. */ +#define ALT_FPGAMGR_CTL_CONFDONEPULL_MSB 4 +/* The width in bits of the ALT_FPGAMGR_CTL_CONFDONEPULL register field. */ +#define ALT_FPGAMGR_CTL_CONFDONEPULL_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_CTL_CONFDONEPULL register field value. */ +#define ALT_FPGAMGR_CTL_CONFDONEPULL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_FPGAMGR_CTL_CONFDONEPULL register field value. */ +#define ALT_FPGAMGR_CTL_CONFDONEPULL_CLR_MSK 0xffffffef +/* The reset value of the ALT_FPGAMGR_CTL_CONFDONEPULL register field. */ +#define ALT_FPGAMGR_CTL_CONFDONEPULL_RESET 0x0 +/* Extracts the ALT_FPGAMGR_CTL_CONFDONEPULL field value from a register. */ +#define ALT_FPGAMGR_CTL_CONFDONEPULL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_FPGAMGR_CTL_CONFDONEPULL register field value suitable for setting the register. */ +#define ALT_FPGAMGR_CTL_CONFDONEPULL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Partial Reconfiguration - prreq + * + * This field is used to assert PR_REQUEST to request partial reconfiguration while + * the FPGA is in User Mode. This field only affects the FPGA if CTRL.EN is 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_FPGAMGR_CTL_PRREQ_E_DEASSERT | 0x0 | De-assert PR_REQUEST (driven to 0). + * ALT_FPGAMGR_CTL_PRREQ_E_ASSERT | 0x1 | Assert PR_REQUEST (driven to 1). + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_PRREQ + * + * De-assert PR_REQUEST (driven to 0). + */ +#define ALT_FPGAMGR_CTL_PRREQ_E_DEASSERT 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_PRREQ + * + * Assert PR_REQUEST (driven to 1). + */ +#define ALT_FPGAMGR_CTL_PRREQ_E_ASSERT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_PRREQ register field. */ +#define ALT_FPGAMGR_CTL_PRREQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_PRREQ register field. */ +#define ALT_FPGAMGR_CTL_PRREQ_MSB 5 +/* The width in bits of the ALT_FPGAMGR_CTL_PRREQ register field. */ +#define ALT_FPGAMGR_CTL_PRREQ_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_CTL_PRREQ register field value. */ +#define ALT_FPGAMGR_CTL_PRREQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_FPGAMGR_CTL_PRREQ register field value. */ +#define ALT_FPGAMGR_CTL_PRREQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_FPGAMGR_CTL_PRREQ register field. */ +#define ALT_FPGAMGR_CTL_PRREQ_RESET 0x0 +/* Extracts the ALT_FPGAMGR_CTL_PRREQ field value from a register. */ +#define ALT_FPGAMGR_CTL_PRREQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_FPGAMGR_CTL_PRREQ register field value suitable for setting the register. */ +#define ALT_FPGAMGR_CTL_PRREQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : CD Ratio - cdratio + * + * This field controls the Clock to Data Ratio (CDRATIO) for Normal Configuration + * and Partial Reconfiguration data transfer from the AXI Slave to the FPGA. + * + * For Normal Configuration, the value in this field must be set to be consistent + * to the implied CD ratio of the MSEL setting. + * + * For Partial Reconfiguration, the value in this field must be set to the same + * clock to data ratio in the options bits in the Normal Configuration file. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------- + * ALT_FPGAMGR_CTL_CDRATIO_E_X1 | 0x0 | CDRATIO of 1 + * ALT_FPGAMGR_CTL_CDRATIO_E_X2 | 0x1 | CDRATIO of 2 + * ALT_FPGAMGR_CTL_CDRATIO_E_X4 | 0x2 | CDRATIO of 4 + * ALT_FPGAMGR_CTL_CDRATIO_E_X8 | 0x3 | CDRATIO of 8 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO + * + * CDRATIO of 1 + */ +#define ALT_FPGAMGR_CTL_CDRATIO_E_X1 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO + * + * CDRATIO of 2 + */ +#define ALT_FPGAMGR_CTL_CDRATIO_E_X2 0x1 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO + * + * CDRATIO of 4 + */ +#define ALT_FPGAMGR_CTL_CDRATIO_E_X4 0x2 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO + * + * CDRATIO of 8 + */ +#define ALT_FPGAMGR_CTL_CDRATIO_E_X8 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_CDRATIO register field. */ +#define ALT_FPGAMGR_CTL_CDRATIO_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_CDRATIO register field. */ +#define ALT_FPGAMGR_CTL_CDRATIO_MSB 7 +/* The width in bits of the ALT_FPGAMGR_CTL_CDRATIO register field. */ +#define ALT_FPGAMGR_CTL_CDRATIO_WIDTH 2 +/* The mask used to set the ALT_FPGAMGR_CTL_CDRATIO register field value. */ +#define ALT_FPGAMGR_CTL_CDRATIO_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_FPGAMGR_CTL_CDRATIO register field value. */ +#define ALT_FPGAMGR_CTL_CDRATIO_CLR_MSK 0xffffff3f +/* The reset value of the ALT_FPGAMGR_CTL_CDRATIO register field. */ +#define ALT_FPGAMGR_CTL_CDRATIO_RESET 0x0 +/* Extracts the ALT_FPGAMGR_CTL_CDRATIO field value from a register. */ +#define ALT_FPGAMGR_CTL_CDRATIO_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_FPGAMGR_CTL_CDRATIO register field value suitable for setting the register. */ +#define ALT_FPGAMGR_CTL_CDRATIO_SET(value) (((value) << 6) & 0x000000c0) + +/* + * Field : AXI Configuration Enable - axicfgen + * + * There are strict SW initialization steps for configuration, partial + * configuration and error cases. When SW is sending configuration files, this bit + * must be set before the file is transferred on the AXI bus. This bit enables the + * DCLK during the AXI configuration data transfers. + * + * Note, the AXI and configuration datapaths remain active irregardless of the + * state of this bit. Simply, if the AXI slave is enabled, the DCLK to the CB + * will be active. If disabled, the DCLK to the CB will not be active. So AXI + * transfers destined to the FPGA Manager when AXIEN is 0, will complete normally + * from the HPS perspective. + * + * This field only affects the FPGA if CTRL.EN is 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:--------------------------------------------- + * ALT_FPGAMGR_CTL_AXICFGEN_E_DISD | 0x0 | Incoming AXI data transfers will be ignored. + * : | | DCLK will not toggle during data transfer. + * ALT_FPGAMGR_CTL_AXICFGEN_E_END | 0x1 | AXI data transfer to CB is active. DCLK will + * : | | toggle during data transfer. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_AXICFGEN + * + * Incoming AXI data transfers will be ignored. DCLK will not toggle during data + * transfer. + */ +#define ALT_FPGAMGR_CTL_AXICFGEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_AXICFGEN + * + * AXI data transfer to CB is active. DCLK will toggle during data transfer. + */ +#define ALT_FPGAMGR_CTL_AXICFGEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_AXICFGEN register field. */ +#define ALT_FPGAMGR_CTL_AXICFGEN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_AXICFGEN register field. */ +#define ALT_FPGAMGR_CTL_AXICFGEN_MSB 8 +/* The width in bits of the ALT_FPGAMGR_CTL_AXICFGEN register field. */ +#define ALT_FPGAMGR_CTL_AXICFGEN_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_CTL_AXICFGEN register field value. */ +#define ALT_FPGAMGR_CTL_AXICFGEN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_FPGAMGR_CTL_AXICFGEN register field value. */ +#define ALT_FPGAMGR_CTL_AXICFGEN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_FPGAMGR_CTL_AXICFGEN register field. */ +#define ALT_FPGAMGR_CTL_AXICFGEN_RESET 0x0 +/* Extracts the ALT_FPGAMGR_CTL_AXICFGEN field value from a register. */ +#define ALT_FPGAMGR_CTL_AXICFGEN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_FPGAMGR_CTL_AXICFGEN register field value suitable for setting the register. */ +#define ALT_FPGAMGR_CTL_AXICFGEN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Configuration Data Width - cfgwdth + * + * This field determines the Configuration Passive Parallel data bus width when HPS + * configures the FPGA. Only 32-bit Passive Parallel or 16-bit Passive Parallel + * are supported. + * + * When HPS does Normal Configuration, configuration should use 32-bit Passive + * Parallel Mode. The external pins MSEL must be set appropriately for the + * configuration selected. + * + * For Partial Reconfiguration, 16-bit Passive Parallel must be used. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------ + * ALT_FPGAMGR_CTL_CFGWDTH_E_PPX16 | 0x0 | 16-bit Passive Parallel + * ALT_FPGAMGR_CTL_CFGWDTH_E_PPX32 | 0x1 | 32-bit Passive Parallel + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_CFGWDTH + * + * 16-bit Passive Parallel + */ +#define ALT_FPGAMGR_CTL_CFGWDTH_E_PPX16 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_CTL_CFGWDTH + * + * 32-bit Passive Parallel + */ +#define ALT_FPGAMGR_CTL_CFGWDTH_E_PPX32 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_CFGWDTH register field. */ +#define ALT_FPGAMGR_CTL_CFGWDTH_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_CFGWDTH register field. */ +#define ALT_FPGAMGR_CTL_CFGWDTH_MSB 9 +/* The width in bits of the ALT_FPGAMGR_CTL_CFGWDTH register field. */ +#define ALT_FPGAMGR_CTL_CFGWDTH_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_CTL_CFGWDTH register field value. */ +#define ALT_FPGAMGR_CTL_CFGWDTH_SET_MSK 0x00000200 +/* The mask used to clear the ALT_FPGAMGR_CTL_CFGWDTH register field value. */ +#define ALT_FPGAMGR_CTL_CFGWDTH_CLR_MSK 0xfffffdff +/* The reset value of the ALT_FPGAMGR_CTL_CFGWDTH register field. */ +#define ALT_FPGAMGR_CTL_CFGWDTH_RESET 0x1 +/* Extracts the ALT_FPGAMGR_CTL_CFGWDTH field value from a register. */ +#define ALT_FPGAMGR_CTL_CFGWDTH_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_FPGAMGR_CTL_CFGWDTH register field value suitable for setting the register. */ +#define ALT_FPGAMGR_CTL_CFGWDTH_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_FPGAMGR_CTL. + */ +struct ALT_FPGAMGR_CTL_s +{ + uint32_t en : 1; /* Enable */ + uint32_t nce : 1; /* nCE */ + uint32_t nconfigpull : 1; /* nCONFIG Pull-Down */ + uint32_t nstatuspull : 1; /* nSTATUS Pull-Down */ + uint32_t confdonepull : 1; /* CONF_DONE Pull-Down */ + uint32_t prreq : 1; /* Partial Reconfiguration */ + uint32_t cdratio : 2; /* CD Ratio */ + uint32_t axicfgen : 1; /* AXI Configuration Enable */ + uint32_t cfgwdth : 1; /* Configuration Data Width */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_FPGAMGR_CTL. */ +typedef volatile struct ALT_FPGAMGR_CTL_s ALT_FPGAMGR_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_FPGAMGR_CTL register from the beginning of the component. */ +#define ALT_FPGAMGR_CTL_OFST 0x4 + +/* + * Register : DCLK Count Register - dclkcnt + * + * Used to give software control in enabling DCLK at any time. + * + * SW will need control of the DCLK in specific configuration and partial + * reconfiguration initialization steps to send spurious DCLKs required by the CB. + * SW takes ownership for DCLK during normal configuration, partial + * reconfiguration, error scenerio handshakes including SEU CRC error during + * partial reconfiguration, SW early abort of partial reconfiguration, and + * initializatin phase DCLK driving. + * + * During initialization phase, a configuration image loaded into the FPGA can + * request that DCLK be used as the initialization phase clock instead of the + * default internal oscillator or optionally the CLKUSR pin. In the case that DCLK + * is requested, the DCLKCNT register is used by software to control DCLK during + * the initialization phase. + * + * Software should poll the DCLKSTAT.DCNTDONE write one to clear register to be set + * when the correct number of DCLKs have completed. Software should clear + * DCLKSTAT.DCNTDONE before writing to the DCLKCNT register again. + * + * This field only affects the FPGA if CTRL.EN is 1. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | Count + * + */ +/* + * Field : Count - cnt + * + * Controls DCLK counter. + * + * Software writes a non-zero value into CNT and the FPGA Manager generates the + * specified number of DCLK pulses and decrements COUNT. This register will read + * back the original value written by software. + * + * Software can write CNT at any time. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DCLKCNT_CNT register field. */ +#define ALT_FPGAMGR_DCLKCNT_CNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DCLKCNT_CNT register field. */ +#define ALT_FPGAMGR_DCLKCNT_CNT_MSB 31 +/* The width in bits of the ALT_FPGAMGR_DCLKCNT_CNT register field. */ +#define ALT_FPGAMGR_DCLKCNT_CNT_WIDTH 32 +/* The mask used to set the ALT_FPGAMGR_DCLKCNT_CNT register field value. */ +#define ALT_FPGAMGR_DCLKCNT_CNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_FPGAMGR_DCLKCNT_CNT register field value. */ +#define ALT_FPGAMGR_DCLKCNT_CNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_FPGAMGR_DCLKCNT_CNT register field. */ +#define ALT_FPGAMGR_DCLKCNT_CNT_RESET 0x0 +/* Extracts the ALT_FPGAMGR_DCLKCNT_CNT field value from a register. */ +#define ALT_FPGAMGR_DCLKCNT_CNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_FPGAMGR_DCLKCNT_CNT register field value suitable for setting the register. */ +#define ALT_FPGAMGR_DCLKCNT_CNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_FPGAMGR_DCLKCNT. + */ +struct ALT_FPGAMGR_DCLKCNT_s +{ + uint32_t cnt : 32; /* Count */ +}; + +/* The typedef declaration for register ALT_FPGAMGR_DCLKCNT. */ +typedef volatile struct ALT_FPGAMGR_DCLKCNT_s ALT_FPGAMGR_DCLKCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_FPGAMGR_DCLKCNT register from the beginning of the component. */ +#define ALT_FPGAMGR_DCLKCNT_OFST 0x8 + +/* + * Register : DCLK Status Register - dclkstat + * + * This write one to clear register indicates that the DCLKCNT has counted down to + * zero. The DCLKCNT is used by software to drive spurious DCLKs to the FPGA. + * Software will poll this bit after writing DCLKCNT to know when all of the DCLKs + * have been sent. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | RW | 0x0 | DCLK Count Done + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DCLK Count Done - dcntdone + * + * This bit is write one to clear. This bit gets set after the DCLKCNT has + * counted down to zero (transition from 1 to 0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------- + * ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_NOTDONE | 0x0 | DCLKCNT is still counting down. + * ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE | 0x1 | DCLKCNT is done counting down. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_FPGAMGR_DCLKSTAT_DCNTDONE + * + * DCLKCNT is still counting down. + */ +#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_NOTDONE 0x0 +/* + * Enumerated value for register field ALT_FPGAMGR_DCLKSTAT_DCNTDONE + * + * DCLKCNT is done counting down. + */ +#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */ +#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */ +#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_MSB 0 +/* The width in bits of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */ +#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field value. */ +#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field value. */ +#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */ +#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_RESET 0x0 +/* Extracts the ALT_FPGAMGR_DCLKSTAT_DCNTDONE field value from a register. */ +#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field value suitable for setting the register. */ +#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_FPGAMGR_DCLKSTAT. + */ +struct ALT_FPGAMGR_DCLKSTAT_s +{ + uint32_t dcntdone : 1; /* DCLK Count Done */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_FPGAMGR_DCLKSTAT. */ +typedef volatile struct ALT_FPGAMGR_DCLKSTAT_s ALT_FPGAMGR_DCLKSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_FPGAMGR_DCLKSTAT register from the beginning of the component. */ +#define ALT_FPGAMGR_DCLKSTAT_OFST 0xc + +/* + * Register : General-Purpose Output Register - gpo + * + * Provides a low-latency, low-performance, and simple way to drive general-purpose + * signals to the FPGA fabric. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | Value + * + */ +/* + * Field : Value - value + * + * Drives h2f_gp[31:0] with specified value. When read, returns the current value + * being driven to the FPGA fabric. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_GPO_VALUE register field. */ +#define ALT_FPGAMGR_GPO_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_GPO_VALUE register field. */ +#define ALT_FPGAMGR_GPO_VALUE_MSB 31 +/* The width in bits of the ALT_FPGAMGR_GPO_VALUE register field. */ +#define ALT_FPGAMGR_GPO_VALUE_WIDTH 32 +/* The mask used to set the ALT_FPGAMGR_GPO_VALUE register field value. */ +#define ALT_FPGAMGR_GPO_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_FPGAMGR_GPO_VALUE register field value. */ +#define ALT_FPGAMGR_GPO_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_FPGAMGR_GPO_VALUE register field. */ +#define ALT_FPGAMGR_GPO_VALUE_RESET 0x0 +/* Extracts the ALT_FPGAMGR_GPO_VALUE field value from a register. */ +#define ALT_FPGAMGR_GPO_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_FPGAMGR_GPO_VALUE register field value suitable for setting the register. */ +#define ALT_FPGAMGR_GPO_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_FPGAMGR_GPO. + */ +struct ALT_FPGAMGR_GPO_s +{ + uint32_t value : 32; /* Value */ +}; + +/* The typedef declaration for register ALT_FPGAMGR_GPO. */ +typedef volatile struct ALT_FPGAMGR_GPO_s ALT_FPGAMGR_GPO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_FPGAMGR_GPO register from the beginning of the component. */ +#define ALT_FPGAMGR_GPO_OFST 0x10 + +/* + * Register : General-Purpose Input Register - gpi + * + * Provides a low-latency, low-performance, and simple way to read general-purpose + * signals driven from the FPGA fabric. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | R | Unknown | Value + * + */ +/* + * Field : Value - value + * + * The value being driven from the FPGA fabric on f2h_gp[31:0]. If the FPGA is not + * in User Mode, the value of this field is undefined. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_GPI_VALUE register field. */ +#define ALT_FPGAMGR_GPI_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_GPI_VALUE register field. */ +#define ALT_FPGAMGR_GPI_VALUE_MSB 31 +/* The width in bits of the ALT_FPGAMGR_GPI_VALUE register field. */ +#define ALT_FPGAMGR_GPI_VALUE_WIDTH 32 +/* The mask used to set the ALT_FPGAMGR_GPI_VALUE register field value. */ +#define ALT_FPGAMGR_GPI_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_FPGAMGR_GPI_VALUE register field value. */ +#define ALT_FPGAMGR_GPI_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_FPGAMGR_GPI_VALUE register field is UNKNOWN. */ +#define ALT_FPGAMGR_GPI_VALUE_RESET 0x0 +/* Extracts the ALT_FPGAMGR_GPI_VALUE field value from a register. */ +#define ALT_FPGAMGR_GPI_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_FPGAMGR_GPI_VALUE register field value suitable for setting the register. */ +#define ALT_FPGAMGR_GPI_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_FPGAMGR_GPI. + */ +struct ALT_FPGAMGR_GPI_s +{ + const uint32_t value : 32; /* Value */ +}; + +/* The typedef declaration for register ALT_FPGAMGR_GPI. */ +typedef volatile struct ALT_FPGAMGR_GPI_s ALT_FPGAMGR_GPI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_FPGAMGR_GPI register from the beginning of the component. */ +#define ALT_FPGAMGR_GPI_OFST 0x14 + +/* + * Register : Miscellaneous Input Register - misci + * + * Provides a low-latency, low-performance, and simple way to read specific + * handshaking signals driven from the FPGA fabric. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------- + * [0] | R | Unknown | Boot From FPGA on Failure + * [1] | R | Unknown | Boot From FPGA Ready + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Boot From FPGA on Failure - bootFPGAfail + * + * The value of the f2h_boot_from_fpga_on_failure signal from the FPGA fabric. If + * the FPGA is not in User Mode, the value of this field is undefined. + * + * 1 = Boot ROM will boot from FPGA if boot from normal boot device fails. + * + * 0 = Boot ROM will not boot from FPGA if boot from normal boot device fails. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_MSB 0 +/* The width in bits of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field value. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field value. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field is UNKNOWN. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_RESET 0x0 +/* Extracts the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL field value from a register. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field value suitable for setting the register. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Boot From FPGA Ready - bootFPGArdy + * + * The value of the f2h_boot_from_fpga_ready signal from the FPGA fabric. If the + * FPGA is not in User Mode, the value of this field is undefined. + * + * 1 = FPGA fabric is ready to accept AXI master requests from the HPS2FPGA bridge. + * + * 0 = FPGA fabric is not ready (probably still processing a reset). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_MSB 1 +/* The width in bits of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_WIDTH 1 +/* The mask used to set the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field value. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_SET_MSK 0x00000002 +/* The mask used to clear the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field value. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_CLR_MSK 0xfffffffd +/* The reset value of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field is UNKNOWN. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_RESET 0x0 +/* Extracts the ALT_FPGAMGR_MISCI_BOOTFPGARDY field value from a register. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_FPGAMGR_MISCI_BOOTFPGARDY register field value suitable for setting the register. */ +#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_FPGAMGR_MISCI. + */ +struct ALT_FPGAMGR_MISCI_s +{ + const uint32_t bootFPGAfail : 1; /* Boot From FPGA on Failure */ + const uint32_t bootFPGArdy : 1; /* Boot From FPGA Ready */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_FPGAMGR_MISCI. */ +typedef volatile struct ALT_FPGAMGR_MISCI_s ALT_FPGAMGR_MISCI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_FPGAMGR_MISCI register from the beginning of the component. */ +#define ALT_FPGAMGR_MISCI_OFST 0x18 + +/* + * Register Group : Configuration Monitor (MON) Registers - ALT_MON + * Configuration Monitor (MON) Registers + * + * The Configuration Monitor allows software to poll or be interrupted by changes + * in the FPGA state. The Configuration Monitor is an instantiation of a Synopsys + * GPIO. Only registers relevant to the MON operation are shown. + * + * The GPIO inputs are connected to the following signals:[list][*]nSTATUS - Driven + * to 0 by the FPGA in this device if the FPGA is in Reset Phase or if the FPGA + * detected an error during the Configuration Phase.[*]CONF_DONE - Driven to 0 by + * the FPGA in this device during the Reset Phase and driven to 1 when the FPGA + * Configuration Phase is done.[*]INIT_DONE - Driven to 0 by the FPGA in this + * device during the Configuration Phase and driven to 1 when the FPGA + * Initialization Phase is done.[*]CRC_ERROR - CRC error indicator. A CRC_ERROR + * value of 1 indicates that the FPGA detected a CRC error while in User + * Mode.[*]CVP_CONF_DONE - Configuration via PCIe done indicator. A CVP_CONF_DONE + * value of 1 indicates that CVP is done.[*]PR_READY - Partial reconfiguration + * ready indicator. A PR_READY value of 1 indicates that the FPGA is ready to + * receive partial reconfiguration or external scrubbing data.[*]PR_ERROR - Partial + * reconfiguration error indicator. A PR_ERROR value of 1 indicates that the FPGA + * detected an error during partial reconfiguration or external + * scrubbing.[*]PR_DONE - Partial reconfiguration done indicator. A PR_DONE value + * of 1 indicates partial reconfiguration or external scrubbing is done.[*]nCONFIG + * Pin - Value of the nCONFIG pin. This can be pulled-down by the FPGA in this + * device or logic external to this device connected to the nCONFIG pin. See the + * description of the nCONFIG field in this register to understand when the FPGA in + * this device pulls-down the nCONFIG pin. Logic external to this device pulls-down + * the nCONFIG pin to put the FPGA into the Reset Phase.[*]nSTATUS Pin - Value of + * the nSTATUS pin. This can be pulled-down by the FPGA in this device or logic + * external to this device connected to the nSTATUS pin. See the description of the + * nSTATUS field in this register to understand when the FPGA in this device pulls- + * down the nSTATUS pin. Logic external to this device pulls-down the nSTATUS pin + * during Configuration Phase or Initialization Phase if it detected an + * error.[*]CONF_DONE Pin - Value of the CONF_DONE pin. This can be pulled-down by + * the FPGA in this device or logic external to this device connected to the + * CONF_DONE pin. See the description of the CONF_DONE field in this register to + * understand when the FPGA in this device pulls-down the CONF_DONE pin. See FPGA + * documentation to determine how logic external to this device drives + * CONF_DONE.[*]FPGA_POWER_ON - FPGA powered on indicator + * + * [list][*]0 = FPGA portion of device is powered off.[*]1 = FPGA portion of device + * is powered on.[/list][/list] + * + */ +/* + * Register : Interrupt Enable Register - gpio_inten + * + * Allows each bit of Port A to be configured to generate an interrupt or not. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | Interrupt Enable Field (nSTATUS) + * [1] | RW | 0x0 | Interrupt Enable Field (CONF_DONE) + * [2] | RW | 0x0 | Interrupt Enable Field (INIT_DONE) + * [3] | RW | 0x0 | Interrupt Enable Field (CRC_ERROR) + * [4] | RW | 0x0 | Interrupt Enable Field (CVP_CONF_DONE) + * [5] | RW | 0x0 | Interrupt Enable Field (PR_READY) + * [6] | RW | 0x0 | Interrupt Enable Field (PR_ERROR) + * [7] | RW | 0x0 | Interrupt Enable Field (PR_DONE) + * [8] | RW | 0x0 | Interrupt Enable Field (nCONFIG Pin) + * [9] | RW | 0x0 | Interrupt Enable Field (nSTATUS Pin) + * [10] | RW | 0x0 | Interrupt Enable Field (CONF_DONE Pin) + * [11] | RW | 0x0 | Interrupt Enable Field (FPGA_POWER_ON) + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Enable Field (nSTATUS) - ns + * + * Enables interrupt generation for nSTATUS + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_NS_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_NS_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_NS + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_NS_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_NS + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_NS_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_NS register field. */ +#define ALT_MON_GPIO_INTEN_NS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_NS register field. */ +#define ALT_MON_GPIO_INTEN_NS_MSB 0 +/* The width in bits of the ALT_MON_GPIO_INTEN_NS register field. */ +#define ALT_MON_GPIO_INTEN_NS_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_NS register field value. */ +#define ALT_MON_GPIO_INTEN_NS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_MON_GPIO_INTEN_NS register field value. */ +#define ALT_MON_GPIO_INTEN_NS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_MON_GPIO_INTEN_NS register field. */ +#define ALT_MON_GPIO_INTEN_NS_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_NS field value from a register. */ +#define ALT_MON_GPIO_INTEN_NS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MON_GPIO_INTEN_NS register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_NS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Interrupt Enable Field (CONF_DONE) - cd + * + * Enables interrupt generation for CONF_DONE + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_CD_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_CD_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_CD + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_CD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_CD + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_CD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_CD register field. */ +#define ALT_MON_GPIO_INTEN_CD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_CD register field. */ +#define ALT_MON_GPIO_INTEN_CD_MSB 1 +/* The width in bits of the ALT_MON_GPIO_INTEN_CD register field. */ +#define ALT_MON_GPIO_INTEN_CD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_CD register field value. */ +#define ALT_MON_GPIO_INTEN_CD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_MON_GPIO_INTEN_CD register field value. */ +#define ALT_MON_GPIO_INTEN_CD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_MON_GPIO_INTEN_CD register field. */ +#define ALT_MON_GPIO_INTEN_CD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_CD field value from a register. */ +#define ALT_MON_GPIO_INTEN_CD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_MON_GPIO_INTEN_CD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_CD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Interrupt Enable Field (INIT_DONE) - id + * + * Enables interrupt generation for INIT_DONE + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_ID_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_ID_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_ID + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_ID_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_ID + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_ID_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_ID register field. */ +#define ALT_MON_GPIO_INTEN_ID_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_ID register field. */ +#define ALT_MON_GPIO_INTEN_ID_MSB 2 +/* The width in bits of the ALT_MON_GPIO_INTEN_ID register field. */ +#define ALT_MON_GPIO_INTEN_ID_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_ID register field value. */ +#define ALT_MON_GPIO_INTEN_ID_SET_MSK 0x00000004 +/* The mask used to clear the ALT_MON_GPIO_INTEN_ID register field value. */ +#define ALT_MON_GPIO_INTEN_ID_CLR_MSK 0xfffffffb +/* The reset value of the ALT_MON_GPIO_INTEN_ID register field. */ +#define ALT_MON_GPIO_INTEN_ID_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_ID field value from a register. */ +#define ALT_MON_GPIO_INTEN_ID_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_MON_GPIO_INTEN_ID register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_ID_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Interrupt Enable Field (CRC_ERROR) - crc + * + * Enables interrupt generation for CRC_ERROR + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_CRC_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_CRC_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_CRC + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_CRC_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_CRC + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_CRC_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_CRC register field. */ +#define ALT_MON_GPIO_INTEN_CRC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_CRC register field. */ +#define ALT_MON_GPIO_INTEN_CRC_MSB 3 +/* The width in bits of the ALT_MON_GPIO_INTEN_CRC register field. */ +#define ALT_MON_GPIO_INTEN_CRC_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_CRC register field value. */ +#define ALT_MON_GPIO_INTEN_CRC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_MON_GPIO_INTEN_CRC register field value. */ +#define ALT_MON_GPIO_INTEN_CRC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_MON_GPIO_INTEN_CRC register field. */ +#define ALT_MON_GPIO_INTEN_CRC_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_CRC field value from a register. */ +#define ALT_MON_GPIO_INTEN_CRC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_MON_GPIO_INTEN_CRC register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_CRC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Interrupt Enable Field (CVP_CONF_DONE) - ccd + * + * Enables interrupt generation for CVP_CONF_DONE + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_CCD_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_CCD_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_CCD + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_CCD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_CCD + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_CCD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_CCD register field. */ +#define ALT_MON_GPIO_INTEN_CCD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_CCD register field. */ +#define ALT_MON_GPIO_INTEN_CCD_MSB 4 +/* The width in bits of the ALT_MON_GPIO_INTEN_CCD register field. */ +#define ALT_MON_GPIO_INTEN_CCD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_CCD register field value. */ +#define ALT_MON_GPIO_INTEN_CCD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_MON_GPIO_INTEN_CCD register field value. */ +#define ALT_MON_GPIO_INTEN_CCD_CLR_MSK 0xffffffef +/* The reset value of the ALT_MON_GPIO_INTEN_CCD register field. */ +#define ALT_MON_GPIO_INTEN_CCD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_CCD field value from a register. */ +#define ALT_MON_GPIO_INTEN_CCD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_MON_GPIO_INTEN_CCD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_CCD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Interrupt Enable Field (PR_READY) - prr + * + * Enables interrupt generation for PR_READY + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_PRR_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_PRR_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_PRR + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_PRR_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_PRR + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_PRR_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_PRR register field. */ +#define ALT_MON_GPIO_INTEN_PRR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_PRR register field. */ +#define ALT_MON_GPIO_INTEN_PRR_MSB 5 +/* The width in bits of the ALT_MON_GPIO_INTEN_PRR register field. */ +#define ALT_MON_GPIO_INTEN_PRR_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_PRR register field value. */ +#define ALT_MON_GPIO_INTEN_PRR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_MON_GPIO_INTEN_PRR register field value. */ +#define ALT_MON_GPIO_INTEN_PRR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_MON_GPIO_INTEN_PRR register field. */ +#define ALT_MON_GPIO_INTEN_PRR_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_PRR field value from a register. */ +#define ALT_MON_GPIO_INTEN_PRR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_MON_GPIO_INTEN_PRR register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_PRR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Interrupt Enable Field (PR_ERROR) - pre + * + * Enables interrupt generation for PR_ERROR + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_PRE_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_PRE_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_PRE + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_PRE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_PRE + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_PRE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_PRE register field. */ +#define ALT_MON_GPIO_INTEN_PRE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_PRE register field. */ +#define ALT_MON_GPIO_INTEN_PRE_MSB 6 +/* The width in bits of the ALT_MON_GPIO_INTEN_PRE register field. */ +#define ALT_MON_GPIO_INTEN_PRE_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_PRE register field value. */ +#define ALT_MON_GPIO_INTEN_PRE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_MON_GPIO_INTEN_PRE register field value. */ +#define ALT_MON_GPIO_INTEN_PRE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_MON_GPIO_INTEN_PRE register field. */ +#define ALT_MON_GPIO_INTEN_PRE_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_PRE field value from a register. */ +#define ALT_MON_GPIO_INTEN_PRE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_MON_GPIO_INTEN_PRE register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_PRE_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Interrupt Enable Field (PR_DONE) - prd + * + * Enables interrupt generation for PR_DONE + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_PRD_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_PRD_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_PRD + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_PRD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_PRD + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_PRD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_PRD register field. */ +#define ALT_MON_GPIO_INTEN_PRD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_PRD register field. */ +#define ALT_MON_GPIO_INTEN_PRD_MSB 7 +/* The width in bits of the ALT_MON_GPIO_INTEN_PRD register field. */ +#define ALT_MON_GPIO_INTEN_PRD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_PRD register field value. */ +#define ALT_MON_GPIO_INTEN_PRD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_MON_GPIO_INTEN_PRD register field value. */ +#define ALT_MON_GPIO_INTEN_PRD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_MON_GPIO_INTEN_PRD register field. */ +#define ALT_MON_GPIO_INTEN_PRD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_PRD field value from a register. */ +#define ALT_MON_GPIO_INTEN_PRD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_MON_GPIO_INTEN_PRD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_PRD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Interrupt Enable Field (nCONFIG Pin) - ncp + * + * Enables interrupt generation for nCONFIG Pin + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_NCP_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_NCP_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_NCP + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_NCP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_NCP + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_NCP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_NCP register field. */ +#define ALT_MON_GPIO_INTEN_NCP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_NCP register field. */ +#define ALT_MON_GPIO_INTEN_NCP_MSB 8 +/* The width in bits of the ALT_MON_GPIO_INTEN_NCP register field. */ +#define ALT_MON_GPIO_INTEN_NCP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_NCP register field value. */ +#define ALT_MON_GPIO_INTEN_NCP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_MON_GPIO_INTEN_NCP register field value. */ +#define ALT_MON_GPIO_INTEN_NCP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_MON_GPIO_INTEN_NCP register field. */ +#define ALT_MON_GPIO_INTEN_NCP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_NCP field value from a register. */ +#define ALT_MON_GPIO_INTEN_NCP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_MON_GPIO_INTEN_NCP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_NCP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Interrupt Enable Field (nSTATUS Pin) - nsp + * + * Enables interrupt generation for nSTATUS Pin + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_NSP_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_NSP_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_NSP + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_NSP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_NSP + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_NSP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_NSP register field. */ +#define ALT_MON_GPIO_INTEN_NSP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_NSP register field. */ +#define ALT_MON_GPIO_INTEN_NSP_MSB 9 +/* The width in bits of the ALT_MON_GPIO_INTEN_NSP register field. */ +#define ALT_MON_GPIO_INTEN_NSP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_NSP register field value. */ +#define ALT_MON_GPIO_INTEN_NSP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_MON_GPIO_INTEN_NSP register field value. */ +#define ALT_MON_GPIO_INTEN_NSP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_MON_GPIO_INTEN_NSP register field. */ +#define ALT_MON_GPIO_INTEN_NSP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_NSP field value from a register. */ +#define ALT_MON_GPIO_INTEN_NSP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_MON_GPIO_INTEN_NSP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_NSP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Interrupt Enable Field (CONF_DONE Pin) - cdp + * + * Enables interrupt generation for CONF_DONE Pin + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_CDP_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_CDP_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_CDP + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_CDP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_CDP + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_CDP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_CDP register field. */ +#define ALT_MON_GPIO_INTEN_CDP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_CDP register field. */ +#define ALT_MON_GPIO_INTEN_CDP_MSB 10 +/* The width in bits of the ALT_MON_GPIO_INTEN_CDP register field. */ +#define ALT_MON_GPIO_INTEN_CDP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_CDP register field value. */ +#define ALT_MON_GPIO_INTEN_CDP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_MON_GPIO_INTEN_CDP register field value. */ +#define ALT_MON_GPIO_INTEN_CDP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_MON_GPIO_INTEN_CDP register field. */ +#define ALT_MON_GPIO_INTEN_CDP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_CDP field value from a register. */ +#define ALT_MON_GPIO_INTEN_CDP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_MON_GPIO_INTEN_CDP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_CDP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Interrupt Enable Field (FPGA_POWER_ON) - fpo + * + * Enables interrupt generation for FPGA_POWER_ON + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------ + * ALT_MON_GPIO_INTEN_FPO_E_DIS | 0x0 | Disable Interrupt + * ALT_MON_GPIO_INTEN_FPO_E_EN | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_FPO + * + * Disable Interrupt + */ +#define ALT_MON_GPIO_INTEN_FPO_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTEN_FPO + * + * Enable Interrupt + */ +#define ALT_MON_GPIO_INTEN_FPO_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_FPO register field. */ +#define ALT_MON_GPIO_INTEN_FPO_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_FPO register field. */ +#define ALT_MON_GPIO_INTEN_FPO_MSB 11 +/* The width in bits of the ALT_MON_GPIO_INTEN_FPO register field. */ +#define ALT_MON_GPIO_INTEN_FPO_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTEN_FPO register field value. */ +#define ALT_MON_GPIO_INTEN_FPO_SET_MSK 0x00000800 +/* The mask used to clear the ALT_MON_GPIO_INTEN_FPO register field value. */ +#define ALT_MON_GPIO_INTEN_FPO_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_MON_GPIO_INTEN_FPO register field. */ +#define ALT_MON_GPIO_INTEN_FPO_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTEN_FPO field value from a register. */ +#define ALT_MON_GPIO_INTEN_FPO_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_MON_GPIO_INTEN_FPO register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTEN_FPO_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_INTEN. + */ +struct ALT_MON_GPIO_INTEN_s +{ + uint32_t ns : 1; /* Interrupt Enable Field (nSTATUS) */ + uint32_t cd : 1; /* Interrupt Enable Field (CONF_DONE) */ + uint32_t id : 1; /* Interrupt Enable Field (INIT_DONE) */ + uint32_t crc : 1; /* Interrupt Enable Field (CRC_ERROR) */ + uint32_t ccd : 1; /* Interrupt Enable Field (CVP_CONF_DONE) */ + uint32_t prr : 1; /* Interrupt Enable Field (PR_READY) */ + uint32_t pre : 1; /* Interrupt Enable Field (PR_ERROR) */ + uint32_t prd : 1; /* Interrupt Enable Field (PR_DONE) */ + uint32_t ncp : 1; /* Interrupt Enable Field (nCONFIG Pin) */ + uint32_t nsp : 1; /* Interrupt Enable Field (nSTATUS Pin) */ + uint32_t cdp : 1; /* Interrupt Enable Field (CONF_DONE Pin) */ + uint32_t fpo : 1; /* Interrupt Enable Field (FPGA_POWER_ON) */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_INTEN. */ +typedef volatile struct ALT_MON_GPIO_INTEN_s ALT_MON_GPIO_INTEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_INTEN register from the beginning of the component. */ +#define ALT_MON_GPIO_INTEN_OFST 0x30 +/* The address of the ALT_MON_GPIO_INTEN register. */ +#define ALT_MON_GPIO_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_INTEN_OFST)) + +/* + * Register : Interrupt Mask Register - gpio_intmask + * + * This register has 12 individual interrupt masks for the MON. Controls whether an + * interrupt on Port A can create an interrupt for the interrupt controller by not + * masking it. By default, all interrupts bits are unmasked. Whenever a 1 is + * written to a bit in this register, it masks the interrupt generation capability + * for this signal; otherwise interrupts are allowed through. The unmasked status + * can be read as well as the resultant status after masking. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------- + * [0] | RW | 0x0 | Interrupt Mask Field (nSTATUS) + * [1] | RW | 0x0 | Interrupt Mask Field (CONF_DONE) + * [2] | RW | 0x0 | Interrupt Mask Field (INIT_DONE) + * [3] | RW | 0x0 | Interrupt Mask Field (CRC_ERROR) + * [4] | RW | 0x0 | Interrupt Mask Field (CVP_CONF_DONE) + * [5] | RW | 0x0 | Interrupt Mask Field (PR_READY) + * [6] | RW | 0x0 | Interrupt Mask Field (PR_ERROR) + * [7] | RW | 0x0 | Interrupt Mask Field (PR_DONE) + * [8] | RW | 0x0 | Interrupt Mask Field (nCONFIG Pin) + * [9] | RW | 0x0 | Interrupt Mask Field (nSTATUS Pin) + * [10] | RW | 0x0 | Interrupt Mask Field (CONF_DONE Pin) + * [11] | RW | 0x0 | Interrupt Mask Field (FPGA_POWER_ON) + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Mask Field (nSTATUS) - ns + * + * Controls whether an interrupt for nSTATUS can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_NS_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_NS_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_NS + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_NS_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_NS + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_NS_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_NS register field. */ +#define ALT_MON_GPIO_INTMSK_NS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_NS register field. */ +#define ALT_MON_GPIO_INTMSK_NS_MSB 0 +/* The width in bits of the ALT_MON_GPIO_INTMSK_NS register field. */ +#define ALT_MON_GPIO_INTMSK_NS_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_NS register field value. */ +#define ALT_MON_GPIO_INTMSK_NS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_NS register field value. */ +#define ALT_MON_GPIO_INTMSK_NS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_MON_GPIO_INTMSK_NS register field. */ +#define ALT_MON_GPIO_INTMSK_NS_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_NS field value from a register. */ +#define ALT_MON_GPIO_INTMSK_NS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MON_GPIO_INTMSK_NS register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_NS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Interrupt Mask Field (CONF_DONE) - cd + * + * Controls whether an interrupt for CONF_DONE can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_CD_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_CD_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_CD + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_CD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_CD + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_CD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_CD register field. */ +#define ALT_MON_GPIO_INTMSK_CD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_CD register field. */ +#define ALT_MON_GPIO_INTMSK_CD_MSB 1 +/* The width in bits of the ALT_MON_GPIO_INTMSK_CD register field. */ +#define ALT_MON_GPIO_INTMSK_CD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_CD register field value. */ +#define ALT_MON_GPIO_INTMSK_CD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_CD register field value. */ +#define ALT_MON_GPIO_INTMSK_CD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_MON_GPIO_INTMSK_CD register field. */ +#define ALT_MON_GPIO_INTMSK_CD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_CD field value from a register. */ +#define ALT_MON_GPIO_INTMSK_CD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_MON_GPIO_INTMSK_CD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_CD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Interrupt Mask Field (INIT_DONE) - id + * + * Controls whether an interrupt for INIT_DONE can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_ID_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_ID_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_ID + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_ID_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_ID + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_ID_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_ID register field. */ +#define ALT_MON_GPIO_INTMSK_ID_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_ID register field. */ +#define ALT_MON_GPIO_INTMSK_ID_MSB 2 +/* The width in bits of the ALT_MON_GPIO_INTMSK_ID register field. */ +#define ALT_MON_GPIO_INTMSK_ID_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_ID register field value. */ +#define ALT_MON_GPIO_INTMSK_ID_SET_MSK 0x00000004 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_ID register field value. */ +#define ALT_MON_GPIO_INTMSK_ID_CLR_MSK 0xfffffffb +/* The reset value of the ALT_MON_GPIO_INTMSK_ID register field. */ +#define ALT_MON_GPIO_INTMSK_ID_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_ID field value from a register. */ +#define ALT_MON_GPIO_INTMSK_ID_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_MON_GPIO_INTMSK_ID register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_ID_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Interrupt Mask Field (CRC_ERROR) - crc + * + * Controls whether an interrupt for CRC_ERROR can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_CRC_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_CRC_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_CRC + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_CRC_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_CRC + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_CRC_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_CRC register field. */ +#define ALT_MON_GPIO_INTMSK_CRC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_CRC register field. */ +#define ALT_MON_GPIO_INTMSK_CRC_MSB 3 +/* The width in bits of the ALT_MON_GPIO_INTMSK_CRC register field. */ +#define ALT_MON_GPIO_INTMSK_CRC_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_CRC register field value. */ +#define ALT_MON_GPIO_INTMSK_CRC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_CRC register field value. */ +#define ALT_MON_GPIO_INTMSK_CRC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_MON_GPIO_INTMSK_CRC register field. */ +#define ALT_MON_GPIO_INTMSK_CRC_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_CRC field value from a register. */ +#define ALT_MON_GPIO_INTMSK_CRC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_MON_GPIO_INTMSK_CRC register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_CRC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Interrupt Mask Field (CVP_CONF_DONE) - ccd + * + * Controls whether an interrupt for CVP_CONF_DONE can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_CCD_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_CCD_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_CCD + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_CCD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_CCD + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_CCD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_CCD register field. */ +#define ALT_MON_GPIO_INTMSK_CCD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_CCD register field. */ +#define ALT_MON_GPIO_INTMSK_CCD_MSB 4 +/* The width in bits of the ALT_MON_GPIO_INTMSK_CCD register field. */ +#define ALT_MON_GPIO_INTMSK_CCD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_CCD register field value. */ +#define ALT_MON_GPIO_INTMSK_CCD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_CCD register field value. */ +#define ALT_MON_GPIO_INTMSK_CCD_CLR_MSK 0xffffffef +/* The reset value of the ALT_MON_GPIO_INTMSK_CCD register field. */ +#define ALT_MON_GPIO_INTMSK_CCD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_CCD field value from a register. */ +#define ALT_MON_GPIO_INTMSK_CCD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_MON_GPIO_INTMSK_CCD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_CCD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Interrupt Mask Field (PR_READY) - prr + * + * Controls whether an interrupt for PR_READY can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_PRR_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_PRR_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRR + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_PRR_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRR + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_PRR_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_PRR register field. */ +#define ALT_MON_GPIO_INTMSK_PRR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_PRR register field. */ +#define ALT_MON_GPIO_INTMSK_PRR_MSB 5 +/* The width in bits of the ALT_MON_GPIO_INTMSK_PRR register field. */ +#define ALT_MON_GPIO_INTMSK_PRR_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_PRR register field value. */ +#define ALT_MON_GPIO_INTMSK_PRR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_PRR register field value. */ +#define ALT_MON_GPIO_INTMSK_PRR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_MON_GPIO_INTMSK_PRR register field. */ +#define ALT_MON_GPIO_INTMSK_PRR_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_PRR field value from a register. */ +#define ALT_MON_GPIO_INTMSK_PRR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_MON_GPIO_INTMSK_PRR register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_PRR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Interrupt Mask Field (PR_ERROR) - pre + * + * Controls whether an interrupt for PR_ERROR can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_PRE_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_PRE_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRE + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_PRE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRE + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_PRE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_PRE register field. */ +#define ALT_MON_GPIO_INTMSK_PRE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_PRE register field. */ +#define ALT_MON_GPIO_INTMSK_PRE_MSB 6 +/* The width in bits of the ALT_MON_GPIO_INTMSK_PRE register field. */ +#define ALT_MON_GPIO_INTMSK_PRE_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_PRE register field value. */ +#define ALT_MON_GPIO_INTMSK_PRE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_PRE register field value. */ +#define ALT_MON_GPIO_INTMSK_PRE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_MON_GPIO_INTMSK_PRE register field. */ +#define ALT_MON_GPIO_INTMSK_PRE_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_PRE field value from a register. */ +#define ALT_MON_GPIO_INTMSK_PRE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_MON_GPIO_INTMSK_PRE register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_PRE_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Interrupt Mask Field (PR_DONE) - prd + * + * Controls whether an interrupt for PR_DONE can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_PRD_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_PRD_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRD + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_PRD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRD + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_PRD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_PRD register field. */ +#define ALT_MON_GPIO_INTMSK_PRD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_PRD register field. */ +#define ALT_MON_GPIO_INTMSK_PRD_MSB 7 +/* The width in bits of the ALT_MON_GPIO_INTMSK_PRD register field. */ +#define ALT_MON_GPIO_INTMSK_PRD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_PRD register field value. */ +#define ALT_MON_GPIO_INTMSK_PRD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_PRD register field value. */ +#define ALT_MON_GPIO_INTMSK_PRD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_MON_GPIO_INTMSK_PRD register field. */ +#define ALT_MON_GPIO_INTMSK_PRD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_PRD field value from a register. */ +#define ALT_MON_GPIO_INTMSK_PRD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_MON_GPIO_INTMSK_PRD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_PRD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Interrupt Mask Field (nCONFIG Pin) - ncp + * + * Controls whether an interrupt for nCONFIG Pin can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_NCP_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_NCP_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_NCP + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_NCP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_NCP + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_NCP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_NCP register field. */ +#define ALT_MON_GPIO_INTMSK_NCP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_NCP register field. */ +#define ALT_MON_GPIO_INTMSK_NCP_MSB 8 +/* The width in bits of the ALT_MON_GPIO_INTMSK_NCP register field. */ +#define ALT_MON_GPIO_INTMSK_NCP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_NCP register field value. */ +#define ALT_MON_GPIO_INTMSK_NCP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_NCP register field value. */ +#define ALT_MON_GPIO_INTMSK_NCP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_MON_GPIO_INTMSK_NCP register field. */ +#define ALT_MON_GPIO_INTMSK_NCP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_NCP field value from a register. */ +#define ALT_MON_GPIO_INTMSK_NCP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_MON_GPIO_INTMSK_NCP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_NCP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Interrupt Mask Field (nSTATUS Pin) - nsp + * + * Controls whether an interrupt for nSTATUS Pin can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_NSP_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_NSP_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_NSP + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_NSP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_NSP + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_NSP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_NSP register field. */ +#define ALT_MON_GPIO_INTMSK_NSP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_NSP register field. */ +#define ALT_MON_GPIO_INTMSK_NSP_MSB 9 +/* The width in bits of the ALT_MON_GPIO_INTMSK_NSP register field. */ +#define ALT_MON_GPIO_INTMSK_NSP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_NSP register field value. */ +#define ALT_MON_GPIO_INTMSK_NSP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_NSP register field value. */ +#define ALT_MON_GPIO_INTMSK_NSP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_MON_GPIO_INTMSK_NSP register field. */ +#define ALT_MON_GPIO_INTMSK_NSP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_NSP field value from a register. */ +#define ALT_MON_GPIO_INTMSK_NSP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_MON_GPIO_INTMSK_NSP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_NSP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Interrupt Mask Field (CONF_DONE Pin) - cdp + * + * Controls whether an interrupt for CONF_DONE Pin can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_CDP_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_CDP_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_CDP + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_CDP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_CDP + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_CDP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_CDP register field. */ +#define ALT_MON_GPIO_INTMSK_CDP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_CDP register field. */ +#define ALT_MON_GPIO_INTMSK_CDP_MSB 10 +/* The width in bits of the ALT_MON_GPIO_INTMSK_CDP register field. */ +#define ALT_MON_GPIO_INTMSK_CDP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_CDP register field value. */ +#define ALT_MON_GPIO_INTMSK_CDP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_CDP register field value. */ +#define ALT_MON_GPIO_INTMSK_CDP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_MON_GPIO_INTMSK_CDP register field. */ +#define ALT_MON_GPIO_INTMSK_CDP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_CDP field value from a register. */ +#define ALT_MON_GPIO_INTMSK_CDP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_MON_GPIO_INTMSK_CDP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_CDP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Interrupt Mask Field (FPGA_POWER_ON) - fpo + * + * Controls whether an interrupt for FPGA_POWER_ON can generate an interrupt to the + * interrupt controller by not masking it. The unmasked status can be read as well + * as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_MON_GPIO_INTMSK_FPO_E_DIS | 0x0 | Unmask Interrupt + * ALT_MON_GPIO_INTMSK_FPO_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_FPO + * + * Unmask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_FPO_E_DIS 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTMSK_FPO + * + * Mask Interrupt + */ +#define ALT_MON_GPIO_INTMSK_FPO_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_FPO register field. */ +#define ALT_MON_GPIO_INTMSK_FPO_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_FPO register field. */ +#define ALT_MON_GPIO_INTMSK_FPO_MSB 11 +/* The width in bits of the ALT_MON_GPIO_INTMSK_FPO register field. */ +#define ALT_MON_GPIO_INTMSK_FPO_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTMSK_FPO register field value. */ +#define ALT_MON_GPIO_INTMSK_FPO_SET_MSK 0x00000800 +/* The mask used to clear the ALT_MON_GPIO_INTMSK_FPO register field value. */ +#define ALT_MON_GPIO_INTMSK_FPO_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_MON_GPIO_INTMSK_FPO register field. */ +#define ALT_MON_GPIO_INTMSK_FPO_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTMSK_FPO field value from a register. */ +#define ALT_MON_GPIO_INTMSK_FPO_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_MON_GPIO_INTMSK_FPO register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTMSK_FPO_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_INTMSK. + */ +struct ALT_MON_GPIO_INTMSK_s +{ + uint32_t ns : 1; /* Interrupt Mask Field (nSTATUS) */ + uint32_t cd : 1; /* Interrupt Mask Field (CONF_DONE) */ + uint32_t id : 1; /* Interrupt Mask Field (INIT_DONE) */ + uint32_t crc : 1; /* Interrupt Mask Field (CRC_ERROR) */ + uint32_t ccd : 1; /* Interrupt Mask Field (CVP_CONF_DONE) */ + uint32_t prr : 1; /* Interrupt Mask Field (PR_READY) */ + uint32_t pre : 1; /* Interrupt Mask Field (PR_ERROR) */ + uint32_t prd : 1; /* Interrupt Mask Field (PR_DONE) */ + uint32_t ncp : 1; /* Interrupt Mask Field (nCONFIG Pin) */ + uint32_t nsp : 1; /* Interrupt Mask Field (nSTATUS Pin) */ + uint32_t cdp : 1; /* Interrupt Mask Field (CONF_DONE Pin) */ + uint32_t fpo : 1; /* Interrupt Mask Field (FPGA_POWER_ON) */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_INTMSK. */ +typedef volatile struct ALT_MON_GPIO_INTMSK_s ALT_MON_GPIO_INTMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_INTMSK register from the beginning of the component. */ +#define ALT_MON_GPIO_INTMSK_OFST 0x34 +/* The address of the ALT_MON_GPIO_INTMSK register. */ +#define ALT_MON_GPIO_INTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_INTMSK_OFST)) + +/* + * Register : Interrupt Level Register - gpio_inttype_level + * + * The interrupt level register defines the type of interrupt (edge or level) for + * each GPIO input. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x0 | Interrupt Level Field (nSTATUS) + * [1] | RW | 0x0 | Interrupt Level Field (CONF_DONE) + * [2] | RW | 0x0 | Interrupt Level Field (INIT_DONE) + * [3] | RW | 0x0 | Interrupt Level Field (CRC_ERROR) + * [4] | RW | 0x0 | Interrupt Level Field (CVP_CONF_DONE) + * [5] | RW | 0x0 | Interrupt Level Field (PR_READY) + * [6] | RW | 0x0 | Interrupt Level Field (PR_ERROR) + * [7] | RW | 0x0 | Interrupt Level Field (PR_DONE) + * [8] | RW | 0x0 | Interrupt Level Field (nCONFIG Pin) + * [9] | RW | 0x0 | Interrupt Level Field (nSTATUS Pin) + * [10] | RW | 0x0 | Interrupt Level Field (CONF_DONE Pin) + * [11] | RW | 0x0 | Interrupt Level Field (FPGA_POWER_ON) + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Level Field (nSTATUS) - ns + * + * Controls whether the level of nSTATUS or an edge on nSTATUS generates an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_NS_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_NS_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NS + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NS_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NS + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NS_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NS_MSB 0 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NS_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NS_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_NS field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_NS register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Interrupt Level Field (CONF_DONE) - cd + * + * Controls whether the level of CONF_DONE or an edge on CONF_DONE generates an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_CD_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_CD_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CD + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CD_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CD + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CD_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CD_MSB 1 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_CD field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_CD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Interrupt Level Field (INIT_DONE) - id + * + * Controls whether the level of INIT_DONE or an edge on INIT_DONE generates an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_ID_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_ID_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_ID + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ID_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_ID + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ID_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ID_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ID_MSB 2 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ID_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ID_SET_MSK 0x00000004 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ID_CLR_MSK 0xfffffffb +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ID_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_ID field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ID_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_ID register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ID_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Interrupt Level Field (CRC_ERROR) - crc + * + * Controls whether the level of CRC_ERROR or an edge on CRC_ERROR generates an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_CRC_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_CRC_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CRC + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CRC + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_MSB 3 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_CRC field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Interrupt Level Field (CVP_CONF_DONE) - ccd + * + * Controls whether the level of CVP_CONF_DONE or an edge on CVP_CONF_DONE + * generates an interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_CCD_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_CCD_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CCD + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CCD + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_MSB 4 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_CLR_MSK 0xffffffef +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_CCD field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Interrupt Level Field (PR_READY) - prr + * + * Controls whether the level of PR_READY or an edge on PR_READY generates an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_PRR_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_PRR_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRR + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRR + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_MSB 5 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_PRR field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Interrupt Level Field (PR_ERROR) - pre + * + * Controls whether the level of PR_ERROR or an edge on PR_ERROR generates an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_PRE_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_PRE_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRE + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRE + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_MSB 6 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_PRE field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Interrupt Level Field (PR_DONE) - prd + * + * Controls whether the level of PR_DONE or an edge on PR_DONE generates an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_PRD_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_PRD_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRD + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRD + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_MSB 7 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_PRD field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Interrupt Level Field (nCONFIG Pin) - ncp + * + * Controls whether the level of nCONFIG Pin or an edge on nCONFIG Pin generates an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_NCP_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_NCP_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NCP + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NCP + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_MSB 8 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_NCP field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Interrupt Level Field (nSTATUS Pin) - nsp + * + * Controls whether the level of nSTATUS Pin or an edge on nSTATUS Pin generates an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_NSP_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_NSP_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NSP + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NSP + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_MSB 9 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_NSP field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Interrupt Level Field (CONF_DONE Pin) - cdp + * + * Controls whether the level of CONF_DONE Pin or an edge on CONF_DONE Pin + * generates an interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_CDP_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_CDP_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CDP + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CDP + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_MSB 10 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_CDP field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Interrupt Level Field (FPGA_POWER_ON) - fpo + * + * Controls whether the level of FPGA_POWER_ON or an edge on FPGA_POWER_ON + * generates an interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------- + * ALT_MON_GPIO_INTTYPE_LEVEL_FPO_E_LEVEL | 0x0 | Level-sensitive + * ALT_MON_GPIO_INTTYPE_LEVEL_FPO_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_FPO + * + * Level-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_FPO + * + * Edge-sensitive + */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_MSB 11 +/* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_SET_MSK 0x00000800 +/* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field value. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_FPO field value from a register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_INTTYPE_LEVEL. + */ +struct ALT_MON_GPIO_INTTYPE_LEVEL_s +{ + uint32_t ns : 1; /* Interrupt Level Field (nSTATUS) */ + uint32_t cd : 1; /* Interrupt Level Field (CONF_DONE) */ + uint32_t id : 1; /* Interrupt Level Field (INIT_DONE) */ + uint32_t crc : 1; /* Interrupt Level Field (CRC_ERROR) */ + uint32_t ccd : 1; /* Interrupt Level Field (CVP_CONF_DONE) */ + uint32_t prr : 1; /* Interrupt Level Field (PR_READY) */ + uint32_t pre : 1; /* Interrupt Level Field (PR_ERROR) */ + uint32_t prd : 1; /* Interrupt Level Field (PR_DONE) */ + uint32_t ncp : 1; /* Interrupt Level Field (nCONFIG Pin) */ + uint32_t nsp : 1; /* Interrupt Level Field (nSTATUS Pin) */ + uint32_t cdp : 1; /* Interrupt Level Field (CONF_DONE Pin) */ + uint32_t fpo : 1; /* Interrupt Level Field (FPGA_POWER_ON) */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_INTTYPE_LEVEL. */ +typedef volatile struct ALT_MON_GPIO_INTTYPE_LEVEL_s ALT_MON_GPIO_INTTYPE_LEVEL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_INTTYPE_LEVEL register from the beginning of the component. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_OFST 0x38 +/* The address of the ALT_MON_GPIO_INTTYPE_LEVEL register. */ +#define ALT_MON_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_INTTYPE_LEVEL_OFST)) + +/* + * Register : Interrupt Polarity Register - gpio_int_polarity + * + * Controls the polarity of interrupts that can occur on each GPIO input. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | Polarity Control Field (nSTATUS) + * [1] | RW | 0x0 | Polarity Control Field (CONF_DONE) + * [2] | RW | 0x0 | Polarity Control Field (INIT_DONE) + * [3] | RW | 0x0 | Polarity Control Field (CRC_ERROR) + * [4] | RW | 0x0 | Polarity Control Field (CVP_CONF_DONE) + * [5] | RW | 0x0 | Polarity Control Field (PR_READY) + * [6] | RW | 0x0 | Polarity Control Field (PR_ERROR) + * [7] | RW | 0x0 | Polarity Control Field (PR_DONE) + * [8] | RW | 0x0 | Polarity Control Field (nCONFIG Pin) + * [9] | RW | 0x0 | Polarity Control Field (nSTATUS Pin) + * [10] | RW | 0x0 | Polarity Control Field (CONF_DONE Pin) + * [11] | RW | 0x0 | Polarity Control Field (FPGA_POWER_ON) + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Polarity Control Field (nSTATUS) - ns + * + * Controls the polarity of edge or level sensitivity for nSTATUS + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_NS_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_NS_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_NS + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_NS_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_NS + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_NS_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_NS register field. */ +#define ALT_MON_GPIO_INT_POL_NS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_NS register field. */ +#define ALT_MON_GPIO_INT_POL_NS_MSB 0 +/* The width in bits of the ALT_MON_GPIO_INT_POL_NS register field. */ +#define ALT_MON_GPIO_INT_POL_NS_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_NS register field value. */ +#define ALT_MON_GPIO_INT_POL_NS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_NS register field value. */ +#define ALT_MON_GPIO_INT_POL_NS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_MON_GPIO_INT_POL_NS register field. */ +#define ALT_MON_GPIO_INT_POL_NS_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_NS field value from a register. */ +#define ALT_MON_GPIO_INT_POL_NS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MON_GPIO_INT_POL_NS register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_NS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Polarity Control Field (CONF_DONE) - cd + * + * Controls the polarity of edge or level sensitivity for CONF_DONE + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_CD_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_CD_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_CD + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_CD_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_CD + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_CD_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_CD register field. */ +#define ALT_MON_GPIO_INT_POL_CD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_CD register field. */ +#define ALT_MON_GPIO_INT_POL_CD_MSB 1 +/* The width in bits of the ALT_MON_GPIO_INT_POL_CD register field. */ +#define ALT_MON_GPIO_INT_POL_CD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_CD register field value. */ +#define ALT_MON_GPIO_INT_POL_CD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_CD register field value. */ +#define ALT_MON_GPIO_INT_POL_CD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_MON_GPIO_INT_POL_CD register field. */ +#define ALT_MON_GPIO_INT_POL_CD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_CD field value from a register. */ +#define ALT_MON_GPIO_INT_POL_CD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_MON_GPIO_INT_POL_CD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_CD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Polarity Control Field (INIT_DONE) - id + * + * Controls the polarity of edge or level sensitivity for INIT_DONE + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_ID_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_ID_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_ID + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_ID_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_ID + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_ID_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_ID register field. */ +#define ALT_MON_GPIO_INT_POL_ID_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_ID register field. */ +#define ALT_MON_GPIO_INT_POL_ID_MSB 2 +/* The width in bits of the ALT_MON_GPIO_INT_POL_ID register field. */ +#define ALT_MON_GPIO_INT_POL_ID_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_ID register field value. */ +#define ALT_MON_GPIO_INT_POL_ID_SET_MSK 0x00000004 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_ID register field value. */ +#define ALT_MON_GPIO_INT_POL_ID_CLR_MSK 0xfffffffb +/* The reset value of the ALT_MON_GPIO_INT_POL_ID register field. */ +#define ALT_MON_GPIO_INT_POL_ID_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_ID field value from a register. */ +#define ALT_MON_GPIO_INT_POL_ID_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_MON_GPIO_INT_POL_ID register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_ID_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Polarity Control Field (CRC_ERROR) - crc + * + * Controls the polarity of edge or level sensitivity for CRC_ERROR + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_CRC_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_CRC_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_CRC + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_CRC_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_CRC + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_CRC_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_CRC register field. */ +#define ALT_MON_GPIO_INT_POL_CRC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_CRC register field. */ +#define ALT_MON_GPIO_INT_POL_CRC_MSB 3 +/* The width in bits of the ALT_MON_GPIO_INT_POL_CRC register field. */ +#define ALT_MON_GPIO_INT_POL_CRC_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_CRC register field value. */ +#define ALT_MON_GPIO_INT_POL_CRC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_CRC register field value. */ +#define ALT_MON_GPIO_INT_POL_CRC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_MON_GPIO_INT_POL_CRC register field. */ +#define ALT_MON_GPIO_INT_POL_CRC_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_CRC field value from a register. */ +#define ALT_MON_GPIO_INT_POL_CRC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_MON_GPIO_INT_POL_CRC register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_CRC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Polarity Control Field (CVP_CONF_DONE) - ccd + * + * Controls the polarity of edge or level sensitivity for CVP_CONF_DONE + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_CCD_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_CCD_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_CCD + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_CCD_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_CCD + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_CCD_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_CCD register field. */ +#define ALT_MON_GPIO_INT_POL_CCD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_CCD register field. */ +#define ALT_MON_GPIO_INT_POL_CCD_MSB 4 +/* The width in bits of the ALT_MON_GPIO_INT_POL_CCD register field. */ +#define ALT_MON_GPIO_INT_POL_CCD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_CCD register field value. */ +#define ALT_MON_GPIO_INT_POL_CCD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_CCD register field value. */ +#define ALT_MON_GPIO_INT_POL_CCD_CLR_MSK 0xffffffef +/* The reset value of the ALT_MON_GPIO_INT_POL_CCD register field. */ +#define ALT_MON_GPIO_INT_POL_CCD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_CCD field value from a register. */ +#define ALT_MON_GPIO_INT_POL_CCD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_MON_GPIO_INT_POL_CCD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_CCD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Polarity Control Field (PR_READY) - prr + * + * Controls the polarity of edge or level sensitivity for PR_READY + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_PRR_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_PRR_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRR + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_PRR_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRR + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_PRR_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_PRR register field. */ +#define ALT_MON_GPIO_INT_POL_PRR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_PRR register field. */ +#define ALT_MON_GPIO_INT_POL_PRR_MSB 5 +/* The width in bits of the ALT_MON_GPIO_INT_POL_PRR register field. */ +#define ALT_MON_GPIO_INT_POL_PRR_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_PRR register field value. */ +#define ALT_MON_GPIO_INT_POL_PRR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_PRR register field value. */ +#define ALT_MON_GPIO_INT_POL_PRR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_MON_GPIO_INT_POL_PRR register field. */ +#define ALT_MON_GPIO_INT_POL_PRR_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_PRR field value from a register. */ +#define ALT_MON_GPIO_INT_POL_PRR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_MON_GPIO_INT_POL_PRR register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_PRR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Polarity Control Field (PR_ERROR) - pre + * + * Controls the polarity of edge or level sensitivity for PR_ERROR + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_PRE_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_PRE_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRE + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_PRE_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRE + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_PRE_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_PRE register field. */ +#define ALT_MON_GPIO_INT_POL_PRE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_PRE register field. */ +#define ALT_MON_GPIO_INT_POL_PRE_MSB 6 +/* The width in bits of the ALT_MON_GPIO_INT_POL_PRE register field. */ +#define ALT_MON_GPIO_INT_POL_PRE_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_PRE register field value. */ +#define ALT_MON_GPIO_INT_POL_PRE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_PRE register field value. */ +#define ALT_MON_GPIO_INT_POL_PRE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_MON_GPIO_INT_POL_PRE register field. */ +#define ALT_MON_GPIO_INT_POL_PRE_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_PRE field value from a register. */ +#define ALT_MON_GPIO_INT_POL_PRE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_MON_GPIO_INT_POL_PRE register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_PRE_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Polarity Control Field (PR_DONE) - prd + * + * Controls the polarity of edge or level sensitivity for PR_DONE + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_PRD_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_PRD_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRD + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_PRD_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRD + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_PRD_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_PRD register field. */ +#define ALT_MON_GPIO_INT_POL_PRD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_PRD register field. */ +#define ALT_MON_GPIO_INT_POL_PRD_MSB 7 +/* The width in bits of the ALT_MON_GPIO_INT_POL_PRD register field. */ +#define ALT_MON_GPIO_INT_POL_PRD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_PRD register field value. */ +#define ALT_MON_GPIO_INT_POL_PRD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_PRD register field value. */ +#define ALT_MON_GPIO_INT_POL_PRD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_MON_GPIO_INT_POL_PRD register field. */ +#define ALT_MON_GPIO_INT_POL_PRD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_PRD field value from a register. */ +#define ALT_MON_GPIO_INT_POL_PRD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_MON_GPIO_INT_POL_PRD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_PRD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Polarity Control Field (nCONFIG Pin) - ncp + * + * Controls the polarity of edge or level sensitivity for nCONFIG Pin + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_NCP_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_NCP_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_NCP + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_NCP_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_NCP + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_NCP_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_NCP register field. */ +#define ALT_MON_GPIO_INT_POL_NCP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_NCP register field. */ +#define ALT_MON_GPIO_INT_POL_NCP_MSB 8 +/* The width in bits of the ALT_MON_GPIO_INT_POL_NCP register field. */ +#define ALT_MON_GPIO_INT_POL_NCP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_NCP register field value. */ +#define ALT_MON_GPIO_INT_POL_NCP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_NCP register field value. */ +#define ALT_MON_GPIO_INT_POL_NCP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_MON_GPIO_INT_POL_NCP register field. */ +#define ALT_MON_GPIO_INT_POL_NCP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_NCP field value from a register. */ +#define ALT_MON_GPIO_INT_POL_NCP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_MON_GPIO_INT_POL_NCP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_NCP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Polarity Control Field (nSTATUS Pin) - nsp + * + * Controls the polarity of edge or level sensitivity for nSTATUS Pin + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_NSP_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_NSP_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_NSP + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_NSP_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_NSP + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_NSP_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_NSP register field. */ +#define ALT_MON_GPIO_INT_POL_NSP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_NSP register field. */ +#define ALT_MON_GPIO_INT_POL_NSP_MSB 9 +/* The width in bits of the ALT_MON_GPIO_INT_POL_NSP register field. */ +#define ALT_MON_GPIO_INT_POL_NSP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_NSP register field value. */ +#define ALT_MON_GPIO_INT_POL_NSP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_NSP register field value. */ +#define ALT_MON_GPIO_INT_POL_NSP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_MON_GPIO_INT_POL_NSP register field. */ +#define ALT_MON_GPIO_INT_POL_NSP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_NSP field value from a register. */ +#define ALT_MON_GPIO_INT_POL_NSP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_MON_GPIO_INT_POL_NSP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_NSP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Polarity Control Field (CONF_DONE Pin) - cdp + * + * Controls the polarity of edge or level sensitivity for CONF_DONE Pin + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_CDP_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_CDP_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_CDP + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_CDP_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_CDP + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_CDP_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_CDP register field. */ +#define ALT_MON_GPIO_INT_POL_CDP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_CDP register field. */ +#define ALT_MON_GPIO_INT_POL_CDP_MSB 10 +/* The width in bits of the ALT_MON_GPIO_INT_POL_CDP register field. */ +#define ALT_MON_GPIO_INT_POL_CDP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_CDP register field value. */ +#define ALT_MON_GPIO_INT_POL_CDP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_CDP register field value. */ +#define ALT_MON_GPIO_INT_POL_CDP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_MON_GPIO_INT_POL_CDP register field. */ +#define ALT_MON_GPIO_INT_POL_CDP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_CDP field value from a register. */ +#define ALT_MON_GPIO_INT_POL_CDP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_MON_GPIO_INT_POL_CDP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_CDP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Polarity Control Field (FPGA_POWER_ON) - fpo + * + * Controls the polarity of edge or level sensitivity for FPGA_POWER_ON + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_MON_GPIO_INT_POL_FPO_E_ACTLOW | 0x0 | Active low + * ALT_MON_GPIO_INT_POL_FPO_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_FPO + * + * Active low + */ +#define ALT_MON_GPIO_INT_POL_FPO_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INT_POL_FPO + * + * Active high + */ +#define ALT_MON_GPIO_INT_POL_FPO_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_FPO register field. */ +#define ALT_MON_GPIO_INT_POL_FPO_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_FPO register field. */ +#define ALT_MON_GPIO_INT_POL_FPO_MSB 11 +/* The width in bits of the ALT_MON_GPIO_INT_POL_FPO register field. */ +#define ALT_MON_GPIO_INT_POL_FPO_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INT_POL_FPO register field value. */ +#define ALT_MON_GPIO_INT_POL_FPO_SET_MSK 0x00000800 +/* The mask used to clear the ALT_MON_GPIO_INT_POL_FPO register field value. */ +#define ALT_MON_GPIO_INT_POL_FPO_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_MON_GPIO_INT_POL_FPO register field. */ +#define ALT_MON_GPIO_INT_POL_FPO_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INT_POL_FPO field value from a register. */ +#define ALT_MON_GPIO_INT_POL_FPO_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_MON_GPIO_INT_POL_FPO register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INT_POL_FPO_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_INT_POL. + */ +struct ALT_MON_GPIO_INT_POL_s +{ + uint32_t ns : 1; /* Polarity Control Field (nSTATUS) */ + uint32_t cd : 1; /* Polarity Control Field (CONF_DONE) */ + uint32_t id : 1; /* Polarity Control Field (INIT_DONE) */ + uint32_t crc : 1; /* Polarity Control Field (CRC_ERROR) */ + uint32_t ccd : 1; /* Polarity Control Field (CVP_CONF_DONE) */ + uint32_t prr : 1; /* Polarity Control Field (PR_READY) */ + uint32_t pre : 1; /* Polarity Control Field (PR_ERROR) */ + uint32_t prd : 1; /* Polarity Control Field (PR_DONE) */ + uint32_t ncp : 1; /* Polarity Control Field (nCONFIG Pin) */ + uint32_t nsp : 1; /* Polarity Control Field (nSTATUS Pin) */ + uint32_t cdp : 1; /* Polarity Control Field (CONF_DONE Pin) */ + uint32_t fpo : 1; /* Polarity Control Field (FPGA_POWER_ON) */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_INT_POL. */ +typedef volatile struct ALT_MON_GPIO_INT_POL_s ALT_MON_GPIO_INT_POL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_INT_POL register from the beginning of the component. */ +#define ALT_MON_GPIO_INT_POL_OFST 0x3c +/* The address of the ALT_MON_GPIO_INT_POL register. */ +#define ALT_MON_GPIO_INT_POL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_INT_POL_OFST)) + +/* + * Register : Interrupt Status Register - gpio_intstatus + * + * Reports on interrupt status for each GPIO input. The interrupt status includes + * the effects of masking. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Interrupt Status Field (nSTATUS) + * [1] | R | 0x0 | Interrupt Status Field (CONF_DONE) + * [2] | R | 0x0 | Interrupt Status Field (INIT_DONE) + * [3] | R | 0x0 | Interrupt Status Field (CRC_ERROR) + * [4] | R | 0x0 | Interrupt Status Field (CVP_CONF_DONE) + * [5] | R | 0x0 | Interrupt Status Field (PR_READY) + * [6] | R | 0x0 | Interrupt Status Field (PR_ERROR) + * [7] | R | 0x0 | Interrupt Status Field (PR_DONE) + * [8] | R | 0x0 | Interrupt Status Field (nCONFIG Pin) + * [9] | R | 0x0 | Interrupt Status Field (nSTATUS Pin) + * [10] | R | 0x0 | Interrupt Status Field (CONF_DONE Pin) + * [11] | R | 0x0 | Interrupt Status Field (FPGA_POWER_ON) + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Status Field (nSTATUS) - ns + * + * Indicates whether nSTATUS has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_NS_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_NS_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NS + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_NS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NS + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_NS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_NS register field. */ +#define ALT_MON_GPIO_INTSTAT_NS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_NS register field. */ +#define ALT_MON_GPIO_INTSTAT_NS_MSB 0 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_NS register field. */ +#define ALT_MON_GPIO_INTSTAT_NS_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_NS register field value. */ +#define ALT_MON_GPIO_INTSTAT_NS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_NS register field value. */ +#define ALT_MON_GPIO_INTSTAT_NS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_MON_GPIO_INTSTAT_NS register field. */ +#define ALT_MON_GPIO_INTSTAT_NS_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_NS field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_NS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MON_GPIO_INTSTAT_NS register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_NS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Interrupt Status Field (CONF_DONE) - cd + * + * Indicates whether CONF_DONE has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_CD_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_CD_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CD + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_CD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CD + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_CD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_CD register field. */ +#define ALT_MON_GPIO_INTSTAT_CD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_CD register field. */ +#define ALT_MON_GPIO_INTSTAT_CD_MSB 1 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_CD register field. */ +#define ALT_MON_GPIO_INTSTAT_CD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_CD register field value. */ +#define ALT_MON_GPIO_INTSTAT_CD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_CD register field value. */ +#define ALT_MON_GPIO_INTSTAT_CD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_MON_GPIO_INTSTAT_CD register field. */ +#define ALT_MON_GPIO_INTSTAT_CD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_CD field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_CD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_MON_GPIO_INTSTAT_CD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_CD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Interrupt Status Field (INIT_DONE) - id + * + * Indicates whether INIT_DONE has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_ID_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_ID_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_ID + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_ID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_ID + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_ID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_ID register field. */ +#define ALT_MON_GPIO_INTSTAT_ID_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_ID register field. */ +#define ALT_MON_GPIO_INTSTAT_ID_MSB 2 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_ID register field. */ +#define ALT_MON_GPIO_INTSTAT_ID_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_ID register field value. */ +#define ALT_MON_GPIO_INTSTAT_ID_SET_MSK 0x00000004 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_ID register field value. */ +#define ALT_MON_GPIO_INTSTAT_ID_CLR_MSK 0xfffffffb +/* The reset value of the ALT_MON_GPIO_INTSTAT_ID register field. */ +#define ALT_MON_GPIO_INTSTAT_ID_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_ID field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_ID_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_MON_GPIO_INTSTAT_ID register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_ID_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Interrupt Status Field (CRC_ERROR) - crc + * + * Indicates whether CRC_ERROR has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_CRC_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_CRC_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CRC + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_CRC_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CRC + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_CRC_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_CRC register field. */ +#define ALT_MON_GPIO_INTSTAT_CRC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_CRC register field. */ +#define ALT_MON_GPIO_INTSTAT_CRC_MSB 3 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_CRC register field. */ +#define ALT_MON_GPIO_INTSTAT_CRC_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_CRC register field value. */ +#define ALT_MON_GPIO_INTSTAT_CRC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_CRC register field value. */ +#define ALT_MON_GPIO_INTSTAT_CRC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_MON_GPIO_INTSTAT_CRC register field. */ +#define ALT_MON_GPIO_INTSTAT_CRC_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_CRC field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_CRC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_MON_GPIO_INTSTAT_CRC register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_CRC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Interrupt Status Field (CVP_CONF_DONE) - ccd + * + * Indicates whether CVP_CONF_DONE has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_CCD_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_CCD_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CCD + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_CCD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CCD + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_CCD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_CCD register field. */ +#define ALT_MON_GPIO_INTSTAT_CCD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_CCD register field. */ +#define ALT_MON_GPIO_INTSTAT_CCD_MSB 4 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_CCD register field. */ +#define ALT_MON_GPIO_INTSTAT_CCD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_CCD register field value. */ +#define ALT_MON_GPIO_INTSTAT_CCD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_CCD register field value. */ +#define ALT_MON_GPIO_INTSTAT_CCD_CLR_MSK 0xffffffef +/* The reset value of the ALT_MON_GPIO_INTSTAT_CCD register field. */ +#define ALT_MON_GPIO_INTSTAT_CCD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_CCD field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_CCD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_MON_GPIO_INTSTAT_CCD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_CCD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Interrupt Status Field (PR_READY) - prr + * + * Indicates whether PR_READY has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_PRR_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_PRR_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRR + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_PRR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRR + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_PRR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_PRR register field. */ +#define ALT_MON_GPIO_INTSTAT_PRR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_PRR register field. */ +#define ALT_MON_GPIO_INTSTAT_PRR_MSB 5 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_PRR register field. */ +#define ALT_MON_GPIO_INTSTAT_PRR_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_PRR register field value. */ +#define ALT_MON_GPIO_INTSTAT_PRR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_PRR register field value. */ +#define ALT_MON_GPIO_INTSTAT_PRR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_MON_GPIO_INTSTAT_PRR register field. */ +#define ALT_MON_GPIO_INTSTAT_PRR_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_PRR field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_PRR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_MON_GPIO_INTSTAT_PRR register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_PRR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Interrupt Status Field (PR_ERROR) - pre + * + * Indicates whether PR_ERROR has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_PRE_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_PRE_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRE + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_PRE_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRE + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_PRE_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_PRE register field. */ +#define ALT_MON_GPIO_INTSTAT_PRE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_PRE register field. */ +#define ALT_MON_GPIO_INTSTAT_PRE_MSB 6 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_PRE register field. */ +#define ALT_MON_GPIO_INTSTAT_PRE_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_PRE register field value. */ +#define ALT_MON_GPIO_INTSTAT_PRE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_PRE register field value. */ +#define ALT_MON_GPIO_INTSTAT_PRE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_MON_GPIO_INTSTAT_PRE register field. */ +#define ALT_MON_GPIO_INTSTAT_PRE_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_PRE field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_PRE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_MON_GPIO_INTSTAT_PRE register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_PRE_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Interrupt Status Field (PR_DONE) - prd + * + * Indicates whether PR_DONE has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_PRD_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_PRD_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRD + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_PRD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRD + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_PRD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_PRD register field. */ +#define ALT_MON_GPIO_INTSTAT_PRD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_PRD register field. */ +#define ALT_MON_GPIO_INTSTAT_PRD_MSB 7 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_PRD register field. */ +#define ALT_MON_GPIO_INTSTAT_PRD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_PRD register field value. */ +#define ALT_MON_GPIO_INTSTAT_PRD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_PRD register field value. */ +#define ALT_MON_GPIO_INTSTAT_PRD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_MON_GPIO_INTSTAT_PRD register field. */ +#define ALT_MON_GPIO_INTSTAT_PRD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_PRD field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_PRD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_MON_GPIO_INTSTAT_PRD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_PRD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Interrupt Status Field (nCONFIG Pin) - ncp + * + * Indicates whether nCONFIG Pin has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_NCP_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_NCP_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NCP + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_NCP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NCP + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_NCP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_NCP register field. */ +#define ALT_MON_GPIO_INTSTAT_NCP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_NCP register field. */ +#define ALT_MON_GPIO_INTSTAT_NCP_MSB 8 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_NCP register field. */ +#define ALT_MON_GPIO_INTSTAT_NCP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_NCP register field value. */ +#define ALT_MON_GPIO_INTSTAT_NCP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_NCP register field value. */ +#define ALT_MON_GPIO_INTSTAT_NCP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_MON_GPIO_INTSTAT_NCP register field. */ +#define ALT_MON_GPIO_INTSTAT_NCP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_NCP field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_NCP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_MON_GPIO_INTSTAT_NCP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_NCP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Interrupt Status Field (nSTATUS Pin) - nsp + * + * Indicates whether nSTATUS Pin has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_NSP_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_NSP_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NSP + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_NSP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NSP + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_NSP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_NSP register field. */ +#define ALT_MON_GPIO_INTSTAT_NSP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_NSP register field. */ +#define ALT_MON_GPIO_INTSTAT_NSP_MSB 9 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_NSP register field. */ +#define ALT_MON_GPIO_INTSTAT_NSP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_NSP register field value. */ +#define ALT_MON_GPIO_INTSTAT_NSP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_NSP register field value. */ +#define ALT_MON_GPIO_INTSTAT_NSP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_MON_GPIO_INTSTAT_NSP register field. */ +#define ALT_MON_GPIO_INTSTAT_NSP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_NSP field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_NSP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_MON_GPIO_INTSTAT_NSP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_NSP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Interrupt Status Field (CONF_DONE Pin) - cdp + * + * Indicates whether CONF_DONE Pin has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_CDP_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_CDP_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CDP + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_CDP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CDP + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_CDP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_CDP register field. */ +#define ALT_MON_GPIO_INTSTAT_CDP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_CDP register field. */ +#define ALT_MON_GPIO_INTSTAT_CDP_MSB 10 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_CDP register field. */ +#define ALT_MON_GPIO_INTSTAT_CDP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_CDP register field value. */ +#define ALT_MON_GPIO_INTSTAT_CDP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_CDP register field value. */ +#define ALT_MON_GPIO_INTSTAT_CDP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_MON_GPIO_INTSTAT_CDP register field. */ +#define ALT_MON_GPIO_INTSTAT_CDP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_CDP field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_CDP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_MON_GPIO_INTSTAT_CDP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_CDP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Interrupt Status Field (FPGA_POWER_ON) - fpo + * + * Indicates whether FPGA_POWER_ON has an active interrupt or not (after masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_MON_GPIO_INTSTAT_FPO_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_INTSTAT_FPO_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_FPO + * + * Inactive + */ +#define ALT_MON_GPIO_INTSTAT_FPO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_INTSTAT_FPO + * + * Active + */ +#define ALT_MON_GPIO_INTSTAT_FPO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_FPO register field. */ +#define ALT_MON_GPIO_INTSTAT_FPO_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_FPO register field. */ +#define ALT_MON_GPIO_INTSTAT_FPO_MSB 11 +/* The width in bits of the ALT_MON_GPIO_INTSTAT_FPO register field. */ +#define ALT_MON_GPIO_INTSTAT_FPO_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_INTSTAT_FPO register field value. */ +#define ALT_MON_GPIO_INTSTAT_FPO_SET_MSK 0x00000800 +/* The mask used to clear the ALT_MON_GPIO_INTSTAT_FPO register field value. */ +#define ALT_MON_GPIO_INTSTAT_FPO_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_MON_GPIO_INTSTAT_FPO register field. */ +#define ALT_MON_GPIO_INTSTAT_FPO_RESET 0x0 +/* Extracts the ALT_MON_GPIO_INTSTAT_FPO field value from a register. */ +#define ALT_MON_GPIO_INTSTAT_FPO_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_MON_GPIO_INTSTAT_FPO register field value suitable for setting the register. */ +#define ALT_MON_GPIO_INTSTAT_FPO_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_INTSTAT. + */ +struct ALT_MON_GPIO_INTSTAT_s +{ + const uint32_t ns : 1; /* Interrupt Status Field (nSTATUS) */ + const uint32_t cd : 1; /* Interrupt Status Field (CONF_DONE) */ + const uint32_t id : 1; /* Interrupt Status Field (INIT_DONE) */ + const uint32_t crc : 1; /* Interrupt Status Field (CRC_ERROR) */ + const uint32_t ccd : 1; /* Interrupt Status Field (CVP_CONF_DONE) */ + const uint32_t prr : 1; /* Interrupt Status Field (PR_READY) */ + const uint32_t pre : 1; /* Interrupt Status Field (PR_ERROR) */ + const uint32_t prd : 1; /* Interrupt Status Field (PR_DONE) */ + const uint32_t ncp : 1; /* Interrupt Status Field (nCONFIG Pin) */ + const uint32_t nsp : 1; /* Interrupt Status Field (nSTATUS Pin) */ + const uint32_t cdp : 1; /* Interrupt Status Field (CONF_DONE Pin) */ + const uint32_t fpo : 1; /* Interrupt Status Field (FPGA_POWER_ON) */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_INTSTAT. */ +typedef volatile struct ALT_MON_GPIO_INTSTAT_s ALT_MON_GPIO_INTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_INTSTAT register from the beginning of the component. */ +#define ALT_MON_GPIO_INTSTAT_OFST 0x40 +/* The address of the ALT_MON_GPIO_INTSTAT register. */ +#define ALT_MON_GPIO_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_INTSTAT_OFST)) + +/* + * Register : Raw Interrupt Status Register - gpio_raw_intstatus + * + * Reports on raw interrupt status for each GPIO input. The raw interrupt status + * excludes the effects of masking. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | R | 0x0 | Raw Interrupt Status Field (nSTATUS) + * [1] | R | 0x0 | Raw Interrupt Status Field (CONF_DONE) + * [2] | R | 0x0 | Raw Interrupt Status Field (INIT_DONE) + * [3] | R | 0x0 | Raw Interrupt Status Field (CRC_ERROR) + * [4] | R | 0x0 | Raw Interrupt Status Field (CVP_CONF_DONE) + * [5] | R | 0x0 | Raw Interrupt Status Field (PR_READY) + * [6] | R | 0x0 | Raw Interrupt Status Field (PR_ERROR) + * [7] | R | 0x0 | Raw Interrupt Status Field (PR_DONE) + * [8] | R | 0x0 | Raw Interrupt Status Field (nCONFIG Pin) + * [9] | R | 0x0 | Raw Interrupt Status Field (nSTATUS Pin) + * [10] | R | 0x0 | Raw Interrupt Status Field (CONF_DONE Pin) + * [11] | R | 0x0 | Raw Interrupt Status Field (FPGA_POWER_ON) + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Raw Interrupt Status Field (nSTATUS) - ns + * + * Indicates whether nSTATUS has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_NS_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_NS_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NS + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_NS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NS + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_NS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NS register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NS register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NS_MSB 0 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_NS register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NS_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_NS register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_NS register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_NS register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NS_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_NS field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_NS register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Raw Interrupt Status Field (CONF_DONE) - cd + * + * Indicates whether CONF_DONE has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_CD_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_CD_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CD + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_CD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CD + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_CD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CD_MSB 1 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_CD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_CD register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_CD register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_CD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_CD field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_CD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Raw Interrupt Status Field (INIT_DONE) - id + * + * Indicates whether INIT_DONE has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_ID_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_ID_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_ID + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_ID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_ID + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_ID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_ID register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_ID_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_ID register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_ID_MSB 2 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_ID register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_ID_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_ID register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_ID_SET_MSK 0x00000004 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_ID register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_ID_CLR_MSK 0xfffffffb +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_ID register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_ID_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_ID field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_ID_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_ID register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_ID_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Raw Interrupt Status Field (CRC_ERROR) - crc + * + * Indicates whether CRC_ERROR has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_CRC_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_CRC_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CRC + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_CRC_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CRC + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_CRC_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CRC register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CRC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CRC register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CRC_MSB 3 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_CRC register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CRC_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_CRC register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CRC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_CRC register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CRC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_CRC register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CRC_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_CRC field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CRC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_CRC register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CRC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Raw Interrupt Status Field (CVP_CONF_DONE) - ccd + * + * Indicates whether CVP_CONF_DONE has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_CCD_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_CCD_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CCD + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_CCD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CCD + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_CCD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CCD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CCD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CCD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CCD_MSB 4 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_CCD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CCD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_CCD register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CCD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_CCD register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CCD_CLR_MSK 0xffffffef +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_CCD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CCD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_CCD field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CCD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_CCD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CCD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Raw Interrupt Status Field (PR_READY) - prr + * + * Indicates whether PR_READY has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_PRR_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_PRR_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRR + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRR + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRR register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRR register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRR_MSB 5 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_PRR register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRR_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_PRR register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_PRR register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_PRR register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRR_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_PRR field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_PRR register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Raw Interrupt Status Field (PR_ERROR) - pre + * + * Indicates whether PR_ERROR has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_PRE_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_PRE_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRE + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRE_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRE + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRE_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRE register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRE register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRE_MSB 6 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_PRE register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRE_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_PRE register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_PRE register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_PRE register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRE_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_PRE field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_PRE register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRE_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Raw Interrupt Status Field (PR_DONE) - prd + * + * Indicates whether PR_DONE has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_PRD_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_PRD_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRD + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRD + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRD_MSB 7 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_PRD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_PRD register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_PRD register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_PRD register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_PRD field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_PRD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_PRD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Raw Interrupt Status Field (nCONFIG Pin) - ncp + * + * Indicates whether nCONFIG Pin has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_NCP_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_NCP_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NCP + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_NCP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NCP + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_NCP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NCP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NCP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NCP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NCP_MSB 8 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_NCP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NCP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_NCP register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NCP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_NCP register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NCP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_NCP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NCP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_NCP field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NCP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_NCP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NCP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Raw Interrupt Status Field (nSTATUS Pin) - nsp + * + * Indicates whether nSTATUS Pin has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_NSP_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_NSP_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NSP + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_NSP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NSP + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_NSP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NSP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NSP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NSP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NSP_MSB 9 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_NSP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NSP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_NSP register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NSP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_NSP register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NSP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_NSP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NSP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_NSP field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NSP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_NSP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_NSP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Raw Interrupt Status Field (CONF_DONE Pin) - cdp + * + * Indicates whether CONF_DONE Pin has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_CDP_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_CDP_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CDP + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_CDP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CDP + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_CDP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CDP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CDP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CDP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CDP_MSB 10 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_CDP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CDP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_CDP register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CDP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_CDP register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CDP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_CDP register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CDP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_CDP field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CDP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_CDP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_CDP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Raw Interrupt Status Field (FPGA_POWER_ON) - fpo + * + * Indicates whether FPGA_POWER_ON has an active interrupt or not (before masking). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_MON_GPIO_RAW_INTSTAT_FPO_E_INACT | 0x0 | Inactive + * ALT_MON_GPIO_RAW_INTSTAT_FPO_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_FPO + * + * Inactive + */ +#define ALT_MON_GPIO_RAW_INTSTAT_FPO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_FPO + * + * Active + */ +#define ALT_MON_GPIO_RAW_INTSTAT_FPO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_FPO register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_FPO_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_FPO register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_FPO_MSB 11 +/* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_FPO register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_FPO_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_FPO register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_FPO_SET_MSK 0x00000800 +/* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_FPO register field value. */ +#define ALT_MON_GPIO_RAW_INTSTAT_FPO_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_FPO register field. */ +#define ALT_MON_GPIO_RAW_INTSTAT_FPO_RESET 0x0 +/* Extracts the ALT_MON_GPIO_RAW_INTSTAT_FPO field value from a register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_FPO_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_MON_GPIO_RAW_INTSTAT_FPO register field value suitable for setting the register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_FPO_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_RAW_INTSTAT. + */ +struct ALT_MON_GPIO_RAW_INTSTAT_s +{ + const uint32_t ns : 1; /* Raw Interrupt Status Field (nSTATUS) */ + const uint32_t cd : 1; /* Raw Interrupt Status Field (CONF_DONE) */ + const uint32_t id : 1; /* Raw Interrupt Status Field (INIT_DONE) */ + const uint32_t crc : 1; /* Raw Interrupt Status Field (CRC_ERROR) */ + const uint32_t ccd : 1; /* Raw Interrupt Status Field (CVP_CONF_DONE) */ + const uint32_t prr : 1; /* Raw Interrupt Status Field (PR_READY) */ + const uint32_t pre : 1; /* Raw Interrupt Status Field (PR_ERROR) */ + const uint32_t prd : 1; /* Raw Interrupt Status Field (PR_DONE) */ + const uint32_t ncp : 1; /* Raw Interrupt Status Field (nCONFIG Pin) */ + const uint32_t nsp : 1; /* Raw Interrupt Status Field (nSTATUS Pin) */ + const uint32_t cdp : 1; /* Raw Interrupt Status Field (CONF_DONE Pin) */ + const uint32_t fpo : 1; /* Raw Interrupt Status Field (FPGA_POWER_ON) */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_RAW_INTSTAT. */ +typedef volatile struct ALT_MON_GPIO_RAW_INTSTAT_s ALT_MON_GPIO_RAW_INTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_RAW_INTSTAT register from the beginning of the component. */ +#define ALT_MON_GPIO_RAW_INTSTAT_OFST 0x44 +/* The address of the ALT_MON_GPIO_RAW_INTSTAT register. */ +#define ALT_MON_GPIO_RAW_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_RAW_INTSTAT_OFST)) + +/* + * Register : Clear Interrupt Register - gpio_porta_eoi + * + * This register is written by software to clear edge interrupts generated by each + * individual GPIO input. This register always reads back as zero. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | W | 0x0 | Clear Edge Interrupt Field (nSTATUS) + * [1] | W | 0x0 | Clear Edge Interrupt Field (CONF_DONE) + * [2] | W | 0x0 | Clear Edge Interrupt Field (INIT_DONE) + * [3] | W | 0x0 | Clear Edge Interrupt Field (CRC_ERROR) + * [4] | W | 0x0 | Clear Edge Interrupt Field (CVP_CONF_DONE) + * [5] | W | 0x0 | Clear Edge Interrupt Field (PR_READY) + * [6] | W | 0x0 | Clear Edge Interrupt Field (PR_ERROR) + * [7] | W | 0x0 | Clear Edge Interrupt Field (PR_DONE) + * [8] | W | 0x0 | Clear Edge Interrupt Field (nCONFIG Pin) + * [9] | W | 0x0 | Clear Edge Interrupt Field (nSTATUS Pin) + * [10] | W | 0x0 | Clear Edge Interrupt Field (CONF_DONE Pin) + * [11] | W | 0x0 | Clear Edge Interrupt Field (FPGA_POWER_ON) + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Edge Interrupt Field (nSTATUS) - ns + * + * Used by software to clear an nSTATUS edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_NS_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_NS_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NS + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_NS_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NS + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_NS_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_NS register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_NS register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NS_MSB 0 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_NS register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NS_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_NS register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_NS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_NS register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_NS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_NS register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NS_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_NS field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_NS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MON_GPIO_PORTA_EOI_NS register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_NS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Clear Edge Interrupt Field (CONF_DONE) - cd + * + * Used by software to clear an CONF_DONE edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_CD_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_CD_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CD + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_CD_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CD + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_CD_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_CD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_CD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CD_MSB 1 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_CD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_CD register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_CD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_CD register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_CD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_CD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_CD field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_CD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_MON_GPIO_PORTA_EOI_CD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_CD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Clear Edge Interrupt Field (INIT_DONE) - id + * + * Used by software to clear an INIT_DONE edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_ID_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_ID_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_ID + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_ID_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_ID + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_ID_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_ID register field. */ +#define ALT_MON_GPIO_PORTA_EOI_ID_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_ID register field. */ +#define ALT_MON_GPIO_PORTA_EOI_ID_MSB 2 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_ID register field. */ +#define ALT_MON_GPIO_PORTA_EOI_ID_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_ID register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_ID_SET_MSK 0x00000004 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_ID register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_ID_CLR_MSK 0xfffffffb +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_ID register field. */ +#define ALT_MON_GPIO_PORTA_EOI_ID_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_ID field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_ID_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_MON_GPIO_PORTA_EOI_ID register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_ID_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Clear Edge Interrupt Field (CRC_ERROR) - crc + * + * Used by software to clear an CRC_ERROR edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_CRC_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_CRC_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CRC + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_CRC_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CRC + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_CRC_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_CRC register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CRC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_CRC register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CRC_MSB 3 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_CRC register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CRC_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_CRC register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_CRC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_CRC register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_CRC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_CRC register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CRC_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_CRC field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_CRC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_MON_GPIO_PORTA_EOI_CRC register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_CRC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Clear Edge Interrupt Field (CVP_CONF_DONE) - ccd + * + * Used by software to clear an CVP_CONF_DONE edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_CCD_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_CCD_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CCD + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_CCD_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CCD + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_CCD_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_CCD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CCD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_CCD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CCD_MSB 4 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_CCD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CCD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_CCD register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_CCD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_CCD register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_CCD_CLR_MSK 0xffffffef +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_CCD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CCD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_CCD field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_CCD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_MON_GPIO_PORTA_EOI_CCD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_CCD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Clear Edge Interrupt Field (PR_READY) - prr + * + * Used by software to clear an PR_READY edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_PRR_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_PRR_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRR + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_PRR_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRR + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_PRR_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_PRR register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_PRR register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRR_MSB 5 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_PRR register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRR_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_PRR register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_PRR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_PRR register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_PRR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_PRR register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRR_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_PRR field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_PRR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_MON_GPIO_PORTA_EOI_PRR register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_PRR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Clear Edge Interrupt Field (PR_ERROR) - pre + * + * Used by software to clear an PR_ERROR edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_PRE_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_PRE_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRE + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_PRE_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRE + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_PRE_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_PRE register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_PRE register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRE_MSB 6 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_PRE register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRE_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_PRE register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_PRE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_PRE register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_PRE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_PRE register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRE_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_PRE field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_PRE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_MON_GPIO_PORTA_EOI_PRE register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_PRE_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Clear Edge Interrupt Field (PR_DONE) - prd + * + * Used by software to clear an PR_DONE edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_PRD_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_PRD_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRD + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_PRD_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRD + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_PRD_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_PRD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_PRD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRD_MSB 7 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_PRD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_PRD register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_PRD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_PRD register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_PRD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_PRD register field. */ +#define ALT_MON_GPIO_PORTA_EOI_PRD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_PRD field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_PRD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_MON_GPIO_PORTA_EOI_PRD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_PRD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Clear Edge Interrupt Field (nCONFIG Pin) - ncp + * + * Used by software to clear an nCONFIG Pin edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_NCP_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_NCP_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NCP + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_NCP_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NCP + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_NCP_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_NCP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NCP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_NCP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NCP_MSB 8 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_NCP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NCP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_NCP register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_NCP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_NCP register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_NCP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_NCP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NCP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_NCP field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_NCP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_MON_GPIO_PORTA_EOI_NCP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_NCP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Clear Edge Interrupt Field (nSTATUS Pin) - nsp + * + * Used by software to clear an nSTATUS Pin edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_NSP_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_NSP_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NSP + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_NSP_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NSP + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_NSP_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_NSP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NSP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_NSP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NSP_MSB 9 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_NSP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NSP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_NSP register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_NSP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_NSP register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_NSP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_NSP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_NSP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_NSP field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_NSP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_MON_GPIO_PORTA_EOI_NSP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_NSP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Clear Edge Interrupt Field (CONF_DONE Pin) - cdp + * + * Used by software to clear an CONF_DONE Pin edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_CDP_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_CDP_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CDP + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_CDP_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CDP + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_CDP_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_CDP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CDP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_CDP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CDP_MSB 10 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_CDP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CDP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_CDP register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_CDP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_CDP register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_CDP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_CDP register field. */ +#define ALT_MON_GPIO_PORTA_EOI_CDP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_CDP field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_CDP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_MON_GPIO_PORTA_EOI_CDP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_CDP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Clear Edge Interrupt Field (FPGA_POWER_ON) - fpo + * + * Used by software to clear an FPGA_POWER_ON edge interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_MON_GPIO_PORTA_EOI_FPO_E_NOCLR | 0x0 | No interrupt clear + * ALT_MON_GPIO_PORTA_EOI_FPO_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_FPO + * + * No interrupt clear + */ +#define ALT_MON_GPIO_PORTA_EOI_FPO_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_FPO + * + * Clear interrupt + */ +#define ALT_MON_GPIO_PORTA_EOI_FPO_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_FPO register field. */ +#define ALT_MON_GPIO_PORTA_EOI_FPO_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_FPO register field. */ +#define ALT_MON_GPIO_PORTA_EOI_FPO_MSB 11 +/* The width in bits of the ALT_MON_GPIO_PORTA_EOI_FPO register field. */ +#define ALT_MON_GPIO_PORTA_EOI_FPO_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_PORTA_EOI_FPO register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_FPO_SET_MSK 0x00000800 +/* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_FPO register field value. */ +#define ALT_MON_GPIO_PORTA_EOI_FPO_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_MON_GPIO_PORTA_EOI_FPO register field. */ +#define ALT_MON_GPIO_PORTA_EOI_FPO_RESET 0x0 +/* Extracts the ALT_MON_GPIO_PORTA_EOI_FPO field value from a register. */ +#define ALT_MON_GPIO_PORTA_EOI_FPO_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_MON_GPIO_PORTA_EOI_FPO register field value suitable for setting the register. */ +#define ALT_MON_GPIO_PORTA_EOI_FPO_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_PORTA_EOI. + */ +struct ALT_MON_GPIO_PORTA_EOI_s +{ + uint32_t ns : 1; /* Clear Edge Interrupt Field (nSTATUS) */ + uint32_t cd : 1; /* Clear Edge Interrupt Field (CONF_DONE) */ + uint32_t id : 1; /* Clear Edge Interrupt Field (INIT_DONE) */ + uint32_t crc : 1; /* Clear Edge Interrupt Field (CRC_ERROR) */ + uint32_t ccd : 1; /* Clear Edge Interrupt Field (CVP_CONF_DONE) */ + uint32_t prr : 1; /* Clear Edge Interrupt Field (PR_READY) */ + uint32_t pre : 1; /* Clear Edge Interrupt Field (PR_ERROR) */ + uint32_t prd : 1; /* Clear Edge Interrupt Field (PR_DONE) */ + uint32_t ncp : 1; /* Clear Edge Interrupt Field (nCONFIG Pin) */ + uint32_t nsp : 1; /* Clear Edge Interrupt Field (nSTATUS Pin) */ + uint32_t cdp : 1; /* Clear Edge Interrupt Field (CONF_DONE Pin) */ + uint32_t fpo : 1; /* Clear Edge Interrupt Field (FPGA_POWER_ON) */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_PORTA_EOI. */ +typedef volatile struct ALT_MON_GPIO_PORTA_EOI_s ALT_MON_GPIO_PORTA_EOI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_PORTA_EOI register from the beginning of the component. */ +#define ALT_MON_GPIO_PORTA_EOI_OFST 0x4c +/* The address of the ALT_MON_GPIO_PORTA_EOI register. */ +#define ALT_MON_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_PORTA_EOI_OFST)) + +/* + * Register : External Port A Register - gpio_ext_porta + * + * Reading this register reads the values of the GPIO inputs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [0] | R | 0x0 | External Port Field (nSTATUS) + * [1] | R | 0x0 | External Port Field (CONF_DONE) + * [2] | R | 0x0 | External Port Field (INIT_DONE) + * [3] | R | 0x0 | External Port Field (CRC_ERROR) + * [4] | R | 0x0 | External Port Field (CVP_CONF_DONE) + * [5] | R | 0x0 | External Port Field (PR_READY) + * [6] | R | 0x0 | External Port Field (PR_ERROR) + * [7] | R | 0x0 | External Port Field (PR_DONE) + * [8] | R | 0x0 | External Port Field (nCONFIG Pin) + * [9] | R | 0x0 | External Port Field (nSTATUS Pin) + * [10] | R | 0x0 | External Port Field (CONF_DONE Pin) + * [11] | R | 0x0 | External Port Field (FPGA_POWER_ON) + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : External Port Field (nSTATUS) - ns + * + * Reading this provides the value of nSTATUS + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_NS register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_NS register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NS_MSB 0 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_NS register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NS_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_NS register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_NS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_NS register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_NS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_NS register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NS_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_NS field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_NS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MON_GPIO_EXT_PORTA_NS register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_NS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : External Port Field (CONF_DONE) - cd + * + * Reading this provides the value of CONF_DONE + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_CD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_CD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CD_MSB 1 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_CD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_CD register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_CD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_CD register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_CD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_CD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_CD field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_CD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_MON_GPIO_EXT_PORTA_CD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_CD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : External Port Field (INIT_DONE) - id + * + * Reading this provides the value of INIT_DONE + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_ID register field. */ +#define ALT_MON_GPIO_EXT_PORTA_ID_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_ID register field. */ +#define ALT_MON_GPIO_EXT_PORTA_ID_MSB 2 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_ID register field. */ +#define ALT_MON_GPIO_EXT_PORTA_ID_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_ID register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_ID_SET_MSK 0x00000004 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_ID register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_ID_CLR_MSK 0xfffffffb +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_ID register field. */ +#define ALT_MON_GPIO_EXT_PORTA_ID_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_ID field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_ID_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_MON_GPIO_EXT_PORTA_ID register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_ID_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : External Port Field (CRC_ERROR) - crc + * + * Reading this provides the value of CRC_ERROR + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_CRC register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CRC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_CRC register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CRC_MSB 3 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_CRC register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CRC_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_CRC register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_CRC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_CRC register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_CRC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_CRC register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CRC_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_CRC field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_CRC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_MON_GPIO_EXT_PORTA_CRC register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_CRC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : External Port Field (CVP_CONF_DONE) - ccd + * + * Reading this provides the value of CVP_CONF_DONE + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_CCD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CCD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_CCD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CCD_MSB 4 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_CCD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CCD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_CCD register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_CCD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_CCD register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_CCD_CLR_MSK 0xffffffef +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_CCD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CCD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_CCD field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_CCD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_MON_GPIO_EXT_PORTA_CCD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_CCD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : External Port Field (PR_READY) - prr + * + * Reading this provides the value of PR_READY + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_PRR register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_PRR register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRR_MSB 5 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_PRR register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRR_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_PRR register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_PRR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_PRR register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_PRR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_PRR register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRR_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_PRR field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_PRR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_MON_GPIO_EXT_PORTA_PRR register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_PRR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : External Port Field (PR_ERROR) - pre + * + * Reading this provides the value of PR_ERROR + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_PRE register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_PRE register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRE_MSB 6 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_PRE register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRE_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_PRE register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_PRE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_PRE register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_PRE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_PRE register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRE_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_PRE field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_PRE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_MON_GPIO_EXT_PORTA_PRE register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_PRE_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : External Port Field (PR_DONE) - prd + * + * Reading this provides the value of PR_DONE + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_PRD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_PRD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRD_MSB 7 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_PRD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRD_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_PRD register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_PRD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_PRD register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_PRD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_PRD register field. */ +#define ALT_MON_GPIO_EXT_PORTA_PRD_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_PRD field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_PRD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_MON_GPIO_EXT_PORTA_PRD register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_PRD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : External Port Field (nCONFIG Pin) - ncp + * + * Reading this provides the value of nCONFIG Pin + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_NCP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NCP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_NCP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NCP_MSB 8 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_NCP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NCP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_NCP register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_NCP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_NCP register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_NCP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_NCP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NCP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_NCP field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_NCP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_MON_GPIO_EXT_PORTA_NCP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_NCP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : External Port Field (nSTATUS Pin) - nsp + * + * Reading this provides the value of nSTATUS Pin + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_NSP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NSP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_NSP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NSP_MSB 9 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_NSP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NSP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_NSP register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_NSP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_NSP register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_NSP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_NSP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_NSP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_NSP field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_NSP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_MON_GPIO_EXT_PORTA_NSP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_NSP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : External Port Field (CONF_DONE Pin) - cdp + * + * Reading this provides the value of CONF_DONE Pin + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_CDP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CDP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_CDP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CDP_MSB 10 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_CDP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CDP_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_CDP register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_CDP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_CDP register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_CDP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_CDP register field. */ +#define ALT_MON_GPIO_EXT_PORTA_CDP_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_CDP field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_CDP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_MON_GPIO_EXT_PORTA_CDP register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_CDP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : External Port Field (FPGA_POWER_ON) - fpo + * + * Reading this provides the value of FPGA_POWER_ON + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_FPO register field. */ +#define ALT_MON_GPIO_EXT_PORTA_FPO_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_FPO register field. */ +#define ALT_MON_GPIO_EXT_PORTA_FPO_MSB 11 +/* The width in bits of the ALT_MON_GPIO_EXT_PORTA_FPO register field. */ +#define ALT_MON_GPIO_EXT_PORTA_FPO_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_EXT_PORTA_FPO register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_FPO_SET_MSK 0x00000800 +/* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_FPO register field value. */ +#define ALT_MON_GPIO_EXT_PORTA_FPO_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_MON_GPIO_EXT_PORTA_FPO register field. */ +#define ALT_MON_GPIO_EXT_PORTA_FPO_RESET 0x0 +/* Extracts the ALT_MON_GPIO_EXT_PORTA_FPO field value from a register. */ +#define ALT_MON_GPIO_EXT_PORTA_FPO_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_MON_GPIO_EXT_PORTA_FPO register field value suitable for setting the register. */ +#define ALT_MON_GPIO_EXT_PORTA_FPO_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_EXT_PORTA. + */ +struct ALT_MON_GPIO_EXT_PORTA_s +{ + const uint32_t ns : 1; /* External Port Field (nSTATUS) */ + const uint32_t cd : 1; /* External Port Field (CONF_DONE) */ + const uint32_t id : 1; /* External Port Field (INIT_DONE) */ + const uint32_t crc : 1; /* External Port Field (CRC_ERROR) */ + const uint32_t ccd : 1; /* External Port Field (CVP_CONF_DONE) */ + const uint32_t prr : 1; /* External Port Field (PR_READY) */ + const uint32_t pre : 1; /* External Port Field (PR_ERROR) */ + const uint32_t prd : 1; /* External Port Field (PR_DONE) */ + const uint32_t ncp : 1; /* External Port Field (nCONFIG Pin) */ + const uint32_t nsp : 1; /* External Port Field (nSTATUS Pin) */ + const uint32_t cdp : 1; /* External Port Field (CONF_DONE Pin) */ + const uint32_t fpo : 1; /* External Port Field (FPGA_POWER_ON) */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_EXT_PORTA. */ +typedef volatile struct ALT_MON_GPIO_EXT_PORTA_s ALT_MON_GPIO_EXT_PORTA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_EXT_PORTA register from the beginning of the component. */ +#define ALT_MON_GPIO_EXT_PORTA_OFST 0x50 +/* The address of the ALT_MON_GPIO_EXT_PORTA register. */ +#define ALT_MON_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_EXT_PORTA_OFST)) + +/* + * Register : Synchronization Level Register - gpio_ls_sync + * + * The Synchronization level register is used to synchronize inputs to the + * l4_mp_clk. All MON interrupts are already synchronized before the GPIO instance + * so it is not necessary to setup this register to enable synchronization. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | Synchronization Level Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Synchronization Level Field - gpio_ls_sync + * + * The level-sensitive interrupts is synchronized to l4_mp_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------- + * ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC | 0x0 | No synchronization to l4_mp_clk + * ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC | 0x1 | Synchronize to l4_mp_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC + * + * No synchronization to l4_mp_clk + */ +#define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC 0x0 +/* + * Enumerated value for register field ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC + * + * Synchronize to l4_mp_clk + */ +#define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0 +/* The width in bits of the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */ +#define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001 +/* The mask used to clear the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */ +#define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe +/* The reset value of the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0 +/* Extracts the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */ +#define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */ +#define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_LS_SYNC. + */ +struct ALT_MON_GPIO_LS_SYNC_s +{ + uint32_t gpio_ls_sync : 1; /* Synchronization Level Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_LS_SYNC. */ +typedef volatile struct ALT_MON_GPIO_LS_SYNC_s ALT_MON_GPIO_LS_SYNC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_LS_SYNC register from the beginning of the component. */ +#define ALT_MON_GPIO_LS_SYNC_OFST 0x60 +/* The address of the ALT_MON_GPIO_LS_SYNC register. */ +#define ALT_MON_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_LS_SYNC_OFST)) + +/* + * Register : GPIO Version Register - gpio_ver_id_code + * + * GPIO Component Version + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------------------------ + * [31:0] | R | 0x3230382a | ASCII Component Version Field + * + */ +/* + * Field : ASCII Component Version Field - gpio_ver_id_code + * + * ASCII value for each number in the version, followed by *. For example. + * 32_30_31_2A represents the version 2.01 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31 +/* The width in bits of the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32 +/* The mask used to set the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */ +#define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */ +#define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000 +/* The reset value of the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3230382a +/* Extracts the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */ +#define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */ +#define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_VER_ID_CODE. + */ +struct ALT_MON_GPIO_VER_ID_CODE_s +{ + const uint32_t gpio_ver_id_code : 32; /* ASCII Component Version Field */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_VER_ID_CODE. */ +typedef volatile struct ALT_MON_GPIO_VER_ID_CODE_s ALT_MON_GPIO_VER_ID_CODE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_VER_ID_CODE register from the beginning of the component. */ +#define ALT_MON_GPIO_VER_ID_CODE_OFST 0x6c +/* The address of the ALT_MON_GPIO_VER_ID_CODE register. */ +#define ALT_MON_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_VER_ID_CODE_OFST)) + +/* + * Register : Configuration Register 2 - gpio_config_reg2 + * + * Specifies the bit width of port A. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------- + * [4:0] | R | 0xb | Port A Width (less 1) + * [9:5] | R | 0x7 | Port B Width (less 1) + * [14:10] | R | 0x7 | Port C Width (less 1) + * [19:15] | R | 0x7 | Port D Width (less 1) + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port A Width (less 1) - encoded_id_pwidth_a + * + * Specifies the width of GPIO Port A. The value 11 represents the 12-bit width + * less one. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------------|:------|:-------------------------- + * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE12BITS | 0xb | Width (less 1) of 12 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A + * + * Width (less 1) of 8 bits + */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A + * + * Width (less 1) of 12 bits + */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE12BITS 0xb + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB 4 +/* The width in bits of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH 5 +/* The mask used to set the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK 0x0000001f +/* The mask used to clear the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET 0xb +/* Extracts the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f) + +/* + * Field : Port B Width (less 1) - encoded_id_pwidth_b + * + * Specifies the width of GPIO Port B. Ignored because there is no Port B in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------------|:------|:-------------------------- + * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE12BITS | 0xb | Width (less 1) of 12 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B + * + * Width (less 1) of 8 bits + */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B + * + * Width (less 1) of 12 bits + */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE12BITS 0xb + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB 9 +/* The width in bits of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH 5 +/* The mask used to set the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK 0x000003e0 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK 0xfffffc1f +/* The reset value of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET 0x7 +/* Extracts the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5) +/* Produces a ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0) + +/* + * Field : Port C Width (less 1) - encoded_id_pwidth_c + * + * Specifies the width of GPIO Port C. Ignored because there is no Port C in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------------|:------|:-------------------------- + * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE12BITS | 0xb | Width (less 1) of 12 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C + * + * Width (less 1) of 8 bits + */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C + * + * Width (less 1) of 12 bits + */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE12BITS 0xb + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB 14 +/* The width in bits of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH 5 +/* The mask used to set the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK 0x00007c00 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK 0xffff83ff +/* The reset value of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET 0x7 +/* Extracts the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10) +/* Produces a ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00) + +/* + * Field : Port D Width (less 1) - encoded_id_pwidth_d + * + * Specifies the width of GPIO Port D. Ignored because there is no Port D in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------------|:------|:-------------------------- + * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE12BITS | 0xb | Width (less 1) of 12 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D + * + * Width (less 1) of 8 bits + */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D + * + * Width (less 1) of 12 bits + */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE12BITS 0xb + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB 19 +/* The width in bits of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH 5 +/* The mask used to set the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK 0x000f8000 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK 0xfff07fff +/* The reset value of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET 0x7 +/* Extracts the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15) +/* Produces a ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_CFG_REG2. + */ +struct ALT_MON_GPIO_CFG_REG2_s +{ + const uint32_t encoded_id_pwidth_a : 5; /* Port A Width (less 1) */ + const uint32_t encoded_id_pwidth_b : 5; /* Port B Width (less 1) */ + const uint32_t encoded_id_pwidth_c : 5; /* Port C Width (less 1) */ + const uint32_t encoded_id_pwidth_d : 5; /* Port D Width (less 1) */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_CFG_REG2. */ +typedef volatile struct ALT_MON_GPIO_CFG_REG2_s ALT_MON_GPIO_CFG_REG2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_CFG_REG2 register from the beginning of the component. */ +#define ALT_MON_GPIO_CFG_REG2_OFST 0x70 +/* The address of the ALT_MON_GPIO_CFG_REG2 register. */ +#define ALT_MON_GPIO_CFG_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_CFG_REG2_OFST)) + +/* + * Register : Configuration Register 1 - gpio_config_reg1 + * + * Reports settings of various GPIO configuration parameters + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [1:0] | R | 0x2 | APB DATA WIDTH + * [3:2] | R | 0x0 | NUM PORTS + * [4] | R | 0x1 | PORT A SINGLE CTL + * [5] | R | 0x1 | PORT B SINGLE CTL + * [6] | R | 0x1 | PORT C SINGLE CTL + * [7] | R | 0x1 | PORT D SINGLE CTL + * [8] | R | 0x0 | HW PORTA + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [12] | R | 0x1 | Port A Interrupt Field + * [13] | R | 0x0 | Debounce Field + * [14] | R | 0x1 | Encoded GPIO Parameters Available + * [15] | R | 0x0 | ID Field + * [20:16] | R | 0x1f | Encoded ID Width Field + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB DATA WIDTH - apb_data_width + * + * Fixed to support an APB data bus width of 32-bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------------- + * ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH + * + * APB Data Width = 32-bits + */ +#define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */ +#define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */ +#define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2 +/* Extracts the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : NUM PORTS - num_ports + * + * The value of this register is fixed at one port (Port A). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------- + * ALT_MON_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA | 0x0 | Number of GPIO Ports = 1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_NUM_PORTS + * + * Number of GPIO Ports = 1 + */ +#define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_MSB 3 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field value. */ +#define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field value. */ +#define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0 +/* Extracts the ALT_MON_GPIO_CFG_REG1_NUM_PORTS field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : PORT A SINGLE CTL - porta_single_ctl + * + * Indicates the mode of operation of Port A to be software controlled only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:----------------------------------------- + * ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef +/* The reset value of the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : PORT B SINGLE CTL - portb_single_ctl + * + * Indicates the mode of operation of Port B to be software controlled only. + * Ignored because there is no Port B in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:----------------------------------------- + * ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */ +#define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */ +#define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : PORT C SINGLE CTL - portc_single_ctl + * + * Indicates the mode of operation of Port C to be software controlled only. + * Ignored because there is no Port C in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:----------------------------------------- + * ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */ +#define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */ +#define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : PORT D SINGLE CTL - portd_single_ctl + * + * Indicates the mode of operation of Port D to be software controlled only. + * Ignored because there is no Port D in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:----------------------------------------- + * ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */ +#define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */ +#define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f +/* The reset value of the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : HW PORTA - hw_porta + * + * The value is fixed to enable Port A configuration to be controlled by software + * only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:--------------------------------------- + * ALT_MON_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD | 0x0 | Software Configuration Control Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_HW_PORTA + * + * Software Configuration Control Enabled + */ +#define ALT_MON_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_MON_GPIO_CFG_REG1_HW_PORTA_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_MON_GPIO_CFG_REG1_HW_PORTA_MSB 8 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_MON_GPIO_CFG_REG1_HW_PORTA_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field value. */ +#define ALT_MON_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field value. */ +#define ALT_MON_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff +/* The reset value of the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_MON_GPIO_CFG_REG1_HW_PORTA_RESET 0x0 +/* Extracts the ALT_MON_GPIO_CFG_REG1_HW_PORTA field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_MON_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Port A Interrupt Field - porta_intr + * + * The value of this field is fixed to allow interrupts on Port A. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:-------------------------- + * ALT_MON_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR | 0x1 | Port A Interrupts Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_PORTA_INTR + * + * Port A Interrupts Enabled + */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_MSB 12 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field value. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field value. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff +/* The reset value of the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1 +/* Extracts the ALT_MON_GPIO_CFG_REG1_PORTA_INTR field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Debounce Field - debounce + * + * The value of this field is fixed to not allow debouncing of the Port A signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------- + * ALT_MON_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA_DISD | 0x0 | Debounce is Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_DEBOUNCE + * + * Debounce is Disabled + */ +#define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_MSB 13 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field value. */ +#define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field value. */ +#define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_RESET 0x0 +/* Extracts the ALT_MON_GPIO_CFG_REG1_DEBOUNCE field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Encoded GPIO Parameters Available - add_encoded_params + * + * Fixed to allow the indentification of the Designware IP component. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:-------------------------- + * ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Enable IP indentification + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS + * + * Enable IP indentification + */ +#define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */ +#define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */ +#define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff +/* The reset value of the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1 +/* Extracts the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : ID Field - gpio_id + * + * Provides an ID code value + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------------- + * ALT_MON_GPIO_CFG_REG1_GPIO_ID_E_IDCODE_EXCLUDED | 0x0 | GPIO ID Code Register Excluded + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_GPIO_ID + * + * GPIO ID Code Register Excluded + */ +#define ALT_MON_GPIO_CFG_REG1_GPIO_ID_E_IDCODE_EXCLUDED 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_MON_GPIO_CFG_REG1_GPIO_ID_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_MON_GPIO_CFG_REG1_GPIO_ID_MSB 15 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_MON_GPIO_CFG_REG1_GPIO_ID_WIDTH 1 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field value. */ +#define ALT_MON_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field value. */ +#define ALT_MON_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff +/* The reset value of the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_MON_GPIO_CFG_REG1_GPIO_ID_RESET 0x0 +/* Extracts the ALT_MON_GPIO_CFG_REG1_GPIO_ID field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_MON_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Encoded ID Width Field - encoded_id_width + * + * This value is fixed at 32 bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------ + * ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH | 0x1f | Width of ID Field + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH + * + * Width of ID Field + */ +#define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f + +/* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20 +/* The width in bits of the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5 +/* The mask used to set the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */ +#define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000 +/* The mask used to clear the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */ +#define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff +/* The reset value of the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f +/* Extracts the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */ +#define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16) +/* Produces a ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */ +#define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MON_GPIO_CFG_REG1. + */ +struct ALT_MON_GPIO_CFG_REG1_s +{ + const uint32_t apb_data_width : 2; /* APB DATA WIDTH */ + const uint32_t num_ports : 2; /* NUM PORTS */ + const uint32_t porta_single_ctl : 1; /* PORT A SINGLE CTL */ + const uint32_t portb_single_ctl : 1; /* PORT B SINGLE CTL */ + const uint32_t portc_single_ctl : 1; /* PORT C SINGLE CTL */ + const uint32_t portd_single_ctl : 1; /* PORT D SINGLE CTL */ + const uint32_t hw_porta : 1; /* HW PORTA */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t porta_intr : 1; /* Port A Interrupt Field */ + const uint32_t debounce : 1; /* Debounce Field */ + const uint32_t add_encoded_params : 1; /* Encoded GPIO Parameters Available */ + const uint32_t gpio_id : 1; /* ID Field */ + const uint32_t encoded_id_width : 5; /* Encoded ID Width Field */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_MON_GPIO_CFG_REG1. */ +typedef volatile struct ALT_MON_GPIO_CFG_REG1_s ALT_MON_GPIO_CFG_REG1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MON_GPIO_CFG_REG1 register from the beginning of the component. */ +#define ALT_MON_GPIO_CFG_REG1_OFST 0x74 +/* The address of the ALT_MON_GPIO_CFG_REG1 register. */ +#define ALT_MON_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_CFG_REG1_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_MON. + */ +struct ALT_MON_s +{ + volatile uint32_t _pad_0x0_0x2f[12]; /* *UNDEFINED* */ + volatile ALT_MON_GPIO_INTEN_t gpio_inten; /* ALT_MON_GPIO_INTEN */ + volatile ALT_MON_GPIO_INTMSK_t gpio_intmask; /* ALT_MON_GPIO_INTMSK */ + volatile ALT_MON_GPIO_INTTYPE_LEVEL_t gpio_inttype_level; /* ALT_MON_GPIO_INTTYPE_LEVEL */ + volatile ALT_MON_GPIO_INT_POL_t gpio_int_polarity; /* ALT_MON_GPIO_INT_POL */ + volatile ALT_MON_GPIO_INTSTAT_t gpio_intstatus; /* ALT_MON_GPIO_INTSTAT */ + volatile ALT_MON_GPIO_RAW_INTSTAT_t gpio_raw_intstatus; /* ALT_MON_GPIO_RAW_INTSTAT */ + volatile uint32_t _pad_0x48_0x4b; /* *UNDEFINED* */ + volatile ALT_MON_GPIO_PORTA_EOI_t gpio_porta_eoi; /* ALT_MON_GPIO_PORTA_EOI */ + volatile ALT_MON_GPIO_EXT_PORTA_t gpio_ext_porta; /* ALT_MON_GPIO_EXT_PORTA */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile ALT_MON_GPIO_LS_SYNC_t gpio_ls_sync; /* ALT_MON_GPIO_LS_SYNC */ + volatile uint32_t _pad_0x64_0x6b[2]; /* *UNDEFINED* */ + volatile ALT_MON_GPIO_VER_ID_CODE_t gpio_ver_id_code; /* ALT_MON_GPIO_VER_ID_CODE */ + volatile ALT_MON_GPIO_CFG_REG2_t gpio_config_reg2; /* ALT_MON_GPIO_CFG_REG2 */ + volatile ALT_MON_GPIO_CFG_REG1_t gpio_config_reg1; /* ALT_MON_GPIO_CFG_REG1 */ + volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_MON. */ +typedef volatile struct ALT_MON_s ALT_MON_t; +/* The struct declaration for the raw register contents of register group ALT_MON. */ +struct ALT_MON_raw_s +{ + volatile uint32_t _pad_0x0_0x2f[12]; /* *UNDEFINED* */ + volatile uint32_t gpio_inten; /* ALT_MON_GPIO_INTEN */ + volatile uint32_t gpio_intmask; /* ALT_MON_GPIO_INTMSK */ + volatile uint32_t gpio_inttype_level; /* ALT_MON_GPIO_INTTYPE_LEVEL */ + volatile uint32_t gpio_int_polarity; /* ALT_MON_GPIO_INT_POL */ + volatile uint32_t gpio_intstatus; /* ALT_MON_GPIO_INTSTAT */ + volatile uint32_t gpio_raw_intstatus; /* ALT_MON_GPIO_RAW_INTSTAT */ + volatile uint32_t _pad_0x48_0x4b; /* *UNDEFINED* */ + volatile uint32_t gpio_porta_eoi; /* ALT_MON_GPIO_PORTA_EOI */ + volatile uint32_t gpio_ext_porta; /* ALT_MON_GPIO_EXT_PORTA */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile uint32_t gpio_ls_sync; /* ALT_MON_GPIO_LS_SYNC */ + volatile uint32_t _pad_0x64_0x6b[2]; /* *UNDEFINED* */ + volatile uint32_t gpio_ver_id_code; /* ALT_MON_GPIO_VER_ID_CODE */ + volatile uint32_t gpio_config_reg2; /* ALT_MON_GPIO_CFG_REG2 */ + volatile uint32_t gpio_config_reg1; /* ALT_MON_GPIO_CFG_REG1 */ + volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_MON. */ +typedef volatile struct ALT_MON_raw_s ALT_MON_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_FPGAMGR. + */ +struct ALT_FPGAMGR_s +{ + volatile ALT_FPGAMGR_STAT_t stat; /* ALT_FPGAMGR_STAT */ + volatile ALT_FPGAMGR_CTL_t ctrl; /* ALT_FPGAMGR_CTL */ + volatile ALT_FPGAMGR_DCLKCNT_t dclkcnt; /* ALT_FPGAMGR_DCLKCNT */ + volatile ALT_FPGAMGR_DCLKSTAT_t dclkstat; /* ALT_FPGAMGR_DCLKSTAT */ + volatile ALT_FPGAMGR_GPO_t gpo; /* ALT_FPGAMGR_GPO */ + volatile ALT_FPGAMGR_GPI_t gpi; /* ALT_FPGAMGR_GPI */ + volatile ALT_FPGAMGR_MISCI_t misci; /* ALT_FPGAMGR_MISCI */ + volatile uint32_t _pad_0x1c_0x7ff[505]; /* *UNDEFINED* */ + volatile ALT_MON_t mon; /* ALT_MON */ + volatile uint32_t _pad_0x880_0x1000[480]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_FPGAMGR. */ +typedef volatile struct ALT_FPGAMGR_s ALT_FPGAMGR_t; +/* The struct declaration for the raw register contents of register group ALT_FPGAMGR. */ +struct ALT_FPGAMGR_raw_s +{ + volatile uint32_t stat; /* ALT_FPGAMGR_STAT */ + volatile uint32_t ctrl; /* ALT_FPGAMGR_CTL */ + volatile uint32_t dclkcnt; /* ALT_FPGAMGR_DCLKCNT */ + volatile uint32_t dclkstat; /* ALT_FPGAMGR_DCLKSTAT */ + volatile uint32_t gpo; /* ALT_FPGAMGR_GPO */ + volatile uint32_t gpi; /* ALT_FPGAMGR_GPI */ + volatile uint32_t misci; /* ALT_FPGAMGR_MISCI */ + volatile uint32_t _pad_0x1c_0x7ff[505]; /* *UNDEFINED* */ + volatile ALT_MON_raw_t mon; /* ALT_MON */ + volatile uint32_t _pad_0x880_0x1000[480]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_FPGAMGR. */ +typedef volatile struct ALT_FPGAMGR_raw_s ALT_FPGAMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_FPGAMGR_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_fpgamgrdata.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_fpgamgrdata.h new file mode 100644 index 000000000..e5eb09dd4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_fpgamgrdata.h @@ -0,0 +1,158 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_FPGAMGRDATA */ + +#ifndef __ALTERA_ALT_FPGAMGRDATA_H__ +#define __ALTERA_ALT_FPGAMGRDATA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : FPGA Manager Module Configuration Data - ALT_FPGAMGRDATA + * FPGA Manager Module Configuration Data + * + * Registers in the FPGA Manager module accessible via its AXI slave + * + */ +/* + * Register : Write Data Register - data + * + * Used to send configuration image to FPGA. + * + * The DATA register accepts 4 bytes of the configuration image on each write. The + * configuration image byte-stream is converted into a 4-byte word with little- + * endian ordering. If the configuration image is not an integer multiple of 4 + * bytes, software should pad the configuration image with extra zero bytes to make + * it an integer multiple of 4 bytes. + * + * The FPGA Manager converts the DATA to 16 bits wide when writing CB.DATA for + * partial reconfiguration. + * + * The FPGA Manager waits to transmit the data to the CB until the FPGA is able to + * receive it. For a full configuration, the FPGA Manager waits until the FPGA + * exits the Reset Phase and enters the Configuration Phase. For a partial + * reconfiguration, the FPGA Manager waits until the CB.PR_READY signal indicates + * that the FPGA is ready. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------- + * [31:0] | RW | Unknown | Write Data Value + * + */ +/* + * Field : Write Data Value - value + * + * Accepts configuration image to be sent to CB when the HPS configures the FPGA. + * Software normally just writes this register. If software reads this register, it + * returns the value 0 and replies with an AXI SLVERR error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_FPGAMGRDATA_DATA_VALUE register field. */ +#define ALT_FPGAMGRDATA_DATA_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_FPGAMGRDATA_DATA_VALUE register field. */ +#define ALT_FPGAMGRDATA_DATA_VALUE_MSB 31 +/* The width in bits of the ALT_FPGAMGRDATA_DATA_VALUE register field. */ +#define ALT_FPGAMGRDATA_DATA_VALUE_WIDTH 32 +/* The mask used to set the ALT_FPGAMGRDATA_DATA_VALUE register field value. */ +#define ALT_FPGAMGRDATA_DATA_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_FPGAMGRDATA_DATA_VALUE register field value. */ +#define ALT_FPGAMGRDATA_DATA_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_FPGAMGRDATA_DATA_VALUE register field is UNKNOWN. */ +#define ALT_FPGAMGRDATA_DATA_VALUE_RESET 0x0 +/* Extracts the ALT_FPGAMGRDATA_DATA_VALUE field value from a register. */ +#define ALT_FPGAMGRDATA_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_FPGAMGRDATA_DATA_VALUE register field value suitable for setting the register. */ +#define ALT_FPGAMGRDATA_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_FPGAMGRDATA_DATA. + */ +struct ALT_FPGAMGRDATA_DATA_s +{ + uint32_t value : 32; /* Write Data Value */ +}; + +/* The typedef declaration for register ALT_FPGAMGRDATA_DATA. */ +typedef volatile struct ALT_FPGAMGRDATA_DATA_s ALT_FPGAMGRDATA_DATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_FPGAMGRDATA_DATA register from the beginning of the component. */ +#define ALT_FPGAMGRDATA_DATA_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_FPGAMGRDATA. + */ +struct ALT_FPGAMGRDATA_s +{ + volatile ALT_FPGAMGRDATA_DATA_t data; /* ALT_FPGAMGRDATA_DATA */ +}; + +/* The typedef declaration for register group ALT_FPGAMGRDATA. */ +typedef volatile struct ALT_FPGAMGRDATA_s ALT_FPGAMGRDATA_t; +/* The struct declaration for the raw register contents of register group ALT_FPGAMGRDATA. */ +struct ALT_FPGAMGRDATA_raw_s +{ + volatile uint32_t data; /* ALT_FPGAMGRDATA_DATA */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_FPGAMGRDATA. */ +typedef volatile struct ALT_FPGAMGRDATA_raw_s ALT_FPGAMGRDATA_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_FPGAMGRDATA_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_gpio.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_gpio.h new file mode 100644 index 000000000..b72ffbce7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_gpio.h @@ -0,0 +1,1991 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_GPIO */ + +#ifndef __ALTERA_ALT_GPIO_H__ +#define __ALTERA_ALT_GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : GPIO Module - ALT_GPIO + * GPIO Module + * + * Registers in the GPIO module + * + */ +/* + * Register : Port A Data Register - gpio_swporta_dr + * + * This GPIO Data register is used to input or output data + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [28:0] | RW | 0x0 | Port A Data + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port A Data - gpio_swporta_dr + * + * Values written to this register are output on the I/O signals of the GPIO Data + * Register, if the corresponding data direction bits for GPIO Data Direction Field + * are set to Output mode. The value read back is equal to the last value written + * to this register. + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_MSB 28 +/* The width in bits of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_WIDTH 29 +/* The mask used to set the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_RESET 0x0 +/* Extracts the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR field value from a register. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value suitable for setting the register. */ +#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_SWPORTA_DR. + */ +struct ALT_GPIO_SWPORTA_DR_s +{ + uint32_t gpio_swporta_dr : 29; /* Port A Data */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_SWPORTA_DR. */ +typedef volatile struct ALT_GPIO_SWPORTA_DR_s ALT_GPIO_SWPORTA_DR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_SWPORTA_DR register from the beginning of the component. */ +#define ALT_GPIO_SWPORTA_DR_OFST 0x0 +/* The address of the ALT_GPIO_SWPORTA_DR register. */ +#define ALT_GPIO_SWPORTA_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DR_OFST)) + +/* + * Register : Port A Data Direction Register - gpio_swporta_ddr + * + * This register establishes the direction of each corresponding GPIO Data Field + * Bit. + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [28:0] | RW | 0x0 | Port A Data Direction Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port A Data Direction Field - gpio_swporta_ddr + * + * Values written to this register independently control the direction of the + * corresponding data bit in the Port A Data Register. + * + * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:----------------- + * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN | 0x0 | Input Direction + * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT | 0x1 | Output Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR + * + * Input Direction + */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN 0x0 +/* + * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR + * + * Output Direction + */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_MSB 28 +/* The width in bits of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_WIDTH 29 +/* The mask used to set the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_RESET 0x0 +/* Extracts the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR field value from a register. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value suitable for setting the register. */ +#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_SWPORTA_DDR. + */ +struct ALT_GPIO_SWPORTA_DDR_s +{ + uint32_t gpio_swporta_ddr : 29; /* Port A Data Direction Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_SWPORTA_DDR. */ +typedef volatile struct ALT_GPIO_SWPORTA_DDR_s ALT_GPIO_SWPORTA_DDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_SWPORTA_DDR register from the beginning of the component. */ +#define ALT_GPIO_SWPORTA_DDR_OFST 0x4 +/* The address of the ALT_GPIO_SWPORTA_DDR register. */ +#define ALT_GPIO_SWPORTA_DDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DDR_OFST)) + +/* + * Register : Interrupt Enable Register - gpio_inten + * + * The Interrupt enable register allows interrupts for each bit of the Port A data + * register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [28:0] | RW | 0x0 | Interrupt Enable Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Enable Field - gpio_inten + * + * Allows each bit of Port A Data Register to be configured for interrupt + * capability. Interrupts are disabled on the corresponding bits of Port A Data + * Register if the corresponding data direction register is set to Output. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------- + * ALT_GPIO_INTEN_GPIO_INTEN_E_DIS | 0x0 | Disable Interrupt on Port A + * ALT_GPIO_INTEN_GPIO_INTEN_E_EN | 0x1 | Enable Interrupt on Port A + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN + * + * Disable Interrupt on Port A + */ +#define ALT_GPIO_INTEN_GPIO_INTEN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN + * + * Enable Interrupt on Port A + */ +#define ALT_GPIO_INTEN_GPIO_INTEN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_MSB 28 +/* The width in bits of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTEN_GPIO_INTEN register field value. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTEN_GPIO_INTEN register field value. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_RESET 0x0 +/* Extracts the ALT_GPIO_INTEN_GPIO_INTEN field value from a register. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTEN_GPIO_INTEN register field value suitable for setting the register. */ +#define ALT_GPIO_INTEN_GPIO_INTEN_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTEN. + */ +struct ALT_GPIO_INTEN_s +{ + uint32_t gpio_inten : 29; /* Interrupt Enable Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTEN. */ +typedef volatile struct ALT_GPIO_INTEN_s ALT_GPIO_INTEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTEN register from the beginning of the component. */ +#define ALT_GPIO_INTEN_OFST 0x30 +/* The address of the ALT_GPIO_INTEN register. */ +#define ALT_GPIO_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTEN_OFST)) + +/* + * Register : Interrupt Mask Register - gpio_intmask + * + * Controls which pins cause interrupts on Port A Data Register inputs. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [28:0] | RW | 0x0 | Interrupt Mask Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Mask Field - gpio_intmask + * + * Controls whether an interrupt on Port A Data Register can generate an interrupt + * to the interrupt controller by not masking it. The unmasked status can be read + * as well as the resultant status after masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------- + * ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS | 0x0 | Interrupt bits are unmasked + * ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN | 0x1 | Mask Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK + * + * Interrupt bits are unmasked + */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK + * + * Mask Interrupt + */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_MSB 28 +/* The width in bits of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_RESET 0x0 +/* Extracts the ALT_GPIO_INTMSK_GPIO_INTMSK field value from a register. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTMSK_GPIO_INTMSK register field value suitable for setting the register. */ +#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTMSK. + */ +struct ALT_GPIO_INTMSK_s +{ + uint32_t gpio_intmask : 29; /* Interrupt Mask Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTMSK. */ +typedef volatile struct ALT_GPIO_INTMSK_s ALT_GPIO_INTMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTMSK register from the beginning of the component. */ +#define ALT_GPIO_INTMSK_OFST 0x34 +/* The address of the ALT_GPIO_INTMSK register. */ +#define ALT_GPIO_INTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTMSK_OFST)) + +/* + * Register : Interrupt Level Register - gpio_inttype_level + * + * The interrupt level register defines the type of interrupt (edge or level). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------- + * [28:0] | RW | 0x0 | Interrupt Level Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Level Field - gpio_inttype_level + * + * This field controls the type of interrupt that can occur on the Port A Data + * Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:---------------- + * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL | 0x0 | Level-sensitive + * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE | 0x1 | Edge-sensitive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL + * + * Level-sensitive + */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL + * + * Edge-sensitive + */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_MSB 28 +/* The width in bits of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_RESET 0x0 +/* Extracts the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL field value from a register. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value suitable for setting the register. */ +#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTTYPE_LEVEL. + */ +struct ALT_GPIO_INTTYPE_LEVEL_s +{ + uint32_t gpio_inttype_level : 29; /* Interrupt Level Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTTYPE_LEVEL. */ +typedef volatile struct ALT_GPIO_INTTYPE_LEVEL_s ALT_GPIO_INTTYPE_LEVEL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTTYPE_LEVEL register from the beginning of the component. */ +#define ALT_GPIO_INTTYPE_LEVEL_OFST 0x38 +/* The address of the ALT_GPIO_INTTYPE_LEVEL register. */ +#define ALT_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTTYPE_LEVEL_OFST)) + +/* + * Register : Interrupt Polarity Register - gpio_int_polarity + * + * Controls the Polarity of Interrupts that can occur on inputs of Port A Data + * Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [28:0] | RW | 0x0 | Polarity Control Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Polarity Control Field - gpio_int_polarity + * + * Controls the polarity of edge or level sensitivity that can occur on input of + * Port A Data Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------ + * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW | 0x0 | Active low + * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH | 0x1 | Active high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL + * + * Active low + */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW 0x0 +/* + * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL + * + * Active high + */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_MSB 28 +/* The width in bits of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_WIDTH 29 +/* The mask used to set the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_RESET 0x0 +/* Extracts the ALT_GPIO_INT_POL_GPIO_INT_POL field value from a register. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INT_POL_GPIO_INT_POL register field value suitable for setting the register. */ +#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INT_POL. + */ +struct ALT_GPIO_INT_POL_s +{ + uint32_t gpio_int_polarity : 29; /* Polarity Control Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INT_POL. */ +typedef volatile struct ALT_GPIO_INT_POL_s ALT_GPIO_INT_POL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INT_POL register from the beginning of the component. */ +#define ALT_GPIO_INT_POL_OFST 0x3c +/* The address of the ALT_GPIO_INT_POL register. */ +#define ALT_GPIO_INT_POL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INT_POL_OFST)) + +/* + * Register : Interrupt Status Register - gpio_intstatus + * + * The Interrupt status is reported for all Port A Data Register Bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [28:0] | RW | 0x0 | Interrupt Status Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Status Field - gpio_intstatus + * + * Interrupt status of Port A Data Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------ + * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT | 0x0 | Inactive + * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT + * + * Inactive + */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT + * + * Active + */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_MSB 28 +/* The width in bits of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_WIDTH 29 +/* The mask used to set the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_RESET 0x0 +/* Extracts the ALT_GPIO_INTSTAT_GPIO_INTSTAT field value from a register. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value suitable for setting the register. */ +#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_INTSTAT. + */ +struct ALT_GPIO_INTSTAT_s +{ + uint32_t gpio_intstatus : 29; /* Interrupt Status Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_INTSTAT. */ +typedef volatile struct ALT_GPIO_INTSTAT_s ALT_GPIO_INTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_INTSTAT register from the beginning of the component. */ +#define ALT_GPIO_INTSTAT_OFST 0x40 +/* The address of the ALT_GPIO_INTSTAT register. */ +#define ALT_GPIO_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTSTAT_OFST)) + +/* + * Register : Raw Interrupt Status Register - gpio_raw_intstatus + * + * This is the Raw Interrupt Status Register for Port A Data Register. It is used + * with the Interrupt Mask Register to allow interrupts from the Port A Data + * Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [28:0] | RW | 0x0 | Raw Interrupt Status Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Raw Interrupt Status Field - gpio_raw_intstatus + * + * Raw interrupt of status of Port A Data Register (premasking bits) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------ + * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT | 0x0 | Inactive + * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT | 0x1 | Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT + * + * Inactive + */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT + * + * Active + */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_MSB 28 +/* The width in bits of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_WIDTH 29 +/* The mask used to set the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_RESET 0x0 +/* Extracts the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT field value from a register. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value suitable for setting the register. */ +#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_RAW_INTSTAT. + */ +struct ALT_GPIO_RAW_INTSTAT_s +{ + uint32_t gpio_raw_intstatus : 29; /* Raw Interrupt Status Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_RAW_INTSTAT. */ +typedef volatile struct ALT_GPIO_RAW_INTSTAT_s ALT_GPIO_RAW_INTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_RAW_INTSTAT register from the beginning of the component. */ +#define ALT_GPIO_RAW_INTSTAT_OFST 0x44 +/* The address of the ALT_GPIO_RAW_INTSTAT register. */ +#define ALT_GPIO_RAW_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_RAW_INTSTAT_OFST)) + +/* + * Register : Debounce Enable Register - gpio_debounce + * + * Debounces each IO Pin + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [28:0] | RW | 0x0 | ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : gpio_debounce + * + * Controls whether an external signal that is the source of an interrupt needs to + * be debounced to remove any spurious glitches. A signal must be valid for two + * periods of an external clock (gpio_db_clk) before it is internally processed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------- + * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS | 0x0 | No debounce + * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN | 0x1 | Enable debounce + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE + * + * No debounce + */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE + * + * Enable debounce + */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_MSB 28 +/* The width in bits of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_WIDTH 29 +/* The mask used to set the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_RESET 0x0 +/* Extracts the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE field value from a register. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value suitable for setting the register. */ +#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_DEBOUNCE. + */ +struct ALT_GPIO_DEBOUNCE_s +{ + uint32_t gpio_debounce : 29; /* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_DEBOUNCE. */ +typedef volatile struct ALT_GPIO_DEBOUNCE_s ALT_GPIO_DEBOUNCE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_DEBOUNCE register from the beginning of the component. */ +#define ALT_GPIO_DEBOUNCE_OFST 0x48 +/* The address of the ALT_GPIO_DEBOUNCE register. */ +#define ALT_GPIO_DEBOUNCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_DEBOUNCE_OFST)) + +/* + * Register : Clear Interrupt Register - gpio_porta_eoi + * + * Port A Data Register interrupt handling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [28:0] | W | 0x0 | Clears Edge Interrupts Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clears Edge Interrupts Field - gpio_porta_eoi + * + * Controls the clearing of edge type interrupts from the Port A Data Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------- + * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR | 0x0 | No interrupt clear + * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR | 0x1 | Clear interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI + * + * No interrupt clear + */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI + * + * Clear interrupt + */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_MSB 28 +/* The width in bits of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_WIDTH 29 +/* The mask used to set the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_RESET 0x0 +/* Extracts the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI field value from a register. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value suitable for setting the register. */ +#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_PORTA_EOI. + */ +struct ALT_GPIO_PORTA_EOI_s +{ + uint32_t gpio_porta_eoi : 29; /* Clears Edge Interrupts Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_PORTA_EOI. */ +typedef volatile struct ALT_GPIO_PORTA_EOI_s ALT_GPIO_PORTA_EOI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_PORTA_EOI register from the beginning of the component. */ +#define ALT_GPIO_PORTA_EOI_OFST 0x4c +/* The address of the ALT_GPIO_PORTA_EOI register. */ +#define ALT_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_PORTA_EOI_OFST)) + +/* + * Register : External Port A Register - gpio_ext_porta + * + * The external port register is used to input data to the metastability flops. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [28:0] | R | 0x0 | External Port Field + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : External Port Field - gpio_ext_porta + * + * When Port A Data Register is configured as Input, then reading this location + * reads the values on the signals. When the data direction of Port A Data Register + * is set as Output, reading this location reads Port A Data Register + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_MSB 28 +/* The width in bits of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_WIDTH 29 +/* The mask used to set the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET_MSK 0x1fffffff +/* The mask used to clear the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_CLR_MSK 0xe0000000 +/* The reset value of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_RESET 0x0 +/* Extracts the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA field value from a register. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_GET(value) (((value) & 0x1fffffff) >> 0) +/* Produces a ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value suitable for setting the register. */ +#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET(value) (((value) << 0) & 0x1fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_EXT_PORTA. + */ +struct ALT_GPIO_EXT_PORTA_s +{ + const uint32_t gpio_ext_porta : 29; /* External Port Field */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_EXT_PORTA. */ +typedef volatile struct ALT_GPIO_EXT_PORTA_s ALT_GPIO_EXT_PORTA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_EXT_PORTA register from the beginning of the component. */ +#define ALT_GPIO_EXT_PORTA_OFST 0x50 +/* The address of the ALT_GPIO_EXT_PORTA register. */ +#define ALT_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_EXT_PORTA_OFST)) + +/* + * Register : Synchronization Level Register - gpio_ls_sync + * + * The Synchronization level register is used to synchronize input with l4_mp_clk + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | Synchronization Level Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Synchronization Level Field - gpio_ls_sync + * + * The level-sensitive interrupts is synchronized to l4_mp_clk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------- + * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC | 0x0 | No synchronization to l4_mp_clk + * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC | 0x1 | Synchronize to l4_mp_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC + * + * No synchronization to l4_mp_clk + */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC 0x0 +/* + * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC + * + * Synchronize to l4_mp_clk + */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0 +/* The width in bits of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1 +/* The mask used to set the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001 +/* The mask used to clear the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe +/* The reset value of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0 +/* Extracts the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */ +#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_LS_SYNC. + */ +struct ALT_GPIO_LS_SYNC_s +{ + uint32_t gpio_ls_sync : 1; /* Synchronization Level Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_LS_SYNC. */ +typedef volatile struct ALT_GPIO_LS_SYNC_s ALT_GPIO_LS_SYNC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_LS_SYNC register from the beginning of the component. */ +#define ALT_GPIO_LS_SYNC_OFST 0x60 +/* The address of the ALT_GPIO_LS_SYNC register. */ +#define ALT_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_LS_SYNC_OFST)) + +/* + * Register : ID Code Register - gpio_id_code + * + * GPIO ID code. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [31:0] | R | 0x0 | ID Code Field + * + */ +/* + * Field : ID Code Field - gpio_id_code + * + * Chip identification + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_MSB 31 +/* The width in bits of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_WIDTH 32 +/* The mask used to set the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_CLR_MSK 0x00000000 +/* The reset value of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_RESET 0x0 +/* Extracts the ALT_GPIO_ID_CODE_GPIO_ID_CODE field value from a register. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value suitable for setting the register. */ +#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_ID_CODE. + */ +struct ALT_GPIO_ID_CODE_s +{ + const uint32_t gpio_id_code : 32; /* ID Code Field */ +}; + +/* The typedef declaration for register ALT_GPIO_ID_CODE. */ +typedef volatile struct ALT_GPIO_ID_CODE_s ALT_GPIO_ID_CODE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_ID_CODE register from the beginning of the component. */ +#define ALT_GPIO_ID_CODE_OFST 0x64 +/* The address of the ALT_GPIO_ID_CODE register. */ +#define ALT_GPIO_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_ID_CODE_OFST)) + +/* + * Register : GPIO Version Register - gpio_ver_id_code + * + * GPIO Component Version + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------------------------ + * [31:0] | R | 0x3230382a | ASCII Component Version Field + * + */ +/* + * Field : ASCII Component Version Field - gpio_ver_id_code + * + * ASCII value for each number in the version, followed by *. For example. + * 32_30_31_2A represents the version 2.01 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31 +/* The width in bits of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32 +/* The mask used to set the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000 +/* The reset value of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3230382a +/* Extracts the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */ +#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_VER_ID_CODE. + */ +struct ALT_GPIO_VER_ID_CODE_s +{ + const uint32_t gpio_ver_id_code : 32; /* ASCII Component Version Field */ +}; + +/* The typedef declaration for register ALT_GPIO_VER_ID_CODE. */ +typedef volatile struct ALT_GPIO_VER_ID_CODE_s ALT_GPIO_VER_ID_CODE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_VER_ID_CODE register from the beginning of the component. */ +#define ALT_GPIO_VER_ID_CODE_OFST 0x6c +/* The address of the ALT_GPIO_VER_ID_CODE register. */ +#define ALT_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_VER_ID_CODE_OFST)) + +/* + * Register : Configuration Register 2 - gpio_config_reg2 + * + * Specifies the bit width of port A. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------- + * [4:0] | R | 0x1c | Port A Width (less 1) + * [9:5] | R | 0x7 | Port B Width (less 1) + * [14:10] | R | 0x7 | Port C Width (less 1) + * [19:15] | R | 0x7 | Port D Width (less 1) + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port A Width (less 1) - encoded_id_pwidth_a + * + * Specifies the width of GPIO Port A. The value 28 represents the 29-bit width + * less one. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB 4 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK 0x0000001f +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET 0x1c +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f) + +/* + * Field : Port B Width (less 1) - encoded_id_pwidth_b + * + * Specifies the width of GPIO Port B. Ignored because there is no Port B in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB 9 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK 0x000003e0 +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK 0xfffffc1f +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET 0x7 +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0) + +/* + * Field : Port C Width (less 1) - encoded_id_pwidth_c + * + * Specifies the width of GPIO Port C. Ignored because there is no Port C in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB 14 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK 0x00007c00 +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK 0xffff83ff +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET 0x7 +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00) + +/* + * Field : Port D Width (less 1) - encoded_id_pwidth_d + * + * Specifies the width of GPIO Port D. Ignored because there is no Port D in the + * GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits + * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D + * + * Width (less 1) of 8 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7 +/* + * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D + * + * Width (less 1) of 29 bits + */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS 0x1c + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB 19 +/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK 0x000f8000 +/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK 0xfff07fff +/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET 0x7 +/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15) +/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_CFG_REG2. + */ +struct ALT_GPIO_CFG_REG2_s +{ + const uint32_t encoded_id_pwidth_a : 5; /* Port A Width (less 1) */ + const uint32_t encoded_id_pwidth_b : 5; /* Port B Width (less 1) */ + const uint32_t encoded_id_pwidth_c : 5; /* Port C Width (less 1) */ + const uint32_t encoded_id_pwidth_d : 5; /* Port D Width (less 1) */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_CFG_REG2. */ +typedef volatile struct ALT_GPIO_CFG_REG2_s ALT_GPIO_CFG_REG2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_CFG_REG2 register from the beginning of the component. */ +#define ALT_GPIO_CFG_REG2_OFST 0x70 +/* The address of the ALT_GPIO_CFG_REG2 register. */ +#define ALT_GPIO_CFG_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG2_OFST)) + +/* + * Register : Configuration Register 1 - gpio_config_reg1 + * + * Reports settings of various GPIO configuration parameters + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [1:0] | R | 0x2 | APB DATA WIDTH + * [3:2] | R | 0x0 | NUM PORTS + * [4] | R | 0x1 | PORT A SINGLE CTL + * [5] | R | 0x1 | PORT B SINGLE CTL + * [6] | R | 0x1 | PORT C SINGLE CTL + * [7] | R | 0x1 | PORT D SINGLE CTL + * [8] | R | 0x0 | HW PORTA + * [11:9] | ??? | 0x0 | *UNDEFINED* + * [12] | R | 0x1 | Port A Interrupt Field + * [13] | R | 0x1 | Debounce Field + * [14] | R | 0x1 | Encoded GPIO Parameters Available + * [15] | R | 0x1 | ID Field + * [20:16] | R | 0x1f | Encoded ID Width Field + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB DATA WIDTH - apb_data_width + * + * Fixed to support an ABP data bus width of 32-bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------------- + * ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_APB_DATA_WIDTH + * + * APB Data Width = 32-bits + */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1 +/* The width in bits of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2 +/* The mask used to set the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2 +/* Extracts the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : NUM PORTS - num_ports + * + * The value of this register is fixed at one port (Port A). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------- + * ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA | 0x0 | Number of GPIO Ports = 1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_NUM_PORTS + * + * Number of GPIO Ports = 1 + */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_MSB 3 +/* The width in bits of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2 +/* The mask used to set the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c +/* The mask used to clear the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0 +/* Extracts the ALT_GPIO_CFG_REG1_NUM_PORTS field value from a register. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : PORT A SINGLE CTL - porta_single_ctl + * + * Indicates the mode of operation of Port A to be software controlled only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef +/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : PORT B SINGLE CTL - portb_single_ctl + * + * Indicates the mode of operation of Port B to be software controlled only. + * Ignored because there is no Port B in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : PORT C SINGLE CTL - portc_single_ctl + * + * Indicates the mode of operation of Port C to be software controlled only. + * Ignored because there is no Port C in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : PORT D SINGLE CTL - portd_single_ctl + * + * Indicates the mode of operation of Port D to be software controlled only. + * Ignored because there is no Port D in the GPIO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:----------------------------------------- + * ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL + * + * Software Enabled Individual Port Control + */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f +/* The reset value of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : HW PORTA - hw_porta + * + * The value is fixed to enable Port A configuration to be controlled by software + * only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------- + * ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD | 0x0 | Software Configuration Control Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_HW_PORTA + * + * Software Configuration Control Enabled + */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_MSB 8 +/* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100 +/* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff +/* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_RESET 0x0 +/* Extracts the ALT_GPIO_CFG_REG1_HW_PORTA field value from a register. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Port A Interrupt Field - porta_intr + * + * The value of this field is fixed to allow interrupts on Port A. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR | 0x1 | Port A Interrupts Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_INTR + * + * Port A Interrupts Enabled + */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_MSB 12 +/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff +/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_PORTA_INTR field value from a register. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Debounce Field - debounce + * + * The value of this field is fixed to allow debouncing of the Port A signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA | 0x1 | Debounce is Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_DEBOUNCE + * + * Debounce is Enabled + */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_MSB 13 +/* The width in bits of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_DEBOUNCE field value from a register. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Encoded GPIO Parameters Available - add_encoded_params + * + * Fixed to allow the indentification of the Designware IP component. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:-------------------------- + * ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Enable IP indentification + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS + * + * Enable IP indentification + */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14 +/* The width in bits of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff +/* The reset value of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : ID Field - gpio_id + * + * Provides an ID code value + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE | 0x1 | GPIO ID Code + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_GPIO_ID + * + * GPIO ID Code + */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_MSB 15 +/* The width in bits of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH 1 +/* The mask used to set the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff +/* The reset value of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_RESET 0x1 +/* Extracts the ALT_GPIO_CFG_REG1_GPIO_ID field value from a register. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Encoded ID Width Field - encoded_id_width + * + * This value is fixed at 32 bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH | 0x1f | Width of ID Field + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_GPIO_CFG_REG1_ENC_ID_WIDTH + * + * Width of ID Field + */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f + +/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20 +/* The width in bits of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5 +/* The mask used to set the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000 +/* The mask used to clear the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff +/* The reset value of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f +/* Extracts the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16) +/* Produces a ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */ +#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_GPIO_CFG_REG1. + */ +struct ALT_GPIO_CFG_REG1_s +{ + const uint32_t apb_data_width : 2; /* APB DATA WIDTH */ + const uint32_t num_ports : 2; /* NUM PORTS */ + const uint32_t porta_single_ctl : 1; /* PORT A SINGLE CTL */ + const uint32_t portb_single_ctl : 1; /* PORT B SINGLE CTL */ + const uint32_t portc_single_ctl : 1; /* PORT C SINGLE CTL */ + const uint32_t portd_single_ctl : 1; /* PORT D SINGLE CTL */ + const uint32_t hw_porta : 1; /* HW PORTA */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t porta_intr : 1; /* Port A Interrupt Field */ + const uint32_t debounce : 1; /* Debounce Field */ + const uint32_t add_encoded_params : 1; /* Encoded GPIO Parameters Available */ + const uint32_t gpio_id : 1; /* ID Field */ + const uint32_t encoded_id_width : 5; /* Encoded ID Width Field */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_GPIO_CFG_REG1. */ +typedef volatile struct ALT_GPIO_CFG_REG1_s ALT_GPIO_CFG_REG1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_GPIO_CFG_REG1 register from the beginning of the component. */ +#define ALT_GPIO_CFG_REG1_OFST 0x74 +/* The address of the ALT_GPIO_CFG_REG1 register. */ +#define ALT_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG1_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_GPIO. + */ +struct ALT_GPIO_s +{ + volatile ALT_GPIO_SWPORTA_DR_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */ + volatile ALT_GPIO_SWPORTA_DDR_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */ + volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */ + volatile ALT_GPIO_INTEN_t gpio_inten; /* ALT_GPIO_INTEN */ + volatile ALT_GPIO_INTMSK_t gpio_intmask; /* ALT_GPIO_INTMSK */ + volatile ALT_GPIO_INTTYPE_LEVEL_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */ + volatile ALT_GPIO_INT_POL_t gpio_int_polarity; /* ALT_GPIO_INT_POL */ + volatile ALT_GPIO_INTSTAT_t gpio_intstatus; /* ALT_GPIO_INTSTAT */ + volatile ALT_GPIO_RAW_INTSTAT_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */ + volatile ALT_GPIO_DEBOUNCE_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */ + volatile ALT_GPIO_PORTA_EOI_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */ + volatile ALT_GPIO_EXT_PORTA_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile ALT_GPIO_LS_SYNC_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */ + volatile ALT_GPIO_ID_CODE_t gpio_id_code; /* ALT_GPIO_ID_CODE */ + volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */ + volatile ALT_GPIO_VER_ID_CODE_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */ + volatile ALT_GPIO_CFG_REG2_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */ + volatile ALT_GPIO_CFG_REG1_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */ + volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_GPIO. */ +typedef volatile struct ALT_GPIO_s ALT_GPIO_t; +/* The struct declaration for the raw register contents of register group ALT_GPIO. */ +struct ALT_GPIO_raw_s +{ + volatile uint32_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */ + volatile uint32_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */ + volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */ + volatile uint32_t gpio_inten; /* ALT_GPIO_INTEN */ + volatile uint32_t gpio_intmask; /* ALT_GPIO_INTMSK */ + volatile uint32_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */ + volatile uint32_t gpio_int_polarity; /* ALT_GPIO_INT_POL */ + volatile uint32_t gpio_intstatus; /* ALT_GPIO_INTSTAT */ + volatile uint32_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */ + volatile uint32_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */ + volatile uint32_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */ + volatile uint32_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile uint32_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */ + volatile uint32_t gpio_id_code; /* ALT_GPIO_ID_CODE */ + volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */ + volatile uint32_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */ + volatile uint32_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */ + volatile uint32_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */ + volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_GPIO. */ +typedef volatile struct ALT_GPIO_raw_s ALT_GPIO_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_GPIO_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_h2f.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_h2f.h new file mode 100644 index 000000000..835850224 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_h2f.h @@ -0,0 +1,1073 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_H2F */ + +#ifndef __ALTERA_ALT_H2F_H__ +#define __ALTERA_ALT_H2F_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : HPS2FPGA AXI Bridge Module - ALT_H2F + * HPS2FPGA AXI Bridge Module + * + * Registers in the HPS2FPGA AXI Bridge Module. + * + */ +/* + * Register Group : ID Register Group - ALT_H2F_IDGRP + * ID Register Group + * + * Contains registers that identify the ARM NIC-301 IP Core. + * + */ +/* + * Register : Peripheral ID4 Register - periph_id_4 + * + * JEP106 continuation code + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [7:0] | R | 0x4 | Peripheral ID4 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Peripheral ID4 - periph_id_4 + * + * JEP106 continuation code + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7 +/* The width in bits of the ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8 +/* The mask used to set the ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4 +/* Extracts the ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */ +#define ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */ +#define ALT_H2F_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_ID_PERIPH_ID_4. + */ +struct ALT_H2F_ID_PERIPH_ID_4_s +{ + const uint32_t periph_id_4 : 8; /* Peripheral ID4 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_ID_PERIPH_ID_4. */ +typedef volatile struct ALT_H2F_ID_PERIPH_ID_4_s ALT_H2F_ID_PERIPH_ID_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_ID_PERIPH_ID_4 register from the beginning of the component. */ +#define ALT_H2F_ID_PERIPH_ID_4_OFST 0xfd0 + +/* + * Register : Peripheral ID0 Register - periph_id_0 + * + * Peripheral ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [7:0] | R | 0x1 | Part Number [7:0] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Part Number [7:0] - pn7to0 + * + * Part Number [7:0] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_H2F_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_H2F_ID_PERIPH_ID_0_PN7TO0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_H2F_ID_PERIPH_ID_0_PN7TO0_MSB 7 +/* The width in bits of the ALT_H2F_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_H2F_ID_PERIPH_ID_0_PN7TO0_WIDTH 8 +/* The mask used to set the ALT_H2F_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_H2F_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff +/* The mask used to clear the ALT_H2F_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_H2F_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00 +/* The reset value of the ALT_H2F_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_H2F_ID_PERIPH_ID_0_PN7TO0_RESET 0x1 +/* Extracts the ALT_H2F_ID_PERIPH_ID_0_PN7TO0 field value from a register. */ +#define ALT_H2F_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_H2F_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */ +#define ALT_H2F_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_ID_PERIPH_ID_0. + */ +struct ALT_H2F_ID_PERIPH_ID_0_s +{ + const uint32_t pn7to0 : 8; /* Part Number [7:0] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_ID_PERIPH_ID_0. */ +typedef volatile struct ALT_H2F_ID_PERIPH_ID_0_s ALT_H2F_ID_PERIPH_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_ID_PERIPH_ID_0 register from the beginning of the component. */ +#define ALT_H2F_ID_PERIPH_ID_0_OFST 0xfe0 + +/* + * Register : Peripheral ID1 Register - periph_id_1 + * + * Peripheral ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8 + * + * JEP106[3:0], Part Number [11:8] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7 +/* The width in bits of the ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8 +/* The mask used to set the ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff +/* The mask used to clear the ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00 +/* The reset value of the ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3 +/* Extracts the ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */ +#define ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */ +#define ALT_H2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_ID_PERIPH_ID_1. + */ +struct ALT_H2F_ID_PERIPH_ID_1_s +{ + const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_ID_PERIPH_ID_1. */ +typedef volatile struct ALT_H2F_ID_PERIPH_ID_1_s ALT_H2F_ID_PERIPH_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_ID_PERIPH_ID_1 register from the beginning of the component. */ +#define ALT_H2F_ID_PERIPH_ID_1_OFST 0xfe4 + +/* + * Register : Peripheral ID2 Register - periph_id_2 + * + * Peripheral ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4 + * + * Revision, JEP106 code flag, JEP106[6:4] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7 +/* The width in bits of the ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8 +/* The mask used to set the ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b +/* Extracts the ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */ +#define ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */ +#define ALT_H2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_ID_PERIPH_ID_2. + */ +struct ALT_H2F_ID_PERIPH_ID_2_s +{ + const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_ID_PERIPH_ID_2. */ +typedef volatile struct ALT_H2F_ID_PERIPH_ID_2_s ALT_H2F_ID_PERIPH_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_ID_PERIPH_ID_2 register from the beginning of the component. */ +#define ALT_H2F_ID_PERIPH_ID_2_OFST 0xfe8 + +/* + * Register : Peripheral ID3 Register - periph_id_3 + * + * Peripheral ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [3:0] | R | 0x0 | Customer Model Number + * [7:4] | R | 0x0 | Revision + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Customer Model Number - cust_mod_num + * + * Customer Model Number + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3 +/* The width in bits of the ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4 +/* The mask used to set the ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f +/* The mask used to clear the ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0 +/* Extracts the ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */ +#define ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */ +#define ALT_H2F_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Revision - rev_and + * + * Revision + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_H2F_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_H2F_ID_PERIPH_ID_3_REV_AND_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_H2F_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_H2F_ID_PERIPH_ID_3_REV_AND_MSB 7 +/* The width in bits of the ALT_H2F_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_H2F_ID_PERIPH_ID_3_REV_AND_WIDTH 4 +/* The mask used to set the ALT_H2F_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_H2F_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_H2F_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_H2F_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f +/* The reset value of the ALT_H2F_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_H2F_ID_PERIPH_ID_3_REV_AND_RESET 0x0 +/* Extracts the ALT_H2F_ID_PERIPH_ID_3_REV_AND field value from a register. */ +#define ALT_H2F_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_H2F_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */ +#define ALT_H2F_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_ID_PERIPH_ID_3. + */ +struct ALT_H2F_ID_PERIPH_ID_3_s +{ + const uint32_t cust_mod_num : 4; /* Customer Model Number */ + const uint32_t rev_and : 4; /* Revision */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_ID_PERIPH_ID_3. */ +typedef volatile struct ALT_H2F_ID_PERIPH_ID_3_s ALT_H2F_ID_PERIPH_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_ID_PERIPH_ID_3 register from the beginning of the component. */ +#define ALT_H2F_ID_PERIPH_ID_3_OFST 0xfec + +/* + * Register : Component ID0 Register - comp_id_0 + * + * Component ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xd | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_H2F_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_0_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_0_PREAMBLE_MSB 7 +/* The width in bits of the ALT_H2F_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_0_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_H2F_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_H2F_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_H2F_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_H2F_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_H2F_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_0_PREAMBLE_RESET 0xd +/* Extracts the ALT_H2F_ID_COMP_ID_0_PREAMBLE field value from a register. */ +#define ALT_H2F_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_H2F_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */ +#define ALT_H2F_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_ID_COMP_ID_0. + */ +struct ALT_H2F_ID_COMP_ID_0_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_ID_COMP_ID_0. */ +typedef volatile struct ALT_H2F_ID_COMP_ID_0_s ALT_H2F_ID_COMP_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_ID_COMP_ID_0 register from the beginning of the component. */ +#define ALT_H2F_ID_COMP_ID_0_OFST 0xff0 + +/* + * Register : Component ID1 Register - comp_id_1 + * + * Component ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------- + * [7:0] | R | 0xf0 | Generic IP component class, Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generic IP component class, Preamble - genipcompcls_preamble + * + * Generic IP component class, Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7 +/* The width in bits of the ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0 +/* Extracts the ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */ +#define ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */ +#define ALT_H2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_ID_COMP_ID_1. + */ +struct ALT_H2F_ID_COMP_ID_1_s +{ + const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_ID_COMP_ID_1. */ +typedef volatile struct ALT_H2F_ID_COMP_ID_1_s ALT_H2F_ID_COMP_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_ID_COMP_ID_1 register from the beginning of the component. */ +#define ALT_H2F_ID_COMP_ID_1_OFST 0xff4 + +/* + * Register : Component ID2 Register - comp_id_2 + * + * Component ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0x5 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_H2F_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_2_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_2_PREAMBLE_MSB 7 +/* The width in bits of the ALT_H2F_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_2_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_H2F_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_H2F_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_H2F_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_H2F_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_H2F_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_2_PREAMBLE_RESET 0x5 +/* Extracts the ALT_H2F_ID_COMP_ID_2_PREAMBLE field value from a register. */ +#define ALT_H2F_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_H2F_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */ +#define ALT_H2F_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_ID_COMP_ID_2. + */ +struct ALT_H2F_ID_COMP_ID_2_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_ID_COMP_ID_2. */ +typedef volatile struct ALT_H2F_ID_COMP_ID_2_s ALT_H2F_ID_COMP_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_ID_COMP_ID_2 register from the beginning of the component. */ +#define ALT_H2F_ID_COMP_ID_2_OFST 0xff8 + +/* + * Register : Component ID3 Register - comp_id_3 + * + * Component ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xb1 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_H2F_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_3_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_3_PREAMBLE_MSB 7 +/* The width in bits of the ALT_H2F_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_3_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_H2F_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_H2F_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_H2F_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_H2F_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_H2F_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_H2F_ID_COMP_ID_3_PREAMBLE_RESET 0xb1 +/* Extracts the ALT_H2F_ID_COMP_ID_3_PREAMBLE field value from a register. */ +#define ALT_H2F_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_H2F_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */ +#define ALT_H2F_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_ID_COMP_ID_3. + */ +struct ALT_H2F_ID_COMP_ID_3_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_ID_COMP_ID_3. */ +typedef volatile struct ALT_H2F_ID_COMP_ID_3_s ALT_H2F_ID_COMP_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_ID_COMP_ID_3 register from the beginning of the component. */ +#define ALT_H2F_ID_COMP_ID_3_OFST 0xffc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_H2F_IDGRP. + */ +struct ALT_H2F_IDGRP_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile ALT_H2F_ID_PERIPH_ID_4_t periph_id_4; /* ALT_H2F_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile ALT_H2F_ID_PERIPH_ID_0_t periph_id_0; /* ALT_H2F_ID_PERIPH_ID_0 */ + volatile ALT_H2F_ID_PERIPH_ID_1_t periph_id_1; /* ALT_H2F_ID_PERIPH_ID_1 */ + volatile ALT_H2F_ID_PERIPH_ID_2_t periph_id_2; /* ALT_H2F_ID_PERIPH_ID_2 */ + volatile ALT_H2F_ID_PERIPH_ID_3_t periph_id_3; /* ALT_H2F_ID_PERIPH_ID_3 */ + volatile ALT_H2F_ID_COMP_ID_0_t comp_id_0; /* ALT_H2F_ID_COMP_ID_0 */ + volatile ALT_H2F_ID_COMP_ID_1_t comp_id_1; /* ALT_H2F_ID_COMP_ID_1 */ + volatile ALT_H2F_ID_COMP_ID_2_t comp_id_2; /* ALT_H2F_ID_COMP_ID_2 */ + volatile ALT_H2F_ID_COMP_ID_3_t comp_id_3; /* ALT_H2F_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for register group ALT_H2F_IDGRP. */ +typedef volatile struct ALT_H2F_IDGRP_s ALT_H2F_IDGRP_t; +/* The struct declaration for the raw register contents of register group ALT_H2F_IDGRP. */ +struct ALT_H2F_IDGRP_raw_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile uint32_t periph_id_4; /* ALT_H2F_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile uint32_t periph_id_0; /* ALT_H2F_ID_PERIPH_ID_0 */ + volatile uint32_t periph_id_1; /* ALT_H2F_ID_PERIPH_ID_1 */ + volatile uint32_t periph_id_2; /* ALT_H2F_ID_PERIPH_ID_2 */ + volatile uint32_t periph_id_3; /* ALT_H2F_ID_PERIPH_ID_3 */ + volatile uint32_t comp_id_0; /* ALT_H2F_ID_COMP_ID_0 */ + volatile uint32_t comp_id_1; /* ALT_H2F_ID_COMP_ID_1 */ + volatile uint32_t comp_id_2; /* ALT_H2F_ID_COMP_ID_2 */ + volatile uint32_t comp_id_3; /* ALT_H2F_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_H2F_IDGRP. */ +typedef volatile struct ALT_H2F_IDGRP_raw_s ALT_H2F_IDGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Master Register Group - ALT_H2F_MSTGRP + * Master Register Group + * + * Registers associated with master interfaces. + * + */ +/* + * Register Group : 32-bit Master - ALT_H2F_MST_B32 + * 32-bit Master + * + * Registers associated with the 32-bit AXI master interface. + * + * These registers are only active when the HPS2FPGA AXI Bridge is configured with + * a 32-bit FPGA AXI master interface. + * + */ +/* + * Register : Functionality Modification 2 Register - fn_mod2 + * + * Controls bypass merge of upsizing/downsizing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Bypass Merge + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bypass Merge - bypass_merge + * + * Controls bypass merge of upsizing/downsizing. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------- + * ALT_H2F_FN_MOD2_BYPASS_MERGE_E_ALTER | 0x0 | The network can alter transactions. + * ALT_H2F_FN_MOD2_BYPASS_MERGE_E_NOALTER | 0x1 | The network does not alter any transactions that + * : | | could pass through the upsizer legally without + * : | | alteration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_H2F_FN_MOD2_BYPASS_MERGE + * + * The network can alter transactions. + */ +#define ALT_H2F_FN_MOD2_BYPASS_MERGE_E_ALTER 0x0 +/* + * Enumerated value for register field ALT_H2F_FN_MOD2_BYPASS_MERGE + * + * The network does not alter any transactions that could pass through the upsizer + * legally without alteration. + */ +#define ALT_H2F_FN_MOD2_BYPASS_MERGE_E_NOALTER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_H2F_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_H2F_FN_MOD2_BYPASS_MERGE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_H2F_FN_MOD2_BYPASS_MERGE_MSB 0 +/* The width in bits of the ALT_H2F_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_H2F_FN_MOD2_BYPASS_MERGE_WIDTH 1 +/* The mask used to set the ALT_H2F_FN_MOD2_BYPASS_MERGE register field value. */ +#define ALT_H2F_FN_MOD2_BYPASS_MERGE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_H2F_FN_MOD2_BYPASS_MERGE register field value. */ +#define ALT_H2F_FN_MOD2_BYPASS_MERGE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_H2F_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_H2F_FN_MOD2_BYPASS_MERGE_RESET 0x0 +/* Extracts the ALT_H2F_FN_MOD2_BYPASS_MERGE field value from a register. */ +#define ALT_H2F_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_H2F_FN_MOD2_BYPASS_MERGE register field value suitable for setting the register. */ +#define ALT_H2F_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_FN_MOD2. + */ +struct ALT_H2F_FN_MOD2_s +{ + uint32_t bypass_merge : 1; /* Bypass Merge */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_FN_MOD2. */ +typedef volatile struct ALT_H2F_FN_MOD2_s ALT_H2F_FN_MOD2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_FN_MOD2 register from the beginning of the component. */ +#define ALT_H2F_FN_MOD2_OFST 0x24 +/* The address of the ALT_H2F_FN_MOD2 register. */ +#define ALT_H2F_FN_MOD2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_H2F_FN_MOD2_OFST)) + +/* + * Register : Issuing Functionality Modification Register - fn_mod + * + * Sets the block issuing capability to multiple or single outstanding + * transactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [0] | RW | 0x0 | ALT_H2F_FN_MOD_RD + * [1] | RW | 0x0 | ALT_H2F_FN_MOD_WR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : rd + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------------------------------------- + * ALT_H2F_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions + * ALT_H2F_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_H2F_FN_MOD_RD + * + * Multiple outstanding read transactions + */ +#define ALT_H2F_FN_MOD_RD_E_MULT 0x0 +/* + * Enumerated value for register field ALT_H2F_FN_MOD_RD + * + * Only a single outstanding read transaction + */ +#define ALT_H2F_FN_MOD_RD_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_H2F_FN_MOD_RD register field. */ +#define ALT_H2F_FN_MOD_RD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_H2F_FN_MOD_RD register field. */ +#define ALT_H2F_FN_MOD_RD_MSB 0 +/* The width in bits of the ALT_H2F_FN_MOD_RD register field. */ +#define ALT_H2F_FN_MOD_RD_WIDTH 1 +/* The mask used to set the ALT_H2F_FN_MOD_RD register field value. */ +#define ALT_H2F_FN_MOD_RD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_H2F_FN_MOD_RD register field value. */ +#define ALT_H2F_FN_MOD_RD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_H2F_FN_MOD_RD register field. */ +#define ALT_H2F_FN_MOD_RD_RESET 0x0 +/* Extracts the ALT_H2F_FN_MOD_RD field value from a register. */ +#define ALT_H2F_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_H2F_FN_MOD_RD register field value suitable for setting the register. */ +#define ALT_H2F_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : wr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_H2F_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions + * ALT_H2F_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_H2F_FN_MOD_WR + * + * Multiple outstanding write transactions + */ +#define ALT_H2F_FN_MOD_WR_E_MULT 0x0 +/* + * Enumerated value for register field ALT_H2F_FN_MOD_WR + * + * Only a single outstanding write transaction + */ +#define ALT_H2F_FN_MOD_WR_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_H2F_FN_MOD_WR register field. */ +#define ALT_H2F_FN_MOD_WR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_H2F_FN_MOD_WR register field. */ +#define ALT_H2F_FN_MOD_WR_MSB 1 +/* The width in bits of the ALT_H2F_FN_MOD_WR register field. */ +#define ALT_H2F_FN_MOD_WR_WIDTH 1 +/* The mask used to set the ALT_H2F_FN_MOD_WR register field value. */ +#define ALT_H2F_FN_MOD_WR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_H2F_FN_MOD_WR register field value. */ +#define ALT_H2F_FN_MOD_WR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_H2F_FN_MOD_WR register field. */ +#define ALT_H2F_FN_MOD_WR_RESET 0x0 +/* Extracts the ALT_H2F_FN_MOD_WR field value from a register. */ +#define ALT_H2F_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_H2F_FN_MOD_WR register field value suitable for setting the register. */ +#define ALT_H2F_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_H2F_FN_MOD. + */ +struct ALT_H2F_FN_MOD_s +{ + uint32_t rd : 1; /* ALT_H2F_FN_MOD_RD */ + uint32_t wr : 1; /* ALT_H2F_FN_MOD_WR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_H2F_FN_MOD. */ +typedef volatile struct ALT_H2F_FN_MOD_s ALT_H2F_FN_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_H2F_FN_MOD register from the beginning of the component. */ +#define ALT_H2F_FN_MOD_OFST 0x108 +/* The address of the ALT_H2F_FN_MOD register. */ +#define ALT_H2F_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_H2F_FN_MOD_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_H2F_MST_B32. + */ +struct ALT_H2F_MST_B32_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile ALT_H2F_FN_MOD2_t fn_mod2; /* ALT_H2F_FN_MOD2 */ + volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */ + volatile ALT_H2F_FN_MOD_t fn_mod; /* ALT_H2F_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_H2F_MST_B32. */ +typedef volatile struct ALT_H2F_MST_B32_s ALT_H2F_MST_B32_t; +/* The struct declaration for the raw register contents of register group ALT_H2F_MST_B32. */ +struct ALT_H2F_MST_B32_raw_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile uint32_t fn_mod2; /* ALT_H2F_FN_MOD2 */ + volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_H2F_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_H2F_MST_B32. */ +typedef volatile struct ALT_H2F_MST_B32_raw_s ALT_H2F_MST_B32_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : 128-bit Master - ALT_H2F_MST_B128 + * 128-bit Master + * + * Registers associated with the 128-bit AXI master interface. + * + * These registers are only active when the HPS2FPGA AXI Bridge is configured with + * a 128-bit FPGA AXI master interface. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_H2F_MST_B128. + */ +struct ALT_H2F_MST_B128_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile ALT_H2F_FN_MOD2_t fn_mod2; /* ALT_H2F_FN_MOD2 */ + volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */ + volatile ALT_H2F_FN_MOD_t fn_mod; /* ALT_H2F_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_H2F_MST_B128. */ +typedef volatile struct ALT_H2F_MST_B128_s ALT_H2F_MST_B128_t; +/* The struct declaration for the raw register contents of register group ALT_H2F_MST_B128. */ +struct ALT_H2F_MST_B128_raw_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile uint32_t fn_mod2; /* ALT_H2F_FN_MOD2 */ + volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_H2F_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_H2F_MST_B128. */ +typedef volatile struct ALT_H2F_MST_B128_raw_s ALT_H2F_MST_B128_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_H2F_MSTGRP. + */ +struct ALT_H2F_MSTGRP_s +{ + volatile ALT_H2F_MST_B32_t mastergrp_b32; /* ALT_H2F_MST_B32 */ + volatile uint32_t _pad_0x10c_0x1fff[1981]; /* *UNDEFINED* */ + volatile ALT_H2F_MST_B128_t mastergrp_b128; /* ALT_H2F_MST_B128 */ +}; + +/* The typedef declaration for register group ALT_H2F_MSTGRP. */ +typedef volatile struct ALT_H2F_MSTGRP_s ALT_H2F_MSTGRP_t; +/* The struct declaration for the raw register contents of register group ALT_H2F_MSTGRP. */ +struct ALT_H2F_MSTGRP_raw_s +{ + volatile ALT_H2F_MST_B32_raw_t mastergrp_b32; /* ALT_H2F_MST_B32 */ + volatile uint32_t _pad_0x10c_0x1fff[1981]; /* *UNDEFINED* */ + volatile ALT_H2F_MST_B128_raw_t mastergrp_b128; /* ALT_H2F_MST_B128 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_H2F_MSTGRP. */ +typedef volatile struct ALT_H2F_MSTGRP_raw_s ALT_H2F_MSTGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_H2F. + */ +struct ALT_H2F_s +{ + volatile uint32_t _pad_0x0_0xfff[1024]; /* *UNDEFINED* */ + volatile ALT_H2F_IDGRP_t idgrp; /* ALT_H2F_IDGRP */ + volatile ALT_H2F_MSTGRP_t mastergrp; /* ALT_H2F_MSTGRP */ + volatile uint32_t _pad_0x410c_0x8000[4029]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_H2F. */ +typedef volatile struct ALT_H2F_s ALT_H2F_t; +/* The struct declaration for the raw register contents of register group ALT_H2F. */ +struct ALT_H2F_raw_s +{ + volatile uint32_t _pad_0x0_0xfff[1024]; /* *UNDEFINED* */ + volatile ALT_H2F_IDGRP_raw_t idgrp; /* ALT_H2F_IDGRP */ + volatile ALT_H2F_MSTGRP_raw_t mastergrp; /* ALT_H2F_MSTGRP */ + volatile uint32_t _pad_0x410c_0x8000[4029]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_H2F. */ +typedef volatile struct ALT_H2F_raw_s ALT_H2F_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_H2F_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_i2c.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_i2c.h new file mode 100644 index 000000000..1a1e39d13 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_i2c.h @@ -0,0 +1,5940 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_I2C */ + +#ifndef __ALTERA_ALT_I2C_H__ +#define __ALTERA_ALT_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : I2C Module - ALT_I2C + * I2C Module + * + * Registers in the I2C module + * + */ +/* + * Register : Control Register - ic_con + * + * This register can be written only when the I2C is disabled, which corresponds to + * the Bit [0] of the Enable Register being set to 0. Writes at other times have no + * effect. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | Master Enable + * [2:1] | RW | 0x2 | Master Speed Control + * [3] | RW | 0x1 | Slave Address Size + * [4] | RW | 0x1 | Master Address Size + * [5] | RW | 0x1 | Restart Enable + * [6] | RW | 0x1 | Slave Disable + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Enable - master_mode + * + * This bit controls whether the i2c master is enabled. + * + * NOTE: Software should ensure that if this bit is written with '1', then bit 6 + * should also be written with a '1'. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------- + * ALT_I2C_CON_MST_MOD_E_DIS | 0x0 | master disabled + * ALT_I2C_CON_MST_MOD_E_EN | 0x1 | master enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_MST_MOD + * + * master disabled + */ +#define ALT_I2C_CON_MST_MOD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_MST_MOD + * + * master enabled + */ +#define ALT_I2C_CON_MST_MOD_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_MSB 0 +/* The width in bits of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_MST_MOD register field value. */ +#define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CON_MST_MOD register field value. */ +#define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CON_MST_MOD register field. */ +#define ALT_I2C_CON_MST_MOD_RESET 0x1 +/* Extracts the ALT_I2C_CON_MST_MOD field value from a register. */ +#define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register. */ +#define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Master Speed Control - speed + * + * These bits control at which speed the I2C operates, its setting is relevant only + * if one is operating the I2C in master mode. Hardware protects against illegal + * values being programmed by software. This field should be programmed only with + * standard or fast speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:--------------------------- + * ALT_I2C_CON_SPEED_E_STANDARD | 0x1 | standard mode (100 kbit/s) + * ALT_I2C_CON_SPEED_E_FAST | 0x2 | fast mode (400 kbit/s) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_SPEED + * + * standard mode (100 kbit/s) + */ +#define ALT_I2C_CON_SPEED_E_STANDARD 0x1 +/* + * Enumerated value for register field ALT_I2C_CON_SPEED + * + * fast mode (400 kbit/s) + */ +#define ALT_I2C_CON_SPEED_E_FAST 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_MSB 2 +/* The width in bits of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_WIDTH 2 +/* The mask used to set the ALT_I2C_CON_SPEED register field value. */ +#define ALT_I2C_CON_SPEED_SET_MSK 0x00000006 +/* The mask used to clear the ALT_I2C_CON_SPEED register field value. */ +#define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_I2C_CON_SPEED register field. */ +#define ALT_I2C_CON_SPEED_RESET 0x2 +/* Extracts the ALT_I2C_CON_SPEED field value from a register. */ +#define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register. */ +#define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : Slave Address Size - ic_10bitaddr_slave + * + * When acting as a slave, this bit controls whether the I2C responds to 7- or + * 10-bit addresses. In 7-bit addressing, only the lower 7 bits of the Slave + * Address Register are compared. The I2C responds will only respond to 10-bit + * addressing transfers that match the full 10 bits of the Slave Address register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT | 0x0 | 7-bit addressing + * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT | 0x1 | 10-bit addressing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV + * + * 7-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV + * + * 10-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3 +/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Master Address Size - ic_10bitaddr_master + * + * This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing + * mode when acting as a master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------ + * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT | 0x0 | 7-bit addressing + * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT | 0x1 | 10-bit addressing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST + * + * 7-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST + * + * 10-bit addressing + */ +#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4 +/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Restart Enable - ic_restart_en + * + * Determines whether RESTART conditions may be sent when acting as a master. Some + * older slaves do not support handling RESTART conditions; however, RESTART + * conditions are used in several I2C operations. When RESTART is disabled, the + * master is prohibited from performing the following functions + * + * * Changing direction within a transfer (split), + * + * * Sending a START BYTE, + * + * * High-speed mode operation, + * + * * Combined format transfers in 7-bit addressing modes, + * + * * Read operation with a 10-bit address, + * + * * Sending multiple bytes per transfer, + * + * By replacing RESTART condition followed by a STOP and a subsequent START + * condition, split operations are broken down into multiple I2C transfers. If the + * above operations are performed, it will result in setting bit [6](tx_abort) of + * the Raw Interrupt Status Register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------- + * ALT_I2C_CON_IC_RESTART_EN_E_DIS | 0x0 | restart master disable + * ALT_I2C_CON_IC_RESTART_EN_E_EN | 0x1 | restart master enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN + * + * restart master disable + */ +#define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN + * + * restart master enable + */ +#define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_MSB 5 +/* The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value. */ +#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value. */ +#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_CON_IC_RESTART_EN register field. */ +#define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register. */ +#define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Slave Disable - ic_slave_disable + * + * This bit controls whether I2C has its slave disabled. The slave will be + * disabled, after reset. + * + * NOTE: Software should ensure that if this bit is written with 0, then bit [0] of + * this register should also be written with a 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------- + * ALT_I2C_CON_IC_SLV_DIS_E_DIS | 0x1 | slave disable + * ALT_I2C_CON_IC_SLV_DIS_E_EN | 0x0 | slave enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS + * + * slave disable + */ +#define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1 +/* + * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS + * + * slave enable + */ +#define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_MSB 6 +/* The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1 +/* The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value. */ +#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value. */ +#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_CON_IC_SLV_DIS register field. */ +#define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1 +/* Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register. */ +#define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register. */ +#define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CON. + */ +struct ALT_I2C_CON_s +{ + uint32_t master_mode : 1; /* Master Enable */ + uint32_t speed : 2; /* Master Speed Control */ + uint32_t ic_10bitaddr_slave : 1; /* Slave Address Size */ + uint32_t ic_10bitaddr_master : 1; /* Master Address Size */ + uint32_t ic_restart_en : 1; /* Restart Enable */ + uint32_t ic_slave_disable : 1; /* Slave Disable */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CON. */ +typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CON register from the beginning of the component. */ +#define ALT_I2C_CON_OFST 0x0 +/* The address of the ALT_I2C_CON register. */ +#define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST)) + +/* + * Register : Target Address Register - ic_tar + * + * This register can be written to only when the ic_enable register is set to 0. + * This register is 13 bits wide. All bits can be dynamically updated as long as + * any set of the following conditions are true, + * + * (Enable Register bit 0 is set to 0) or (Enable Register bit 0 is set to 1 AND + * (I2C is NOT engaged in any Master [tx, rx] operation [ic_status register + * mst_activity bit 5 is set to 0]) AND (I2C is enabled to operate in Master + * mode[ic_con bit[0] is set to one]) AND (there are NO entries in the TX FIFO + * Register [IC_STATUS bit [2] is set to 1]) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [9:0] | RW | 0x55 | Master Target Address + * [10] | RW | 0x0 | General Call OR Start + * [11] | RW | 0x0 | Special + * [12] | RW | 0x1 | Master Addressing Bit Control + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Target Address - ic_tar + * + * This is the target address for any master transaction. When transmitting a + * General Call, these bits are ignored. To generate a START BYTE, the CPU needs to + * write only once into these bits. If the ic_tar and ic_sar are the same, loopback + * exists but the FIFOs are shared between master and slave, so full loopback is + * not feasible. Only one direction loopback mode is supported (simplex), not + * duplex. A master cannot transmit to itself; it can transmit to only a slave. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_MSB 9 +/* The width in bits of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_WIDTH 10 +/* The mask used to set the ALT_I2C_TAR_IC_TAR register field value. */ +#define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff +/* The mask used to clear the ALT_I2C_TAR_IC_TAR register field value. */ +#define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_I2C_TAR_IC_TAR register field. */ +#define ALT_I2C_TAR_IC_TAR_RESET 0x55 +/* Extracts the ALT_I2C_TAR_IC_TAR field value from a register. */ +#define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_I2C_TAR_IC_TAR register field value suitable for setting the register. */ +#define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff) + +/* + * Field : General Call OR Start - gc_or_start + * + * If bit 11 (SPECIAL) of this Register is set to 1, then this bit indicates + * whether a General Call or START byte command is to be performed by the I2C or + * General Call Address after issuing a General Call, only writes may be performed. + * Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the Raw + * Interrupt_Status register. The I2C remains in General Call mode until the + * special bit value (bit 11) is cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------- + * ALT_I2C_TAR_GC_OR_START_E_GENCALL | 0x0 | General Call + * ALT_I2C_TAR_GC_OR_START_E_STARTBYTE | 0x1 | START Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_GC_OR_START + * + * General Call + */ +#define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_GC_OR_START + * + * START Byte + */ +#define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_MSB 10 +/* The width in bits of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_GC_OR_START register field value. */ +#define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_TAR_GC_OR_START register field value. */ +#define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_TAR_GC_OR_START register field. */ +#define ALT_I2C_TAR_GC_OR_START_RESET 0x0 +/* Extracts the ALT_I2C_TAR_GC_OR_START field value from a register. */ +#define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_TAR_GC_OR_START register field value suitable for setting the register. */ +#define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Special - special + * + * This bit indicates whether software performs a General Call or START BYTE + * command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:-------------------------------------------- + * ALT_I2C_TAR_SPECIAL_E_GENCALL | 0x0 | Ignore bit 10 gc_or_start and use ic_tar + * : | | normally + * ALT_I2C_TAR_SPECIAL_E_STARTBYTE | 0x1 | Perform special I2C command as specified in + * : | | gc_or_start + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_SPECIAL + * + * Ignore bit 10 gc_or_start and use ic_tar normally + */ +#define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_SPECIAL + * + * Perform special I2C command as specified in gc_or_start + */ +#define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_MSB 11 +/* The width in bits of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_SPECIAL register field value. */ +#define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_TAR_SPECIAL register field value. */ +#define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_TAR_SPECIAL register field. */ +#define ALT_I2C_TAR_SPECIAL_RESET 0x0 +/* Extracts the ALT_I2C_TAR_SPECIAL field value from a register. */ +#define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_TAR_SPECIAL register field value suitable for setting the register. */ +#define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Master Addressing Bit Control - ic_10bitaddr_master + * + * This bit controls whether the i2c starts its transfers in 7-bit or 10-bit + * addressing mode when acting as a master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------- + * ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 | 0x0 | Master Address, 7bit + * ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 | 0x1 | Master Address, 10bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST + * + * Master Address, 7bit + */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0 +/* + * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST + * + * Master Address, 10bit + */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12 +/* The width in bits of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1 +/* The mask used to set the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff +/* The reset value of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1 +/* Extracts the ALT_I2C_TAR_IC_10BITADDR_MST field value from a register. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_I2C_TAR_IC_10BITADDR_MST register field value suitable for setting the register. */ +#define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TAR. + */ +struct ALT_I2C_TAR_s +{ + uint32_t ic_tar : 10; /* Master Target Address */ + uint32_t gc_or_start : 1; /* General Call OR Start */ + uint32_t special : 1; /* Special */ + uint32_t ic_10bitaddr_master : 1; /* Master Addressing Bit Control */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TAR. */ +typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TAR register from the beginning of the component. */ +#define ALT_I2C_TAR_OFST 0x4 +/* The address of the ALT_I2C_TAR register. */ +#define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST)) + +/* + * Register : Slave Address Register - ic_sar + * + * Holds Address of Slave + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [9:0] | RW | 0x55 | Slave Address + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Slave Address - ic_sar + * + * The Slave Address register holds the slave address when the I2C is operating as + * a slave. For 7-bit addressing, only Field Bits [6:0] of the Slave Address + * Register are used. This register can be written only when the I2C interface is + * disabled, which corresponds to field bit 0 of the Enable Register being set to + * 0. Writes at other times have no effect. + * + * Note, the default values cannot be any of the reserved address locations: that + * is, + * + * 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not + * guaranteed if you program the Slave Address Register or Target Address Register + * to a reserved value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_MSB 9 +/* The width in bits of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_WIDTH 10 +/* The mask used to set the ALT_I2C_SAR_IC_SAR register field value. */ +#define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff +/* The mask used to clear the ALT_I2C_SAR_IC_SAR register field value. */ +#define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_I2C_SAR_IC_SAR register field. */ +#define ALT_I2C_SAR_IC_SAR_RESET 0x55 +/* Extracts the ALT_I2C_SAR_IC_SAR field value from a register. */ +#define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_I2C_SAR_IC_SAR register field value suitable for setting the register. */ +#define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SAR. + */ +struct ALT_I2C_SAR_s +{ + uint32_t ic_sar : 10; /* Slave Address */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SAR. */ +typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SAR register from the beginning of the component. */ +#define ALT_I2C_SAR_OFST 0x8 +/* The address of the ALT_I2C_SAR register. */ +#define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST)) + +/* + * Register : Tx Rx Data and Command Register - ic_data_cmd + * + * This is the register the CPU writes to when filling the TX FIFO. Reading from + * this register returns bytes from RX FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------- + * [7:0] | RW | 0x0 | Tx Rx Data + * [8] | W | 0x0 | Master Read Write Control + * [9] | W | 0x0 | Generate Stop + * [10] | W | 0x0 | Generate Restart + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx Rx Data - dat + * + * This Field contains the data to be transmitted or received on the I2C bus. If + * you are writing to these bits and want to perform a read, bits 7:0 (dat) are + * ignored by the I2C. However, when you read from this register, these bits return + * the value of data received on the I2C interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_MSB 7 +/* The width in bits of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_WIDTH 8 +/* The mask used to set the ALT_I2C_DATA_CMD_DAT register field value. */ +#define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_DATA_CMD_DAT register field value. */ +#define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_DATA_CMD_DAT register field. */ +#define ALT_I2C_DATA_CMD_DAT_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_DAT field value from a register. */ +#define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_DATA_CMD_DAT register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Master Read Write Control - cmd + * + * This bit controls whether a read or a write is performed. This bit does not + * control the direction when the I2C acts as a slave. It controls only the + * direction when it acts as a master. When a command is entered in the TX FIFO, + * this bit distinguishes the write and read commands. In slave-receiver mode, this + * bit is a 'don't care' because writes to this register are not required. In + * slave-transmitter mode, a '0' indicates that the CPU data is to be transmitted. + * When programming this bit, you should remember the following: attempting to + * perform a read operation after a General Call command has been sent results in a + * tx_abrt interrupt (bit 6 of the Raw Intr Status Register), unless bit 11 special + * in the Target Address Register has been cleared. If a '1' is written to this bit + * after receiving a RD_REQ interrupt, then a tx_abrt interrupt occurs. + * + * NOTE: It is possible that while attempting a master I2C read transfer on I2C, a + * RD_REQ interrupt may have occurred simultaneously due to a remote I2C master + * addressing I2C. In this type of scenario, I2C ignores the Data Cmd write, + * generates a tx_abrt interrupt, and waits to service the RD_REQ interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------- + * ALT_I2C_DATA_CMD_CMD_E_RD | 0x1 | Master Read + * ALT_I2C_DATA_CMD_CMD_E_WR | 0x0 | Master Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_CMD + * + * Master Read + */ +#define ALT_I2C_DATA_CMD_CMD_E_RD 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_CMD + * + * Master Write + */ +#define ALT_I2C_DATA_CMD_CMD_E_WR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_MSB 8 +/* The width in bits of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_CMD register field value. */ +#define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_DATA_CMD_CMD register field value. */ +#define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_DATA_CMD_CMD register field. */ +#define ALT_I2C_DATA_CMD_CMD_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_CMD field value from a register. */ +#define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_DATA_CMD_CMD register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Generate Stop - stop + * + * This bit controls whether a STOP is issued after the byte is sent or received. + * + * 1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is + * empty. If the Tx FIFO is not empty, the master immediately tries to start a new + * transfer by issuing a START and arbitrating for the bus. + * + * 0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO + * is empty. If the Tx FIFO is not empty, the master continues the current transfer + * by sending/receiving data bytes according to the value of the CMD bit. If the Tx + * FIFO is empty, the master holds the SCL line low and stalls the bus until a new + * command is available in the Tx FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------ + * ALT_I2C_DATA_CMD_STOP_E_STOP | 0x1 | Issue Stop + * ALT_I2C_DATA_CMD_STOP_E_NO_STOP | 0x0 | Do Not Issue Stop + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_STOP + * + * Issue Stop + */ +#define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_STOP + * + * Do Not Issue Stop + */ +#define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_MSB 9 +/* The width in bits of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_STOP register field value. */ +#define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_DATA_CMD_STOP register field value. */ +#define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_DATA_CMD_STOP register field. */ +#define ALT_I2C_DATA_CMD_STOP_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_STOP field value from a register. */ +#define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_DATA_CMD_STOP register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Generate Restart - restart + * + * This bit controls whether a RESTART is issued before the byte is sent or + * received. + * + * 1 = A RESTART is issued before the data is sent/received (according to the value + * of CMD), regardless of whether or not the transfer direction is changing from + * the previous command. + * + * 0 = A RESTART is issued only if the transfer direction is changing from the + * previous command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:---------------------------------- + * ALT_I2C_DATA_CMD_RESTART_E_RESTART | 0x1 | Issue Restart + * ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE | 0x0 | Issue Restart On Direction Change + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART + * + * Issue Restart + */ +#define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1 +/* + * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART + * + * Issue Restart On Direction Change + */ +#define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_MSB 10 +/* The width in bits of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_WIDTH 1 +/* The mask used to set the ALT_I2C_DATA_CMD_RESTART register field value. */ +#define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_DATA_CMD_RESTART register field value. */ +#define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_DATA_CMD_RESTART register field. */ +#define ALT_I2C_DATA_CMD_RESTART_RESET 0x0 +/* Extracts the ALT_I2C_DATA_CMD_RESTART field value from a register. */ +#define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_DATA_CMD_RESTART register field value suitable for setting the register. */ +#define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DATA_CMD. + */ +struct ALT_I2C_DATA_CMD_s +{ + uint32_t dat : 8; /* Tx Rx Data */ + uint32_t cmd : 1; /* Master Read Write Control */ + uint32_t stop : 1; /* Generate Stop */ + uint32_t restart : 1; /* Generate Restart */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DATA_CMD. */ +typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DATA_CMD register from the beginning of the component. */ +#define ALT_I2C_DATA_CMD_OFST 0x10 +/* The address of the ALT_I2C_DATA_CMD register. */ +#define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST)) + +/* + * Register : Std Spd Clock SCL HCNT Register - ic_ss_scl_hcnt + * + * This register sets the SCL clock high-period count for standard speed. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [15:0] | RW | 0x190 | Std Spd SCL High Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Std Spd SCL High Period - ic_ss_scl_hcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock high-period count for + * standard speed. This register can be written only when the I2C interface is + * disabled which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect. The minimum valid value is 6; hardware prevents + * values less than this being written, and if attempted results in 6 being set. It + * is readable and writeable. + * + * NOTE: This register must not be programmed to a value higher than 65525, because + * I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter + * reaches a value of IC_SS_SCL_HCNT + 10. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 +/* The width in bits of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190 +/* Extracts the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT field value from a register. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value suitable for setting the register. */ +#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SS_SCL_HCNT. + */ +struct ALT_I2C_SS_SCL_HCNT_s +{ + uint32_t ic_ss_scl_hcnt : 16; /* Std Spd SCL High Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SS_SCL_HCNT. */ +typedef volatile struct ALT_I2C_SS_SCL_HCNT_s ALT_I2C_SS_SCL_HCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SS_SCL_HCNT register from the beginning of the component. */ +#define ALT_I2C_SS_SCL_HCNT_OFST 0x14 +/* The address of the ALT_I2C_SS_SCL_HCNT register. */ +#define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST)) + +/* + * Register : Std Spd Clock SCL LCNT Register - ic_ss_scl_lcnt + * + * This register sets the SCL clock low-period count for standard speed + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [15:0] | RW | 0x1d6 | Std Spd SCL Low Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Std Spd SCL Low Period - ic_ss_scl_lcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock low period count for + * standard speed. This register can be written only when the I2C interface is + * disabled which corresponds to the Enable Register register being set to 0. + * Writes at other times have no effect. The minimum valid value is 8; hardware + * prevents values less than this from being written, and if attempted, results in + * 8 being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 +/* The width in bits of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6 +/* Extracts the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT field value from a register. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value suitable for setting the register. */ +#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SS_SCL_LCNT. + */ +struct ALT_I2C_SS_SCL_LCNT_s +{ + uint32_t ic_ss_scl_lcnt : 16; /* Std Spd SCL Low Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SS_SCL_LCNT. */ +typedef volatile struct ALT_I2C_SS_SCL_LCNT_s ALT_I2C_SS_SCL_LCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SS_SCL_LCNT register from the beginning of the component. */ +#define ALT_I2C_SS_SCL_LCNT_OFST 0x18 +/* The address of the ALT_I2C_SS_SCL_LCNT register. */ +#define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST)) + +/* + * Register : Fast Spd Clock SCL HCNT Register - ic_fs_scl_hcnt + * + * This register sets the SCL clock high-period count for fast speed + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [15:0] | RW | 0x3c | Fast Spd SCL High Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Fast Spd SCL High Period - ic_fs_scl_hcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This register sets the SCL clock high-period count for + * fast speed. It is used in high-speed mode to send the Master Code and START BYTE + * or General CALL. This register goes away and becomes read-only returning 0s if + * in Standard Speed Mode. This register can be written only when the I2C interface + * is disabled, which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect. The minimum valid value is 6; hardware prevents + * values less than this from being written, and if attempted results in 6 being + * set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 +/* The width in bits of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c +/* Extracts the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT field value from a register. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value suitable for setting the register. */ +#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SCL_HCNT. + */ +struct ALT_I2C_FS_SCL_HCNT_s +{ + uint32_t ic_fs_scl_hcnt : 16; /* Fast Spd SCL High Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SCL_HCNT. */ +typedef volatile struct ALT_I2C_FS_SCL_HCNT_s ALT_I2C_FS_SCL_HCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SCL_HCNT register from the beginning of the component. */ +#define ALT_I2C_FS_SCL_HCNT_OFST 0x1c +/* The address of the ALT_I2C_FS_SCL_HCNT register. */ +#define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST)) + +/* + * Register : Fast Spd Clock SCL LCNT Register - ic_fs_scl_lcnt + * + * This register sets the SCL clock low period count + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [15:0] | RW | 0x82 | Fast Spd SCL Low Period + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Fast Spd SCL Low Period - ic_fs_scl_lcnt + * + * This register must be set before any I2C bus transaction can take place to + * ensure proper I/O timing. This field sets the SCL clock low period count for + * fast speed. It is used in high-speed mode to send the Master Code and START BYTE + * or General CALL. This register can be written only when the I2C interface is + * disabled, which corresponds to the Enable Register being set to 0. Writes at + * other times have no effect.The minimum valid value is 8; hardware prevents + * values less than this being written, and if attempted results in 8 being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 +/* The width in bits of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16 +/* The mask used to set the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82 +/* Extracts the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT field value from a register. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value suitable for setting the register. */ +#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SCL_LCNT. + */ +struct ALT_I2C_FS_SCL_LCNT_s +{ + uint32_t ic_fs_scl_lcnt : 16; /* Fast Spd SCL Low Period */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SCL_LCNT. */ +typedef volatile struct ALT_I2C_FS_SCL_LCNT_s ALT_I2C_FS_SCL_LCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SCL_LCNT register from the beginning of the component. */ +#define ALT_I2C_FS_SCL_LCNT_OFST 0x20 +/* The address of the ALT_I2C_FS_SCL_LCNT register. */ +#define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST)) + +/* + * Register : Interrupt Status Register - ic_intr_stat + * + * Each bit in this register has a corresponding mask bit in the Interrupt Mask + * Register. These bits are cleared by reading the matching Interrupt Clear + * Register. The unmasked raw versions of these bits are available in the Raw + * Interrupt Status Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | R | 0x0 | Receiver Under + * [1] | R | 0x0 | Receiver Over + * [2] | R | 0x0 | Receive Full + * [3] | R | 0x0 | Interrupt Transmit Over + * [4] | R | 0x0 | Interrupt Transmit Empty + * [5] | R | 0x0 | Interrupt Read Request + * [6] | R | 0x0 | Interrupt TX Abort + * [7] | R | 0x0 | Interrupt RX Done + * [8] | R | 0x0 | Interrupt R_activity + * [9] | R | 0x0 | Interrupt Stop Detect + * [10] | R | 0x0 | Interrupt Start Detect + * [11] | R | 0x0 | Interrupt General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receiver Under - r_rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the Tx Rx Data and Command Register. If the module is disabled, + * Enable Register is set to 0, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_UNDER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_INTR_STAT_R_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Receiver Over - r_rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled, + * Enable Register bit[0] is set to 0 this bit keeps its level until the master or + * slave state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_OVER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_INTR_STAT_R_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive Full - r_rx_full + * + * Set when the receive buffer reaches or goes above the Receive FIFO Threshold + * Value(rx_tl). It is automatically cleared by hardware when buffer level goes + * below the threshold. If the module is disabled, Bit [0] of the Enable Register + * set to 0, the RX FIFO is flushed and held in reset; therefore the RX FIFO is not + * full. So this bit is cleared once the Enable Register Bit 0 is programmed with a + * 0, regardless of the activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_FULL field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_INTR_STAT_R_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Interrupt Transmit Over - r_tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the Data and Command + * Register. When the module is disabled, this bit keeps its level until the master + * or slave state machines goes into idle, then interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_OVER field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_INTR_STAT_R_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Interrupt Transmit Empty - r_tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, this bit is set to 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_EMPTY field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Interrupt Read Request - r_rd_req + * + * This bit is set to 1 when i2c is acting as a slave and another I2C master is + * attempting to read data from I2C. The I2C holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the IC_DATA_CMD register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RD_REQ field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_INTR_STAT_R_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Interrupt TX Abort - r_tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit + * abort'.When this bit is set to 1, the ic_tx_abrt_source register indicates the + * reason why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_TX_ABRT field value from a register. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_INTR_STAT_R_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Interrupt RX Done - r_rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_RX_DONE field value from a register. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_INTR_STAT_R_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Interrupt R_activity - r_activity + * + * This bit captures I2C activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the I2C + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * I2C reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the I2C module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_ACTIVITY field value from a register. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_INTR_STAT_R_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Interrupt Stop Detect - r_stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_STOP_DET field value from a register. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_INTR_STAT_R_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Interrupt Start Detect - r_start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_START_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_START_DET register field value. */ +#define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_INTR_STAT_R_START_DET register field. */ +#define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_START_DET field value from a register. */ +#define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_INTR_STAT_R_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Interrupt General Call - r_gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_INTR_STAT_R_GEN_CALL field value from a register. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_INTR_STAT_R_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_INTR_STAT. + */ +struct ALT_I2C_INTR_STAT_s +{ + const uint32_t r_rx_under : 1; /* Receiver Under */ + const uint32_t r_rx_over : 1; /* Receiver Over */ + const uint32_t r_rx_full : 1; /* Receive Full */ + const uint32_t r_tx_over : 1; /* Interrupt Transmit Over */ + const uint32_t r_tx_empty : 1; /* Interrupt Transmit Empty */ + const uint32_t r_rd_req : 1; /* Interrupt Read Request */ + const uint32_t r_tx_abrt : 1; /* Interrupt TX Abort */ + const uint32_t r_rx_done : 1; /* Interrupt RX Done */ + const uint32_t r_activity : 1; /* Interrupt R_activity */ + const uint32_t r_stop_det : 1; /* Interrupt Stop Detect */ + const uint32_t r_start_det : 1; /* Interrupt Start Detect */ + const uint32_t r_gen_call : 1; /* Interrupt General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_INTR_STAT. */ +typedef volatile struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_INTR_STAT register from the beginning of the component. */ +#define ALT_I2C_INTR_STAT_OFST 0x2c +/* The address of the ALT_I2C_INTR_STAT register. */ +#define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST)) + +/* + * Register : Interrupt Mask Register - ic_intr_mask + * + * These bits mask their corresponding interrupt status bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------- + * [0] | RW | 0x1 | Mask RX Under + * [1] | RW | 0x1 | RX Buffer Over + * [2] | RW | 0x1 | RX Buffer Full + * [3] | RW | 0x1 | TX Buffer Over + * [4] | RW | 0x1 | TX Buffer Empty + * [5] | RW | 0x1 | Read Request + * [6] | RW | 0x1 | TX Abort + * [7] | RW | 0x1 | RX Done + * [8] | RW | 0x0 | Activity Bit + * [9] | RW | 0x0 | Stop Detect + * [10] | RW | 0x0 | Start Detect + * [11] | RW | 0x1 | General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mask RX Under - m_rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, + * this bit keeps its level until the master or slave state machines go into idle, + * and then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_UNDER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_INTR_MSK_M_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : RX Buffer Over - m_rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled + * ic_enable[0]=0, this bit keeps its level until the master or slave state + * machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_OVER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_INTR_MSK_M_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : RX Buffer Full - m_rx_full + * + * Set when the receive buffer reaches or goes above the RX_TL threshold in the + * ic_rx_tl register. It is automatically cleared by hardware when buffer level + * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is + * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the + * activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_FULL field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_INTR_MSK_M_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : TX Buffer Over - m_tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the ic_data_cmd register. + * When the module is disabled, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_OVER field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_INTR_MSK_M_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : TX Buffer Empty - m_tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, then this bit is set to + * 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_EMPTY field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_INTR_MSK_M_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Read Request - m_rd_req + * + * This bit is set to 1 when I2C is acting as a slave and another I2C master is + * attempting to read data from I2C. The I2C holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the ic_data_cmd register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RD_REQ field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_INTR_MSK_M_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TX Abort - m_tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. + * When this bit is set to 1, the ic_tx_abrt_source register indicates the reason + * why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_TX_ABRT field value from a register. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_INTR_MSK_M_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : RX Done - m_rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_RX_DONE field value from a register. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_INTR_MSK_M_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Activity Bit - m_activity + * + * This bit captures i2c activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the i2c + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * System reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the I2C module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_ACTIVITY field value from a register. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_INTR_MSK_M_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Stop Detect - m_stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether i2c is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_STOP_DET field value from a register. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_INTR_MSK_M_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Start Detect - m_start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_START_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_START_DET register field value. */ +#define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_INTR_MSK_M_START_DET register field. */ +#define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_INTR_MSK_M_START_DET field value from a register. */ +#define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_INTR_MSK_M_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : General Call - m_gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1 +/* Extracts the ALT_I2C_INTR_MSK_M_GEN_CALL field value from a register. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_INTR_MSK_M_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_INTR_MSK. + */ +struct ALT_I2C_INTR_MSK_s +{ + uint32_t m_rx_under : 1; /* Mask RX Under */ + uint32_t m_rx_over : 1; /* RX Buffer Over */ + uint32_t m_rx_full : 1; /* RX Buffer Full */ + uint32_t m_tx_over : 1; /* TX Buffer Over */ + uint32_t m_tx_empty : 1; /* TX Buffer Empty */ + uint32_t m_rd_req : 1; /* Read Request */ + uint32_t m_tx_abrt : 1; /* TX Abort */ + uint32_t m_rx_done : 1; /* RX Done */ + uint32_t m_activity : 1; /* Activity Bit */ + uint32_t m_stop_det : 1; /* Stop Detect */ + uint32_t m_start_det : 1; /* Start Detect */ + uint32_t m_gen_call : 1; /* General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_INTR_MSK. */ +typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_INTR_MSK register from the beginning of the component. */ +#define ALT_I2C_INTR_MSK_OFST 0x30 +/* The address of the ALT_I2C_INTR_MSK register. */ +#define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST)) + +/* + * Register : Raw Interrupt Status Register - ic_raw_intr_stat + * + * Unlike the ic_intr_stat register, these bits are not masked so they always show + * the true status of the I2C. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | I2C Raw Interrupt RX Under + * [1] | R | 0x0 | Raw Interrupt RX Over + * [2] | R | 0x0 | Raw Interrupt RX Full + * [3] | R | 0x0 | Raw Interrupt TX Over + * [4] | R | 0x0 | Raw Interrupt TX Empty + * [5] | R | 0x0 | Raw Interrupt Read Request + * [6] | R | 0x0 | Raw Interrupt TX Abort + * [7] | R | 0x0 | Raw Interrupt RX Done + * [8] | R | 0x0 | Raw Interrupt Activity + * [9] | R | 0x0 | Raw Interrupt Stop Detect + * [10] | R | 0x0 | Raw Interrupt Start Detect + * [11] | R | 0x0 | Raw Interrupt General Call + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : I2C Raw Interrupt RX Under - rx_under + * + * Set if the processor attempts to read the receive buffer when it is empty by + * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, + * this bit keeps its level until the master or slave state machines go into idle, + * then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_UNDER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Raw Interrupt RX Over - rx_over + * + * Set if the receive buffer is completely filled to 64 and an additional byte is + * received from an external I2C device. The I2C acknowledges this, but any data + * bytes received after the FIFO is full are lost. If the module is disabled + * ic_enable[0]=0), this bit keeps its level until the master or slave state + * machines go into then, this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_OVER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Raw Interrupt RX Full - rx_full + * + * Set when the receive buffer reaches or goes above the RX_TL threshold in the + * ic_rx_tl register. It is automatically cleared by hardware when buffer level + * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO + * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is + * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the + * activity that continues. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_FULL field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_FULL register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Raw Interrupt TX Over - tx_over + * + * Set during transmit if the transmit buffer is filled to 64 and the processor + * attempts to issue another I2C command by writing to the ic_data_cmd register. + * When the module is disabled, this bit keeps its level until the master or slave + * state machines go into idle, then this interrupt is cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_OVER field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Raw Interrupt TX Empty - tx_empty + * + * This bit is set to 1 when the transmit buffer is at or below the threshold value + * set in the ic_tx_tl register. It is automatically cleared by hardware when the + * buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX + * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data + * within it, so this bit is set to 1, provided there is activity in the master or + * slave state machines. When there is no longer activity, then this bit is set to + * 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_EMPTY field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Raw Interrupt Read Request - rd_req + * + * This bit is set to 1 when I2C is acting as a slave and another I2C master is + * attempting to read data from I2C. The i2c holds the I2C bus in a wait state + * (SCL=0) until this interrupt is serviced, which means that the slave has been + * addressed by a remote master that is asking for data to be transferred. The + * processor must respond to this interrupt and then write the requested data to + * the ic_data_cmd register. This bit is set to 0 just after the processor reads + * the ic_clr_rd_req register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RD_REQ field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_RAW_INTR_STAT_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Raw Interrupt TX Abort - tx_abrt + * + * This bit indicates if I2C, as an I2C transmitter, is unable to complete the + * intended actions on the contents of the transmit FIFO. This situation can occur + * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. + * When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason + * why the transmit abort takes places. + * + * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The + * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. + * Once this read is performed, the TX FIFO is then ready to accept more data bytes + * from the APB interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_ABRT field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Raw Interrupt RX Done - rx_done + * + * When the I2C is acting as a slave-transmitter, this bit is set to 1 if the + * master does not acknowledge a transmitted byte. This occurs on the last byte of + * the transmission, indicating that the transmission is done. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_DONE field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_RAW_INTR_STAT_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Raw Interrupt Activity - activity + * + * This bit captures i2c activity and stays set until it is cleared. There are four + * ways to clear it: + * + * * Disabling the I2C + * + * * Reading the ic_clr_activity register + * + * * Reading the ic_clr_intr register + * + * * System reset + * + * Once this bit is set, it stays set unless one of the four methods is used to + * clear it. Even if the i2c module is idle, this bit remains set until cleared, + * indicating that there was activity on the bus. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_ACTIVITY field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Raw Interrupt Stop Detect - stop_det + * + * Indicates whether a STOP condition has occurred on the I2C interface regardless + * of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_STOP_DET field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_RAW_INTR_STAT_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Raw Interrupt Start Detect - start_det + * + * Indicates whether a START or RESTART condition has occurred on the I2C interface + * regardless of whether I2C is operating in slave or master mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_START_DET field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_RAW_INTR_STAT_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Raw Interrupt General Call - gen_call + * + * Set only when a General Call address is received and it is acknowledged. It + * stays set until it is cleared either by disabling I2C or when the CPU reads bit + * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx + * buffer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11 +/* The width in bits of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_RAW_INTR_STAT_GEN_CALL field value from a register. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RAW_INTR_STAT. + */ +struct ALT_I2C_RAW_INTR_STAT_s +{ + const uint32_t rx_under : 1; /* I2C Raw Interrupt RX Under */ + const uint32_t rx_over : 1; /* Raw Interrupt RX Over */ + const uint32_t rx_full : 1; /* Raw Interrupt RX Full */ + const uint32_t tx_over : 1; /* Raw Interrupt TX Over */ + const uint32_t tx_empty : 1; /* Raw Interrupt TX Empty */ + const uint32_t rd_req : 1; /* Raw Interrupt Read Request */ + const uint32_t tx_abrt : 1; /* Raw Interrupt TX Abort */ + const uint32_t rx_done : 1; /* Raw Interrupt RX Done */ + const uint32_t activity : 1; /* Raw Interrupt Activity */ + const uint32_t stop_det : 1; /* Raw Interrupt Stop Detect */ + const uint32_t start_det : 1; /* Raw Interrupt Start Detect */ + const uint32_t gen_call : 1; /* Raw Interrupt General Call */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RAW_INTR_STAT. */ +typedef volatile struct ALT_I2C_RAW_INTR_STAT_s ALT_I2C_RAW_INTR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RAW_INTR_STAT register from the beginning of the component. */ +#define ALT_I2C_RAW_INTR_STAT_OFST 0x34 +/* The address of the ALT_I2C_RAW_INTR_STAT register. */ +#define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST)) + +/* + * Register : Receive FIFO Threshold Register - ic_rx_tl + * + * I2C Receive FIFO Threshold Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [7:0] | RW | 0x0 | Receive FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Threshold Level - rx_tl + * + * Controls the level of entries (or above) that triggers the RX_FULL interrupt + * (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the + * additional restriction that hardware does not allow this value to be set to a + * value larger than the depth of the buffer. If an attempt is made to do that, the + * actual value set will be the maximum depth of the buffer. A value of 0 sets the + * threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_MSB 7 +/* The width in bits of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_WIDTH 8 +/* The mask used to set the ALT_I2C_RX_TL_RX_TL register field value. */ +#define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_RX_TL_RX_TL register field value. */ +#define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_RX_TL_RX_TL register field. */ +#define ALT_I2C_RX_TL_RX_TL_RESET 0x0 +/* Extracts the ALT_I2C_RX_TL_RX_TL field value from a register. */ +#define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_RX_TL_RX_TL register field value suitable for setting the register. */ +#define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RX_TL. + */ +struct ALT_I2C_RX_TL_s +{ + uint32_t rx_tl : 8; /* Receive FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RX_TL. */ +typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RX_TL register from the beginning of the component. */ +#define ALT_I2C_RX_TL_OFST 0x38 +/* The address of the ALT_I2C_RX_TL register. */ +#define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST)) + +/* + * Register : Transmit FIFO Threshold Level Register - ic_tx_tl + * + * Sets FIFO depth for Interrupt. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [7:0] | RW | 0x0 | Transmit FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Threshold Level - tx_tl + * + * Controls the level of entries (or below) that trigger the TX_EMPTY interrupt + * (bit 4 in ic_raw_intr_stat register). The valid range is 0-255, with the + * additional restriction that it may not be set to value larger than the depth of + * the buffer. If an attempt is made to do that, the actual value set will be the + * maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and + * a value of 255 sets the threshold for 255 entries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_MSB 7 +/* The width in bits of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_WIDTH 8 +/* The mask used to set the ALT_I2C_TX_TL_TX_TL register field value. */ +#define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_TX_TL_TX_TL register field value. */ +#define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_TX_TL_TX_TL register field. */ +#define ALT_I2C_TX_TL_TX_TL_RESET 0x0 +/* Extracts the ALT_I2C_TX_TL_TX_TL field value from a register. */ +#define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_TX_TL_TX_TL register field value suitable for setting the register. */ +#define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TX_TL. + */ +struct ALT_I2C_TX_TL_s +{ + uint32_t tx_tl : 8; /* Transmit FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TX_TL. */ +typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TX_TL register from the beginning of the component. */ +#define ALT_I2C_TX_TL_OFST 0x3c +/* The address of the ALT_I2C_TX_TL register. */ +#define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST)) + +/* + * Register : Combined and Individual Interrupt Register - ic_clr_intr + * + * Controls Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Combined and Individual Interrupt Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Combined and Individual Interrupt Bits - clr_intr + * + * Read this register to clear the combined interrupt, all individual interrupts, + * and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable + * interrupts but software clearable interrupts. Refer to Bit 9 of the + * ic_tx_abrt_source register for an exception to clearing ic_tx_abrt_source. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0 +/* The width in bits of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0 +/* Extracts the ALT_I2C_CLR_INTR_CLR_INTR field value from a register. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_INTR_CLR_INTR register field value suitable for setting the register. */ +#define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_INTR. + */ +struct ALT_I2C_CLR_INTR_s +{ + const uint32_t clr_intr : 1; /* Combined and Individual Interrupt Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_INTR. */ +typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_INTR register from the beginning of the component. */ +#define ALT_I2C_CLR_INTR_OFST 0x40 +/* The address of the ALT_I2C_CLR_INTR register. */ +#define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST)) + +/* + * Register : Rx Under Interrupt Register - ic_clr_rx_under + * + * Rx Under Interrupt Bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | R | 0x0 | Clear Rx Under Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Rx Under Interrupt Bit - clr_rx_under + * + * Read this register to clear the RX_UNDER interrupt bit 0 of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER field value from a register. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_UNDER. + */ +struct ALT_I2C_CLR_RX_UNDER_s +{ + const uint32_t clr_rx_under : 1; /* Clear Rx Under Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_UNDER. */ +typedef volatile struct ALT_I2C_CLR_RX_UNDER_s ALT_I2C_CLR_RX_UNDER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_UNDER register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_UNDER_OFST 0x44 +/* The address of the ALT_I2C_CLR_RX_UNDER register. */ +#define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST)) + +/* + * Register : RX Over Interrupt Register - ic_clr_rx_over + * + * Clears Rx over Interrupt Bit + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | RX Over Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RX Over Interrupt Bit - clr_rx_over + * + * Read this register to clear the RX_OVER interrupt bit 1 of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER field value from a register. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_OVER. + */ +struct ALT_I2C_CLR_RX_OVER_s +{ + const uint32_t clr_rx_over : 1; /* RX Over Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_OVER. */ +typedef volatile struct ALT_I2C_CLR_RX_OVER_s ALT_I2C_CLR_RX_OVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_OVER register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_OVER_OFST 0x48 +/* The address of the ALT_I2C_CLR_RX_OVER register. */ +#define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST)) + +/* + * Register : TX Over Interrupt Register - ic_clr_tx_over + * + * Clears Over Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | TX Over Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : TX Over Interrupt Bit - clr_tx_over + * + * Read this register to clear the TX_OVER interrupt (bit 3) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0 +/* The width in bits of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 +/* Extracts the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER field value from a register. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value suitable for setting the register. */ +#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_TX_OVER. + */ +struct ALT_I2C_CLR_TX_OVER_s +{ + const uint32_t clr_tx_over : 1; /* TX Over Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_TX_OVER. */ +typedef volatile struct ALT_I2C_CLR_TX_OVER_s ALT_I2C_CLR_TX_OVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_TX_OVER register from the beginning of the component. */ +#define ALT_I2C_CLR_TX_OVER_OFST 0x4c +/* The address of the ALT_I2C_CLR_TX_OVER register. */ +#define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST)) + +/* + * Register : Interrupt Read Request Register - ic_clr_rd_req + * + * Clear RD_REQ Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | R | 0x0 | Interrupt Register Read Request Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Register Read Request Bit - clr_rd_req + * + * Read this register to clear the RD_REQ interrupt (bit 5) of the ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ field value from a register. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RD_REQ. + */ +struct ALT_I2C_CLR_RD_REQ_s +{ + const uint32_t clr_rd_req : 1; /* Interrupt Register Read Request Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RD_REQ. */ +typedef volatile struct ALT_I2C_CLR_RD_REQ_s ALT_I2C_CLR_RD_REQ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RD_REQ register from the beginning of the component. */ +#define ALT_I2C_CLR_RD_REQ_OFST 0x50 +/* The address of the ALT_I2C_CLR_RD_REQ register. */ +#define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST)) + +/* + * Register : Tx Abort Interrupt Register - ic_clr_tx_abrt + * + * Clear TX_ABRT Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Tx Abort Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx Abort Interrupt Bit - clr_tx_abort + * + * Read this register to clear the TX_ABRT interrupt (bit 6) of the + * ic_raw_intr_stat register, and the ic_tx_abrt_source register. This also + * releases the TX FIFO from the flushed/reset state, allowing more writes to the + * TX FIFO. Refer to Bit 9 of the ic_tx_abrt_source register for an exception to + * clearing ic_tx_abrt_source. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0 +/* The width in bits of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0 +/* Extracts the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT field value from a register. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value suitable for setting the register. */ +#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_TX_ABRT. + */ +struct ALT_I2C_CLR_TX_ABRT_s +{ + const uint32_t clr_tx_abort : 1; /* Tx Abort Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_TX_ABRT. */ +typedef volatile struct ALT_I2C_CLR_TX_ABRT_s ALT_I2C_CLR_TX_ABRT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_TX_ABRT register from the beginning of the component. */ +#define ALT_I2C_CLR_TX_ABRT_OFST 0x54 +/* The address of the ALT_I2C_CLR_TX_ABRT register. */ +#define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST)) + +/* + * Register : Rx Done Interrupt Register - ic_clr_rx_done + * + * Clear RX_DONE Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | R | 0x0 | RX_DONE Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RX_DONE Interrupt Bit - clr_rx_done + * + * Read this register to clear the RX_DONE interrupt (bit 7) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0 +/* The width in bits of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 +/* Extracts the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE field value from a register. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value suitable for setting the register. */ +#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_RX_DONE. + */ +struct ALT_I2C_CLR_RX_DONE_s +{ + const uint32_t clr_rx_done : 1; /* RX_DONE Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_RX_DONE. */ +typedef volatile struct ALT_I2C_CLR_RX_DONE_s ALT_I2C_CLR_RX_DONE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_RX_DONE register from the beginning of the component. */ +#define ALT_I2C_CLR_RX_DONE_OFST 0x58 +/* The address of the ALT_I2C_CLR_RX_DONE register. */ +#define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST)) + +/* + * Register : Activity Interrupt Register - ic_clr_activity + * + * Clears ACTIVITY Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | Activity Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Activity Interrupt Bit - clr_activity + * + * Reading this register clears the ACTIVITY interrupt if the I2C is not active + * anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt + * bit continues to be set. It is automatically cleared by hardware if the module + * is disabled and if there is no further activity on the bus. The value read from + * this register to get status of the ACTIVITY interrupt (bit 8) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 +/* The width in bits of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY field value from a register. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_ACTIVITY. + */ +struct ALT_I2C_CLR_ACTIVITY_s +{ + const uint32_t clr_activity : 1; /* Activity Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_ACTIVITY. */ +typedef volatile struct ALT_I2C_CLR_ACTIVITY_s ALT_I2C_CLR_ACTIVITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_ACTIVITY register from the beginning of the component. */ +#define ALT_I2C_CLR_ACTIVITY_OFST 0x5c +/* The address of the ALT_I2C_CLR_ACTIVITY register. */ +#define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST)) + +/* + * Register : Stop Detect Interrupt Register - ic_clr_stop_det + * + * Clear Interrupts. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [0] | R | 0x0 | Stop Detect Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Stop Detect Interrupt Bit - clr_stop_det + * + * Read this register to clear the clr_stop_det interrupt (bit 9) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0 +/* The width in bits of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 +/* Extracts the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET field value from a register. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value suitable for setting the register. */ +#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_STOP_DET. + */ +struct ALT_I2C_CLR_STOP_DET_s +{ + const uint32_t clr_stop_det : 1; /* Stop Detect Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_STOP_DET. */ +typedef volatile struct ALT_I2C_CLR_STOP_DET_s ALT_I2C_CLR_STOP_DET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_STOP_DET register from the beginning of the component. */ +#define ALT_I2C_CLR_STOP_DET_OFST 0x60 +/* The address of the ALT_I2C_CLR_STOP_DET register. */ +#define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST)) + +/* + * Register : Start Detect Interrupt Register - ic_clr_start_det + * + * Clears START_DET Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | Start Detect Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Detect Interrupt Bit - clr_start_det + * + * Read this register to clear the start_det interrupt (bit 10) of the + * ic_raw_intr_stat register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0 +/* The width in bits of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0 +/* Extracts the ALT_I2C_CLR_START_DET_CLR_START_DET field value from a register. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_START_DET_CLR_START_DET register field value suitable for setting the register. */ +#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_START_DET. + */ +struct ALT_I2C_CLR_START_DET_s +{ + const uint32_t clr_start_det : 1; /* Start Detect Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_START_DET. */ +typedef volatile struct ALT_I2C_CLR_START_DET_s ALT_I2C_CLR_START_DET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_START_DET register from the beginning of the component. */ +#define ALT_I2C_CLR_START_DET_OFST 0x64 +/* The address of the ALT_I2C_CLR_START_DET register. */ +#define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST)) + +/* + * Register : GEN CALL Interrupt Register - ic_clr_gen_call + * + * Clear GEN_CALL Interrupt Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | GEN CALL Interrupt Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GEN CALL Interrupt Bit - clr_gen_call + * + * Read this register to clear the GEN_CALL interrupt (bit 11) of ic_raw_intr_stat + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 +/* The width in bits of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 +/* Extracts the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL field value from a register. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_CLR_GEN_CALL. + */ +struct ALT_I2C_CLR_GEN_CALL_s +{ + const uint32_t clr_gen_call : 1; /* GEN CALL Interrupt Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_CLR_GEN_CALL. */ +typedef volatile struct ALT_I2C_CLR_GEN_CALL_s ALT_I2C_CLR_GEN_CALL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_CLR_GEN_CALL register from the beginning of the component. */ +#define ALT_I2C_CLR_GEN_CALL_OFST 0x68 +/* The address of the ALT_I2C_CLR_GEN_CALL register. */ +#define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST)) + +/* + * Register : Enable Register - ic_enable + * + * Enable and disable i2c operation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Enable Bit + * [1] | RW | 0x0 | TX abort Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable Bit - enable + * + * Controls whether the I2C is enabled. Software can disable I2C while it is + * active. However, it is important that care be taken to ensure that I2C is + * disabled properly. When the I2C is disabled, the following occurs: + * + * The TX FIFO and RX FIFO get flushed. Status bits in the IC_INTR_STAT register + * are still active until I2C goes into IDLE state. If the module is transmitting, + * it stops as well as deletes the contents of the transmit buffer after the + * current transfer is complete. If the module is receiving, the I2C stops the + * current transfer at the end of the current byte and does not acknowledge the + * transfer. The l4_sp_clk synchronizes pclk and ic_clk. The register + * ic_enable_status is added to allow software to determine when the hardware has + * completely shutdown in response to the IC_ENABLE register being set from 1 to 0. + * Only one register is required to be monitored. Procedure for Disabling I2C + * + * 1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling + * period for the highest I2C transfer speed used in the system and supported by + * I2C. For example, if the highest I2C transfer mode is 400 kb/s, then this + * ti2c_poll is 25us. + * + * 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any + * repeated polling operation exceeds this maximum value, an error is reported. 3. + * Execute a blocking thread/process/function that prevents any further I2C master + * transactions to be started by software, but allows any pending transfers to be + * completed. + * + * 4. The variable POLL_COUNT is initialized to zero. 5. Set IC_ENABLE to 0. + * + * 6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment + * POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant + * error code. + * + * 7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the + * previous step. Otherwise, exit with a relevant success code. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------|:------|:----------------------------------------------- + * ALT_I2C_EN_EN_E_DIS | 0x0 | Disables i2c. TX and RX FIFOs are held in an + * : | | erased state + * ALT_I2C_EN_EN_E_EN | 0x1 | Enables i2c. Software can disable i2c while it + * : | | is active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_EN_EN + * + * Disables i2c. TX and RX FIFOs are held in an erased state + */ +#define ALT_I2C_EN_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_EN_EN + * + * Enables i2c. Software can disable i2c while it is active + */ +#define ALT_I2C_EN_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_MSB 0 +/* The width in bits of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_EN register field value. */ +#define ALT_I2C_EN_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_EN_EN register field value. */ +#define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_EN_EN register field. */ +#define ALT_I2C_EN_EN_RESET 0x0 +/* Extracts the ALT_I2C_EN_EN field value from a register. */ +#define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_EN_EN register field value suitable for setting the register. */ +#define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TX abort Bit - txabort + * + * Write 1 does a TX abort. Self cleared on abort completion + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_MSB 1 +/* The width in bits of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_TXABT register field value. */ +#define ALT_I2C_EN_TXABT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_EN_TXABT register field value. */ +#define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_EN_TXABT register field. */ +#define ALT_I2C_EN_TXABT_RESET 0x0 +/* Extracts the ALT_I2C_EN_TXABT field value from a register. */ +#define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_EN_TXABT register field value suitable for setting the register. */ +#define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_EN. + */ +struct ALT_I2C_EN_s +{ + uint32_t enable : 1; /* Enable Bit */ + uint32_t txabort : 1; /* TX abort Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_EN. */ +typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_EN register from the beginning of the component. */ +#define ALT_I2C_EN_OFST 0x6c +/* The address of the ALT_I2C_EN register. */ +#define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST)) + +/* + * Register : Status Register - ic_status + * + * This is a read-only register used to indicate the current transfer status and + * FIFO status. The status register may be read at any time. None of the bits in + * this register request an interrupt.When the I2C is disabled by writing 0 in bit + * 0 of the ic_enable register: + * + * * Bits 1 and 2 are set to 1 + * + * * Bits 3 and 4 are set to 0 + * + * When the master or slave state machines goes to idle + * + * * Bits 5 and 6 are set to 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | R | 0x0 | Activity Status Bit + * [1] | R | 0x1 | TX FIFO Not Full Bit + * [2] | R | 0x1 | TX FIFO Empty Bit + * [3] | R | 0x0 | RX FIFO Empty Bit + * [4] | R | 0x0 | RX FIFO Full Bit + * [5] | R | 0x0 | Master FSM Activity Status Bit + * [6] | R | 0x0 | Slave FSM Activity Status Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Activity Status Bit - activity + * + * I2C Activity. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_MSB 0 +/* The width in bits of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_ACTIVITY register field value. */ +#define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_STAT_ACTIVITY register field value. */ +#define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_STAT_ACTIVITY register field. */ +#define ALT_I2C_STAT_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_STAT_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : TX FIFO Not Full Bit - tfnf + * + * Transmit Fifo Full + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------------- + * ALT_I2C_STAT_TFNF_E_FULL | 0x0 | Transmit FIFO is full + * ALT_I2C_STAT_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_TFNF + * + * Transmit FIFO is full + */ +#define ALT_I2C_STAT_TFNF_E_FULL 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_TFNF + * + * Transmit FIFO is not full + */ +#define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_MSB 1 +/* The width in bits of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_TFNF register field value. */ +#define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_STAT_TFNF register field value. */ +#define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_STAT_TFNF register field. */ +#define ALT_I2C_STAT_TFNF_RESET 0x1 +/* Extracts the ALT_I2C_STAT_TFNF field value from a register. */ +#define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_STAT_TFNF register field value suitable for setting the register. */ +#define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : TX FIFO Empty Bit - tfe + * + * Transmit FIFO Empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_I2C_STAT_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty + * ALT_I2C_STAT_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_TFE + * + * Transmit FIFO is not empty + */ +#define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_TFE + * + * Transmit FIFO is empty + */ +#define ALT_I2C_STAT_TFE_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_MSB 2 +/* The width in bits of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_TFE register field value. */ +#define ALT_I2C_STAT_TFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_STAT_TFE register field value. */ +#define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_STAT_TFE register field. */ +#define ALT_I2C_STAT_TFE_RESET 0x1 +/* Extracts the ALT_I2C_STAT_TFE field value from a register. */ +#define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_STAT_TFE register field value suitable for setting the register. */ +#define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : RX FIFO Empty Bit - rfne + * + * Receive FIFO Not Empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------- + * ALT_I2C_STAT_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty + * ALT_I2C_STAT_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_RFNE + * + * Receive FIFO is empty + */ +#define ALT_I2C_STAT_RFNE_E_EMPTY 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_RFNE + * + * Receive FIFO is not empty + */ +#define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_MSB 3 +/* The width in bits of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_RFNE register field value. */ +#define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_STAT_RFNE register field value. */ +#define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_STAT_RFNE register field. */ +#define ALT_I2C_STAT_RFNE_RESET 0x0 +/* Extracts the ALT_I2C_STAT_RFNE field value from a register. */ +#define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_STAT_RFNE register field value suitable for setting the register. */ +#define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : RX FIFO Full Bit - rff + * + * Receive FIFO Completely Full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------------------- + * ALT_I2C_STAT_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full + * ALT_I2C_STAT_RFF_E_FULL | 0x1 | Receive FIFO is full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_RFF + * + * Receive FIFO is not full + */ +#define ALT_I2C_STAT_RFF_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_RFF + * + * Receive FIFO is full + */ +#define ALT_I2C_STAT_RFF_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_MSB 4 +/* The width in bits of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_RFF register field value. */ +#define ALT_I2C_STAT_RFF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_STAT_RFF register field value. */ +#define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_STAT_RFF register field. */ +#define ALT_I2C_STAT_RFF_RESET 0x0 +/* Extracts the ALT_I2C_STAT_RFF field value from a register. */ +#define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_STAT_RFF register field value suitable for setting the register. */ +#define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Master FSM Activity Status Bit - mst_activity + * + * When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is + * set. Note:IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and + * MST_ACTIVITY bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------ + * ALT_I2C_STAT_MST_ACTIVITY_E_IDLE | 0x0 | Master FSM is in IDLE state. Master part of i2c + * : | | is not Active + * ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE | 0x1 | Master FSM is not in IDLE state. Master part of + * : | | i2c is Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY + * + * Master FSM is in IDLE state. Master part of i2c is not Active + */ +#define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY + * + * Master FSM is not in IDLE state. Master part of i2c is Active + */ +#define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_MSB 5 +/* The width in bits of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_MST_ACTIVITY register field value. */ +#define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_STAT_MST_ACTIVITY register field value. */ +#define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_STAT_MST_ACTIVITY register field. */ +#define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_MST_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_STAT_MST_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Slave FSM Activity Status Bit - slv_activity + * + * Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in + * the IDLE state, this bit is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE | 0x0 | Slave FSM is in IDLE state so the Slave part of + * : | | i2c is not Active + * ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE | 0x1 | Slave FSM is not in IDLE state so the Slave part + * : | | of i2c is Active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY + * + * Slave FSM is in IDLE state so the Slave part of i2c is not Active + */ +#define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0 +/* + * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY + * + * Slave FSM is not in IDLE state so the Slave part of i2c is Active + */ +#define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6 +/* The width in bits of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1 +/* The mask used to set the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0 +/* Extracts the ALT_I2C_STAT_SLV_ACTIVITY field value from a register. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_STAT_SLV_ACTIVITY register field value suitable for setting the register. */ +#define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_STAT. + */ +struct ALT_I2C_STAT_s +{ + const uint32_t activity : 1; /* Activity Status Bit */ + const uint32_t tfnf : 1; /* TX FIFO Not Full Bit */ + const uint32_t tfe : 1; /* TX FIFO Empty Bit */ + const uint32_t rfne : 1; /* RX FIFO Empty Bit */ + const uint32_t rff : 1; /* RX FIFO Full Bit */ + const uint32_t mst_activity : 1; /* Master FSM Activity Status Bit */ + const uint32_t slv_activity : 1; /* Slave FSM Activity Status Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_STAT. */ +typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_STAT register from the beginning of the component. */ +#define ALT_I2C_STAT_OFST 0x70 +/* The address of the ALT_I2C_STAT register. */ +#define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST)) + +/* + * Register : Transmit FIFO Level Register - ic_txflr + * + * This register contains the number of valid data entries in the transmit FIFO + * buffer. It is cleared whenever: + * + * * The I2C is disabled + * + * * There is a transmit abort that is, TX_ABRT bit is set in the ic_raw_intr_stat + * register. The slave bulk transmit mode is aborted The register increments + * whenever data is placed into the transmit FIFO and decrements when data is + * taken from the transmit FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [6:0] | R | 0x0 | Transmit FIFO Level Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Level Bit - txflr + * + * Transmit FIFO Level.Contains the number of valid data entries in the transmit + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_MSB 6 +/* The width in bits of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_WIDTH 7 +/* The mask used to set the ALT_I2C_TXFLR_TXFLR register field value. */ +#define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_I2C_TXFLR_TXFLR register field value. */ +#define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_I2C_TXFLR_TXFLR register field. */ +#define ALT_I2C_TXFLR_TXFLR_RESET 0x0 +/* Extracts the ALT_I2C_TXFLR_TXFLR field value from a register. */ +#define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_I2C_TXFLR_TXFLR register field value suitable for setting the register. */ +#define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TXFLR. + */ +struct ALT_I2C_TXFLR_s +{ + const uint32_t txflr : 7; /* Transmit FIFO Level Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TXFLR. */ +typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TXFLR register from the beginning of the component. */ +#define ALT_I2C_TXFLR_OFST 0x74 +/* The address of the ALT_I2C_TXFLR register. */ +#define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST)) + +/* + * Register : Receive FIFO Level Register - ic_rxflr + * + * This register contains the number of valid data entries in the receive FIFO + * buffer. It is cleared whenever: + * + * * The I2C is disabled + * + * * Whenever there is a transmit abort caused by any of the events tracked in + * ic_tx_abrt_source The register increments whenever data is placed into the + * receive FIFO and decrements when data is taken from the receive FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [6:0] | R | 0x0 | Receive FIFO Level Bit + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Level Bit - rxflr + * + * Receive FIFO Level. Contains the number of valid data entries in the receive + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_MSB 6 +/* The width in bits of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_WIDTH 7 +/* The mask used to set the ALT_I2C_RXFLR_RXFLR register field value. */ +#define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_I2C_RXFLR_RXFLR register field value. */ +#define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_I2C_RXFLR_RXFLR register field. */ +#define ALT_I2C_RXFLR_RXFLR_RESET 0x0 +/* Extracts the ALT_I2C_RXFLR_RXFLR field value from a register. */ +#define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_I2C_RXFLR_RXFLR register field value suitable for setting the register. */ +#define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_RXFLR. + */ +struct ALT_I2C_RXFLR_s +{ + const uint32_t rxflr : 7; /* Receive FIFO Level Bit */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_RXFLR. */ +typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_RXFLR register from the beginning of the component. */ +#define ALT_I2C_RXFLR_OFST 0x78 +/* The address of the ALT_I2C_RXFLR register. */ +#define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST)) + +/* + * Register : SDA Hold Register - ic_sda_hold + * + * This register controls the amount of time delay (in terms of number of l4_sp_clk + * clock periods) introduced in the falling edge of SCL, relative to SDA changing, + * when I2C services a read request in a slave-transmitter operation. The relevant + * I2C requirement is thd:DAT as detailed in the I2C Bus Specification. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------- + * [15:0] | RW | 0x1 | SDA Hold Bit + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDA Hold Bit - ic_sda_hold + * + * Program to a minimum 0f 300ns. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_MSB 15 +/* The width in bits of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_WIDTH 16 +/* The mask used to set the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_CLR_MSK 0xffff0000 +/* The reset value of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_RESET 0x1 +/* Extracts the ALT_I2C_SDA_HOLD_IC_SDA_HOLD field value from a register. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value suitable for setting the register. */ +#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SDA_HOLD. + */ +struct ALT_I2C_SDA_HOLD_s +{ + uint32_t ic_sda_hold : 16; /* SDA Hold Bit */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SDA_HOLD. */ +typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SDA_HOLD register from the beginning of the component. */ +#define ALT_I2C_SDA_HOLD_OFST 0x7c +/* The address of the ALT_I2C_SDA_HOLD register. */ +#define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST)) + +/* + * Register : Transmit Abort Source Register - ic_tx_abrt_source + * + * This register has 16 bits that indicate the source of the TX_ABRT bit. Except + * for Bit 9, this register is cleared whenever the ic_clr_tx_abrt register or the + * ic_clr_intr register is read. To clear Bit 9, the source of the + * abrt_sbyte_norstrt must be fixed first; RESTART must be enabled (ic_con[5]=1), + * the special bit must be cleared (ic_tar[11]), or the gc_or_start bit must be + * cleared (ic_tar[10]). Once the source of the abrt_sbyte_norstrt is fixed, then + * this bit can be cleared in the same manner as other bits in this register. If + * the source of the abrt_sbyte_norstrt is not fixed before attempting to clear + * this bit, Bit 9 clears for one cycle and is then re-asserted. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | Master Abort 7 Bit Address + * [1] | RW | 0x0 | Master Abort 10 Bit Address Byte 1 + * [2] | RW | 0x0 | Master Abort 10 Bit Address Byte 2 + * [3] | RW | 0x0 | Master Abort TX Noack Bit + * [4] | RW | 0x0 | Master Abort GC Noack Bit + * [5] | RW | 0x0 | Master Abort GC Read Bit + * [6] | RW | 0x0 | Master HS MC Ack + * [7] | RW | 0x0 | Master Abort START Byte + * [8] | RW | 0x0 | Master HS Restart Disabled + * [9] | RW | 0x0 | Master Abort START No Restart + * [10] | RW | 0x0 | Master Abort 10 Bit No Restart + * [11] | RW | 0x0 | Master Oper Master Dis + * [12] | RW | 0x0 | Master Abort Arbitration Lost + * [13] | RW | 0x0 | Slave Abort Flush TXFIFO + * [14] | RW | 0x0 | Slave Abort Arbitration Lost + * [15] | RW | 0x0 | Slave Abort Read TX + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Master Abort 7 Bit Address - abrt_7b_addr_noack + * + * Master is in 7-bit addressing mode and the address sent was not acknowledged by + * any slave. Role of i2c: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Master Abort 10 Bit Address Byte 1 - abrt_10addr1_noack + * + * Master is in 10-bit address mode and the first 10-bit address byte was not + * acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Master Abort 10 Bit Address Byte 2 - abrt_10addr2_noack + * + * Master is in 10-bit address mode and the second address byte of the 10-bit + * address was not acknowledged by any slave. Role of i2c: Master-Transmitter or + * Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Master Abort TX Noack Bit - abrt_txdata_noack + * + * This is a master-mode only bit. Master has received an acknowledgement for the + * address, but when it sent data byte(s) following the address, it did not receive + * an acknowledge from the remote slave(s). Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Master Abort GC Noack Bit - abrt_gcall_noack + * + * i2c in master mode sent a General Call and no slave on the bus acknowledged the + * General Call. Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Master Abort GC Read Bit - abrt_gcall_read + * + * i2c in master mode sent a General Call but the user programmed the byte + * following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to + * 1). Role of i2c: Master-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Master HS MC Ack - abrt_hs_ackdet + * + * Master is in High Speed mode and the High Speed Master code was acknowledged + * (wrong behavior). Role of i2c: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Master Abort START Byte - abrt_sbyte_ackdet + * + * Master has sent a START Byte and the START Byte was acknowledged (wrong + * behavior). Role of i2c: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Master HS Restart Disabled - abrt_hs_norstrt + * + * The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is + * trying to use the master to transfer data in High Speed mode. Role of i2c: + * Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Master Abort START No Restart - abrt_sbyte_norstrt + * + * To clear Bit 9, the source of then abrt_sbyte_norstrt must be fixed first; + * restart must be enabled (ic_con[5]=1), the SPECIAL bit must be cleared + * (ic_tar[11]), or the GC_OR_START bit must be cleared (ic_tar[10]). Once the + * source of the abrt_sbyte_norstrt is fixed, then this bit can be cleared in the + * same manner as other bits in this register. If the source of the + * abrt_sbyte_norstrt is not fixed before attempting to clear this bit, bit 9 + * clears for one cycle and then gets reasserted. 1: The restart is disabled + * (IC_RESTART_EN bit (ic_con[5]) =0) and the user is trying to send a START Byte. + * Role of I2C: Master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Master Abort 10 Bit No Restart - abrt_10b_rd_norstrt + * + * The restart is disabled (ic_restart_en bit (ic_con[5]) =0) and the master sends + * a read command in 10-bit addressing mode. Role of I2C: Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Master Oper Master Dis - abrt_master_dis + * + * User tries to initiate a Master operation with the Master mode disabled. Role of + * I2C: Master-Transmitter or Master-Receiver + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Master Abort Arbitration Lost - arb_lost + * + * Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the + * slave transmitter has lost arbitration. Note: I2C can be both master and slave + * at the same time. Role of i2c: Master-Transmitter or Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ARB_LOST field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Slave Abort Flush TXFIFO - abrt_slvflush_txfifo + * + * Slave has received a read command and some data exists in the TX FIFO so the + * slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Role of I2C: + * Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Slave Abort Arbitration Lost - abrt_slv_arblost + * + * Slave lost the bus while transmitting data to a remote master. + * IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never + * 'owns' the bus, something could go wrong on the bus. This is a fail safe check. + * For instance, during a data transmission at the low-to-high transition of SCL, + * if what is on the data bus is not what is supposed to be transmitted, then i2c + * no longer own the bus. Role of I2C: Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Slave Abort Read TX - abrt_slvrd_intx + * + * When the processor side responds to a slave mode request for data to be + * transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD + * register. Role of I2C: Slave-Transmitter + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15 +/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1 +/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000 +/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff +/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0 +/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX field value from a register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value suitable for setting the register. */ +#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_TX_ABRT_SRC. + */ +struct ALT_I2C_TX_ABRT_SRC_s +{ + uint32_t abrt_7b_addr_noack : 1; /* Master Abort 7 Bit Address */ + uint32_t abrt_10addr1_noack : 1; /* Master Abort 10 Bit Address Byte 1 */ + uint32_t abrt_10addr2_noack : 1; /* Master Abort 10 Bit Address Byte 2 */ + uint32_t abrt_txdata_noack : 1; /* Master Abort TX Noack Bit */ + uint32_t abrt_gcall_noack : 1; /* Master Abort GC Noack Bit */ + uint32_t abrt_gcall_read : 1; /* Master Abort GC Read Bit */ + uint32_t abrt_hs_ackdet : 1; /* Master HS MC Ack */ + uint32_t abrt_sbyte_ackdet : 1; /* Master Abort START Byte */ + uint32_t abrt_hs_norstrt : 1; /* Master HS Restart Disabled */ + uint32_t abrt_sbyte_norstrt : 1; /* Master Abort START No Restart */ + uint32_t abrt_10b_rd_norstrt : 1; /* Master Abort 10 Bit No Restart */ + uint32_t abrt_master_dis : 1; /* Master Oper Master Dis */ + uint32_t arb_lost : 1; /* Master Abort Arbitration Lost */ + uint32_t abrt_slvflush_txfifo : 1; /* Slave Abort Flush TXFIFO */ + uint32_t abrt_slv_arblost : 1; /* Slave Abort Arbitration Lost */ + uint32_t abrt_slvrd_intx : 1; /* Slave Abort Read TX */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_TX_ABRT_SRC. */ +typedef volatile struct ALT_I2C_TX_ABRT_SRC_s ALT_I2C_TX_ABRT_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_TX_ABRT_SRC register from the beginning of the component. */ +#define ALT_I2C_TX_ABRT_SRC_OFST 0x80 +/* The address of the ALT_I2C_TX_ABRT_SRC register. */ +#define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST)) + +/* + * Register : Generate Slave Data NACK - ic_slv_data_nack_only + * + * The register is used to generate a NACK for the data part of a transfer when i2c + * is acting as a slave-receiver. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [0] | RW | 0x0 | Generate Nack Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generate Nack Bit - nack + * + * This Bit control Nack generation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:-------------------------------------- + * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE | 0x1 | Generate NACK after data byte receive + * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM | 0x0 | Generate NACK/ACK normally + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK + * + * Generate NACK after data byte receive + */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1 +/* + * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK + * + * Generate NACK/ACK normally + */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0 +/* The width in bits of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1 +/* The mask used to set the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 +/* Extracts the ALT_I2C_SLV_DATA_NACK_ONLY_NACK field value from a register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value suitable for setting the register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. + */ +struct ALT_I2C_SLV_DATA_NACK_ONLY_s +{ + uint32_t nack : 1; /* Generate Nack Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. */ +typedef volatile struct ALT_I2C_SLV_DATA_NACK_ONLY_s ALT_I2C_SLV_DATA_NACK_ONLY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SLV_DATA_NACK_ONLY register from the beginning of the component. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84 +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register. */ +#define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST)) + +/* + * Register : DMA Control - ic_dma_cr + * + * The register is used to enable the DMA Controller interface operation. There is + * a separate bit for transmit and receive. This can be programmed regardless of + * the state of IC_ENABLE. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | Receive DMA Enable Bit + * [1] | RW | 0x0 | Transmit DMA Enable Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive DMA Enable Bit - rdmae + * + * This bit enables/disables the receive FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------- + * ALT_I2C_DMA_CR_RDMAE_E_DIS | 0x0 | Receive DMA disable + * ALT_I2C_DMA_CR_RDMAE_E_EN | 0x1 | Receive DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE + * + * Receive DMA disable + */ +#define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE + * + * Receive DMA enabled + */ +#define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_MSB 0 +/* The width in bits of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_WIDTH 1 +/* The mask used to set the ALT_I2C_DMA_CR_RDMAE register field value. */ +#define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_DMA_CR_RDMAE register field value. */ +#define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_DMA_CR_RDMAE register field. */ +#define ALT_I2C_DMA_CR_RDMAE_RESET 0x0 +/* Extracts the ALT_I2C_DMA_CR_RDMAE field value from a register. */ +#define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_DMA_CR_RDMAE register field value suitable for setting the register. */ +#define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit DMA Enable Bit - tdmae + * + * This bit enables/disables the transmit FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------- + * ALT_I2C_DMA_CR_TDMAE_E_DIS | 0x0 | Transmit DMA disable + * ALT_I2C_DMA_CR_TDMAE_E_EN | 0x1 | Transmit DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE + * + * Transmit DMA disable + */ +#define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE + * + * Transmit DMA enabled + */ +#define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_MSB 1 +/* The width in bits of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_WIDTH 1 +/* The mask used to set the ALT_I2C_DMA_CR_TDMAE register field value. */ +#define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_DMA_CR_TDMAE register field value. */ +#define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_DMA_CR_TDMAE register field. */ +#define ALT_I2C_DMA_CR_TDMAE_RESET 0x0 +/* Extracts the ALT_I2C_DMA_CR_TDMAE field value from a register. */ +#define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_DMA_CR_TDMAE register field value suitable for setting the register. */ +#define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_CR. + */ +struct ALT_I2C_DMA_CR_s +{ + uint32_t rdmae : 1; /* Receive DMA Enable Bit */ + uint32_t tdmae : 1; /* Transmit DMA Enable Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_CR. */ +typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_CR register from the beginning of the component. */ +#define ALT_I2C_DMA_CR_OFST 0x88 +/* The address of the ALT_I2C_DMA_CR register. */ +#define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST)) + +/* + * Register : DMA Transmit Data Level - ic_dma_tdlr + * + * This register supports DMA Transmit Operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [5:0] | RW | 0x0 | DMA Transmit Data Level Bit + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA Transmit Data Level Bit - dmatdl + * + * This bit field controls the level at which a DMA request is made by the transmit + * logic. It is equal to the watermark level; that is, the i2c_dma_tx_req signal is + * generated when the number of valid data entries in the transmit FIFO is equal to + * or below this field value, and TDMAE = 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_MSB 5 +/* The width in bits of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6 +/* The mask used to set the ALT_I2C_DMA_TDLR_DMATDL register field value. */ +#define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f +/* The mask used to clear the ALT_I2C_DMA_TDLR_DMATDL register field value. */ +#define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_I2C_DMA_TDLR_DMATDL register field. */ +#define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0 +/* Extracts the ALT_I2C_DMA_TDLR_DMATDL field value from a register. */ +#define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_I2C_DMA_TDLR_DMATDL register field value suitable for setting the register. */ +#define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_TDLR. + */ +struct ALT_I2C_DMA_TDLR_s +{ + uint32_t dmatdl : 6; /* DMA Transmit Data Level Bit */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_TDLR. */ +typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_TDLR register from the beginning of the component. */ +#define ALT_I2C_DMA_TDLR_OFST 0x8c +/* The address of the ALT_I2C_DMA_TDLR register. */ +#define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST)) + +/* + * Register : Receive Data Level - ic_dma_rdlr + * + * DMA Control Signals Interface. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [5:0] | RW | 0x0 | Receive Data Level Bits + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive Data Level Bits - dmardl + * + * This bit field controls the level at which a DMA request is made by the receive + * logic. The watermark level \= DMARDL+1; that is, dma_rx_req is generated when + * the number of valid data entries in the receive FIFO is equal to or more than + * this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then + * dma_rx_req is asserted when or more data entries are present in the receive + * FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_MSB 5 +/* The width in bits of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6 +/* The mask used to set the ALT_I2C_DMA_RDLR_DMARDL register field value. */ +#define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f +/* The mask used to clear the ALT_I2C_DMA_RDLR_DMARDL register field value. */ +#define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_I2C_DMA_RDLR_DMARDL register field. */ +#define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0 +/* Extracts the ALT_I2C_DMA_RDLR_DMARDL field value from a register. */ +#define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_I2C_DMA_RDLR_DMARDL register field value suitable for setting the register. */ +#define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_DMA_RDLR. + */ +struct ALT_I2C_DMA_RDLR_s +{ + uint32_t dmardl : 6; /* Receive Data Level Bits */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_DMA_RDLR. */ +typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_DMA_RDLR register from the beginning of the component. */ +#define ALT_I2C_DMA_RDLR_OFST 0x90 +/* The address of the ALT_I2C_DMA_RDLR register. */ +#define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST)) + +/* + * Register : SDA Setup Register - ic_sda_setup + * + * This register controls the amount of time delay (in terms of number of l4_sp_clk + * clock periods) introduced in the rising edge of SCL relative to SDA changing by + * holding SCL low when I2C services a read request while operating as a slave- + * transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the + * I2C Bus Specification. This register must be programmed with a value equal to or + * greater than 2. + * + * Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * + * (l4_sp_clk)], so if the user requires 10 l4_sp_clk periods of setup time, they + * should program a value of 11. The IC_SDA_SETUP register is only used by the I2C + * when operating as a slave transmitter. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [7:0] | RW | 0x64 | SDA Setup Value + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDA Setup Value - sda_setup + * + * It is recommended that if the required delay is 1000ns, then for an l4_sp_clk + * frequency of 10 MHz, ic_sda_setup should be programmed to a value of 11. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7 +/* The width in bits of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8 +/* The mask used to set the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64 +/* Extracts the ALT_I2C_SDA_SETUP_SDA_SETUP field value from a register. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_SDA_SETUP_SDA_SETUP register field value suitable for setting the register. */ +#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_SDA_SETUP. + */ +struct ALT_I2C_SDA_SETUP_s +{ + uint32_t sda_setup : 8; /* SDA Setup Value */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_SDA_SETUP. */ +typedef volatile struct ALT_I2C_SDA_SETUP_s ALT_I2C_SDA_SETUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_SDA_SETUP register from the beginning of the component. */ +#define ALT_I2C_SDA_SETUP_OFST 0x94 +/* The address of the ALT_I2C_SDA_SETUP register. */ +#define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST)) + +/* + * Register : ACK General Call - ic_ack_general_call + * + * The register controls whether i2c responds with a ACK or NACK when it receives + * an I2C General Call address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x1 | ACK General Call Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ACK General Call Bit - ack_gen_call + * + * When an ACK is asserted, (by asserting i2c_out_data) when it receives a General + * call. Otherwise, i2c responds with a NACK (by negating i2c_out_data). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------- + * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK | 0x0 | I2C responds with a NACK + * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK | 0x1 | I2C responds with an ACK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL + * + * I2C responds with a NACK + */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0 +/* + * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL + * + * I2C responds with an ACK + */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 +/* The width in bits of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1 +/* The mask used to set the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 +/* Extracts the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL field value from a register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value suitable for setting the register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_ACK_GENERAL_CALL. + */ +struct ALT_I2C_ACK_GENERAL_CALL_s +{ + uint32_t ack_gen_call : 1; /* ACK General Call Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_ACK_GENERAL_CALL. */ +typedef volatile struct ALT_I2C_ACK_GENERAL_CALL_s ALT_I2C_ACK_GENERAL_CALL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_ACK_GENERAL_CALL register from the beginning of the component. */ +#define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98 +/* The address of the ALT_I2C_ACK_GENERAL_CALL register. */ +#define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST)) + +/* + * Register : Enable Status Register - ic_enable_status + * + * This register is used to report the i2c hardware status when the IC_ENABLE + * register is set from 1 to 0; that is, when i2c is disabled. If IC_ENABLE has + * been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE + * has been set to 0, bits 2:1 are only valid as soon as bit 0 is read as '0'. + * + * Note: When ic_enable has been written with '0' a delay occurs for bit 0 to be + * read as '0' because disabling the i2c depends on I2C bus activities. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | R | 0x0 | Enable Status Bit + * [1] | R | 0x0 | Slave Disabled While Busy Bit + * [2] | R | 0x0 | Slave Received Data Lost Bit + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable Status Bit - ic_en + * + * This bit always reflects the value driven on the output port ic_en. Not used in + * current application. When read as 1, i2c is deemed to be in an enabled state. + * When read as 0, i2c is deemed completely inactive. NOTE: The CPU can safely read + * this bit anytime. When this bit is read as 0, the CPU can safely read + * slv_rx_data_lost (bit 2) and slv_disabled_while_busy (bit 1). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_MSB 0 +/* The width in bits of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_IC_EN register field value. */ +#define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_I2C_EN_STAT_IC_EN register field value. */ +#define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_I2C_EN_STAT_IC_EN register field. */ +#define ALT_I2C_EN_STAT_IC_EN_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_IC_EN field value from a register. */ +#define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_I2C_EN_STAT_IC_EN register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Slave Disabled While Busy Bit - slv_disabled_while_busy + * + * This bit indicates if a potential or active Slave operation has been aborted due + * to the setting of the ic_enable register from 1 to 0. This bit is set when the + * CPU writes a 0 to the ic_enable register while: (a) I2C is receiving the address + * byte of the Slave-Transmitter operation from a remote master; OR, (b) address + * and data bytes of the Slave-Receiver operation from a remote master. When read + * as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, + * irrespective of whether the I2C address matches the slave address set in i2c + * (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 + * but has not taken effect. NOTE: If the remote I2C master terminates the transfer + * with a STOP condition before the i2c has a chance to NACK a transfer, and + * IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as + * 0, i2c is deemed to have been disabled when there is master activity, or when + * the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) + * is read as 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1 +/* The width in bits of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002 +/* The mask used to clear the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd +/* The reset value of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY field value from a register. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Slave Received Data Lost Bit - slv_rx_data_lost + * + * This bit indicates if a Slave-Receiver operation has been aborted with at least + * one data byte received from an I2C transfer due to the setting of IC ENABLE from + * 1 to 0. When read as 1, i2c is deemed to have been actively engaged in an + * aborted I2C transfer (with matching address) and the data phase of the I2C + * transfer has been entered, even though a data byte has been responded with a + * NACK. NOTE: If the remote I2C master terminates the transfer with a STOP + * condition before the i2c has a chance to NACK a transfer, and ic_enable has been + * set to 0, then this bit is also set to 1. When read as 0, i2c is deemed to have + * been disabled without being actively involved in the data phase of a Slave- + * Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is + * read as 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2 +/* The width in bits of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1 +/* The mask used to set the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004 +/* The mask used to clear the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb +/* The reset value of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0 +/* Extracts the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST field value from a register. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value suitable for setting the register. */ +#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_EN_STAT. + */ +struct ALT_I2C_EN_STAT_s +{ + const uint32_t ic_en : 1; /* Enable Status Bit */ + const uint32_t slv_disabled_while_busy : 1; /* Slave Disabled While Busy Bit */ + const uint32_t slv_rx_data_lost : 1; /* Slave Received Data Lost Bit */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_EN_STAT. */ +typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_EN_STAT register from the beginning of the component. */ +#define ALT_I2C_EN_STAT_OFST 0x9c +/* The address of the ALT_I2C_EN_STAT register. */ +#define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST)) + +/* + * Register : SS and FS Spike Suppression Limit Register - ic_fs_spklen + * + * This register is used to store the duration, measured in ic_clk cycles, of the + * longest spike that is filtered out by the spike suppression logic when the + * component is operating in SS or FS modes. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [7:0] | RW | 0x2 | Spike Suppression Limit Register + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Spike Suppression Limit Register - spklen + * + * This register must be set before any I2C bus transaction can take place to + * ensure stable operation. This register sets the duration, measured in ic_clk + * cycles, of the longest spike in the SCL or SDA lines that are filtered out by + * the spike suppression logic. This register can be written only when the I2C + * interface is disabled, which corresponds to the IC_ENABLE register being set to + * 0. Writes at other times have no effect. The minimum valid value is 1; hardware + * prevents values less than this being written, and if attempted results in 2 + * being set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_MSB 7 +/* The width in bits of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_WIDTH 8 +/* The mask used to set the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK 0x000000ff +/* The mask used to clear the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_CLR_MSK 0xffffff00 +/* The reset value of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_RESET 0x2 +/* Extracts the ALT_I2C_FS_SPKLEN_SPKLEN field value from a register. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_I2C_FS_SPKLEN_SPKLEN register field value suitable for setting the register. */ +#define ALT_I2C_FS_SPKLEN_SPKLEN_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_FS_SPKLEN. + */ +struct ALT_I2C_FS_SPKLEN_s +{ + uint32_t spklen : 8; /* Spike Suppression Limit Register */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_FS_SPKLEN. */ +typedef volatile struct ALT_I2C_FS_SPKLEN_s ALT_I2C_FS_SPKLEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_FS_SPKLEN register from the beginning of the component. */ +#define ALT_I2C_FS_SPKLEN_OFST 0xa0 +/* The address of the ALT_I2C_FS_SPKLEN register. */ +#define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST)) + +/* + * Register : Component Parameter Register 1 - ic_comp_param_1 + * + * This is a constant read-only register that contains encoded information about + * the component's parameter settings. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [1:0] | R | 0x2 | APB Data Width Register + * [3:2] | R | 0x2 | Max Speed Mode + * [4] | R | 0x0 | CNT Registers Access + * [5] | R | 0x1 | Intr IO + * [6] | R | 0x1 | Has DMA + * [7] | R | 0x1 | Add Encoded Params + * [15:8] | R | 0x3f | Rx Buffer Depth + * [23:16] | R | 0x3f | Tx Buffer Depth + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB Data Width Register - apb_data_width + * + * Sets the APB Data Width. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH + * + * APB Data Width is 32 Bits + */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2 +/* Extracts the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Max Speed Mode - max_speed_mode + * + * The value of this field determines the maximum i2c bus interface speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------- + * ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST | 0x2 | Fast Mode (400 kbit/s) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD + * + * Fast Mode (400 kbit/s) + */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2 +/* Extracts the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : CNT Registers Access - hc_count_values + * + * This makes the *CNT registers readable and writable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR | 0x0 | *CNT registers read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES + * + * * CNT registers read/write + */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef +/* The reset value of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 +/* Extracts the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Intr IO - intr_io + * + * All interrupt sources are combined in to a single output. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------- + * ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED | 0x1 | Combined Interrupt Output + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_INTR_IO + * + * Combined Interrupt Output + */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf +/* The reset value of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_INTR_IO field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_I2C_COMP_PARAM_1_INTR_IO register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Has DMA - has_dma + * + * This configures the inclusion of DMA handshaking interface signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------ + * ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT | 0x1 | Has DMA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HAS_DMA + * + * Has DMA + */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf +/* The reset value of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_HAS_DMA field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_I2C_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Add Encoded Params - add_encoded_params + * + * By adding in the encoded parameters, this gives firmware an easy and quick way + * of identifying the DesignWare component within an I/O memory map. Some critical + * design-time options determine how a driver should interact with the peripheral. + * There is a minimal area overhead by including these parameters. Allows a single + * driver to be developed for each component which will be self-configurable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------- + * ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Add Encoded Params + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS + * + * Add Encoded Params + */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1 +/* Extracts the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Rx Buffer Depth - rx_buffer_depth + * + * Sets Rx FIFO Depth. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------- + * ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Rx Fifo Depth 64 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH + * + * Rx Fifo Depth 64 Entries + */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff +/* The reset value of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f +/* Extracts the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Tx Buffer Depth - tx_buffer_depth + * + * Sets Tx FIFO Depth. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------- + * ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Tx Buffer Depth 64 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH + * + * Tx Buffer Depth 64 Entries + */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40 + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23 +/* The width in bits of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8 +/* The mask used to set the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff +/* The reset value of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f +/* Extracts the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH field value from a register. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value suitable for setting the register. */ +#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_PARAM_1. + */ +struct ALT_I2C_COMP_PARAM_1_s +{ + const uint32_t apb_data_width : 2; /* APB Data Width Register */ + const uint32_t max_speed_mode : 2; /* Max Speed Mode */ + const uint32_t hc_count_values : 1; /* CNT Registers Access */ + const uint32_t intr_io : 1; /* Intr IO */ + const uint32_t has_dma : 1; /* Has DMA */ + const uint32_t add_encoded_params : 1; /* Add Encoded Params */ + const uint32_t rx_buffer_depth : 8; /* Rx Buffer Depth */ + const uint32_t tx_buffer_depth : 8; /* Tx Buffer Depth */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_PARAM_1. */ +typedef volatile struct ALT_I2C_COMP_PARAM_1_s ALT_I2C_COMP_PARAM_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_PARAM_1 register from the beginning of the component. */ +#define ALT_I2C_COMP_PARAM_1_OFST 0xf4 +/* The address of the ALT_I2C_COMP_PARAM_1 register. */ +#define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST)) + +/* + * Register : Component Version Register - ic_comp_version + * + * Describes the version of the I2C + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------------------- + * [31:0] | R | 0x3132302a | Component Parameter Value + * + */ +/* + * Field : Component Parameter Value - ic_comp_version + * + * Specifies I2C release number (encoded as 4 ASCII characters) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:-----------|:-------------- + * ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A | 0x3132302a | Version 1.20a + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_I2C_COMP_VER_IC_COMP_VER + * + * Version 1.20a + */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A 0x3132302a + +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31 +/* The width in bits of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32 +/* The mask used to set the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff +/* The mask used to clear the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000 +/* The reset value of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132302a +/* Extracts the ALT_I2C_COMP_VER_IC_COMP_VER field value from a register. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_I2C_COMP_VER_IC_COMP_VER register field value suitable for setting the register. */ +#define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_VER. + */ +struct ALT_I2C_COMP_VER_s +{ + const uint32_t ic_comp_version : 32; /* Component Parameter Value */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_VER. */ +typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_VER register from the beginning of the component. */ +#define ALT_I2C_COMP_VER_OFST 0xf8 +/* The address of the ALT_I2C_COMP_VER register. */ +#define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST)) + +/* + * Register : Component Type Register - ic_comp_type + * + * Describes a unique ASCII value + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | R | 0x44570140 | Component Type Number + * + */ +/* + * Field : Component Type Number - ic_comp_type + * + * Designware Component Type number = 0x44_57_01_40. This assigned unique hex value + * is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit + * unsigned number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31 +/* The width in bits of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32 +/* The mask used to set the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000 +/* The reset value of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 +/* Extracts the ALT_I2C_COMP_TYPE_IC_COMP_TYPE field value from a register. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value suitable for setting the register. */ +#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_I2C_COMP_TYPE. + */ +struct ALT_I2C_COMP_TYPE_s +{ + const uint32_t ic_comp_type : 32; /* Component Type Number */ +}; + +/* The typedef declaration for register ALT_I2C_COMP_TYPE. */ +typedef volatile struct ALT_I2C_COMP_TYPE_s ALT_I2C_COMP_TYPE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_I2C_COMP_TYPE register from the beginning of the component. */ +#define ALT_I2C_COMP_TYPE_OFST 0xfc +/* The address of the ALT_I2C_COMP_TYPE register. */ +#define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_I2C. + */ +struct ALT_I2C_s +{ + volatile ALT_I2C_CON_t ic_con; /* ALT_I2C_CON */ + volatile ALT_I2C_TAR_t ic_tar; /* ALT_I2C_TAR */ + volatile ALT_I2C_SAR_t ic_sar; /* ALT_I2C_SAR */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_I2C_DATA_CMD_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ + volatile ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ + volatile ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ + volatile ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ + volatile ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ + volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ + volatile ALT_I2C_INTR_STAT_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ + volatile ALT_I2C_INTR_MSK_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ + volatile ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ + volatile ALT_I2C_RX_TL_t ic_rx_tl; /* ALT_I2C_RX_TL */ + volatile ALT_I2C_TX_TL_t ic_tx_tl; /* ALT_I2C_TX_TL */ + volatile ALT_I2C_CLR_INTR_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ + volatile ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ + volatile ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ + volatile ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ + volatile ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ + volatile ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ + volatile ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ + volatile ALT_I2C_CLR_ACTIVITY_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ + volatile ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ + volatile ALT_I2C_CLR_START_DET_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ + volatile ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ + volatile ALT_I2C_EN_t ic_enable; /* ALT_I2C_EN */ + volatile ALT_I2C_STAT_t ic_status; /* ALT_I2C_STAT */ + volatile ALT_I2C_TXFLR_t ic_txflr; /* ALT_I2C_TXFLR */ + volatile ALT_I2C_RXFLR_t ic_rxflr; /* ALT_I2C_RXFLR */ + volatile ALT_I2C_SDA_HOLD_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ + volatile ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ + volatile ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ + volatile ALT_I2C_DMA_CR_t ic_dma_cr; /* ALT_I2C_DMA_CR */ + volatile ALT_I2C_DMA_TDLR_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ + volatile ALT_I2C_DMA_RDLR_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ + volatile ALT_I2C_SDA_SETUP_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ + volatile ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ + volatile ALT_I2C_EN_STAT_t ic_enable_status; /* ALT_I2C_EN_STAT */ + volatile ALT_I2C_FS_SPKLEN_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ + volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ + volatile ALT_I2C_COMP_PARAM_1_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ + volatile ALT_I2C_COMP_VER_t ic_comp_version; /* ALT_I2C_COMP_VER */ + volatile ALT_I2C_COMP_TYPE_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ +}; + +/* The typedef declaration for register group ALT_I2C. */ +typedef volatile struct ALT_I2C_s ALT_I2C_t; +/* The struct declaration for the raw register contents of register group ALT_I2C. */ +struct ALT_I2C_raw_s +{ + volatile uint32_t ic_con; /* ALT_I2C_CON */ + volatile uint32_t ic_tar; /* ALT_I2C_TAR */ + volatile uint32_t ic_sar; /* ALT_I2C_SAR */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ + volatile uint32_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ + volatile uint32_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ + volatile uint32_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ + volatile uint32_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ + volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ + volatile uint32_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ + volatile uint32_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ + volatile uint32_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ + volatile uint32_t ic_rx_tl; /* ALT_I2C_RX_TL */ + volatile uint32_t ic_tx_tl; /* ALT_I2C_TX_TL */ + volatile uint32_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ + volatile uint32_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ + volatile uint32_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ + volatile uint32_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ + volatile uint32_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ + volatile uint32_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ + volatile uint32_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ + volatile uint32_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ + volatile uint32_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ + volatile uint32_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ + volatile uint32_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ + volatile uint32_t ic_enable; /* ALT_I2C_EN */ + volatile uint32_t ic_status; /* ALT_I2C_STAT */ + volatile uint32_t ic_txflr; /* ALT_I2C_TXFLR */ + volatile uint32_t ic_rxflr; /* ALT_I2C_RXFLR */ + volatile uint32_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ + volatile uint32_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ + volatile uint32_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ + volatile uint32_t ic_dma_cr; /* ALT_I2C_DMA_CR */ + volatile uint32_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ + volatile uint32_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ + volatile uint32_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ + volatile uint32_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ + volatile uint32_t ic_enable_status; /* ALT_I2C_EN_STAT */ + volatile uint32_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ + volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ + volatile uint32_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ + volatile uint32_t ic_comp_version; /* ALT_I2C_COMP_VER */ + volatile uint32_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_I2C. */ +typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_I2C_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_l3.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_l3.h new file mode 100644 index 000000000..09af557a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_l3.h @@ -0,0 +1,6299 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_L3 */ + +#ifndef __ALTERA_ALT_L3_H__ +#define __ALTERA_ALT_L3_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : L3 (NIC-301) GPV Registers - ALT_L3 + * L3 (NIC-301) GPV Registers + * + * Registers to control L3 interconnect settings + * + */ +/* + * Register : Remap - remap + * + * The L3 interconnect has separate address maps for the various L3 Masters. + * Generally, the addresses are the same for most masters. However, the sparse + * interconnect of the L3 switch causes some masters to have holes in their memory + * maps. The remap bits are not mutually exclusive. Each bit can be set + * independently and in combinations. Priority for the bits is determined by the + * bit offset: lower offset bits take precedence over higher offset bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [0] | W | 0x0 | MPU at 0x0 + * [1] | W | 0x0 | Non-MPU at 0x0 + * [2] | ??? | 0x0 | *UNDEFINED* + * [3] | W | 0x0 | HPS2FPGA AXI Bridge Visibility + * [4] | W | 0x0 | LWHPS2FPGA AXI Bridge Visibility + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MPU at 0x0 - mpuzero + * + * Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or + * On-chip RAM. This field only has an effect on the MPU L3 master. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------------------- + * ALT_L3_REMAP_MPUZERO_E_BOOTROM | 0x0 | Maps the Boot ROM to address 0x0 for the MPU L3 + * : | | master. Note that the Boot ROM is also always + * : | | mapped to address 0xfffd_0000 for the MPU L3 + * : | | master independent of this field's value. + * ALT_L3_REMAP_MPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the MPU + * : | | L3 master. Note that the On-chip RAM is also + * : | | always mapped to address 0xffff_0000 for the MPU + * : | | L3 master independent of this field's value. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_MPUZERO + * + * Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM + * is also always mapped to address 0xfffd_0000 for the MPU L3 master independent + * of this field's value. + */ +#define ALT_L3_REMAP_MPUZERO_E_BOOTROM 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_MPUZERO + * + * Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip + * RAM is also always mapped to address 0xffff_0000 for the MPU L3 master + * independent of this field's value. + */ +#define ALT_L3_REMAP_MPUZERO_E_OCRAM 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_MSB 0 +/* The width in bits of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_MPUZERO register field value. */ +#define ALT_L3_REMAP_MPUZERO_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_REMAP_MPUZERO register field value. */ +#define ALT_L3_REMAP_MPUZERO_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_REMAP_MPUZERO register field. */ +#define ALT_L3_REMAP_MPUZERO_RESET 0x0 +/* Extracts the ALT_L3_REMAP_MPUZERO field value from a register. */ +#define ALT_L3_REMAP_MPUZERO_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_REMAP_MPUZERO register field value suitable for setting the register. */ +#define ALT_L3_REMAP_MPUZERO_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Non-MPU at 0x0 - nonmpuzero + * + * Controls whether address 0x0 for the non-MPU L3 masters is mapped to the SDRAM + * or On-chip RAM. This field only has an effect on the non-MPU L3 masters. The + * non-MPU L3 masters are the DMA controllers (standalone and those built-in to + * peripherals), the FPGA2HPS AXI Bridge, and the DAP. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_L3_REMAP_NONMPUZERO_E_SDRAM | 0x0 | Maps the SDRAM to address 0x0 for the non-MPU L3 + * : | | masters. + * ALT_L3_REMAP_NONMPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the non- + * : | | MPU L3 masters. Note that the On-chip RAM is + * : | | also always mapped to address 0xffff_0000 for + * : | | the non-MPU L3 masters independent of this + * : | | field's value. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO + * + * Maps the SDRAM to address 0x0 for the non-MPU L3 masters. + */ +#define ALT_L3_REMAP_NONMPUZERO_E_SDRAM 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO + * + * Maps the On-chip RAM to address 0x0 for the non-MPU L3 masters. Note that the + * On-chip RAM is also always mapped to address 0xffff_0000 for the non-MPU L3 + * masters independent of this field's value. + */ +#define ALT_L3_REMAP_NONMPUZERO_E_OCRAM 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_MSB 1 +/* The width in bits of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_NONMPUZERO register field value. */ +#define ALT_L3_REMAP_NONMPUZERO_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_REMAP_NONMPUZERO register field value. */ +#define ALT_L3_REMAP_NONMPUZERO_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_REMAP_NONMPUZERO register field. */ +#define ALT_L3_REMAP_NONMPUZERO_RESET 0x0 +/* Extracts the ALT_L3_REMAP_NONMPUZERO field value from a register. */ +#define ALT_L3_REMAP_NONMPUZERO_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_REMAP_NONMPUZERO register field value suitable for setting the register. */ +#define ALT_L3_REMAP_NONMPUZERO_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : HPS2FPGA AXI Bridge Visibility - hps2fpga + * + * Controls whether the HPS2FPGA AXI Bridge is visible to L3 masters or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------------------------------------ + * ALT_L3_REMAP_H2F_E_INVISIBLE | 0x0 | The HPS2FPGA AXI Bridge is not visible to L3 + * : | | masters. Accesses to the associated address + * : | | range return an AXI decode error to the master. + * ALT_L3_REMAP_H2F_E_VISIBLE | 0x1 | The HPS2FPGA AXI Bridge is visible to L3 + * : | | masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_H2F + * + * The HPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated + * address range return an AXI decode error to the master. + */ +#define ALT_L3_REMAP_H2F_E_INVISIBLE 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_H2F + * + * The HPS2FPGA AXI Bridge is visible to L3 masters. + */ +#define ALT_L3_REMAP_H2F_E_VISIBLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_MSB 3 +/* The width in bits of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_H2F register field value. */ +#define ALT_L3_REMAP_H2F_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_REMAP_H2F register field value. */ +#define ALT_L3_REMAP_H2F_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_REMAP_H2F register field. */ +#define ALT_L3_REMAP_H2F_RESET 0x0 +/* Extracts the ALT_L3_REMAP_H2F field value from a register. */ +#define ALT_L3_REMAP_H2F_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_REMAP_H2F register field value suitable for setting the register. */ +#define ALT_L3_REMAP_H2F_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : LWHPS2FPGA AXI Bridge Visibility - lwhps2fpga + * + * Controls whether the Lightweight HPS2FPGA AXI Bridge is visible to L3 masters or + * not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------------------ + * ALT_L3_REMAP_LWH2F_E_INVISIBLE | 0x0 | The LWHPS2FPGA AXI Bridge is not visible to L3 + * : | | masters. Accesses to the associated address + * : | | range return an AXI decode error to the master. + * ALT_L3_REMAP_LWH2F_E_VISIBLE | 0x1 | The LWHPS2FPGA AXI Bridge is visible to L3 + * : | | masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_REMAP_LWH2F + * + * The LWHPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the + * associated address range return an AXI decode error to the master. + */ +#define ALT_L3_REMAP_LWH2F_E_INVISIBLE 0x0 +/* + * Enumerated value for register field ALT_L3_REMAP_LWH2F + * + * The LWHPS2FPGA AXI Bridge is visible to L3 masters. + */ +#define ALT_L3_REMAP_LWH2F_E_VISIBLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_MSB 4 +/* The width in bits of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_WIDTH 1 +/* The mask used to set the ALT_L3_REMAP_LWH2F register field value. */ +#define ALT_L3_REMAP_LWH2F_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_REMAP_LWH2F register field value. */ +#define ALT_L3_REMAP_LWH2F_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_REMAP_LWH2F register field. */ +#define ALT_L3_REMAP_LWH2F_RESET 0x0 +/* Extracts the ALT_L3_REMAP_LWH2F field value from a register. */ +#define ALT_L3_REMAP_LWH2F_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_REMAP_LWH2F register field value suitable for setting the register. */ +#define ALT_L3_REMAP_LWH2F_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_REMAP. + */ +struct ALT_L3_REMAP_s +{ + uint32_t mpuzero : 1; /* MPU at 0x0 */ + uint32_t nonmpuzero : 1; /* Non-MPU at 0x0 */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t hps2fpga : 1; /* HPS2FPGA AXI Bridge Visibility */ + uint32_t lwhps2fpga : 1; /* LWHPS2FPGA AXI Bridge Visibility */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_REMAP. */ +typedef volatile struct ALT_L3_REMAP_s ALT_L3_REMAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_REMAP register from the beginning of the component. */ +#define ALT_L3_REMAP_OFST 0x0 + +/* + * Register Group : Security Register Group - ALT_L3_SECGRP + * Security Register Group + * + * Registers that control slave security. + * + */ +/* + * Register : L4 Main Peripherals Security - l4main + * + * Controls security settings for L4 Main peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | W | 0x0 | SPI Slave 0 Security + * [1] | W | 0x0 | SPI Slave 1 Security + * [2] | W | 0x0 | DMA Secure Security + * [3] | W | 0x0 | DMA Non-secure Security + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SPI Slave 0 Security - spis0 + * + * Controls whether secure or non-secure masters can access the SPI Slave 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_SPIS0 field value from a register. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4MAIN_SPIS0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_SPIS0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SPI Slave 1 Security - spis1 + * + * Controls whether secure or non-secure masters can access the SPI Slave 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_SPIS1 field value from a register. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4MAIN_SPIS1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_SPIS1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : DMA Secure Security - dmasecure + * + * Controls whether secure or non-secure masters can access the DMA Secure slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_DMASECURE field value from a register. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4MAIN_DMASECURE register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_DMASECURE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DMA Non-secure Security - dmanonsecure + * + * Controls whether secure or non-secure masters can access the DMA Non-secure + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MAIN_DMANONSECURE field value from a register. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4MAIN_DMANONSECURE register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4MAIN. + */ +struct ALT_L3_SEC_L4MAIN_s +{ + uint32_t spis0 : 1; /* SPI Slave 0 Security */ + uint32_t spis1 : 1; /* SPI Slave 1 Security */ + uint32_t dmasecure : 1; /* DMA Secure Security */ + uint32_t dmanonsecure : 1; /* DMA Non-secure Security */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4MAIN. */ +typedef volatile struct ALT_L3_SEC_L4MAIN_s ALT_L3_SEC_L4MAIN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4MAIN register from the beginning of the component. */ +#define ALT_L3_SEC_L4MAIN_OFST 0x0 + +/* + * Register : L4 SP Peripherals Security - l4sp + * + * Controls security settings for L4 SP peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | W | 0x0 | SDRAM Registers Security + * [1] | W | 0x0 | SP Timer 0 Security + * [2] | W | 0x0 | I2C0 Security + * [3] | W | 0x0 | I2C1 Security + * [4] | W | 0x0 | I2C2 (EMAC 0) Security + * [5] | W | 0x0 | I2C3 (EMAC 1) Security + * [6] | W | 0x0 | UART 0 Security + * [7] | W | 0x0 | UART 1 Security + * [8] | W | 0x0 | CAN 0 Security + * [9] | W | 0x0 | CAN 1 Security + * [10] | W | 0x0 | SP Timer 1 Security + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDRAM Registers Security - sdrregs + * + * Controls whether secure or non-secure masters can access the SDRAM Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_SDRREGS_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_SDRREGS_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_SDRREGS register field value. */ +#define ALT_L3_SEC_L4SP_SDRREGS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4SP_SDRREGS register field value. */ +#define ALT_L3_SEC_L4SP_SDRREGS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4SP_SDRREGS register field. */ +#define ALT_L3_SEC_L4SP_SDRREGS_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_SDRREGS field value from a register. */ +#define ALT_L3_SEC_L4SP_SDRREGS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4SP_SDRREGS register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_SDRREGS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SP Timer 0 Security - sptimer0 + * + * Controls whether secure or non-secure masters can access the SP Timer 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_SPTMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_SPTMR0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_SPTMR0 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR0_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR0 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR0_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_SPTMR0 field value from a register. */ +#define ALT_L3_SEC_L4SP_SPTMR0_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4SP_SPTMR0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_SPTMR0_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : I2C0 Security - i2c0 + * + * Controls whether secure or non-secure masters can access the I2C0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C0 register field value. */ +#define ALT_L3_SEC_L4SP_I2C0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C0 register field value. */ +#define ALT_L3_SEC_L4SP_I2C0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4SP_I2C0 register field. */ +#define ALT_L3_SEC_L4SP_I2C0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C0 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4SP_I2C0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : I2C1 Security - i2c1 + * + * Controls whether secure or non-secure masters can access the I2C1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C1 register field value. */ +#define ALT_L3_SEC_L4SP_I2C1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C1 register field value. */ +#define ALT_L3_SEC_L4SP_I2C1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4SP_I2C1 register field. */ +#define ALT_L3_SEC_L4SP_I2C1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C1 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4SP_I2C1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : I2C2 (EMAC 0) Security - i2c2 + * + * Controls whether secure or non-secure masters can access the I2C2 (EMAC 0) + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C2_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C2_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C2_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_MSB 4 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C2 register field value. */ +#define ALT_L3_SEC_L4SP_I2C2_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C2 register field value. */ +#define ALT_L3_SEC_L4SP_I2C2_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_SEC_L4SP_I2C2 register field. */ +#define ALT_L3_SEC_L4SP_I2C2_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C2 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C2_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_SEC_L4SP_I2C2 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C2_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : I2C3 (EMAC 1) Security - i2c3 + * + * Controls whether secure or non-secure masters can access the I2C3 (EMAC 1) + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_I2C3_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_I2C3_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_I2C3_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_I2C3_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_MSB 5 +/* The width in bits of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_I2C3 register field value. */ +#define ALT_L3_SEC_L4SP_I2C3_SET_MSK 0x00000020 +/* The mask used to clear the ALT_L3_SEC_L4SP_I2C3 register field value. */ +#define ALT_L3_SEC_L4SP_I2C3_CLR_MSK 0xffffffdf +/* The reset value of the ALT_L3_SEC_L4SP_I2C3 register field. */ +#define ALT_L3_SEC_L4SP_I2C3_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_I2C3 field value from a register. */ +#define ALT_L3_SEC_L4SP_I2C3_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_L3_SEC_L4SP_I2C3 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_I2C3_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : UART 0 Security - uart0 + * + * Controls whether secure or non-secure masters can access the UART 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_UART0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_UART0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_UART0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_UART0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_MSB 6 +/* The width in bits of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_UART0 register field value. */ +#define ALT_L3_SEC_L4SP_UART0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_L3_SEC_L4SP_UART0 register field value. */ +#define ALT_L3_SEC_L4SP_UART0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_L3_SEC_L4SP_UART0 register field. */ +#define ALT_L3_SEC_L4SP_UART0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_UART0 field value from a register. */ +#define ALT_L3_SEC_L4SP_UART0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_L3_SEC_L4SP_UART0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_UART0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : UART 1 Security - uart1 + * + * Controls whether secure or non-secure masters can access the UART 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_UART1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_UART1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_UART1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_UART1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_UART1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_MSB 7 +/* The width in bits of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_UART1 register field value. */ +#define ALT_L3_SEC_L4SP_UART1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_L3_SEC_L4SP_UART1 register field value. */ +#define ALT_L3_SEC_L4SP_UART1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_L3_SEC_L4SP_UART1 register field. */ +#define ALT_L3_SEC_L4SP_UART1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_UART1 field value from a register. */ +#define ALT_L3_SEC_L4SP_UART1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_L3_SEC_L4SP_UART1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_UART1_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : CAN 0 Security - can0 + * + * Controls whether secure or non-secure masters can access the CAN 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_CAN0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_CAN0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_CAN0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_CAN0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_MSB 8 +/* The width in bits of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_CAN0 register field value. */ +#define ALT_L3_SEC_L4SP_CAN0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_L3_SEC_L4SP_CAN0 register field value. */ +#define ALT_L3_SEC_L4SP_CAN0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_L3_SEC_L4SP_CAN0 register field. */ +#define ALT_L3_SEC_L4SP_CAN0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_CAN0 field value from a register. */ +#define ALT_L3_SEC_L4SP_CAN0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_L3_SEC_L4SP_CAN0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_CAN0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : CAN 1 Security - can1 + * + * Controls whether secure or non-secure masters can access the CAN 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_CAN1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_CAN1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_CAN1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_CAN1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_MSB 9 +/* The width in bits of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_CAN1 register field value. */ +#define ALT_L3_SEC_L4SP_CAN1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_L3_SEC_L4SP_CAN1 register field value. */ +#define ALT_L3_SEC_L4SP_CAN1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_L3_SEC_L4SP_CAN1 register field. */ +#define ALT_L3_SEC_L4SP_CAN1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_CAN1 field value from a register. */ +#define ALT_L3_SEC_L4SP_CAN1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_L3_SEC_L4SP_CAN1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_CAN1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : SP Timer 1 Security - sptimer1 + * + * Controls whether secure or non-secure masters can access the SP Timer 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SP_SPTMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SP_SPTMR1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_MSB 10 +/* The width in bits of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SP_SPTMR1 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR1_SET_MSK 0x00000400 +/* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR1 register field value. */ +#define ALT_L3_SEC_L4SP_SPTMR1_CLR_MSK 0xfffffbff +/* The reset value of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ +#define ALT_L3_SEC_L4SP_SPTMR1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SP_SPTMR1 field value from a register. */ +#define ALT_L3_SEC_L4SP_SPTMR1_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_L3_SEC_L4SP_SPTMR1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SP_SPTMR1_SET(value) (((value) << 10) & 0x00000400) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4SP. + */ +struct ALT_L3_SEC_L4SP_s +{ + uint32_t sdrregs : 1; /* SDRAM Registers Security */ + uint32_t sptimer0 : 1; /* SP Timer 0 Security */ + uint32_t i2c0 : 1; /* I2C0 Security */ + uint32_t i2c1 : 1; /* I2C1 Security */ + uint32_t i2c2 : 1; /* I2C2 (EMAC 0) Security */ + uint32_t i2c3 : 1; /* I2C3 (EMAC 1) Security */ + uint32_t uart0 : 1; /* UART 0 Security */ + uint32_t uart1 : 1; /* UART 1 Security */ + uint32_t can0 : 1; /* CAN 0 Security */ + uint32_t can1 : 1; /* CAN 1 Security */ + uint32_t sptimer1 : 1; /* SP Timer 1 Security */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4SP. */ +typedef volatile struct ALT_L3_SEC_L4SP_s ALT_L3_SEC_L4SP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4SP register from the beginning of the component. */ +#define ALT_L3_SEC_L4SP_OFST 0x4 + +/* + * Register : L4 MP Peripherals Security - l4mp + * + * Controls security settings for L4 MP peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------- + * [0] | W | 0x0 | FPGA Manager Register Security + * [1] | W | 0x0 | DAP Security + * [2] | W | 0x0 | QSPI Registers Security + * [3] | W | 0x0 | SDMMC Security + * [4] | W | 0x0 | EMAC 0 Security + * [5] | W | 0x0 | EMAC 1 Security + * [6] | W | 0x0 | ACP ID Mapper Security + * [7] | W | 0x0 | GPIO 0 Security + * [8] | W | 0x0 | GPIO 1 Security + * [9] | W | 0x0 | GPIO 2 Security + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA Manager Register Security - fpgamgrregs + * + * Controls whether secure or non-secure masters can access the FPGA Manager + * Register slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_FPGAMGR register field value. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4MP_FPGAMGR register field value. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_FPGAMGR field value from a register. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4MP_FPGAMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_FPGAMGR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : DAP Security - dap + * + * Controls whether secure or non-secure masters can access the DAP slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_DAP_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_DAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_DAP + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_DAP_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_DAP + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_DAP_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_DAP register field value. */ +#define ALT_L3_SEC_L4MP_DAP_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4MP_DAP register field value. */ +#define ALT_L3_SEC_L4MP_DAP_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4MP_DAP register field. */ +#define ALT_L3_SEC_L4MP_DAP_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_DAP field value from a register. */ +#define ALT_L3_SEC_L4MP_DAP_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4MP_DAP register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_DAP_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : QSPI Registers Security - qspiregs + * + * Controls whether secure or non-secure masters can access the QSPI Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_QSPI_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_QSPI_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_QSPI_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_QSPI_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_QSPI register field value. */ +#define ALT_L3_SEC_L4MP_QSPI_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4MP_QSPI register field value. */ +#define ALT_L3_SEC_L4MP_QSPI_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4MP_QSPI register field. */ +#define ALT_L3_SEC_L4MP_QSPI_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_QSPI field value from a register. */ +#define ALT_L3_SEC_L4MP_QSPI_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4MP_QSPI register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_QSPI_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SDMMC Security - sdmmc + * + * Controls whether secure or non-secure masters can access the SDMMC slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_SDMMC_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_SDMMC_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_SDMMC register field value. */ +#define ALT_L3_SEC_L4MP_SDMMC_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4MP_SDMMC register field value. */ +#define ALT_L3_SEC_L4MP_SDMMC_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4MP_SDMMC register field. */ +#define ALT_L3_SEC_L4MP_SDMMC_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_SDMMC field value from a register. */ +#define ALT_L3_SEC_L4MP_SDMMC_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4MP_SDMMC register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_SDMMC_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : EMAC 0 Security - emac0 + * + * Controls whether secure or non-secure masters can access the EMAC 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_EMAC0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_EMAC0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_MSB 4 +/* The width in bits of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_EMAC0 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_SEC_L4MP_EMAC0 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC0_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_SEC_L4MP_EMAC0 register field. */ +#define ALT_L3_SEC_L4MP_EMAC0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_EMAC0 field value from a register. */ +#define ALT_L3_SEC_L4MP_EMAC0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_SEC_L4MP_EMAC0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_EMAC0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : EMAC 1 Security - emac1 + * + * Controls whether secure or non-secure masters can access the EMAC 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_EMAC1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_EMAC1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_MSB 5 +/* The width in bits of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_EMAC1 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_L3_SEC_L4MP_EMAC1 register field value. */ +#define ALT_L3_SEC_L4MP_EMAC1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_L3_SEC_L4MP_EMAC1 register field. */ +#define ALT_L3_SEC_L4MP_EMAC1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_EMAC1 field value from a register. */ +#define ALT_L3_SEC_L4MP_EMAC1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_L3_SEC_L4MP_EMAC1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_EMAC1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : ACP ID Mapper Security - acpidmap + * + * Controls whether secure or non-secure masters can access the ACP ID Mapper + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_MSB 6 +/* The width in bits of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_ACPIDMAP field value from a register. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_L3_SEC_L4MP_ACPIDMAP register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_ACPIDMAP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : GPIO 0 Security - gpio0 + * + * Controls whether secure or non-secure masters can access the GPIO 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_GPIO0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_GPIO0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_MSB 7 +/* The width in bits of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_GPIO0 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO0_SET_MSK 0x00000080 +/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO0 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO0_CLR_MSK 0xffffff7f +/* The reset value of the ALT_L3_SEC_L4MP_GPIO0 register field. */ +#define ALT_L3_SEC_L4MP_GPIO0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_GPIO0 field value from a register. */ +#define ALT_L3_SEC_L4MP_GPIO0_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_L3_SEC_L4MP_GPIO0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_GPIO0_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : GPIO 1 Security - gpio1 + * + * Controls whether secure or non-secure masters can access the GPIO 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_GPIO1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_GPIO1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_MSB 8 +/* The width in bits of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_GPIO1 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO1_SET_MSK 0x00000100 +/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO1 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO1_CLR_MSK 0xfffffeff +/* The reset value of the ALT_L3_SEC_L4MP_GPIO1 register field. */ +#define ALT_L3_SEC_L4MP_GPIO1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_GPIO1 field value from a register. */ +#define ALT_L3_SEC_L4MP_GPIO1_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_L3_SEC_L4MP_GPIO1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_GPIO1_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : GPIO 2 Security - gpio2 + * + * Controls whether secure or non-secure masters can access the GPIO 2 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4MP_GPIO2_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4MP_GPIO2_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_MSB 9 +/* The width in bits of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4MP_GPIO2 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO2_SET_MSK 0x00000200 +/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO2 register field value. */ +#define ALT_L3_SEC_L4MP_GPIO2_CLR_MSK 0xfffffdff +/* The reset value of the ALT_L3_SEC_L4MP_GPIO2 register field. */ +#define ALT_L3_SEC_L4MP_GPIO2_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4MP_GPIO2 field value from a register. */ +#define ALT_L3_SEC_L4MP_GPIO2_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_L3_SEC_L4MP_GPIO2 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4MP_GPIO2_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4MP. + */ +struct ALT_L3_SEC_L4MP_s +{ + uint32_t fpgamgrregs : 1; /* FPGA Manager Register Security */ + uint32_t dap : 1; /* DAP Security */ + uint32_t qspiregs : 1; /* QSPI Registers Security */ + uint32_t sdmmc : 1; /* SDMMC Security */ + uint32_t emac0 : 1; /* EMAC 0 Security */ + uint32_t emac1 : 1; /* EMAC 1 Security */ + uint32_t acpidmap : 1; /* ACP ID Mapper Security */ + uint32_t gpio0 : 1; /* GPIO 0 Security */ + uint32_t gpio1 : 1; /* GPIO 1 Security */ + uint32_t gpio2 : 1; /* GPIO 2 Security */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4MP. */ +typedef volatile struct ALT_L3_SEC_L4MP_s ALT_L3_SEC_L4MP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4MP register from the beginning of the component. */ +#define ALT_L3_SEC_L4MP_OFST 0x8 + +/* + * Register : L4 OSC1 Peripherals Security - l4osc1 + * + * Controls security settings for L4 OSC1 peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | W | 0x0 | L4 Watchdog Timer 0 Security + * [1] | W | 0x0 | L4 Watchdog Timer 0 Security + * [2] | W | 0x0 | Clock Manager Security + * [3] | W | 0x0 | Reset Manager Security + * [4] | W | 0x0 | System Manager Security + * [5] | W | 0x0 | OSC1 Timer 0 Security + * [6] | W | 0x0 | OSC1 Timer 1 Security + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : L4 Watchdog Timer 0 Security - l4wd0 + * + * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_L4WD0 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4OSC1_L4WD0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_L4WD0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : L4 Watchdog Timer 0 Security - l4wd1 + * + * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_L4WD1 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4OSC1_L4WD1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_L4WD1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Clock Manager Security - clkmgr + * + * Controls whether secure or non-secure masters can access the Clock Manager + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_CLKMGR field value from a register. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4OSC1_CLKMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_CLKMGR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Reset Manager Security - rstmgr + * + * Controls whether secure or non-secure masters can access the Reset Manager + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_MSB 3 +/* The width in bits of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_RSTMGR field value from a register. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L3_SEC_L4OSC1_RSTMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_RSTMGR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : System Manager Security - sysmgr + * + * Controls whether secure or non-secure masters can access the System Manager + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_MSB 4 +/* The width in bits of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_CLR_MSK 0xffffffef +/* The reset value of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_SYSMGR field value from a register. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L3_SEC_L4OSC1_SYSMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_SYSMGR_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : OSC1 Timer 0 Security - osc1timer0 + * + * Controls whether secure or non-secure masters can access the OSC1 Timer 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_MSB 5 +/* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET_MSK 0x00000020 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_CLR_MSK 0xffffffdf +/* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR0 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : OSC1 Timer 1 Security - osc1timer1 + * + * Controls whether secure or non-secure masters can access the OSC1 Timer 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_MSB 6 +/* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET_MSK 0x00000040 +/* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_CLR_MSK 0xffffffbf +/* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR1 field value from a register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4OSC1. + */ +struct ALT_L3_SEC_L4OSC1_s +{ + uint32_t l4wd0 : 1; /* L4 Watchdog Timer 0 Security */ + uint32_t l4wd1 : 1; /* L4 Watchdog Timer 0 Security */ + uint32_t clkmgr : 1; /* Clock Manager Security */ + uint32_t rstmgr : 1; /* Reset Manager Security */ + uint32_t sysmgr : 1; /* System Manager Security */ + uint32_t osc1timer0 : 1; /* OSC1 Timer 0 Security */ + uint32_t osc1timer1 : 1; /* OSC1 Timer 1 Security */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4OSC1. */ +typedef volatile struct ALT_L3_SEC_L4OSC1_s ALT_L3_SEC_L4OSC1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4OSC1 register from the beginning of the component. */ +#define ALT_L3_SEC_L4OSC1_OFST 0xc + +/* + * Register : L4 SPIM Peripherals Security - l4spim + * + * Controls security settings for L4 SPIM peripherals. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | W | 0x0 | SPI Master 0 Security + * [1] | W | 0x0 | SPI Master 1 Security + * [2] | W | 0x0 | Scan Manager Security + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SPI Master 0 Security - spim0 + * + * Controls whether secure or non-secure masters can access the SPI Master 0 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_MSB 0 +/* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SPIM_SPIM0 field value from a register. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_L4SPIM_SPIM0 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SPIM_SPIM0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SPI Master 1 Security - spim1 + * + * Controls whether secure or non-secure masters can access the SPI Master 1 slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1 + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1 + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_MSB 1 +/* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SPIM_SPIM1 field value from a register. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_SEC_L4SPIM_SPIM1 register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SPIM_SPIM1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Scan Manager Security - scanmgr + * + * Controls whether secure or non-secure masters can access the Scan Manager slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_MSB 2 +/* The width in bits of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_RESET 0x0 +/* Extracts the ALT_L3_SEC_L4SPIM_SCANMGR field value from a register. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L3_SEC_L4SPIM_SCANMGR register field value suitable for setting the register. */ +#define ALT_L3_SEC_L4SPIM_SCANMGR_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_L4SPIM. + */ +struct ALT_L3_SEC_L4SPIM_s +{ + uint32_t spim0 : 1; /* SPI Master 0 Security */ + uint32_t spim1 : 1; /* SPI Master 1 Security */ + uint32_t scanmgr : 1; /* Scan Manager Security */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_L4SPIM. */ +typedef volatile struct ALT_L3_SEC_L4SPIM_s ALT_L3_SEC_L4SPIM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_L4SPIM register from the beginning of the component. */ +#define ALT_L3_SEC_L4SPIM_OFST 0x10 + +/* + * Register : STM Peripheral Security - stm + * + * Controls security settings for STM peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | W | 0x0 | STM Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : STM Security - s + * + * Controls whether secure or non-secure masters can access the STM slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_STM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_STM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_STM_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_STM_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_STM_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_STM_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_STM_S register field value. */ +#define ALT_L3_SEC_STM_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_STM_S register field value. */ +#define ALT_L3_SEC_STM_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_STM_S register field. */ +#define ALT_L3_SEC_STM_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_STM_S field value from a register. */ +#define ALT_L3_SEC_STM_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_STM_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_STM_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_STM. + */ +struct ALT_L3_SEC_STM_s +{ + uint32_t s : 1; /* STM Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_STM. */ +typedef volatile struct ALT_L3_SEC_STM_s ALT_L3_SEC_STM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_STM register from the beginning of the component. */ +#define ALT_L3_SEC_STM_OFST 0x14 + +/* + * Register : LWHPS2FPGA AXI Bridge Registers Peripheral Security - lwhps2fpgaregs + * + * Controls security settings for LWHPS2FPGA AXI Bridge Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | W | 0x0 | LWHPS2FPGA AXI Bridge Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : LWHPS2FPGA AXI Bridge Registers Security - s + * + * Controls whether secure or non-secure masters can access the LWHPS2FPGA AXI + * Bridge Registers slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_LWH2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_LWH2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_LWH2F_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_LWH2F_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_LWH2F_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_LWH2F_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_LWH2F_S register field value. */ +#define ALT_L3_SEC_LWH2F_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_LWH2F_S register field value. */ +#define ALT_L3_SEC_LWH2F_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_LWH2F_S register field. */ +#define ALT_L3_SEC_LWH2F_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_LWH2F_S field value from a register. */ +#define ALT_L3_SEC_LWH2F_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_LWH2F_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_LWH2F_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_LWH2F. + */ +struct ALT_L3_SEC_LWH2F_s +{ + uint32_t s : 1; /* LWHPS2FPGA AXI Bridge Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_LWH2F. */ +typedef volatile struct ALT_L3_SEC_LWH2F_s ALT_L3_SEC_LWH2F_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_LWH2F register from the beginning of the component. */ +#define ALT_L3_SEC_LWH2F_OFST 0x18 + +/* + * Register : USB1 Registers Peripheral Security - usb1 + * + * Controls security settings for USB1 Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | W | 0x0 | USB1 Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB1 Registers Security - s + * + * Controls whether secure or non-secure masters can access the USB1 Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_USB1_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_USB1_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_USB1_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_USB1_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_USB1_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_USB1_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_USB1_S register field value. */ +#define ALT_L3_SEC_USB1_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_USB1_S register field value. */ +#define ALT_L3_SEC_USB1_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_USB1_S register field. */ +#define ALT_L3_SEC_USB1_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_USB1_S field value from a register. */ +#define ALT_L3_SEC_USB1_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_USB1_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_USB1_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_USB1. + */ +struct ALT_L3_SEC_USB1_s +{ + uint32_t s : 1; /* USB1 Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_USB1. */ +typedef volatile struct ALT_L3_SEC_USB1_s ALT_L3_SEC_USB1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_USB1 register from the beginning of the component. */ +#define ALT_L3_SEC_USB1_OFST 0x20 + +/* + * Register : NAND Flash Controller Data Peripheral Security - nanddata + * + * Controls security settings for NAND Flash Controller Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | W | 0x0 | NAND Flash Controller Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND Flash Controller Data Security - s + * + * Controls whether secure or non-secure masters can access the NAND Flash + * Controller Data slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_NANDDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_NANDDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_NANDDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_NANDDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_NANDDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_NANDDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_NANDDATA_S register field value. */ +#define ALT_L3_SEC_NANDDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_NANDDATA_S register field value. */ +#define ALT_L3_SEC_NANDDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_NANDDATA_S register field. */ +#define ALT_L3_SEC_NANDDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_NANDDATA_S field value from a register. */ +#define ALT_L3_SEC_NANDDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_NANDDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_NANDDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_NANDDATA. + */ +struct ALT_L3_SEC_NANDDATA_s +{ + uint32_t s : 1; /* NAND Flash Controller Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_NANDDATA. */ +typedef volatile struct ALT_L3_SEC_NANDDATA_s ALT_L3_SEC_NANDDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_NANDDATA register from the beginning of the component. */ +#define ALT_L3_SEC_NANDDATA_OFST 0x24 + +/* + * Register : USB0 Registers Peripheral Security - usb0 + * + * Controls security settings for USB0 Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | W | 0x0 | USB0 Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB0 Registers Security - s + * + * Controls whether secure or non-secure masters can access the USB0 Registers + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_USB0_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_USB0_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_USB0_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_USB0_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_USB0_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_USB0_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_USB0_S register field value. */ +#define ALT_L3_SEC_USB0_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_USB0_S register field value. */ +#define ALT_L3_SEC_USB0_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_USB0_S register field. */ +#define ALT_L3_SEC_USB0_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_USB0_S field value from a register. */ +#define ALT_L3_SEC_USB0_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_USB0_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_USB0_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_USB0. + */ +struct ALT_L3_SEC_USB0_s +{ + uint32_t s : 1; /* USB0 Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_USB0. */ +typedef volatile struct ALT_L3_SEC_USB0_s ALT_L3_SEC_USB0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_USB0 register from the beginning of the component. */ +#define ALT_L3_SEC_USB0_OFST 0x78 + +/* + * Register : NAND Flash Controller Registers Peripheral Security - nandregs + * + * Controls security settings for NAND Flash Controller Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | W | 0x0 | NAND Flash Controller Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND Flash Controller Registers Security - s + * + * Controls whether secure or non-secure masters can access the NAND Flash + * Controller Registers slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_NAND_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_NAND_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_NAND_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_NAND_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_NAND_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_NAND_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_NAND_S register field value. */ +#define ALT_L3_SEC_NAND_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_NAND_S register field value. */ +#define ALT_L3_SEC_NAND_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_NAND_S register field. */ +#define ALT_L3_SEC_NAND_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_NAND_S field value from a register. */ +#define ALT_L3_SEC_NAND_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_NAND_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_NAND_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_NAND. + */ +struct ALT_L3_SEC_NAND_s +{ + uint32_t s : 1; /* NAND Flash Controller Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_NAND. */ +typedef volatile struct ALT_L3_SEC_NAND_s ALT_L3_SEC_NAND_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_NAND register from the beginning of the component. */ +#define ALT_L3_SEC_NAND_OFST 0x7c + +/* + * Register : QSPI Flash Controller Data Peripheral Security - qspidata + * + * Controls security settings for QSPI Flash Controller Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | W | 0x0 | QSPI Flash Controller Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : QSPI Flash Controller Data Security - s + * + * Controls whether secure or non-secure masters can access the QSPI Flash + * Controller Data slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_QSPIDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_QSPIDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_QSPIDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_QSPIDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_QSPIDATA_S register field value. */ +#define ALT_L3_SEC_QSPIDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_QSPIDATA_S register field value. */ +#define ALT_L3_SEC_QSPIDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_QSPIDATA_S register field. */ +#define ALT_L3_SEC_QSPIDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_QSPIDATA_S field value from a register. */ +#define ALT_L3_SEC_QSPIDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_QSPIDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_QSPIDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_QSPIDATA. + */ +struct ALT_L3_SEC_QSPIDATA_s +{ + uint32_t s : 1; /* QSPI Flash Controller Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_QSPIDATA. */ +typedef volatile struct ALT_L3_SEC_QSPIDATA_s ALT_L3_SEC_QSPIDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_QSPIDATA register from the beginning of the component. */ +#define ALT_L3_SEC_QSPIDATA_OFST 0x80 + +/* + * Register : FPGA Manager Data Peripheral Security - fpgamgrdata + * + * Controls security settings for FPGA Manager Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | W | 0x0 | FPGA Manager Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA Manager Data Security - s + * + * Controls whether secure or non-secure masters can access the FPGA Manager Data + * slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_FPGAMGRDATA_S register field value. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_FPGAMGRDATA_S register field value. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_FPGAMGRDATA_S field value from a register. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_FPGAMGRDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_FPGAMGRDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_FPGAMGRDATA. + */ +struct ALT_L3_SEC_FPGAMGRDATA_s +{ + uint32_t s : 1; /* FPGA Manager Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_FPGAMGRDATA. */ +typedef volatile struct ALT_L3_SEC_FPGAMGRDATA_s ALT_L3_SEC_FPGAMGRDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_FPGAMGRDATA register from the beginning of the component. */ +#define ALT_L3_SEC_FPGAMGRDATA_OFST 0x84 + +/* + * Register : HPS2FPGA AXI Bridge Registers Peripheral Security - hps2fpgaregs + * + * Controls security settings for HPS2FPGA AXI Bridge Registers peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | W | 0x0 | HPS2FPGA AXI Bridge Registers Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : HPS2FPGA AXI Bridge Registers Security - s + * + * Controls whether secure or non-secure masters can access the HPS2FPGA AXI Bridge + * Registers slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_H2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_H2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_H2F_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_H2F_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_H2F_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_H2F_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_H2F_S register field value. */ +#define ALT_L3_SEC_H2F_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_H2F_S register field value. */ +#define ALT_L3_SEC_H2F_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_H2F_S register field. */ +#define ALT_L3_SEC_H2F_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_H2F_S field value from a register. */ +#define ALT_L3_SEC_H2F_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_H2F_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_H2F_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_H2F. + */ +struct ALT_L3_SEC_H2F_s +{ + uint32_t s : 1; /* HPS2FPGA AXI Bridge Registers Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_H2F. */ +typedef volatile struct ALT_L3_SEC_H2F_s ALT_L3_SEC_H2F_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_H2F register from the beginning of the component. */ +#define ALT_L3_SEC_H2F_OFST 0x88 + +/* + * Register : MPU ACP Peripheral Security - acp + * + * Controls security settings for MPU ACP peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | W | 0x0 | MPU ACP Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : MPU ACP Security - s + * + * Controls whether secure or non-secure masters can access the MPU ACP slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_ACP_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_ACP_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_ACP_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_ACP_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_ACP_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_ACP_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_ACP_S register field value. */ +#define ALT_L3_SEC_ACP_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_ACP_S register field value. */ +#define ALT_L3_SEC_ACP_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_ACP_S register field. */ +#define ALT_L3_SEC_ACP_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_ACP_S field value from a register. */ +#define ALT_L3_SEC_ACP_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_ACP_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_ACP_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_ACP. + */ +struct ALT_L3_SEC_ACP_s +{ + uint32_t s : 1; /* MPU ACP Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_ACP. */ +typedef volatile struct ALT_L3_SEC_ACP_s ALT_L3_SEC_ACP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_ACP register from the beginning of the component. */ +#define ALT_L3_SEC_ACP_OFST 0x8c + +/* + * Register : ROM Peripheral Security - rom + * + * Controls security settings for ROM peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | W | 0x0 | ROM Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ROM Security - s + * + * Controls whether secure or non-secure masters can access the ROM slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_ROM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_ROM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_ROM_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_ROM_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_ROM_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_ROM_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_ROM_S register field value. */ +#define ALT_L3_SEC_ROM_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_ROM_S register field value. */ +#define ALT_L3_SEC_ROM_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_ROM_S register field. */ +#define ALT_L3_SEC_ROM_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_ROM_S field value from a register. */ +#define ALT_L3_SEC_ROM_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_ROM_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_ROM_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_ROM. + */ +struct ALT_L3_SEC_ROM_s +{ + uint32_t s : 1; /* ROM Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_ROM. */ +typedef volatile struct ALT_L3_SEC_ROM_s ALT_L3_SEC_ROM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_ROM register from the beginning of the component. */ +#define ALT_L3_SEC_ROM_OFST 0x90 + +/* + * Register : On-chip RAM Peripheral Security - ocram + * + * Controls security settings for On-chip RAM peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | W | 0x0 | On-chip RAM Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : On-chip RAM Security - s + * + * Controls whether secure or non-secure masters can access the On-chip RAM slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_OCRAM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_OCRAM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_OCRAM_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_OCRAM_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_OCRAM_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_OCRAM_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_OCRAM_S register field value. */ +#define ALT_L3_SEC_OCRAM_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_OCRAM_S register field value. */ +#define ALT_L3_SEC_OCRAM_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_OCRAM_S register field. */ +#define ALT_L3_SEC_OCRAM_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_OCRAM_S field value from a register. */ +#define ALT_L3_SEC_OCRAM_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_OCRAM_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_OCRAM_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_OCRAM. + */ +struct ALT_L3_SEC_OCRAM_s +{ + uint32_t s : 1; /* On-chip RAM Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_OCRAM. */ +typedef volatile struct ALT_L3_SEC_OCRAM_s ALT_L3_SEC_OCRAM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_OCRAM register from the beginning of the component. */ +#define ALT_L3_SEC_OCRAM_OFST 0x94 + +/* + * Register : SDRAM Data Peripheral Security - sdrdata + * + * Controls security settings for SDRAM Data peripheral. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [0] | W | 0x0 | SDRAM Data Security + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDRAM Data Security - s + * + * Controls whether secure or non-secure masters can access the SDRAM Data slave. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------------------------- + * ALT_L3_SEC_SDRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure + * : | | master. + * ALT_L3_SEC_SDRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or + * : | | non-secure masters. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_SEC_SDRDATA_S + * + * The slave can only be accessed by a secure master. + */ +#define ALT_L3_SEC_SDRDATA_S_E_SECURE 0x0 +/* + * Enumerated value for register field ALT_L3_SEC_SDRDATA_S + * + * The slave can only be accessed by a secure or non-secure masters. + */ +#define ALT_L3_SEC_SDRDATA_S_E_NONSECURE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_MSB 0 +/* The width in bits of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_WIDTH 1 +/* The mask used to set the ALT_L3_SEC_SDRDATA_S register field value. */ +#define ALT_L3_SEC_SDRDATA_S_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_SEC_SDRDATA_S register field value. */ +#define ALT_L3_SEC_SDRDATA_S_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_SEC_SDRDATA_S register field. */ +#define ALT_L3_SEC_SDRDATA_S_RESET 0x0 +/* Extracts the ALT_L3_SEC_SDRDATA_S field value from a register. */ +#define ALT_L3_SEC_SDRDATA_S_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_SEC_SDRDATA_S register field value suitable for setting the register. */ +#define ALT_L3_SEC_SDRDATA_S_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_SEC_SDRDATA. + */ +struct ALT_L3_SEC_SDRDATA_s +{ + uint32_t s : 1; /* SDRAM Data Security */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_SEC_SDRDATA. */ +typedef volatile struct ALT_L3_SEC_SDRDATA_s ALT_L3_SEC_SDRDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_SEC_SDRDATA register from the beginning of the component. */ +#define ALT_L3_SEC_SDRDATA_OFST 0x98 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SECGRP. + */ +struct ALT_L3_SECGRP_s +{ + volatile ALT_L3_SEC_L4MAIN_t l4main; /* ALT_L3_SEC_L4MAIN */ + volatile ALT_L3_SEC_L4SP_t l4sp; /* ALT_L3_SEC_L4SP */ + volatile ALT_L3_SEC_L4MP_t l4mp; /* ALT_L3_SEC_L4MP */ + volatile ALT_L3_SEC_L4OSC1_t l4osc1; /* ALT_L3_SEC_L4OSC1 */ + volatile ALT_L3_SEC_L4SPIM_t l4spim; /* ALT_L3_SEC_L4SPIM */ + volatile ALT_L3_SEC_STM_t stm; /* ALT_L3_SEC_STM */ + volatile ALT_L3_SEC_LWH2F_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */ + volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */ + volatile ALT_L3_SEC_USB1_t usb1; /* ALT_L3_SEC_USB1 */ + volatile ALT_L3_SEC_NANDDATA_t nanddata; /* ALT_L3_SEC_NANDDATA */ + volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */ + volatile ALT_L3_SEC_USB0_t usb0; /* ALT_L3_SEC_USB0 */ + volatile ALT_L3_SEC_NAND_t nandregs; /* ALT_L3_SEC_NAND */ + volatile ALT_L3_SEC_QSPIDATA_t qspidata; /* ALT_L3_SEC_QSPIDATA */ + volatile ALT_L3_SEC_FPGAMGRDATA_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */ + volatile ALT_L3_SEC_H2F_t hps2fpgaregs; /* ALT_L3_SEC_H2F */ + volatile ALT_L3_SEC_ACP_t acp; /* ALT_L3_SEC_ACP */ + volatile ALT_L3_SEC_ROM_t rom; /* ALT_L3_SEC_ROM */ + volatile ALT_L3_SEC_OCRAM_t ocram; /* ALT_L3_SEC_OCRAM */ + volatile ALT_L3_SEC_SDRDATA_t sdrdata; /* ALT_L3_SEC_SDRDATA */ +}; + +/* The typedef declaration for register group ALT_L3_SECGRP. */ +typedef volatile struct ALT_L3_SECGRP_s ALT_L3_SECGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SECGRP. */ +struct ALT_L3_SECGRP_raw_s +{ + volatile uint32_t l4main; /* ALT_L3_SEC_L4MAIN */ + volatile uint32_t l4sp; /* ALT_L3_SEC_L4SP */ + volatile uint32_t l4mp; /* ALT_L3_SEC_L4MP */ + volatile uint32_t l4osc1; /* ALT_L3_SEC_L4OSC1 */ + volatile uint32_t l4spim; /* ALT_L3_SEC_L4SPIM */ + volatile uint32_t stm; /* ALT_L3_SEC_STM */ + volatile uint32_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */ + volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */ + volatile uint32_t usb1; /* ALT_L3_SEC_USB1 */ + volatile uint32_t nanddata; /* ALT_L3_SEC_NANDDATA */ + volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */ + volatile uint32_t usb0; /* ALT_L3_SEC_USB0 */ + volatile uint32_t nandregs; /* ALT_L3_SEC_NAND */ + volatile uint32_t qspidata; /* ALT_L3_SEC_QSPIDATA */ + volatile uint32_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */ + volatile uint32_t hps2fpgaregs; /* ALT_L3_SEC_H2F */ + volatile uint32_t acp; /* ALT_L3_SEC_ACP */ + volatile uint32_t rom; /* ALT_L3_SEC_ROM */ + volatile uint32_t ocram; /* ALT_L3_SEC_OCRAM */ + volatile uint32_t sdrdata; /* ALT_L3_SEC_SDRDATA */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SECGRP. */ +typedef volatile struct ALT_L3_SECGRP_raw_s ALT_L3_SECGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ID Register Group - ALT_L3_IDGRP + * ID Register Group + * + * Contains registers that identify the ARM NIC-301 IP Core. + * + */ +/* + * Register : Peripheral ID4 Register - periph_id_4 + * + * JEP106 continuation code + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [7:0] | R | 0x4 | Peripheral ID4 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Peripheral ID4 - periph_id_4 + * + * JEP106 continuation code + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4 +/* Extracts the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_4. + */ +struct ALT_L3_ID_PERIPH_ID_4_s +{ + const uint32_t periph_id_4 : 8; /* Peripheral ID4 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_4. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_4_s ALT_L3_ID_PERIPH_ID_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_4 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_4_OFST 0xfd0 + +/* + * Register : Peripheral ID0 Register - periph_id_0 + * + * Peripheral ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [7:0] | R | 0x1 | Part Number [7:0] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Part Number [7:0] - pn7to0 + * + * Part Number [7:0] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_RESET 0x1 +/* Extracts the ALT_L3_ID_PERIPH_ID_0_PN7TO0 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_0. + */ +struct ALT_L3_ID_PERIPH_ID_0_s +{ + const uint32_t pn7to0 : 8; /* Part Number [7:0] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_0. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_0_s ALT_L3_ID_PERIPH_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_0 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_0_OFST 0xfe0 + +/* + * Register : Peripheral ID1 Register - periph_id_1 + * + * Peripheral ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8 + * + * JEP106[3:0], Part Number [11:8] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3 +/* Extracts the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_1. + */ +struct ALT_L3_ID_PERIPH_ID_1_s +{ + const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_1. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_1_s ALT_L3_ID_PERIPH_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_1 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_1_OFST 0xfe4 + +/* + * Register : Peripheral ID2 Register - periph_id_2 + * + * Peripheral ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4 + * + * Revision, JEP106 code flag, JEP106[6:4] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b +/* Extracts the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_2. + */ +struct ALT_L3_ID_PERIPH_ID_2_s +{ + const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_2. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_2_s ALT_L3_ID_PERIPH_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_2 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_2_OFST 0xfe8 + +/* + * Register : Peripheral ID3 Register - periph_id_3 + * + * Peripheral ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [3:0] | R | 0x0 | Customer Model Number + * [7:4] | R | 0x0 | Revision + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Customer Model Number - cust_mod_num + * + * Customer Model Number + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0 +/* Extracts the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Revision - rev_and + * + * Revision + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_MSB 7 +/* The width in bits of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_WIDTH 4 +/* The mask used to set the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f +/* The reset value of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_RESET 0x0 +/* Extracts the ALT_L3_ID_PERIPH_ID_3_REV_AND field value from a register. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_L3_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */ +#define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_PERIPH_ID_3. + */ +struct ALT_L3_ID_PERIPH_ID_3_s +{ + const uint32_t cust_mod_num : 4; /* Customer Model Number */ + const uint32_t rev_and : 4; /* Revision */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_3. */ +typedef volatile struct ALT_L3_ID_PERIPH_ID_3_s ALT_L3_ID_PERIPH_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_PERIPH_ID_3 register from the beginning of the component. */ +#define ALT_L3_ID_PERIPH_ID_3_OFST 0xfec + +/* + * Register : Component ID0 Register - comp_id_0 + * + * Component ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xd | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_RESET 0xd +/* Extracts the ALT_L3_ID_COMP_ID_0_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_0. + */ +struct ALT_L3_ID_COMP_ID_0_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_0. */ +typedef volatile struct ALT_L3_ID_COMP_ID_0_s ALT_L3_ID_COMP_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_0 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_0_OFST 0xff0 + +/* + * Register : Component ID1 Register - comp_id_1 + * + * Component ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------- + * [7:0] | R | 0xf0 | Generic IP component class, Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generic IP component class, Preamble - genipcompcls_preamble + * + * Generic IP component class, Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0 +/* Extracts the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_1. + */ +struct ALT_L3_ID_COMP_ID_1_s +{ + const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_1. */ +typedef volatile struct ALT_L3_ID_COMP_ID_1_s ALT_L3_ID_COMP_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_1 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_1_OFST 0xff4 + +/* + * Register : Component ID2 Register - comp_id_2 + * + * Component ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0x5 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_RESET 0x5 +/* Extracts the ALT_L3_ID_COMP_ID_2_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_2. + */ +struct ALT_L3_ID_COMP_ID_2_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_2. */ +typedef volatile struct ALT_L3_ID_COMP_ID_2_s ALT_L3_ID_COMP_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_2 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_2_OFST 0xff8 + +/* + * Register : Component ID3 Register - comp_id_3 + * + * Component ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xb1 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_MSB 7 +/* The width in bits of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_RESET 0xb1 +/* Extracts the ALT_L3_ID_COMP_ID_3_PREAMBLE field value from a register. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L3_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */ +#define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_ID_COMP_ID_3. + */ +struct ALT_L3_ID_COMP_ID_3_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_ID_COMP_ID_3. */ +typedef volatile struct ALT_L3_ID_COMP_ID_3_s ALT_L3_ID_COMP_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_ID_COMP_ID_3 register from the beginning of the component. */ +#define ALT_L3_ID_COMP_ID_3_OFST 0xffc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_IDGRP. + */ +struct ALT_L3_IDGRP_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile ALT_L3_ID_PERIPH_ID_4_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile ALT_L3_ID_PERIPH_ID_0_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */ + volatile ALT_L3_ID_PERIPH_ID_1_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */ + volatile ALT_L3_ID_PERIPH_ID_2_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */ + volatile ALT_L3_ID_PERIPH_ID_3_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */ + volatile ALT_L3_ID_COMP_ID_0_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */ + volatile ALT_L3_ID_COMP_ID_1_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */ + volatile ALT_L3_ID_COMP_ID_2_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */ + volatile ALT_L3_ID_COMP_ID_3_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for register group ALT_L3_IDGRP. */ +typedef volatile struct ALT_L3_IDGRP_s ALT_L3_IDGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_IDGRP. */ +struct ALT_L3_IDGRP_raw_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile uint32_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile uint32_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */ + volatile uint32_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */ + volatile uint32_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */ + volatile uint32_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */ + volatile uint32_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */ + volatile uint32_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */ + volatile uint32_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */ + volatile uint32_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_IDGRP. */ +typedef volatile struct ALT_L3_IDGRP_raw_s ALT_L3_IDGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Master Register Group - ALT_L3_MSTGRP + * Master Register Group + * + * Registers associated with master interfaces in the L3 Interconnect. Note that a + * master in the L3 Interconnect connects to a slave in a module. + * + */ +/* + * Register Group : L4 MAIN - ALT_L3_MST_L4MAIN + * L4 MAIN + * + * Registers associated with the L4 MAIN master. This master is used to access the + * APB slaves on the L4 MAIN bus. + * + */ +/* + * Register : Bus Matrix Issuing Functionality Modification Register - fn_mod_bm_iss + * + * Sets the issuing capability of the preceding switch arbitration scheme to + * multiple or single outstanding transactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_RD + * [1] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_WR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : rd + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------- + * ALT_L3_FN_MOD_BM_ISS_RD_E_MULT | 0x0 | Multiple outstanding read transactions + * ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD + * + * Multiple outstanding read transactions + */ +#define ALT_L3_FN_MOD_BM_ISS_RD_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD + * + * Only a single outstanding read transaction + */ +#define ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_BM_ISS_RD register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_RD register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_BM_ISS_RD field value from a register. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD_BM_ISS_RD register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_BM_ISS_RD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : wr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------------------------------------- + * ALT_L3_FN_MOD_BM_ISS_WR_E_MULT | 0x0 | Multiple outstanding write transactions + * ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR + * + * Multiple outstanding write transactions + */ +#define ALT_L3_FN_MOD_BM_ISS_WR_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR + * + * Only a single outstanding write transaction + */ +#define ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_MSB 1 +/* The width in bits of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_BM_ISS_WR register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_WR register field value. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_BM_ISS_WR field value from a register. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_FN_MOD_BM_ISS_WR register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_BM_ISS_WR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD_BM_ISS. + */ +struct ALT_L3_FN_MOD_BM_ISS_s +{ + uint32_t rd : 1; /* ALT_L3_FN_MOD_BM_ISS_RD */ + uint32_t wr : 1; /* ALT_L3_FN_MOD_BM_ISS_WR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD_BM_ISS. */ +typedef volatile struct ALT_L3_FN_MOD_BM_ISS_s ALT_L3_FN_MOD_BM_ISS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD_BM_ISS register from the beginning of the component. */ +#define ALT_L3_FN_MOD_BM_ISS_OFST 0x8 +/* The address of the ALT_L3_FN_MOD_BM_ISS register. */ +#define ALT_L3_FN_MOD_BM_ISS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_BM_ISS_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4MAIN. + */ +struct ALT_L3_MST_L4MAIN_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4MAIN. */ +typedef volatile struct ALT_L3_MST_L4MAIN_s ALT_L3_MST_L4MAIN_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */ +struct ALT_L3_MST_L4MAIN_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */ +typedef volatile struct ALT_L3_MST_L4MAIN_raw_s ALT_L3_MST_L4MAIN_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 SP - ALT_L3_MST_L4SP + * L4 SP + * + * Registers associated with the L4 SP master. This master is used to access the + * APB slaves on the L4 SP bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4SP. + */ +struct ALT_L3_MST_L4SP_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4SP. */ +typedef volatile struct ALT_L3_MST_L4SP_s ALT_L3_MST_L4SP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SP. */ +struct ALT_L3_MST_L4SP_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SP. */ +typedef volatile struct ALT_L3_MST_L4SP_raw_s ALT_L3_MST_L4SP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 MP - ALT_L3_MST_L4MP + * L4 MP + * + * Registers associated with the L4 MP master. This master is used to access the + * APB slaves on the L4 MP bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4MP. + */ +struct ALT_L3_MST_L4MP_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4MP. */ +typedef volatile struct ALT_L3_MST_L4MP_s ALT_L3_MST_L4MP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MP. */ +struct ALT_L3_MST_L4MP_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MP. */ +typedef volatile struct ALT_L3_MST_L4MP_raw_s ALT_L3_MST_L4MP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 OSC1 - ALT_L3_MST_L4OSC1 + * L4 OSC1 + * + * Registers associated with the L4 OSC1 master. This master is used to access the + * APB slaves on the L4 OSC1 bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4OSC1. + */ +struct ALT_L3_MST_L4OSC1_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4OSC1. */ +typedef volatile struct ALT_L3_MST_L4OSC1_s ALT_L3_MST_L4OSC1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */ +struct ALT_L3_MST_L4OSC1_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */ +typedef volatile struct ALT_L3_MST_L4OSC1_raw_s ALT_L3_MST_L4OSC1_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : L4 SPIM - ALT_L3_MST_L4SPIM + * L4 SPIM + * + * Registers associated with the L4 SPIM master. This master is used to access the + * APB slaves on the L4 SPIM bus. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_L4SPIM. + */ +struct ALT_L3_MST_L4SPIM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for register group ALT_L3_MST_L4SPIM. */ +typedef volatile struct ALT_L3_MST_L4SPIM_s ALT_L3_MST_L4SPIM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */ +struct ALT_L3_MST_L4SPIM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */ +typedef volatile struct ALT_L3_MST_L4SPIM_raw_s ALT_L3_MST_L4SPIM_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : STM - ALT_L3_MST_STM + * STM + * + * Registers associated with the STM master. This master is used to access the STM + * AXI slave. + * + */ +/* + * Register : Issuing Functionality Modification Register - fn_mod + * + * Sets the block issuing capability to multiple or single outstanding + * transactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | ALT_L3_FN_MOD_RD + * [1] | RW | 0x0 | ALT_L3_FN_MOD_WR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : rd + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------- + * ALT_L3_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions + * ALT_L3_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_RD + * + * Multiple outstanding read transactions + */ +#define ALT_L3_FN_MOD_RD_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_RD + * + * Only a single outstanding read transaction + */ +#define ALT_L3_FN_MOD_RD_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_RD register field value. */ +#define ALT_L3_FN_MOD_RD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD_RD register field value. */ +#define ALT_L3_FN_MOD_RD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD_RD register field. */ +#define ALT_L3_FN_MOD_RD_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_RD field value from a register. */ +#define ALT_L3_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD_RD register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : wr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:-------------------------------------------- + * ALT_L3_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions + * ALT_L3_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_WR + * + * Multiple outstanding write transactions + */ +#define ALT_L3_FN_MOD_WR_E_MULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_WR + * + * Only a single outstanding write transaction + */ +#define ALT_L3_FN_MOD_WR_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_MSB 1 +/* The width in bits of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_WR register field value. */ +#define ALT_L3_FN_MOD_WR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_FN_MOD_WR register field value. */ +#define ALT_L3_FN_MOD_WR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_FN_MOD_WR register field. */ +#define ALT_L3_FN_MOD_WR_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_WR field value from a register. */ +#define ALT_L3_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_FN_MOD_WR register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD. + */ +struct ALT_L3_FN_MOD_s +{ + uint32_t rd : 1; /* ALT_L3_FN_MOD_RD */ + uint32_t wr : 1; /* ALT_L3_FN_MOD_WR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD. */ +typedef volatile struct ALT_L3_FN_MOD_s ALT_L3_FN_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD register from the beginning of the component. */ +#define ALT_L3_FN_MOD_OFST 0x108 +/* The address of the ALT_L3_FN_MOD register. */ +#define ALT_L3_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_STM. + */ +struct ALT_L3_MST_STM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_STM. */ +typedef volatile struct ALT_L3_MST_STM_s ALT_L3_MST_STM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_STM. */ +struct ALT_L3_MST_STM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_STM. */ +typedef volatile struct ALT_L3_MST_STM_raw_s ALT_L3_MST_STM_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : LWHPS2FPGA - ALT_L3_MST_LWH2F + * LWHPS2FPGA + * + * Registers associated with the LWHPS2FPGA AXI Bridge master. This master is used + * to access the LWHPS2FPGA AXI Bridge slave. This slave is used to access the + * registers for all 3 AXI bridges and to access slaves in the FPGA connected to + * the LWHPS2FPGA AXI Bridge. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_LWH2F. + */ +struct ALT_L3_MST_LWH2F_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_LWH2F. */ +typedef volatile struct ALT_L3_MST_LWH2F_s ALT_L3_MST_LWH2F_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */ +struct ALT_L3_MST_LWH2F_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */ +typedef volatile struct ALT_L3_MST_LWH2F_raw_s ALT_L3_MST_LWH2F_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB1 - ALT_L3_MST_USB1 + * USB1 + * + * Registers associated with the USB1 master. This master is used to access the + * registers in USB1. + * + */ +/* + * Register : AHB Control Register - ahb_cntl + * + * Sets the block issuing capability to one outstanding transaction. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | ALT_L3_AHB_CNTL_DECERR_EN + * [1] | RW | 0x0 | ALT_L3_AHB_CNTL_FORCE_INCR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : decerr_en + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_L3_AHB_CNTL_DECERR_EN_E_DIS | 0x0 | No DECERR response. + * ALT_L3_AHB_CNTL_DECERR_EN_E_EN | 0x1 | If the AHB protocol conversion function receives + * : | | an unaligned address or a write data beat + * : | | without all the byte strobes set, creates a + * : | | DECERR response. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN + * + * No DECERR response. + */ +#define ALT_L3_AHB_CNTL_DECERR_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN + * + * If the AHB protocol conversion function receives an unaligned address or a write + * data beat without all the byte strobes set, creates a DECERR response. + */ +#define ALT_L3_AHB_CNTL_DECERR_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_MSB 0 +/* The width in bits of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_WIDTH 1 +/* The mask used to set the ALT_L3_AHB_CNTL_DECERR_EN register field value. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_AHB_CNTL_DECERR_EN register field value. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_RESET 0x0 +/* Extracts the ALT_L3_AHB_CNTL_DECERR_EN field value from a register. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_AHB_CNTL_DECERR_EN register field value suitable for setting the register. */ +#define ALT_L3_AHB_CNTL_DECERR_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : force_incr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------------- + * ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS | 0x0 | Multiple outstanding write transactions + * ALT_L3_AHB_CNTL_FORCE_INCR_E_EN | 0x1 | If a beat is received that has no write data + * : | | strobes set, that write data beat is replaced + * : | | with an IDLE beat. Also, causes all transactions + * : | | that are to be output to the AHB domain to be an + * : | | undefined length INCR. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR + * + * Multiple outstanding write transactions + */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS 0x0 +/* + * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR + * + * If a beat is received that has no write data strobes set, that write data beat + * is replaced with an IDLE beat. Also, causes all transactions that are to be + * output to the AHB domain to be an undefined length INCR. + */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_MSB 1 +/* The width in bits of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_WIDTH 1 +/* The mask used to set the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_RESET 0x0 +/* Extracts the ALT_L3_AHB_CNTL_FORCE_INCR field value from a register. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_AHB_CNTL_FORCE_INCR register field value suitable for setting the register. */ +#define ALT_L3_AHB_CNTL_FORCE_INCR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_AHB_CNTL. + */ +struct ALT_L3_AHB_CNTL_s +{ + uint32_t decerr_en : 1; /* ALT_L3_AHB_CNTL_DECERR_EN */ + uint32_t force_incr : 1; /* ALT_L3_AHB_CNTL_FORCE_INCR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_AHB_CNTL. */ +typedef volatile struct ALT_L3_AHB_CNTL_s ALT_L3_AHB_CNTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_AHB_CNTL register from the beginning of the component. */ +#define ALT_L3_AHB_CNTL_OFST 0x44 +/* The address of the ALT_L3_AHB_CNTL register. */ +#define ALT_L3_AHB_CNTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_AHB_CNTL_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_USB1. + */ +struct ALT_L3_MST_USB1_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_L3_MST_USB1. */ +typedef volatile struct ALT_L3_MST_USB1_s ALT_L3_MST_USB1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_USB1. */ +struct ALT_L3_MST_USB1_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB1. */ +typedef volatile struct ALT_L3_MST_USB1_raw_s ALT_L3_MST_USB1_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NANDDATA - ALT_L3_MST_NANDDATA + * NANDDATA + * + * Registers associated with the NANDDATA master. This master is used to access + * data in the NAND flash controller. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_NANDDATA. + */ +struct ALT_L3_MST_NANDDATA_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_NANDDATA. */ +typedef volatile struct ALT_L3_MST_NANDDATA_s ALT_L3_MST_NANDDATA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */ +struct ALT_L3_MST_NANDDATA_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */ +typedef volatile struct ALT_L3_MST_NANDDATA_raw_s ALT_L3_MST_NANDDATA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB0 - ALT_L3_MST_USB0 + * USB0 + * + * Registers associated with the USB0 master. This master is used to access the + * registers in USB0. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_USB0. + */ +struct ALT_L3_MST_USB0_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_L3_MST_USB0. */ +typedef volatile struct ALT_L3_MST_USB0_s ALT_L3_MST_USB0_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_USB0. */ +struct ALT_L3_MST_USB0_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB0. */ +typedef volatile struct ALT_L3_MST_USB0_raw_s ALT_L3_MST_USB0_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NANDREGS - ALT_L3_MST_NAND + * NANDREGS + * + * Registers associated with the NANDREGS master. This master is used to access the + * registers in the NAND flash controller. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_NAND. + */ +struct ALT_L3_MST_NAND_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_NAND. */ +typedef volatile struct ALT_L3_MST_NAND_s ALT_L3_MST_NAND_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_NAND. */ +struct ALT_L3_MST_NAND_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_NAND. */ +typedef volatile struct ALT_L3_MST_NAND_raw_s ALT_L3_MST_NAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : QSPIDATA - ALT_L3_MST_QSPIDATA + * QSPIDATA + * + * Registers associated with the QSPIDATA master. This master is used to access + * data in the QSPI flash controller. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_QSPIDATA. + */ +struct ALT_L3_MST_QSPIDATA_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_L3_MST_QSPIDATA. */ +typedef volatile struct ALT_L3_MST_QSPIDATA_s ALT_L3_MST_QSPIDATA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */ +struct ALT_L3_MST_QSPIDATA_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */ +typedef volatile struct ALT_L3_MST_QSPIDATA_raw_s ALT_L3_MST_QSPIDATA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : FPGAMGRDATA - ALT_L3_MST_FPGAMGRDATA + * FPGAMGRDATA + * + * Registers associated with the FPGAMGRDATA master. This master is used to send + * FPGA configuration image data to the FPGA Manager. + * + */ +/* + * Register : Write Tidemark - wr_tidemark + * + * Controls the release of the transaction in the write data FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x4 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Stalls the transaction in the write data FIFO until the number of occupied slots + * in the write data FIFO exceeds the level. Note that the transaction is released + * before this level is achieved if the network receives the WLAST beat or the + * write FIFO becomes full. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_MSB 3 +/* The width in bits of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_WIDTH 4 +/* The mask used to set the ALT_L3_WR_TIDEMARK_LEVEL register field value. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_WR_TIDEMARK_LEVEL register field value. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_RESET 0x4 +/* Extracts the ALT_L3_WR_TIDEMARK_LEVEL field value from a register. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_WR_TIDEMARK_LEVEL register field value suitable for setting the register. */ +#define ALT_L3_WR_TIDEMARK_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_WR_TIDEMARK. + */ +struct ALT_L3_WR_TIDEMARK_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_WR_TIDEMARK. */ +typedef volatile struct ALT_L3_WR_TIDEMARK_s ALT_L3_WR_TIDEMARK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_WR_TIDEMARK register from the beginning of the component. */ +#define ALT_L3_WR_TIDEMARK_OFST 0x40 +/* The address of the ALT_L3_WR_TIDEMARK register. */ +#define ALT_L3_WR_TIDEMARK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_TIDEMARK_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_FPGAMGRDATA. + */ +struct ALT_L3_MST_FPGAMGRDATA_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_FPGAMGRDATA. */ +typedef volatile struct ALT_L3_MST_FPGAMGRDATA_s ALT_L3_MST_FPGAMGRDATA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */ +struct ALT_L3_MST_FPGAMGRDATA_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */ +typedef volatile struct ALT_L3_MST_FPGAMGRDATA_raw_s ALT_L3_MST_FPGAMGRDATA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : HPS2FPGA - ALT_L3_MST_H2F + * HPS2FPGA + * + * Registers associated with the HPS2FPGA AXI Bridge master. This master is used to + * access the HPS2FPGA AXI Bridge slave. This slave is used to access slaves in the + * FPGA connected to the HPS2FPGA AXI Bridge. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_H2F. + */ +struct ALT_L3_MST_H2F_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_H2F. */ +typedef volatile struct ALT_L3_MST_H2F_s ALT_L3_MST_H2F_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_H2F. */ +struct ALT_L3_MST_H2F_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_H2F. */ +typedef volatile struct ALT_L3_MST_H2F_raw_s ALT_L3_MST_H2F_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ACP - ALT_L3_MST_ACP + * ACP + * + * Registers associated with the ACP master. This master is used to access the MPU + * ACP slave via the ACP ID Mapper. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_ACP. + */ +struct ALT_L3_MST_ACP_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_ACP. */ +typedef volatile struct ALT_L3_MST_ACP_s ALT_L3_MST_ACP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_ACP. */ +struct ALT_L3_MST_ACP_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_ACP. */ +typedef volatile struct ALT_L3_MST_ACP_raw_s ALT_L3_MST_ACP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Boot ROM - ALT_L3_MST_ROM + * Boot ROM + * + * Registers associated with the Boot ROM master. This master is used to access the + * contents of the Boot ROM. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_ROM. + */ +struct ALT_L3_MST_ROM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_ROM. */ +typedef volatile struct ALT_L3_MST_ROM_s ALT_L3_MST_ROM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_ROM. */ +struct ALT_L3_MST_ROM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_ROM. */ +typedef volatile struct ALT_L3_MST_ROM_raw_s ALT_L3_MST_ROM_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : On-chip RAM - ALT_L3_MST_OCRAM + * On-chip RAM + * + * Registers associated with the On-chip RAM master. This master is used to access + * the contents of the On-chip RAM. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MST_OCRAM. + */ +struct ALT_L3_MST_OCRAM_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_MST_OCRAM. */ +typedef volatile struct ALT_L3_MST_OCRAM_s ALT_L3_MST_OCRAM_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */ +struct ALT_L3_MST_OCRAM_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */ +typedef volatile struct ALT_L3_MST_OCRAM_raw_s ALT_L3_MST_OCRAM_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_MSTGRP. + */ +struct ALT_L3_MSTGRP_s +{ + volatile ALT_L3_MST_L4MAIN_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */ + volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SP_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */ + volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4MP_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */ + volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4OSC1_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */ + volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SPIM_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */ + volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_STM_t mastergrp_stm; /* ALT_L3_MST_STM */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_LWH2F_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */ + volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB1_t mastergrp_usb1; /* ALT_L3_MST_USB1 */ + volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NANDDATA_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */ + volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB0_t mastergrp_usb0; /* ALT_L3_MST_USB0 */ + volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NAND_t mastergrp_nandregs; /* ALT_L3_MST_NAND */ + volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_QSPIDATA_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */ + volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_FPGAMGRDATA_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */ + volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_H2F_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */ + volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ACP_t mastergrp_acp; /* ALT_L3_MST_ACP */ + volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ROM_t mastergrp_rom; /* ALT_L3_MST_ROM */ + volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_OCRAM_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */ +}; + +/* The typedef declaration for register group ALT_L3_MSTGRP. */ +typedef volatile struct ALT_L3_MSTGRP_s ALT_L3_MSTGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_MSTGRP. */ +struct ALT_L3_MSTGRP_raw_s +{ + volatile ALT_L3_MST_L4MAIN_raw_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */ + volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SP_raw_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */ + volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4MP_raw_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */ + volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4OSC1_raw_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */ + volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_L4SPIM_raw_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */ + volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */ + volatile ALT_L3_MST_STM_raw_t mastergrp_stm; /* ALT_L3_MST_STM */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_LWH2F_raw_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */ + volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB1_raw_t mastergrp_usb1; /* ALT_L3_MST_USB1 */ + volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NANDDATA_raw_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */ + volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */ + volatile ALT_L3_MST_USB0_raw_t mastergrp_usb0; /* ALT_L3_MST_USB0 */ + volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_NAND_raw_t mastergrp_nandregs; /* ALT_L3_MST_NAND */ + volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_QSPIDATA_raw_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */ + volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */ + volatile ALT_L3_MST_FPGAMGRDATA_raw_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */ + volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_H2F_raw_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */ + volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ACP_raw_t mastergrp_acp; /* ALT_L3_MST_ACP */ + volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_ROM_raw_t mastergrp_rom; /* ALT_L3_MST_ROM */ + volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_MST_OCRAM_raw_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_MSTGRP. */ +typedef volatile struct ALT_L3_MSTGRP_raw_s ALT_L3_MSTGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Slave Register Group - ALT_L3_SLVGRP + * Slave Register Group + * + * Registers associated with slave interfaces. + * + */ +/* + * Register Group : DAP - ALT_L3_SLV_DAP + * DAP + * + * Registers associated with the DAP slave interface. This slave is used by the DAP + * to access slaves attached to the L3/L4 Interconnect. + * + */ +/* + * Register : Functionality Modification 2 Register - fn_mod2 + * + * Controls bypass merge of upsizing/downsizing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Bypass Merge + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bypass Merge - bypass_merge + * + * Controls bypass merge of upsizing/downsizing. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------- + * ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER | 0x0 | The network can alter transactions. + * ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER | 0x1 | The network does not alter any transactions that + * : | | could pass through the upsizer legally without + * : | | alteration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE + * + * The network can alter transactions. + */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE + * + * The network does not alter any transactions that could pass through the upsizer + * legally without alteration. + */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD2_BYPASS_MERGE field value from a register. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD2_BYPASS_MERGE register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD2. + */ +struct ALT_L3_FN_MOD2_s +{ + uint32_t bypass_merge : 1; /* Bypass Merge */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD2. */ +typedef volatile struct ALT_L3_FN_MOD2_s ALT_L3_FN_MOD2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD2 register from the beginning of the component. */ +#define ALT_L3_FN_MOD2_OFST 0x24 +/* The address of the ALT_L3_FN_MOD2 register. */ +#define ALT_L3_FN_MOD2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD2_OFST)) + +/* + * Register : Functionality Modification AHB Register - fn_mod_ahb + * + * Controls how AHB-lite burst transactions are converted to AXI tranactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x0 | Read Increment Override + * [1] | RW | 0x0 | Write Increment Override + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read Increment Override - rd_incr_override + * + * Controls how AHB-lite read burst transactions are converted to AXI tranactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:---------------------------------------------- + * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite read + * : | | bursts to AXI transactions in accordance with + * : | | the default behavior as specified in the ARM + * : | | NIC-301 documentation. + * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite read + * : | | bursts to AXI single transactions. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite read bursts to AXI transactions in + * accordance with the default behavior as specified in the ARM NIC-301 + * documentation. + */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite read bursts to AXI single transactions. + */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_MSB 0 +/* The width in bits of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE field value from a register. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Write Increment Override - wr_incr_override + * + * Controls how AHB-lite write burst transactions are converted to AXI tranactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:---------------------------------------------- + * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite write + * : | | bursts to AXI transactions in accordance with + * : | | the default behavior as specified in the ARM + * : | | NIC-301 documentation. + * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite write + * : | | bursts to AXI single transactions. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite write bursts to AXI transactions in + * accordance with the default behavior as specified in the ARM NIC-301 + * documentation. + */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT 0x0 +/* + * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE + * + * The L3 Interconnect converts AHB-lite write bursts to AXI single transactions. + */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_MSB 1 +/* The width in bits of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_WIDTH 1 +/* The mask used to set the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_RESET 0x0 +/* Extracts the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE field value from a register. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value suitable for setting the register. */ +#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_FN_MOD_AHB. + */ +struct ALT_L3_FN_MOD_AHB_s +{ + uint32_t rd_incr_override : 1; /* Read Increment Override */ + uint32_t wr_incr_override : 1; /* Write Increment Override */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_FN_MOD_AHB. */ +typedef volatile struct ALT_L3_FN_MOD_AHB_s ALT_L3_FN_MOD_AHB_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_FN_MOD_AHB register from the beginning of the component. */ +#define ALT_L3_FN_MOD_AHB_OFST 0x28 +/* The address of the ALT_L3_FN_MOD_AHB register. */ +#define ALT_L3_FN_MOD_AHB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_AHB_OFST)) + +/* + * Register : Read Channel QoS Value - read_qos + * + * QoS (Quality of Service) value for the read channel. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x0 | Priority + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Priority - pri + * + * QoS (Quality of Service) value for the read channel. A higher value has a higher + * priority. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_MSB 3 +/* The width in bits of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_WIDTH 4 +/* The mask used to set the ALT_L3_RD_QOS_PRI register field value. */ +#define ALT_L3_RD_QOS_PRI_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_RD_QOS_PRI register field value. */ +#define ALT_L3_RD_QOS_PRI_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_RD_QOS_PRI register field. */ +#define ALT_L3_RD_QOS_PRI_RESET 0x0 +/* Extracts the ALT_L3_RD_QOS_PRI field value from a register. */ +#define ALT_L3_RD_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_RD_QOS_PRI register field value suitable for setting the register. */ +#define ALT_L3_RD_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_RD_QOS. + */ +struct ALT_L3_RD_QOS_s +{ + uint32_t pri : 4; /* Priority */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_RD_QOS. */ +typedef volatile struct ALT_L3_RD_QOS_s ALT_L3_RD_QOS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_RD_QOS register from the beginning of the component. */ +#define ALT_L3_RD_QOS_OFST 0x100 +/* The address of the ALT_L3_RD_QOS register. */ +#define ALT_L3_RD_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_RD_QOS_OFST)) + +/* + * Register : Write Channel QoS Value - write_qos + * + * QoS (Quality of Service) value for the write channel. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x0 | Priority + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Priority - pri + * + * QoS (Quality of Service) value for the write channel. A higher value has a + * higher priority. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_MSB 3 +/* The width in bits of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_WIDTH 4 +/* The mask used to set the ALT_L3_WR_QOS_PRI register field value. */ +#define ALT_L3_WR_QOS_PRI_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L3_WR_QOS_PRI register field value. */ +#define ALT_L3_WR_QOS_PRI_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L3_WR_QOS_PRI register field. */ +#define ALT_L3_WR_QOS_PRI_RESET 0x0 +/* Extracts the ALT_L3_WR_QOS_PRI field value from a register. */ +#define ALT_L3_WR_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L3_WR_QOS_PRI register field value suitable for setting the register. */ +#define ALT_L3_WR_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L3_WR_QOS. + */ +struct ALT_L3_WR_QOS_s +{ + uint32_t pri : 4; /* Priority */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L3_WR_QOS. */ +typedef volatile struct ALT_L3_WR_QOS_s ALT_L3_WR_QOS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L3_WR_QOS register from the beginning of the component. */ +#define ALT_L3_WR_QOS_OFST 0x104 +/* The address of the ALT_L3_WR_QOS register. */ +#define ALT_L3_WR_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_QOS_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_DAP. + */ +struct ALT_L3_SLV_DAP_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD2_t fn_mod2; /* ALT_L3_FN_MOD2 */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_DAP. */ +typedef volatile struct ALT_L3_SLV_DAP_s ALT_L3_SLV_DAP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_DAP. */ +struct ALT_L3_SLV_DAP_raw_s +{ + volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ + volatile uint32_t fn_mod2; /* ALT_L3_FN_MOD2 */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DAP. */ +typedef volatile struct ALT_L3_SLV_DAP_raw_s ALT_L3_SLV_DAP_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : MPU - ALT_L3_SLV_MPU + * MPU + * + * Registers associated with the MPU slave interface. This slave is used by the MPU + * to access slaves attached to the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_MPU. + */ +struct ALT_L3_SLV_MPU_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_MPU. */ +typedef volatile struct ALT_L3_SLV_MPU_s ALT_L3_SLV_MPU_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_MPU. */ +struct ALT_L3_SLV_MPU_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_MPU. */ +typedef volatile struct ALT_L3_SLV_MPU_raw_s ALT_L3_SLV_MPU_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : SDMMC - ALT_L3_SLV_SDMMC + * SDMMC + * + * Registers associated with the SDMMC slave interface. This slave is used by the + * DMA controller built into the SDMMC to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_SDMMC. + */ +struct ALT_L3_SLV_SDMMC_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_SDMMC. */ +typedef volatile struct ALT_L3_SLV_SDMMC_s ALT_L3_SLV_SDMMC_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */ +struct ALT_L3_SLV_SDMMC_raw_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */ +typedef volatile struct ALT_L3_SLV_SDMMC_raw_s ALT_L3_SLV_SDMMC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : DMA - ALT_L3_SLV_DMA + * DMA + * + * Registers associated with the DMA Controller slave interface. This slave is used + * by the DMA Controller to access slaves attached to the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_DMA. + */ +struct ALT_L3_SLV_DMA_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_DMA. */ +typedef volatile struct ALT_L3_SLV_DMA_s ALT_L3_SLV_DMA_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_DMA. */ +struct ALT_L3_SLV_DMA_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DMA. */ +typedef volatile struct ALT_L3_SLV_DMA_raw_s ALT_L3_SLV_DMA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : FPGA2HPS - ALT_L3_SLV_F2H + * FPGA2HPS + * + * Registers associated with the FPGA2HPS AXI Bridge slave interface. This slave is + * used by the FPGA2HPS AXI Bridge to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_F2H. + */ +struct ALT_L3_SLV_F2H_s +{ + volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */ + volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_F2H. */ +typedef volatile struct ALT_L3_SLV_F2H_s ALT_L3_SLV_F2H_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_F2H. */ +struct ALT_L3_SLV_F2H_raw_s +{ + volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_F2H. */ +typedef volatile struct ALT_L3_SLV_F2H_raw_s ALT_L3_SLV_F2H_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ETR - ALT_L3_SLV_ETR + * ETR + * + * Registers associated with the ETR (TMC) slave interface. This slave is used by + * the ETR to access slaves attached to the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_ETR. + */ +struct ALT_L3_SLV_ETR_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_ETR. */ +typedef volatile struct ALT_L3_SLV_ETR_s ALT_L3_SLV_ETR_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_ETR. */ +struct ALT_L3_SLV_ETR_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_ETR. */ +typedef volatile struct ALT_L3_SLV_ETR_raw_s ALT_L3_SLV_ETR_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : EMAC0 - ALT_L3_SLV_EMAC0 + * EMAC0 + * + * Registers associated with the EMAC0 slave interface. This slave is used by the + * DMA controller built into the EMAC0 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_EMAC0. + */ +struct ALT_L3_SLV_EMAC0_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_EMAC0. */ +typedef volatile struct ALT_L3_SLV_EMAC0_s ALT_L3_SLV_EMAC0_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */ +struct ALT_L3_SLV_EMAC0_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */ +typedef volatile struct ALT_L3_SLV_EMAC0_raw_s ALT_L3_SLV_EMAC0_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : EMAC1 - ALT_L3_SLV_EMAC1 + * EMAC1 + * + * Registers associated with the EMAC1 slave interface. This slave is used by the + * DMA controller built into the EMAC1 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_EMAC1. + */ +struct ALT_L3_SLV_EMAC1_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_EMAC1. */ +typedef volatile struct ALT_L3_SLV_EMAC1_s ALT_L3_SLV_EMAC1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */ +struct ALT_L3_SLV_EMAC1_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */ +typedef volatile struct ALT_L3_SLV_EMAC1_raw_s ALT_L3_SLV_EMAC1_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB0 - ALT_L3_SLV_USB0 + * USB0 + * + * Registers associated with the USB0 slave interface. This slave is used by the + * DMA controller built into the USB0 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_USB0. + */ +struct ALT_L3_SLV_USB0_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_USB0. */ +typedef volatile struct ALT_L3_SLV_USB0_s ALT_L3_SLV_USB0_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB0. */ +struct ALT_L3_SLV_USB0_raw_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB0. */ +typedef volatile struct ALT_L3_SLV_USB0_raw_s ALT_L3_SLV_USB0_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NAND - ALT_L3_SLV_NAND + * NAND + * + * Registers associated with the NAND slave interface. This slave is used by the + * DMA controller built into the NAND flash controller to access slaves attached to + * the L3/L4 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_NAND. + */ +struct ALT_L3_SLV_NAND_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_NAND. */ +typedef volatile struct ALT_L3_SLV_NAND_s ALT_L3_SLV_NAND_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_NAND. */ +struct ALT_L3_SLV_NAND_raw_s +{ + volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_NAND. */ +typedef volatile struct ALT_L3_SLV_NAND_raw_s ALT_L3_SLV_NAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB1 - ALT_L3_SLV_USB1 + * USB1 + * + * Registers associated with the USB1 slave interface. This slave is used by the + * DMA controller built into the USB1 to access slaves attached to the L3/L4 + * Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLV_USB1. + */ +struct ALT_L3_SLV_USB1_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ + volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ + volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_L3_SLV_USB1. */ +typedef volatile struct ALT_L3_SLV_USB1_s ALT_L3_SLV_USB1_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB1. */ +struct ALT_L3_SLV_USB1_raw_s +{ + volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ + volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ + volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ + volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ + volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB1. */ +typedef volatile struct ALT_L3_SLV_USB1_raw_s ALT_L3_SLV_USB1_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3_SLVGRP. + */ +struct ALT_L3_SLVGRP_s +{ + volatile ALT_L3_SLV_DAP_t slavegrp_dap; /* ALT_L3_SLV_DAP */ + volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_MPU_t slavegrp_mpu; /* ALT_L3_SLV_MPU */ + volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_SDMMC_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */ + volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_DMA_t slavegrp_dma; /* ALT_L3_SLV_DMA */ + volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_F2H_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */ + volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_ETR_t slavegrp_etr; /* ALT_L3_SLV_ETR */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC0_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */ + volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC1_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */ + volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB0_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */ + volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_NAND_t slavegrp_nand; /* ALT_L3_SLV_NAND */ + volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB1_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */ +}; + +/* The typedef declaration for register group ALT_L3_SLVGRP. */ +typedef volatile struct ALT_L3_SLVGRP_s ALT_L3_SLVGRP_t; +/* The struct declaration for the raw register contents of register group ALT_L3_SLVGRP. */ +struct ALT_L3_SLVGRP_raw_s +{ + volatile ALT_L3_SLV_DAP_raw_t slavegrp_dap; /* ALT_L3_SLV_DAP */ + volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_MPU_raw_t slavegrp_mpu; /* ALT_L3_SLV_MPU */ + volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_SDMMC_raw_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */ + volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_DMA_raw_t slavegrp_dma; /* ALT_L3_SLV_DMA */ + volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_F2H_raw_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */ + volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_ETR_raw_t slavegrp_etr; /* ALT_L3_SLV_ETR */ + volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC0_raw_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */ + volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_EMAC1_raw_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */ + volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB0_raw_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */ + volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_NAND_raw_t slavegrp_nand; /* ALT_L3_SLV_NAND */ + volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */ + volatile ALT_L3_SLV_USB1_raw_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3_SLVGRP. */ +typedef volatile struct ALT_L3_SLVGRP_raw_s ALT_L3_SLVGRP_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L3. + */ +struct ALT_L3_s +{ + volatile ALT_L3_REMAP_t remap; /* ALT_L3_REMAP */ + volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */ + volatile ALT_L3_SECGRP_t secgrp; /* ALT_L3_SECGRP */ + volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */ + volatile ALT_L3_IDGRP_t idgrp; /* ALT_L3_IDGRP */ + volatile ALT_L3_MSTGRP_t mastergrp; /* ALT_L3_MSTGRP */ + volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */ + volatile ALT_L3_SLVGRP_t slavegrp; /* ALT_L3_SLVGRP */ + volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_L3. */ +typedef volatile struct ALT_L3_s ALT_L3_t; +/* The struct declaration for the raw register contents of register group ALT_L3. */ +struct ALT_L3_raw_s +{ + volatile uint32_t remap; /* ALT_L3_REMAP */ + volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */ + volatile ALT_L3_SECGRP_raw_t secgrp; /* ALT_L3_SECGRP */ + volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */ + volatile ALT_L3_IDGRP_raw_t idgrp; /* ALT_L3_IDGRP */ + volatile ALT_L3_MSTGRP_raw_t mastergrp; /* ALT_L3_MSTGRP */ + volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */ + volatile ALT_L3_SLVGRP_raw_t slavegrp; /* ALT_L3_SLVGRP */ + volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L3. */ +typedef volatile struct ALT_L3_raw_s ALT_L3_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_L3_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_l4wd.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_l4wd.h new file mode 100644 index 000000000..e2aa20cfd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_l4wd.h @@ -0,0 +1,1801 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_L4WD */ + +#ifndef __ALTERA_ALT_L4WD_H__ +#define __ALTERA_ALT_L4WD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : L4 Watchdog Module - ALT_L4WD + * L4 Watchdog Module + * + * Registers in the L4 Watchdog module + * + */ +/* + * Register : Control Register - wdt_cr + * + * Contains fields that control operating functions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [0] | RW | 0x0 | Enable + * [1] | RW | 0x1 | Response Mode + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable - wdt_en + * + * This bit is used to enable and disable the watchdog. When disabled, the counter + * does not decrement. Thus, no interrupts or warm reset requests are generated. + * Once this bit has been enabled, it can only be cleared only by resetting the + * watchdog. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------ + * ALT_L4WD_CR_WDT_EN_E_DISD | 0x0 | Watchdog disabled + * ALT_L4WD_CR_WDT_EN_E_END | 0x1 | Watchdog enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_CR_WDT_EN + * + * Watchdog disabled + */ +#define ALT_L4WD_CR_WDT_EN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_L4WD_CR_WDT_EN + * + * Watchdog enabled + */ +#define ALT_L4WD_CR_WDT_EN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_CR_WDT_EN register field. */ +#define ALT_L4WD_CR_WDT_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_CR_WDT_EN register field. */ +#define ALT_L4WD_CR_WDT_EN_MSB 0 +/* The width in bits of the ALT_L4WD_CR_WDT_EN register field. */ +#define ALT_L4WD_CR_WDT_EN_WIDTH 1 +/* The mask used to set the ALT_L4WD_CR_WDT_EN register field value. */ +#define ALT_L4WD_CR_WDT_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L4WD_CR_WDT_EN register field value. */ +#define ALT_L4WD_CR_WDT_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L4WD_CR_WDT_EN register field. */ +#define ALT_L4WD_CR_WDT_EN_RESET 0x0 +/* Extracts the ALT_L4WD_CR_WDT_EN field value from a register. */ +#define ALT_L4WD_CR_WDT_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L4WD_CR_WDT_EN register field value suitable for setting the register. */ +#define ALT_L4WD_CR_WDT_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Response Mode - rmod + * + * Selects the output response generated to a timeout. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------------------------------------- + * ALT_L4WD_CR_RMOD_E_RST | 0x0 | Generate a warm reset request + * ALT_L4WD_CR_RMOD_E_IRQRST | 0x1 | First generate an interrupt, and if it is not + * : | | cleared by the time a second timeout occurs, + * : | | then generate a warm reset request. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_CR_RMOD + * + * Generate a warm reset request + */ +#define ALT_L4WD_CR_RMOD_E_RST 0x0 +/* + * Enumerated value for register field ALT_L4WD_CR_RMOD + * + * First generate an interrupt, and if it is not cleared by the time a second + * timeout occurs, then generate a warm reset request. + */ +#define ALT_L4WD_CR_RMOD_E_IRQRST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_CR_RMOD register field. */ +#define ALT_L4WD_CR_RMOD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_CR_RMOD register field. */ +#define ALT_L4WD_CR_RMOD_MSB 1 +/* The width in bits of the ALT_L4WD_CR_RMOD register field. */ +#define ALT_L4WD_CR_RMOD_WIDTH 1 +/* The mask used to set the ALT_L4WD_CR_RMOD register field value. */ +#define ALT_L4WD_CR_RMOD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L4WD_CR_RMOD register field value. */ +#define ALT_L4WD_CR_RMOD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L4WD_CR_RMOD register field. */ +#define ALT_L4WD_CR_RMOD_RESET 0x1 +/* Extracts the ALT_L4WD_CR_RMOD field value from a register. */ +#define ALT_L4WD_CR_RMOD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L4WD_CR_RMOD register field value suitable for setting the register. */ +#define ALT_L4WD_CR_RMOD_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_CR. + */ +struct ALT_L4WD_CR_s +{ + uint32_t wdt_en : 1; /* Enable */ + uint32_t rmod : 1; /* Response Mode */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L4WD_CR. */ +typedef volatile struct ALT_L4WD_CR_s ALT_L4WD_CR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_CR register from the beginning of the component. */ +#define ALT_L4WD_CR_OFST 0x0 +/* The address of the ALT_L4WD_CR register. */ +#define ALT_L4WD_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CR_OFST)) + +/* + * Register : Timeout Range Register - wdt_torr + * + * Contains fields that determine the watchdog timeout. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [3:0] | RW | 0xf | Timeout Period + * [7:4] | RW | 0xf | Timeout Period for Initialization + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timeout Period - top + * + * This field is used to select the timeout period from which the watchdog counter + * restarts. A change of the timeout period takes effect only after the next + * counter restart (kick). The timeout period (in clocks) is: + * + * t = 2**(16 + top) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------------ + * ALT_L4WD_TORR_TOP_E_TMO64K | 0x0 | Timeout = 65536 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO128K | 0x1 | Timeout = 131072 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO256K | 0x2 | Timeout = 262144 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO512K | 0x3 | Timeout = 524288 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO1M | 0x4 | Timeout = 1048576 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO2M | 0x5 | Timeout = 2097152 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO4M | 0x6 | Timeout = 4194304 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO8M | 0x7 | Timeout = 8388608 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO16M | 0x8 | Timeout = 16777216 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO32M | 0x9 | Timeout = 33554432 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO64M | 0xa | Timeout = 67108864 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO128M | 0xb | Timeout = 134217728 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO256M | 0xc | Timeout = 268435456 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO512M | 0xd | Timeout = 536870912 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO1G | 0xe | Timeout = 1073741824 osc1_clk + * ALT_L4WD_TORR_TOP_E_TMO2G | 0xf | Timeout = 2147483648 osc1_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 65536 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO64K 0x0 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 131072 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO128K 0x1 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 262144 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO256K 0x2 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 524288 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO512K 0x3 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 1048576 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO1M 0x4 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 2097152 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO2M 0x5 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 4194304 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO4M 0x6 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 8388608 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO8M 0x7 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 16777216 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO16M 0x8 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 33554432 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO32M 0x9 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 67108864 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO64M 0xa +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 134217728 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO128M 0xb +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 268435456 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO256M 0xc +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 536870912 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO512M 0xd +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 1073741824 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO1G 0xe +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP + * + * Timeout = 2147483648 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_E_TMO2G 0xf + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_TORR_TOP register field. */ +#define ALT_L4WD_TORR_TOP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_TORR_TOP register field. */ +#define ALT_L4WD_TORR_TOP_MSB 3 +/* The width in bits of the ALT_L4WD_TORR_TOP register field. */ +#define ALT_L4WD_TORR_TOP_WIDTH 4 +/* The mask used to set the ALT_L4WD_TORR_TOP register field value. */ +#define ALT_L4WD_TORR_TOP_SET_MSK 0x0000000f +/* The mask used to clear the ALT_L4WD_TORR_TOP register field value. */ +#define ALT_L4WD_TORR_TOP_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_L4WD_TORR_TOP register field. */ +#define ALT_L4WD_TORR_TOP_RESET 0xf +/* Extracts the ALT_L4WD_TORR_TOP field value from a register. */ +#define ALT_L4WD_TORR_TOP_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_L4WD_TORR_TOP register field value suitable for setting the register. */ +#define ALT_L4WD_TORR_TOP_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Timeout Period for Initialization - top_init + * + * Used to select the timeout period that the watchdog counter restarts from for + * the first counter restart (kick). This register should be written after reset + * and before the watchdog is enabled. A change of the TOP_INIT is seen only once + * the watchdog has been enabled, and any change after the first kick is not seen + * as subsequent kicks use the period specified by the TOP bits. The timeout period + * (in clocks) is: + * + * t = 2**(16 + top_init) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------ + * ALT_L4WD_TORR_TOP_INIT_E_TMO64K | 0x0 | Timeout = 65536 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO128K | 0x1 | Timeout = 131072 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO256K | 0x2 | Timeout = 262144 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO512K | 0x3 | Timeout = 524288 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO1M | 0x4 | Timeout = 1048576 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO2M | 0x5 | Timeout = 2097152 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO4M | 0x6 | Timeout = 4194304 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO8M | 0x7 | Timeout = 8388608 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO16M | 0x8 | Timeout = 16777216 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO32M | 0x9 | Timeout = 33554432 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO64M | 0xa | Timeout = 67108864 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO128M | 0xb | Timeout = 134217728 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO256M | 0xc | Timeout = 268435456 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO512M | 0xd | Timeout = 536870912 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO1G | 0xe | Timeout = 1073741824 osc1_clk + * ALT_L4WD_TORR_TOP_INIT_E_TMO2G | 0xf | Timeout = 2147483648 osc1_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 65536 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO64K 0x0 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 131072 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO128K 0x1 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 262144 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO256K 0x2 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 524288 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO512K 0x3 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 1048576 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO1M 0x4 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 2097152 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO2M 0x5 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 4194304 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO4M 0x6 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 8388608 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO8M 0x7 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 16777216 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO16M 0x8 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 33554432 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO32M 0x9 +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 67108864 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO64M 0xa +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 134217728 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO128M 0xb +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 268435456 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO256M 0xc +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 536870912 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO512M 0xd +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 1073741824 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO1G 0xe +/* + * Enumerated value for register field ALT_L4WD_TORR_TOP_INIT + * + * Timeout = 2147483648 osc1_clk + */ +#define ALT_L4WD_TORR_TOP_INIT_E_TMO2G 0xf + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_TORR_TOP_INIT register field. */ +#define ALT_L4WD_TORR_TOP_INIT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_TORR_TOP_INIT register field. */ +#define ALT_L4WD_TORR_TOP_INIT_MSB 7 +/* The width in bits of the ALT_L4WD_TORR_TOP_INIT register field. */ +#define ALT_L4WD_TORR_TOP_INIT_WIDTH 4 +/* The mask used to set the ALT_L4WD_TORR_TOP_INIT register field value. */ +#define ALT_L4WD_TORR_TOP_INIT_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_L4WD_TORR_TOP_INIT register field value. */ +#define ALT_L4WD_TORR_TOP_INIT_CLR_MSK 0xffffff0f +/* The reset value of the ALT_L4WD_TORR_TOP_INIT register field. */ +#define ALT_L4WD_TORR_TOP_INIT_RESET 0xf +/* Extracts the ALT_L4WD_TORR_TOP_INIT field value from a register. */ +#define ALT_L4WD_TORR_TOP_INIT_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_L4WD_TORR_TOP_INIT register field value suitable for setting the register. */ +#define ALT_L4WD_TORR_TOP_INIT_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_TORR. + */ +struct ALT_L4WD_TORR_s +{ + uint32_t top : 4; /* Timeout Period */ + uint32_t top_init : 4; /* Timeout Period for Initialization */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L4WD_TORR. */ +typedef volatile struct ALT_L4WD_TORR_s ALT_L4WD_TORR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_TORR register from the beginning of the component. */ +#define ALT_L4WD_TORR_OFST 0x4 +/* The address of the ALT_L4WD_TORR register. */ +#define ALT_L4WD_TORR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_TORR_OFST)) + +/* + * Register : Current Counter Value Register - wdt_ccvr + * + * See Field Description + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------------- + * [31:0] | R | 0x7fffffff | Current Counter Value + * + */ +/* + * Field : Current Counter Value - wdt_ccvr + * + * This register provides the current value of the internal counter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L4WD_CCVR_WDT_CCVR register field. */ +#define ALT_L4WD_CCVR_WDT_CCVR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_CCVR_WDT_CCVR register field. */ +#define ALT_L4WD_CCVR_WDT_CCVR_MSB 31 +/* The width in bits of the ALT_L4WD_CCVR_WDT_CCVR register field. */ +#define ALT_L4WD_CCVR_WDT_CCVR_WIDTH 32 +/* The mask used to set the ALT_L4WD_CCVR_WDT_CCVR register field value. */ +#define ALT_L4WD_CCVR_WDT_CCVR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_L4WD_CCVR_WDT_CCVR register field value. */ +#define ALT_L4WD_CCVR_WDT_CCVR_CLR_MSK 0x00000000 +/* The reset value of the ALT_L4WD_CCVR_WDT_CCVR register field. */ +#define ALT_L4WD_CCVR_WDT_CCVR_RESET 0x7fffffff +/* Extracts the ALT_L4WD_CCVR_WDT_CCVR field value from a register. */ +#define ALT_L4WD_CCVR_WDT_CCVR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_L4WD_CCVR_WDT_CCVR register field value suitable for setting the register. */ +#define ALT_L4WD_CCVR_WDT_CCVR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_CCVR. + */ +struct ALT_L4WD_CCVR_s +{ + const uint32_t wdt_ccvr : 32; /* Current Counter Value */ +}; + +/* The typedef declaration for register ALT_L4WD_CCVR. */ +typedef volatile struct ALT_L4WD_CCVR_s ALT_L4WD_CCVR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_CCVR register from the beginning of the component. */ +#define ALT_L4WD_CCVR_OFST 0x8 +/* The address of the ALT_L4WD_CCVR register. */ +#define ALT_L4WD_CCVR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CCVR_OFST)) + +/* + * Register : Counter Restart Register - wdt_crr + * + * Restarts the watchdog. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [7:0] | W | 0x0 | Counter Restart Register + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Counter Restart Register - wdt_crr + * + * This register is used to restart the watchdog counter. As a safety feature to + * prevent accidental restarts, the kick value of 0x76 must be written. A restart + * also clears the watchdog interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------------------------- + * ALT_L4WD_CRR_WDT_CRR_E_KICK | 0x76 | Value to write to restart watchdog timer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_CRR_WDT_CRR + * + * Value to write to restart watchdog timer + */ +#define ALT_L4WD_CRR_WDT_CRR_E_KICK 0x76 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_CRR_WDT_CRR register field. */ +#define ALT_L4WD_CRR_WDT_CRR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_CRR_WDT_CRR register field. */ +#define ALT_L4WD_CRR_WDT_CRR_MSB 7 +/* The width in bits of the ALT_L4WD_CRR_WDT_CRR register field. */ +#define ALT_L4WD_CRR_WDT_CRR_WIDTH 8 +/* The mask used to set the ALT_L4WD_CRR_WDT_CRR register field value. */ +#define ALT_L4WD_CRR_WDT_CRR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_L4WD_CRR_WDT_CRR register field value. */ +#define ALT_L4WD_CRR_WDT_CRR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_L4WD_CRR_WDT_CRR register field. */ +#define ALT_L4WD_CRR_WDT_CRR_RESET 0x0 +/* Extracts the ALT_L4WD_CRR_WDT_CRR field value from a register. */ +#define ALT_L4WD_CRR_WDT_CRR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_L4WD_CRR_WDT_CRR register field value suitable for setting the register. */ +#define ALT_L4WD_CRR_WDT_CRR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_CRR. + */ +struct ALT_L4WD_CRR_s +{ + uint32_t wdt_crr : 8; /* Counter Restart Register */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L4WD_CRR. */ +typedef volatile struct ALT_L4WD_CRR_s ALT_L4WD_CRR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_CRR register from the beginning of the component. */ +#define ALT_L4WD_CRR_OFST 0xc +/* The address of the ALT_L4WD_CRR register. */ +#define ALT_L4WD_CRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CRR_OFST)) + +/* + * Register : Interrupt Status Register. - wdt_stat + * + * Provides interrupt status + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | R | 0x0 | Interrupt Status + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Status - wdt_stat + * + * Provides the interrupt status of the watchdog. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------- + * ALT_L4WD_STAT_WDT_STAT_E_ACT | 0x1 | Interrupt is active + * ALT_L4WD_STAT_WDT_STAT_E_INACT | 0x0 | Interrupt is inactive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_STAT_WDT_STAT + * + * Interrupt is active + */ +#define ALT_L4WD_STAT_WDT_STAT_E_ACT 0x1 +/* + * Enumerated value for register field ALT_L4WD_STAT_WDT_STAT + * + * Interrupt is inactive + */ +#define ALT_L4WD_STAT_WDT_STAT_E_INACT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_STAT_WDT_STAT register field. */ +#define ALT_L4WD_STAT_WDT_STAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_STAT_WDT_STAT register field. */ +#define ALT_L4WD_STAT_WDT_STAT_MSB 0 +/* The width in bits of the ALT_L4WD_STAT_WDT_STAT register field. */ +#define ALT_L4WD_STAT_WDT_STAT_WIDTH 1 +/* The mask used to set the ALT_L4WD_STAT_WDT_STAT register field value. */ +#define ALT_L4WD_STAT_WDT_STAT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L4WD_STAT_WDT_STAT register field value. */ +#define ALT_L4WD_STAT_WDT_STAT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L4WD_STAT_WDT_STAT register field. */ +#define ALT_L4WD_STAT_WDT_STAT_RESET 0x0 +/* Extracts the ALT_L4WD_STAT_WDT_STAT field value from a register. */ +#define ALT_L4WD_STAT_WDT_STAT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L4WD_STAT_WDT_STAT register field value suitable for setting the register. */ +#define ALT_L4WD_STAT_WDT_STAT_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_STAT. + */ +struct ALT_L4WD_STAT_s +{ + const uint32_t wdt_stat : 1; /* Interrupt Status */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L4WD_STAT. */ +typedef volatile struct ALT_L4WD_STAT_s ALT_L4WD_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_STAT register from the beginning of the component. */ +#define ALT_L4WD_STAT_OFST 0x10 +/* The address of the ALT_L4WD_STAT register. */ +#define ALT_L4WD_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_STAT_OFST)) + +/* + * Register : Interrupt Clear Register - wdt_eoi + * + * Clears the watchdog interrupt when read. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | R | 0x0 | Interrupt Clear + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Clear - wdt_eoi + * + * Clears the watchdog interrupt. This can be used to clear the interrupt without + * restarting the watchdog counter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L4WD_EOI_WDT_EOI register field. */ +#define ALT_L4WD_EOI_WDT_EOI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_EOI_WDT_EOI register field. */ +#define ALT_L4WD_EOI_WDT_EOI_MSB 0 +/* The width in bits of the ALT_L4WD_EOI_WDT_EOI register field. */ +#define ALT_L4WD_EOI_WDT_EOI_WIDTH 1 +/* The mask used to set the ALT_L4WD_EOI_WDT_EOI register field value. */ +#define ALT_L4WD_EOI_WDT_EOI_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L4WD_EOI_WDT_EOI register field value. */ +#define ALT_L4WD_EOI_WDT_EOI_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L4WD_EOI_WDT_EOI register field. */ +#define ALT_L4WD_EOI_WDT_EOI_RESET 0x0 +/* Extracts the ALT_L4WD_EOI_WDT_EOI field value from a register. */ +#define ALT_L4WD_EOI_WDT_EOI_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L4WD_EOI_WDT_EOI register field value suitable for setting the register. */ +#define ALT_L4WD_EOI_WDT_EOI_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_EOI. + */ +struct ALT_L4WD_EOI_s +{ + const uint32_t wdt_eoi : 1; /* Interrupt Clear */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L4WD_EOI. */ +typedef volatile struct ALT_L4WD_EOI_s ALT_L4WD_EOI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_EOI register from the beginning of the component. */ +#define ALT_L4WD_EOI_OFST 0x14 +/* The address of the ALT_L4WD_EOI register. */ +#define ALT_L4WD_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_EOI_OFST)) + +/* + * Register : Component Parameters Register 5 - cp_wdt_user_top_max + * + * This is a constant read-only register that contains encoded information about + * the component's parameter settings. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [31:0] | R | 0x0 | Component Parameters 5 + * + */ +/* + * Field : Component Parameters 5 - cp_wdt_user_top_max + * + * Upper limit of Timeout Period parameters. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */ +#define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */ +#define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_MSB 31 +/* The width in bits of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */ +#define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_WIDTH 32 +/* The mask used to set the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field value. */ +#define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field value. */ +#define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_CLR_MSK 0x00000000 +/* The reset value of the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field. */ +#define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_RESET 0x0 +/* Extracts the ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL field value from a register. */ +#define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL register field value suitable for setting the register. */ +#define ALT_L4WD_CP_WDT_USER_TOP_MAX_VAL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_CP_WDT_USER_TOP_MAX. + */ +struct ALT_L4WD_CP_WDT_USER_TOP_MAX_s +{ + const uint32_t cp_wdt_user_top_max : 32; /* Component Parameters 5 */ +}; + +/* The typedef declaration for register ALT_L4WD_CP_WDT_USER_TOP_MAX. */ +typedef volatile struct ALT_L4WD_CP_WDT_USER_TOP_MAX_s ALT_L4WD_CP_WDT_USER_TOP_MAX_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_CP_WDT_USER_TOP_MAX register from the beginning of the component. */ +#define ALT_L4WD_CP_WDT_USER_TOP_MAX_OFST 0xe4 +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register. */ +#define ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CP_WDT_USER_TOP_MAX_OFST)) + +/* + * Register : Component Parameters Register 4 - cp_wdt_user_top_init_max + * + * This is a constant read-only register that contains encoded information about + * the component's parameter settings + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [31:0] | R | 0x0 | Component Parameters 4 + * + */ +/* + * Field : Component Parameters 4 - cp_wdt_user_top_init_max + * + * Upper limit of Initial Timeout Period parameters. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */ +#define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */ +#define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_MSB 31 +/* The width in bits of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */ +#define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_WIDTH 32 +/* The mask used to set the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field value. */ +#define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field value. */ +#define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_CLR_MSK 0x00000000 +/* The reset value of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field. */ +#define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_RESET 0x0 +/* Extracts the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL field value from a register. */ +#define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL register field value suitable for setting the register. */ +#define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_VAL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX. + */ +struct ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_s +{ + const uint32_t cp_wdt_user_top_init_max : 32; /* Component Parameters 4 */ +}; + +/* The typedef declaration for register ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX. */ +typedef volatile struct ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_s ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register from the beginning of the component. */ +#define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_OFST 0xe8 +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register. */ +#define ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_OFST)) + +/* + * Register : Component Parameters Register 3 - cd_wdt_top_rst + * + * This is a constant read-only register that contains encoded information about + * the component's parameter settings. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | R | 0xff | Component Parameters 3 + * + */ +/* + * Field : Component Parameters 3 - cd_wdt_top_rst + * + * Contains the reset value of the WDT_TORR register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */ +#define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */ +#define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_MSB 31 +/* The width in bits of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */ +#define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_WIDTH 32 +/* The mask used to set the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field value. */ +#define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_SET_MSK 0xffffffff +/* The mask used to clear the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field value. */ +#define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_CLR_MSK 0x00000000 +/* The reset value of the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field. */ +#define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_RESET 0xff +/* Extracts the ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST field value from a register. */ +#define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST register field value suitable for setting the register. */ +#define ALT_L4WD_CD_WDT_TOP_RST_CD_WDT_TOP_RST_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_CD_WDT_TOP_RST. + */ +struct ALT_L4WD_CD_WDT_TOP_RST_s +{ + const uint32_t cd_wdt_top_rst : 32; /* Component Parameters 3 */ +}; + +/* The typedef declaration for register ALT_L4WD_CD_WDT_TOP_RST. */ +typedef volatile struct ALT_L4WD_CD_WDT_TOP_RST_s ALT_L4WD_CD_WDT_TOP_RST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_CD_WDT_TOP_RST register from the beginning of the component. */ +#define ALT_L4WD_CD_WDT_TOP_RST_OFST 0xec +/* The address of the ALT_L4WD_CD_WDT_TOP_RST register. */ +#define ALT_L4WD_CD_WDT_TOP_RST_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CD_WDT_TOP_RST_OFST)) + +/* + * Register : Component Parameters Register 2 - cp_wdt_cnt_rst + * + * This is a constant read-only register that contains encoded information about + * the component's parameter settings. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------------------ + * [31:0] | R | 0x7fffffff | Component Parameters 2 + * + */ +/* + * Field : Component Parameters 2 - cp_wdt_cnt_rst + * + * The timeout period range is fixed. The range increments by the power of 2 from 2 + * to the 16 to 2 to the 31. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */ +#define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */ +#define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_MSB 31 +/* The width in bits of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */ +#define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_WIDTH 32 +/* The mask used to set the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field value. */ +#define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_SET_MSK 0xffffffff +/* The mask used to clear the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field value. */ +#define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_CLR_MSK 0x00000000 +/* The reset value of the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field. */ +#define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_RESET 0x7fffffff +/* Extracts the ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST field value from a register. */ +#define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST register field value suitable for setting the register. */ +#define ALT_L4WD_CP_WDT_CNT_RST_CP_WDT_CNT_RST_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_CP_WDT_CNT_RST. + */ +struct ALT_L4WD_CP_WDT_CNT_RST_s +{ + const uint32_t cp_wdt_cnt_rst : 32; /* Component Parameters 2 */ +}; + +/* The typedef declaration for register ALT_L4WD_CP_WDT_CNT_RST. */ +typedef volatile struct ALT_L4WD_CP_WDT_CNT_RST_s ALT_L4WD_CP_WDT_CNT_RST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_CP_WDT_CNT_RST register from the beginning of the component. */ +#define ALT_L4WD_CP_WDT_CNT_RST_OFST 0xf0 +/* The address of the ALT_L4WD_CP_WDT_CNT_RST register. */ +#define ALT_L4WD_CP_WDT_CNT_RST_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CP_WDT_CNT_RST_OFST)) + +/* + * Register : Component Parameters Register 1 - wdt_comp_param_1 + * + * This is a constant read-only register that contains encoded information about + * the component's parameter settings. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Always Enable + * [1] | R | 0x0 | Default Mode + * [2] | R | 0x1 | Dual Timeout Period + * [3] | R | 0x0 | Hardcode Response Mode + * [4] | R | 0x1 | Hardcode Reset Pulse Length + * [5] | R | 0x0 | Hardcode Timeout Period + * [6] | R | 0x1 | Use Pre-defined (Fixed) Timeout Values + * [7] | R | 0x0 | Include Pause Input + * [9:8] | R | 0x2 | APB Data Width + * [12:10] | R | 0x0 | Default Reset Pulse Length + * [15:13] | ??? | 0x0 | *UNDEFINED* + * [19:16] | R | 0xf | Default Timeout Period + * [23:20] | R | 0xf | Default Initial Timeout Period + * [28:24] | R | 0x10 | Counter Width in Bits + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Always Enable - cp_wdt_always_en + * + * Specifies whether watchdog starts after reset or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD | 0x0 | Watchdog disabled on reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN + * + * Watchdog disabled on reset + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_MSB 0 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_WIDTH 1 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_RESET 0x0 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Default Mode - cp_wdt_dflt_rmod + * + * Specifies default output response mode after reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ | 0x0 | Generate a warm reset request (don't generate an + * : | | interrupt first) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD + * + * Generate a warm reset request (don't generate an interrupt first) + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_MSB 1 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_WIDTH 1 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_RESET 0x0 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Dual Timeout Period - cp_wdt_dual_top + * + * Specifies whether a second timeout period that is used for initialization prior + * to the first kick is present or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP | 0x1 | Second timeout period is present + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP + * + * Second timeout period is present + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_MSB 2 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_WIDTH 1 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_RESET 0x1 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Hardcode Response Mode - cp_wdt_hc_rmod + * + * Specifies if response mode (when counter reaches 0) is programmable or + * hardcoded. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:-------------------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML | 0x0 | Output response mode is programmable. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD + * + * Output response mode is programmable. + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_MSB 3 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_WIDTH 1 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET_MSK 0x00000008 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_RESET 0x0 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Hardcode Reset Pulse Length - cp_wdt_hc_rpl + * + * Specifies if the reset pulse length is programmable or hardcoded. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:--------------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED | 0x1 | Reset pulse length is hardcoded. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL + * + * Reset pulse length is hardcoded. + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_MSB 4 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_WIDTH 1 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_CLR_MSK 0xffffffef +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_RESET 0x1 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Hardcode Timeout Period - cp_wdt_hc_top + * + * Specifies if the timeout period is programmable or hardcoded. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML | 0x0 | Timeout period is programmable. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP + * + * Timeout period is programmable. + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_MSB 5 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_WIDTH 1 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET_MSK 0x00000020 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_CLR_MSK 0xffffffdf +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_RESET 0x0 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Use Pre-defined (Fixed) Timeout Values - cp_wdt_use_fix_top + * + * Specifies if the watchdog uses the pre-defined timeout values or if these were + * overriden with customer values when the watchdog was configured. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------------|:------|:---------------------------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED | 0x1 | Use pre-defined (fixed) timeout values (range + * : | | from 2**16 to 2**31) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP + * + * Use pre-defined (fixed) timeout values (range from 2**16 to 2**31) + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_MSB 6 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_WIDTH 1 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_RESET 0x1 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Include Pause Input - cp_wdt_pause + * + * Should specify if the pause input is included or not. However, this field is + * always hardwired to 0 so you can't figure this out by reading this field. The + * pause input is included and can be used to pause the watchdog when the MPU is in + * debug mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_MSB 7 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_WIDTH 1 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_RESET 0x0 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : APB Data Width - cp_wdt_apb_data_width + * + * APB Bus Width + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------------|:------|:-------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH + * + * APB Data Width is 32 Bits + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_MSB 9 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_WIDTH 2 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET_MSK 0x00000300 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_CLR_MSK 0xfffffcff +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_RESET 0x2 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : Default Reset Pulse Length - cp_wdt_dflt_rpl + * + * Specifies the reset pulse length in cycles. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:-------------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES | 0x0 | Reset pulse length of 2 cycles. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL + * + * Reset pulse length of 2 cycles. + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_MSB 12 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_WIDTH 3 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET_MSK 0x00001c00 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_CLR_MSK 0xffffe3ff +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_RESET 0x0 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_GET(value) (((value) & 0x00001c00) >> 10) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET(value) (((value) << 10) & 0x00001c00) + +/* + * Field : Default Timeout Period - cp_wdt_dflt_top + * + * Specifies the timeout period that is available directly after reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15 | 0xf | Timeout period is 15 (2**31 cycles). + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP + * + * Timeout period is 15 (2**31 cycles). + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_MSB 19 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_WIDTH 4 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET_MSK 0x000f0000 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_CLR_MSK 0xfff0ffff +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_RESET 0xf +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_GET(value) (((value) & 0x000f0000) >> 16) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET(value) (((value) << 16) & 0x000f0000) + +/* + * Field : Default Initial Timeout Period - cp_wdt_dflt_top_init + * + * Specifies the initial timeout period that is available directly after reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:--------------------------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15 | 0xf | Initial timeout period is 15 (2**31 cycles). + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT + * + * Initial timeout period is 15 (2**31 cycles). + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_MSB 23 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_WIDTH 4 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET_MSK 0x00f00000 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_CLR_MSK 0xff0fffff +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_RESET 0xf +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_GET(value) (((value) & 0x00f00000) >> 20) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET(value) (((value) << 20) & 0x00f00000) + +/* + * Field : Counter Width in Bits - cp_wdt_cnt_width + * + * Width of counter in bits less 16. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:------------------------- + * ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS | 0x10 | Counter width is 32 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH + * + * Counter width is 32 bits + */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS 0x10 + +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_MSB 28 +/* The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_WIDTH 5 +/* The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_RESET 0x10 +/* Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH field value from a register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_COMP_PARAM_1. + */ +struct ALT_L4WD_COMP_PARAM_1_s +{ + const uint32_t cp_wdt_always_en : 1; /* Always Enable */ + const uint32_t cp_wdt_dflt_rmod : 1; /* Default Mode */ + const uint32_t cp_wdt_dual_top : 1; /* Dual Timeout Period */ + const uint32_t cp_wdt_hc_rmod : 1; /* Hardcode Response Mode */ + const uint32_t cp_wdt_hc_rpl : 1; /* Hardcode Reset Pulse Length */ + const uint32_t cp_wdt_hc_top : 1; /* Hardcode Timeout Period */ + const uint32_t cp_wdt_use_fix_top : 1; /* Use Pre-defined (Fixed) Timeout Values */ + const uint32_t cp_wdt_pause : 1; /* Include Pause Input */ + const uint32_t cp_wdt_apb_data_width : 2; /* APB Data Width */ + const uint32_t cp_wdt_dflt_rpl : 3; /* Default Reset Pulse Length */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t cp_wdt_dflt_top : 4; /* Default Timeout Period */ + const uint32_t cp_wdt_dflt_top_init : 4; /* Default Initial Timeout Period */ + const uint32_t cp_wdt_cnt_width : 5; /* Counter Width in Bits */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_L4WD_COMP_PARAM_1. */ +typedef volatile struct ALT_L4WD_COMP_PARAM_1_s ALT_L4WD_COMP_PARAM_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_COMP_PARAM_1 register from the beginning of the component. */ +#define ALT_L4WD_COMP_PARAM_1_OFST 0xf4 +/* The address of the ALT_L4WD_COMP_PARAM_1 register. */ +#define ALT_L4WD_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_PARAM_1_OFST)) + +/* + * Register : Component Version Register - wdt_comp_version + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------------ + * [31:0] | R | 0x3130362a | Component Version + * + */ +/* + * Field : Component Version - wdt_comp_version + * + * ASCII value for each number in the version, followed by *. For example, + * 32_30_31_2A represents the version 2.01*. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */ +#define ALT_L4WD_COMP_VER_WDT_COMP_VER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */ +#define ALT_L4WD_COMP_VER_WDT_COMP_VER_MSB 31 +/* The width in bits of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */ +#define ALT_L4WD_COMP_VER_WDT_COMP_VER_WIDTH 32 +/* The mask used to set the ALT_L4WD_COMP_VER_WDT_COMP_VER register field value. */ +#define ALT_L4WD_COMP_VER_WDT_COMP_VER_SET_MSK 0xffffffff +/* The mask used to clear the ALT_L4WD_COMP_VER_WDT_COMP_VER register field value. */ +#define ALT_L4WD_COMP_VER_WDT_COMP_VER_CLR_MSK 0x00000000 +/* The reset value of the ALT_L4WD_COMP_VER_WDT_COMP_VER register field. */ +#define ALT_L4WD_COMP_VER_WDT_COMP_VER_RESET 0x3130362a +/* Extracts the ALT_L4WD_COMP_VER_WDT_COMP_VER field value from a register. */ +#define ALT_L4WD_COMP_VER_WDT_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_L4WD_COMP_VER_WDT_COMP_VER register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_VER_WDT_COMP_VER_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_COMP_VER. + */ +struct ALT_L4WD_COMP_VER_s +{ + const uint32_t wdt_comp_version : 32; /* Component Version */ +}; + +/* The typedef declaration for register ALT_L4WD_COMP_VER. */ +typedef volatile struct ALT_L4WD_COMP_VER_s ALT_L4WD_COMP_VER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_COMP_VER register from the beginning of the component. */ +#define ALT_L4WD_COMP_VER_OFST 0xf8 +/* The address of the ALT_L4WD_COMP_VER register. */ +#define ALT_L4WD_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_VER_OFST)) + +/* + * Register : Component Type Register - wdt_comp_type + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:--------------- + * [31:0] | R | 0x44570120 | Component Type + * + */ +/* + * Field : Component Type - wdt_comp_type + * + * Designware Component Type number = 0x44_57_01_20. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */ +#define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */ +#define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_MSB 31 +/* The width in bits of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */ +#define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_WIDTH 32 +/* The mask used to set the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field value. */ +#define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field value. */ +#define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_CLR_MSK 0x00000000 +/* The reset value of the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field. */ +#define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_RESET 0x44570120 +/* Extracts the ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE field value from a register. */ +#define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE register field value suitable for setting the register. */ +#define ALT_L4WD_COMP_TYPE_WDT_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_L4WD_COMP_TYPE. + */ +struct ALT_L4WD_COMP_TYPE_s +{ + const uint32_t wdt_comp_type : 32; /* Component Type */ +}; + +/* The typedef declaration for register ALT_L4WD_COMP_TYPE. */ +typedef volatile struct ALT_L4WD_COMP_TYPE_s ALT_L4WD_COMP_TYPE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_L4WD_COMP_TYPE register from the beginning of the component. */ +#define ALT_L4WD_COMP_TYPE_OFST 0xfc +/* The address of the ALT_L4WD_COMP_TYPE register. */ +#define ALT_L4WD_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_TYPE_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_L4WD. + */ +struct ALT_L4WD_s +{ + volatile ALT_L4WD_CR_t wdt_cr; /* ALT_L4WD_CR */ + volatile ALT_L4WD_TORR_t wdt_torr; /* ALT_L4WD_TORR */ + volatile ALT_L4WD_CCVR_t wdt_ccvr; /* ALT_L4WD_CCVR */ + volatile ALT_L4WD_CRR_t wdt_crr; /* ALT_L4WD_CRR */ + volatile ALT_L4WD_STAT_t wdt_stat; /* ALT_L4WD_STAT */ + volatile ALT_L4WD_EOI_t wdt_eoi; /* ALT_L4WD_EOI */ + volatile uint32_t _pad_0x18_0xe3[51]; /* *UNDEFINED* */ + volatile ALT_L4WD_CP_WDT_USER_TOP_MAX_t cp_wdt_user_top_max; /* ALT_L4WD_CP_WDT_USER_TOP_MAX */ + volatile ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_t cp_wdt_user_top_init_max; /* ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX */ + volatile ALT_L4WD_CD_WDT_TOP_RST_t cd_wdt_top_rst; /* ALT_L4WD_CD_WDT_TOP_RST */ + volatile ALT_L4WD_CP_WDT_CNT_RST_t cp_wdt_cnt_rst; /* ALT_L4WD_CP_WDT_CNT_RST */ + volatile ALT_L4WD_COMP_PARAM_1_t wdt_comp_param_1; /* ALT_L4WD_COMP_PARAM_1 */ + volatile ALT_L4WD_COMP_VER_t wdt_comp_version; /* ALT_L4WD_COMP_VER */ + volatile ALT_L4WD_COMP_TYPE_t wdt_comp_type; /* ALT_L4WD_COMP_TYPE */ +}; + +/* The typedef declaration for register group ALT_L4WD. */ +typedef volatile struct ALT_L4WD_s ALT_L4WD_t; +/* The struct declaration for the raw register contents of register group ALT_L4WD. */ +struct ALT_L4WD_raw_s +{ + volatile uint32_t wdt_cr; /* ALT_L4WD_CR */ + volatile uint32_t wdt_torr; /* ALT_L4WD_TORR */ + volatile uint32_t wdt_ccvr; /* ALT_L4WD_CCVR */ + volatile uint32_t wdt_crr; /* ALT_L4WD_CRR */ + volatile uint32_t wdt_stat; /* ALT_L4WD_STAT */ + volatile uint32_t wdt_eoi; /* ALT_L4WD_EOI */ + volatile uint32_t _pad_0x18_0xe3[51]; /* *UNDEFINED* */ + volatile uint32_t cp_wdt_user_top_max; /* ALT_L4WD_CP_WDT_USER_TOP_MAX */ + volatile uint32_t cp_wdt_user_top_init_max; /* ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX */ + volatile uint32_t cd_wdt_top_rst; /* ALT_L4WD_CD_WDT_TOP_RST */ + volatile uint32_t cp_wdt_cnt_rst; /* ALT_L4WD_CP_WDT_CNT_RST */ + volatile uint32_t wdt_comp_param_1; /* ALT_L4WD_COMP_PARAM_1 */ + volatile uint32_t wdt_comp_version; /* ALT_L4WD_COMP_VER */ + volatile uint32_t wdt_comp_type; /* ALT_L4WD_COMP_TYPE */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_L4WD. */ +typedef volatile struct ALT_L4WD_raw_s ALT_L4WD_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_L4WD_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_lwfpgaslvs.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_lwfpgaslvs.h new file mode 100644 index 000000000..b5f6bc1d1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_lwfpgaslvs.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_LWFPGASLVS */ + +#ifndef __ALTERA_ALT_LWFPGASLVS_H__ +#define __ALTERA_ALT_LWFPGASLVS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : FPGA Slaves Accessed Via Lightweight HPS2FPGA AXI Bridge - ALT_LWFPGASLVS + * FPGA Slaves Accessed Via Lightweight HPS2FPGA AXI Bridge + * + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_LWFPGASLVS_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_lwh2f.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_lwh2f.h new file mode 100644 index 000000000..7cf4aa34a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_lwh2f.h @@ -0,0 +1,1450 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_LWH2F */ + +#ifndef __ALTERA_ALT_LWH2F_H__ +#define __ALTERA_ALT_LWH2F_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : LWHPS2FPGA AXI Bridge Module - ALT_LWH2F + * LWHPS2FPGA AXI Bridge Module + * + * Registers in the LWHPS2FPGA AXI Bridge Module. + * + */ +/* + * Register Group : ID Register Group - ALT_LWH2F_ID + * ID Register Group + * + * Contains registers that identify the ARM NIC-301 IP Core. + * + */ +/* + * Register : Peripheral ID4 Register - periph_id_4 + * + * JEP106 continuation code + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [7:0] | R | 0x4 | Peripheral ID4 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Peripheral ID4 - periph_id_4 + * + * JEP106 continuation code + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7 +/* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8 +/* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4 +/* Extracts the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_ID_PERIPH_ID_4. + */ +struct ALT_LWH2F_ID_PERIPH_ID_4_s +{ + const uint32_t periph_id_4 : 8; /* Peripheral ID4 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_ID_PERIPH_ID_4. */ +typedef volatile struct ALT_LWH2F_ID_PERIPH_ID_4_s ALT_LWH2F_ID_PERIPH_ID_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_ID_PERIPH_ID_4 register from the beginning of the component. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_OFST 0xfd0 + +/* + * Register : Peripheral ID0 Register - periph_id_0 + * + * Peripheral ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [7:0] | R | 0x1 | Part Number [7:0] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Part Number [7:0] - pn7to0 + * + * Part Number [7:0] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_MSB 7 +/* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_WIDTH 8 +/* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff +/* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00 +/* The reset value of the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_RESET 0x1 +/* Extracts the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 field value from a register. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_ID_PERIPH_ID_0. + */ +struct ALT_LWH2F_ID_PERIPH_ID_0_s +{ + const uint32_t pn7to0 : 8; /* Part Number [7:0] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_ID_PERIPH_ID_0. */ +typedef volatile struct ALT_LWH2F_ID_PERIPH_ID_0_s ALT_LWH2F_ID_PERIPH_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_ID_PERIPH_ID_0 register from the beginning of the component. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_OFST 0xfe0 + +/* + * Register : Peripheral ID1 Register - periph_id_1 + * + * Peripheral ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8 + * + * JEP106[3:0], Part Number [11:8] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7 +/* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8 +/* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff +/* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00 +/* The reset value of the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3 +/* Extracts the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_ID_PERIPH_ID_1. + */ +struct ALT_LWH2F_ID_PERIPH_ID_1_s +{ + const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_ID_PERIPH_ID_1. */ +typedef volatile struct ALT_LWH2F_ID_PERIPH_ID_1_s ALT_LWH2F_ID_PERIPH_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_ID_PERIPH_ID_1 register from the beginning of the component. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_OFST 0xfe4 + +/* + * Register : Peripheral ID2 Register - periph_id_2 + * + * Peripheral ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4] + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4 + * + * Revision, JEP106 code flag, JEP106[6:4] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7 +/* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8 +/* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff +/* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00 +/* The reset value of the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b +/* Extracts the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_ID_PERIPH_ID_2. + */ +struct ALT_LWH2F_ID_PERIPH_ID_2_s +{ + const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_ID_PERIPH_ID_2. */ +typedef volatile struct ALT_LWH2F_ID_PERIPH_ID_2_s ALT_LWH2F_ID_PERIPH_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_ID_PERIPH_ID_2 register from the beginning of the component. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_OFST 0xfe8 + +/* + * Register : Peripheral ID3 Register - periph_id_3 + * + * Peripheral ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [3:0] | R | 0x0 | Customer Model Number + * [7:4] | R | 0x0 | Revision + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Customer Model Number - cust_mod_num + * + * Customer Model Number + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3 +/* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4 +/* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f +/* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0 +/* Extracts the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Revision - rev_and + * + * Revision + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_MSB 7 +/* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_WIDTH 4 +/* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field value. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f +/* The reset value of the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_RESET 0x0 +/* Extracts the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND field value from a register. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_ID_PERIPH_ID_3. + */ +struct ALT_LWH2F_ID_PERIPH_ID_3_s +{ + const uint32_t cust_mod_num : 4; /* Customer Model Number */ + const uint32_t rev_and : 4; /* Revision */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_ID_PERIPH_ID_3. */ +typedef volatile struct ALT_LWH2F_ID_PERIPH_ID_3_s ALT_LWH2F_ID_PERIPH_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_ID_PERIPH_ID_3 register from the beginning of the component. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_OFST 0xfec + +/* + * Register : Component ID0 Register - comp_id_0 + * + * Component ID0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xd | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_MSB 7 +/* The width in bits of the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field value. */ +#define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_RESET 0xd +/* Extracts the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE field value from a register. */ +#define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */ +#define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_ID_COMP_ID_0. + */ +struct ALT_LWH2F_ID_COMP_ID_0_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_ID_COMP_ID_0. */ +typedef volatile struct ALT_LWH2F_ID_COMP_ID_0_s ALT_LWH2F_ID_COMP_ID_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_ID_COMP_ID_0 register from the beginning of the component. */ +#define ALT_LWH2F_ID_COMP_ID_0_OFST 0xff0 + +/* + * Register : Component ID1 Register - comp_id_1 + * + * Component ID1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------- + * [7:0] | R | 0xf0 | Generic IP component class, Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Generic IP component class, Preamble - genipcompcls_preamble + * + * Generic IP component class, Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7 +/* The width in bits of the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ +#define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0 +/* Extracts the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */ +#define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */ +#define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_ID_COMP_ID_1. + */ +struct ALT_LWH2F_ID_COMP_ID_1_s +{ + const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_ID_COMP_ID_1. */ +typedef volatile struct ALT_LWH2F_ID_COMP_ID_1_s ALT_LWH2F_ID_COMP_ID_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_ID_COMP_ID_1 register from the beginning of the component. */ +#define ALT_LWH2F_ID_COMP_ID_1_OFST 0xff4 + +/* + * Register : Component ID2 Register - comp_id_2 + * + * Component ID2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0x5 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_MSB 7 +/* The width in bits of the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field value. */ +#define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_RESET 0x5 +/* Extracts the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE field value from a register. */ +#define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */ +#define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_ID_COMP_ID_2. + */ +struct ALT_LWH2F_ID_COMP_ID_2_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_ID_COMP_ID_2. */ +typedef volatile struct ALT_LWH2F_ID_COMP_ID_2_s ALT_LWH2F_ID_COMP_ID_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_ID_COMP_ID_2 register from the beginning of the component. */ +#define ALT_LWH2F_ID_COMP_ID_2_OFST 0xff8 + +/* + * Register : Component ID3 Register - comp_id_3 + * + * Component ID3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | R | 0xb1 | Preamble + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Preamble - preamble + * + * Preamble + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_MSB 7 +/* The width in bits of the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_WIDTH 8 +/* The mask used to set the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field value. */ +#define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field. */ +#define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_RESET 0xb1 +/* Extracts the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE field value from a register. */ +#define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */ +#define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_ID_COMP_ID_3. + */ +struct ALT_LWH2F_ID_COMP_ID_3_s +{ + const uint32_t preamble : 8; /* Preamble */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_ID_COMP_ID_3. */ +typedef volatile struct ALT_LWH2F_ID_COMP_ID_3_s ALT_LWH2F_ID_COMP_ID_3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_ID_COMP_ID_3 register from the beginning of the component. */ +#define ALT_LWH2F_ID_COMP_ID_3_OFST 0xffc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_LWH2F_ID. + */ +struct ALT_LWH2F_ID_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile ALT_LWH2F_ID_PERIPH_ID_4_t periph_id_4; /* ALT_LWH2F_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile ALT_LWH2F_ID_PERIPH_ID_0_t periph_id_0; /* ALT_LWH2F_ID_PERIPH_ID_0 */ + volatile ALT_LWH2F_ID_PERIPH_ID_1_t periph_id_1; /* ALT_LWH2F_ID_PERIPH_ID_1 */ + volatile ALT_LWH2F_ID_PERIPH_ID_2_t periph_id_2; /* ALT_LWH2F_ID_PERIPH_ID_2 */ + volatile ALT_LWH2F_ID_PERIPH_ID_3_t periph_id_3; /* ALT_LWH2F_ID_PERIPH_ID_3 */ + volatile ALT_LWH2F_ID_COMP_ID_0_t comp_id_0; /* ALT_LWH2F_ID_COMP_ID_0 */ + volatile ALT_LWH2F_ID_COMP_ID_1_t comp_id_1; /* ALT_LWH2F_ID_COMP_ID_1 */ + volatile ALT_LWH2F_ID_COMP_ID_2_t comp_id_2; /* ALT_LWH2F_ID_COMP_ID_2 */ + volatile ALT_LWH2F_ID_COMP_ID_3_t comp_id_3; /* ALT_LWH2F_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for register group ALT_LWH2F_ID. */ +typedef volatile struct ALT_LWH2F_ID_s ALT_LWH2F_ID_t; +/* The struct declaration for the raw register contents of register group ALT_LWH2F_ID. */ +struct ALT_LWH2F_ID_raw_s +{ + volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ + volatile uint32_t periph_id_4; /* ALT_LWH2F_ID_PERIPH_ID_4 */ + volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ + volatile uint32_t periph_id_0; /* ALT_LWH2F_ID_PERIPH_ID_0 */ + volatile uint32_t periph_id_1; /* ALT_LWH2F_ID_PERIPH_ID_1 */ + volatile uint32_t periph_id_2; /* ALT_LWH2F_ID_PERIPH_ID_2 */ + volatile uint32_t periph_id_3; /* ALT_LWH2F_ID_PERIPH_ID_3 */ + volatile uint32_t comp_id_0; /* ALT_LWH2F_ID_COMP_ID_0 */ + volatile uint32_t comp_id_1; /* ALT_LWH2F_ID_COMP_ID_1 */ + volatile uint32_t comp_id_2; /* ALT_LWH2F_ID_COMP_ID_2 */ + volatile uint32_t comp_id_3; /* ALT_LWH2F_ID_COMP_ID_3 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_LWH2F_ID. */ +typedef volatile struct ALT_LWH2F_ID_raw_s ALT_LWH2F_ID_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Master Register Group - ALT_LWH2F_MST + * Master Register Group + * + * Registers associated with master interfaces. + * + */ +/* + * Register Group : FPGA2HPS AXI Bridge Registers - ALT_LWH2F_MST_F2H + * FPGA2HPS AXI Bridge Registers + * + * Registers associated with the FPGA2HPS master interface. + * + * This master interface provides access to the registers in the FPGA2HPS AXI + * Bridge. + * + */ +/* + * Register : Bus Matrix Issuing Functionality Modification Register - fn_mod_bm_iss + * + * Sets the issuing capability of the preceding switch arbitration scheme to + * multiple or single outstanding transactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | ALT_LWH2F_FN_MOD_BM_ISS_RD + * [1] | RW | 0x0 | ALT_LWH2F_FN_MOD_BM_ISS_WR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : rd + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------- + * ALT_LWH2F_FN_MOD_BM_ISS_RD_E_MULT | 0x0 | Multiple outstanding read transactions + * ALT_LWH2F_FN_MOD_BM_ISS_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_LWH2F_FN_MOD_BM_ISS_RD + * + * Multiple outstanding read transactions + */ +#define ALT_LWH2F_FN_MOD_BM_ISS_RD_E_MULT 0x0 +/* + * Enumerated value for register field ALT_LWH2F_FN_MOD_BM_ISS_RD + * + * Only a single outstanding read transaction + */ +#define ALT_LWH2F_FN_MOD_BM_ISS_RD_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_FN_MOD_BM_ISS_RD register field. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_RD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_FN_MOD_BM_ISS_RD register field. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_RD_MSB 0 +/* The width in bits of the ALT_LWH2F_FN_MOD_BM_ISS_RD register field. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_RD_WIDTH 1 +/* The mask used to set the ALT_LWH2F_FN_MOD_BM_ISS_RD register field value. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_RD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_LWH2F_FN_MOD_BM_ISS_RD register field value. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_RD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_LWH2F_FN_MOD_BM_ISS_RD register field. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_RD_RESET 0x0 +/* Extracts the ALT_LWH2F_FN_MOD_BM_ISS_RD field value from a register. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_RD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_LWH2F_FN_MOD_BM_ISS_RD register field value suitable for setting the register. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_RD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : wr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------------------------------- + * ALT_LWH2F_FN_MOD_BM_ISS_WR_E_MULT | 0x0 | Multiple outstanding write transactions + * ALT_LWH2F_FN_MOD_BM_ISS_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_LWH2F_FN_MOD_BM_ISS_WR + * + * Multiple outstanding write transactions + */ +#define ALT_LWH2F_FN_MOD_BM_ISS_WR_E_MULT 0x0 +/* + * Enumerated value for register field ALT_LWH2F_FN_MOD_BM_ISS_WR + * + * Only a single outstanding write transaction + */ +#define ALT_LWH2F_FN_MOD_BM_ISS_WR_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_FN_MOD_BM_ISS_WR register field. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_WR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_FN_MOD_BM_ISS_WR register field. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_WR_MSB 1 +/* The width in bits of the ALT_LWH2F_FN_MOD_BM_ISS_WR register field. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_WR_WIDTH 1 +/* The mask used to set the ALT_LWH2F_FN_MOD_BM_ISS_WR register field value. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_WR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_LWH2F_FN_MOD_BM_ISS_WR register field value. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_WR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_LWH2F_FN_MOD_BM_ISS_WR register field. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_WR_RESET 0x0 +/* Extracts the ALT_LWH2F_FN_MOD_BM_ISS_WR field value from a register. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_WR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_LWH2F_FN_MOD_BM_ISS_WR register field value suitable for setting the register. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_WR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_FN_MOD_BM_ISS. + */ +struct ALT_LWH2F_FN_MOD_BM_ISS_s +{ + uint32_t rd : 1; /* ALT_LWH2F_FN_MOD_BM_ISS_RD */ + uint32_t wr : 1; /* ALT_LWH2F_FN_MOD_BM_ISS_WR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_FN_MOD_BM_ISS. */ +typedef volatile struct ALT_LWH2F_FN_MOD_BM_ISS_s ALT_LWH2F_FN_MOD_BM_ISS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_FN_MOD_BM_ISS register from the beginning of the component. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_OFST 0x8 +/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register. */ +#define ALT_LWH2F_FN_MOD_BM_ISS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_LWH2F_FN_MOD_BM_ISS_OFST)) + +/* + * Register : AHB Control Register - ahb_cntl + * + * Sets the block issuing capability to one outstanding transaction. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | ALT_LWH2F_AHB_CNTL_DECERR_EN + * [1] | RW | 0x0 | ALT_LWH2F_AHB_CNTL_FORCE_INCR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : decerr_en + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_LWH2F_AHB_CNTL_DECERR_EN_E_DIS | 0x0 | No DECERR response. + * ALT_LWH2F_AHB_CNTL_DECERR_EN_E_EN | 0x1 | If the AHB protocol conversion function receives + * : | | an unaligned address or a write data beat + * : | | without all the byte strobes set, creates a + * : | | DECERR response. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_LWH2F_AHB_CNTL_DECERR_EN + * + * No DECERR response. + */ +#define ALT_LWH2F_AHB_CNTL_DECERR_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_LWH2F_AHB_CNTL_DECERR_EN + * + * If the AHB protocol conversion function receives an unaligned address or a write + * data beat without all the byte strobes set, creates a DECERR response. + */ +#define ALT_LWH2F_AHB_CNTL_DECERR_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_AHB_CNTL_DECERR_EN register field. */ +#define ALT_LWH2F_AHB_CNTL_DECERR_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_AHB_CNTL_DECERR_EN register field. */ +#define ALT_LWH2F_AHB_CNTL_DECERR_EN_MSB 0 +/* The width in bits of the ALT_LWH2F_AHB_CNTL_DECERR_EN register field. */ +#define ALT_LWH2F_AHB_CNTL_DECERR_EN_WIDTH 1 +/* The mask used to set the ALT_LWH2F_AHB_CNTL_DECERR_EN register field value. */ +#define ALT_LWH2F_AHB_CNTL_DECERR_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_LWH2F_AHB_CNTL_DECERR_EN register field value. */ +#define ALT_LWH2F_AHB_CNTL_DECERR_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_LWH2F_AHB_CNTL_DECERR_EN register field. */ +#define ALT_LWH2F_AHB_CNTL_DECERR_EN_RESET 0x0 +/* Extracts the ALT_LWH2F_AHB_CNTL_DECERR_EN field value from a register. */ +#define ALT_LWH2F_AHB_CNTL_DECERR_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_LWH2F_AHB_CNTL_DECERR_EN register field value suitable for setting the register. */ +#define ALT_LWH2F_AHB_CNTL_DECERR_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : force_incr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_LWH2F_AHB_CNTL_FORCE_INCR_E_DIS | 0x0 | Multiple outstanding write transactions + * ALT_LWH2F_AHB_CNTL_FORCE_INCR_E_EN | 0x1 | If a beat is received that has no write data + * : | | strobes set, that write data beat is replaced + * : | | with an IDLE beat. Also, causes all transactions + * : | | that are to be output to the AHB domain to be an + * : | | undefined length INCR. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_LWH2F_AHB_CNTL_FORCE_INCR + * + * Multiple outstanding write transactions + */ +#define ALT_LWH2F_AHB_CNTL_FORCE_INCR_E_DIS 0x0 +/* + * Enumerated value for register field ALT_LWH2F_AHB_CNTL_FORCE_INCR + * + * If a beat is received that has no write data strobes set, that write data beat + * is replaced with an IDLE beat. Also, causes all transactions that are to be + * output to the AHB domain to be an undefined length INCR. + */ +#define ALT_LWH2F_AHB_CNTL_FORCE_INCR_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_LWH2F_AHB_CNTL_FORCE_INCR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_LWH2F_AHB_CNTL_FORCE_INCR_MSB 1 +/* The width in bits of the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_LWH2F_AHB_CNTL_FORCE_INCR_WIDTH 1 +/* The mask used to set the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field value. */ +#define ALT_LWH2F_AHB_CNTL_FORCE_INCR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field value. */ +#define ALT_LWH2F_AHB_CNTL_FORCE_INCR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field. */ +#define ALT_LWH2F_AHB_CNTL_FORCE_INCR_RESET 0x0 +/* Extracts the ALT_LWH2F_AHB_CNTL_FORCE_INCR field value from a register. */ +#define ALT_LWH2F_AHB_CNTL_FORCE_INCR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_LWH2F_AHB_CNTL_FORCE_INCR register field value suitable for setting the register. */ +#define ALT_LWH2F_AHB_CNTL_FORCE_INCR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_AHB_CNTL. + */ +struct ALT_LWH2F_AHB_CNTL_s +{ + uint32_t decerr_en : 1; /* ALT_LWH2F_AHB_CNTL_DECERR_EN */ + uint32_t force_incr : 1; /* ALT_LWH2F_AHB_CNTL_FORCE_INCR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_AHB_CNTL. */ +typedef volatile struct ALT_LWH2F_AHB_CNTL_s ALT_LWH2F_AHB_CNTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_AHB_CNTL register from the beginning of the component. */ +#define ALT_LWH2F_AHB_CNTL_OFST 0x44 +/* The address of the ALT_LWH2F_AHB_CNTL register. */ +#define ALT_LWH2F_AHB_CNTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_LWH2F_AHB_CNTL_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_LWH2F_MST_F2H. + */ +struct ALT_LWH2F_MST_F2H_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_LWH2F_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_LWH2F_AHB_CNTL_t ahb_cntl; /* ALT_LWH2F_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_LWH2F_MST_F2H. */ +typedef volatile struct ALT_LWH2F_MST_F2H_s ALT_LWH2F_MST_F2H_t; +/* The struct declaration for the raw register contents of register group ALT_LWH2F_MST_F2H. */ +struct ALT_LWH2F_MST_F2H_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_LWH2F_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_LWH2F_MST_F2H. */ +typedef volatile struct ALT_LWH2F_MST_F2H_raw_s ALT_LWH2F_MST_F2H_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : HPS2FPGA AXI Bridge Registers - ALT_LWH2F_MST_H2F + * HPS2FPGA AXI Bridge Registers + * + * Registers associated with the HPS2FPGA master interface. + * + * This master interface provides access to the registers in the HPS2FPGA AXI + * Bridge. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_LWH2F_MST_H2F. + */ +struct ALT_LWH2F_MST_H2F_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_LWH2F_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile ALT_LWH2F_AHB_CNTL_t ahb_cntl; /* ALT_LWH2F_AHB_CNTL */ +}; + +/* The typedef declaration for register group ALT_LWH2F_MST_H2F. */ +typedef volatile struct ALT_LWH2F_MST_H2F_s ALT_LWH2F_MST_H2F_t; +/* The struct declaration for the raw register contents of register group ALT_LWH2F_MST_H2F. */ +struct ALT_LWH2F_MST_H2F_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ + volatile uint32_t ahb_cntl; /* ALT_LWH2F_AHB_CNTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_LWH2F_MST_H2F. */ +typedef volatile struct ALT_LWH2F_MST_H2F_raw_s ALT_LWH2F_MST_H2F_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : 32-bit Master - ALT_LWH2F_MST_B32 + * 32-bit Master + * + * Registers associated with the 32-bit AXI master interface. This master provides + * access to slaves in the FPGA. + * + */ +/* + * Register : Write Tidemark - wr_tidemark + * + * Controls the release of the transaction in the write data FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x4 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Stalls the transaction in the write data FIFO until the number of occupied slots + * in the write data FIFO exceeds the level. Note that the transaction is released + * before this level is achieved if the network receives the WLAST beat or the + * write FIFO becomes full. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_WR_TIDEMARK_LEVEL register field. */ +#define ALT_LWH2F_WR_TIDEMARK_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_WR_TIDEMARK_LEVEL register field. */ +#define ALT_LWH2F_WR_TIDEMARK_LEVEL_MSB 3 +/* The width in bits of the ALT_LWH2F_WR_TIDEMARK_LEVEL register field. */ +#define ALT_LWH2F_WR_TIDEMARK_LEVEL_WIDTH 4 +/* The mask used to set the ALT_LWH2F_WR_TIDEMARK_LEVEL register field value. */ +#define ALT_LWH2F_WR_TIDEMARK_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_LWH2F_WR_TIDEMARK_LEVEL register field value. */ +#define ALT_LWH2F_WR_TIDEMARK_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_LWH2F_WR_TIDEMARK_LEVEL register field. */ +#define ALT_LWH2F_WR_TIDEMARK_LEVEL_RESET 0x4 +/* Extracts the ALT_LWH2F_WR_TIDEMARK_LEVEL field value from a register. */ +#define ALT_LWH2F_WR_TIDEMARK_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_LWH2F_WR_TIDEMARK_LEVEL register field value suitable for setting the register. */ +#define ALT_LWH2F_WR_TIDEMARK_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_WR_TIDEMARK. + */ +struct ALT_LWH2F_WR_TIDEMARK_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_WR_TIDEMARK. */ +typedef volatile struct ALT_LWH2F_WR_TIDEMARK_s ALT_LWH2F_WR_TIDEMARK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_WR_TIDEMARK register from the beginning of the component. */ +#define ALT_LWH2F_WR_TIDEMARK_OFST 0x40 +/* The address of the ALT_LWH2F_WR_TIDEMARK register. */ +#define ALT_LWH2F_WR_TIDEMARK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_LWH2F_WR_TIDEMARK_OFST)) + +/* + * Register : Issuing Functionality Modification Register - fn_mod + * + * Sets the block issuing capability to multiple or single outstanding + * transactions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [0] | RW | 0x0 | ALT_LWH2F_FN_MOD_RD + * [1] | RW | 0x0 | ALT_LWH2F_FN_MOD_WR + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : rd + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------------------------------- + * ALT_LWH2F_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions + * ALT_LWH2F_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_LWH2F_FN_MOD_RD + * + * Multiple outstanding read transactions + */ +#define ALT_LWH2F_FN_MOD_RD_E_MULT 0x0 +/* + * Enumerated value for register field ALT_LWH2F_FN_MOD_RD + * + * Only a single outstanding read transaction + */ +#define ALT_LWH2F_FN_MOD_RD_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_FN_MOD_RD register field. */ +#define ALT_LWH2F_FN_MOD_RD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_FN_MOD_RD register field. */ +#define ALT_LWH2F_FN_MOD_RD_MSB 0 +/* The width in bits of the ALT_LWH2F_FN_MOD_RD register field. */ +#define ALT_LWH2F_FN_MOD_RD_WIDTH 1 +/* The mask used to set the ALT_LWH2F_FN_MOD_RD register field value. */ +#define ALT_LWH2F_FN_MOD_RD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_LWH2F_FN_MOD_RD register field value. */ +#define ALT_LWH2F_FN_MOD_RD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_LWH2F_FN_MOD_RD register field. */ +#define ALT_LWH2F_FN_MOD_RD_RESET 0x0 +/* Extracts the ALT_LWH2F_FN_MOD_RD field value from a register. */ +#define ALT_LWH2F_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_LWH2F_FN_MOD_RD register field value suitable for setting the register. */ +#define ALT_LWH2F_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : wr + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------------------------- + * ALT_LWH2F_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions + * ALT_LWH2F_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_LWH2F_FN_MOD_WR + * + * Multiple outstanding write transactions + */ +#define ALT_LWH2F_FN_MOD_WR_E_MULT 0x0 +/* + * Enumerated value for register field ALT_LWH2F_FN_MOD_WR + * + * Only a single outstanding write transaction + */ +#define ALT_LWH2F_FN_MOD_WR_E_SINGLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_LWH2F_FN_MOD_WR register field. */ +#define ALT_LWH2F_FN_MOD_WR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_LWH2F_FN_MOD_WR register field. */ +#define ALT_LWH2F_FN_MOD_WR_MSB 1 +/* The width in bits of the ALT_LWH2F_FN_MOD_WR register field. */ +#define ALT_LWH2F_FN_MOD_WR_WIDTH 1 +/* The mask used to set the ALT_LWH2F_FN_MOD_WR register field value. */ +#define ALT_LWH2F_FN_MOD_WR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_LWH2F_FN_MOD_WR register field value. */ +#define ALT_LWH2F_FN_MOD_WR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_LWH2F_FN_MOD_WR register field. */ +#define ALT_LWH2F_FN_MOD_WR_RESET 0x0 +/* Extracts the ALT_LWH2F_FN_MOD_WR field value from a register. */ +#define ALT_LWH2F_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_LWH2F_FN_MOD_WR register field value suitable for setting the register. */ +#define ALT_LWH2F_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_LWH2F_FN_MOD. + */ +struct ALT_LWH2F_FN_MOD_s +{ + uint32_t rd : 1; /* ALT_LWH2F_FN_MOD_RD */ + uint32_t wr : 1; /* ALT_LWH2F_FN_MOD_WR */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_LWH2F_FN_MOD. */ +typedef volatile struct ALT_LWH2F_FN_MOD_s ALT_LWH2F_FN_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_LWH2F_FN_MOD register from the beginning of the component. */ +#define ALT_LWH2F_FN_MOD_OFST 0x108 +/* The address of the ALT_LWH2F_FN_MOD register. */ +#define ALT_LWH2F_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_LWH2F_FN_MOD_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_LWH2F_MST_B32. + */ +struct ALT_LWH2F_MST_B32_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile ALT_LWH2F_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile ALT_LWH2F_WR_TIDEMARK_t wr_tidemark; /* ALT_LWH2F_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile ALT_LWH2F_FN_MOD_t fn_mod; /* ALT_LWH2F_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_LWH2F_MST_B32. */ +typedef volatile struct ALT_LWH2F_MST_B32_s ALT_LWH2F_MST_B32_t; +/* The struct declaration for the raw register contents of register group ALT_LWH2F_MST_B32. */ +struct ALT_LWH2F_MST_B32_raw_s +{ + volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ + volatile uint32_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */ + volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ + volatile uint32_t wr_tidemark; /* ALT_LWH2F_WR_TIDEMARK */ + volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_LWH2F_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_LWH2F_MST_B32. */ +typedef volatile struct ALT_LWH2F_MST_B32_raw_s ALT_LWH2F_MST_B32_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_LWH2F_MST. + */ +struct ALT_LWH2F_MST_s +{ + volatile ALT_LWH2F_MST_F2H_t mastergrp_fpga2hpsregs; /* ALT_LWH2F_MST_F2H */ + volatile uint32_t _pad_0x48_0xfff[1006]; /* *UNDEFINED* */ + volatile ALT_LWH2F_MST_H2F_t mastergrp_hps2fpgaregs; /* ALT_LWH2F_MST_H2F */ + volatile uint32_t _pad_0x1048_0x2fff[2030]; /* *UNDEFINED* */ + volatile ALT_LWH2F_MST_B32_t mastergrp_b32; /* ALT_LWH2F_MST_B32 */ +}; + +/* The typedef declaration for register group ALT_LWH2F_MST. */ +typedef volatile struct ALT_LWH2F_MST_s ALT_LWH2F_MST_t; +/* The struct declaration for the raw register contents of register group ALT_LWH2F_MST. */ +struct ALT_LWH2F_MST_raw_s +{ + volatile ALT_LWH2F_MST_F2H_raw_t mastergrp_fpga2hpsregs; /* ALT_LWH2F_MST_F2H */ + volatile uint32_t _pad_0x48_0xfff[1006]; /* *UNDEFINED* */ + volatile ALT_LWH2F_MST_H2F_raw_t mastergrp_hps2fpgaregs; /* ALT_LWH2F_MST_H2F */ + volatile uint32_t _pad_0x1048_0x2fff[2030]; /* *UNDEFINED* */ + volatile ALT_LWH2F_MST_B32_raw_t mastergrp_b32; /* ALT_LWH2F_MST_B32 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_LWH2F_MST. */ +typedef volatile struct ALT_LWH2F_MST_raw_s ALT_LWH2F_MST_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Slave Register Group - ALT_LWH2F_SLV + * Slave Register Group + * + * Registers associated with slave interfaces. + * + */ +/* + * Register Group : L3 Slave Register Group - ALT_LWH2F_SLV_B32 + * L3 Slave Register Group + * + * Registers associated with the 32-bit AXI slave interface. This slave connects to + * the L3 Interconnect. + * + */ +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_LWH2F_SLV_B32. + */ +struct ALT_LWH2F_SLV_B32_s +{ + volatile uint32_t _pad_0x0_0x107[66]; /* *UNDEFINED* */ + volatile ALT_LWH2F_FN_MOD_t fn_mod; /* ALT_LWH2F_FN_MOD */ +}; + +/* The typedef declaration for register group ALT_LWH2F_SLV_B32. */ +typedef volatile struct ALT_LWH2F_SLV_B32_s ALT_LWH2F_SLV_B32_t; +/* The struct declaration for the raw register contents of register group ALT_LWH2F_SLV_B32. */ +struct ALT_LWH2F_SLV_B32_raw_s +{ + volatile uint32_t _pad_0x0_0x107[66]; /* *UNDEFINED* */ + volatile uint32_t fn_mod; /* ALT_LWH2F_FN_MOD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_LWH2F_SLV_B32. */ +typedef volatile struct ALT_LWH2F_SLV_B32_raw_s ALT_LWH2F_SLV_B32_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_LWH2F_SLV. + */ +struct ALT_LWH2F_SLV_s +{ + volatile uint32_t _pad_0x0_0x2fff[3072]; /* *UNDEFINED* */ + volatile ALT_LWH2F_SLV_B32_t slavegrp_b32; /* ALT_LWH2F_SLV_B32 */ +}; + +/* The typedef declaration for register group ALT_LWH2F_SLV. */ +typedef volatile struct ALT_LWH2F_SLV_s ALT_LWH2F_SLV_t; +/* The struct declaration for the raw register contents of register group ALT_LWH2F_SLV. */ +struct ALT_LWH2F_SLV_raw_s +{ + volatile uint32_t _pad_0x0_0x2fff[3072]; /* *UNDEFINED* */ + volatile ALT_LWH2F_SLV_B32_raw_t slavegrp_b32; /* ALT_LWH2F_SLV_B32 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_LWH2F_SLV. */ +typedef volatile struct ALT_LWH2F_SLV_raw_s ALT_LWH2F_SLV_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_LWH2F. + */ +struct ALT_LWH2F_s +{ + volatile uint32_t _pad_0x0_0xfff[1024]; /* *UNDEFINED* */ + volatile ALT_LWH2F_ID_t idgrp; /* ALT_LWH2F_ID */ + volatile ALT_LWH2F_MST_t mastergrp; /* ALT_LWH2F_MST */ + volatile uint32_t _pad_0x510c_0x41fff[62397]; /* *UNDEFINED* */ + volatile ALT_LWH2F_SLV_t slavegrp; /* ALT_LWH2F_SLV */ + volatile uint32_t _pad_0x4510c_0x80000[60349]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_LWH2F. */ +typedef volatile struct ALT_LWH2F_s ALT_LWH2F_t; +/* The struct declaration for the raw register contents of register group ALT_LWH2F. */ +struct ALT_LWH2F_raw_s +{ + volatile uint32_t _pad_0x0_0xfff[1024]; /* *UNDEFINED* */ + volatile ALT_LWH2F_ID_raw_t idgrp; /* ALT_LWH2F_ID */ + volatile ALT_LWH2F_MST_raw_t mastergrp; /* ALT_LWH2F_MST */ + volatile uint32_t _pad_0x510c_0x41fff[62397]; /* *UNDEFINED* */ + volatile ALT_LWH2F_SLV_raw_t slavegrp; /* ALT_LWH2F_SLV */ + volatile uint32_t _pad_0x4510c_0x80000[60349]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_LWH2F. */ +typedef volatile struct ALT_LWH2F_raw_s ALT_LWH2F_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_LWH2F_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_mpul2.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_mpul2.h new file mode 100644 index 000000000..f12a06a3b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_mpul2.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_MPUL2 */ + +#ifndef __ALTERA_ALT_MPUL2_H__ +#define __ALTERA_ALT_MPUL2_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : MPU L2 cache controller Module Address Space - ALT_MPUL2 + * MPU L2 cache controller Module Address Space + * + * Address space allocated to the MPU L2 cache controller. For detailed information + * about the use of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246e/index.html]click + * here[/url] to access the ARM documentation for the L2C-301. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MPUL2_REG_FLD register field. */ +#define ALT_MPUL2_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MPUL2_REG_FLD register field. */ +#define ALT_MPUL2_REG_FLD_MSB 31 +/* The width in bits of the ALT_MPUL2_REG_FLD register field. */ +#define ALT_MPUL2_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_MPUL2_REG_FLD register field value. */ +#define ALT_MPUL2_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_MPUL2_REG_FLD register field value. */ +#define ALT_MPUL2_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_MPUL2_REG_FLD register field is UNKNOWN. */ +#define ALT_MPUL2_REG_FLD_RESET 0x0 +/* Extracts the ALT_MPUL2_REG_FLD field value from a register. */ +#define ALT_MPUL2_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_MPUL2_REG_FLD register field value suitable for setting the register. */ +#define ALT_MPUL2_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MPUL2_REG. + */ +struct ALT_MPUL2_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_MPUL2_REG. */ +typedef volatile struct ALT_MPUL2_REG_s ALT_MPUL2_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MPUL2_REG register from the beginning of the component. */ +#define ALT_MPUL2_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_MPUL2. + */ +struct ALT_MPUL2_s +{ + volatile ALT_MPUL2_REG_t reg; /* ALT_MPUL2_REG */ +}; + +/* The typedef declaration for register group ALT_MPUL2. */ +typedef volatile struct ALT_MPUL2_s ALT_MPUL2_t; +/* The struct declaration for the raw register contents of register group ALT_MPUL2. */ +struct ALT_MPUL2_raw_s +{ + volatile uint32_t reg; /* ALT_MPUL2_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_MPUL2. */ +typedef volatile struct ALT_MPUL2_raw_s ALT_MPUL2_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_MPUL2_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_mpuscu.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_mpuscu.h new file mode 100644 index 000000000..e07822f96 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_mpuscu.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_MPUSCU */ + +#ifndef __ALTERA_ALT_MPUSCU_H__ +#define __ALTERA_ALT_MPUSCU_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : MPU SCU Module Address Space - ALT_MPUSCU + * MPU SCU Module Address Space + * + * Address space allocated to the MPU SCU. For detailed information about the use + * of this address space, + * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/index.html]click + * here[/url] to access the ARM documentation for the Cortex-A9 MPCore. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_MPUSCU_REG_FLD register field. */ +#define ALT_MPUSCU_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_MPUSCU_REG_FLD register field. */ +#define ALT_MPUSCU_REG_FLD_MSB 31 +/* The width in bits of the ALT_MPUSCU_REG_FLD register field. */ +#define ALT_MPUSCU_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_MPUSCU_REG_FLD register field value. */ +#define ALT_MPUSCU_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_MPUSCU_REG_FLD register field value. */ +#define ALT_MPUSCU_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_MPUSCU_REG_FLD register field is UNKNOWN. */ +#define ALT_MPUSCU_REG_FLD_RESET 0x0 +/* Extracts the ALT_MPUSCU_REG_FLD field value from a register. */ +#define ALT_MPUSCU_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_MPUSCU_REG_FLD register field value suitable for setting the register. */ +#define ALT_MPUSCU_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_MPUSCU_REG. + */ +struct ALT_MPUSCU_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_MPUSCU_REG. */ +typedef volatile struct ALT_MPUSCU_REG_s ALT_MPUSCU_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_MPUSCU_REG register from the beginning of the component. */ +#define ALT_MPUSCU_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_MPUSCU. + */ +struct ALT_MPUSCU_s +{ + volatile ALT_MPUSCU_REG_t reg; /* ALT_MPUSCU_REG */ +}; + +/* The typedef declaration for register group ALT_MPUSCU. */ +typedef volatile struct ALT_MPUSCU_s ALT_MPUSCU_t; +/* The struct declaration for the raw register contents of register group ALT_MPUSCU. */ +struct ALT_MPUSCU_raw_s +{ + volatile uint32_t reg; /* ALT_MPUSCU_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_MPUSCU. */ +typedef volatile struct ALT_MPUSCU_raw_s ALT_MPUSCU_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_MPUSCU_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_nand.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_nand.h new file mode 100644 index 000000000..f10f46bbb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_nand.h @@ -0,0 +1,10617 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_NAND */ + +#ifndef __ALTERA_ALT_NAND_H__ +#define __ALTERA_ALT_NAND_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : NAND Flash Controller Module Registers (AXI Slave) - ALT_NAND + * NAND Flash Controller Module Registers (AXI Slave) + * + * Registers in the NAND Flash Controller module accessible via its register AXI + * slave + * + */ +/* + * Register Group : Configuration registers - ALT_NAND_CFG + * Configuration registers + * + * Common across all types of flash devices, configuration registers setup the + * basic operating modes of the controller + * + */ +/* + * Register : device_reset + * + * Device reset. Controller sends a RESET command to device. Controller resets bit + * after sending command to device + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK0 + * [1] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK1 + * [2] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK2 + * [3] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK3 + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : bank0 + * + * Issues reset to bank 0. Controller resets the bit after reset command is issued + * to device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK0_MSB 0 +/* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK0_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK0 register field value. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK0 register field value. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK0_RESET 0x0 +/* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK0 field value from a register. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_DEVICE_RST_BANK0 register field value suitable for setting the register. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : bank1 + * + * Issues reset to bank 1. Controller resets the bit after reset command is issued + * to device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK1_MSB 1 +/* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK1_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK1 register field value. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK1 register field value. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK1_RESET 0x0 +/* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK1 field value from a register. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_NAND_CFG_DEVICE_RST_BANK1 register field value suitable for setting the register. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : bank2 + * + * Issues reset to bank 2. Controller resets the bit after reset command is issued + * to device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK2_MSB 2 +/* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK2_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK2 register field value. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK2 register field value. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK2_RESET 0x0 +/* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK2 field value from a register. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_NAND_CFG_DEVICE_RST_BANK2 register field value suitable for setting the register. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : bank3 + * + * Issues reset to bank 3. Controller resets the bit after reset command is issued + * to device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK3_MSB 3 +/* The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK3_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK3 register field value. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK3 register field value. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK3_RESET 0x0 +/* Extracts the ALT_NAND_CFG_DEVICE_RST_BANK3 field value from a register. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_NAND_CFG_DEVICE_RST_BANK3 register field value suitable for setting the register. */ +#define ALT_NAND_CFG_DEVICE_RST_BANK3_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_DEVICE_RST. + */ +struct ALT_NAND_CFG_DEVICE_RST_s +{ + uint32_t bank0 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK0 */ + uint32_t bank1 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK1 */ + uint32_t bank2 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK2 */ + uint32_t bank3 : 1; /* ALT_NAND_CFG_DEVICE_RST_BANK3 */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_DEVICE_RST. */ +typedef volatile struct ALT_NAND_CFG_DEVICE_RST_s ALT_NAND_CFG_DEVICE_RST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_DEVICE_RST register from the beginning of the component. */ +#define ALT_NAND_CFG_DEVICE_RST_OFST 0x0 + +/* + * Register : transfer_spare_reg + * + * Default data transfer mode. (Ignored during Spare only mode) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [0] | RW | 0x0 | ALT_NAND_CFG_TFR_SPARE_REG_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * On all read or write commands through Map 01, if this bit is set, data in spare + * area of memory will be transfered to host along with main area of data. The main + * area will be transfered followed by spare area.[list][*]1 - MAIN+SPARE [*]0 - + * MAIN[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field value. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field value. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_CFG_TFR_SPARE_REG_FLAG field value from a register. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_TFR_SPARE_REG_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_TFR_SPARE_REG. + */ +struct ALT_NAND_CFG_TFR_SPARE_REG_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_TFR_SPARE_REG_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_TFR_SPARE_REG. */ +typedef volatile struct ALT_NAND_CFG_TFR_SPARE_REG_s ALT_NAND_CFG_TFR_SPARE_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_TFR_SPARE_REG register from the beginning of the component. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_OFST 0x10 + +/* + * Register : load_wait_cnt + * + * Wait count value for Load operation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------- + * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_LD_WAIT_CNT_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Number of clock cycles after issue of load operation before NAND Flash + * Controller polls for status. This values is of relevance for status polling mode + * of operation and has been provided to minimize redundant polling after issuing a + * command. After a load command, the first polling will happen after this many + * number of cycles have elapsed and then on polling will happen every + * int_mon_cyccnt cycles. The default values is equal to the default value of + * int_mon_cyccnt + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_RESET 0x1f4 +/* Extracts the ALT_NAND_CFG_LD_WAIT_CNT_VALUE field value from a register. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_LD_WAIT_CNT_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_LD_WAIT_CNT. + */ +struct ALT_NAND_CFG_LD_WAIT_CNT_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_LD_WAIT_CNT_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_LD_WAIT_CNT. */ +typedef volatile struct ALT_NAND_CFG_LD_WAIT_CNT_s ALT_NAND_CFG_LD_WAIT_CNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_LD_WAIT_CNT register from the beginning of the component. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_OFST 0x20 + +/* + * Register : program_wait_cnt + * + * Wait count value for Program operation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Number of clock cycles after issue of program operation before NAND Flash + * Controller polls for status. This values is of relevance for status polling mode + * of operation and has been provided to minimize redundant polling after issuing a + * command. After a program command, the first polling will happen after this many + * number of cycles have elapsed and then on polling will happen every + * int_mon_cyccnt cycles. The default values is equal to the default value of + * int_mon_cyccnt. The controller internally multiplies the value programmed into + * this register by 16 to provide a wider range for polling. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_RESET 0x1f4 +/* Extracts the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE field value from a register. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_PROGRAM_WAIT_CNT. + */ +struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_PROGRAM_WAIT_CNT. */ +typedef volatile struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s ALT_NAND_CFG_PROGRAM_WAIT_CNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register from the beginning of the component. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST 0x30 + +/* + * Register : erase_wait_cnt + * + * Wait count value for Erase operation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Number of clock cycles after issue of erase operation before NAND Flash + * Controller polls for status. This values is of relevance for status polling mode + * of operation and has been provided to minimize redundant polling after issuing a + * command. After a erase command, the first polling will happen after this many + * number of cycles have elapsed and then on polling will happen every + * int_mon_cyccnt cycles. The default values is equal to the default value of + * int_mon_cyccnt. The controller internally multiplies the value programmed into + * this register by 16 to provide a wider range for polling. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_RESET 0x1f4 +/* Extracts the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE field value from a register. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_ERASE_WAIT_CNT. + */ +struct ALT_NAND_CFG_ERASE_WAIT_CNT_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_ERASE_WAIT_CNT. */ +typedef volatile struct ALT_NAND_CFG_ERASE_WAIT_CNT_s ALT_NAND_CFG_ERASE_WAIT_CNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_ERASE_WAIT_CNT register from the beginning of the component. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_OFST 0x40 + +/* + * Register : int_mon_cyccnt + * + * Interrupt monitor cycle count value + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_INT_MON_CYCCNT_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * In polling mode, sets the number of cycles Denali Flash Controller must wait + * before checking the status register. This register is only used when R/B pins + * are not available to NAND Flash Controller. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_RESET 0x1f4 +/* Extracts the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE field value from a register. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_INT_MON_CYCCNT. + */ +struct ALT_NAND_CFG_INT_MON_CYCCNT_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_INT_MON_CYCCNT_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_INT_MON_CYCCNT. */ +typedef volatile struct ALT_NAND_CFG_INT_MON_CYCCNT_s ALT_NAND_CFG_INT_MON_CYCCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_INT_MON_CYCCNT register from the beginning of the component. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_OFST 0x50 + +/* + * Register : rb_pin_enabled + * + * Interrupt or polling mode. Ready/Busy pin is enabled from device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x1 | ALT_NAND_CFG_RB_PIN_END_BANK0 + * [1] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_END_BANK1 + * [2] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_END_BANK2 + * [3] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_END_BANK3 + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : bank0 + * + * Sets Denali Flash Controller in interrupt pin or polling mode [list][*]1 - R/B + * pin enabled for bank 0. Interrupt pin mode. [*]0 - R/B pin disabled for bank 0. + * Polling mode.[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK0_MSB 0 +/* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK0_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK0 register field value. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK0 register field value. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK0 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK0_RESET 0x1 +/* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK0 field value from a register. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_RB_PIN_END_BANK0 register field value suitable for setting the register. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : bank1 + * + * Sets Denali Flash Controller in interrupt pin or polling mode [list][*]1 - R/B + * pin enabled for bank 1. Interrupt pin mode. [*]0 - R/B pin disabled for bank 1. + * Polling mode.[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK1_MSB 1 +/* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK1_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK1 register field value. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK1 register field value. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK1 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK1_RESET 0x0 +/* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK1 field value from a register. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_NAND_CFG_RB_PIN_END_BANK1 register field value suitable for setting the register. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : bank2 + * + * Sets Denali Flash Controller in interrupt pin or polling mode [list][*]1 - R/B + * pin enabled for bank 2. Interrupt pin mode. [*]0 - R/B pin disabled for bank 2. + * Polling mode.[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK2_MSB 2 +/* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK2_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK2 register field value. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK2 register field value. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK2 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK2_RESET 0x0 +/* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK2 field value from a register. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_NAND_CFG_RB_PIN_END_BANK2 register field value suitable for setting the register. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : bank3 + * + * Sets Denali Flash Controller in interrupt pin or polling mode [list][*]1 - R/B + * pin enabled for bank 3. Interrupt pin mode. [*]0 - R/B pin disabled for bank 3. + * Polling mode.[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK3_MSB 3 +/* The width in bits of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK3_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_RB_PIN_END_BANK3 register field value. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_NAND_CFG_RB_PIN_END_BANK3 register field value. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_NAND_CFG_RB_PIN_END_BANK3 register field. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK3_RESET 0x0 +/* Extracts the ALT_NAND_CFG_RB_PIN_END_BANK3 field value from a register. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_NAND_CFG_RB_PIN_END_BANK3 register field value suitable for setting the register. */ +#define ALT_NAND_CFG_RB_PIN_END_BANK3_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_RB_PIN_END. + */ +struct ALT_NAND_CFG_RB_PIN_END_s +{ + uint32_t bank0 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK0 */ + uint32_t bank1 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK1 */ + uint32_t bank2 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK2 */ + uint32_t bank3 : 1; /* ALT_NAND_CFG_RB_PIN_END_BANK3 */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_RB_PIN_END. */ +typedef volatile struct ALT_NAND_CFG_RB_PIN_END_s ALT_NAND_CFG_RB_PIN_END_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_RB_PIN_END register from the beginning of the component. */ +#define ALT_NAND_CFG_RB_PIN_END_OFST 0x60 + +/* + * Register : multiplane_operation + * + * Multiplane transfer mode. Pipelined read, copyback, erase and program commands + * are transfered in multiplane mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_OP_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * [list][*]1 - Multiplane operation enabled [*]0 - Multiplane operation + * disabled[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field value. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field value. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_CFG_MULTIPLANE_OP_FLAG field value from a register. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_MULTIPLANE_OP_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_OP. + */ +struct ALT_NAND_CFG_MULTIPLANE_OP_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_OP_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_OP. */ +typedef volatile struct ALT_NAND_CFG_MULTIPLANE_OP_s ALT_NAND_CFG_MULTIPLANE_OP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_MULTIPLANE_OP register from the beginning of the component. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_OFST 0x70 + +/* + * Register : multiplane_read_enable + * + * Device supports multiplane read command sequence + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * Certain devices support dedicated multiplane read command sequences to read data + * in the same fashion as is written with multiplane program commands. This bit set + * should be set for the above devices. When not set, pipeline reads in multiplane + * mode will still happen in the order of multiplane writes, though normal read + * command sequences will be issued to the device. [list][*]1 - Device supports + * multiplane read sequence [*]0 - Device does not support multiplane read + * sequence[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field value. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field value. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG field value from a register. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_RD_EN. + */ +struct ALT_NAND_CFG_MULTIPLANE_RD_EN_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_RD_EN. */ +typedef volatile struct ALT_NAND_CFG_MULTIPLANE_RD_EN_s ALT_NAND_CFG_MULTIPLANE_RD_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_MULTIPLANE_RD_EN register from the beginning of the component. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST 0x80 + +/* + * Register : copyback_disable + * + * Device does not support copyback command sequence + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | RW | 0x0 | ALT_NAND_CFG_COPYBACK_DIS_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * [list][*]1 - Copyback disabled [*]0 - Copyback enabled[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */ +#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */ +#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */ +#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field value. */ +#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field value. */ +#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_COPYBACK_DIS_FLAG register field. */ +#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_CFG_COPYBACK_DIS_FLAG field value from a register. */ +#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_COPYBACK_DIS_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_COPYBACK_DIS. + */ +struct ALT_NAND_CFG_COPYBACK_DIS_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_COPYBACK_DIS_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_COPYBACK_DIS. */ +typedef volatile struct ALT_NAND_CFG_COPYBACK_DIS_s ALT_NAND_CFG_COPYBACK_DIS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_COPYBACK_DIS register from the beginning of the component. */ +#define ALT_NAND_CFG_COPYBACK_DIS_OFST 0x90 + +/* + * Register : cache_write_enable + * + * Device supports cache write command sequence + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | ALT_NAND_CFG_CACHE_WR_EN_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * [list][*]1 - Cache write supported [*]0 - Cache write not supported[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */ +#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */ +#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */ +#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field value. */ +#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field value. */ +#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_CACHE_WR_EN_FLAG register field. */ +#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_CFG_CACHE_WR_EN_FLAG field value from a register. */ +#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_CACHE_WR_EN_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_CACHE_WR_EN. + */ +struct ALT_NAND_CFG_CACHE_WR_EN_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_CACHE_WR_EN_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_CACHE_WR_EN. */ +typedef volatile struct ALT_NAND_CFG_CACHE_WR_EN_s ALT_NAND_CFG_CACHE_WR_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_CACHE_WR_EN register from the beginning of the component. */ +#define ALT_NAND_CFG_CACHE_WR_EN_OFST 0xa0 + +/* + * Register : cache_read_enable + * + * Device supports cache read command sequence + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | ALT_NAND_CFG_CACHE_RD_EN_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * [list][*]1 - Cache read supported [*]0 - Cache read not supported[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */ +#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */ +#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */ +#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field value. */ +#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field value. */ +#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_CACHE_RD_EN_FLAG register field. */ +#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_CFG_CACHE_RD_EN_FLAG field value from a register. */ +#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_CACHE_RD_EN_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_CACHE_RD_EN. + */ +struct ALT_NAND_CFG_CACHE_RD_EN_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_CACHE_RD_EN_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_CACHE_RD_EN. */ +typedef volatile struct ALT_NAND_CFG_CACHE_RD_EN_s ALT_NAND_CFG_CACHE_RD_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_CACHE_RD_EN register from the beginning of the component. */ +#define ALT_NAND_CFG_CACHE_RD_EN_OFST 0xb0 + +/* + * Register : prefetch_mode + * + * Enables read data prefetching to faster performance + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------------- + * [0] | RW | 0x1 | ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN + * [3:1] | ??? | 0x0 | *UNDEFINED* + * [15:4] | RW | 0x0 | ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : prefetch_en + * + * Enable prefetch of Data + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_MSB 0 +/* The width in bits of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field value. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field value. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_RESET 0x1 +/* Extracts the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN field value from a register. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN register field value suitable for setting the register. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : prefetch_burst_length + * + * If prefetch_en is set and prefetch_burst_length is set to ZERO, the controller + * will start prefetching data only after the receiving the first Map01 read + * command for the page. If prefetch_en is set and prefetch_burst_length is set to + * a non-ZERO, valid value, the controller will start prefetching data + * corresponding to this value even before the first Map01 for the current page has + * been received. The value written here should be in bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_MSB 15 +/* The width in bits of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_WIDTH 12 +/* The mask used to set the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field value. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET_MSK 0x0000fff0 +/* The mask used to clear the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field value. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_CLR_MSK 0xffff000f +/* The reset value of the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_RESET 0x0 +/* Extracts the ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN field value from a register. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_GET(value) (((value) & 0x0000fff0) >> 4) +/* Produces a ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN register field value suitable for setting the register. */ +#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET(value) (((value) << 4) & 0x0000fff0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_PREFETCH_MOD. + */ +struct ALT_NAND_CFG_PREFETCH_MOD_s +{ + uint32_t prefetch_en : 1; /* ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t prefetch_burst_length : 12; /* ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_PREFETCH_MOD. */ +typedef volatile struct ALT_NAND_CFG_PREFETCH_MOD_s ALT_NAND_CFG_PREFETCH_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_PREFETCH_MOD register from the beginning of the component. */ +#define ALT_NAND_CFG_PREFETCH_MOD_OFST 0xc0 + +/* + * Register : chip_enable_dont_care + * + * Device can work in the chip enable dont care mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | RW | 0x0 | ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * Controller can interleave commands between banks when this feature is enabled. + * [list][*]1 - Device in dont care mode [*]0 - Device cares for chip enable[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field value. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field value. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG field value from a register. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_CHIP_EN_DONT_CARE. + */ +struct ALT_NAND_CFG_CHIP_EN_DONT_CARE_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_CHIP_EN_DONT_CARE. */ +typedef volatile struct ALT_NAND_CFG_CHIP_EN_DONT_CARE_s ALT_NAND_CFG_CHIP_EN_DONT_CARE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_CHIP_EN_DONT_CARE register from the beginning of the component. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST 0xd0 + +/* + * Register : ecc_enable + * + * Enable controller ECC check bit generation and correction + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x1 | ALT_NAND_CFG_ECC_EN_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * Enables or disables controller ECC capabilities. When enabled, controller + * calculates ECC check-bits and writes them onto device on program operation. On + * page reads, check-bits are recomputed and errors reported, if any, after + * comparing with stored check-bits. When disabled, controller does not compute + * check-bits. [list][*]1 - ECC Enabled [*]0 - ECC disabled[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_EN_FLAG register field. */ +#define ALT_NAND_CFG_ECC_EN_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_EN_FLAG register field. */ +#define ALT_NAND_CFG_ECC_EN_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_ECC_EN_FLAG register field. */ +#define ALT_NAND_CFG_ECC_EN_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_ECC_EN_FLAG register field value. */ +#define ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_ECC_EN_FLAG register field value. */ +#define ALT_NAND_CFG_ECC_EN_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_ECC_EN_FLAG register field. */ +#define ALT_NAND_CFG_ECC_EN_FLAG_RESET 0x1 +/* Extracts the ALT_NAND_CFG_ECC_EN_FLAG field value from a register. */ +#define ALT_NAND_CFG_ECC_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_ECC_EN_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_ECC_EN_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_ECC_EN. + */ +struct ALT_NAND_CFG_ECC_EN_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_ECC_EN_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_ECC_EN. */ +typedef volatile struct ALT_NAND_CFG_ECC_EN_s ALT_NAND_CFG_ECC_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_ECC_EN register from the beginning of the component. */ +#define ALT_NAND_CFG_ECC_EN_OFST 0xe0 + +/* + * Register : global_int_enable + * + * Global Interrupt enable and Error/Timeout disable. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_CFG_GLOB_INT_EN_FLAG + * [3:1] | ??? | 0x0 | *UNDEFINED* + * [4] | RW | 0x0 | ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS + * [7:5] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * Host will receive an interrupt only when this bit is set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field value. */ +#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field value. */ +#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_GLOB_INT_EN_FLAG register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_CFG_GLOB_INT_EN_FLAG field value from a register. */ +#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_GLOB_INT_EN_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : timeout_disable + * + * Watchdog timer logic will be de-activated when this bit is set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_MSB 4 +/* The width in bits of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field value. */ +#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field value. */ +#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_RESET 0x0 +/* Extracts the ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS field value from a register. */ +#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS register field value suitable for setting the register. */ +#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : error_rpt_disable + * + * Command and ECC uncorrectable failures will not be reported when this bit is set + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_MSB 8 +/* The width in bits of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field value. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field value. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_RESET 0x0 +/* Extracts the ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS field value from a register. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS register field value suitable for setting the register. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_GLOB_INT_EN. + */ +struct ALT_NAND_CFG_GLOB_INT_EN_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_GLOB_INT_EN_FLAG */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t timeout_disable : 1; /* ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t error_rpt_disable : 1; /* ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_GLOB_INT_EN. */ +typedef volatile struct ALT_NAND_CFG_GLOB_INT_EN_s ALT_NAND_CFG_GLOB_INT_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_GLOB_INT_EN register from the beginning of the component. */ +#define ALT_NAND_CFG_GLOB_INT_EN_OFST 0xf0 + +/* + * Register : twhr2_and_we_2_re + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [5:0] | RW | 0x32 | ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE + * [7:6] | ??? | 0x0 | *UNDEFINED* + * [13:8] | RW | 0x14 | ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : we_2_re + * + * Signifies the number of bus interface nand_mp_clk clocks that should be + * introduced between write enable going high to read enable going low. The number + * of clocks is the function of device parameter Twhr and controller clock + * frequency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB 5 +/* The width in bits of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH 6 +/* The mask used to set the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK 0x0000003f +/* The mask used to clear the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET 0x32 +/* Extracts the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE field value from a register. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET(value) (((value) << 0) & 0x0000003f) + +/* + * Field : twhr2 + * + * Signifies the number of controller clocks that should be introduced between the + * last command of a random data output command to the start of the data transfer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB 13 +/* The width in bits of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH 6 +/* The mask used to set the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK 0x00003f00 +/* The mask used to clear the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK 0xffffc0ff +/* The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET 0x14 +/* Extracts the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 field value from a register. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET(value) (((value) & 0x00003f00) >> 8) +/* Produces a ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value suitable for setting the register. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET(value) (((value) << 8) & 0x00003f00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_TWHR2_AND_WE_2_RE. + */ +struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s +{ + uint32_t we_2_re : 6; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t twhr2 : 6; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_TWHR2_AND_WE_2_RE. */ +typedef volatile struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register from the beginning of the component. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST 0x100 + +/* + * Register : tcwaw_and_addr_2_data + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------------- + * [5:0] | RW | 0x32 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA + * [7:6] | ??? | 0x0 | *UNDEFINED* + * [13:8] | RW | 0x14 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : addr_2_data + * + * Signifies the number of bus interface nand_mp_clk clocks that should be + * introduced between address latch enable going low to write enable going low. The + * number of clocks is the function of device parameter Tadl and controller clock + * frequency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 5 +/* The width in bits of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 6 +/* The mask used to set the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000003f +/* The mask used to clear the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32 +/* Extracts the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA field value from a register. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value suitable for setting the register. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET(value) (((value) << 0) & 0x0000003f) + +/* + * Field : tcwaw + * + * Signifies the number of controller clocks that should be introduced between the + * command cycle of a random data input command to the address cycle of the random + * data input command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13 +/* The width in bits of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6 +/* The mask used to set the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00 +/* The mask used to clear the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff +/* The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14 +/* Extracts the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW field value from a register. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET(value) (((value) & 0x00003f00) >> 8) +/* Produces a ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value suitable for setting the register. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET(value) (((value) << 8) & 0x00003f00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA. + */ +struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s +{ + uint32_t addr_2_data : 6; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t tcwaw : 6; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA. */ +typedef volatile struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register from the beginning of the component. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110 + +/* + * Register : re_2_we + * + * Timing parameter between re high to we low (Trhw) + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [5:0] | RW | 0x32 | ALT_NAND_CFG_RE_2_WE_VALUE + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Signifies the number of bus interface nand_mp_clk clocks that should be + * introduced between read enable going high to write enable going low. The number + * of clocks is the function of device parameter Trhw and controller clock + * frequency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */ +#define ALT_NAND_CFG_RE_2_WE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */ +#define ALT_NAND_CFG_RE_2_WE_VALUE_MSB 5 +/* The width in bits of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */ +#define ALT_NAND_CFG_RE_2_WE_VALUE_WIDTH 6 +/* The mask used to set the ALT_NAND_CFG_RE_2_WE_VALUE register field value. */ +#define ALT_NAND_CFG_RE_2_WE_VALUE_SET_MSK 0x0000003f +/* The mask used to clear the ALT_NAND_CFG_RE_2_WE_VALUE register field value. */ +#define ALT_NAND_CFG_RE_2_WE_VALUE_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */ +#define ALT_NAND_CFG_RE_2_WE_VALUE_RESET 0x32 +/* Extracts the ALT_NAND_CFG_RE_2_WE_VALUE field value from a register. */ +#define ALT_NAND_CFG_RE_2_WE_VALUE_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_NAND_CFG_RE_2_WE_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_RE_2_WE_VALUE_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_RE_2_WE. + */ +struct ALT_NAND_CFG_RE_2_WE_s +{ + uint32_t value : 6; /* ALT_NAND_CFG_RE_2_WE_VALUE */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_RE_2_WE. */ +typedef volatile struct ALT_NAND_CFG_RE_2_WE_s ALT_NAND_CFG_RE_2_WE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_RE_2_WE register from the beginning of the component. */ +#define ALT_NAND_CFG_RE_2_WE_OFST 0x120 + +/* + * Register : acc_clks + * + * Timing parameter from read enable going low to capture read data + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [3:0] | RW | 0x0 | ALT_NAND_CFG_ACC_CLKS_VALUE + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Signifies the number of bus interface nand_mp_clk clock cycles, controller + * should wait from read enable going low to sending out a strobe of nand_mp_clk + * for capturing of incoming data. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */ +#define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */ +#define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB 3 +/* The width in bits of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */ +#define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH 4 +/* The mask used to set the ALT_NAND_CFG_ACC_CLKS_VALUE register field value. */ +#define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK 0x0000000f +/* The mask used to clear the ALT_NAND_CFG_ACC_CLKS_VALUE register field value. */ +#define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */ +#define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_ACC_CLKS_VALUE field value from a register. */ +#define ALT_NAND_CFG_ACC_CLKS_VALUE_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_NAND_CFG_ACC_CLKS_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_ACC_CLKS_VALUE_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_ACC_CLKS. + */ +struct ALT_NAND_CFG_ACC_CLKS_s +{ + uint32_t value : 4; /* ALT_NAND_CFG_ACC_CLKS_VALUE */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_ACC_CLKS. */ +typedef volatile struct ALT_NAND_CFG_ACC_CLKS_s ALT_NAND_CFG_ACC_CLKS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_ACC_CLKS register from the beginning of the component. */ +#define ALT_NAND_CFG_ACC_CLKS_OFST 0x130 + +/* + * Register : number_of_planes + * + * Number of planes in the device + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [2:0] | RW | 0x0 | ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Controller will read Electronic Signature of devices and populate this field as + * the number of planes information is present in the signature. For 512B device, + * this information needs to be programmed by software. Software could also choose + * to override the populated value. The values in the fields should be as + * follows[list] [*]3'h0 - Monoplane device [*]3'h1 - Two plane device [*]3'h3 - 4 + * plane device [*]3'h7 - 8 plane device [*]All other values - Reserved[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_MSB 2 +/* The width in bits of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_WIDTH 3 +/* The mask used to set the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET_MSK 0x00000007 +/* The mask used to clear the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE field value from a register. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET(value) (((value) << 0) & 0x00000007) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_NUMBER_OF_PLANES. + */ +struct ALT_NAND_CFG_NUMBER_OF_PLANES_s +{ + uint32_t value : 3; /* ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_NUMBER_OF_PLANES. */ +typedef volatile struct ALT_NAND_CFG_NUMBER_OF_PLANES_s ALT_NAND_CFG_NUMBER_OF_PLANES_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_NUMBER_OF_PLANES register from the beginning of the component. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_OFST 0x140 + +/* + * Register : pages_per_block + * + * Number of pages in a block + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [15:0] | RW | 0x0 | ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Controller will read Electronic Signature of devices and populate this field. + * The PAGE512 field of the System Manager NANDGRP_BOOTSTRAP register will + * determine the value of this field to be of 32. Software could also choose to + * override the populated value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE field value from a register. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_PAGES_PER_BLOCK. + */ +struct ALT_NAND_CFG_PAGES_PER_BLOCK_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_PAGES_PER_BLOCK. */ +typedef volatile struct ALT_NAND_CFG_PAGES_PER_BLOCK_s ALT_NAND_CFG_PAGES_PER_BLOCK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_PAGES_PER_BLOCK register from the beginning of the component. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_OFST 0x150 + +/* + * Register : device_width + * + * I/O width of attached devices + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x3 | ALT_NAND_CFG_DEVICE_WIDTH_VALUE + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Controller will read Electronic Signature of devices and populate this field. + * Software could also choose to override the populated value although only one + * value is supported. The values in this field should be as follows[list][*]2'h00 + * - 8bit device[*]All other values - Reserved[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_MSB 1 +/* The width in bits of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_WIDTH 2 +/* The mask used to set the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET_MSK 0x00000003 +/* The mask used to clear the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_CLR_MSK 0xfffffffc +/* The reset value of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_RESET 0x3 +/* Extracts the ALT_NAND_CFG_DEVICE_WIDTH_VALUE field value from a register. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_DEVICE_WIDTH. + */ +struct ALT_NAND_CFG_DEVICE_WIDTH_s +{ + uint32_t value : 2; /* ALT_NAND_CFG_DEVICE_WIDTH_VALUE */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_DEVICE_WIDTH. */ +typedef volatile struct ALT_NAND_CFG_DEVICE_WIDTH_s ALT_NAND_CFG_DEVICE_WIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_DEVICE_WIDTH register from the beginning of the component. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_OFST 0x160 + +/* + * Register : device_main_area_size + * + * Page main area size of device in bytes + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------- + * [15:0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Controller will read Electronic Signature of devices and populate this field. + * The PAGE512 field of the System Manager NANDGRP_BOOTSTRAP register will + * determine the value of this field to be 512. Software could also choose to + * override the populated value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE field value from a register. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE. + */ +struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE. */ +typedef volatile struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register from the beginning of the component. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST 0x170 + +/* + * Register : device_spare_area_size + * + * Page spare area size of device in bytes + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [15:0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Controller will read Electronic Signature of devices and populate this field. + * The PAGE512 field of the System Manager NANDGRP_BOOTSTRAP register will + * determine the value of this field to be 16. Software could also choose to + * override the populated value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE field value from a register. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE. + */ +struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE. */ +typedef volatile struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register from the beginning of the component. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST 0x180 + +/* + * Register : two_row_addr_cycles + * + * Attached device has only 2 ROW address cycles + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * This flag must be set for devices which allow for 2 ROW address cycles instead + * of the usual 3. Alternatively, the TWOROWADDR field of the System Manager + * NANDGRP_BOOTSTRAP register when asserted will set this flag. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG field value from a register. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES. + */ +struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES. */ +typedef volatile struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register from the beginning of the component. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190 + +/* + * Register : multiplane_addr_restrict + * + * Address restriction for multiplane commands + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * This flag must be set for devices which require that during multiplane + * operations all but the address for the last plane should have their address + * cycles tied low. The last plane address cycles has proper values. This ensures + * multiplane address restrictions in the device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG field value from a register. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT. + */ +struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT. */ +typedef volatile struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register from the beginning of the component. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST 0x1a0 + +/* + * Register : ecc_correction + * + * Correction capability required + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [7:0] | RW | 0x8 | ALT_NAND_CFG_ECC_CORRECTION_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The required correction capability can be a number less than the configured + * error correction capability. A smaller correction capability will lead to lesser + * number of ECC check-bits being written per ECC sector. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */ +#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */ +#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */ +#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value. */ +#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value. */ +#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */ +#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET 0x8 +/* Extracts the ALT_NAND_CFG_ECC_CORRECTION_VALUE field value from a register. */ +#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_ECC_CORRECTION. + */ +struct ALT_NAND_CFG_ECC_CORRECTION_s +{ + uint32_t value : 8; /* ALT_NAND_CFG_ECC_CORRECTION_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_ECC_CORRECTION. */ +typedef volatile struct ALT_NAND_CFG_ECC_CORRECTION_s ALT_NAND_CFG_ECC_CORRECTION_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_ECC_CORRECTION register from the beginning of the component. */ +#define ALT_NAND_CFG_ECC_CORRECTION_OFST 0x1b0 + +/* + * Register : read_mode + * + * The type of read sequence that the controller will follow for pipe read + * commands. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [3:0] | RW | 0x0 | ALT_NAND_CFG_RD_MOD_VALUE + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The values in the field should be as follows[list] [*]4'h0 - This value informs + * the controller that the pipe read sequence to follow is of a normal read. For + * 512 byte page devices, Normal read sequence is, C00, Address, Data, ..... For + * devices with page size greater that 512 bytes, the sequence is, C00, Address, + * C30, Data..... [*]4'h1 - This value informs the controller that the pipe read + * sequence to follow is of a Cache Read with the following sequence, C00, Address, + * C30, C31, Data, C31, Data, ....., C3F, Data. [*]4'h2 - This value informs the + * controller that the pipe read sequence to follow is of a Cache Read with the + * following sequence, C00, Address, C31, Data, Data, ....., C34. [*]4'h3 - This + * value informs the controller that the pipe read sequence to follow is of a 'N' + * Plane Read with the following sequence, C00, Address, C00, Address, C30, Data, + * C06, Address, CE0, Data..... [*]4'h4 - This value informs the controller that + * the pipe read sequence to follow is of a 'N' Plane Read with the following + * sequence, C60, Address, C60, Address, C30, C00, Address, C05, Address, CE0, + * Data, C00, Address, C05, Address, CE0, Data..... [*]4'h5 - This value informs + * the controller that the pipe read sequence to follow is of a 'N' Plane Cache + * Read with the following sequence, C60, Address, C60, Address, C30, C31, C00, + * Address, C05, Address, CE0, Data, C00, Address, C05, Address, CE0, Data, ....., + * C3F, C00, Address, C05, Address, CE0, Data, C00, Address, C05, Address, CE0, + * Data [*]4'h6 - This value informs the controller that the pipe read sequence to + * follow is of a 'N' Plane Read with the following sequence, C00, Address, C32, + * .., C00, Address, C30, C06, Address, CE0, Data, C06, Address, CE0, Data,.... + * [*]4'h7 - This value informs the controller that the pipe read sequence to + * follow is of a 'N' Plane Cache Read with the following sequence, C00, Address, + * C32,..., C00, Address, C30, C31,C06, Address, CE0, Data, C31, C06, Address, CE0, + * Data, C3F, C06, Address, CE0, Data.... [*]4'h8 - This value informs the + * controller that the pipe read sequence to follow is of a 'N' Plane Cache Read + * with the following sequence, C60, Address, C60, Address, C33, C31, C00, Address, + * C05, Address, CE0, Data, C00, Address, C05, Address, CE0, Data, ....., C3F, C00, + * Address, C05, Address, CE0, Data, C00, Address, C05, Address, CE0, Data [*]4'h9 + * - 4'h15 - Reserved. [/list] ..... indicates that the previous sequence is + * repeated till the last page. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RD_MOD_VALUE register field. */ +#define ALT_NAND_CFG_RD_MOD_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RD_MOD_VALUE register field. */ +#define ALT_NAND_CFG_RD_MOD_VALUE_MSB 3 +/* The width in bits of the ALT_NAND_CFG_RD_MOD_VALUE register field. */ +#define ALT_NAND_CFG_RD_MOD_VALUE_WIDTH 4 +/* The mask used to set the ALT_NAND_CFG_RD_MOD_VALUE register field value. */ +#define ALT_NAND_CFG_RD_MOD_VALUE_SET_MSK 0x0000000f +/* The mask used to clear the ALT_NAND_CFG_RD_MOD_VALUE register field value. */ +#define ALT_NAND_CFG_RD_MOD_VALUE_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_NAND_CFG_RD_MOD_VALUE register field. */ +#define ALT_NAND_CFG_RD_MOD_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_RD_MOD_VALUE field value from a register. */ +#define ALT_NAND_CFG_RD_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_NAND_CFG_RD_MOD_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_RD_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_RD_MOD. + */ +struct ALT_NAND_CFG_RD_MOD_s +{ + uint32_t value : 4; /* ALT_NAND_CFG_RD_MOD_VALUE */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_RD_MOD. */ +typedef volatile struct ALT_NAND_CFG_RD_MOD_s ALT_NAND_CFG_RD_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_RD_MOD register from the beginning of the component. */ +#define ALT_NAND_CFG_RD_MOD_OFST 0x1c0 + +/* + * Register : write_mode + * + * The type of write sequence that the controller will follow for pipe write + * commands. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [3:0] | RW | 0x0 | ALT_NAND_CFG_WR_MOD_VALUE + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The values in the field should be as follows[list] [*]4'h0 - This value informs + * the controller that the pipe write sequence to follow is of a normal write with + * the following sequence, C80, Address, Data, C10..... [*]4'h1 - This value + * informs the controller that the pipe write sequence to follow is of a Cache + * Program with the following sequence, C80, Address, Data, C15, ....., C80, + * Address, Data, C10. [*]4'h2 - This value informs the controller that the pipe + * write sequence to follow is of a Two/Four Plane Program with the following + * sequence, C80, Address, Data, C11, C81, Address, Data, C10..... [*]4'h3 - This + * value informs the controller that the pipe write sequence to follow is of a 'N' + * Plane Program with the following sequence, C80, Address, Data, C11, C80, + * Address, Data, C10..... [*]4'h4 - This value informs the controller that the + * pipe write sequence to follow is of a 'N' Plane Cache Program with the following + * sequence, C80, Address, Data, C11, C80, Address, Data, C15.....C80, Address, + * Data, C11, C80, Address, Data, C10. [*]4'h5 - This value informs the controller + * that the pipe write sequence to follow is of a 'N' Plane Cache Program with the + * following sequence, C80, Address, Data, C11, C81, Address, Data, C15.....C80, + * Address, Data, C11, C81, Address, Data, C10. [*]4'h6 - 4'h15 - Reserved. [/list] + * ..... indicates that the previous sequence is repeated till the last page. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WR_MOD_VALUE register field. */ +#define ALT_NAND_CFG_WR_MOD_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WR_MOD_VALUE register field. */ +#define ALT_NAND_CFG_WR_MOD_VALUE_MSB 3 +/* The width in bits of the ALT_NAND_CFG_WR_MOD_VALUE register field. */ +#define ALT_NAND_CFG_WR_MOD_VALUE_WIDTH 4 +/* The mask used to set the ALT_NAND_CFG_WR_MOD_VALUE register field value. */ +#define ALT_NAND_CFG_WR_MOD_VALUE_SET_MSK 0x0000000f +/* The mask used to clear the ALT_NAND_CFG_WR_MOD_VALUE register field value. */ +#define ALT_NAND_CFG_WR_MOD_VALUE_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_NAND_CFG_WR_MOD_VALUE register field. */ +#define ALT_NAND_CFG_WR_MOD_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_WR_MOD_VALUE field value from a register. */ +#define ALT_NAND_CFG_WR_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_NAND_CFG_WR_MOD_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_WR_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_WR_MOD. + */ +struct ALT_NAND_CFG_WR_MOD_s +{ + uint32_t value : 4; /* ALT_NAND_CFG_WR_MOD_VALUE */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_WR_MOD. */ +typedef volatile struct ALT_NAND_CFG_WR_MOD_s ALT_NAND_CFG_WR_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_WR_MOD register from the beginning of the component. */ +#define ALT_NAND_CFG_WR_MOD_OFST 0x1d0 + +/* + * Register : copyback_mode + * + * The type of copyback sequence that the controller will follow. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [3:0] | RW | 0x0 | ALT_NAND_CFG_COPYBACK_MOD_VALUE + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The values in the field should be as follows[list] [*]4'h0 - This value informs + * the controller that the copyback sequence to follow is, C00, Address, C35, C85, + * Address, C10 [*]4'h1 - This value informs the controller that the copyback + * sequence to follow is, C00, Address, C30, C8C, Address, C10 [*]4'h2 - This value + * informs the controller that the copyback sequence to follow is, C00, Address, + * C8A, Address, C10 [*]4'h3 - This value informs the controller that the copyback + * sequence to follow is of a four plane copyback sequence, C00, Address, C03, + * Address, C03, Address, C03, Address, C8A, Address, C11, C8A, Address, C11, C8A, + * Address, C11, C8A, Address, C10. [*]4'h4 - This value informs the controller + * that the copyback sequence to follow is of a two plane copyback sequence, C00, + * Address, C35, C00, Address, C35, C85, Address, C11, C81, Address, C10. [*]4'h5 - + * This value informs the controller that the copyback sequence to follow is of a + * two plane copyback sequence, C60, Address, C60, Address, C35, C85, Address, C11, + * C81, Address, C10. [*]4'h6 - This value informs the controller that the copyback + * sequence to follow is of a two plane copyback sequence, C00, Address, C00, + * Address, C35, C85, Address, C11, C80, Address, C10. [*]4'h7 - This value informs + * the controller that the copyback sequence to follow is of a two plane copyback + * sequence, C60, Address, C60, Address, C30, C8C, Address, C11, C8C, Address, C10. + * [*]4'h8 - 4'h15 - Reserved.[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */ +#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */ +#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_MSB 3 +/* The width in bits of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */ +#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_WIDTH 4 +/* The mask used to set the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field value. */ +#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET_MSK 0x0000000f +/* The mask used to clear the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field value. */ +#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_NAND_CFG_COPYBACK_MOD_VALUE register field. */ +#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_COPYBACK_MOD_VALUE field value from a register. */ +#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_NAND_CFG_COPYBACK_MOD_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_COPYBACK_MOD. + */ +struct ALT_NAND_CFG_COPYBACK_MOD_s +{ + uint32_t value : 4; /* ALT_NAND_CFG_COPYBACK_MOD_VALUE */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_COPYBACK_MOD. */ +typedef volatile struct ALT_NAND_CFG_COPYBACK_MOD_s ALT_NAND_CFG_COPYBACK_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_COPYBACK_MOD register from the beginning of the component. */ +#define ALT_NAND_CFG_COPYBACK_MOD_OFST 0x1e0 + +/* + * Register : rdwr_en_lo_cnt + * + * Read/Write Enable low pulse width + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [4:0] | RW | 0x12 | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Number of nand_mp_clk cycles that read or write enable will kept low to meet the + * min Trp/Twp parameter of the device. The value in this register plus + * rdwr_en_hi_cnt register value should meet the min cycle time of the device + * connected. The default value is calculated assuming the max nand_mp_clk time + * period of 4ns to work with ONFI Mode 0 mode of 100ns device cycle time. This + * assumes a 1x/4x clocking scheme. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4 +/* The width in bits of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5 +/* The mask used to set the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f +/* The mask used to clear the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12 +/* Extracts the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE field value from a register. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_RDWR_EN_LO_CNT. + */ +struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s +{ + uint32_t value : 5; /* ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_RDWR_EN_LO_CNT. */ +typedef volatile struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s ALT_NAND_CFG_RDWR_EN_LO_CNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_RDWR_EN_LO_CNT register from the beginning of the component. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0 + +/* + * Register : rdwr_en_hi_cnt + * + * Read/Write Enable high pulse width + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [4:0] | RW | 0xc | ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Number of nand_mp_clk cycles that read or write enable will kept high to meet + * the min Treh/Tweh parameter of the device. The value in this register plus + * rdwr_en_lo_cnt register value should meet the min cycle time of the device + * connected. The default value is calculated assuming the max nand_mp_clk time + * period of 4ns to work with ONFI Mode 0 mode of 100ns device cycle time. This + * assumes a 1x/4x clocking scheme. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_MSB 4 +/* The width in bits of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_WIDTH 5 +/* The mask used to set the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET_MSK 0x0000001f +/* The mask used to clear the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_RESET 0xc +/* Extracts the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE field value from a register. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_RDWR_EN_HI_CNT. + */ +struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s +{ + uint32_t value : 5; /* ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_RDWR_EN_HI_CNT. */ +typedef volatile struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s ALT_NAND_CFG_RDWR_EN_HI_CNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_RDWR_EN_HI_CNT register from the beginning of the component. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST 0x200 + +/* + * Register : max_rd_delay + * + * Max round trip read data delay for data capture + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [3:0] | RW | 0x0 | ALT_NAND_CFG_MAX_RD_DELAY_VALUE + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Number of nand_mp_clk cycles after generation of feedback nand_mp_clk pulse when + * it is safe to synchronize received data to nand_mp_clk domain. Data should have + * been registered with nand_mp_clk and stable by the time max_rd_delay cycles has + * elapsed. A default value of zero will mean a value of nand_mp_clk multiple minus + * one. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB 3 +/* The width in bits of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH 4 +/* The mask used to set the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK 0x0000000f +/* The mask used to clear the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_MAX_RD_DELAY_VALUE field value from a register. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_MAX_RD_DELAY. + */ +struct ALT_NAND_CFG_MAX_RD_DELAY_s +{ + uint32_t value : 4; /* ALT_NAND_CFG_MAX_RD_DELAY_VALUE */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_MAX_RD_DELAY. */ +typedef volatile struct ALT_NAND_CFG_MAX_RD_DELAY_s ALT_NAND_CFG_MAX_RD_DELAY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_MAX_RD_DELAY register from the beginning of the component. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_OFST 0x210 + +/* + * Register : cs_setup_cnt + * + * Chip select setup time + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [4:0] | RW | 0x3 | ALT_NAND_CFG_CS_SETUP_CNT_VALUE + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Number of nand_mp_clk cycles required for meeting chip select setup time. This + * register refers to device timing parameter Tcs. The value in this registers + * reflects the extra setup cycles for chip select before read/write enable signal + * is set low. The default value is calculated for ONFI Timing mode 0 Tcs = 70ns + * and maximum nand_mp_clk period of 4ns for 1x/4x clock multiple for 16ns cycle + * time device. Please refer to Figure 3.3 for the relationship between the + * cs_setup_cnt and rdwr_en_lo_cnt values. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4 +/* The width in bits of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5 +/* The mask used to set the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f +/* The mask used to clear the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3 +/* Extracts the ALT_NAND_CFG_CS_SETUP_CNT_VALUE field value from a register. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_CS_SETUP_CNT. + */ +struct ALT_NAND_CFG_CS_SETUP_CNT_s +{ + uint32_t value : 5; /* ALT_NAND_CFG_CS_SETUP_CNT_VALUE */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_CS_SETUP_CNT. */ +typedef volatile struct ALT_NAND_CFG_CS_SETUP_CNT_s ALT_NAND_CFG_CS_SETUP_CNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_CS_SETUP_CNT register from the beginning of the component. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220 + +/* + * Register : spare_area_skip_bytes + * + * Spare area skip bytes + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [5:0] | RW | 0x0 | ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Number of bytes to skip from start of spare area before last ECC sector data + * starts. The bytes will be written with the value programmed in the + * spare_area_marker register. This register could be potentially used to preserve + * the bad block marker in the spare area by marking it good. The default value is + * zero which means no bytes will be skipped and last ECC sector will start from + * the beginning of spare area. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_MSB 5 +/* The width in bits of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_WIDTH 6 +/* The mask used to set the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET_MSK 0x0000003f +/* The mask used to clear the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE field value from a register. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES. + */ +struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s +{ + uint32_t value : 6; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES. */ +typedef volatile struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register from the beginning of the component. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST 0x230 + +/* + * Register : spare_area_marker + * + * Spare area marker value + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------------- + * [15:0] | RW | 0xffff | ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The value that will be written in the spare area skip bytes. This value will be + * used by controller while in the MAIN mode of data transfer. Only the least- + * significant 8 bits of the field value are used. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_RESET 0xffff +/* Extracts the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE field value from a register. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_SPARE_AREA_MARKER. + */ +struct ALT_NAND_CFG_SPARE_AREA_MARKER_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_SPARE_AREA_MARKER. */ +typedef volatile struct ALT_NAND_CFG_SPARE_AREA_MARKER_s ALT_NAND_CFG_SPARE_AREA_MARKER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_SPARE_AREA_MARKER register from the beginning of the component. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_OFST 0x240 + +/* + * Register : devices_connected + * + * Number of Devices connected on one bank + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------- + * [2:0] | RW | 0x0 | ALT_NAND_CFG_DEVICES_CONNECTED_VALUE + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Indicates the number of devices connected to a bank. At reset, the value loaded + * is the maximum possible devices that could be connected in this configuration. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_MSB 2 +/* The width in bits of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_WIDTH 3 +/* The mask used to set the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET_MSK 0x00000007 +/* The mask used to clear the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE field value from a register. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET(value) (((value) << 0) & 0x00000007) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_DEVICES_CONNECTED. + */ +struct ALT_NAND_CFG_DEVICES_CONNECTED_s +{ + uint32_t value : 3; /* ALT_NAND_CFG_DEVICES_CONNECTED_VALUE */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_DEVICES_CONNECTED. */ +typedef volatile struct ALT_NAND_CFG_DEVICES_CONNECTED_s ALT_NAND_CFG_DEVICES_CONNECTED_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_DEVICES_CONNECTED register from the beginning of the component. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_OFST 0x250 + +/* + * Register : die_mask + * + * Indicates the die differentiator in case of NAND devices with stacked dies. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [7:0] | RW | 0x0 | ALT_NAND_CFG_DIE_MSK_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The die_mask register information will be used for devices having address + * restrictions. For example, in certain Samsung devices, when the first address in + * a two-plane command is being sent, it is expected that the address is all zeros. + * But if the NAND device internally has multiple dies stacked, the die information + * (MSB of final row address) has to be sent. The value programmed in this register + * will be used to mask the address while sending out the last row address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */ +#define ALT_NAND_CFG_DIE_MSK_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */ +#define ALT_NAND_CFG_DIE_MSK_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */ +#define ALT_NAND_CFG_DIE_MSK_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_CFG_DIE_MSK_VALUE register field value. */ +#define ALT_NAND_CFG_DIE_MSK_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_CFG_DIE_MSK_VALUE register field value. */ +#define ALT_NAND_CFG_DIE_MSK_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_CFG_DIE_MSK_VALUE register field. */ +#define ALT_NAND_CFG_DIE_MSK_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_CFG_DIE_MSK_VALUE field value from a register. */ +#define ALT_NAND_CFG_DIE_MSK_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_CFG_DIE_MSK_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_DIE_MSK_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_DIE_MSK. + */ +struct ALT_NAND_CFG_DIE_MSK_s +{ + uint32_t value : 8; /* ALT_NAND_CFG_DIE_MSK_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_DIE_MSK. */ +typedef volatile struct ALT_NAND_CFG_DIE_MSK_s ALT_NAND_CFG_DIE_MSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_DIE_MSK register from the beginning of the component. */ +#define ALT_NAND_CFG_DIE_MSK_OFST 0x260 + +/* + * Register : first_block_of_next_plane + * + * The starting block address of the next plane in a multi plane device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------------- + * [15:0] | RW | 0x1 | ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * This values informs the controller of the plane structure of the device. In case + * the device is a multi plane device and the value here is 1, the controller + * understands that the next plane starts from Block number 1 and in conjunction + * with the number of planes parameter can decide upon the distribution of blocks + * in a plane in the device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_RESET 0x1 +/* Extracts the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE field value from a register. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE. + */ +struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE. */ +typedef volatile struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register from the beginning of the component. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST 0x270 + +/* + * Register : write_protect + * + * This register is used to control the assertion/de-assertion of the WP# pin to + * the device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | RW | 0x1 | ALT_NAND_CFG_WR_PROTECT_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * When the controller is in reset, the WP# pin is always asserted to the device. + * Once the reset is removed, the WP# is de-asserted. The software will then have + * to come and program this bit to assert/de-assert the same. [list][*]1 - Write + * protect de-assert [*]0 - Write protect assert[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */ +#define ALT_NAND_CFG_WR_PROTECT_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */ +#define ALT_NAND_CFG_WR_PROTECT_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */ +#define ALT_NAND_CFG_WR_PROTECT_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_CFG_WR_PROTECT_FLAG register field value. */ +#define ALT_NAND_CFG_WR_PROTECT_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_CFG_WR_PROTECT_FLAG register field value. */ +#define ALT_NAND_CFG_WR_PROTECT_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_CFG_WR_PROTECT_FLAG register field. */ +#define ALT_NAND_CFG_WR_PROTECT_FLAG_RESET 0x1 +/* Extracts the ALT_NAND_CFG_WR_PROTECT_FLAG field value from a register. */ +#define ALT_NAND_CFG_WR_PROTECT_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_CFG_WR_PROTECT_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_CFG_WR_PROTECT_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_WR_PROTECT. + */ +struct ALT_NAND_CFG_WR_PROTECT_s +{ + uint32_t flag : 1; /* ALT_NAND_CFG_WR_PROTECT_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_WR_PROTECT. */ +typedef volatile struct ALT_NAND_CFG_WR_PROTECT_s ALT_NAND_CFG_WR_PROTECT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_WR_PROTECT register from the beginning of the component. */ +#define ALT_NAND_CFG_WR_PROTECT_OFST 0x280 + +/* + * Register : re_2_re + * + * Timing parameter between re high to re low (Trhz) for the next bank + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [5:0] | RW | 0x32 | ALT_NAND_CFG_RE_2_RE_VALUE + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Signifies the number of bus interface nand_mp_clk clocks that should be + * introduced between read enable going high to a bank to the read enable going low + * to the next bank. The number of clocks is the function of device parameter Trhz + * and controller clock frequency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */ +#define ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */ +#define ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5 +/* The width in bits of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */ +#define ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6 +/* The mask used to set the ALT_NAND_CFG_RE_2_RE_VALUE register field value. */ +#define ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f +/* The mask used to clear the ALT_NAND_CFG_RE_2_RE_VALUE register field value. */ +#define ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */ +#define ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32 +/* Extracts the ALT_NAND_CFG_RE_2_RE_VALUE field value from a register. */ +#define ALT_NAND_CFG_RE_2_RE_VALUE_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_NAND_CFG_RE_2_RE_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_RE_2_RE_VALUE_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_RE_2_RE. + */ +struct ALT_NAND_CFG_RE_2_RE_s +{ + uint32_t value : 6; /* ALT_NAND_CFG_RE_2_RE_VALUE */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_RE_2_RE. */ +typedef volatile struct ALT_NAND_CFG_RE_2_RE_s ALT_NAND_CFG_RE_2_RE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_RE_2_RE register from the beginning of the component. */ +#define ALT_NAND_CFG_RE_2_RE_OFST 0x290 + +/* + * Register : por_reset_count + * + * The number of cycles the controller waits after reset to issue the first RESET + * command to the device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------- + * [15:0] | RW | 0x13b | ALT_NAND_CFG_POR_RST_COUNT_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The controller waits for this number of cycles before issuing the first RESET + * command to the device. The number in this register is multiplied internally by + * 16 in the controller to form the final reset wait count. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */ +#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */ +#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */ +#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value. */ +#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value. */ +#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field. */ +#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_RESET 0x13b +/* Extracts the ALT_NAND_CFG_POR_RST_COUNT_VALUE field value from a register. */ +#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_POR_RST_COUNT. + */ +struct ALT_NAND_CFG_POR_RST_COUNT_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_POR_RST_COUNT_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_POR_RST_COUNT. */ +typedef volatile struct ALT_NAND_CFG_POR_RST_COUNT_s ALT_NAND_CFG_POR_RST_COUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_POR_RST_COUNT register from the beginning of the component. */ +#define ALT_NAND_CFG_POR_RST_COUNT_OFST 0x2a0 + +/* + * Register : watchdog_reset_count + * + * The number of cycles the controller waits before flagging a watchdog timeout + * interrupt. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:-------------------------------- + * [15:0] | RW | 0x5b9a | ALT_NAND_CFG_WD_RST_COUNT_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The controller waits for this number of cycles before issuing a watchdog timeout + * interrupt. The value in this register is multiplied internally by 32 in the + * controller to form the final watchdog counter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */ +#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */ +#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */ +#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field value. */ +#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field value. */ +#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_CFG_WD_RST_COUNT_VALUE register field. */ +#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_RESET 0x5b9a +/* Extracts the ALT_NAND_CFG_WD_RST_COUNT_VALUE field value from a register. */ +#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_CFG_WD_RST_COUNT_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_CFG_WD_RST_COUNT. + */ +struct ALT_NAND_CFG_WD_RST_COUNT_s +{ + uint32_t value : 16; /* ALT_NAND_CFG_WD_RST_COUNT_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_CFG_WD_RST_COUNT. */ +typedef volatile struct ALT_NAND_CFG_WD_RST_COUNT_s ALT_NAND_CFG_WD_RST_COUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_CFG_WD_RST_COUNT register from the beginning of the component. */ +#define ALT_NAND_CFG_WD_RST_COUNT_OFST 0x2b0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_NAND_CFG. + */ +struct ALT_NAND_CFG_s +{ + volatile ALT_NAND_CFG_DEVICE_RST_t device_reset; /* ALT_NAND_CFG_DEVICE_RST */ + volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_TFR_SPARE_REG_t transfer_spare_reg; /* ALT_NAND_CFG_TFR_SPARE_REG */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_LD_WAIT_CNT_t load_wait_cnt; /* ALT_NAND_CFG_LD_WAIT_CNT */ + volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_PROGRAM_WAIT_CNT_t program_wait_cnt; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_ERASE_WAIT_CNT_t erase_wait_cnt; /* ALT_NAND_CFG_ERASE_WAIT_CNT */ + volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_INT_MON_CYCCNT_t int_mon_cyccnt; /* ALT_NAND_CFG_INT_MON_CYCCNT */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_RB_PIN_END_t rb_pin_enabled; /* ALT_NAND_CFG_RB_PIN_END */ + volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_MULTIPLANE_OP_t multiplane_operation; /* ALT_NAND_CFG_MULTIPLANE_OP */ + volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_MULTIPLANE_RD_EN_t multiplane_read_enable; /* ALT_NAND_CFG_MULTIPLANE_RD_EN */ + volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_COPYBACK_DIS_t copyback_disable; /* ALT_NAND_CFG_COPYBACK_DIS */ + volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_CACHE_WR_EN_t cache_write_enable; /* ALT_NAND_CFG_CACHE_WR_EN */ + volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_CACHE_RD_EN_t cache_read_enable; /* ALT_NAND_CFG_CACHE_RD_EN */ + volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_PREFETCH_MOD_t prefetch_mode; /* ALT_NAND_CFG_PREFETCH_MOD */ + volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_CHIP_EN_DONT_CARE_t chip_enable_dont_care; /* ALT_NAND_CFG_CHIP_EN_DONT_CARE */ + volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_ECC_EN_t ecc_enable; /* ALT_NAND_CFG_ECC_EN */ + volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_GLOB_INT_EN_t global_int_enable; /* ALT_NAND_CFG_GLOB_INT_EN */ + volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t twhr2_and_we_2_re; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE */ + volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t tcwaw_and_addr_2_data; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA */ + volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_RE_2_WE_t re_2_we; /* ALT_NAND_CFG_RE_2_WE */ + volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_ACC_CLKS_t acc_clks; /* ALT_NAND_CFG_ACC_CLKS */ + volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_NUMBER_OF_PLANES_t number_of_planes; /* ALT_NAND_CFG_NUMBER_OF_PLANES */ + volatile uint32_t _pad_0x144_0x14f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_PAGES_PER_BLOCK_t pages_per_block; /* ALT_NAND_CFG_PAGES_PER_BLOCK */ + volatile uint32_t _pad_0x154_0x15f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_DEVICE_WIDTH_t device_width; /* ALT_NAND_CFG_DEVICE_WIDTH */ + volatile uint32_t _pad_0x164_0x16f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t device_main_area_size; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE */ + volatile uint32_t _pad_0x174_0x17f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t device_spare_area_size; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE */ + volatile uint32_t _pad_0x184_0x18f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t two_row_addr_cycles; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES */ + volatile uint32_t _pad_0x194_0x19f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t multiplane_addr_restrict; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT */ + volatile uint32_t _pad_0x1a4_0x1af[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_ECC_CORRECTION_t ecc_correction; /* ALT_NAND_CFG_ECC_CORRECTION */ + volatile uint32_t _pad_0x1b4_0x1bf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_RD_MOD_t read_mode; /* ALT_NAND_CFG_RD_MOD */ + volatile uint32_t _pad_0x1c4_0x1cf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_WR_MOD_t write_mode; /* ALT_NAND_CFG_WR_MOD */ + volatile uint32_t _pad_0x1d4_0x1df[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_COPYBACK_MOD_t copyback_mode; /* ALT_NAND_CFG_COPYBACK_MOD */ + volatile uint32_t _pad_0x1e4_0x1ef[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_RDWR_EN_LO_CNT_t rdwr_en_lo_cnt; /* ALT_NAND_CFG_RDWR_EN_LO_CNT */ + volatile uint32_t _pad_0x1f4_0x1ff[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_RDWR_EN_HI_CNT_t rdwr_en_hi_cnt; /* ALT_NAND_CFG_RDWR_EN_HI_CNT */ + volatile uint32_t _pad_0x204_0x20f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_MAX_RD_DELAY_t max_rd_delay; /* ALT_NAND_CFG_MAX_RD_DELAY */ + volatile uint32_t _pad_0x214_0x21f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_CS_SETUP_CNT_t cs_setup_cnt; /* ALT_NAND_CFG_CS_SETUP_CNT */ + volatile uint32_t _pad_0x224_0x22f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t spare_area_skip_bytes; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES */ + volatile uint32_t _pad_0x234_0x23f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_SPARE_AREA_MARKER_t spare_area_marker; /* ALT_NAND_CFG_SPARE_AREA_MARKER */ + volatile uint32_t _pad_0x244_0x24f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_DEVICES_CONNECTED_t devices_connected; /* ALT_NAND_CFG_DEVICES_CONNECTED */ + volatile uint32_t _pad_0x254_0x25f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_DIE_MSK_t die_mask; /* ALT_NAND_CFG_DIE_MSK */ + volatile uint32_t _pad_0x264_0x26f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t first_block_of_next_plane; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE */ + volatile uint32_t _pad_0x274_0x27f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_WR_PROTECT_t write_protect; /* ALT_NAND_CFG_WR_PROTECT */ + volatile uint32_t _pad_0x284_0x28f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_RE_2_RE_t re_2_re; /* ALT_NAND_CFG_RE_2_RE */ + volatile uint32_t _pad_0x294_0x29f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_POR_RST_COUNT_t por_reset_count; /* ALT_NAND_CFG_POR_RST_COUNT */ + volatile uint32_t _pad_0x2a4_0x2af[3]; /* *UNDEFINED* */ + volatile ALT_NAND_CFG_WD_RST_COUNT_t watchdog_reset_count; /* ALT_NAND_CFG_WD_RST_COUNT */ +}; + +/* The typedef declaration for register group ALT_NAND_CFG. */ +typedef volatile struct ALT_NAND_CFG_s ALT_NAND_CFG_t; +/* The struct declaration for the raw register contents of register group ALT_NAND_CFG. */ +struct ALT_NAND_CFG_raw_s +{ + volatile uint32_t device_reset; /* ALT_NAND_CFG_DEVICE_RST */ + volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */ + volatile uint32_t transfer_spare_reg; /* ALT_NAND_CFG_TFR_SPARE_REG */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile uint32_t load_wait_cnt; /* ALT_NAND_CFG_LD_WAIT_CNT */ + volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */ + volatile uint32_t program_wait_cnt; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile uint32_t erase_wait_cnt; /* ALT_NAND_CFG_ERASE_WAIT_CNT */ + volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */ + volatile uint32_t int_mon_cyccnt; /* ALT_NAND_CFG_INT_MON_CYCCNT */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile uint32_t rb_pin_enabled; /* ALT_NAND_CFG_RB_PIN_END */ + volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */ + volatile uint32_t multiplane_operation; /* ALT_NAND_CFG_MULTIPLANE_OP */ + volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */ + volatile uint32_t multiplane_read_enable; /* ALT_NAND_CFG_MULTIPLANE_RD_EN */ + volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */ + volatile uint32_t copyback_disable; /* ALT_NAND_CFG_COPYBACK_DIS */ + volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */ + volatile uint32_t cache_write_enable; /* ALT_NAND_CFG_CACHE_WR_EN */ + volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */ + volatile uint32_t cache_read_enable; /* ALT_NAND_CFG_CACHE_RD_EN */ + volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */ + volatile uint32_t prefetch_mode; /* ALT_NAND_CFG_PREFETCH_MOD */ + volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */ + volatile uint32_t chip_enable_dont_care; /* ALT_NAND_CFG_CHIP_EN_DONT_CARE */ + volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */ + volatile uint32_t ecc_enable; /* ALT_NAND_CFG_ECC_EN */ + volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */ + volatile uint32_t global_int_enable; /* ALT_NAND_CFG_GLOB_INT_EN */ + volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */ + volatile uint32_t twhr2_and_we_2_re; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE */ + volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */ + volatile uint32_t tcwaw_and_addr_2_data; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA */ + volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */ + volatile uint32_t re_2_we; /* ALT_NAND_CFG_RE_2_WE */ + volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */ + volatile uint32_t acc_clks; /* ALT_NAND_CFG_ACC_CLKS */ + volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */ + volatile uint32_t number_of_planes; /* ALT_NAND_CFG_NUMBER_OF_PLANES */ + volatile uint32_t _pad_0x144_0x14f[3]; /* *UNDEFINED* */ + volatile uint32_t pages_per_block; /* ALT_NAND_CFG_PAGES_PER_BLOCK */ + volatile uint32_t _pad_0x154_0x15f[3]; /* *UNDEFINED* */ + volatile uint32_t device_width; /* ALT_NAND_CFG_DEVICE_WIDTH */ + volatile uint32_t _pad_0x164_0x16f[3]; /* *UNDEFINED* */ + volatile uint32_t device_main_area_size; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE */ + volatile uint32_t _pad_0x174_0x17f[3]; /* *UNDEFINED* */ + volatile uint32_t device_spare_area_size; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE */ + volatile uint32_t _pad_0x184_0x18f[3]; /* *UNDEFINED* */ + volatile uint32_t two_row_addr_cycles; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES */ + volatile uint32_t _pad_0x194_0x19f[3]; /* *UNDEFINED* */ + volatile uint32_t multiplane_addr_restrict; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT */ + volatile uint32_t _pad_0x1a4_0x1af[3]; /* *UNDEFINED* */ + volatile uint32_t ecc_correction; /* ALT_NAND_CFG_ECC_CORRECTION */ + volatile uint32_t _pad_0x1b4_0x1bf[3]; /* *UNDEFINED* */ + volatile uint32_t read_mode; /* ALT_NAND_CFG_RD_MOD */ + volatile uint32_t _pad_0x1c4_0x1cf[3]; /* *UNDEFINED* */ + volatile uint32_t write_mode; /* ALT_NAND_CFG_WR_MOD */ + volatile uint32_t _pad_0x1d4_0x1df[3]; /* *UNDEFINED* */ + volatile uint32_t copyback_mode; /* ALT_NAND_CFG_COPYBACK_MOD */ + volatile uint32_t _pad_0x1e4_0x1ef[3]; /* *UNDEFINED* */ + volatile uint32_t rdwr_en_lo_cnt; /* ALT_NAND_CFG_RDWR_EN_LO_CNT */ + volatile uint32_t _pad_0x1f4_0x1ff[3]; /* *UNDEFINED* */ + volatile uint32_t rdwr_en_hi_cnt; /* ALT_NAND_CFG_RDWR_EN_HI_CNT */ + volatile uint32_t _pad_0x204_0x20f[3]; /* *UNDEFINED* */ + volatile uint32_t max_rd_delay; /* ALT_NAND_CFG_MAX_RD_DELAY */ + volatile uint32_t _pad_0x214_0x21f[3]; /* *UNDEFINED* */ + volatile uint32_t cs_setup_cnt; /* ALT_NAND_CFG_CS_SETUP_CNT */ + volatile uint32_t _pad_0x224_0x22f[3]; /* *UNDEFINED* */ + volatile uint32_t spare_area_skip_bytes; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES */ + volatile uint32_t _pad_0x234_0x23f[3]; /* *UNDEFINED* */ + volatile uint32_t spare_area_marker; /* ALT_NAND_CFG_SPARE_AREA_MARKER */ + volatile uint32_t _pad_0x244_0x24f[3]; /* *UNDEFINED* */ + volatile uint32_t devices_connected; /* ALT_NAND_CFG_DEVICES_CONNECTED */ + volatile uint32_t _pad_0x254_0x25f[3]; /* *UNDEFINED* */ + volatile uint32_t die_mask; /* ALT_NAND_CFG_DIE_MSK */ + volatile uint32_t _pad_0x264_0x26f[3]; /* *UNDEFINED* */ + volatile uint32_t first_block_of_next_plane; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE */ + volatile uint32_t _pad_0x274_0x27f[3]; /* *UNDEFINED* */ + volatile uint32_t write_protect; /* ALT_NAND_CFG_WR_PROTECT */ + volatile uint32_t _pad_0x284_0x28f[3]; /* *UNDEFINED* */ + volatile uint32_t re_2_re; /* ALT_NAND_CFG_RE_2_RE */ + volatile uint32_t _pad_0x294_0x29f[3]; /* *UNDEFINED* */ + volatile uint32_t por_reset_count; /* ALT_NAND_CFG_POR_RST_COUNT */ + volatile uint32_t _pad_0x2a4_0x2af[3]; /* *UNDEFINED* */ + volatile uint32_t watchdog_reset_count; /* ALT_NAND_CFG_WD_RST_COUNT */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_NAND_CFG. */ +typedef volatile struct ALT_NAND_CFG_raw_s ALT_NAND_CFG_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Device parameters - ALT_NAND_PARAM + * Device parameters + * + * Controller reads device parameters after initialization and stores in the + * following registers for software + * + */ +/* + * Register : manufacturer_id + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------- + * [7:0] | RW | 0x0 | ALT_NAND_PARAM_MANUFACTURER_ID_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Manufacturer ID + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE field value from a register. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_MANUFACTURER_ID. + */ +struct ALT_NAND_PARAM_MANUFACTURER_ID_s +{ + uint32_t value : 8; /* ALT_NAND_PARAM_MANUFACTURER_ID_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_MANUFACTURER_ID. */ +typedef volatile struct ALT_NAND_PARAM_MANUFACTURER_ID_s ALT_NAND_PARAM_MANUFACTURER_ID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_MANUFACTURER_ID register from the beginning of the component. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_OFST 0x0 + +/* + * Register : device_id + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_ID_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Device ID. This register is updated only for Legacy NAND devices. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_ID_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_ID_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_ID_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_PARAM_DEVICE_ID_VALUE register field value. */ +#define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_PARAM_DEVICE_ID_VALUE register field value. */ +#define ALT_NAND_PARAM_DEVICE_ID_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_ID_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_DEVICE_ID_VALUE field value from a register. */ +#define ALT_NAND_PARAM_DEVICE_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_PARAM_DEVICE_ID_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_DEVICE_ID. + */ +struct ALT_NAND_PARAM_DEVICE_ID_s +{ + const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_ID_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_DEVICE_ID. */ +typedef volatile struct ALT_NAND_PARAM_DEVICE_ID_s ALT_NAND_PARAM_DEVICE_ID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_DEVICE_ID register from the beginning of the component. */ +#define ALT_NAND_PARAM_DEVICE_ID_OFST 0x10 + +/* + * Register : device_param_0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * 3rd byte relating to Device Signature. This register is updated only for Legacy + * NAND devices. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE field value from a register. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_0. + */ +struct ALT_NAND_PARAM_DEVICE_PARAM_0_s +{ + const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_0. */ +typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_0_s ALT_NAND_PARAM_DEVICE_PARAM_0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_0 register from the beginning of the component. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_OFST 0x20 + +/* + * Register : device_param_1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * 4th byte relating to Device Signature. This register is updated only for Legacy + * NAND devices. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE field value from a register. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_1. + */ +struct ALT_NAND_PARAM_DEVICE_PARAM_1_s +{ + const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_1. */ +typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_1_s ALT_NAND_PARAM_DEVICE_PARAM_1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_1 register from the beginning of the component. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_OFST 0x30 + +/* + * Register : device_param_2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE field value from a register. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_2. + */ +struct ALT_NAND_PARAM_DEVICE_PARAM_2_s +{ + const uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_2. */ +typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_2_s ALT_NAND_PARAM_DEVICE_PARAM_2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_2 register from the beginning of the component. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_OFST 0x40 + +/* + * Register : logical_page_data_size + * + * Logical page data area size in bytes + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Logical page spare area size in bytes. If multiple devices are connected on a + * single chip select, physical page data size will be multiplied by the number of + * devices to arrive at logical page size. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE field value from a register. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE. + */ +struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s +{ + const uint32_t value : 16; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE. */ +typedef volatile struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register from the beginning of the component. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST 0x50 + +/* + * Register : logical_page_spare_size + * + * Logical page data area size in bytes + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Logical page spare area size in bytes. If multiple devices are connected on a + * single chip select, physical page spare size will be multiplied by the number of + * devices to arrive at logical page size. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE field value from a register. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE. + */ +struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s +{ + const uint32_t value : 16; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE. */ +typedef volatile struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register from the beginning of the component. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST 0x60 + +/* + * Register : revision + * + * Controller revision number + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [15:0] | R | 0x5 | ALT_NAND_PARAM_REVISION_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Controller revision number + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_REVISION_VALUE register field. */ +#define ALT_NAND_PARAM_REVISION_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_REVISION_VALUE register field. */ +#define ALT_NAND_PARAM_REVISION_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_PARAM_REVISION_VALUE register field. */ +#define ALT_NAND_PARAM_REVISION_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_PARAM_REVISION_VALUE register field value. */ +#define ALT_NAND_PARAM_REVISION_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_PARAM_REVISION_VALUE register field value. */ +#define ALT_NAND_PARAM_REVISION_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_PARAM_REVISION_VALUE register field. */ +#define ALT_NAND_PARAM_REVISION_VALUE_RESET 0x5 +/* Extracts the ALT_NAND_PARAM_REVISION_VALUE field value from a register. */ +#define ALT_NAND_PARAM_REVISION_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_PARAM_REVISION_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_REVISION_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_REVISION. + */ +struct ALT_NAND_PARAM_REVISION_s +{ + const uint32_t value : 16; /* ALT_NAND_PARAM_REVISION_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_REVISION. */ +typedef volatile struct ALT_NAND_PARAM_REVISION_s ALT_NAND_PARAM_REVISION_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_REVISION register from the beginning of the component. */ +#define ALT_NAND_PARAM_REVISION_OFST 0x70 + +/* + * Register : onfi_device_features + * + * Features supported by the connected ONFI device + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The values in the field should be interpreted as follows[list] [*]Bit 0 - + * Supports 16 bit data bus width. [*]Bit 1 - Supports multiple LUN operations. + * [*]Bit 2 - Supports non-sequential page programming. [*]Bit 3 - Supports + * interleaved program and erase operations. [*]Bit 4 - Supports odd to even page + * copyback. [*]Bit 5 - Supports source synchronous. [*]Bit 6 - Supports + * interleaved read operations. [*]Bit 7 - Supports extended parameter page. [*]Bit + * 8 - Supports program page register clear enhancement. [*]Bit 9-15 - + * Reserved.[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE field value from a register. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_FEATURES. + */ +struct ALT_NAND_PARAM_ONFI_DEV_FEATURES_s +{ + const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_FEATURES. */ +typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_FEATURES_s ALT_NAND_PARAM_ONFI_DEV_FEATURES_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_FEATURES register from the beginning of the component. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST 0x80 + +/* + * Register : onfi_optional_commands + * + * Optional commands supported by the connected ONFI device + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The values in the field should be interpreted as follows[list] [*]Bit 0 - + * Supports page cache program command. [*]Bit 1 - Supports read cache commands. + * [*]Bit 2 - Supports get and set features. [*]Bit 3 - Supports read status + * enhanced commands. [*]Bit 4 - Supports copyback. [*]Bit 5 - Supports Read Unique + * Id. [*]Bit 6 - Supports Change Read Column Enhanced. [*]Bit 7 - Supports change + * row address. [*]Bit 8 - Supports Change small data move. [*]Bit 9 - Supports + * RESET Lun. [*]Bit 10-15 - Reserved.[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE field value from a register. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS. + */ +struct ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s +{ + const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS. */ +typedef volatile struct ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS register from the beginning of the component. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST 0x90 + +/* + * Register : onfi_timing_mode + * + * Asynchronous Timing modes supported by the connected ONFI device + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------- + * [5:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The values in the field should be interpreted as follows[list] [*]Bit 0 - + * Supports Timing mode 0. [*]Bit 1 - Supports Timing mode 1. [*]Bit 2 - Supports + * Timing mode 2. [*]Bit 3 - Supports Timing mode 3. [*]Bit 4 - Supports Timing + * mode 4. [*]Bit 5 - Supports Timing mode 5.[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_MSB 5 +/* The width in bits of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_WIDTH 6 +/* The mask used to set the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET_MSK 0x0000003f +/* The mask used to clear the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE field value from a register. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_ONFI_TIMING_MOD. + */ +struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s +{ + const uint32_t value : 6; /* ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_ONFI_TIMING_MOD. */ +typedef volatile struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s ALT_NAND_PARAM_ONFI_TIMING_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_ONFI_TIMING_MOD register from the beginning of the component. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST 0xa0 + +/* + * Register : onfi_pgm_cache_timing_mode + * + * Asynchronous Program Cache Timing modes supported by the connected ONFI device + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------------- + * [5:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * The values in the field should be interpreted as follows[list] [*]Bit 0 - + * Supports Timing mode 0. [*]Bit 1 - Supports Timing mode 1. [*]Bit 2 - Supports + * Timing mode 2. [*]Bit 3 - Supports Timing mode 3. [*]Bit 4 - Supports Timing + * mode 4. [*]Bit 5 - Supports Timing mode 5.[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_MSB 5 +/* The width in bits of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_WIDTH 6 +/* The mask used to set the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET_MSK 0x0000003f +/* The mask used to clear the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE field value from a register. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD. + */ +struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s +{ + const uint32_t value : 6; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD. */ +typedef volatile struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD register from the beginning of the component. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST 0xb0 + +/* + * Register : onfi_device_no_of_luns + * + * Indicates if the device is an ONFI compliant device and the number of LUNS + * present in the device + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------------- + * [7:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS + * [8] | RW | 0x0 | ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : no_of_luns + * + * Indicates the number of LUNS present in the device + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_MSB 7 +/* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_WIDTH 8 +/* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field value. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field value. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS field value from a register. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : onfi_device + * + * Indicates if the device is an ONFI compliant device.[list] [*]0 - Non-ONFI + * compliant device [*]1 - ONFI compliant device[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_MSB 8 +/* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_WIDTH 1 +/* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field value. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field value. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE field value from a register. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS. + */ +struct ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s +{ + const uint32_t no_of_luns : 8; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS */ + uint32_t onfi_device : 1; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS. */ +typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS register from the beginning of the component. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST 0xc0 + +/* + * Register : onfi_device_no_of_blocks_per_lun_l + * + * Lower bits of number of blocks per LUN present in the ONFI complaint device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Indicates the lower bits of number of blocks per LUN present in the ONFI + * complaint device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE field value from a register. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L. + */ +struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s +{ + const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L. */ +typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L register from the beginning of the component. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST 0xd0 + +/* + * Register : onfi_device_no_of_blocks_per_lun_u + * + * Upper bits of number of blocks per LUN present in the ONFI complaint device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Indicates the upper bits of number of blocks per LUN present in the ONFI + * complaint device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field value. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE field value from a register. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U. + */ +struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s +{ + const uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U. */ +typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U register from the beginning of the component. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST 0xe0 + +/* + * Register : features + * + * Shows Available hardware features or attributes + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [1:0] | R | 0x1 | ALT_NAND_PARAM_FEATURES_N_BANKS + * [5:2] | ??? | 0x0 | *UNDEFINED* + * [6] | R | 0x1 | ALT_NAND_PARAM_FEATURES_DMA + * [7] | R | 0x0 | ALT_NAND_PARAM_FEATURES_CMD_DMA + * [8] | R | 0x0 | ALT_NAND_PARAM_FEATURES_PARTITION + * [9] | R | 0x0 | ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND + * [10] | R | 0x0 | ALT_NAND_PARAM_FEATURES_GPREG + * [11] | R | 0x1 | ALT_NAND_PARAM_FEATURES_INDEX_ADDR + * [12] | R | 0x0 | ALT_NAND_PARAM_FEATURES_DFI_INTF + * [13] | R | 0x0 | ALT_NAND_PARAM_FEATURES_LBA + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : n_banks + * + * Maximum number of banks supported by hardware. This is an encoded value. + * [list][*]0 - Two banks [*]1 - Four banks [*]2 - Eight banks [*]3 - Sixteen + * banks[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */ +#define ALT_NAND_PARAM_FEATURES_N_BANKS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */ +#define ALT_NAND_PARAM_FEATURES_N_BANKS_MSB 1 +/* The width in bits of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */ +#define ALT_NAND_PARAM_FEATURES_N_BANKS_WIDTH 2 +/* The mask used to set the ALT_NAND_PARAM_FEATURES_N_BANKS register field value. */ +#define ALT_NAND_PARAM_FEATURES_N_BANKS_SET_MSK 0x00000003 +/* The mask used to clear the ALT_NAND_PARAM_FEATURES_N_BANKS register field value. */ +#define ALT_NAND_PARAM_FEATURES_N_BANKS_CLR_MSK 0xfffffffc +/* The reset value of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */ +#define ALT_NAND_PARAM_FEATURES_N_BANKS_RESET 0x1 +/* Extracts the ALT_NAND_PARAM_FEATURES_N_BANKS field value from a register. */ +#define ALT_NAND_PARAM_FEATURES_N_BANKS_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_NAND_PARAM_FEATURES_N_BANKS register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_FEATURES_N_BANKS_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : dma + * + * if set, DATA-DMA is present in hardware. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_DMA register field. */ +#define ALT_NAND_PARAM_FEATURES_DMA_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_DMA register field. */ +#define ALT_NAND_PARAM_FEATURES_DMA_MSB 6 +/* The width in bits of the ALT_NAND_PARAM_FEATURES_DMA register field. */ +#define ALT_NAND_PARAM_FEATURES_DMA_WIDTH 1 +/* The mask used to set the ALT_NAND_PARAM_FEATURES_DMA register field value. */ +#define ALT_NAND_PARAM_FEATURES_DMA_SET_MSK 0x00000040 +/* The mask used to clear the ALT_NAND_PARAM_FEATURES_DMA register field value. */ +#define ALT_NAND_PARAM_FEATURES_DMA_CLR_MSK 0xffffffbf +/* The reset value of the ALT_NAND_PARAM_FEATURES_DMA register field. */ +#define ALT_NAND_PARAM_FEATURES_DMA_RESET 0x1 +/* Extracts the ALT_NAND_PARAM_FEATURES_DMA field value from a register. */ +#define ALT_NAND_PARAM_FEATURES_DMA_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_NAND_PARAM_FEATURES_DMA register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_FEATURES_DMA_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : cmd_dma + * + * Not implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */ +#define ALT_NAND_PARAM_FEATURES_CMD_DMA_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */ +#define ALT_NAND_PARAM_FEATURES_CMD_DMA_MSB 7 +/* The width in bits of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */ +#define ALT_NAND_PARAM_FEATURES_CMD_DMA_WIDTH 1 +/* The mask used to set the ALT_NAND_PARAM_FEATURES_CMD_DMA register field value. */ +#define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_PARAM_FEATURES_CMD_DMA register field value. */ +#define ALT_NAND_PARAM_FEATURES_CMD_DMA_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */ +#define ALT_NAND_PARAM_FEATURES_CMD_DMA_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_FEATURES_CMD_DMA field value from a register. */ +#define ALT_NAND_PARAM_FEATURES_CMD_DMA_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_PARAM_FEATURES_CMD_DMA register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : partition + * + * if set, Partition logic is present in hardware. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */ +#define ALT_NAND_PARAM_FEATURES_PARTITION_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */ +#define ALT_NAND_PARAM_FEATURES_PARTITION_MSB 8 +/* The width in bits of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */ +#define ALT_NAND_PARAM_FEATURES_PARTITION_WIDTH 1 +/* The mask used to set the ALT_NAND_PARAM_FEATURES_PARTITION register field value. */ +#define ALT_NAND_PARAM_FEATURES_PARTITION_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_PARAM_FEATURES_PARTITION register field value. */ +#define ALT_NAND_PARAM_FEATURES_PARTITION_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */ +#define ALT_NAND_PARAM_FEATURES_PARTITION_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_FEATURES_PARTITION field value from a register. */ +#define ALT_NAND_PARAM_FEATURES_PARTITION_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_PARAM_FEATURES_PARTITION register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_FEATURES_PARTITION_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : xdma_sideband + * + * if set, Side band DMA signals are present in hardware. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */ +#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */ +#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_MSB 9 +/* The width in bits of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */ +#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_WIDTH 1 +/* The mask used to set the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value. */ +#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET_MSK 0x00000200 +/* The mask used to clear the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value. */ +#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_CLR_MSK 0xfffffdff +/* The reset value of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */ +#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND field value from a register. */ +#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : gpreg + * + * if set, General purpose registers are is present in hardware. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_GPREG register field. */ +#define ALT_NAND_PARAM_FEATURES_GPREG_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_GPREG register field. */ +#define ALT_NAND_PARAM_FEATURES_GPREG_MSB 10 +/* The width in bits of the ALT_NAND_PARAM_FEATURES_GPREG register field. */ +#define ALT_NAND_PARAM_FEATURES_GPREG_WIDTH 1 +/* The mask used to set the ALT_NAND_PARAM_FEATURES_GPREG register field value. */ +#define ALT_NAND_PARAM_FEATURES_GPREG_SET_MSK 0x00000400 +/* The mask used to clear the ALT_NAND_PARAM_FEATURES_GPREG register field value. */ +#define ALT_NAND_PARAM_FEATURES_GPREG_CLR_MSK 0xfffffbff +/* The reset value of the ALT_NAND_PARAM_FEATURES_GPREG register field. */ +#define ALT_NAND_PARAM_FEATURES_GPREG_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_FEATURES_GPREG field value from a register. */ +#define ALT_NAND_PARAM_FEATURES_GPREG_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_NAND_PARAM_FEATURES_GPREG register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_FEATURES_GPREG_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : index_addr + * + * if set, hardware support only Indexed addressing. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */ +#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */ +#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_MSB 11 +/* The width in bits of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */ +#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_WIDTH 1 +/* The mask used to set the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value. */ +#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value. */ +#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */ +#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_RESET 0x1 +/* Extracts the ALT_NAND_PARAM_FEATURES_INDEX_ADDR field value from a register. */ +#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : dfi_intf + * + * if set, hardware supports ONFI2.x synchronous interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */ +#define ALT_NAND_PARAM_FEATURES_DFI_INTF_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */ +#define ALT_NAND_PARAM_FEATURES_DFI_INTF_MSB 12 +/* The width in bits of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */ +#define ALT_NAND_PARAM_FEATURES_DFI_INTF_WIDTH 1 +/* The mask used to set the ALT_NAND_PARAM_FEATURES_DFI_INTF register field value. */ +#define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET_MSK 0x00001000 +/* The mask used to clear the ALT_NAND_PARAM_FEATURES_DFI_INTF register field value. */ +#define ALT_NAND_PARAM_FEATURES_DFI_INTF_CLR_MSK 0xffffefff +/* The reset value of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */ +#define ALT_NAND_PARAM_FEATURES_DFI_INTF_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_FEATURES_DFI_INTF field value from a register. */ +#define ALT_NAND_PARAM_FEATURES_DFI_INTF_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_NAND_PARAM_FEATURES_DFI_INTF register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : lba + * + * if set, hardware supports Toshiba LBA devices. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_LBA register field. */ +#define ALT_NAND_PARAM_FEATURES_LBA_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_LBA register field. */ +#define ALT_NAND_PARAM_FEATURES_LBA_MSB 13 +/* The width in bits of the ALT_NAND_PARAM_FEATURES_LBA register field. */ +#define ALT_NAND_PARAM_FEATURES_LBA_WIDTH 1 +/* The mask used to set the ALT_NAND_PARAM_FEATURES_LBA register field value. */ +#define ALT_NAND_PARAM_FEATURES_LBA_SET_MSK 0x00002000 +/* The mask used to clear the ALT_NAND_PARAM_FEATURES_LBA register field value. */ +#define ALT_NAND_PARAM_FEATURES_LBA_CLR_MSK 0xffffdfff +/* The reset value of the ALT_NAND_PARAM_FEATURES_LBA register field. */ +#define ALT_NAND_PARAM_FEATURES_LBA_RESET 0x0 +/* Extracts the ALT_NAND_PARAM_FEATURES_LBA field value from a register. */ +#define ALT_NAND_PARAM_FEATURES_LBA_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_NAND_PARAM_FEATURES_LBA register field value suitable for setting the register. */ +#define ALT_NAND_PARAM_FEATURES_LBA_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_PARAM_FEATURES. + */ +struct ALT_NAND_PARAM_FEATURES_s +{ + const uint32_t n_banks : 2; /* ALT_NAND_PARAM_FEATURES_N_BANKS */ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t dma : 1; /* ALT_NAND_PARAM_FEATURES_DMA */ + const uint32_t cmd_dma : 1; /* ALT_NAND_PARAM_FEATURES_CMD_DMA */ + const uint32_t partition : 1; /* ALT_NAND_PARAM_FEATURES_PARTITION */ + const uint32_t xdma_sideband : 1; /* ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND */ + const uint32_t gpreg : 1; /* ALT_NAND_PARAM_FEATURES_GPREG */ + const uint32_t index_addr : 1; /* ALT_NAND_PARAM_FEATURES_INDEX_ADDR */ + const uint32_t dfi_intf : 1; /* ALT_NAND_PARAM_FEATURES_DFI_INTF */ + const uint32_t lba : 1; /* ALT_NAND_PARAM_FEATURES_LBA */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_PARAM_FEATURES. */ +typedef volatile struct ALT_NAND_PARAM_FEATURES_s ALT_NAND_PARAM_FEATURES_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_PARAM_FEATURES register from the beginning of the component. */ +#define ALT_NAND_PARAM_FEATURES_OFST 0xf0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_NAND_PARAM. + */ +struct ALT_NAND_PARAM_s +{ + volatile ALT_NAND_PARAM_MANUFACTURER_ID_t manufacturer_id; /* ALT_NAND_PARAM_MANUFACTURER_ID */ + volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_DEVICE_ID_t device_id; /* ALT_NAND_PARAM_DEVICE_ID */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_DEVICE_PARAM_0_t device_param_0; /* ALT_NAND_PARAM_DEVICE_PARAM_0 */ + volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_DEVICE_PARAM_1_t device_param_1; /* ALT_NAND_PARAM_DEVICE_PARAM_1 */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_DEVICE_PARAM_2_t device_param_2; /* ALT_NAND_PARAM_DEVICE_PARAM_2 */ + volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t logical_page_data_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t logical_page_spare_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE */ + volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_REVISION_t revision; /* ALT_NAND_PARAM_REVISION */ + volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_ONFI_DEV_FEATURES_t onfi_device_features; /* ALT_NAND_PARAM_ONFI_DEV_FEATURES */ + volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t onfi_optional_commands; /* ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS */ + volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_ONFI_TIMING_MOD_t onfi_timing_mode; /* ALT_NAND_PARAM_ONFI_TIMING_MOD */ + volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t onfi_pgm_cache_timing_mode; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD */ + volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t onfi_device_no_of_luns; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS */ + volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t onfi_device_no_of_blocks_per_lun_l; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L */ + volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t onfi_device_no_of_blocks_per_lun_u; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U */ + volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_FEATURES_t features; /* ALT_NAND_PARAM_FEATURES */ +}; + +/* The typedef declaration for register group ALT_NAND_PARAM. */ +typedef volatile struct ALT_NAND_PARAM_s ALT_NAND_PARAM_t; +/* The struct declaration for the raw register contents of register group ALT_NAND_PARAM. */ +struct ALT_NAND_PARAM_raw_s +{ + volatile uint32_t manufacturer_id; /* ALT_NAND_PARAM_MANUFACTURER_ID */ + volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */ + volatile uint32_t device_id; /* ALT_NAND_PARAM_DEVICE_ID */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile uint32_t device_param_0; /* ALT_NAND_PARAM_DEVICE_PARAM_0 */ + volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */ + volatile uint32_t device_param_1; /* ALT_NAND_PARAM_DEVICE_PARAM_1 */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile uint32_t device_param_2; /* ALT_NAND_PARAM_DEVICE_PARAM_2 */ + volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */ + volatile uint32_t logical_page_data_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile uint32_t logical_page_spare_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE */ + volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */ + volatile uint32_t revision; /* ALT_NAND_PARAM_REVISION */ + volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */ + volatile uint32_t onfi_device_features; /* ALT_NAND_PARAM_ONFI_DEV_FEATURES */ + volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */ + volatile uint32_t onfi_optional_commands; /* ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS */ + volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */ + volatile uint32_t onfi_timing_mode; /* ALT_NAND_PARAM_ONFI_TIMING_MOD */ + volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */ + volatile uint32_t onfi_pgm_cache_timing_mode; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD */ + volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */ + volatile uint32_t onfi_device_no_of_luns; /* ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS */ + volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */ + volatile uint32_t onfi_device_no_of_blocks_per_lun_l; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L */ + volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */ + volatile uint32_t onfi_device_no_of_blocks_per_lun_u; /* ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U */ + volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */ + volatile uint32_t features; /* ALT_NAND_PARAM_FEATURES */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_NAND_PARAM. */ +typedef volatile struct ALT_NAND_PARAM_raw_s ALT_NAND_PARAM_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Interrupt and Status Registers - ALT_NAND_STAT + * Interrupt and Status Registers + * + * Contains interrupt and status registers of controller accessible by software. + * + */ +/* + * Register : transfer_mode + * + * Current data transfer mode is Main only, Spare only or Main+Spare. This + * information is per bank. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE0 + * [3:2] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE1 + * [5:4] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE2 + * [7:6] | R | 0x0 | ALT_NAND_STAT_TFR_MOD_VALUE3 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value0 + * + * [list][*]00 - Bank 0 is in Main mode [*]01 - Bank 0 is in Spare mode [*]10 - + * Bank 0 is in Main+Spare mode[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE0_MSB 1 +/* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE0_WIDTH 2 +/* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE0 register field value. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE0_SET_MSK 0x00000003 +/* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE0 register field value. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE0_CLR_MSK 0xfffffffc +/* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE0 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE0_RESET 0x0 +/* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE0 field value from a register. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE0_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_NAND_STAT_TFR_MOD_VALUE0 register field value suitable for setting the register. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE0_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : value1 + * + * [list][*]00 - Bank 1 is in Main mode [*]01 - Bank 1 is in Spare mode [*]10 - + * Bank 1 is in Main+Spare mode[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE1_MSB 3 +/* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE1_WIDTH 2 +/* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE1 register field value. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE1_SET_MSK 0x0000000c +/* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE1 register field value. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE1_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE1 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE1_RESET 0x0 +/* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE1 field value from a register. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE1_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_NAND_STAT_TFR_MOD_VALUE1 register field value suitable for setting the register. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE1_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : value2 + * + * [list][*]00 - Bank 2 is in Main mode [*]01 - Bank 2 is in Spare mode [*]10 - + * Bank 2 is in Main+Spare mode[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE2_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE2_MSB 5 +/* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE2_WIDTH 2 +/* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE2 register field value. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE2_SET_MSK 0x00000030 +/* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE2 register field value. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE2_CLR_MSK 0xffffffcf +/* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE2 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE2_RESET 0x0 +/* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE2 field value from a register. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE2_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_NAND_STAT_TFR_MOD_VALUE2 register field value suitable for setting the register. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE2_SET(value) (((value) << 4) & 0x00000030) + +/* + * Field : value3 + * + * [list][*]00 - Bank 3 is in Main mode [*]01 - Bank 3 is in Spare mode [*]10 - + * Bank 3 is in Main+Spare mode[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE3_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE3_MSB 7 +/* The width in bits of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE3_WIDTH 2 +/* The mask used to set the ALT_NAND_STAT_TFR_MOD_VALUE3 register field value. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE3_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_NAND_STAT_TFR_MOD_VALUE3 register field value. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE3_CLR_MSK 0xffffff3f +/* The reset value of the ALT_NAND_STAT_TFR_MOD_VALUE3 register field. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE3_RESET 0x0 +/* Extracts the ALT_NAND_STAT_TFR_MOD_VALUE3 field value from a register. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE3_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_NAND_STAT_TFR_MOD_VALUE3 register field value suitable for setting the register. */ +#define ALT_NAND_STAT_TFR_MOD_VALUE3_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_TFR_MOD. + */ +struct ALT_NAND_STAT_TFR_MOD_s +{ + const uint32_t value0 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE0 */ + const uint32_t value1 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE1 */ + const uint32_t value2 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE2 */ + const uint32_t value3 : 2; /* ALT_NAND_STAT_TFR_MOD_VALUE3 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_TFR_MOD. */ +typedef volatile struct ALT_NAND_STAT_TFR_MOD_s ALT_NAND_STAT_TFR_MOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_TFR_MOD register from the beginning of the component. */ +#define ALT_NAND_STAT_TFR_MOD_OFST 0x0 + +/* + * Register : intr_status0 + * + * Interrupt status register for bank 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP + * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_TIME_OUT + * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL + * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL + * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_LD_COMP + * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP + * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_ERASE_COMP + * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP + * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK + * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD + * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_INT_ACT + * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_RST_COMP + * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR + * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ecc_uncor_err + * + * Ecc logic detected uncorrectable error while reading data from flash device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_MSB 0 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : dma_cmd_comp + * + * Not implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_MSB 2 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : time_out + * + * Watchdog timer has triggered in the controller due to one of the reasons like + * device not responding or controller state machine did not get back to idle + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_MSB 3 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_TIME_OUT field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_NAND_STAT_INTR_STAT0_TIME_OUT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : program_fail + * + * Program failure occurred in the device on issuance of a program command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed program operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_MSB 4 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : erase_fail + * + * Erase failure occurred in the device on issuance of a erase command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_MSB 5 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : load_comp + * + * Device finished the last issued load command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_MSB 6 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_LD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_NAND_STAT_INTR_STAT0_LD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : program_comp + * + * Device finished the last issued program command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_MSB 7 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : erase_comp + * + * Device erase operation complete + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_MSB 8 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_ERASE_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_STAT_INTR_STAT0_ERASE_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : pipe_cpybck_cmd_comp + * + * A pipeline command or a copyback bank command has completed on this particular + * bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_MSB 9 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : locked_blk + * + * The address to program or erase operation is to a locked block and the operation + * failed due to this reason + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_MSB 10 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : unsup_cmd + * + * An unsupported command was received. This interrupt is set when an invalid + * command is received, or when a command sequence is broken. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_MSB 11 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET_MSK 0x00000800 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : INT_act + * + * R/B pin of device transitioned from low to high + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_MSB 12 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET_MSK 0x00001000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_CLR_MSK 0xffffefff +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_INT_ACT field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_NAND_STAT_INTR_STAT0_INT_ACT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : rst_comp + * + * Controller has finished reset and initialization process + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_MSB 13 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET_MSK 0x00002000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_CLR_MSK 0xffffdfff +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_RST_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_NAND_STAT_INTR_STAT0_RST_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : pipe_cmd_err + * + * A pipeline command sequence has been violated. This occurs when Map 01 page + * read/write address does not match the corresponding expected address from the + * pipeline commands issued earlier. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_MSB 14 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET_MSK 0x00004000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : page_xfer_inc + * + * For every page of data transfer to or from the device, this bit will be set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_MSB 15 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET_MSK 0x00008000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_CLR_MSK 0xffff7fff +/* The reset value of the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_INTR_STAT0. + */ +struct ALT_NAND_STAT_INTR_STAT0_s +{ + uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP */ + uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT0_TIME_OUT */ + uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL */ + uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL */ + uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_LD_COMP */ + uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP */ + uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_ERASE_COMP */ + uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP */ + uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK */ + uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD */ + uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_STAT0_INT_ACT */ + uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT0_RST_COMP */ + uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR */ + uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_INTR_STAT0. */ +typedef volatile struct ALT_NAND_STAT_INTR_STAT0_s ALT_NAND_STAT_INTR_STAT0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_INTR_STAT0 register from the beginning of the component. */ +#define ALT_NAND_STAT_INTR_STAT0_OFST 0x10 + +/* + * Register : intr_en0 + * + * Enables corresponding interrupt bit in interrupt register for bank 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP + * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_TIME_OUT + * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL + * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ERASE_FAIL + * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_LD_COMP + * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP + * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ERASE_COMP + * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP + * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_LOCKED_BLK + * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_UNSUP_CMD + * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_INT_ACT + * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN0_RST_COMP + * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR + * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ecc_uncor_err + * + * If set, Controller will interrupt processor when Ecc logic detects uncorrectable + * error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_MSB 0 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : dma_cmd_comp + * + * Not implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_MSB 2 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : time_out + * + * Watchdog timer has triggered in the controller due to one of the reasons like + * device not responding or controller state machine did not get back to idle + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_MSB 3 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_TIME_OUT field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : program_fail + * + * Program failure occurred in the device on issuance of a program command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed program operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_MSB 4 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : erase_fail + * + * Erase failure occurred in the device on issuance of a erase command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_MSB 5 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : load_comp + * + * Device finished the last issued load command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_LD_COMP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_LD_COMP_MSB 6 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_LD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_LD_COMP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_NAND_STAT_INTR_EN0_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_LD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_LD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_NAND_STAT_INTR_EN0_LD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : program_comp + * + * Device finished the last issued program command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_MSB 7 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : erase_comp + * + * Device erase operation complete + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_MSB 8 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_ERASE_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : pipe_cpybck_cmd_comp + * + * A pipeline command or a copyback bank command has completed on this particular + * bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_MSB 9 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : locked_blk + * + * The address to program or erase operation is to a locked block and the operation + * failed due to this reason + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_MSB 10 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : unsup_cmd + * + * An unsupported command was received. This interrupt is set when an invalid + * command is received, or when a command sequence is broken. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_MSB 11 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK 0x00000800 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : INT_act + * + * R/B pin of device transitioned from low to high + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN0_INT_ACT_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN0_INT_ACT_MSB 12 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN0_INT_ACT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET_MSK 0x00001000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_EN0_INT_ACT_CLR_MSK 0xffffefff +/* The reset value of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN0_INT_ACT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_INT_ACT field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_NAND_STAT_INTR_EN0_INT_ACT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : rst_comp + * + * A reset command has completed on this bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_RST_COMP_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_RST_COMP_MSB 13 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_RST_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET_MSK 0x00002000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN0_RST_COMP_CLR_MSK 0xffffdfff +/* The reset value of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN0_RST_COMP_RESET 0x1 +/* Extracts the ALT_NAND_STAT_INTR_EN0_RST_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_NAND_STAT_INTR_EN0_RST_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : pipe_cmd_err + * + * A pipeline command sequence has been violated. This occurs when Map 01 page + * read/write address does not match the corresponding expected address from the + * pipeline commands issued earlier. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_MSB 14 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET_MSK 0x00004000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff +/* The reset value of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : page_xfer_inc + * + * For every page of data transfer to or from the device, this bit will be set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_MSB 15 +/* The width in bits of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET_MSK 0x00008000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_CLR_MSK 0xffff7fff +/* The reset value of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC field value from a register. */ +#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_INTR_EN0. + */ +struct ALT_NAND_STAT_INTR_EN0_s +{ + uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP */ + uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN0_TIME_OUT */ + uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL */ + uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN0_ERASE_FAIL */ + uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN0_LD_COMP */ + uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP */ + uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN0_ERASE_COMP */ + uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP */ + uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN0_LOCKED_BLK */ + uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN0_UNSUP_CMD */ + uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_EN0_INT_ACT */ + uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN0_RST_COMP */ + uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR */ + uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_INTR_EN0. */ +typedef volatile struct ALT_NAND_STAT_INTR_EN0_s ALT_NAND_STAT_INTR_EN0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_INTR_EN0 register from the beginning of the component. */ +#define ALT_NAND_STAT_INTR_EN0_OFST 0x20 + +/* + * Register : page_cnt0 + * + * Decrementing page count bank 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT0_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Maintains a decrementing count of the number of pages in the multi-page + * (pipeline and copyback) command being executed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT0_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT0_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT0_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_STAT_PAGE_CNT0_VALUE register field value. */ +#define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_STAT_PAGE_CNT0_VALUE register field value. */ +#define ALT_NAND_STAT_PAGE_CNT0_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT0_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_PAGE_CNT0_VALUE field value from a register. */ +#define ALT_NAND_STAT_PAGE_CNT0_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_STAT_PAGE_CNT0_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_PAGE_CNT0. + */ +struct ALT_NAND_STAT_PAGE_CNT0_s +{ + const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT0_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT0. */ +typedef volatile struct ALT_NAND_STAT_PAGE_CNT0_s ALT_NAND_STAT_PAGE_CNT0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_PAGE_CNT0 register from the beginning of the component. */ +#define ALT_NAND_STAT_PAGE_CNT0_OFST 0x30 + +/* + * Register : err_page_addr0 + * + * Erred page address bank 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Holds the page address that resulted in a failure on program or erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE field value from a register. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR0. + */ +struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s +{ + const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR0. */ +typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s ALT_NAND_STAT_ERR_PAGE_ADDR0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register from the beginning of the component. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST 0x40 + +/* + * Register : err_block_addr0 + * + * Erred block address bank 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Holds the block address that resulted in a failure on program or erase + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE field value from a register. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR0. + */ +struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s +{ + const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR0. */ +typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s ALT_NAND_STAT_ERR_BLOCK_ADDR0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register from the beginning of the component. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST 0x50 + +/* + * Register : intr_status1 + * + * Interrupt status register for bank 1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP + * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_TIME_OUT + * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL + * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL + * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_LD_COMP + * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP + * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_ERASE_COMP + * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP + * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK + * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD + * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_INT_ACT + * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_RST_COMP + * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR + * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ecc_uncor_err + * + * Ecc logic detected uncorrectable error while reading data from flash device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_MSB 0 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : dma_cmd_comp + * + * Not implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_MSB 2 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : time_out + * + * Watchdog timer has triggered in the controller due to one of the reasons like + * device not responding or controller state machine did not get back to idle + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_MSB 3 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_TIME_OUT field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_NAND_STAT_INTR_STAT1_TIME_OUT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : program_fail + * + * Program failure occurred in the device on issuance of a program command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed program operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_MSB 4 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : erase_fail + * + * Erase failure occurred in the device on issuance of a erase command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_MSB 5 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : load_comp + * + * Device finished the last issued load command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_MSB 6 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_LD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_NAND_STAT_INTR_STAT1_LD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : program_comp + * + * Device finished the last issued program command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_MSB 7 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : erase_comp + * + * Device erase operation complete + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_MSB 8 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_ERASE_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_STAT_INTR_STAT1_ERASE_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : pipe_cpybck_cmd_comp + * + * A pipeline command or a copyback bank command has completed on this particular + * bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_MSB 9 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : locked_blk + * + * The address to program or erase operation is to a locked block and the operation + * failed due to this reason + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_MSB 10 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : unsup_cmd + * + * An unsupported command was received. This interrupt is set when an invalid + * command is received, or when a command sequence is broken. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_MSB 11 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET_MSK 0x00000800 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : INT_act + * + * R/B pin of device transitioned from low to high + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_MSB 12 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET_MSK 0x00001000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_CLR_MSK 0xffffefff +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_INT_ACT field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_NAND_STAT_INTR_STAT1_INT_ACT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : rst_comp + * + * The NAND Flash Memory Controller has completed its reset and initialization + * process + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_MSB 13 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET_MSK 0x00002000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_CLR_MSK 0xffffdfff +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_RST_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_NAND_STAT_INTR_STAT1_RST_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : pipe_cmd_err + * + * A pipeline command sequence has been violated. This occurs when Map 01 page + * read/write address does not match the corresponding expected address from the + * pipeline commands issued earlier. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_MSB 14 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET_MSK 0x00004000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : page_xfer_inc + * + * For every page of data transfer to or from the device, this bit will be set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_MSB 15 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET_MSK 0x00008000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_CLR_MSK 0xffff7fff +/* The reset value of the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_INTR_STAT1. + */ +struct ALT_NAND_STAT_INTR_STAT1_s +{ + uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP */ + uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT1_TIME_OUT */ + uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL */ + uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL */ + uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_LD_COMP */ + uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP */ + uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_ERASE_COMP */ + uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP */ + uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK */ + uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD */ + uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_STAT1_INT_ACT */ + uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT1_RST_COMP */ + uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR */ + uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_INTR_STAT1. */ +typedef volatile struct ALT_NAND_STAT_INTR_STAT1_s ALT_NAND_STAT_INTR_STAT1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_INTR_STAT1 register from the beginning of the component. */ +#define ALT_NAND_STAT_INTR_STAT1_OFST 0x60 + +/* + * Register : intr_en1 + * + * Enables corresponding interrupt bit in interrupt register for bank 1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP + * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_TIME_OUT + * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL + * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ERASE_FAIL + * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_LD_COMP + * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP + * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ERASE_COMP + * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP + * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_LOCKED_BLK + * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_UNSUP_CMD + * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_INT_ACT + * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN1_RST_COMP + * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR + * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ecc_uncor_err + * + * If set, Controller will interrupt processor when Ecc logic detects uncorrectable + * error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_MSB 0 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : dma_cmd_comp + * + * Not implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_MSB 2 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : time_out + * + * Watchdog timer has triggered in the controller due to one of the reasons like + * device not responding or controller state machine did not get back to idle + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_MSB 3 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_TIME_OUT field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : program_fail + * + * Program failure occurred in the device on issuance of a program command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed program operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_MSB 4 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : erase_fail + * + * Erase failure occurred in the device on issuance of a erase command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_MSB 5 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : load_comp + * + * Device finished the last issued load command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_LD_COMP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_LD_COMP_MSB 6 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_LD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_LD_COMP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_NAND_STAT_INTR_EN1_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_LD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_LD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_NAND_STAT_INTR_EN1_LD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : program_comp + * + * Device finished the last issued program command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_MSB 7 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : erase_comp + * + * Device erase operation complete + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_MSB 8 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_ERASE_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : pipe_cpybck_cmd_comp + * + * A pipeline command or a copyback bank command has completed on this particular + * bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_MSB 9 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : locked_blk + * + * The address to program or erase operation is to a locked block and the operation + * failed due to this reason + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_MSB 10 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : unsup_cmd + * + * An unsupported command was received. This interrupt is set when an invalid + * command is received, or when a command sequence is broken. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_MSB 11 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET_MSK 0x00000800 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : INT_act + * + * R/B pin of device transitioned from low to high + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN1_INT_ACT_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN1_INT_ACT_MSB 12 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN1_INT_ACT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET_MSK 0x00001000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_EN1_INT_ACT_CLR_MSK 0xffffefff +/* The reset value of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN1_INT_ACT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_INT_ACT field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_NAND_STAT_INTR_EN1_INT_ACT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : rst_comp + * + * A reset command has completed on this bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_RST_COMP_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_RST_COMP_MSB 13 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_RST_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET_MSK 0x00002000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN1_RST_COMP_CLR_MSK 0xffffdfff +/* The reset value of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN1_RST_COMP_RESET 0x1 +/* Extracts the ALT_NAND_STAT_INTR_EN1_RST_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_NAND_STAT_INTR_EN1_RST_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : pipe_cmd_err + * + * A pipeline command sequence has been violated. This occurs when Map 01 page + * read/write address does not match the corresponding expected address from the + * pipeline commands issued earlier. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_MSB 14 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET_MSK 0x00004000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff +/* The reset value of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : page_xfer_inc + * + * For every page of data transfer to or from the device, this bit will be set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_MSB 15 +/* The width in bits of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET_MSK 0x00008000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_CLR_MSK 0xffff7fff +/* The reset value of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC field value from a register. */ +#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_INTR_EN1. + */ +struct ALT_NAND_STAT_INTR_EN1_s +{ + uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP */ + uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN1_TIME_OUT */ + uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL */ + uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN1_ERASE_FAIL */ + uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN1_LD_COMP */ + uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP */ + uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN1_ERASE_COMP */ + uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP */ + uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN1_LOCKED_BLK */ + uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN1_UNSUP_CMD */ + uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_EN1_INT_ACT */ + uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN1_RST_COMP */ + uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR */ + uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_INTR_EN1. */ +typedef volatile struct ALT_NAND_STAT_INTR_EN1_s ALT_NAND_STAT_INTR_EN1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_INTR_EN1 register from the beginning of the component. */ +#define ALT_NAND_STAT_INTR_EN1_OFST 0x70 + +/* + * Register : page_cnt1 + * + * Decrementing page count bank 1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT1_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Maintains a decrementing count of the number of pages in the multi-page + * (pipeline and copyback) command being executed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT1_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT1_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT1_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_STAT_PAGE_CNT1_VALUE register field value. */ +#define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_STAT_PAGE_CNT1_VALUE register field value. */ +#define ALT_NAND_STAT_PAGE_CNT1_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT1_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_PAGE_CNT1_VALUE field value from a register. */ +#define ALT_NAND_STAT_PAGE_CNT1_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_STAT_PAGE_CNT1_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_PAGE_CNT1. + */ +struct ALT_NAND_STAT_PAGE_CNT1_s +{ + const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT1_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT1. */ +typedef volatile struct ALT_NAND_STAT_PAGE_CNT1_s ALT_NAND_STAT_PAGE_CNT1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_PAGE_CNT1 register from the beginning of the component. */ +#define ALT_NAND_STAT_PAGE_CNT1_OFST 0x80 + +/* + * Register : err_page_addr1 + * + * Erred page address bank 1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Holds the page address that resulted in a failure on program or erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE field value from a register. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR1. + */ +struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s +{ + const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR1. */ +typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s ALT_NAND_STAT_ERR_PAGE_ADDR1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register from the beginning of the component. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST 0x90 + +/* + * Register : err_block_addr1 + * + * Erred block address bank 1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Holds the block address that resulted in a failure on program or erase + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE field value from a register. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR1. + */ +struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s +{ + const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR1. */ +typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s ALT_NAND_STAT_ERR_BLOCK_ADDR1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register from the beginning of the component. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST 0xa0 + +/* + * Register : intr_status2 + * + * Interrupt status register for bank 2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP + * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_TIME_OUT + * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL + * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL + * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_LD_COMP + * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP + * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_ERASE_COMP + * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP + * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK + * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD + * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_INT_ACT + * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_RST_COMP + * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR + * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ecc_uncor_err + * + * Ecc logic detected uncorrectable error while reading data from flash device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_MSB 0 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : dma_cmd_comp + * + * Not implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_MSB 2 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : time_out + * + * Watchdog timer has triggered in the controller due to one of the reasons like + * device not responding or controller state machine did not get back to idle + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_MSB 3 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_TIME_OUT field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_NAND_STAT_INTR_STAT2_TIME_OUT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : program_fail + * + * Program failure occurred in the device on issuance of a program command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed program operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_MSB 4 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : erase_fail + * + * Erase failure occurred in the device on issuance of a erase command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_MSB 5 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : load_comp + * + * Device finished the last issued load command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_MSB 6 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_LD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_NAND_STAT_INTR_STAT2_LD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : program_comp + * + * Device finished the last issued program command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_MSB 7 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : erase_comp + * + * Device erase operation complete + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_MSB 8 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_ERASE_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_STAT_INTR_STAT2_ERASE_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : pipe_cpybck_cmd_comp + * + * A pipeline command or a copyback bank command has completed on this particular + * bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_MSB 9 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : locked_blk + * + * The address to program or erase operation is to a locked block and the operation + * failed due to this reason + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_MSB 10 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : unsup_cmd + * + * An unsupported command was received. This interrupt is set when an invalid + * command is received, or when a command sequence is broken. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_MSB 11 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET_MSK 0x00000800 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : INT_act + * + * R/B pin of device transitioned from low to high + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_MSB 12 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET_MSK 0x00001000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_CLR_MSK 0xffffefff +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_INT_ACT field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_NAND_STAT_INTR_STAT2_INT_ACT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : rst_comp + * + * The NAND Flash Memory Controller has completed its reset and initialization + * process + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_MSB 13 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET_MSK 0x00002000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_CLR_MSK 0xffffdfff +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_RST_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_NAND_STAT_INTR_STAT2_RST_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : pipe_cmd_err + * + * A pipeline command sequence has been violated. This occurs when Map 01 page + * read/write address does not match the corresponding expected address from the + * pipeline commands issued earlier. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_MSB 14 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET_MSK 0x00004000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : page_xfer_inc + * + * For every page of data transfer to or from the device, this bit will be set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_MSB 15 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET_MSK 0x00008000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_CLR_MSK 0xffff7fff +/* The reset value of the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_INTR_STAT2. + */ +struct ALT_NAND_STAT_INTR_STAT2_s +{ + uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP */ + uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT2_TIME_OUT */ + uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL */ + uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL */ + uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_LD_COMP */ + uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP */ + uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_ERASE_COMP */ + uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP */ + uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK */ + uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD */ + uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_STAT2_INT_ACT */ + uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT2_RST_COMP */ + uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR */ + uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_INTR_STAT2. */ +typedef volatile struct ALT_NAND_STAT_INTR_STAT2_s ALT_NAND_STAT_INTR_STAT2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_INTR_STAT2 register from the beginning of the component. */ +#define ALT_NAND_STAT_INTR_STAT2_OFST 0xb0 + +/* + * Register : intr_en2 + * + * Enables corresponding interrupt bit in interrupt register for bank 2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP + * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_TIME_OUT + * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL + * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ERASE_FAIL + * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_LD_COMP + * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP + * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ERASE_COMP + * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP + * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_LOCKED_BLK + * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_UNSUP_CMD + * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_INT_ACT + * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN2_RST_COMP + * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR + * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ecc_uncor_err + * + * If set, Controller will interrupt processor when Ecc logic detects uncorrectable + * error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_MSB 0 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : dma_cmd_comp + * + * Not implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_MSB 2 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : time_out + * + * Watchdog timer has triggered in the controller due to one of the reasons like + * device not responding or controller state machine did not get back to idle + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_MSB 3 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_TIME_OUT field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : program_fail + * + * Program failure occurred in the device on issuance of a program command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed program operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_MSB 4 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : erase_fail + * + * Erase failure occurred in the device on issuance of a erase command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_MSB 5 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : load_comp + * + * Device finished the last issued load command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_LD_COMP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_LD_COMP_MSB 6 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_LD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_LD_COMP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_NAND_STAT_INTR_EN2_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_LD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_LD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_NAND_STAT_INTR_EN2_LD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : program_comp + * + * Device finished the last issued program command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_MSB 7 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : erase_comp + * + * Device erase operation complete + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_MSB 8 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_ERASE_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : pipe_cpybck_cmd_comp + * + * A pipeline command or a copyback bank command has completed on this particular + * bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_MSB 9 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : locked_blk + * + * The address to program or erase operation is to a locked block and the operation + * failed due to this reason + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_MSB 10 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : unsup_cmd + * + * An unsupported command was received. This interrupt is set when an invalid + * command is received, or when a command sequence is broken. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_MSB 11 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET_MSK 0x00000800 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : INT_act + * + * R/B pin of device transitioned from low to high + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN2_INT_ACT_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN2_INT_ACT_MSB 12 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN2_INT_ACT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET_MSK 0x00001000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_EN2_INT_ACT_CLR_MSK 0xffffefff +/* The reset value of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN2_INT_ACT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_INT_ACT field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_NAND_STAT_INTR_EN2_INT_ACT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : rst_comp + * + * A reset command has completed on this bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_RST_COMP_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_RST_COMP_MSB 13 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_RST_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET_MSK 0x00002000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN2_RST_COMP_CLR_MSK 0xffffdfff +/* The reset value of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN2_RST_COMP_RESET 0x1 +/* Extracts the ALT_NAND_STAT_INTR_EN2_RST_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_NAND_STAT_INTR_EN2_RST_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : pipe_cmd_err + * + * A pipeline command sequence has been violated. This occurs when Map 01 page + * read/write address does not match the corresponding expected address from the + * pipeline commands issued earlier. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_MSB 14 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET_MSK 0x00004000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff +/* The reset value of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : page_xfer_inc + * + * For every page of data transfer to or from the device, this bit will be set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_MSB 15 +/* The width in bits of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET_MSK 0x00008000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_CLR_MSK 0xffff7fff +/* The reset value of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC field value from a register. */ +#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_INTR_EN2. + */ +struct ALT_NAND_STAT_INTR_EN2_s +{ + uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP */ + uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN2_TIME_OUT */ + uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL */ + uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN2_ERASE_FAIL */ + uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN2_LD_COMP */ + uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP */ + uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN2_ERASE_COMP */ + uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP */ + uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN2_LOCKED_BLK */ + uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN2_UNSUP_CMD */ + uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_EN2_INT_ACT */ + uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN2_RST_COMP */ + uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR */ + uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_INTR_EN2. */ +typedef volatile struct ALT_NAND_STAT_INTR_EN2_s ALT_NAND_STAT_INTR_EN2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_INTR_EN2 register from the beginning of the component. */ +#define ALT_NAND_STAT_INTR_EN2_OFST 0xc0 + +/* + * Register : page_cnt2 + * + * Decrementing page count bank 2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT2_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Maintains a decrementing count of the number of pages in the multi-page + * (pipeline and copyback) command being executed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT2_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT2_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT2_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_STAT_PAGE_CNT2_VALUE register field value. */ +#define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_STAT_PAGE_CNT2_VALUE register field value. */ +#define ALT_NAND_STAT_PAGE_CNT2_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT2_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_PAGE_CNT2_VALUE field value from a register. */ +#define ALT_NAND_STAT_PAGE_CNT2_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_STAT_PAGE_CNT2_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_PAGE_CNT2. + */ +struct ALT_NAND_STAT_PAGE_CNT2_s +{ + const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT2_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT2. */ +typedef volatile struct ALT_NAND_STAT_PAGE_CNT2_s ALT_NAND_STAT_PAGE_CNT2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_PAGE_CNT2 register from the beginning of the component. */ +#define ALT_NAND_STAT_PAGE_CNT2_OFST 0xd0 + +/* + * Register : err_page_addr2 + * + * Erred page address bank 2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Holds the page address that resulted in a failure on program or erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE field value from a register. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR2. + */ +struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s +{ + const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR2. */ +typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s ALT_NAND_STAT_ERR_PAGE_ADDR2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register from the beginning of the component. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST 0xe0 + +/* + * Register : err_block_addr2 + * + * Erred block address bank 2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Holds the block address that resulted in a failure on program or erase + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE field value from a register. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR2. + */ +struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s +{ + const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR2. */ +typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s ALT_NAND_STAT_ERR_BLOCK_ADDR2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register from the beginning of the component. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST 0xf0 + +/* + * Register : intr_status3 + * + * Interrupt status register for bank 3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP + * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_TIME_OUT + * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL + * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL + * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_LD_COMP + * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP + * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP + * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP + * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK + * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD + * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_INT_ACT + * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_RST_COMP + * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR + * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ecc_uncor_err + * + * Ecc logic detected uncorrectable error while reading data from flash device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_MSB 0 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : dma_cmd_comp + * + * Not implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_MSB 2 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : time_out + * + * Watchdog timer has triggered in the controller due to one of the reasons like + * device not responding or controller state machine did not get back to idle + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_MSB 3 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_TIME_OUT field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : program_fail + * + * Program failure occurred in the device on issuance of a program command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed program operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_MSB 4 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : erase_fail + * + * Erase failure occurred in the device on issuance of a erase command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_MSB 5 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : load_comp + * + * Device finished the last issued load command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_MSB 6 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_LD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : program_comp + * + * Device finished the last issued program command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_MSB 7 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : erase_comp + * + * Device erase operation complete + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_MSB 8 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : pipe_cpybck_cmd_comp + * + * A pipeline command or a copyback bank command has completed on this particular + * bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_MSB 9 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : locked_blk + * + * The address to program or erase operation is to a locked block and the operation + * failed due to this reason + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_MSB 10 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : unsup_cmd + * + * An unsupported command was received. This interrupt is set when an invalid + * command is received, or when a command sequence is broken. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_MSB 11 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET_MSK 0x00000800 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : INT_act + * + * R/B pin of device transitioned from low to high + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_MSB 12 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET_MSK 0x00001000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_CLR_MSK 0xffffefff +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_INT_ACT field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : rst_comp + * + * The NAND Flash Memory Controller has completed its reset and initialization + * process + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_MSB 13 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET_MSK 0x00002000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_CLR_MSK 0xffffdfff +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_RST_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : pipe_cmd_err + * + * A pipeline command sequence has been violated. This occurs when Map 01 page + * read/write address does not match the corresponding expected address from the + * pipeline commands issued earlier. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_MSB 14 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET_MSK 0x00004000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : page_xfer_inc + * + * For every page of data transfer to or from the device, this bit will be set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_MSB 15 +/* The width in bits of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET_MSK 0x00008000 +/* The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_CLR_MSK 0xffff7fff +/* The reset value of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC field value from a register. */ +#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_INTR_STAT3. + */ +struct ALT_NAND_STAT_INTR_STAT3_s +{ + uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP */ + uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STAT3_TIME_OUT */ + uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL */ + uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL */ + uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_LD_COMP */ + uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP */ + uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_ERASE_COMP */ + uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP */ + uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK */ + uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD */ + uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_STAT3_INT_ACT */ + uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STAT3_RST_COMP */ + uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR */ + uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_INTR_STAT3. */ +typedef volatile struct ALT_NAND_STAT_INTR_STAT3_s ALT_NAND_STAT_INTR_STAT3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_INTR_STAT3 register from the beginning of the component. */ +#define ALT_NAND_STAT_INTR_STAT3_OFST 0x100 + +/* + * Register : intr_en3 + * + * Enables corresponding interrupt bit in interrupt register for bank 3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP + * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_TIME_OUT + * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL + * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ERASE_FAIL + * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_LD_COMP + * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP + * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ERASE_COMP + * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP + * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_LOCKED_BLK + * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_UNSUP_CMD + * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_INT_ACT + * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN3_RST_COMP + * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR + * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : ecc_uncor_err + * + * If set, Controller will interrupt processor when Ecc logic detects uncorrectable + * error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_MSB 0 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : dma_cmd_comp + * + * Not implemented. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_MSB 2 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : time_out + * + * Watchdog timer has triggered in the controller due to one of the reasons like + * device not responding or controller state machine did not get back to idle + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_MSB 3 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value. */ +#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */ +#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_TIME_OUT field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : program_fail + * + * Program failure occurred in the device on issuance of a program command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed program operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_MSB 4 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : erase_fail + * + * Erase failure occurred in the device on issuance of a erase command. + * err_block_addr and err_page_addr contain the block address and page address that + * failed erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_MSB 5 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : load_comp + * + * Device finished the last issued load command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_LD_COMP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_LD_COMP_MSB 6 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_LD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_LD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_LD_COMP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_NAND_STAT_INTR_EN3_LD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_LD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_LD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_NAND_STAT_INTR_EN3_LD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : program_comp + * + * Device finished the last issued program command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_MSB 7 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : erase_comp + * + * Device erase operation complete + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_MSB 8 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_ERASE_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : pipe_cpybck_cmd_comp + * + * A pipeline command or a copyback bank command has completed on this particular + * bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_MSB 9 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : locked_blk + * + * The address to program or erase operation is to a locked block and the operation + * failed due to this reason + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_MSB 10 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value. */ +#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */ +#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : unsup_cmd + * + * An unsupported command was received. This interrupt is set when an invalid + * command is received, or when a command sequence is broken. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_MSB 11 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET_MSK 0x00000800 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value. */ +#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */ +#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : INT_act + * + * R/B pin of device transitioned from low to high + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN3_INT_ACT_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN3_INT_ACT_MSB 12 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN3_INT_ACT_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET_MSK 0x00001000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_INT_ACT register field value. */ +#define ALT_NAND_STAT_INTR_EN3_INT_ACT_CLR_MSK 0xffffefff +/* The reset value of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */ +#define ALT_NAND_STAT_INTR_EN3_INT_ACT_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_INT_ACT field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_NAND_STAT_INTR_EN3_INT_ACT register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : rst_comp + * + * A reset command has completed on this bank + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_RST_COMP_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_RST_COMP_MSB 13 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_RST_COMP_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET_MSK 0x00002000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_RST_COMP register field value. */ +#define ALT_NAND_STAT_INTR_EN3_RST_COMP_CLR_MSK 0xffffdfff +/* The reset value of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */ +#define ALT_NAND_STAT_INTR_EN3_RST_COMP_RESET 0x1 +/* Extracts the ALT_NAND_STAT_INTR_EN3_RST_COMP field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_NAND_STAT_INTR_EN3_RST_COMP register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : pipe_cmd_err + * + * A pipeline command sequence has been violated. This occurs when Map 01 page + * read/write address does not match the corresponding expected address from the + * pipeline commands issued earlier. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_MSB 14 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET_MSK 0x00004000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff +/* The reset value of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : page_xfer_inc + * + * For every page of data transfer to or from the device, this bit will be set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_MSB 15 +/* The width in bits of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_WIDTH 1 +/* The mask used to set the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET_MSK 0x00008000 +/* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value. */ +#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_CLR_MSK 0xffff7fff +/* The reset value of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */ +#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_RESET 0x0 +/* Extracts the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC field value from a register. */ +#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value suitable for setting the register. */ +#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_INTR_EN3. + */ +struct ALT_NAND_STAT_INTR_EN3_s +{ + uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP */ + uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN3_TIME_OUT */ + uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL */ + uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN3_ERASE_FAIL */ + uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN3_LD_COMP */ + uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP */ + uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN3_ERASE_COMP */ + uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP */ + uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN3_LOCKED_BLK */ + uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN3_UNSUP_CMD */ + uint32_t INT_act : 1; /* ALT_NAND_STAT_INTR_EN3_INT_ACT */ + uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN3_RST_COMP */ + uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR */ + uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_INTR_EN3. */ +typedef volatile struct ALT_NAND_STAT_INTR_EN3_s ALT_NAND_STAT_INTR_EN3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_INTR_EN3 register from the beginning of the component. */ +#define ALT_NAND_STAT_INTR_EN3_OFST 0x110 + +/* + * Register : page_cnt3 + * + * Decrementing page count bank 3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT3_VALUE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Maintains a decrementing count of the number of pages in the multi-page + * (pipeline and copyback) command being executed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT3_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT3_VALUE_MSB 7 +/* The width in bits of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT3_VALUE_WIDTH 8 +/* The mask used to set the ALT_NAND_STAT_PAGE_CNT3_VALUE register field value. */ +#define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_NAND_STAT_PAGE_CNT3_VALUE register field value. */ +#define ALT_NAND_STAT_PAGE_CNT3_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */ +#define ALT_NAND_STAT_PAGE_CNT3_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_PAGE_CNT3_VALUE field value from a register. */ +#define ALT_NAND_STAT_PAGE_CNT3_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_NAND_STAT_PAGE_CNT3_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_PAGE_CNT3. + */ +struct ALT_NAND_STAT_PAGE_CNT3_s +{ + const uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT3_VALUE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT3. */ +typedef volatile struct ALT_NAND_STAT_PAGE_CNT3_s ALT_NAND_STAT_PAGE_CNT3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_PAGE_CNT3 register from the beginning of the component. */ +#define ALT_NAND_STAT_PAGE_CNT3_OFST 0x120 + +/* + * Register : err_page_addr3 + * + * Erred page address bank 3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Holds the page address that resulted in a failure on program or erase operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE field value from a register. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR3. + */ +struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s +{ + const uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR3. */ +typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s ALT_NAND_STAT_ERR_PAGE_ADDR3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register from the beginning of the component. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST 0x130 + +/* + * Register : err_block_addr3 + * + * Erred block address bank 3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Holds the block address that resulted in a failure on program or erase + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE field value from a register. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR3. + */ +struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s +{ + const uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR3. */ +typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s ALT_NAND_STAT_ERR_BLOCK_ADDR3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register from the beginning of the component. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST 0x140 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_NAND_STAT. + */ +struct ALT_NAND_STAT_s +{ + volatile ALT_NAND_STAT_TFR_MOD_t transfer_mode; /* ALT_NAND_STAT_TFR_MOD */ + volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_INTR_STAT0_t intr_status0; /* ALT_NAND_STAT_INTR_STAT0 */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_INTR_EN0_t intr_en0; /* ALT_NAND_STAT_INTR_EN0 */ + volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_PAGE_CNT0_t page_cnt0; /* ALT_NAND_STAT_PAGE_CNT0 */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_ERR_PAGE_ADDR0_t err_page_addr0; /* ALT_NAND_STAT_ERR_PAGE_ADDR0 */ + volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_ERR_BLOCK_ADDR0_t err_block_addr0; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0 */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_INTR_STAT1_t intr_status1; /* ALT_NAND_STAT_INTR_STAT1 */ + volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_INTR_EN1_t intr_en1; /* ALT_NAND_STAT_INTR_EN1 */ + volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_PAGE_CNT1_t page_cnt1; /* ALT_NAND_STAT_PAGE_CNT1 */ + volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_ERR_PAGE_ADDR1_t err_page_addr1; /* ALT_NAND_STAT_ERR_PAGE_ADDR1 */ + volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_ERR_BLOCK_ADDR1_t err_block_addr1; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1 */ + volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_INTR_STAT2_t intr_status2; /* ALT_NAND_STAT_INTR_STAT2 */ + volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_INTR_EN2_t intr_en2; /* ALT_NAND_STAT_INTR_EN2 */ + volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_PAGE_CNT2_t page_cnt2; /* ALT_NAND_STAT_PAGE_CNT2 */ + volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_ERR_PAGE_ADDR2_t err_page_addr2; /* ALT_NAND_STAT_ERR_PAGE_ADDR2 */ + volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_ERR_BLOCK_ADDR2_t err_block_addr2; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2 */ + volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_INTR_STAT3_t intr_status3; /* ALT_NAND_STAT_INTR_STAT3 */ + volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_INTR_EN3_t intr_en3; /* ALT_NAND_STAT_INTR_EN3 */ + volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_PAGE_CNT3_t page_cnt3; /* ALT_NAND_STAT_PAGE_CNT3 */ + volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_ERR_PAGE_ADDR3_t err_page_addr3; /* ALT_NAND_STAT_ERR_PAGE_ADDR3 */ + volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_ERR_BLOCK_ADDR3_t err_block_addr3; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3 */ +}; + +/* The typedef declaration for register group ALT_NAND_STAT. */ +typedef volatile struct ALT_NAND_STAT_s ALT_NAND_STAT_t; +/* The struct declaration for the raw register contents of register group ALT_NAND_STAT. */ +struct ALT_NAND_STAT_raw_s +{ + volatile uint32_t transfer_mode; /* ALT_NAND_STAT_TFR_MOD */ + volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */ + volatile uint32_t intr_status0; /* ALT_NAND_STAT_INTR_STAT0 */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile uint32_t intr_en0; /* ALT_NAND_STAT_INTR_EN0 */ + volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */ + volatile uint32_t page_cnt0; /* ALT_NAND_STAT_PAGE_CNT0 */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile uint32_t err_page_addr0; /* ALT_NAND_STAT_ERR_PAGE_ADDR0 */ + volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */ + volatile uint32_t err_block_addr0; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0 */ + volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ + volatile uint32_t intr_status1; /* ALT_NAND_STAT_INTR_STAT1 */ + volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */ + volatile uint32_t intr_en1; /* ALT_NAND_STAT_INTR_EN1 */ + volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */ + volatile uint32_t page_cnt1; /* ALT_NAND_STAT_PAGE_CNT1 */ + volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */ + volatile uint32_t err_page_addr1; /* ALT_NAND_STAT_ERR_PAGE_ADDR1 */ + volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */ + volatile uint32_t err_block_addr1; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1 */ + volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */ + volatile uint32_t intr_status2; /* ALT_NAND_STAT_INTR_STAT2 */ + volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */ + volatile uint32_t intr_en2; /* ALT_NAND_STAT_INTR_EN2 */ + volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */ + volatile uint32_t page_cnt2; /* ALT_NAND_STAT_PAGE_CNT2 */ + volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */ + volatile uint32_t err_page_addr2; /* ALT_NAND_STAT_ERR_PAGE_ADDR2 */ + volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */ + volatile uint32_t err_block_addr2; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2 */ + volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */ + volatile uint32_t intr_status3; /* ALT_NAND_STAT_INTR_STAT3 */ + volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */ + volatile uint32_t intr_en3; /* ALT_NAND_STAT_INTR_EN3 */ + volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */ + volatile uint32_t page_cnt3; /* ALT_NAND_STAT_PAGE_CNT3 */ + volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */ + volatile uint32_t err_page_addr3; /* ALT_NAND_STAT_ERR_PAGE_ADDR3 */ + volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */ + volatile uint32_t err_block_addr3; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_NAND_STAT. */ +typedef volatile struct ALT_NAND_STAT_raw_s ALT_NAND_STAT_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ECC registers - ALT_NAND_ECC + * ECC registers + * + * + */ +/* + * Register : ECCCorInfo_b01 + * + * ECC Error correction Information register. Controller updates this register when + * it completes a transaction. The values are held in this register till a new + * transaction completes. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [6:0] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 + * [7] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 + * [14:8] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 + * [15] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : max_errors_b0 + * + * Maximum of number of errors corrected per sector in Bank0. This field is not + * valid for uncorrectable errors. A value of zero indicates that no ECC error + * occurred in last completed transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_MSB 6 +/* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_WIDTH 7 +/* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK 0x0000007f +/* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_CLR_MSK 0xffffff80 +/* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_RESET 0x0 +/* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 field value from a register. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value suitable for setting the register. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : uncor_err_b0 + * + * Uncorrectable error occurred while reading pages for last transaction in Bank0. + * Uncorrectable errors also generate interrupts in intr_statusx register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_MSB 7 +/* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_WIDTH 1 +/* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_RESET 0x0 +/* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 field value from a register. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value suitable for setting the register. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : max_errors_b1 + * + * Maximum of number of errors corrected per sector in Bank1. This field is not + * valid for uncorrectable errors. A value of zero indicates that no ECC error + * occurred in last completed transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_MSB 14 +/* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_WIDTH 7 +/* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK 0x00007f00 +/* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_CLR_MSK 0xffff80ff +/* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_RESET 0x0 +/* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 field value from a register. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_GET(value) (((value) & 0x00007f00) >> 8) +/* Produces a ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value suitable for setting the register. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET(value) (((value) << 8) & 0x00007f00) + +/* + * Field : uncor_err_b1 + * + * Uncorrectable error occurred while reading pages for last transaction in Bank1. + * Uncorrectable errors also generate interrupts in intr_statusx register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_MSB 15 +/* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_WIDTH 1 +/* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK 0x00008000 +/* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_CLR_MSK 0xffff7fff +/* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_RESET 0x0 +/* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 field value from a register. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value suitable for setting the register. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_ECC_ECCCORINFO_B01. + */ +struct ALT_NAND_ECC_ECCCORINFO_B01_s +{ + const uint32_t max_errors_b0 : 7; /* ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 */ + const uint32_t uncor_err_b0 : 1; /* ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 */ + const uint32_t max_errors_b1 : 7; /* ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 */ + const uint32_t uncor_err_b1 : 1; /* ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_ECC_ECCCORINFO_B01. */ +typedef volatile struct ALT_NAND_ECC_ECCCORINFO_B01_s ALT_NAND_ECC_ECCCORINFO_B01_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_ECC_ECCCORINFO_B01 register from the beginning of the component. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_OFST 0x0 + +/* + * Register : ECCCorInfo_b23 + * + * ECC Error correction Information register. Controller updates this register when + * it completes a transaction. The values are held in this register till a new + * transaction completes. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [6:0] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 + * [7] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 + * [14:8] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 + * [15] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : max_errors_b2 + * + * Maximum of number of errors corrected per sector in Bank2. This field is not + * valid for uncorrectable errors. A value of zero indicates that no ECC error + * occurred in last completed transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_MSB 6 +/* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_WIDTH 7 +/* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK 0x0000007f +/* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_CLR_MSK 0xffffff80 +/* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_RESET 0x0 +/* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 field value from a register. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value suitable for setting the register. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : uncor_err_b2 + * + * Uncorrectable error occurred while reading pages for last transaction in Bank2. + * Uncorrectable errors also generate interrupts in intr_statusx register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_MSB 7 +/* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_WIDTH 1 +/* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK 0x00000080 +/* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_CLR_MSK 0xffffff7f +/* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_RESET 0x0 +/* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 field value from a register. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value suitable for setting the register. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : max_errors_b3 + * + * Maximum of number of errors corrected per sector in Bank3. This field is not + * valid for uncorrectable errors. A value of zero indicates that no ECC error + * occurred in last completed transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_MSB 14 +/* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_WIDTH 7 +/* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK 0x00007f00 +/* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_CLR_MSK 0xffff80ff +/* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_RESET 0x0 +/* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 field value from a register. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_GET(value) (((value) & 0x00007f00) >> 8) +/* Produces a ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value suitable for setting the register. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET(value) (((value) << 8) & 0x00007f00) + +/* + * Field : uncor_err_b3 + * + * Uncorrectable error occurred while reading pages for last transaction in Bank3. + * Uncorrectable errors also generate interrupts in intr_statusx register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_MSB 15 +/* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_WIDTH 1 +/* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK 0x00008000 +/* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_CLR_MSK 0xffff7fff +/* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_RESET 0x0 +/* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 field value from a register. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value suitable for setting the register. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_ECC_ECCCORINFO_B23. + */ +struct ALT_NAND_ECC_ECCCORINFO_B23_s +{ + const uint32_t max_errors_b2 : 7; /* ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 */ + const uint32_t uncor_err_b2 : 1; /* ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 */ + const uint32_t max_errors_b3 : 7; /* ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 */ + const uint32_t uncor_err_b3 : 1; /* ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_ECC_ECCCORINFO_B23. */ +typedef volatile struct ALT_NAND_ECC_ECCCORINFO_B23_s ALT_NAND_ECC_ECCCORINFO_B23_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_ECC_ECCCORINFO_B23 register from the beginning of the component. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_OFST 0x10 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_NAND_ECC. + */ +struct ALT_NAND_ECC_s +{ + volatile ALT_NAND_ECC_ECCCORINFO_B01_t ECCCorInfo_b01; /* ALT_NAND_ECC_ECCCORINFO_B01 */ + volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */ + volatile ALT_NAND_ECC_ECCCORINFO_B23_t ECCCorInfo_b23; /* ALT_NAND_ECC_ECCCORINFO_B23 */ +}; + +/* The typedef declaration for register group ALT_NAND_ECC. */ +typedef volatile struct ALT_NAND_ECC_s ALT_NAND_ECC_t; +/* The struct declaration for the raw register contents of register group ALT_NAND_ECC. */ +struct ALT_NAND_ECC_raw_s +{ + volatile uint32_t ECCCorInfo_b01; /* ALT_NAND_ECC_ECCCORINFO_B01 */ + volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */ + volatile uint32_t ECCCorInfo_b23; /* ALT_NAND_ECC_ECCCORINFO_B23 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_NAND_ECC. */ +typedef volatile struct ALT_NAND_ECC_raw_s ALT_NAND_ECC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : DMA registers - ALT_NAND_DMA + * DMA registers + * + * + */ +/* + * Register : dma_enable + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_EN_FLAG + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : flag + * + * Enables data DMA operation in the controller 1 - Enable DMA 0 - Disable DMA + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_EN_FLAG register field. */ +#define ALT_NAND_DMA_DMA_EN_FLAG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_EN_FLAG register field. */ +#define ALT_NAND_DMA_DMA_EN_FLAG_MSB 0 +/* The width in bits of the ALT_NAND_DMA_DMA_EN_FLAG register field. */ +#define ALT_NAND_DMA_DMA_EN_FLAG_WIDTH 1 +/* The mask used to set the ALT_NAND_DMA_DMA_EN_FLAG register field value. */ +#define ALT_NAND_DMA_DMA_EN_FLAG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_DMA_DMA_EN_FLAG register field value. */ +#define ALT_NAND_DMA_DMA_EN_FLAG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_DMA_DMA_EN_FLAG register field. */ +#define ALT_NAND_DMA_DMA_EN_FLAG_RESET 0x0 +/* Extracts the ALT_NAND_DMA_DMA_EN_FLAG field value from a register. */ +#define ALT_NAND_DMA_DMA_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_DMA_DMA_EN_FLAG register field value suitable for setting the register. */ +#define ALT_NAND_DMA_DMA_EN_FLAG_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_DMA_DMA_EN. + */ +struct ALT_NAND_DMA_DMA_EN_s +{ + uint32_t flag : 1; /* ALT_NAND_DMA_DMA_EN_FLAG */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_DMA_DMA_EN. */ +typedef volatile struct ALT_NAND_DMA_DMA_EN_s ALT_NAND_DMA_DMA_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_DMA_DMA_EN register from the beginning of the component. */ +#define ALT_NAND_DMA_DMA_EN_OFST 0x0 + +/* + * Register : dma_intr + * + * DMA interrupt register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_TGT_ERROR + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : target_error + * + * Controller initiator interface received an ERROR target response for a + * transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */ +#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */ +#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_MSB 0 +/* The width in bits of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */ +#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_WIDTH 1 +/* The mask used to set the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field value. */ +#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field value. */ +#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field. */ +#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_RESET 0x0 +/* Extracts the ALT_NAND_DMA_DMA_INTR_TGT_ERROR field value from a register. */ +#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_DMA_DMA_INTR_TGT_ERROR register field value suitable for setting the register. */ +#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_DMA_DMA_INTR. + */ +struct ALT_NAND_DMA_DMA_INTR_s +{ + uint32_t target_error : 1; /* ALT_NAND_DMA_DMA_INTR_TGT_ERROR */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_DMA_DMA_INTR. */ +typedef volatile struct ALT_NAND_DMA_DMA_INTR_s ALT_NAND_DMA_DMA_INTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_DMA_DMA_INTR register from the beginning of the component. */ +#define ALT_NAND_DMA_DMA_INTR_OFST 0x20 + +/* + * Register : dma_intr_en + * + * Enables corresponding interrupt bit in dma interrupt register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : target_error + * + * Controller initiator interface received an ERROR target response for a + * transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */ +#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */ +#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_MSB 0 +/* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */ +#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_WIDTH 1 +/* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value. */ +#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value. */ +#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field. */ +#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_RESET 0x0 +/* Extracts the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR field value from a register. */ +#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value suitable for setting the register. */ +#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_DMA_DMA_INTR_EN. + */ +struct ALT_NAND_DMA_DMA_INTR_EN_s +{ + uint32_t target_error : 1; /* ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_DMA_DMA_INTR_EN. */ +typedef volatile struct ALT_NAND_DMA_DMA_INTR_EN_s ALT_NAND_DMA_DMA_INTR_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_DMA_DMA_INTR_EN register from the beginning of the component. */ +#define ALT_NAND_DMA_DMA_INTR_EN_OFST 0x30 + +/* + * Register : target_err_addr_lo + * + * Transaction address for which controller initiator interface received an ERROR + * target response. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Least significant 16 bits + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field value. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field value. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE field value from a register. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_LO. + */ +struct ALT_NAND_DMA_TGT_ERR_ADDR_LO_s +{ + const uint32_t value : 16; /* ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_LO. */ +typedef volatile struct ALT_NAND_DMA_TGT_ERR_ADDR_LO_s ALT_NAND_DMA_TGT_ERR_ADDR_LO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_DMA_TGT_ERR_ADDR_LO register from the beginning of the component. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST 0x40 + +/* + * Register : target_err_addr_hi + * + * Transaction address for which controller initiator interface received an ERROR + * target response. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [15:0] | R | 0x0 | ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Most significant 16 bits + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field value. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field value. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_RESET 0x0 +/* Extracts the ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE field value from a register. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_HI. + */ +struct ALT_NAND_DMA_TGT_ERR_ADDR_HI_s +{ + const uint32_t value : 16; /* ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_DMA_TGT_ERR_ADDR_HI. */ +typedef volatile struct ALT_NAND_DMA_TGT_ERR_ADDR_HI_s ALT_NAND_DMA_TGT_ERR_ADDR_HI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_DMA_TGT_ERR_ADDR_HI register from the beginning of the component. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST 0x50 + +/* + * Register : flash_burst_length + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------------- + * [1:0] | RW | 0x1 | ALT_NAND_DMA_FLSH_BURST_LEN_VALUE + * [3:2] | ??? | 0x0 | *UNDEFINED* + * [4] | RW | 0x0 | ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST + * [7:5] | ??? | 0x0 | *UNDEFINED* + * [31:8] | RW | 0x0 | ALT_NAND_DMA_FLSH_BURST_LEN_RSVD + * + */ +/* + * Field : value + * + * Sets the burst used by data dma for transferring data to/from flash device. This + * burst length is different and is larger than the burst length on the host bus so + * that larger amount of data can be transferred to/from device, descreasing + * controller data transfer overhead in the process. 00 - 64 bytes, 01 - 128 bytes, + * 10 - 256 bytes, 11 - 512 bytes. The host burst size multiplied by the number of + * outstanding requests on the host side should be greater than equal to this + * value. If not, the device side burst length will be equal to host side burst + * length. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_MSB 1 +/* The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_WIDTH 2 +/* The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET_MSK 0x00000003 +/* The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_CLR_MSK 0xfffffffc +/* The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_RESET 0x1 +/* Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE field value from a register. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : continous_burst + * + * When this bit is set, the Data DMA will burst the entire page from/to the flash + * device. Please make sure that the host system can provide/sink data at a fast + * pace to avoid unnecessary pausing of data on the device interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_MSB 4 +/* The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_WIDTH 1 +/* The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_RESET 0x0 +/* Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST field value from a register. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value suitable for setting the register. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : reserved + * + * Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_MSB 31 +/* The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_WIDTH 24 +/* The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field value. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_SET_MSK 0xffffff00 +/* The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field value. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_CLR_MSK 0x000000ff +/* The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_RESET 0x0 +/* Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_RSVD field value from a register. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_GET(value) (((value) & 0xffffff00) >> 8) +/* Produces a ALT_NAND_DMA_FLSH_BURST_LEN_RSVD register field value suitable for setting the register. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_SET(value) (((value) << 8) & 0xffffff00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_DMA_FLSH_BURST_LEN. + */ +struct ALT_NAND_DMA_FLSH_BURST_LEN_s +{ + uint32_t value : 2; /* ALT_NAND_DMA_FLSH_BURST_LEN_VALUE */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t continous_burst : 1; /* ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t reserved : 24; /* ALT_NAND_DMA_FLSH_BURST_LEN_RSVD */ +}; + +/* The typedef declaration for register ALT_NAND_DMA_FLSH_BURST_LEN. */ +typedef volatile struct ALT_NAND_DMA_FLSH_BURST_LEN_s ALT_NAND_DMA_FLSH_BURST_LEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_DMA_FLSH_BURST_LEN register from the beginning of the component. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_OFST 0x70 + +/* + * Register : chip_interleave_enable_and_allow_int_reads + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN + * [3:1] | ??? | 0x0 | *UNDEFINED* + * [4] | RW | 0x1 | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : chip_interleave_enable + * + * This bit informs the controller to enable or disable interleaving among + * banks/LUNS to increase the net performance of the controller. [list][*]1 - + * Enable interleaving [*]0 - Disable Interleaving[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */ +#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */ +#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_MSB 0 +/* The width in bits of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */ +#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_WIDTH 1 +/* The mask used to set the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value. */ +#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value. */ +#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field. */ +#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_RESET 0x0 +/* Extracts the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN field value from a register. */ +#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value suitable for setting the register. */ +#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : allow_int_reads_within_luns + * + * This bit informs the controller to enable or disable simultaneous read accesses + * to different LUNS in the same bank. This bit is of importance only if the + * controller supports interleaved operations among LUNs and if the device has + * multiple LUNS. If the bit is disabled, the controller will send read commands to + * different LUNS of of the same bank only sequentially and if enabled, the + * controller will issue simultaneous read accesses to LUNS of same bank if + * required. [list][*]1 - Enable [*]0 - Disable[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */ +#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */ +#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_MSB 4 +/* The width in bits of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */ +#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_WIDTH 1 +/* The mask used to set the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value. */ +#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value. */ +#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_CLR_MSK 0xffffffef +/* The reset value of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field. */ +#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_RESET 0x1 +/* Extracts the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS field value from a register. */ +#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value suitable for setting the register. */ +#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_DMA_INTRLV. + */ +struct ALT_NAND_DMA_INTRLV_s +{ + uint32_t chip_interleave_enable : 1; /* ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t allow_int_reads_within_luns : 1; /* ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_DMA_INTRLV. */ +typedef volatile struct ALT_NAND_DMA_INTRLV_s ALT_NAND_DMA_INTRLV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_DMA_INTRLV register from the beginning of the component. */ +#define ALT_NAND_DMA_INTRLV_OFST 0x80 + +/* + * Register : no_of_blocks_per_lun + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [3:0] | RW | 0xf | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * Indicates the first block of next LUN. This information is used for extracting + * the target LUN during LUN interleaving. After Initialization, if the controller + * detects an ONFi device, this field is automatically updated by the controller. + * For other devices, software will need to write to this register for proper + * interleaving. The value in this register is interpreted as follows- [list][*]0 - + * Next LUN starts from 1024. [*]1 - Next LUN starts from 2048. [*]2 - Next LUN + * starts from 4096 and so on... [/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3 +/* The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4 +/* The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f +/* The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf +/* Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE field value from a register. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN. + */ +struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s +{ + uint32_t value : 4; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN. */ +typedef volatile struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register from the beginning of the component. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0x90 + +/* + * Register : lun_status_cmd + * + * Indicates the command to be sent while checking status of the next LUN. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:-------------------------------- + * [15:0] | RW | 0x7878 | ALT_NAND_DMA_LUN_STAT_CMD_VALUE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : value + * + * [list][*]7:0 - Indicates the command to check the status of the first LUN/Die. + * [*]15:8 - Indicates the command to check the status of the other LUN/Die.[/list] + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_MSB 15 +/* The width in bits of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_WIDTH 16 +/* The mask used to set the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field value. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field value. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_RESET 0x7878 +/* Extracts the ALT_NAND_DMA_LUN_STAT_CMD_VALUE field value from a register. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_NAND_DMA_LUN_STAT_CMD_VALUE register field value suitable for setting the register. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_NAND_DMA_LUN_STAT_CMD. + */ +struct ALT_NAND_DMA_LUN_STAT_CMD_s +{ + uint32_t value : 16; /* ALT_NAND_DMA_LUN_STAT_CMD_VALUE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_NAND_DMA_LUN_STAT_CMD. */ +typedef volatile struct ALT_NAND_DMA_LUN_STAT_CMD_s ALT_NAND_DMA_LUN_STAT_CMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_NAND_DMA_LUN_STAT_CMD register from the beginning of the component. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_OFST 0xa0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_NAND_DMA. + */ +struct ALT_NAND_DMA_s +{ + volatile ALT_NAND_DMA_DMA_EN_t dma_enable; /* ALT_NAND_DMA_DMA_EN */ + volatile uint32_t _pad_0x4_0x1f[7]; /* *UNDEFINED* */ + volatile ALT_NAND_DMA_DMA_INTR_t dma_intr; /* ALT_NAND_DMA_DMA_INTR */ + volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_DMA_DMA_INTR_EN_t dma_intr_en; /* ALT_NAND_DMA_DMA_INTR_EN */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_DMA_TGT_ERR_ADDR_LO_t target_err_addr_lo; /* ALT_NAND_DMA_TGT_ERR_ADDR_LO */ + volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_DMA_TGT_ERR_ADDR_HI_t target_err_addr_hi; /* ALT_NAND_DMA_TGT_ERR_ADDR_HI */ + volatile uint32_t _pad_0x54_0x6f[7]; /* *UNDEFINED* */ + volatile ALT_NAND_DMA_FLSH_BURST_LEN_t flash_burst_length; /* ALT_NAND_DMA_FLSH_BURST_LEN */ + volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_DMA_INTRLV_t chip_interleave_enable_and_allow_int_reads; /* ALT_NAND_DMA_INTRLV */ + volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t no_of_blocks_per_lun; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN */ + volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */ + volatile ALT_NAND_DMA_LUN_STAT_CMD_t lun_status_cmd; /* ALT_NAND_DMA_LUN_STAT_CMD */ +}; + +/* The typedef declaration for register group ALT_NAND_DMA. */ +typedef volatile struct ALT_NAND_DMA_s ALT_NAND_DMA_t; +/* The struct declaration for the raw register contents of register group ALT_NAND_DMA. */ +struct ALT_NAND_DMA_raw_s +{ + volatile uint32_t dma_enable; /* ALT_NAND_DMA_DMA_EN */ + volatile uint32_t _pad_0x4_0x1f[7]; /* *UNDEFINED* */ + volatile uint32_t dma_intr; /* ALT_NAND_DMA_DMA_INTR */ + volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */ + volatile uint32_t dma_intr_en; /* ALT_NAND_DMA_DMA_INTR_EN */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile uint32_t target_err_addr_lo; /* ALT_NAND_DMA_TGT_ERR_ADDR_LO */ + volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */ + volatile uint32_t target_err_addr_hi; /* ALT_NAND_DMA_TGT_ERR_ADDR_HI */ + volatile uint32_t _pad_0x54_0x6f[7]; /* *UNDEFINED* */ + volatile uint32_t flash_burst_length; /* ALT_NAND_DMA_FLSH_BURST_LEN */ + volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */ + volatile uint32_t chip_interleave_enable_and_allow_int_reads; /* ALT_NAND_DMA_INTRLV */ + volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */ + volatile uint32_t no_of_blocks_per_lun; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN */ + volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */ + volatile uint32_t lun_status_cmd; /* ALT_NAND_DMA_LUN_STAT_CMD */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_NAND_DMA. */ +typedef volatile struct ALT_NAND_DMA_raw_s ALT_NAND_DMA_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_NAND. + */ +struct ALT_NAND_s +{ + volatile ALT_NAND_CFG_t config; /* ALT_NAND_CFG */ + volatile uint32_t _pad_0x2b4_0x2ff[19]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_t param; /* ALT_NAND_PARAM */ + volatile uint32_t _pad_0x3f4_0x3ff[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_t status; /* ALT_NAND_STAT */ + volatile uint32_t _pad_0x544_0x64f[67]; /* *UNDEFINED* */ + volatile ALT_NAND_ECC_t ecc; /* ALT_NAND_ECC */ + volatile uint32_t _pad_0x664_0x6ff[39]; /* *UNDEFINED* */ + volatile ALT_NAND_DMA_t dma; /* ALT_NAND_DMA */ + volatile uint32_t _pad_0x7a4_0x800[23]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_NAND. */ +typedef volatile struct ALT_NAND_s ALT_NAND_t; +/* The struct declaration for the raw register contents of register group ALT_NAND. */ +struct ALT_NAND_raw_s +{ + volatile ALT_NAND_CFG_raw_t config; /* ALT_NAND_CFG */ + volatile uint32_t _pad_0x2b4_0x2ff[19]; /* *UNDEFINED* */ + volatile ALT_NAND_PARAM_raw_t param; /* ALT_NAND_PARAM */ + volatile uint32_t _pad_0x3f4_0x3ff[3]; /* *UNDEFINED* */ + volatile ALT_NAND_STAT_raw_t status; /* ALT_NAND_STAT */ + volatile uint32_t _pad_0x544_0x64f[67]; /* *UNDEFINED* */ + volatile ALT_NAND_ECC_raw_t ecc; /* ALT_NAND_ECC */ + volatile uint32_t _pad_0x664_0x6ff[39]; /* *UNDEFINED* */ + volatile ALT_NAND_DMA_raw_t dma; /* ALT_NAND_DMA */ + volatile uint32_t _pad_0x7a4_0x800[23]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_NAND. */ +typedef volatile struct ALT_NAND_raw_s ALT_NAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_NAND_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_nanddata.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_nanddata.h new file mode 100644 index 000000000..6f26f934d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_nanddata.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_NANDDATA */ + +#ifndef __ALTERA_ALT_NANDDATA_H__ +#define __ALTERA_ALT_NANDDATA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : NAND Controller Module Data (AXI Slave) - ALT_NANDDATA + * NAND Controller Module Data (AXI Slave) + * + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_NANDDATA_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_ocram.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_ocram.h new file mode 100644 index 000000000..12e7b3754 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_ocram.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_OCRAM */ + +#ifndef __ALTERA_ALT_OCRAM_H__ +#define __ALTERA_ALT_OCRAM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : On-chip RAM Module - ALT_OCRAM + * On-chip RAM Module + * + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_OCRAM_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_qspi.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_qspi.h new file mode 100644 index 000000000..183318a77 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_qspi.h @@ -0,0 +1,5951 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_QSPI */ + +#ifndef __ALTERA_ALT_QSPI_H__ +#define __ALTERA_ALT_QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : QSPI Flash Controller Module Registers - ALT_QSPI + * QSPI Flash Controller Module Registers + * + * Registers in the QSPI Flash Controller module accessible via its APB slave + * + */ +/* + * Register : QSPI Configuration Register - cfg + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | QSPI Enable + * [1] | RW | 0x0 | Clock Polarity + * [2] | RW | 0x0 | Select Clock Phase + * [6:3] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | Enable Direct Access Controller + * [8] | RW | 0x0 | Legacy IP Mode Enable + * [9] | RW | 0x0 | Peripheral select decode + * [13:10] | RW | 0x0 | Peripheral Chip Select Lines + * [14] | RW | 0x0 | Write Protect Flash Pin + * [15] | RW | 0x0 | Enable DMA Peripheral Interface + * [16] | RW | 0x0 | Enable AHB Address Re-mapping + * [17] | RW | 0x0 | Enter XIP Mode on next READ + * [18] | RW | 0x0 | Enter XIP Mode Immediately + * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor + * [30:23] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x0 | Serial interface and QSPI pipeline is IDLE + * + */ +/* + * Field : QSPI Enable - en + * + * If this bit is disabled, the QSPI will finish the current transfer of the data + * word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output + * enables are inactive and all pins are set to input mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------|:------|:----------------- + * ALT_QSPI_CFG_EN_E_DIS | 0x0 | Disable the QSPI + * ALT_QSPI_CFG_EN_E_EN | 0x1 | Enable the QSPI + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_EN + * + * Disable the QSPI + */ +#define ALT_QSPI_CFG_EN_E_DIS 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_EN + * + * Enable the QSPI + */ +#define ALT_QSPI_CFG_EN_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_MSB 0 +/* The width in bits of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_EN register field value. */ +#define ALT_QSPI_CFG_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_CFG_EN register field value. */ +#define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_CFG_EN register field. */ +#define ALT_QSPI_CFG_EN_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_EN field value from a register. */ +#define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Clock Polarity - selclkpol + * + * Controls spiclk modes of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------- + * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low + * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL + * + * SPI clock is quiescent low + */ +#define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL + * + * SPI clock is quiescent high + */ +#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_MSB 1 +/* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */ +#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */ +#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */ +#define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */ +#define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Select Clock Phase - selclkphase + * + * Selects whether the clock is in an active or inactive phase outside the SPI + * word. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:--------------------------- + * ALT_QSPI_CFG_SELCLKPHASE_E_ACT | 0x0 | SPI clock is quiescent low + * ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1 | Clock Inactive + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE + * + * SPI clock is quiescent low + */ +#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE + * + * Clock Inactive + */ +#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_MSB 2 +/* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */ +#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */ +#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */ +#define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */ +#define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Enable Direct Access Controller - endiracc + * + * If disabled, the Direct Access Controller becomes inactive once the current + * transfer of the data word (FF_W) is complete. When the Direct Access Controller + * and Indirect Access Controller are both disabled, all AHB requests are completed + * with an error response. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0 | Disable Direct Access Ctrl + * ALT_QSPI_CFG_ENDIRACC_E_EN | 0x1 | Enable Direct Access Ctrl + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC + * + * Disable Direct Access Ctrl + */ +#define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC + * + * Enable Direct Access Ctrl + */ +#define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_MSB 7 +/* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */ +#define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */ +#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */ +#define ALT_QSPI_CFG_ENDIRACC_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */ +#define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Legacy IP Mode Enable - enlegacyip + * + * This bit can select the Direct Access Controller/Indirect Access Controller or + * legacy mode.If legacy mode is selected, any write to the controller via the AHB + * interface is serialized and sent to the FLASH device. Any valid AHB read will + * pop the internal RX-FIFO, retrieving data that was forwarded by the external + * FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and + * controlled via the HSIZE input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------------------------------- + * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1 | Legacy Mode + * ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD | 0x0 | Use Direct/Indirect Access Controller + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP + * + * Legacy Mode + */ +#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP + * + * Use Direct/Indirect Access Controller + */ +#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_MSB 8 +/* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */ +#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */ +#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */ +#define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */ +#define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Peripheral select decode - perseldec + * + * Select between '1 of 4 selects' or 'external 4-to-16 decode'. The + * qspi_n_ss_out[3:0] output signals are controlled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------- + * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode + * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0] + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC + * + * Select external 4-to-16 decode + */ +#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC + * + * Selects 1 of 4 qspi_n_ss_out[3:0] + */ +#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_MSB 9 +/* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */ +#define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */ +#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */ +#define ALT_QSPI_CFG_PERSELDEC_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */ +#define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Peripheral Chip Select Lines - percslines + * + * Peripheral chip select line output decode type. As per perseldec, if perseldec = + * 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The + * asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0] + * require an external 4 to 16 decoder. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_MSB 13 +/* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_WIDTH 4 +/* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */ +#define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00 +/* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */ +#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff +/* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */ +#define ALT_QSPI_CFG_PERCSLINES_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */ +#define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10) +/* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00) + +/* + * Field : Write Protect Flash Pin - wp + * + * This bit controls the write protect pin of the flash devices. The signal + * qspi_mo2_wpn needs to be resynchronized to the generated memory clock as + * necessary. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------- + * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect + * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_WP + * + * Enable Write Protect + */ +#define ALT_QSPI_CFG_WP_E_WRPROTON 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_WP + * + * Disable Write Protect + */ +#define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_MSB 14 +/* The width in bits of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_WP register field value. */ +#define ALT_QSPI_CFG_WP_SET_MSK 0x00004000 +/* The mask used to clear the ALT_QSPI_CFG_WP register field value. */ +#define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff +/* The reset value of the ALT_QSPI_CFG_WP register field. */ +#define ALT_QSPI_CFG_WP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_WP field value from a register. */ +#define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Enable DMA Peripheral Interface - endma + * + * Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer + * requests via the DMA peripheral interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_QSPI_CFG_ENDMA_E_EN | 0x1 | Enable DMA Mode + * ALT_QSPI_CFG_ENDMA_E_DIS | 0x0 | Disable DMA Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDMA + * + * Enable DMA Mode + */ +#define ALT_QSPI_CFG_ENDMA_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENDMA + * + * Disable DMA Mode + */ +#define ALT_QSPI_CFG_ENDMA_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_MSB 15 +/* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */ +#define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */ +#define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_QSPI_CFG_ENDMA register field. */ +#define ALT_QSPI_CFG_ENDMA_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */ +#define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Enable AHB Address Re-mapping - enahbremap + * + * (Direct Access Mode Only) When enabled, the incoming AHB address will be adapted + * and sent to the FLASH device as (address + N), where N is the value stored in + * the remap address register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------- + * ALT_QSPI_CFG_ENAHBREMAP_E_EN | 0x1 | Enable AHB Re-mapping + * ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0 | Disable AHB Re-mapping + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP + * + * Enable AHB Re-mapping + */ +#define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP + * + * Disable AHB Re-mapping + */ +#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_MSB 16 +/* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */ +#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000 +/* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */ +#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff +/* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */ +#define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */ +#define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Enter XIP Mode on next READ - enterxipnextrd + * + * If XIP is enabled, then setting to disabled will cause the controller to exit + * XIP mode on the next READ instruction. If XIP is disabled, then setting to + * enabled will inform the controller that the device is ready to enter XIP on the + * next READ instruction. The controller will therefore send the appropriate + * command sequence, including mode bits to cause the device to enter XIP mode. Use + * this register after the controller has ensured the FLASH device has been + * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit + * should be set to 0. This will take effect in the attached device only AFTER the + * next READ instruction is executed. Software should therefore ensure that at + * least one READ instruction is requested after resetting this bit before it can + * be sure XIP mode in the device is exited. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------------- + * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN | 0x1 | Enter XIP Mode on next READ instruction + * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0 | Exit XIP Mode on next READ instruction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD + * + * Enter XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD + * + * Exit XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17 +/* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000 +/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff +/* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Enter XIP Mode Immediately - enterxipimm + * + * If XIP is enabled, then setting to disabled will cause the controller to exit + * XIP mode on the next READ instruction. If XIP is disabled, then setting enable + * will operate the device in XIP mode immediately. Use this register when the + * external device wakes up in XIP mode (as per the contents of its non- volatile + * configuration register). The controller will assume the next READ instruction + * will be passed to the device as an XIP instruction, and therefore will not + * require the READ opcode to be transferred. Note: To exit XIP mode, this bit + * should be set to 0. This will take effect in the attached device only after the + * next READ instruction is executed. Software therefore should ensure that at + * least one READ instruction is requested after resetting this bit in order to be + * sure that XIP mode is exited. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:--------------------------------------- + * ALT_QSPI_CFG_ENTERXIPIMM_E_EN | 0x1 | Enter XIP Mode immediately + * ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0 | Exit XIP Mode on next READ instruction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM + * + * Enter XIP Mode immediately + */ +#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM + * + * Exit XIP Mode on next READ instruction + */ +#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18 +/* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000 +/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff +/* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Master Mode Baud Rate Divisor - bauddiv + * + * SPI baud rate = ref_clk / (2 * baud_rate_divisor) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------- + * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30 + * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/2 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/4 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/6 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/8 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/10 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/12 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/14 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/16 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/18 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/20 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9 +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/22 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/24 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/26 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/28 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/30 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe +/* + * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV + * + * Baud Rate Div/32 + */ +#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_MSB 22 +/* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_WIDTH 4 +/* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */ +#define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000 +/* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */ +#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff +/* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */ +#define ALT_QSPI_CFG_BAUDDIV_RESET 0xf +/* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */ +#define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19) +/* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000) + +/* + * Field : Serial interface and QSPI pipeline is IDLE - idle + * + * This is a STATUS read-only bit. Note this is a retimed signal, so there will be + * some inherent delay on the generation of this status signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------- + * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode + * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_CFG_IDLE + * + * Idle Mode + */ +#define ALT_QSPI_CFG_IDLE_E_SET 0x1 +/* + * Enumerated value for register field ALT_QSPI_CFG_IDLE + * + * Non-Idle Mode + */ +#define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_MSB 31 +/* The width in bits of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_WIDTH 1 +/* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */ +#define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */ +#define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_QSPI_CFG_IDLE register field. */ +#define ALT_QSPI_CFG_IDLE_RESET 0x0 +/* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */ +#define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */ +#define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_CFG. + */ +struct ALT_QSPI_CFG_s +{ + uint32_t en : 1; /* QSPI Enable */ + uint32_t selclkpol : 1; /* Clock Polarity */ + uint32_t selclkphase : 1; /* Select Clock Phase */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t endiracc : 1; /* Enable Direct Access Controller */ + uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */ + uint32_t perseldec : 1; /* Peripheral select decode */ + uint32_t percslines : 4; /* Peripheral Chip Select Lines */ + uint32_t wp : 1; /* Write Protect Flash Pin */ + uint32_t endma : 1; /* Enable DMA Peripheral Interface */ + uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */ + uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */ + uint32_t enterxipimm : 1; /* Enter XIP Mode Immediately */ + uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */ + uint32_t : 8; /* *UNDEFINED* */ + const uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */ +}; + +/* The typedef declaration for register ALT_QSPI_CFG. */ +typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */ +#define ALT_QSPI_CFG_OFST 0x0 + +/* + * Register : Device Read Instruction Register - devrd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode + * [9:8] | RW | 0x0 | Instruction Transfer Width + * [11:10] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | Address Transfer Width + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [17:16] | RW | 0x0 | Data Transfer Width + * [19:18] | ??? | 0x0 | *UNDEFINED* + * [20] | RW | 0x0 | Mode Bit Enable + * [23:21] | ??? | 0x0 | *UNDEFINED* + * [28:24] | RW | 0x0 | Dummy Read Clock Cycles + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read Opcode in non-XIP mode - rdopcode + * + * Read Opcode to use when not in XIP mode + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_QSPI_DEVRD_RDOPCODE_E_RD | 0x3 | Read Opcode in Non-XIP mode + * ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb | Fast Read in Non-XIP mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE + * + * Read Opcode in Non-XIP mode + */ +#define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE + * + * Fast Read in Non-XIP mode + */ +#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_MSB 7 +/* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */ +#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */ +#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */ +#define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3 +/* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */ +#define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Instruction Transfer Width - instwidth + * + * Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions + * sent to SPI flash device (not just read instructions). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all + * : | | SPI flash devices. + * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1. + * : | | Supported by all SPI flash devices that support + * : | | the Dual SP (DIO-SPI) Protocol. + * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by all SPI flash devices that + * : | | support the Quad SP (QIO-SPI) Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0. Supported by all SPI flash devices. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that + * support the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH + * + * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash + * devices that support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9 +/* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300 +/* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff +/* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : Address Transfer Width - addrwidth + * + * Sets read address transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by + * : | | all SPI flash devices + * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by some SPI flash devices that + * : | | support the Extended SPI Protocol and by all SPI + * : | | flash devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices + * that support the Extended SPI Protocol and by all SPI flash devices that support + * the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH + * + * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13 +/* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000 +/* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff +/* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Data Transfer Width - datawidth + * + * Sets read data transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all + * : | | SPI flash devices + * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported + * : | | by some SPI flash devices that support the + * : | | Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that + * support the Extended SPI Protocol and by all SPI flash devices that support the + * Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH + * + * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17 +/* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Mode Bit Enable - enmodebits + * + * If this bit is set, the mode bits as defined in the Mode Bit Configuration + * register are sent following the address bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------- + * ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0 | No Order + * ALT_QSPI_DEVRD_ENMODBITS_E_ORDER | 0x1 | Mode Bits follow address bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS + * + * No Order + */ +#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS + * + * Mode Bits follow address bytes + */ +#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_MSB 20 +/* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1 +/* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */ +#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000 +/* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */ +#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff +/* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */ +#define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */ +#define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Dummy Read Clock Cycles - dummyrdclks + * + * Number of dummy clock cycles required by device for read instruction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28 +/* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVRD. + */ +struct ALT_QSPI_DEVRD_s +{ + uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */ + uint32_t instwidth : 2; /* Instruction Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t addrwidth : 2; /* Address Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t datawidth : 2; /* Data Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t enmodebits : 1; /* Mode Bit Enable */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVRD. */ +typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */ +#define ALT_QSPI_DEVRD_OFST 0x4 + +/* + * Register : Device Write Instruction Register - devwr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [7:0] | RW | 0x2 | Write Opcode + * [11:8] | ??? | 0x0 | *UNDEFINED* + * [13:12] | RW | 0x0 | Address Transfer Width + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [17:16] | RW | 0x0 | Data Transfer Width + * [23:18] | ??? | 0x0 | *UNDEFINED* + * [28:24] | RW | 0x0 | Dummy Write Clock Cycles + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Opcode - wropcode + * + * Write Opcode + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_MSB 7 +/* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */ +#define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */ +#define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */ +#define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2 +/* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */ +#define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Address Transfer Width - addrwidth + * + * Sets write address transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by + * : | | all SPI flash devices + * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and + * : | | DQ3. Supported by some SPI flash devices that + * : | | support the Extended SPI Protocol and by all SPI + * : | | flash devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Write address transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices + * that support the Extended SPI Protocol and by all SPI flash devices that support + * the Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH + * + * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13 +/* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000 +/* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff +/* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) +/* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) + +/* + * Field : Data Transfer Width - datawidth + * + * Sets write data transfer width (1, 2, or 4 bits). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all + * : | | SPI flash devices + * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported + * : | | by some SPI flash devices that support the + * : | | Extended SPI Protocol and by all SPI flash + * : | | devices that support the Dual SP (DIO-SPI) + * : | | Protocol. + * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. + * : | | Supported by some SPI flash devices that support + * : | | the Extended SPI Protocol and by all SPI flash + * : | | devices that support the Quad SP (QIO-SPI) + * : | | Protocol. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Write data transferred on DQ0. Supported by all SPI flash devices + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that + * support the Extended SPI Protocol and by all SPI flash devices that support the + * Dual SP (DIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1 +/* + * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH + * + * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash + * devices that support the Extended SPI Protocol and by all SPI flash devices that + * support the Quad SP (QIO-SPI) Protocol. + */ +#define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17 +/* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Dummy Write Clock Cycles - dummywrclks + * + * Number of dummy clock cycles required by device for write instruction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28 +/* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000 +/* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff +/* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0 +/* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24) +/* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */ +#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVWR. + */ +struct ALT_QSPI_DEVWR_s +{ + uint32_t wropcode : 8; /* Write Opcode */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t addrwidth : 2; /* Address Transfer Width */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t datawidth : 2; /* Data Transfer Width */ + uint32_t : 6; /* *UNDEFINED* */ + uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVWR. */ +typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */ +#define ALT_QSPI_DEVWR_OFST 0x8 + +/* + * Register : QSPI Device Delay Register - delay + * + * This register is used to introduce relative delays into the generation of the + * master output signals. All timings are defined in cycles of the qspi_clk. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------- + * [7:0] | RW | 0x0 | Clock Delay with qspi_n_ss_out + * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit + * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation + * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert + * + */ +/* + * Field : Clock Delay with qspi_n_ss_out - init + * + * Delay in master reference clocks between setting qspi_n_ss_out low and first bit + * transfer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_MSB 7 +/* The width in bits of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */ +#define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */ +#define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_DELAY_INIT register field. */ +#define ALT_QSPI_DELAY_INIT_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */ +#define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Clock Delay for Last Transaction Bit - after + * + * Delay in master reference clocks between last bit of current transaction and + * deasserting the device chip select (qspi_n_ss_out). By default, the chip select + * will be deasserted on the cycle following the completion of the current + * transaction. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_MSB 15 +/* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */ +#define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */ +#define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff +/* The reset value of the ALT_QSPI_DELAY_AFTER register field. */ +#define ALT_QSPI_DELAY_AFTER_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */ +#define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Clock Delay for Chip Select Deactivation - btwn + * + * Delay in master reference clocks between one chip select being de-activated and + * the activation of another. This is used to ensure a quiet period between the + * selection of two different slaves and requires the transmit FIFO to be empty. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_MSB 23 +/* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */ +#define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */ +#define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff +/* The reset value of the ALT_QSPI_DELAY_BTWN register field. */ +#define ALT_QSPI_DELAY_BTWN_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */ +#define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Clock Delay for Chip Select Deassert - nss + * + * Delay in master reference clocks for the length that the master mode chip select + * outputs are de-asserted between transactions. The minimum delay is always + * qspi_sck_out period to ensure the chip select is never re-asserted within an + * qspi_sck_out period. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_MSB 31 +/* The width in bits of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_WIDTH 8 +/* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */ +#define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000 +/* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */ +#define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff +/* The reset value of the ALT_QSPI_DELAY_NSS register field. */ +#define ALT_QSPI_DELAY_NSS_RESET 0x0 +/* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */ +#define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */ +#define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DELAY. + */ +struct ALT_QSPI_DELAY_s +{ + uint32_t init : 8; /* Clock Delay with qspi_n_ss_out */ + uint32_t after : 8; /* Clock Delay for Last Transaction Bit */ + uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */ + uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */ +}; + +/* The typedef declaration for register ALT_QSPI_DELAY. */ +typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */ +#define ALT_QSPI_DELAY_OFST 0xc + +/* + * Register : Read Data Capture Register - rddatacap + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x1 | Bypass + * [4:1] | RW | 0x0 | Read Delay + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bypass - byp + * + * Controls bypass of the adapted loopback clock circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x0 | No Bypass + * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x1 | Bypass loopback clock circuit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP + * + * No Bypass + */ +#define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0 +/* + * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP + * + * Bypass loopback clock circuit + */ +#define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_MSB 0 +/* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_WIDTH 1 +/* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */ +#define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */ +#define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */ +#define ALT_QSPI_RDDATACAP_BYP_RESET 0x1 +/* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */ +#define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */ +#define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Read Delay - delay + * + * Delay the read data capturing logic by the programmed number of qspi_clk cycles + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_MSB 4 +/* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4 +/* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */ +#define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e +/* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */ +#define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1 +/* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */ +#define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0 +/* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */ +#define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1) +/* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */ +#define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_RDDATACAP. + */ +struct ALT_QSPI_RDDATACAP_s +{ + uint32_t byp : 1; /* Bypass */ + uint32_t delay : 4; /* Read Delay */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_RDDATACAP. */ +typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */ +#define ALT_QSPI_RDDATACAP_OFST 0x10 + +/* + * Register : Device Size Register - devsz + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [3:0] | RW | 0x2 | Number of address Bytes + * [15:4] | RW | 0x100 | Number of Bytes per Device Page + * [20:16] | RW | 0x10 | Number of Bytes per Block + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of address Bytes - numaddrbytes + * + * Number of address bytes. A value of 0 indicates 1 byte. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3 +/* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2 +/* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Number of Bytes per Device Page - bytesperdevicepage + * + * Number of bytes per device page. This is required by the controller for + * performing FLASH writes up to and across page boundaries. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15 +/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12 +/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0 +/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f +/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100 +/* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4) +/* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0) + +/* + * Field : Number of Bytes per Block - bytespersubsector + * + * Number of bytes per Block. This is required by the controller for performing the + * write protection logic. The number of bytes per block must be a power of 2 + * number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20 +/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5 +/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000 +/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff +/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10 +/* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16) +/* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DEVSZ. + */ +struct ALT_QSPI_DEVSZ_s +{ + uint32_t numaddrbytes : 4; /* Number of address Bytes */ + uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */ + uint32_t bytespersubsector : 5; /* Number of Bytes per Block */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DEVSZ. */ +typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */ +#define ALT_QSPI_DEVSZ_OFST 0x14 + +/* + * Register : SRAM Partition Register - srampart + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [6:0] | RW | 0x40 | Indirect Read Partition Size + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Indirect Read Partition Size - addr + * + * Defines the size of the indirect read partition in the SRAM, in units of SRAM + * locations. By default, half of the SRAM is reserved for indirect read operations + * and half for indirect write operations. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_MSB 6 +/* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_WIDTH 7 +/* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */ +#define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */ +#define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */ +#define ALT_QSPI_SRAMPART_ADDR_RESET 0x40 +/* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */ +#define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_SRAMPART. + */ +struct ALT_QSPI_SRAMPART_s +{ + uint32_t addr : 7; /* Indirect Read Partition Size */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_SRAMPART. */ +typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */ +#define ALT_QSPI_SRAMPART_OFST 0x18 + +/* + * Register : Indirect AHB Address Trigger Register - indaddrtrig + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Trigger Address + * + */ +/* + * Field : Trigger Address - addr + * + * This is the base address that will be used by the AHB controller. When the + * incoming AHB read access address matches a range of addresses from this trigger + * address to the trigger address + 15, then the AHB request will be completed by + * fetching data from the Indirect Controllers SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDADDRTRIG. + */ +struct ALT_QSPI_INDADDRTRIG_s +{ + uint32_t addr : 32; /* Trigger Address */ +}; + +/* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */ +typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */ +#define ALT_QSPI_INDADDRTRIG_OFST 0x1c + +/* + * Register : DMA Peripheral Register - dmaper + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [3:0] | RW | 0x0 | Number of Single Bytes + * [7:4] | ??? | 0x0 | *UNDEFINED* + * [11:8] | RW | 0x0 | Number of Burst Bytes + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of Single Bytes - numsglreqbytes + * + * Number of bytes in a single type request on the DMA peripheral request. A + * programmed value of 0 represents a single byte. This should be setup before + * starting the indirect read or write operation. The actual number of bytes used + * is 2**(value in this register) which will simplify implementation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3 +/* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Number of Burst Bytes - numburstreqbytes + * + * Number of bytes in a burst type request on the DMA peripheral request. A + * programmed value of 0 represents a single byte. This should be setup before + * starting the indirect read or write operation. The actual number of bytes used + * is 2**(value in this register) which will simplify implementation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11 +/* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4 +/* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00 +/* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff +/* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8) +/* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_DMAPER. + */ +struct ALT_QSPI_DMAPER_s +{ + uint32_t numsglreqbytes : 4; /* Number of Single Bytes */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_DMAPER. */ +typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */ +#define ALT_QSPI_DMAPER_OFST 0x20 + +/* + * Register : Remap Address Register - remapaddr + * + * This register is used to remap an incoming AHB address to a different address + * used by the FLASH device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | RW | 0x0 | Remap Address Offset + * + */ +/* + * Field : Remap Address Offset - value + * + * This offset is added to the incoming AHB address to determine the address used + * by the FLASH device. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */ +#define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */ +#define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */ +#define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */ +#define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_REMAPADDR. + */ +struct ALT_QSPI_REMAPADDR_s +{ + uint32_t value : 32; /* Remap Address Offset */ +}; + +/* The typedef declaration for register ALT_QSPI_REMAPADDR. */ +typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */ +#define ALT_QSPI_REMAPADDR_OFST 0x24 + +/* + * Register : Mode Bit Register - modebit + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Mode + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mode - mode + * + * These are the 8 mode bits that are sent to the device following the address + * bytes if mode bit transmission has been enabled. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_MSB 7 +/* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_WIDTH 8 +/* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */ +#define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff +/* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */ +#define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00 +/* The reset value of the ALT_QSPI_MODBIT_MOD register field. */ +#define ALT_QSPI_MODBIT_MOD_RESET 0x0 +/* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */ +#define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */ +#define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_MODBIT. + */ +struct ALT_QSPI_MODBIT_s +{ + uint32_t mode : 8; /* Mode */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_MODBIT. */ +typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */ +#define ALT_QSPI_MODBIT_OFST 0x28 + +/* + * Register : SRAM Fill Register - sramfill + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------- + * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS + * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS + * + */ +/* + * Field : SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - indrdpart + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15 +/* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16 +/* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000 +/* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0 +/* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - indwrpart + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31 +/* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16 +/* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff +/* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0 +/* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */ +#define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_SRAMFILL. + */ +struct ALT_QSPI_SRAMFILL_s +{ + const uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS */ + const uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS */ +}; + +/* The typedef declaration for register ALT_QSPI_SRAMFILL. */ +typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */ +#define ALT_QSPI_SRAMFILL_OFST 0x2c + +/* + * Register : TX Threshold Register - txthresh + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x1 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Defines the level at which the transmit FIFO not full interrupt is generated + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_MSB 3 +/* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4 +/* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */ +#define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1 +/* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */ +#define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_TXTHRESH. + */ +struct ALT_QSPI_TXTHRESH_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_TXTHRESH. */ +typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */ +#define ALT_QSPI_TXTHRESH_OFST 0x30 + +/* + * Register : RX Threshold Register - rxthresh + * + * Device Instruction Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [3:0] | RW | 0x1 | Level + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Level - level + * + * Defines the level at which the receive FIFO not empty interrupt is generated + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_MSB 3 +/* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4 +/* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */ +#define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */ +#define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1 +/* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */ +#define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_RXTHRESH. + */ +struct ALT_QSPI_RXTHRESH_s +{ + uint32_t level : 4; /* Level */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_RXTHRESH. */ +typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */ +#define ALT_QSPI_RXTHRESH_OFST 0x34 + +/* + * Register : Interrupt Status Register - irqstat + * + * The status fields in this register are set when the described event occurs and + * the interrupt is enabled in the mask register. When any of these bit fields are + * set, the interrupt output is asserted high. The fields are each cleared by + * writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when + * legacy SPI mode is active. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Underflow Detected + * [2] | RW | 0x0 | Indirect Operation Complete + * [3] | RW | 0x0 | Indirect Read Reject + * [4] | RW | 0x0 | Protected Area Write Attempt + * [5] | RW | 0x0 | Illegal AHB Access Detected + * [6] | RW | 0x0 | Transfer Watermark Reached + * [7] | RW | 0x0 | Receive Overflow + * [8] | RW | 0x1 | Transmit FIFO Compared to Threshold + * [9] | RW | 0x0 | Transmit FIFO Full + * [10] | RW | 0x0 | Receive FIFO Compared to Threshold + * [11] | RW | 0x0 | Receive FIFO Full + * [12] | RW | 0x0 | Indirect Read Partition overflow + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Underflow Detected - underflowdet + * + * An underflow is detected when an attempt to transfer data is made when the + * transmit FIFO is empty. This may occur when the AHB write data is being supplied + * too slowly to keep up with the requested write operation. This bit is reset only + * by a system reset and cleared only when the register is read. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow + * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET + * + * Underflow + */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET + * + * No Underflow + */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1 +/* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Operation Complete - indopdone + * + * Controller has completed last triggered indirect operation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation + * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE + * + * Completed Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE + * + * No Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Indirect Read Reject - indrdreject + * + * Indirect operation was requested but could not be accepted. Two indirect + * operations already in storage. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested + * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT + * + * Indirect Operation Requested + */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT + * + * No Indirect Operation + */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Protected Area Write Attempt - protwrattempt + * + * Write to protected area was attempted and rejected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------- + * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT | 0x1 | Write Attempt to protected area + * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0 | No Write Attempt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT + * + * Write Attempt to protected area + */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT + * + * No Write Attempt + */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4 +/* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Illegal AHB Access Detected - illegalacc + * + * Illegal AHB access has been detected. AHB wrapping bursts and the use of + * SPLIT/RETRY accesses will cause this error interrupt to trigger. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt + * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC + * + * Illegal AHB attempt + */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC + * + * No Illegal AHB attempt + */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5 +/* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transfer Watermark Reached - indxfrlvl + * + * Indirect Transfer Watermark Level Reached + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached + * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL + * + * Water level reached + */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL + * + * No water level reached + */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Overflow - rxover + * + * This should only occur in Legacy SPI mode. Set if an attempt is made to push the + * RX FIFO when it is full. This bit is reset only by a system reset and cleared + * only when this register is read. If a new push to the RX FIFO occurs coincident + * with a register read this flag will remain set. 0 : no overflow has been + * detected. 1 : an overflow has occurred. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow + * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER + * + * Receive Overflow + */ +#define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER + * + * No Receive Overflow + */ +#define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_MSB 7 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */ +#define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */ +#define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */ +#define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit FIFO Compared to Threshold - txthreshcmp + * + * Indicates the number of entries in the transmit FIFO with respect to the + * threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries + * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP + * + * FIFO has > TXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP + * + * FIFO has <= TXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8 +/* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1 +/* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Transmit FIFO Full - txfull + * + * Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy + * mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------- + * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full + * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL + * + * Transmit FIFO Not Full + */ +#define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL + * + * Transmit FIFO Full + */ +#define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_MSB 9 +/* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */ +#define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive FIFO Compared to Threshold - rxthreshcmp + * + * Indicates the number of entries in the receive FIFO with respect to the + * threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries + * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP + * + * FIFO has <= RXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP + * + * FIFO has > RXTHRESH entries + */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Receive FIFO Full - rxfull + * + * Indicates that the receive FIFO is full or not. Only relevant in SPI legacy + * mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------- + * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full + * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL + * + * Receive FIFO Not Full + */ +#define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL + * + * Receive FIFO Full + */ +#define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_MSB 11 +/* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */ +#define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */ +#define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Indirect Read Partition overflow - indsramfull + * + * Indirect Read Partition of SRAM is full and unable to immediately complete + * indirect operation + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------- + * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full + * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL + * + * SRAM is full + */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1 +/* + * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL + * + * SRAM is not full + */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12 +/* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff +/* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_IRQSTAT. + */ +struct ALT_QSPI_IRQSTAT_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t underflowdet : 1; /* Underflow Detected */ + uint32_t indopdone : 1; /* Indirect Operation Complete */ + uint32_t indrdreject : 1; /* Indirect Read Reject */ + uint32_t protwrattempt : 1; /* Protected Area Write Attempt */ + uint32_t illegalacc : 1; /* Illegal AHB Access Detected */ + uint32_t indxfrlvl : 1; /* Transfer Watermark Reached */ + uint32_t rxover : 1; /* Receive Overflow */ + uint32_t txthreshcmp : 1; /* Transmit FIFO Compared to Threshold */ + uint32_t txfull : 1; /* Transmit FIFO Full */ + uint32_t rxthreshcmp : 1; /* Receive FIFO Compared to Threshold */ + uint32_t rxfull : 1; /* Receive FIFO Full */ + uint32_t indsramfull : 1; /* Indirect Read Partition overflow */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_IRQSTAT. */ +typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */ +#define ALT_QSPI_IRQSTAT_OFST 0x40 + +/* + * Register : Interrupt Mask - irqmask + * + * If disabled, the interrupt for the corresponding interrupt status register bit + * is disabled. If enabled, the interrupt for the corresponding interrupt status + * register bit is enabled. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Underflow Detected Mask + * [2] | RW | 0x0 | Mask + * [3] | RW | 0x0 | Indirect Read Reject Mask + * [4] | RW | 0x0 | Protected Area Write Attempt Mask + * [5] | RW | 0x0 | Illegal Access Detected Mask + * [6] | RW | 0x0 | Transfer Watermark Breach Mask + * [7] | RW | 0x0 | Receive Overflow Mask + * [8] | RW | 0x0 | Transmit FIFO Threshold Compare Mask + * [9] | RW | 0x0 | Transmit FIFO Full Mask + * [10] | RW | 0x0 | Receive FIFO Threshold Compare Mask + * [11] | RW | 0x0 | Receive FIFO full Mask + * [12] | RW | 0x0 | Indirect Read Partition overflow mask + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Underflow Detected Mask - underflowdet + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1 +/* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Mask - indopdone + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDOPDONE_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2 +/* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Indirect Read Reject Mask - indrdreject + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDRDREJECT_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3 +/* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Protected Area Write Attempt Mask - protwrattempt + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4 +/* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Illegal Access Detected Mask - illegalacc + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_ILLEGALACC_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5 +/* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transfer Watermark Breach Mask - indxfrlvl + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDXFRLVL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6 +/* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receive Overflow Mask - rxover + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXOVER_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_MSB 7 +/* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */ +#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */ +#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f +/* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */ +#define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */ +#define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transmit FIFO Threshold Compare Mask - txthreshcmp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8 +/* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Transmit FIFO Full Mask - txfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_TXFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_MSB 9 +/* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */ +#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200 +/* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */ +#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff +/* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */ +#define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Receive FIFO Threshold Compare Mask - rxthreshcmp + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10 +/* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Receive FIFO full Mask - rxfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_RXFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_MSB 11 +/* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */ +#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */ +#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */ +#define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Indirect Read Partition overflow mask - indsramfull + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0 | Disable Interrupt by Masking + * ALT_QSPI_IRQMSK_INDSRAMFULL_E_END | 0x1 | Enable Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL + * + * Disable Interrupt by Masking + */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL + * + * Enable Interrupt + */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12 +/* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000 +/* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff +/* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_IRQMSK. + */ +struct ALT_QSPI_IRQMSK_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t underflowdet : 1; /* Underflow Detected Mask */ + uint32_t indopdone : 1; /* Mask */ + uint32_t indrdreject : 1; /* Indirect Read Reject Mask */ + uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */ + uint32_t illegalacc : 1; /* Illegal Access Detected Mask */ + uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */ + uint32_t rxover : 1; /* Receive Overflow Mask */ + uint32_t txthreshcmp : 1; /* Transmit FIFO Threshold Compare Mask */ + uint32_t txfull : 1; /* Transmit FIFO Full Mask */ + uint32_t rxthreshcmp : 1; /* Receive FIFO Threshold Compare Mask */ + uint32_t rxfull : 1; /* Receive FIFO full Mask */ + uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_IRQMSK. */ +typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */ +#define ALT_QSPI_IRQMSK_OFST 0x44 + +/* + * Register : Lower Write Protection Register - lowwrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | RW | 0x0 | Block Number + * + */ +/* + * Field : Block Number - subsector + * + * The block number that defines the lower block in the range of blocks that is to + * be locked from writing. The definition of a block in terms of number of bytes is + * programmable via the Device Size Configuration register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31 +/* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32 +/* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0 +/* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_LOWWRPROT. + */ +struct ALT_QSPI_LOWWRPROT_s +{ + uint32_t subsector : 32; /* Block Number */ +}; + +/* The typedef declaration for register ALT_QSPI_LOWWRPROT. */ +typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */ +#define ALT_QSPI_LOWWRPROT_OFST 0x50 + +/* + * Register : Upper Write Protection Register - uppwrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [31:0] | RW | 0x0 | Block Number + * + */ +/* + * Field : Block Number - subsector + * + * The block number that defines the upper block in the range of blocks that is to + * be locked from writing. The definition of a block in terms of number of bytes is + * programmable via the Device Size Configuration register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31 +/* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32 +/* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0 +/* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */ +#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_UPPWRPROT. + */ +struct ALT_QSPI_UPPWRPROT_s +{ + uint32_t subsector : 32; /* Block Number */ +}; + +/* The typedef declaration for register ALT_QSPI_UPPWRPROT. */ +typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */ +#define ALT_QSPI_UPPWRPROT_OFST 0x54 + +/* + * Register : Write Protection Register - wrprot + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [0] | RW | 0x0 | Write Protection Inversion Bit + * [1] | RW | 0x0 | Write Protection Enable Bit + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Protection Inversion Bit - inv + * + * When enabled, the protection region defined in the lower and upper write + * protection registers is inverted meaning it is the region that the system is + * permitted to write to. When disabled, the protection region defined in the lower + * and upper write protection registers is the region that the system is not + * permitted to write to. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------- + * ALT_QSPI_WRPROT_INV_E_EN | 0x1 | Write Region allowed + * ALT_QSPI_WRPROT_INV_E_DIS | 0x0 | Write Region not allowed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_WRPROT_INV + * + * Write Region allowed + */ +#define ALT_QSPI_WRPROT_INV_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_WRPROT_INV + * + * Write Region not allowed + */ +#define ALT_QSPI_WRPROT_INV_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_MSB 0 +/* The width in bits of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_WIDTH 1 +/* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */ +#define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */ +#define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_WRPROT_INV register field. */ +#define ALT_QSPI_WRPROT_INV_RESET 0x0 +/* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */ +#define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */ +#define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Write Protection Enable Bit - en + * + * When enabled, any AHB write access with an address within the protection region + * defined in the lower and upper write protection registers is rejected. An AHB + * error response is generated and an interrupt source triggered. When disabled, + * the protection region is disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:--------------------------- + * ALT_QSPI_WRPROT_EN_E_EN | 0x1 | AHB Write Access rejected + * ALT_QSPI_WRPROT_EN_E_DIS | 0x0 | Protection Region Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_WRPROT_EN + * + * AHB Write Access rejected + */ +#define ALT_QSPI_WRPROT_EN_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_WRPROT_EN + * + * Protection Region Disabled + */ +#define ALT_QSPI_WRPROT_EN_E_DIS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_MSB 1 +/* The width in bits of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_WIDTH 1 +/* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */ +#define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */ +#define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_WRPROT_EN register field. */ +#define ALT_QSPI_WRPROT_EN_RESET 0x0 +/* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */ +#define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */ +#define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_WRPROT. + */ +struct ALT_QSPI_WRPROT_s +{ + uint32_t inv : 1; /* Write Protection Inversion Bit */ + uint32_t en : 1; /* Write Protection Enable Bit */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_WRPROT. */ +typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */ +#define ALT_QSPI_WRPROT_OFST 0x58 + +/* + * Register : Indirect Read Transfer Register - indrd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------------- + * [0] | RW | 0x0 | Start Indirect Read + * [1] | RW | 0x0 | Cancel Indirect Read + * [2] | R | Unknown | Indirect Read Status + * [3] | RW | Unknown | SRAM Full + * [4] | R | Unknown | Queued Indirect Read Operations + * [5] | RW | Unknown | Indirect Completion Status + * [7:6] | R | Unknown | Completed Indirect Operations + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Indirect Read - start + * + * When this bit is enabled, it will trigger an indirect read operation. The + * assumption is that the indirect start address and the indirect number of bytes + * register is setup before triggering the indirect read operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------- + * ALT_QSPI_INDRD_START_E_END | 0x1 | Trigger Indirect Read + * ALT_QSPI_INDRD_START_E_DISD | 0x0 | No Indirect Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_START + * + * Trigger Indirect Read + */ +#define ALT_QSPI_INDRD_START_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_START + * + * No Indirect Read + */ +#define ALT_QSPI_INDRD_START_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_MSB 0 +/* The width in bits of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_START register field value. */ +#define ALT_QSPI_INDRD_START_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_INDRD_START register field value. */ +#define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_INDRD_START register field. */ +#define ALT_QSPI_INDRD_START_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_START field value from a register. */ +#define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cancel Indirect Read - cancel + * + * This bit will cancel all ongoing indirect read operations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read + * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_CANCEL + * + * Cancel Indirect Read + */ +#define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_CANCEL + * + * Do Not Cancel Indirect Read + */ +#define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_MSB 1 +/* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */ +#define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */ +#define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */ +#define ALT_QSPI_INDRD_CANCEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */ +#define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Read Status - rd_status + * + * Indirect read operation in progress (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------ + * ALT_QSPI_INDRD_RD_STAT_E_RDOP | 0x1 | Read Operation in progress + * ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0 | No read operation in progress + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT + * + * Read Operation in progress + */ +#define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT + * + * No read operation in progress + */ +#define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_MSB 2 +/* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */ +#define ALT_QSPI_INDRD_RD_STAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */ +#define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */ +#define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_RD_STAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */ +#define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SRAM Full - sram_full + * + * SRAM full and unable to immediately complete an indirect operation. Write a 1 to + * this field to clear it. ; indirect operation (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------- + * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation + * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL + * + * Sram Full- Cant complete operation + */ +#define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL + * + * SRram Not Full + */ +#define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_MSB 3 +/* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */ +#define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */ +#define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */ +#define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */ +#define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Queued Indirect Read Operations - rd_queued + * + * Two indirect read operations have been queued + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read + * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED + * + * Queued Indirect Read + */ +#define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED + * + * No Queued Read + */ +#define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_MSB 4 +/* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */ +#define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */ +#define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */ +#define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */ +#define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Indirect Completion Status - ind_ops_done_status + * + * This field is set to 1 when an indirect operation has completed. Write a 1 to + * this field to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP | 0x1 | Indirect Op Complete operation + * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0 | Indirect Op Not Complete + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT + * + * Indirect Op Complete operation + */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT + * + * Indirect Op Not Complete + */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5 +/* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Completed Indirect Operations - num_ind_ops_done + * + * This field contains the number of indirect operations which have been completed. + * This is used in conjunction with the indirect completion status field (bit 5). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7 +/* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2 +/* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f +/* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0 +/* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */ +#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRD. + */ +struct ALT_QSPI_INDRD_s +{ + uint32_t start : 1; /* Start Indirect Read */ + uint32_t cancel : 1; /* Cancel Indirect Read */ + const uint32_t rd_status : 1; /* Indirect Read Status */ + uint32_t sram_full : 1; /* SRAM Full */ + const uint32_t rd_queued : 1; /* Queued Indirect Read Operations */ + uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */ + const uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRD. */ +typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */ +#define ALT_QSPI_INDRD_OFST 0x60 + +/* + * Register : Indirect Read Transfer Watermark Register - indrdwater + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Watermark Value + * + */ +/* + * Field : Watermark Value - level + * + * This represents the minimum fill level of the SRAM before a DMA peripheral + * access is permitted. When the SRAM fill level passes the watermark, an interrupt + * is also generated. This field can be disabled by writing a value of all zeroes. + * The units of this register are BYTES + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */ +#define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */ +#define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */ +#define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */ +#define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDWATER. + */ +struct ALT_QSPI_INDRDWATER_s +{ + uint32_t level : 32; /* Watermark Value */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDWATER. */ +typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */ +#define ALT_QSPI_INDRDWATER_OFST 0x64 + +/* + * Register : Indirect Read Transfer Start Address Register - indrdstaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [31:0] | RW | 0x0 | Start Address of Indirect Access + * + */ +/* + * Field : Start Address of Indirect Access - addr + * + * This is the start address from which the indirect access will commence its READ + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDSTADDR. + */ +struct ALT_QSPI_INDRDSTADDR_s +{ + uint32_t addr : 32; /* Start Address of Indirect Access */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */ +typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */ +#define ALT_QSPI_INDRDSTADDR_OFST 0x68 + +/* + * Register : Indirect Read Transfer Number Bytes Register - indrdcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------- + * [31:0] | RW | 0x0 | Indirect Count + * + */ +/* + * Field : Indirect Count - value + * + * This is the number of bytes that the indirect access will consume. This can be + * bigger than the configured size of SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */ +#define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */ +#define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */ +#define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */ +#define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDRDCNT. + */ +struct ALT_QSPI_INDRDCNT_s +{ + uint32_t value : 32; /* Indirect Count */ +}; + +/* The typedef declaration for register ALT_QSPI_INDRDCNT. */ +typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */ +#define ALT_QSPI_INDRDCNT_OFST 0x6c + +/* + * Register : Indirect Write Transfer Register - indwr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------- + * [0] | RW | 0x0 | Start Indirect Write + * [1] | RW | 0x0 | Cancel Indirect Write + * [2] | R | Unknown | Indirect Write Status + * [3] | R | 0x0 | Reserved + * [4] | R | Unknown | Queued Indirect Write Operations + * [5] | RW | Unknown | Indirect Completion Status + * [7:6] | R | Unknown | Completed Indirect Operations + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Start Indirect Write - start + * + * Writing a 1 to this bit will trigger an indirect write operation. The assumption + * is that the indirect start address and the indirect number of bytes register is + * setup before triggering the indirect write operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------------- + * ALT_QSPI_INDWR_START_E_END | 0x1 | Trigger indirect write operation + * ALT_QSPI_INDWR_START_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_START + * + * Trigger indirect write operation + */ +#define ALT_QSPI_INDWR_START_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_START + * + * No Action + */ +#define ALT_QSPI_INDWR_START_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_MSB 0 +/* The width in bits of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_START register field value. */ +#define ALT_QSPI_INDWR_START_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_INDWR_START register field value. */ +#define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_INDWR_START register field. */ +#define ALT_QSPI_INDWR_START_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_START field value from a register. */ +#define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cancel Indirect Write - cancel + * + * Writing a 1 to this bit will cancel all ongoing indirect write operations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation + * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_CANCEL + * + * Cancel Indirect write operation + */ +#define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_CANCEL + * + * No Action + */ +#define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_MSB 1 +/* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */ +#define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */ +#define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */ +#define ALT_QSPI_INDWR_CANCEL_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */ +#define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Indirect Write Status - rdstat + * + * Indirect write operation in progress (status) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------- + * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation + * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT + * + * Indirect write operation + */ +#define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT + * + * No Action + */ +#define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_MSB 2 +/* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */ +#define ALT_QSPI_INDWR_RDSTAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */ +#define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */ +#define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_RDSTAT_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */ +#define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Reserved - sramfull + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_MSB 3 +/* The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value. */ +#define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value. */ +#define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_QSPI_INDWR_SRAMFULL register field. */ +#define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register. */ +#define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Queued Indirect Write Operations - rdqueued + * + * Two indirect write operations have been queued + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation + * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED + * + * Two Indirect write operation + */ +#define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED + * + * No Action + */ +#define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_MSB 4 +/* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */ +#define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */ +#define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010 +/* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */ +#define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef +/* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */ +#define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Indirect Completion Status - inddone + * + * This field is set to 1 when an indirect operation has completed. Write a 1 to + * this field to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed + * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_INDWR_INDDONE + * + * Indirect operation completed + */ +#define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1 +/* + * Enumerated value for register field ALT_QSPI_INDWR_INDDONE + * + * No Action + */ +#define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_MSB 5 +/* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */ +#define ALT_QSPI_INDWR_INDDONE_WIDTH 1 +/* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */ +#define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */ +#define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_INDDONE_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */ +#define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Completed Indirect Operations - indcnt + * + * This field contains the count of indirect operations which have been completed. + * This is used in conjunction with the indirect completion status field (bit 5). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_MSB 7 +/* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */ +#define ALT_QSPI_INDWR_INDCNT_WIDTH 2 +/* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */ +#define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */ +#define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f +/* The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN. */ +#define ALT_QSPI_INDWR_INDCNT_RESET 0x0 +/* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */ +#define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */ +#define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWR. + */ +struct ALT_QSPI_INDWR_s +{ + uint32_t start : 1; /* Start Indirect Write */ + uint32_t cancel : 1; /* Cancel Indirect Write */ + const uint32_t rdstat : 1; /* Indirect Write Status */ + const uint32_t sramfull : 1; /* Reserved */ + const uint32_t rdqueued : 1; /* Queued Indirect Write Operations */ + uint32_t inddone : 1; /* Indirect Completion Status */ + const uint32_t indcnt : 2; /* Completed Indirect Operations */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWR. */ +typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */ +#define ALT_QSPI_INDWR_OFST 0x70 + +/* + * Register : Indirect Write Transfer Watermark Register - indwrwater + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------- + * [31:0] | RW | 0xffffffff | Watermark Value + * + */ +/* + * Field : Watermark Value - level + * + * This represents the maximum fill level of the SRAM before a DMA peripheral + * access is permitted. When the SRAM fill level falls below the watermark, an + * interrupt is also generated. This field can be disabled by writing a value of + * all ones. The units of this register are bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */ +#define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */ +#define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */ +#define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff +/* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */ +#define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRWATER. + */ +struct ALT_QSPI_INDWRWATER_s +{ + uint32_t level : 32; /* Watermark Value */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRWATER. */ +typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */ +#define ALT_QSPI_INDWRWATER_OFST 0x74 + +/* + * Register : Indirect Write Transfer Start Address Register - indwrstaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | Start of Indirect Access + * + */ +/* + * Field : Start of Indirect Access - addr + * + * This is the start address from which the indirect access will commence its write + * operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRSTADDR. + */ +struct ALT_QSPI_INDWRSTADDR_s +{ + uint32_t addr : 32; /* Start of Indirect Access */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */ +typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */ +#define ALT_QSPI_INDWRSTADDR_OFST 0x78 + +/* + * Register : Indirect Write Transfer Count Register - indwrcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [31:0] | RW | 0x0 | Indirect Number of Bytes + * + */ +/* + * Field : Indirect Number of Bytes - value + * + * This is the number of bytes that the indirect access will consume. This can be + * bigger than the configured size of SRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_MSB 31 +/* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32 +/* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */ +#define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */ +#define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */ +#define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0 +/* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */ +#define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_INDWRCNT. + */ +struct ALT_QSPI_INDWRCNT_s +{ + uint32_t value : 32; /* Indirect Number of Bytes */ +}; + +/* The typedef declaration for register ALT_QSPI_INDWRCNT. */ +typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */ +#define ALT_QSPI_INDWRCNT_OFST 0x7c + +/* + * Register : Flash Command Register - flashcmd + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Execute Command + * [1] | R | 0x0 | Command Execution Status + * [6:2] | ??? | 0x0 | *UNDEFINED* + * [11:7] | RW | 0x0 | Number of Dummy Bytes + * [14:12] | RW | 0x0 | Number of Write Data Bytes + * [15] | RW | 0x0 | Write Data Enable + * [17:16] | RW | 0x0 | Number of Address Bytes + * [18] | RW | 0x0 | Mode Bit Enable + * [19] | RW | 0x0 | Command Address Enable + * [22:20] | RW | 0x0 | Number of Read Data Bytes + * [23] | RW | 0x0 | Read Data Enable + * [31:24] | RW | 0x0 | Command Opcode + * + */ +/* + * Field : Execute Command - execcmd + * + * Execute the command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command + * ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD + * + * Execute Command + */ +#define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0 +/* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Command Execution Status - cmdexecstat + * + * Command execution in progress. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------- + * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status + * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT + * + * Command Execution Status + */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1 +/* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002 +/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd +/* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Number of Dummy Bytes - numdummybytes + * + * Set to the number of dummy bytes required This should be setup before triggering + * the command via the execute field of this register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f +/* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7) +/* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80) + +/* + * Field : Number of Write Data Bytes - numwrdatabytes + * + * Up to 8 Data bytes may be written using this command. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte + * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 1 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 2 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 3 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 4 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 5 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 6 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 7 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES + * + * Write 8 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12) +/* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000) + +/* + * Field : Write Data Enable - enwrdata + * + * Set to 1 if the command specified in the command opcode field requires write + * data bytes to be sent to the device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------- + * ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes + * ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA + * + * Command requires write data bytes + */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff +/* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Number of Address Bytes - numaddrbytes + * + * Set to the number of address bytes required (the address itself is programmed in + * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the + * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address + * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------- + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes + * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 1 Address Byte + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 2 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 3 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES + * + * Write 4 Address Bytes + */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Mode Bit Enable - enmodebit + * + * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration + * register are sent following the address bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------- + * ALT_QSPI_FLSHCMD_ENMODBIT_E_END | 0x1 | Mode Bit follows address bytes + * ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT + * + * Mode Bit follows address bytes + */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Command Address Enable - encmdaddr + * + * If enabled, the command specified in bits 31:24 requires an address. This should + * be setup before triggering the command via writing a 1 to the execute field. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------------------------------- + * ALT_QSPI_FLSHCMD_ENCMDADDR_E_END | 0x1 | Command in bits 31:24 requires address + * ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR + * + * Command in bits 31:24 requires address + */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Number of Read Data Bytes - numrddatabytes + * + * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for + * 8 bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte + * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 1 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 2 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 3 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 4 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 5 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 6 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 7 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES + * + * Read 8 Byte + */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22 +/* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3 +/* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff +/* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20) +/* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000) + +/* + * Field : Read Data Enable - enrddata + * + * If enabled, the command specified in the command opcode field (bits 31:24) + * requires read data bytes to be received from the device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------- + * ALT_QSPI_FLSHCMD_ENRDDATA_E_EN | 0x1 | Command Requires read data + * ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA + * + * Command Requires read data + */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1 +/* + * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA + * + * No Action + */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23 +/* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1 +/* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff +/* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Command Opcode - cmdopcode + * + * The command opcode field should be setup before triggering the command. For + * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of + * this register launches the command. NOTE : Using this approach to issue commands + * to the device will make use of the instruction type of the device instruction + * configuration register. If this field is set to 2'b00, then the command opcode, + * command address, command dummy bytes and command data will all be transferred in + * a serial fashion. If this field is set to 2'b01, then the command opcode, + * command address, command dummy bytes and command data will all be transferred in + * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command + * opcode, command address, command dummy bytes and command data will all be + * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8 +/* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000 +/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff +/* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMD. + */ +struct ALT_QSPI_FLSHCMD_s +{ + uint32_t execcmd : 1; /* Execute Command */ + const uint32_t cmdexecstat : 1; /* Command Execution Status */ + uint32_t : 5; /* *UNDEFINED* */ + uint32_t numdummybytes : 5; /* Number of Dummy Bytes */ + uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */ + uint32_t enwrdata : 1; /* Write Data Enable */ + uint32_t numaddrbytes : 2; /* Number of Address Bytes */ + uint32_t enmodebit : 1; /* Mode Bit Enable */ + uint32_t encmdaddr : 1; /* Command Address Enable */ + uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */ + uint32_t enrddata : 1; /* Read Data Enable */ + uint32_t cmdopcode : 8; /* Command Opcode */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMD. */ +typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMD_OFST 0x90 + +/* + * Register : Flash Command Address Registers - flashcmdaddr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Command Address + * + */ +/* + * Field : Command Address - addr + * + * This should be setup before triggering the command with execute field (bit 0) of + * the Flash Command Control register. It is the address used by the command + * specified in the opcode field (bits 31:24) of the Flash Command Control + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDADDR. + */ +struct ALT_QSPI_FLSHCMDADDR_s +{ + uint32_t addr : 32; /* Command Address */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */ +typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDADDR_OFST 0x94 + +/* + * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | Command Read Data (Lower byte) + * + */ +/* + * Field : Command Read Data (Lower byte) - data + * + * This is the data that is returned by the flash device for any status or + * configuration read operation carried out by triggering the event in the control + * register. The register will be valid when the polling bit in the control + * register is low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO. + */ +struct ALT_QSPI_FLSHCMDRDDATALO_s +{ + uint32_t data : 32; /* Command Read Data (Lower byte) */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */ +typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0 + +/* + * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup + * + * Device Instruction Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | Command Read Data (Upper byte) + * + */ +/* + * Field : Command Read Data (Upper byte) - data + * + * This is the data that is returned by the FLASH device for any status or + * configuration read operation carried out by triggering the event in the control + * register. The register will be valid when the polling bit in the control + * register is low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP. + */ +struct ALT_QSPI_FLSHCMDRDDATAUP_s +{ + uint32_t data : 32; /* Command Read Data (Upper byte) */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */ +typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4 + +/* + * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | Command Write Data Lower Byte + * + */ +/* + * Field : Command Write Data Lower Byte - data + * + * This is the command write data lower byte. This should be setup before + * triggering the command with execute field (bit 0) of the Flash Command Control + * register. It is the data that is to be written to the flash for any status or + * configuration write operation carried out by triggering the event in the Flash + * Command Control register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO. + */ +struct ALT_QSPI_FLSHCMDWRDATALO_s +{ + uint32_t data : 32; /* Command Write Data Lower Byte */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */ +typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8 + +/* + * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | ALT_QSPI_FLSHCMDWRDATAUP_DATA + * + */ +/* + * Field : data + * + * This is the command write data upper byte. This should be setup before + * triggering the command with execute field (bit 0) of the Flash Command Control + * register. It is the data that is to be written to the flash for any status or + * configuration write operation carried out by triggering the event in the Flash + * Command Control register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31 +/* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32 +/* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000 +/* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0 +/* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP. + */ +struct ALT_QSPI_FLSHCMDWRDATAUP_s +{ + uint32_t data : 32; /* ALT_QSPI_FLSHCMDWRDATAUP_DATA */ +}; + +/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */ +typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac + +/* + * Register : Module ID Register - moduleid + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------- + * [24:0] | R | 0x1001 | Module ID number + * [31:25] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Module ID number - value + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_MSB 24 +/* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_WIDTH 25 +/* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */ +#define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff +/* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */ +#define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000 +/* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */ +#define ALT_QSPI_MODULEID_VALUE_RESET 0x1001 +/* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */ +#define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0) +/* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */ +#define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_QSPI_MODULEID. + */ +struct ALT_QSPI_MODULEID_s +{ + const uint32_t value : 25; /* Module ID number */ + uint32_t : 7; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_QSPI_MODULEID. */ +typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */ +#define ALT_QSPI_MODULEID_OFST 0xfc + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_QSPI. + */ +struct ALT_QSPI_s +{ + volatile ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */ + volatile ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */ + volatile ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */ + volatile ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */ + volatile ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */ + volatile ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */ + volatile ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */ + volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ + volatile ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */ + volatile ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */ + volatile ALT_QSPI_MODBIT_t modebit; /* ALT_QSPI_MODBIT */ + volatile ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */ + volatile ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */ + volatile ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */ + volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */ + volatile ALT_QSPI_IRQMSK_t irqmask; /* ALT_QSPI_IRQMSK */ + volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ + volatile ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ + volatile ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */ + volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ + volatile ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */ + volatile ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */ + volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ + volatile ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */ + volatile ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */ + volatile ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */ + volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ + volatile ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */ + volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ + volatile ALT_QSPI_FLSHCMD_t flashcmd; /* ALT_QSPI_FLSHCMD */ + volatile ALT_QSPI_FLSHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ + volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ + volatile ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ + volatile ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ + volatile ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ + volatile ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ + volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ + volatile ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */ +}; + +/* The typedef declaration for register group ALT_QSPI. */ +typedef volatile struct ALT_QSPI_s ALT_QSPI_t; +/* The struct declaration for the raw register contents of register group ALT_QSPI. */ +struct ALT_QSPI_raw_s +{ + volatile uint32_t cfg; /* ALT_QSPI_CFG */ + volatile uint32_t devrd; /* ALT_QSPI_DEVRD */ + volatile uint32_t devwr; /* ALT_QSPI_DEVWR */ + volatile uint32_t delay; /* ALT_QSPI_DELAY */ + volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */ + volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */ + volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */ + volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ + volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */ + volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */ + volatile uint32_t modebit; /* ALT_QSPI_MODBIT */ + volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */ + volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */ + volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */ + volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ + volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */ + volatile uint32_t irqmask; /* ALT_QSPI_IRQMSK */ + volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ + volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ + volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ + volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */ + volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ + volatile uint32_t indrd; /* ALT_QSPI_INDRD */ + volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */ + volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ + volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */ + volatile uint32_t indwr; /* ALT_QSPI_INDWR */ + volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */ + volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ + volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */ + volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ + volatile uint32_t flashcmd; /* ALT_QSPI_FLSHCMD */ + volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ + volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ + volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ + volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ + volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ + volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ + volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ + volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_QSPI. */ +typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_QSPI_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_qspidata.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_qspidata.h new file mode 100644 index 000000000..7dddfe091 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_qspidata.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_QSPIDATA */ + +#ifndef __ALTERA_ALT_QSPIDATA_H__ +#define __ALTERA_ALT_QSPIDATA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : QSPI Flash Module Data (AHB Slave) - ALT_QSPIDATA + * QSPI Flash Module Data (AHB Slave) + * + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_QSPIDATA_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_rom.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_rom.h new file mode 100644 index 000000000..c48147bb9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_rom.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_ROM */ + +#ifndef __ALTERA_ALT_ROM_H__ +#define __ALTERA_ALT_ROM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : Boot ROM Module - ALT_ROM + * Boot ROM Module + * + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_ROM_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_rstmgr.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_rstmgr.h new file mode 100644 index 000000000..af4b663e1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_rstmgr.h @@ -0,0 +1,3382 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_RSTMGR */ + +#ifndef __ALTERA_ALT_RSTMGR_H__ +#define __ALTERA_ALT_RSTMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : Reset Manager Module - ALT_RSTMGR + * Reset Manager Module + * + * Registers in the Reset Manager module + * + */ +/* + * Register : Status Register - stat + * + * The STAT register contains bits that indicate the reset source or a timeout + * event. For reset sources, a field is 1 if its associated reset requester caused + * the reset. For timeout events, a field is 1 if its associated timeout occured as + * part of a hardware sequenced warm/debug reset. + * + * Software clears bits by writing them with a value of 1. Writes to bits with a + * value of 0 are ignored. + * + * After a cold reset is complete, all bits are reset to their reset value except + * for the bit(s) that indicate the source of the cold reset. If multiple cold + * reset requests overlap with each other, the source de-asserts the request last + * will be logged. The other reset request source(s) de-assert the request in the + * same cycle will also be logged, the rest of the fields are reset to default + * value of 0. + * + * After a warm reset is complete, the bit(s) that indicate the source of the warm + * reset are set to 1. A warm reset doesn't clear any of the bits in the STAT + * register; these bits must be cleared by software writing the STAT register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------- + * [0] | RW | 0x0 | Power-On Voltage Detector Cold Reset + * [1] | RW | 0x0 | nPOR Pin Cold Reset + * [2] | RW | 0x0 | FPGA Core Cold Reset + * [3] | RW | 0x0 | CONFIG_IO Cold Reset + * [4] | RW | 0x0 | Software Cold Reset + * [7:5] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | nRST Pin Warm Reset + * [9] | RW | 0x0 | FPGA Core Warm Reset + * [10] | RW | 0x0 | Software Warm Reset + * [11] | ??? | 0x0 | *UNDEFINED* + * [12] | RW | 0x0 | MPU Watchdog 0 Warm Reset + * [13] | RW | 0x0 | MPU Watchdog 1 Warm Reset + * [14] | RW | 0x0 | L4 Watchdog 0 Warm Reset + * [15] | RW | 0x0 | L4 Watchdog 1 Warm Reset + * [17:16] | ??? | 0x0 | *UNDEFINED* + * [18] | RW | 0x0 | FPGA Core Debug Reset + * [19] | RW | 0x0 | DAP Debug Reset + * [23:20] | ??? | 0x0 | *UNDEFINED* + * [24] | RW | 0x0 | SDRAM Self-Refresh Timeout + * [25] | RW | 0x0 | FPGA manager handshake Timeout + * [26] | RW | 0x0 | SCAN manager handshake Timeout + * [27] | RW | 0x0 | FPGA handshake Timeout + * [28] | RW | 0x0 | ETR Stall Timeout + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Power-On Voltage Detector Cold Reset - porvoltrst + * + * Built-in POR voltage detector triggered a cold reset (por_voltage_req = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_MSB 0 +/* The width in bits of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_PORVOLTRST register field value. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_STAT_PORVOLTRST register field value. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_PORVOLTRST field value from a register. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_STAT_PORVOLTRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : nPOR Pin Cold Reset - nporpinrst + * + * nPOR pin triggered a cold reset (por_pin_req = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_MSB 1 +/* The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value. */ +#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value. */ +#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field. */ +#define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register. */ +#define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : FPGA Core Cold Reset - fpgacoldrst + * + * FPGA core triggered a cold reset (f2h_cold_rst_req_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 2 +/* The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : CONFIG_IO Cold Reset - configiocoldrst + * + * FPGA entered CONFIG_IO mode and a triggered a cold reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 3 +/* The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Software Cold Reset - swcoldrst + * + * Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_MSB 4 +/* The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : nRST Pin Warm Reset - nrstpinrst + * + * nRST pin triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8 +/* The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : FPGA Core Warm Reset - fpgawarmrst + * + * FPGA core triggered a hardware sequenced warm reset (f2h_warm_rst_req_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9 +/* The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Software Warm Reset - swwarmrst + * + * Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm + * reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_MSB 10 +/* The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value. */ +#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value. */ +#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field. */ +#define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register. */ +#define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : MPU Watchdog 0 Warm Reset - mpuwd0rst + * + * MPU Watchdog 0 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_MSB 12 +/* The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : MPU Watchdog 1 Warm Reset - mpuwd1rst + * + * MPU Watchdog 1 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_MSB 13 +/* The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : L4 Watchdog 0 Warm Reset - l4wd0rst + * + * L4 Watchdog 0 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_MSB 14 +/* The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field. */ +#define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register. */ +#define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : L4 Watchdog 1 Warm Reset - l4wd1rst + * + * L4 Watchdog 1 triggered a hardware sequenced warm reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_MSB 15 +/* The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00008000 +/* The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value. */ +#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffff7fff +/* The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field. */ +#define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register. */ +#define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : FPGA Core Debug Reset - fpgadbgrst + * + * FPGA triggered debug reset (f2h_dbg_rst_req_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_MSB 18 +/* The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00040000 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffbffff +/* The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : DAP Debug Reset - cdbgreqrst + * + * DAP triggered debug reset + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_MSB 19 +/* The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00080000 +/* The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout + * + * A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to + * put the SDRAM devices into self-refresh mode before starting a hardware + * sequenced warm reset timed-out and the Reset Manager had to proceed with the + * warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB 24 +/* The width in bits of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK 0x01000000 +/* The mask used to clear the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK 0xfeffffff +/* The reset value of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SDRSELFREFTMO field value from a register. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_RSTMGR_STAT_SDRSELFREFTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : FPGA manager handshake Timeout - fpgamgrhstimeout + * + * A 1 indicates that Reset Manager's request to the FPGA manager to stop driving + * configuration clock to FPGA CB before starting a hardware sequenced warm reset + * timed-out and the Reset Manager had to proceed with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB 25 +/* The width in bits of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK 0x02000000 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK 0xfdffffff +/* The reset value of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGAMGRHSTMO field value from a register. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : SCAN manager handshake Timeout - scanhstimeout + * + * A 1 indicates that Reset Manager's request to the SCAN manager to stop driving + * JTAG clock to FPGA CB before starting a hardware sequenced warm reset timed-out + * and the Reset Manager had to proceed with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_MSB 26 +/* The width in bits of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_SCANHSTMO register field value. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK 0x04000000 +/* The mask used to clear the ALT_RSTMGR_STAT_SCANHSTMO register field value. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK 0xfbffffff +/* The reset value of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_SCANHSTMO field value from a register. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_RSTMGR_STAT_SCANHSTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : FPGA handshake Timeout - fpgahstimeout + * + * A 1 indicates that Reset Manager's handshake request to FPGA before starting a + * hardware sequenced warm reset timed-out and the Reset Manager had to proceed + * with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_MSB 27 +/* The width in bits of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK 0x08000000 +/* The mask used to clear the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_FPGAHSTMO field value from a register. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_RSTMGR_STAT_FPGAHSTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : ETR Stall Timeout - etrstalltimeout + * + * A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to + * stall its AXI master port before starting a hardware sequenced warm reset timed- + * out and the Reset Manager had to proceed with the warm reset anyway. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB 28 +/* The width in bits of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK 0x10000000 +/* The mask used to clear the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK 0xefffffff +/* The reset value of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET 0x0 +/* Extracts the ALT_RSTMGR_STAT_ETRSTALLTMO field value from a register. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_RSTMGR_STAT_ETRSTALLTMO register field value suitable for setting the register. */ +#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_STAT. + */ +struct ALT_RSTMGR_STAT_s +{ + uint32_t porvoltrst : 1; /* Power-On Voltage Detector Cold Reset */ + uint32_t nporpinrst : 1; /* nPOR Pin Cold Reset */ + uint32_t fpgacoldrst : 1; /* FPGA Core Cold Reset */ + uint32_t configiocoldrst : 1; /* CONFIG_IO Cold Reset */ + uint32_t swcoldrst : 1; /* Software Cold Reset */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t nrstpinrst : 1; /* nRST Pin Warm Reset */ + uint32_t fpgawarmrst : 1; /* FPGA Core Warm Reset */ + uint32_t swwarmrst : 1; /* Software Warm Reset */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t mpuwd0rst : 1; /* MPU Watchdog 0 Warm Reset */ + uint32_t mpuwd1rst : 1; /* MPU Watchdog 1 Warm Reset */ + uint32_t l4wd0rst : 1; /* L4 Watchdog 0 Warm Reset */ + uint32_t l4wd1rst : 1; /* L4 Watchdog 1 Warm Reset */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t fpgadbgrst : 1; /* FPGA Core Debug Reset */ + uint32_t cdbgreqrst : 1; /* DAP Debug Reset */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t sdrselfreftimeout : 1; /* SDRAM Self-Refresh Timeout */ + uint32_t fpgamgrhstimeout : 1; /* FPGA manager handshake Timeout */ + uint32_t scanhstimeout : 1; /* SCAN manager handshake Timeout */ + uint32_t fpgahstimeout : 1; /* FPGA handshake Timeout */ + uint32_t etrstalltimeout : 1; /* ETR Stall Timeout */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_STAT. */ +typedef volatile struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component. */ +#define ALT_RSTMGR_STAT_OFST 0x0 + +/* + * Register : Control Register - ctrl + * + * The CTRL register is used by software to control reset behavior.It includes + * fields for software to initiate the cold and warm reset, enable hardware + * handshake with other modules before warm reset, and perform software handshake. + * The software handshake sequence must match the hardware sequence. Software + * mustde-assert the handshake request after asserting warm reset and before de- + * assert the warm reset. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------------------------------- + * [0] | RW | 0x0 | Software Cold Reset Request + * [1] | RW | 0x0 | Software Warm Reset Request + * [3:2] | ??? | 0x0 | *UNDEFINED* + * [4] | RW | 0x0 | SDRAM Self-Refresh Enable + * [5] | RW | 0x0 | SDRAM Self-Refresh Request + * [6] | R | 0x0 | SDRAM Self-Refresh Acknowledge + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | FPGA Manager Handshake Enable + * [9] | RW | 0x0 | FPGA Manager Handshake Request + * [10] | R | Unknown | FPGA Manager Handshake Acknowledge + * [11] | ??? | 0x0 | *UNDEFINED* + * [12] | RW | 0x0 | SCAN Manager Handshake Enable + * [13] | RW | 0x0 | SCAN Manager Handshake Request + * [14] | R | Unknown | SCAN Manager Handshake Acknowledge + * [15] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | FPGA Handshake Enable + * [17] | RW | 0x0 | FPGA Handshake Request + * [18] | R | Unknown | FPGA Handshake Acknowledge + * [19] | ??? | 0x0 | *UNDEFINED* + * [20] | RW | 0x1 | ETR (Embedded Trace Router) Stall Enable + * [21] | RW | 0x0 | ETR (Embedded Trace Router) Stall Request + * [22] | R | 0x0 | ETR (Embedded Trace Router) Stall Acknowledge + * [23] | RW | 0x0 | ETR (Embedded Trace Router) Stall After Warm Reset + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Software Cold Reset Request - swcoldrstreq + * + * This is a one-shot bit written by software to 1 to trigger a cold reset. It + * always reads the value 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0 +/* The width in bits of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SWCOLDRSTREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Software Warm Reset Request - swwarmrstreq + * + * This is a one-shot bit written by software to 1 to trigger a hardware sequenced + * warm reset. It always reads the value 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1 +/* The width in bits of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SWWARMRSTREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_CTL_SWWARMRSTREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDRAM Self-Refresh Enable - sdrselfrefen + * + * This field controls whether the contents of SDRAM devices survive a hardware + * sequenced warm reset. If set to 1, the Reset Manager makes a request to the + * SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode + * before asserting warm reset signals. However, if SDRAM is already in warm reset, + * Handshake with SDRAM is not performed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB 4 +/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFEN field value from a register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_CTL_SDRSELFREFEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDRAM Self-Refresh Request - sdrselfrefreq + * + * Software writes this field 1 to request to the SDRAM Controller Subsystem that + * it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM + * contents across a software warm reset. + * + * Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0. + * Note that it is possible for the SDRAM Controller Subsystem to never assert + * SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB 5 +/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_CTL_SDRSELFREFREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack + * + * This is the acknowlege for a SDRAM self-refresh mode request initiated by the + * SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put + * the SDRAM devices into self-refresh mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB 6 +/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SDRSELFREQACK field value from a register. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_CTL_SDRSELFREQACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : FPGA Manager Handshake Enable - fpgamgrhsen + * + * Enables a handshake between the Reset Manager and FPGA Manager before a warm + * reset. The handshake is used to warn the FPGA Manager that a warm reset it + * coming so it can prepare for it. When the FPGA Manager receives a warm reset + * handshake, the FPGA Manager drives its output clock to a quiescent state to + * avoid glitches. + * + * If set to 1, the Manager makes a request to the FPGA Managerbefore asserting + * warm reset signals. However if the FPGA Manager is already in warm reset, the + * handshake is skipped. + * + * If set to 0, the handshake is skipped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB 8 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSEN field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : FPGA Manager Handshake Request - fpgamgrhsreq + * + * Software writes this field 1 to request to the FPGA Manager to idle its output + * clock. + * + * Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0. + * Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so + * software should timeout in this case. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB 9 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSREQ field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack + * + * This is the acknowlege (high active) that the FPGA manager has successfully + * idled its output clock. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB 10 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field is UNKNOWN. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSACK field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : SCAN Manager Handshake Enable - scanmgrhsen + * + * Enables a handshake between the Reset Manager and Scan Manager before a warm + * reset. The handshake is used to warn the Scan Manager that a warm reset it + * coming so it can prepare for it. When the Scan Manager receives a warm reset + * handshake, the Scan Manager drives its output clocks to a quiescent state to + * avoid glitches. + * + * If set to 1, the Reset Manager makes a request to the Scan Managerbefore + * asserting warm reset signals. However if the Scan Manager is already in warm + * reset, the handshake is skipped. + * + * If set to 0, the handshake is skipped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB 12 +/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSEN field value from a register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_CTL_SCANMGRHSEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : SCAN Manager Handshake Request - scanmgrhsreq + * + * Software writes this field 1 to request to the SCAN manager to idle its output + * clocks. + * + * Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0. + * Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g. + * its input clock is disabled) so software should timeout in this case. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB 13 +/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSREQ field value from a register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_CTL_SCANMGRHSREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : SCAN Manager Handshake Acknowledge - scanmgrhsack + * + * This is the acknowlege (high active) that the SCAN manager has successfully + * idled its output clocks. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB 14 +/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSACK register field is UNKNOWN. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSACK field value from a register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_CTL_SCANMGRHSACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : FPGA Handshake Enable - fpgahsen + * + * This field controls whether to perform handshake with FPGA before asserting warm + * reset. + * + * If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm + * reset signals. However if FPGA is already in warm reset state, the handshake is + * not performed. + * + * If set to 0, the handshake is not performed + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_MSB 16 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK 0x00010000 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSEN register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK 0xfffeffff +/* The reset value of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAHSEN field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_RSTMGR_CTL_FPGAHSEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : FPGA Handshake Request - fpgahsreq + * + * Software writes this field 1 to initiate handshake request to FPGA . + * + * Software waits for the FPGAHSACK to be active and then writes this field to 0. + * Note that it is possible for the FPGA to never assert FPGAHSACK so software + * should timeout in this case. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_MSB 17 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK 0x00020000 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK 0xfffdffff +/* The reset value of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAHSREQ field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_RSTMGR_CTL_FPGAHSREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : FPGA Handshake Acknowledge - fpgahsack + * + * This is the acknowlege (high active) that the FPGA handshake acknowledge has + * been received by Reset Manager. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_MSB 18 +/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK 0x00040000 +/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSACK register field value. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK 0xfffbffff +/* The reset value of the ALT_RSTMGR_CTL_FPGAHSACK register field is UNKNOWN. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_FPGAHSACK field value from a register. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_RSTMGR_CTL_FPGAHSACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : ETR (Embedded Trace Router) Stall Enable - etrstallen + * + * This field controls whether the ETR is requested to idle its AXI master + * interface (i.e. finish outstanding transactions and not initiate any more) to + * the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager + * makes a request to the ETR to stall its AXI master and waits for it to finish + * any outstanding AXI transactions before a warm reset of the L3 Interconnect or a + * debug reset of the ETR. This stalling is required because the debug logic + * (including the ETR) is reset on a debug reset and the ETR AXI master is + * connected to the L3 Interconnect which is reset on a warm reset and these resets + * can happen independently. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_MSB 20 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK 0x00100000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK 0xffefffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_RESET 0x1 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLEN field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLEN register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : ETR (Embedded Trace Router) Stall Request - etrstallreq + * + * Software writes this field 1 to request to the ETR that it stalls its AXI master + * to the L3 Interconnect. + * + * Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. + * Note that it is possible for the ETR to never assert ETRSTALLACK so software + * should timeout if ETRSTALLACK is never asserted. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB 21 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK 0x00200000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK 0xffdfffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLREQ field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLREQ register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack + * + * This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ + * field. A 1 indicates that the ETR has stalled its AXI master + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_MSB 22 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK 0x00400000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK 0xffbfffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLACK field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLACK register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst + * + * If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to + * indicate that the stall of the ETR AXI master is pending. Hardware leaves the + * ETR stalled until software clears this field by writing it with 1. Software must + * only clear this field when it is ready to have the ETR AXI master start making + * AXI requests to write trace data. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB 23 +/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK 0x00800000 +/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK 0xff7fffff +/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET 0x0 +/* Extracts the ALT_RSTMGR_CTL_ETRSTALLWARMRST field value from a register. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value suitable for setting the register. */ +#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_CTL. + */ +struct ALT_RSTMGR_CTL_s +{ + uint32_t swcoldrstreq : 1; /* Software Cold Reset Request */ + uint32_t swwarmrstreq : 1; /* Software Warm Reset Request */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t sdrselfrefen : 1; /* SDRAM Self-Refresh Enable */ + uint32_t sdrselfrefreq : 1; /* SDRAM Self-Refresh Request */ + const uint32_t sdrselfreqack : 1; /* SDRAM Self-Refresh Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t fpgamgrhsen : 1; /* FPGA Manager Handshake Enable */ + uint32_t fpgamgrhsreq : 1; /* FPGA Manager Handshake Request */ + const uint32_t fpgamgrhsack : 1; /* FPGA Manager Handshake Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t scanmgrhsen : 1; /* SCAN Manager Handshake Enable */ + uint32_t scanmgrhsreq : 1; /* SCAN Manager Handshake Request */ + const uint32_t scanmgrhsack : 1; /* SCAN Manager Handshake Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t fpgahsen : 1; /* FPGA Handshake Enable */ + uint32_t fpgahsreq : 1; /* FPGA Handshake Request */ + const uint32_t fpgahsack : 1; /* FPGA Handshake Acknowledge */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t etrstallen : 1; /* ETR (Embedded Trace Router) Stall Enable */ + uint32_t etrstallreq : 1; /* ETR (Embedded Trace Router) Stall Request */ + const uint32_t etrstallack : 1; /* ETR (Embedded Trace Router) Stall Acknowledge */ + uint32_t etrstallwarmrst : 1; /* ETR (Embedded Trace Router) Stall After Warm Reset */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_CTL. */ +typedef volatile struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_CTL register from the beginning of the component. */ +#define ALT_RSTMGR_CTL_OFST 0x4 + +/* + * Register : Reset Cycles Count Register - counts + * + * The COUNTS register is used by software to control reset behavior.It includes + * fields for software to control the behavior of the warm reset and nRST pin. + * + * Fields are only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------- + * [7:0] | RW | 0x80 | Warm reset release delay count + * [27:8] | RW | 0x800 | nRST Pin Count + * [31:28] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Warm reset release delay count - warmrstcycles + * + * On a warm reset, the Reset Manager releases the reset to the Clock Manager, and + * then waits for the number of cycles specified in this register before releasing + * the rest of the hardware controlled resets. Value must be greater than 16. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7 +/* The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8 +/* The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff +/* The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00 +/* The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80 +/* Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register. */ +#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : nRST Pin Count - nrstcnt + * + * The Reset Manager pulls down the nRST pin on a warm reset for the number of + * cycles specified in this register. A value of 0x0 prevents the Reset Manager + * from pulling down the nRST pin. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27 +/* The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20 +/* The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00 +/* The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff +/* The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800 +/* Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8) +/* Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register. */ +#define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_COUNTS. + */ +struct ALT_RSTMGR_COUNTS_s +{ + uint32_t warmrstcycles : 8; /* Warm reset release delay count */ + uint32_t nrstcnt : 20; /* nRST Pin Count */ + uint32_t : 4; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_COUNTS. */ +typedef volatile struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component. */ +#define ALT_RSTMGR_COUNTS_OFST 0x8 + +/* + * Register : MPU Module Reset Register - mpumodrst + * + * The MPUMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields except CPU1 are only reset by a cold reset. The CPU1 field is reset + * by a cold reset. The CPU1 field is also reset by a warm reset if not masked by + * the corresponding MPUWARMMASK field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | RW | 0x0 | CPU0 + * [1] | RW | 0x1 | CPU1 + * [2] | RW | 0x0 | Watchdogs + * [3] | RW | 0x0 | SCU/Peripherals + * [4] | RW | 0x0 | L2 + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : CPU0 - cpu0 + * + * Resets Cortex-A9 CPU0 in MPU. Whe software changes this field from 0 to 1, + * ittriggers the following sequence: 1. CPU0 reset is asserted. cpu0 clkoff is + * de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted. + * + * When software changes this field from 1 to 0, it triggers the following + * sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de- + * asserted. + * + * Software needs to wait for at least 64 osc1_clk cycles between each change of + * this field to keep the proper reset/clkoff sequence. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_CPU0 field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_MPUMODRST_CPU0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CPU1 - cpu1 + * + * Resets Cortex-A9 CPU1 in MPU. + * + * It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until + * software is ready to release CPU1 from reset by writing 0 to this field. + * + * On single-core devices, writes to this field are ignored.On dual-core devices, + * writes to this field trigger the same sequence as writes to the CPU0 field + * (except the sequence is performed on CPU1). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1 +/* Extracts the ALT_RSTMGR_MPUMODRST_CPU1 field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_MPUMODRST_CPU1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Watchdogs - wds + * + * Resets both per-CPU Watchdog Reset Status registers in MPU. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_MSB 2 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_WDS register field value. */ +#define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_WDS register field value. */ +#define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_MPUMODRST_WDS register field. */ +#define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_WDS field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_MPUMODRST_WDS register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SCU/Peripherals - scuper + * + * Resets SCU and peripherals. Peripherals consist of the interrupt controller, + * global timer, both per-CPU private timers, and both per-CPU watchdogs (except + * for the Watchdog Reset Status registers). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_SCUPER field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_MPUMODRST_SCUPER register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : L2 - l2 + * + * Resets L2 cache controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_MSB 4 +/* The width in bits of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MPUMODRST_L2 register field value. */ +#define ALT_RSTMGR_MPUMODRST_L2_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_MPUMODRST_L2 register field value. */ +#define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_MPUMODRST_L2 register field. */ +#define ALT_RSTMGR_MPUMODRST_L2_RESET 0x0 +/* Extracts the ALT_RSTMGR_MPUMODRST_L2 field value from a register. */ +#define ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_MPUMODRST_L2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_MPUMODRST. + */ +struct ALT_RSTMGR_MPUMODRST_s +{ + uint32_t cpu0 : 1; /* CPU0 */ + uint32_t cpu1 : 1; /* CPU1 */ + uint32_t wds : 1; /* Watchdogs */ + uint32_t scuper : 1; /* SCU/Peripherals */ + uint32_t l2 : 1; /* L2 */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_MPUMODRST. */ +typedef volatile struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_MPUMODRST_OFST 0x10 + +/* + * Register : Peripheral Module Reset Register - permodrst + * + * The PERMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are reset by a cold reset.All fields are also reset by a warm reset + * if not masked by the corresponding PERWARMMASK field. + * + * The reset value of all fields is 1. This holds the corresponding module in reset + * until software is ready to release the module from reset by writing 0 to its + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | RW | 0x1 | EMAC0 + * [1] | RW | 0x1 | EMAC1 + * [2] | RW | 0x1 | USB0 + * [3] | RW | 0x1 | USB1 + * [4] | RW | 0x1 | NAND Flash + * [5] | RW | 0x1 | QSPI Flash + * [6] | RW | 0x1 | L4 Watchdog 0 + * [7] | RW | 0x1 | L4 Watchdog 1 + * [8] | RW | 0x1 | OSC1 Timer 0 + * [9] | RW | 0x1 | OSC1 Timer 1 + * [10] | RW | 0x1 | SP Timer 0 + * [11] | RW | 0x1 | SP Timer 1 + * [12] | RW | 0x1 | I2C0 + * [13] | RW | 0x1 | I2C1 + * [14] | RW | 0x1 | I2C2 + * [15] | RW | 0x1 | I2C3 + * [16] | RW | 0x1 | UART0 + * [17] | RW | 0x1 | UART1 + * [18] | RW | 0x1 | SPIM0 + * [19] | RW | 0x1 | SPIM1 + * [20] | RW | 0x1 | SPIS0 + * [21] | RW | 0x1 | SPIS1 + * [22] | RW | 0x1 | SD/MMC + * [23] | RW | 0x1 | CAN0 + * [24] | RW | 0x1 | CAN1 + * [25] | RW | 0x1 | GPIO0 + * [26] | RW | 0x1 | GPIO1 + * [27] | RW | 0x1 | GPIO2 + * [28] | RW | 0x1 | DMA Controller + * [29] | RW | 0x1 | SDRAM Controller Subsystem + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC0 - emac0 + * + * Resets EMAC0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_MSB 0 +/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_EMAC0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_PERMODRST_EMAC0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : EMAC1 - emac1 + * + * Resets EMAC1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_MSB 1 +/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_EMAC1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_PERMODRST_EMAC1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB0 - usb0 + * + * Resets USB0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_MSB 2 +/* The width in bits of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_USB0 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB0 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_PERMODRST_USB0 register field. */ +#define ALT_RSTMGR_PERMODRST_USB0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_USB0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_PERMODRST_USB0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB1 - usb1 + * + * Resets USB1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_MSB 3 +/* The width in bits of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_USB1 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB1 register field value. */ +#define ALT_RSTMGR_PERMODRST_USB1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_PERMODRST_USB1 register field. */ +#define ALT_RSTMGR_PERMODRST_USB1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_USB1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_PERMODRST_USB1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAND Flash - nand + * + * Resets NAND flash controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_MSB 4 +/* The width in bits of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_NAND register field value. */ +#define ALT_RSTMGR_PERMODRST_NAND_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_NAND register field value. */ +#define ALT_RSTMGR_PERMODRST_NAND_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_PERMODRST_NAND register field. */ +#define ALT_RSTMGR_PERMODRST_NAND_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_NAND field value from a register. */ +#define ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_PERMODRST_NAND register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : QSPI Flash - qspi + * + * Resets QSPI flash controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_MSB 5 +/* The width in bits of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_QSPI register field value. */ +#define ALT_RSTMGR_PERMODRST_QSPI_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_QSPI register field value. */ +#define ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_PERMODRST_QSPI register field. */ +#define ALT_RSTMGR_PERMODRST_QSPI_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_QSPI field value from a register. */ +#define ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_PERMODRST_QSPI register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : L4 Watchdog 0 - l4wd0 + * + * Resets watchdog 0 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_MSB 6 +/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_L4WD0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_PERMODRST_L4WD0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : L4 Watchdog 1 - l4wd1 + * + * Resets watchdog 1 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_MSB 7 +/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_L4WD1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_RSTMGR_PERMODRST_L4WD1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : OSC1 Timer 0 - osc1timer0 + * + * Resets OSC1 timer 0 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB 8 +/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : OSC1 Timer 1 - osc1timer1 + * + * Resets OSC1 timer 1 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB 9 +/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : SP Timer 0 - sptimer0 + * + * Resets SP timer 0 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_MSB 10 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_PERMODRST_SPTMR0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : SP Timer 1 - sptimer1 + * + * Resets SP timer 1 connected to L4 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_MSB 11 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK 0x00000800 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_RSTMGR_PERMODRST_SPTMR1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : I2C0 - i2c0 + * + * Resets I2C0 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_MSB 12 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C0 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C0_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C0 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_PERMODRST_I2C0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : I2C1 - i2c1 + * + * Resets I2C1 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_MSB 13 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C1 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C1_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C1 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_PERMODRST_I2C1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : I2C2 - i2c2 + * + * Resets I2C2 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_MSB 14 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C2 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C2_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C2 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C2_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C2 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_PERMODRST_I2C2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : I2C3 - i2c3 + * + * Resets I2C3 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_MSB 15 +/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C3 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C3_SET_MSK 0x00008000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C3 register field value. */ +#define ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK 0xffff7fff +/* The reset value of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ +#define ALT_RSTMGR_PERMODRST_I2C3_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_I2C3 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_RSTMGR_PERMODRST_I2C3 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : UART0 - uart0 + * + * Resets UART0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_MSB 16 +/* The width in bits of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_UART0 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART0_SET_MSK 0x00010000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART0 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART0_CLR_MSK 0xfffeffff +/* The reset value of the ALT_RSTMGR_PERMODRST_UART0 register field. */ +#define ALT_RSTMGR_PERMODRST_UART0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_UART0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_RSTMGR_PERMODRST_UART0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : UART1 - uart1 + * + * Resets UART1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_MSB 17 +/* The width in bits of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_UART1 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART1_SET_MSK 0x00020000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART1 register field value. */ +#define ALT_RSTMGR_PERMODRST_UART1_CLR_MSK 0xfffdffff +/* The reset value of the ALT_RSTMGR_PERMODRST_UART1 register field. */ +#define ALT_RSTMGR_PERMODRST_UART1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_UART1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_RSTMGR_PERMODRST_UART1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : SPIM0 - spim0 + * + * Resets SPIM0 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_MSB 18 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK 0x00040000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK 0xfffbffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIM0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_RSTMGR_PERMODRST_SPIM0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : SPIM1 - spim1 + * + * Resets SPIM1 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_MSB 19 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK 0x00080000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIM1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_RSTMGR_PERMODRST_SPIM1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : SPIS0 - spis0 + * + * Resets SPIS0 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_MSB 20 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK 0x00100000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK 0xffefffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIS0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_RSTMGR_PERMODRST_SPIS0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : SPIS1 - spis1 + * + * Resets SPIS1 controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_MSB 21 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK 0x00200000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK 0xffdfffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SPIS1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_RSTMGR_PERMODRST_SPIS1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : SD/MMC - sdmmc + * + * Resets SD/MMC controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_MSB 22 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SDMMC register field value. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK 0x00400000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDMMC register field value. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK 0xffbfffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SDMMC field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_RSTMGR_PERMODRST_SDMMC register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : CAN0 - can0 + * + * Resets CAN0 controller. + * + * Writes to this field on devices not containing CAN controllers will be ignored. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_MSB 23 +/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN0 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN0_SET_MSK 0x00800000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN0 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK 0xff7fffff +/* The reset value of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_CAN0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_RSTMGR_PERMODRST_CAN0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : CAN1 - can1 + * + * Resets CAN1 controller. + * + * Writes to this field on devices not containing CAN controllers will be ignored. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_MSB 24 +/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN1 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN1_SET_MSK 0x01000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN1 register field value. */ +#define ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK 0xfeffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ +#define ALT_RSTMGR_PERMODRST_CAN1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_CAN1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_RSTMGR_PERMODRST_CAN1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : GPIO0 - gpio0 + * + * Resets GPIO0 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_MSB 25 +/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK 0x02000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK 0xfdffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_GPIO0 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_RSTMGR_PERMODRST_GPIO0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : GPIO1 - gpio1 + * + * Resets GPIO1 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_MSB 26 +/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK 0x04000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK 0xfbffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_GPIO1 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_RSTMGR_PERMODRST_GPIO1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : GPIO2 - gpio2 + * + * Resets GPIO2 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_MSB 27 +/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK 0x08000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_GPIO2 field value from a register. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_RSTMGR_PERMODRST_GPIO2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : DMA Controller - dma + * + * Resets DMA controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_MSB 28 +/* The width in bits of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_DMA register field value. */ +#define ALT_RSTMGR_PERMODRST_DMA_SET_MSK 0x10000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_DMA register field value. */ +#define ALT_RSTMGR_PERMODRST_DMA_CLR_MSK 0xefffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_DMA register field. */ +#define ALT_RSTMGR_PERMODRST_DMA_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_DMA field value from a register. */ +#define ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_RSTMGR_PERMODRST_DMA register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : SDRAM Controller Subsystem - sdr + * + * Resets SDRAM Controller Subsystem affected by a warm or cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_MSB 29 +/* The width in bits of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PERMODRST_SDR register field value. */ +#define ALT_RSTMGR_PERMODRST_SDR_SET_MSK 0x20000000 +/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDR register field value. */ +#define ALT_RSTMGR_PERMODRST_SDR_CLR_MSK 0xdfffffff +/* The reset value of the ALT_RSTMGR_PERMODRST_SDR register field. */ +#define ALT_RSTMGR_PERMODRST_SDR_RESET 0x1 +/* Extracts the ALT_RSTMGR_PERMODRST_SDR field value from a register. */ +#define ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_RSTMGR_PERMODRST_SDR register field value suitable for setting the register. */ +#define ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_PERMODRST. + */ +struct ALT_RSTMGR_PERMODRST_s +{ + uint32_t emac0 : 1; /* EMAC0 */ + uint32_t emac1 : 1; /* EMAC1 */ + uint32_t usb0 : 1; /* USB0 */ + uint32_t usb1 : 1; /* USB1 */ + uint32_t nand : 1; /* NAND Flash */ + uint32_t qspi : 1; /* QSPI Flash */ + uint32_t l4wd0 : 1; /* L4 Watchdog 0 */ + uint32_t l4wd1 : 1; /* L4 Watchdog 1 */ + uint32_t osc1timer0 : 1; /* OSC1 Timer 0 */ + uint32_t osc1timer1 : 1; /* OSC1 Timer 1 */ + uint32_t sptimer0 : 1; /* SP Timer 0 */ + uint32_t sptimer1 : 1; /* SP Timer 1 */ + uint32_t i2c0 : 1; /* I2C0 */ + uint32_t i2c1 : 1; /* I2C1 */ + uint32_t i2c2 : 1; /* I2C2 */ + uint32_t i2c3 : 1; /* I2C3 */ + uint32_t uart0 : 1; /* UART0 */ + uint32_t uart1 : 1; /* UART1 */ + uint32_t spim0 : 1; /* SPIM0 */ + uint32_t spim1 : 1; /* SPIM1 */ + uint32_t spis0 : 1; /* SPIS0 */ + uint32_t spis1 : 1; /* SPIS1 */ + uint32_t sdmmc : 1; /* SD/MMC */ + uint32_t can0 : 1; /* CAN0 */ + uint32_t can1 : 1; /* CAN1 */ + uint32_t gpio0 : 1; /* GPIO0 */ + uint32_t gpio1 : 1; /* GPIO1 */ + uint32_t gpio2 : 1; /* GPIO2 */ + uint32_t dma : 1; /* DMA Controller */ + uint32_t sdr : 1; /* SDRAM Controller Subsystem */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_PERMODRST. */ +typedef volatile struct ALT_RSTMGR_PERMODRST_s ALT_RSTMGR_PERMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_PERMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_PERMODRST_OFST 0x14 + +/* + * Register : Peripheral 2 Module Reset Register - per2modrst + * + * The PER2MODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are reset by a cold reset.All fields are also reset by a warm reset + * if not masked by the corresponding PERWARMMASK field. + * + * The reset value of all fields is 1. This holds the corresponding module in reset + * until software is ready to release the module from reset by writing 0 to its + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x1 | FPGA DMA0 + * [1] | RW | 0x1 | FPGA DMA1 + * [2] | RW | 0x1 | FPGA DMA2 + * [3] | RW | 0x1 | FPGA DMA3 + * [4] | RW | 0x1 | FPGA DMA4 + * [5] | RW | 0x1 | FPGA DMA5 + * [6] | RW | 0x1 | FPGA DMA6 + * [7] | RW | 0x1 | FPGA DMA7 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA DMA0 - dmaif0 + * + * Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_MSB 0 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF0 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF0 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : FPGA DMA1 - dmaif1 + * + * Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_MSB 1 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF1 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF1 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : FPGA DMA2 - dmaif2 + * + * Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_MSB 2 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF2 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF2 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : FPGA DMA3 - dmaif3 + * + * Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_MSB 3 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF3 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF3 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : FPGA DMA4 - dmaif4 + * + * Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_MSB 4 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF4 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF4 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : FPGA DMA5 - dmaif5 + * + * Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_MSB 5 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF5 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF5 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : FPGA DMA6 - dmaif6 + * + * Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_MSB 6 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF6 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF6 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : FPGA DMA7 - dmaif7 + * + * Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA + * Controller + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_MSB 7 +/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_RESET 0x1 +/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF7 field value from a register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF7 register field value suitable for setting the register. */ +#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_PER2MODRST. + */ +struct ALT_RSTMGR_PER2MODRST_s +{ + uint32_t dmaif0 : 1; /* FPGA DMA0 */ + uint32_t dmaif1 : 1; /* FPGA DMA1 */ + uint32_t dmaif2 : 1; /* FPGA DMA2 */ + uint32_t dmaif3 : 1; /* FPGA DMA3 */ + uint32_t dmaif4 : 1; /* FPGA DMA4 */ + uint32_t dmaif5 : 1; /* FPGA DMA5 */ + uint32_t dmaif6 : 1; /* FPGA DMA6 */ + uint32_t dmaif7 : 1; /* FPGA DMA7 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_PER2MODRST. */ +typedef volatile struct ALT_RSTMGR_PER2MODRST_s ALT_RSTMGR_PER2MODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_PER2MODRST register from the beginning of the component. */ +#define ALT_RSTMGR_PER2MODRST_OFST 0x18 + +/* + * Register : Bridge Module Reset Register - brgmodrst + * + * The BRGMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are reset by a cold reset.All fields are also reset by a warm reset + * if not masked by the corresponding BRGWARMMASK field. + * + * The reset value of all fields is 1. This holds the corresponding module in reset + * until software is ready to release the module from reset by writing 0 to its + * field. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------ + * [0] | RW | 0x1 | HPS2FPGA Bridge + * [1] | RW | 0x1 | LWHPS2FPGA Bridge + * [2] | RW | 0x1 | FPGA2HPS Bridge + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : HPS2FPGA Bridge - hps2fpga + * + * Resets HPS2FPGA Bridge + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_MSB 0 +/* The width in bits of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_BRGMODRST_H2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_BRGMODRST_H2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_BRGMODRST_H2F register field. */ +#define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1 +/* Extracts the ALT_RSTMGR_BRGMODRST_H2F field value from a register. */ +#define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_BRGMODRST_H2F register field value suitable for setting the register. */ +#define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : LWHPS2FPGA Bridge - lwhps2fpga + * + * Resets LWHPS2FPGA Bridge + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1 +/* The width in bits of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1 +/* Extracts the ALT_RSTMGR_BRGMODRST_LWH2F field value from a register. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_BRGMODRST_LWH2F register field value suitable for setting the register. */ +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : FPGA2HPS Bridge - fpga2hps + * + * Resets FPGA2HPS Bridge + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_MSB 2 +/* The width in bits of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_BRGMODRST_F2H register field value. */ +#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2H register field value. */ +#define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_BRGMODRST_F2H register field. */ +#define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1 +/* Extracts the ALT_RSTMGR_BRGMODRST_F2H field value from a register. */ +#define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_BRGMODRST_F2H register field value suitable for setting the register. */ +#define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_BRGMODRST. + */ +struct ALT_RSTMGR_BRGMODRST_s +{ + uint32_t hps2fpga : 1; /* HPS2FPGA Bridge */ + uint32_t lwhps2fpga : 1; /* LWHPS2FPGA Bridge */ + uint32_t fpga2hps : 1; /* FPGA2HPS Bridge */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_BRGMODRST. */ +typedef volatile struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_BRGMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_BRGMODRST_OFST 0x1c + +/* + * Register : Miscellaneous Module Reset Register - miscmodrst + * + * The MISCMODRST register is used by software to trigger module resets (individual + * module reset signals). Software explicitly asserts and de-asserts module reset + * signals by writing bits in the appropriate *MODRST register. It is up to + * software to ensure module reset signals are asserted for the appropriate length + * of time and are de-asserted in the correct order. It is also up to software to + * not assert a module reset signal that would prevent software from de-asserting + * the module reset signal. For example, software should not assert the module + * reset to the CPU executing the software. + * + * Software writes a bit to 1 to assert the module reset signal and to 0 to de- + * assert the module reset signal. + * + * All fields are only reset by a cold reset + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x0 | Boot ROM + * [1] | RW | 0x0 | On-chip RAM + * [2] | RW | 0x0 | System Manager (Cold or Warm) + * [3] | RW | 0x0 | System Manager (Cold-only) + * [4] | RW | 0x0 | FPGA Manager + * [5] | RW | 0x0 | ACP ID Mapper + * [6] | RW | 0x0 | HPS to FPGA Core (Cold or Warm) + * [7] | RW | 0x0 | HPS to FPGA Core (Cold-only) + * [8] | RW | 0x0 | nRST Pin + * [9] | RW | 0x0 | Timestamp + * [10] | RW | 0x0 | Clock Manager + * [11] | RW | 0x0 | Scan Manager + * [12] | RW | 0x0 | Freeze Controller + * [13] | RW | 0x0 | System/Debug + * [14] | RW | 0x0 | Debug + * [15] | RW | 0x0 | TAP Controller + * [16] | RW | 0x0 | SDRAM Controller Subsystem Cold Reset + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Boot ROM - rom + * + * Resets Boot ROM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_MSB 0 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_ROM register field value. */ +#define ALT_RSTMGR_MISCMODRST_ROM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ROM register field value. */ +#define ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_RSTMGR_MISCMODRST_ROM register field. */ +#define ALT_RSTMGR_MISCMODRST_ROM_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_ROM field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_RSTMGR_MISCMODRST_ROM register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : On-chip RAM - ocram + * + * Resets On-chip RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_MSB 1 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK 0x00000002 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK 0xfffffffd +/* The reset value of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_OCRAM field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_RSTMGR_MISCMODRST_OCRAM register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : System Manager (Cold or Warm) - sysmgr + * + * Resets logic in System Manager that doesn't differentiate between cold and warm + * resets + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_MSB 2 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGR field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGR register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : System Manager (Cold-only) - sysmgrcold + * + * Resets logic in System Manager that is only reset by a cold reset (ignores warm + * reset) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB 3 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK 0x00000008 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : FPGA Manager - fpgamgr + * + * Resets FPGA Manager + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB 4 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK 0xffffffef +/* The reset value of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_FPGAMGR field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_RSTMGR_MISCMODRST_FPGAMGR register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACP ID Mapper - acpidmap + * + * Resets ACP ID Mapper + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB 5 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK 0x00000020 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK 0xffffffdf +/* The reset value of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_ACPIDMAP field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : HPS to FPGA Core (Cold or Warm) - s2f + * + * Resets logic in FPGA core that doesn't differentiate between HPS cold and warm + * resets (h2f_rst_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_MSB 6 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2F register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2F_SET_MSK 0x00000040 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2F register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK 0xffffffbf +/* The reset value of the ALT_RSTMGR_MISCMODRST_S2F register field. */ +#define ALT_RSTMGR_MISCMODRST_S2F_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_S2F field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_RSTMGR_MISCMODRST_S2F register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : HPS to FPGA Core (Cold-only) - s2fcold + * + * Resets logic in FPGA core that is only reset by a cold reset (ignores warm + * reset) (h2f_cold_rst_n = 1) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB 7 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_S2FCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_RSTMGR_MISCMODRST_S2FCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : nRST Pin - nrstpin + * + * Pulls nRST pin low + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB 8 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_NRSTPIN field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_RSTMGR_MISCMODRST_NRSTPIN register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Timestamp - timestampcold + * + * Resets debug timestamp to 0 (cold reset only) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_MSB 9 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK 0x00000200 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK 0xfffffdff +/* The reset value of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_TSCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_RSTMGR_MISCMODRST_TSCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Clock Manager - clkmgrcold + * + * Resets Clock Manager (cold reset only) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB 10 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK 0x00000400 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK 0xfffffbff +/* The reset value of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Scan Manager - scanmgr + * + * Resets Scan Manager + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_MSB 11 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SCANMGR field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_RSTMGR_MISCMODRST_SCANMGR register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Freeze Controller - frzctrlcold + * + * Resets Freeze Controller in System Manager (cold reset only) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_MSB 12 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET_MSK 0x00001000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_CLR_MSK 0xffffefff +/* The reset value of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : System/Debug - sysdbg + * + * Resets logic that spans the system and debug domains. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_MSB 13 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET_MSK 0x00002000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_CLR_MSK 0xffffdfff +/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SYSDBG field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_RSTMGR_MISCMODRST_SYSDBG register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Debug - dbg + * + * Resets logic located only in the debug domain. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_MSB 14 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_DBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_DBG_SET_MSK 0x00004000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_DBG register field value. */ +#define ALT_RSTMGR_MISCMODRST_DBG_CLR_MSK 0xffffbfff +/* The reset value of the ALT_RSTMGR_MISCMODRST_DBG register field. */ +#define ALT_RSTMGR_MISCMODRST_DBG_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_DBG field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_DBG_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_RSTMGR_MISCMODRST_DBG register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_DBG_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : TAP Controller - tapcold + * + * Resets portion of DAP JTAG TAP controller no reset by a debug probe reset (i.e. + * nTRST pin). Cold reset only. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_MSB 15 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET_MSK 0x00008000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_CLR_MSK 0xffff7fff +/* The reset value of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_TAPCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_RSTMGR_MISCMODRST_TAPCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : SDRAM Controller Subsystem Cold Reset - sdrcold + * + * Resets logic in SDRAM Controller Subsystem affected only by a cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_MSB 16 +/* The width in bits of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_WIDTH 1 +/* The mask used to set the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET_MSK 0x00010000 +/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_CLR_MSK 0xfffeffff +/* The reset value of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_RESET 0x0 +/* Extracts the ALT_RSTMGR_MISCMODRST_SDRCOLD field value from a register. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_RSTMGR_MISCMODRST_SDRCOLD register field value suitable for setting the register. */ +#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_RSTMGR_MISCMODRST. + */ +struct ALT_RSTMGR_MISCMODRST_s +{ + uint32_t rom : 1; /* Boot ROM */ + uint32_t ocram : 1; /* On-chip RAM */ + uint32_t sysmgr : 1; /* System Manager (Cold or Warm) */ + uint32_t sysmgrcold : 1; /* System Manager (Cold-only) */ + uint32_t fpgamgr : 1; /* FPGA Manager */ + uint32_t acpidmap : 1; /* ACP ID Mapper */ + uint32_t s2f : 1; /* HPS to FPGA Core (Cold or Warm) */ + uint32_t s2fcold : 1; /* HPS to FPGA Core (Cold-only) */ + uint32_t nrstpin : 1; /* nRST Pin */ + uint32_t timestampcold : 1; /* Timestamp */ + uint32_t clkmgrcold : 1; /* Clock Manager */ + uint32_t scanmgr : 1; /* Scan Manager */ + uint32_t frzctrlcold : 1; /* Freeze Controller */ + uint32_t sysdbg : 1; /* System/Debug */ + uint32_t dbg : 1; /* Debug */ + uint32_t tapcold : 1; /* TAP Controller */ + uint32_t sdrcold : 1; /* SDRAM Controller Subsystem Cold Reset */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_RSTMGR_MISCMODRST. */ +typedef volatile struct ALT_RSTMGR_MISCMODRST_s ALT_RSTMGR_MISCMODRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_RSTMGR_MISCMODRST register from the beginning of the component. */ +#define ALT_RSTMGR_MISCMODRST_OFST 0x20 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_RSTMGR. + */ +struct ALT_RSTMGR_s +{ + volatile ALT_RSTMGR_STAT_t stat; /* ALT_RSTMGR_STAT */ + volatile ALT_RSTMGR_CTL_t ctrl; /* ALT_RSTMGR_CTL */ + volatile ALT_RSTMGR_COUNTS_t counts; /* ALT_RSTMGR_COUNTS */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_RSTMGR_MPUMODRST_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */ + volatile ALT_RSTMGR_PERMODRST_t permodrst; /* ALT_RSTMGR_PERMODRST */ + volatile ALT_RSTMGR_PER2MODRST_t per2modrst; /* ALT_RSTMGR_PER2MODRST */ + volatile ALT_RSTMGR_BRGMODRST_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */ + volatile ALT_RSTMGR_MISCMODRST_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */ + volatile uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_RSTMGR. */ +typedef volatile struct ALT_RSTMGR_s ALT_RSTMGR_t; +/* The struct declaration for the raw register contents of register group ALT_RSTMGR. */ +struct ALT_RSTMGR_raw_s +{ + volatile uint32_t stat; /* ALT_RSTMGR_STAT */ + volatile uint32_t ctrl; /* ALT_RSTMGR_CTL */ + volatile uint32_t counts; /* ALT_RSTMGR_COUNTS */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */ + volatile uint32_t permodrst; /* ALT_RSTMGR_PERMODRST */ + volatile uint32_t per2modrst; /* ALT_RSTMGR_PER2MODRST */ + volatile uint32_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */ + volatile uint32_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */ + volatile uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_RSTMGR. */ +typedef volatile struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_RSTMGR_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_scanmgr.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_scanmgr.h new file mode 100644 index 000000000..325b9e7b0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_scanmgr.h @@ -0,0 +1,927 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_SCANMGR */ + +#ifndef __ALTERA_ALT_SCANMGR_H__ +#define __ALTERA_ALT_SCANMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : Scan Manager Module Registers - ALT_SCANMGR + * Scan Manager Module Registers + * + * Registers in the Scan Manager module. + * + * These registers are implemented by an ARM JTAG-AP module from the ARM DAP. Some + * register and field names have been changed to match the usage in the Scan + * Manager. If modified, the corresponding names from the ARM documentation are + * provided. Only registers and fields that are relevant to the JTAG-AP use in the + * Scan Manager are listed. + * + */ +/* + * Register : Control/Status Word Register - stat + * + * Consist of control bit and status information. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Reset output to the FPGA JTAG + * [2] | ??? | 0x0 | *UNDEFINED* + * [3] | R | Unknown | Ignore + * [23:4] | ??? | 0x0 | *UNDEFINED* + * [26:24] | R | 0x0 | Response FIFO Outstanding Byte Count + * [27] | ??? | 0x0 | *UNDEFINED* + * [30:28] | R | 0x0 | Command FIFO Outstanding Byte Count + * [31] | R | 0x0 | Scan-Chain Engine Active + * + */ +/* + * Field : Reset output to the FPGA JTAG - trst + * + * Specifies the value of the nTRST signal driven to the FPGA JTAG only. The FPGA + * JTAG scan-chain must be enabled via the EN register to drive the value specified + * in this field. The nTRST signal is driven with the inverted value of this + * field.The nTRST signal is active low so, when this bit is set to 1, FPGA JTAG is + * reset. + * + * The name of this field in ARM documentation is TRST_OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------- + * ALT_SCANMGR_STAT_TRST_E_DONT_RST_FPGA_JTAG | 0x0 | Don't reset FPGA JTAG. + * ALT_SCANMGR_STAT_TRST_E_RST_FPGA_JTAG | 0x1 | Reset FPGA JTAG. Must have the FPGA JTAG scan- + * : | | chain enabled in the EN register to take effect. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SCANMGR_STAT_TRST + * + * Don't reset FPGA JTAG. + */ +#define ALT_SCANMGR_STAT_TRST_E_DONT_RST_FPGA_JTAG 0x0 +/* + * Enumerated value for register field ALT_SCANMGR_STAT_TRST + * + * Reset FPGA JTAG. Must have the FPGA JTAG scan-chain enabled in the EN register + * to take effect. + */ +#define ALT_SCANMGR_STAT_TRST_E_RST_FPGA_JTAG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_TRST register field. */ +#define ALT_SCANMGR_STAT_TRST_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_TRST register field. */ +#define ALT_SCANMGR_STAT_TRST_MSB 1 +/* The width in bits of the ALT_SCANMGR_STAT_TRST register field. */ +#define ALT_SCANMGR_STAT_TRST_WIDTH 1 +/* The mask used to set the ALT_SCANMGR_STAT_TRST register field value. */ +#define ALT_SCANMGR_STAT_TRST_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SCANMGR_STAT_TRST register field value. */ +#define ALT_SCANMGR_STAT_TRST_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SCANMGR_STAT_TRST register field. */ +#define ALT_SCANMGR_STAT_TRST_RESET 0x0 +/* Extracts the ALT_SCANMGR_STAT_TRST field value from a register. */ +#define ALT_SCANMGR_STAT_TRST_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SCANMGR_STAT_TRST register field value suitable for setting the register. */ +#define ALT_SCANMGR_STAT_TRST_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Ignore - ignore + * + * Ignore this field. Its value is undefined (may be 0 or 1). + * + * The name of this field in ARM documentation is PORTCONNECTED. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_IGNORE register field. */ +#define ALT_SCANMGR_STAT_IGNORE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_IGNORE register field. */ +#define ALT_SCANMGR_STAT_IGNORE_MSB 3 +/* The width in bits of the ALT_SCANMGR_STAT_IGNORE register field. */ +#define ALT_SCANMGR_STAT_IGNORE_WIDTH 1 +/* The mask used to set the ALT_SCANMGR_STAT_IGNORE register field value. */ +#define ALT_SCANMGR_STAT_IGNORE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SCANMGR_STAT_IGNORE register field value. */ +#define ALT_SCANMGR_STAT_IGNORE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SCANMGR_STAT_IGNORE register field is UNKNOWN. */ +#define ALT_SCANMGR_STAT_IGNORE_RESET 0x0 +/* Extracts the ALT_SCANMGR_STAT_IGNORE field value from a register. */ +#define ALT_SCANMGR_STAT_IGNORE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SCANMGR_STAT_IGNORE register field value suitable for setting the register. */ +#define ALT_SCANMGR_STAT_IGNORE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Response FIFO Outstanding Byte Count - rfifocnt + * + * Response FIFO outstanding byte count. Returns the number of bytes of response + * data available in the Response FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_RFIFOCNT register field. */ +#define ALT_SCANMGR_STAT_RFIFOCNT_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_RFIFOCNT register field. */ +#define ALT_SCANMGR_STAT_RFIFOCNT_MSB 26 +/* The width in bits of the ALT_SCANMGR_STAT_RFIFOCNT register field. */ +#define ALT_SCANMGR_STAT_RFIFOCNT_WIDTH 3 +/* The mask used to set the ALT_SCANMGR_STAT_RFIFOCNT register field value. */ +#define ALT_SCANMGR_STAT_RFIFOCNT_SET_MSK 0x07000000 +/* The mask used to clear the ALT_SCANMGR_STAT_RFIFOCNT register field value. */ +#define ALT_SCANMGR_STAT_RFIFOCNT_CLR_MSK 0xf8ffffff +/* The reset value of the ALT_SCANMGR_STAT_RFIFOCNT register field. */ +#define ALT_SCANMGR_STAT_RFIFOCNT_RESET 0x0 +/* Extracts the ALT_SCANMGR_STAT_RFIFOCNT field value from a register. */ +#define ALT_SCANMGR_STAT_RFIFOCNT_GET(value) (((value) & 0x07000000) >> 24) +/* Produces a ALT_SCANMGR_STAT_RFIFOCNT register field value suitable for setting the register. */ +#define ALT_SCANMGR_STAT_RFIFOCNT_SET(value) (((value) << 24) & 0x07000000) + +/* + * Field : Command FIFO Outstanding Byte Count - wfifocnt + * + * Command FIFO outstanding byte count. Returns the number of command bytes held in + * the Command FIFO that have yet to be processed by the Scan-Chain Engine. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_WFIFOCNT register field. */ +#define ALT_SCANMGR_STAT_WFIFOCNT_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_WFIFOCNT register field. */ +#define ALT_SCANMGR_STAT_WFIFOCNT_MSB 30 +/* The width in bits of the ALT_SCANMGR_STAT_WFIFOCNT register field. */ +#define ALT_SCANMGR_STAT_WFIFOCNT_WIDTH 3 +/* The mask used to set the ALT_SCANMGR_STAT_WFIFOCNT register field value. */ +#define ALT_SCANMGR_STAT_WFIFOCNT_SET_MSK 0x70000000 +/* The mask used to clear the ALT_SCANMGR_STAT_WFIFOCNT register field value. */ +#define ALT_SCANMGR_STAT_WFIFOCNT_CLR_MSK 0x8fffffff +/* The reset value of the ALT_SCANMGR_STAT_WFIFOCNT register field. */ +#define ALT_SCANMGR_STAT_WFIFOCNT_RESET 0x0 +/* Extracts the ALT_SCANMGR_STAT_WFIFOCNT field value from a register. */ +#define ALT_SCANMGR_STAT_WFIFOCNT_GET(value) (((value) & 0x70000000) >> 28) +/* Produces a ALT_SCANMGR_STAT_WFIFOCNT register field value suitable for setting the register. */ +#define ALT_SCANMGR_STAT_WFIFOCNT_SET(value) (((value) << 28) & 0x70000000) + +/* + * Field : Scan-Chain Engine Active - active + * + * Indicates if the Scan-Chain Engine is processing commands from the Command FIFO + * or not. + * + * The Scan-Chain Engine is only guaranteed to be inactive if both the ACTIVE and + * WFIFOCNT fields are zero. + * + * The name of this field in ARM documentation is SERACTV. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_SCANMGR_STAT_ACT_E_POSSIBLY_INACT | 0x0 | The Scan-Chain Engine may or may not be + * : | | processing commands from the Command FIFO. The + * : | | Scan-Chain Engine is only guaranteed to be + * : | | inactive if both this ACTIVE field and the + * : | | WFIFOCNT fields are both zero. + * ALT_SCANMGR_STAT_ACT_E_ACT | 0x1 | The Scan-Chain Engine is processing commands + * : | | from the Command FIFO. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SCANMGR_STAT_ACT + * + * The Scan-Chain Engine may or may not be processing commands from the Command + * FIFO. The Scan-Chain Engine is only guaranteed to be inactive if both this + * ACTIVE field and the WFIFOCNT fields are both zero. + */ +#define ALT_SCANMGR_STAT_ACT_E_POSSIBLY_INACT 0x0 +/* + * Enumerated value for register field ALT_SCANMGR_STAT_ACT + * + * The Scan-Chain Engine is processing commands from the Command FIFO. + */ +#define ALT_SCANMGR_STAT_ACT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_STAT_ACT register field. */ +#define ALT_SCANMGR_STAT_ACT_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_STAT_ACT register field. */ +#define ALT_SCANMGR_STAT_ACT_MSB 31 +/* The width in bits of the ALT_SCANMGR_STAT_ACT register field. */ +#define ALT_SCANMGR_STAT_ACT_WIDTH 1 +/* The mask used to set the ALT_SCANMGR_STAT_ACT register field value. */ +#define ALT_SCANMGR_STAT_ACT_SET_MSK 0x80000000 +/* The mask used to clear the ALT_SCANMGR_STAT_ACT register field value. */ +#define ALT_SCANMGR_STAT_ACT_CLR_MSK 0x7fffffff +/* The reset value of the ALT_SCANMGR_STAT_ACT register field. */ +#define ALT_SCANMGR_STAT_ACT_RESET 0x0 +/* Extracts the ALT_SCANMGR_STAT_ACT field value from a register. */ +#define ALT_SCANMGR_STAT_ACT_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_SCANMGR_STAT_ACT register field value suitable for setting the register. */ +#define ALT_SCANMGR_STAT_ACT_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SCANMGR_STAT. + */ +struct ALT_SCANMGR_STAT_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t trst : 1; /* Reset output to the FPGA JTAG */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t ignore : 1; /* Ignore */ + uint32_t : 20; /* *UNDEFINED* */ + const uint32_t rfifocnt : 3; /* Response FIFO Outstanding Byte Count */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t wfifocnt : 3; /* Command FIFO Outstanding Byte Count */ + const uint32_t active : 1; /* Scan-Chain Engine Active */ +}; + +/* The typedef declaration for register ALT_SCANMGR_STAT. */ +typedef volatile struct ALT_SCANMGR_STAT_s ALT_SCANMGR_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SCANMGR_STAT register from the beginning of the component. */ +#define ALT_SCANMGR_STAT_OFST 0x0 + +/* + * Register : Scan-Chain Enable Register - en + * + * This register is used to enable one of the 5 scan-chains (0-3 and 7). Only one + * scan-chain must be enabled at a time. A scan-chain is enabled by writing its + * corresponding enable field. + * + * Software must use the System Manager to put the corresponding I/O scan-chain + * into the frozen state before attempting to send I/O configuration data to the + * I/O scan-chain. + * + * Software must only write to this register when the Scan-Chain Engine is + * inactive.Writing this field at any other time has unpredictable results. This + * means that before writing to this field, software must read the STAT register + * and check that the ACTIVE and WFIFOCNT fields are both zero. + * + * The name of this register in ARM documentation is PSEL. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | I/O Scan-Chain 0 Enable + * [1] | RW | 0x0 | I/O Scan-Chain 1 Enable + * [2] | RW | 0x0 | I/O Scan-Chain 2 Enable + * [3] | RW | 0x0 | I/O Scan-Chain 3 Enable + * [6:4] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | FPGA JTAG Scan-Chain Enable + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : I/O Scan-Chain 0 Enable - ioscanchain0 + * + * Used to enable or disable I/O Scan-Chain 0 + * + * The name of this field in ARM documentation is PSEL0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_SCANMGR_EN_IOSCANCHAIN0_E_DIS | 0x0 | Disable scan-chain + * ALT_SCANMGR_EN_IOSCANCHAIN0_E_EN | 0x1 | Enable scan-chain + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN0 + * + * Disable scan-chain + */ +#define ALT_SCANMGR_EN_IOSCANCHAIN0_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN0 + * + * Enable scan-chain + */ +#define ALT_SCANMGR_EN_IOSCANCHAIN0_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN0_MSB 0 +/* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN0_WIDTH 1 +/* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN0 register field value. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN0 register field value. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN0 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN0_RESET 0x0 +/* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN0 field value from a register. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SCANMGR_EN_IOSCANCHAIN0 register field value suitable for setting the register. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : I/O Scan-Chain 1 Enable - ioscanchain1 + * + * Used to enable or disable I/O Scan-Chain 1 + * + * The name of this field in ARM documentation is PSEL1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_SCANMGR_EN_IOSCANCHAIN1_E_DIS | 0x0 | Disable scan-chain + * ALT_SCANMGR_EN_IOSCANCHAIN1_E_EN | 0x1 | Enable scan-chain + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN1 + * + * Disable scan-chain + */ +#define ALT_SCANMGR_EN_IOSCANCHAIN1_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN1 + * + * Enable scan-chain + */ +#define ALT_SCANMGR_EN_IOSCANCHAIN1_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN1_MSB 1 +/* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN1_WIDTH 1 +/* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN1 register field value. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN1 register field value. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN1 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN1_RESET 0x0 +/* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN1 field value from a register. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SCANMGR_EN_IOSCANCHAIN1 register field value suitable for setting the register. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : I/O Scan-Chain 2 Enable - ioscanchain2 + * + * Used to enable or disable I/O Scan-Chain 2 + * + * The name of this field in ARM documentation is PSEL2. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_SCANMGR_EN_IOSCANCHAIN2_E_DIS | 0x0 | Disable scan-chain + * ALT_SCANMGR_EN_IOSCANCHAIN2_E_EN | 0x1 | Enable scan-chain + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN2 + * + * Disable scan-chain + */ +#define ALT_SCANMGR_EN_IOSCANCHAIN2_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN2 + * + * Enable scan-chain + */ +#define ALT_SCANMGR_EN_IOSCANCHAIN2_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN2_MSB 2 +/* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN2_WIDTH 1 +/* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN2 register field value. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN2 register field value. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN2 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN2_RESET 0x0 +/* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN2 field value from a register. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SCANMGR_EN_IOSCANCHAIN2 register field value suitable for setting the register. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : I/O Scan-Chain 3 Enable - ioscanchain3 + * + * Used to enable or disable I/O Scan-Chain 3 + * + * The name of this field in ARM documentation is PSEL3. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_SCANMGR_EN_IOSCANCHAIN3_E_DIS | 0x0 | Disable scan-chain + * ALT_SCANMGR_EN_IOSCANCHAIN3_E_EN | 0x1 | Enable scan-chain + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN3 + * + * Disable scan-chain + */ +#define ALT_SCANMGR_EN_IOSCANCHAIN3_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SCANMGR_EN_IOSCANCHAIN3 + * + * Enable scan-chain + */ +#define ALT_SCANMGR_EN_IOSCANCHAIN3_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN3_MSB 3 +/* The width in bits of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN3_WIDTH 1 +/* The mask used to set the ALT_SCANMGR_EN_IOSCANCHAIN3 register field value. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SCANMGR_EN_IOSCANCHAIN3 register field value. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SCANMGR_EN_IOSCANCHAIN3 register field. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN3_RESET 0x0 +/* Extracts the ALT_SCANMGR_EN_IOSCANCHAIN3 field value from a register. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SCANMGR_EN_IOSCANCHAIN3 register field value suitable for setting the register. */ +#define ALT_SCANMGR_EN_IOSCANCHAIN3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : FPGA JTAG Scan-Chain Enable - fpgajtag + * + * Used to enable or disable FPGA JTAG scan-chain.Software must use the System + * Manager to enable the Scan Manager to drive the FPGA JTAG before attempting to + * communicate with the FPGA JTAG via the Scan Manager. + * + * The name of this field in ARM documentation is PSEL7. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------- + * ALT_SCANMGR_EN_FPGAJTAG_E_DIS | 0x0 | Disable scan-chain + * ALT_SCANMGR_EN_FPGAJTAG_E_EN | 0x1 | Enable scan-chain + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SCANMGR_EN_FPGAJTAG + * + * Disable scan-chain + */ +#define ALT_SCANMGR_EN_FPGAJTAG_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SCANMGR_EN_FPGAJTAG + * + * Enable scan-chain + */ +#define ALT_SCANMGR_EN_FPGAJTAG_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_EN_FPGAJTAG register field. */ +#define ALT_SCANMGR_EN_FPGAJTAG_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_EN_FPGAJTAG register field. */ +#define ALT_SCANMGR_EN_FPGAJTAG_MSB 7 +/* The width in bits of the ALT_SCANMGR_EN_FPGAJTAG register field. */ +#define ALT_SCANMGR_EN_FPGAJTAG_WIDTH 1 +/* The mask used to set the ALT_SCANMGR_EN_FPGAJTAG register field value. */ +#define ALT_SCANMGR_EN_FPGAJTAG_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SCANMGR_EN_FPGAJTAG register field value. */ +#define ALT_SCANMGR_EN_FPGAJTAG_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SCANMGR_EN_FPGAJTAG register field. */ +#define ALT_SCANMGR_EN_FPGAJTAG_RESET 0x0 +/* Extracts the ALT_SCANMGR_EN_FPGAJTAG field value from a register. */ +#define ALT_SCANMGR_EN_FPGAJTAG_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SCANMGR_EN_FPGAJTAG register field value suitable for setting the register. */ +#define ALT_SCANMGR_EN_FPGAJTAG_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SCANMGR_EN. + */ +struct ALT_SCANMGR_EN_s +{ + uint32_t ioscanchain0 : 1; /* I/O Scan-Chain 0 Enable */ + uint32_t ioscanchain1 : 1; /* I/O Scan-Chain 1 Enable */ + uint32_t ioscanchain2 : 1; /* I/O Scan-Chain 2 Enable */ + uint32_t ioscanchain3 : 1; /* I/O Scan-Chain 3 Enable */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t fpgajtag : 1; /* FPGA JTAG Scan-Chain Enable */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SCANMGR_EN. */ +typedef volatile struct ALT_SCANMGR_EN_s ALT_SCANMGR_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SCANMGR_EN register from the beginning of the component. */ +#define ALT_SCANMGR_EN_OFST 0x4 + +/* + * Register : FIFO Single Byte Register - fifosinglebyte + * + * Writes to the FIFO Single Byte Register write a single byte value to the command + * FIFO. If the command FIFO is full, the APB write operation is stalled until the + * command FIFO is not full. + * + * Reads from the Single Byte FIFO Register read a single byte value from the + * command FIFO. If the command FIFO is empty, the APB read operation is stalled + * until the command FIFO is not empty. + * + * See the ARM documentation for a description of the read and write values. + * + * The name of this register in ARM documentation is BWFIFO1 for writes and BRFIFO1 + * for reads. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------ + * [7:0] | RW | Unknown | Single Byte Value + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Single Byte Value - value + * + * Transfers single byte value to/from command FIFO + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_MSB 7 +/* The width in bits of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_WIDTH 8 +/* The mask used to set the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field value. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field value. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field is UNKNOWN. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_RESET 0x0 +/* Extracts the ALT_SCANMGR_FIFOSINGLEBYTE_VALUE field value from a register. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SCANMGR_FIFOSINGLEBYTE_VALUE register field value suitable for setting the register. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SCANMGR_FIFOSINGLEBYTE. + */ +struct ALT_SCANMGR_FIFOSINGLEBYTE_s +{ + uint32_t value : 8; /* Single Byte Value */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SCANMGR_FIFOSINGLEBYTE. */ +typedef volatile struct ALT_SCANMGR_FIFOSINGLEBYTE_s ALT_SCANMGR_FIFOSINGLEBYTE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SCANMGR_FIFOSINGLEBYTE register from the beginning of the component. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_OFST 0x10 + +/* + * Register : FIFO Double Byte Register - fifodoublebyte + * + * Writes to the FIFO Double Byte Register write a double byte value to the command + * FIFO. If the command FIFO is full, the APB write operation is stalled until the + * command FIFO is not full. + * + * Reads from the Double Byte FIFO Register read a double byte value from the + * command FIFO. If the command FIFO is empty, the APB read operation is stalled + * until the command FIFO is not empty. + * + * See the ARM documentation for a description of the read and write values. + * + * The name of this register in ARM documentation is BWFIFO2 for writes and BRFIFO2 + * for reads. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------ + * [15:0] | RW | Unknown | Double Byte Value + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Double Byte Value - value + * + * Transfers double byte value to/from command FIFO + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_MSB 15 +/* The width in bits of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_WIDTH 16 +/* The mask used to set the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field value. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field value. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field is UNKNOWN. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_RESET 0x0 +/* Extracts the ALT_SCANMGR_FIFODOUBLEBYTE_VALUE field value from a register. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SCANMGR_FIFODOUBLEBYTE_VALUE register field value suitable for setting the register. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_VALUE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SCANMGR_FIFODOUBLEBYTE. + */ +struct ALT_SCANMGR_FIFODOUBLEBYTE_s +{ + uint32_t value : 16; /* Double Byte Value */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SCANMGR_FIFODOUBLEBYTE. */ +typedef volatile struct ALT_SCANMGR_FIFODOUBLEBYTE_s ALT_SCANMGR_FIFODOUBLEBYTE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SCANMGR_FIFODOUBLEBYTE register from the beginning of the component. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_OFST 0x14 + +/* + * Register : FIFO Triple Byte Register - fifotriplebyte + * + * Writes to the FIFO Triple Byte Register write a triple byte value to the command + * FIFO. If the command FIFO is full, the APB write operation is stalled until the + * command FIFO is not full. + * + * Reads from the Triple Byte FIFO Register read a triple byte value from the + * command FIFO. If the command FIFO is empty, the APB read operation is stalled + * until the command FIFO is not empty. + * + * See the ARM documentation for a description of the read and write values. + * + * The name of this register in ARM documentation is BWFIFO3 for writes and BRFIFO3 + * for reads. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------ + * [23:0] | RW | Unknown | Triple Byte Value + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Triple Byte Value - value + * + * Transfers triple byte value to/from command FIFO + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_MSB 23 +/* The width in bits of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_WIDTH 24 +/* The mask used to set the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field value. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_SET_MSK 0x00ffffff +/* The mask used to clear the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field value. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_CLR_MSK 0xff000000 +/* The reset value of the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field is UNKNOWN. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_RESET 0x0 +/* Extracts the ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE field value from a register. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_GET(value) (((value) & 0x00ffffff) >> 0) +/* Produces a ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE register field value suitable for setting the register. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_VALUE_SET(value) (((value) << 0) & 0x00ffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SCANMGR_FIFOTRIPLEBYTE. + */ +struct ALT_SCANMGR_FIFOTRIPLEBYTE_s +{ + uint32_t value : 24; /* Triple Byte Value */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SCANMGR_FIFOTRIPLEBYTE. */ +typedef volatile struct ALT_SCANMGR_FIFOTRIPLEBYTE_s ALT_SCANMGR_FIFOTRIPLEBYTE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SCANMGR_FIFOTRIPLEBYTE register from the beginning of the component. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_OFST 0x18 + +/* + * Register : FIFO Quad Byte Register - fifoquadbyte + * + * Writes to the FIFO Quad Byte Register write a quad byte value to the command + * FIFO. If the command FIFO is full, the APB write operation is stalled until the + * command FIFO is not full. + * + * Reads from the Quad Byte FIFO Register read a quad byte value from the command + * FIFO. If the command FIFO is empty, the APB read operation is stalled until the + * command FIFO is not empty. + * + * See the ARM documentation for a description of the read and write values. + * + * The name of this register in ARM documentation is BWFIFO4 for writes and BRFIFO4 + * for reads. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:---------------- + * [31:0] | RW | Unknown | Quad Byte Value + * + */ +/* + * Field : Quad Byte Value - value + * + * Transfers quad byte value to/from command FIFO + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_MSB 31 +/* The width in bits of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field. */ +#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_WIDTH 32 +/* The mask used to set the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field value. */ +#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field value. */ +#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SCANMGR_FIFOQUADBYTE_VALUE register field is UNKNOWN. */ +#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_RESET 0x0 +/* Extracts the ALT_SCANMGR_FIFOQUADBYTE_VALUE field value from a register. */ +#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SCANMGR_FIFOQUADBYTE_VALUE register field value suitable for setting the register. */ +#define ALT_SCANMGR_FIFOQUADBYTE_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SCANMGR_FIFOQUADBYTE. + */ +struct ALT_SCANMGR_FIFOQUADBYTE_s +{ + uint32_t value : 32; /* Quad Byte Value */ +}; + +/* The typedef declaration for register ALT_SCANMGR_FIFOQUADBYTE. */ +typedef volatile struct ALT_SCANMGR_FIFOQUADBYTE_s ALT_SCANMGR_FIFOQUADBYTE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SCANMGR_FIFOQUADBYTE register from the beginning of the component. */ +#define ALT_SCANMGR_FIFOQUADBYTE_OFST 0x1c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SCANMGR. + */ +struct ALT_SCANMGR_s +{ + volatile ALT_SCANMGR_STAT_t stat; /* ALT_SCANMGR_STAT */ + volatile ALT_SCANMGR_EN_t en; /* ALT_SCANMGR_EN */ + volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ + volatile ALT_SCANMGR_FIFOSINGLEBYTE_t fifosinglebyte; /* ALT_SCANMGR_FIFOSINGLEBYTE */ + volatile ALT_SCANMGR_FIFODOUBLEBYTE_t fifodoublebyte; /* ALT_SCANMGR_FIFODOUBLEBYTE */ + volatile ALT_SCANMGR_FIFOTRIPLEBYTE_t fifotriplebyte; /* ALT_SCANMGR_FIFOTRIPLEBYTE */ + volatile ALT_SCANMGR_FIFOQUADBYTE_t fifoquadbyte; /* ALT_SCANMGR_FIFOQUADBYTE */ +}; + +/* The typedef declaration for register group ALT_SCANMGR. */ +typedef volatile struct ALT_SCANMGR_s ALT_SCANMGR_t; +/* The struct declaration for the raw register contents of register group ALT_SCANMGR. */ +struct ALT_SCANMGR_raw_s +{ + volatile uint32_t stat; /* ALT_SCANMGR_STAT */ + volatile uint32_t en; /* ALT_SCANMGR_EN */ + volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ + volatile uint32_t fifosinglebyte; /* ALT_SCANMGR_FIFOSINGLEBYTE */ + volatile uint32_t fifodoublebyte; /* ALT_SCANMGR_FIFODOUBLEBYTE */ + volatile uint32_t fifotriplebyte; /* ALT_SCANMGR_FIFOTRIPLEBYTE */ + volatile uint32_t fifoquadbyte; /* ALT_SCANMGR_FIFOQUADBYTE */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SCANMGR. */ +typedef volatile struct ALT_SCANMGR_raw_s ALT_SCANMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_SCANMGR_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdmmc.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdmmc.h new file mode 100644 index 000000000..e2e6e25c7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdmmc.h @@ -0,0 +1,9115 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_SDMMC */ + +#ifndef __ALTERA_ALT_SDMMC_H__ +#define __ALTERA_ALT_SDMMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : SDMMC Module - ALT_SDMMC + * SDMMC Module + * + * Registers in the SD/MMC module + * + */ +/* + * Register : Control Register - ctrl + * + * Sets various operating condiitions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [0] | RW | 0x0 | Controller Reset + * [1] | RW | 0x0 | FIFO Reset + * [2] | RW | 0x0 | Dma Reset + * [3] | ??? | 0x0 | *UNDEFINED* + * [4] | RW | 0x0 | Int Enable + * [5] | ??? | 0x0 | *UNDEFINED* + * [6] | RW | 0x0 | Read Wait + * [7] | RW | 0x0 | Send Irq Response + * [8] | RW | 0x0 | Abort Read Data + * [9] | RW | 0x0 | Send CCSD + * [10] | RW | 0x0 | Send Auto Stop CCSD + * [11] | RW | 0x0 | Ceata Device Interrupt Status + * [24:12] | ??? | 0x0 | *UNDEFINED* + * [25] | RW | 0x0 | Use Internal DMAC + * [31:26] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Controller Reset - controller_reset + * + * This bit resets the controller. This bit is auto-cleared after two l4_mp_clk and + * two sdmmc_clk clock cycles. This resets: + * + * * BIU/CIU interface + * + * * CIU and state machines + * + * * abort_read_data, send_irq_response, and read_wait bits of control register + * + * * start_cmd bit of command register + * + * Does not affect any registers, DMA interface, FIFO or host interrupts. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------ + * ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE | 0x0 | No change -default + * ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE | 0x1 | Reset SD/MMC controller + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_CTLLER_RST + * + * No change -default + */ +#define ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_CTLLER_RST + * + * Reset SD/MMC controller + */ +#define ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CTLLER_RST register field. */ +#define ALT_SDMMC_CTL_CTLLER_RST_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CTLLER_RST register field. */ +#define ALT_SDMMC_CTL_CTLLER_RST_MSB 0 +/* The width in bits of the ALT_SDMMC_CTL_CTLLER_RST register field. */ +#define ALT_SDMMC_CTL_CTLLER_RST_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_CTLLER_RST register field value. */ +#define ALT_SDMMC_CTL_CTLLER_RST_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_CTL_CTLLER_RST register field value. */ +#define ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_CTL_CTLLER_RST register field. */ +#define ALT_SDMMC_CTL_CTLLER_RST_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_CTLLER_RST field value from a register. */ +#define ALT_SDMMC_CTL_CTLLER_RST_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_CTL_CTLLER_RST register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_CTLLER_RST_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : FIFO Reset - fifo_reset + * + * This bit resets the FIFO. This bit is auto-cleared after completion of reset + * operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------ + * ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE | 0x0 | No change + * ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE | 0x1 | Reset to data FIFO To reset FIFO pointers + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_FIFO_RST + * + * No change + */ +#define ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_FIFO_RST + * + * Reset to data FIFO To reset FIFO pointers + */ +#define ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_FIFO_RST register field. */ +#define ALT_SDMMC_CTL_FIFO_RST_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_FIFO_RST register field. */ +#define ALT_SDMMC_CTL_FIFO_RST_MSB 1 +/* The width in bits of the ALT_SDMMC_CTL_FIFO_RST register field. */ +#define ALT_SDMMC_CTL_FIFO_RST_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_FIFO_RST register field value. */ +#define ALT_SDMMC_CTL_FIFO_RST_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDMMC_CTL_FIFO_RST register field value. */ +#define ALT_SDMMC_CTL_FIFO_RST_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDMMC_CTL_FIFO_RST register field. */ +#define ALT_SDMMC_CTL_FIFO_RST_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_FIFO_RST field value from a register. */ +#define ALT_SDMMC_CTL_FIFO_RST_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDMMC_CTL_FIFO_RST register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_FIFO_RST_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Dma Reset - dma_reset + * + * This bit resets the DMA interface control logic + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------------- + * ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE | 0x0 | No change + * ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE | 0x1 | Reset internal DMA interface control logic + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_DMA_RST + * + * No change + */ +#define ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_DMA_RST + * + * Reset internal DMA interface control logic + */ +#define ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_DMA_RST register field. */ +#define ALT_SDMMC_CTL_DMA_RST_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_DMA_RST register field. */ +#define ALT_SDMMC_CTL_DMA_RST_MSB 2 +/* The width in bits of the ALT_SDMMC_CTL_DMA_RST register field. */ +#define ALT_SDMMC_CTL_DMA_RST_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_DMA_RST register field value. */ +#define ALT_SDMMC_CTL_DMA_RST_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDMMC_CTL_DMA_RST register field value. */ +#define ALT_SDMMC_CTL_DMA_RST_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDMMC_CTL_DMA_RST register field. */ +#define ALT_SDMMC_CTL_DMA_RST_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_DMA_RST field value from a register. */ +#define ALT_SDMMC_CTL_DMA_RST_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDMMC_CTL_DMA_RST register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_DMA_RST_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Int Enable - int_enable + * + * This bit enables and disable interrupts if one or more unmasked interrupts are + * set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------- + * ALT_SDMMC_CTL_INT_EN_E_DISD | 0x0 | Disable Interrupts + * ALT_SDMMC_CTL_INT_EN_E_END | 0x1 | Enable interrupts + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_INT_EN + * + * Disable Interrupts + */ +#define ALT_SDMMC_CTL_INT_EN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_INT_EN + * + * Enable interrupts + */ +#define ALT_SDMMC_CTL_INT_EN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_INT_EN register field. */ +#define ALT_SDMMC_CTL_INT_EN_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_INT_EN register field. */ +#define ALT_SDMMC_CTL_INT_EN_MSB 4 +/* The width in bits of the ALT_SDMMC_CTL_INT_EN register field. */ +#define ALT_SDMMC_CTL_INT_EN_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_INT_EN register field value. */ +#define ALT_SDMMC_CTL_INT_EN_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDMMC_CTL_INT_EN register field value. */ +#define ALT_SDMMC_CTL_INT_EN_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDMMC_CTL_INT_EN register field. */ +#define ALT_SDMMC_CTL_INT_EN_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_INT_EN field value from a register. */ +#define ALT_SDMMC_CTL_INT_EN_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDMMC_CTL_INT_EN register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_INT_EN_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Read Wait - read_wait + * + * For sending read-wait to SDIO cards. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------- + * ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT | 0x0 | Read Wait + * ALT_SDMMC_CTL_RD_WAIT_E_ASSERT | 0x1 | Assert Read Wait + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_RD_WAIT + * + * Read Wait + */ +#define ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_RD_WAIT + * + * Assert Read Wait + */ +#define ALT_SDMMC_CTL_RD_WAIT_E_ASSERT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_RD_WAIT register field. */ +#define ALT_SDMMC_CTL_RD_WAIT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_RD_WAIT register field. */ +#define ALT_SDMMC_CTL_RD_WAIT_MSB 6 +/* The width in bits of the ALT_SDMMC_CTL_RD_WAIT register field. */ +#define ALT_SDMMC_CTL_RD_WAIT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_RD_WAIT register field value. */ +#define ALT_SDMMC_CTL_RD_WAIT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SDMMC_CTL_RD_WAIT register field value. */ +#define ALT_SDMMC_CTL_RD_WAIT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SDMMC_CTL_RD_WAIT register field. */ +#define ALT_SDMMC_CTL_RD_WAIT_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_RD_WAIT field value from a register. */ +#define ALT_SDMMC_CTL_RD_WAIT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SDMMC_CTL_RD_WAIT register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_RD_WAIT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Send Irq Response - send_irq_response + * + * Bit automatically clears once response is sent. To wait for MMC card interrupts, + * host issues CMD40, and SD/MMC waits for interrupt response from MMC card(s). In + * meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set + * this bit, at which time SD/MMC command state-machine sends CMD40 response on bus + * and returns to idle state. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------------- + * ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE | 0x0 | No change + * ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE | 0x1 | Send auto IRQ response + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_SEND_IRQ_RESPONSE + * + * No change + */ +#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_SEND_IRQ_RESPONSE + * + * Send auto IRQ response + */ +#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */ +#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */ +#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB 7 +/* The width in bits of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */ +#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value. */ +#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value. */ +#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */ +#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE field value from a register. */ +#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Abort Read Data - abort_read_data + * + * After suspend command is issued during read-transfer, software polls card to + * find when suspend happened. Once suspend occurs software sets bit to reset data + * state-machine, which is waiting for next block of data. Bit automatically clears + * once data statemachine resets to idle. Used in SDIO card suspend sequence. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE | 0x0 | No change + * ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE | 0x1 | Abort Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_ABT_RD_DATA + * + * No change + */ +#define ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_ABT_RD_DATA + * + * Abort Read + */ +#define ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */ +#define ALT_SDMMC_CTL_ABT_RD_DATA_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */ +#define ALT_SDMMC_CTL_ABT_RD_DATA_MSB 8 +/* The width in bits of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */ +#define ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_ABT_RD_DATA register field value. */ +#define ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SDMMC_CTL_ABT_RD_DATA register field value. */ +#define ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */ +#define ALT_SDMMC_CTL_ABT_RD_DATA_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_ABT_RD_DATA field value from a register. */ +#define ALT_SDMMC_CTL_ABT_RD_DATA_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SDMMC_CTL_ABT_RD_DATA register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_ABT_RD_DATA_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Send CCSD - send_ccsd + * + * When set, SD/MMC sends CCSD to CE-ATA device. Software sets this bit only if + * current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in + * CE-ATA device. Once the CCSD pattern is sent to device, SD/MMC automatically + * clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and + * generates interrupt to host if Command Done interrupt is not masked. + * + * NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the + * CCSD on the CMD line. Due to this, during the boundary conditions it may happen + * that CCSD is sent to the CE-ATA device, even if the device signalled CCS. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT | 0x0 | Clear bit if SD/MMC does not reset the bit + * ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT | 0x1 | Send Command Completion Signal Disable (CCSD) to + * : | | CE-ATA device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_SEND_CCSD + * + * Clear bit if SD/MMC does not reset the bit + */ +#define ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_SEND_CCSD + * + * Send Command Completion Signal Disable (CCSD) to CE-ATA device + */ +#define ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_CCSD register field. */ +#define ALT_SDMMC_CTL_SEND_CCSD_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_CCSD register field. */ +#define ALT_SDMMC_CTL_SEND_CCSD_MSB 9 +/* The width in bits of the ALT_SDMMC_CTL_SEND_CCSD register field. */ +#define ALT_SDMMC_CTL_SEND_CCSD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_SEND_CCSD register field value. */ +#define ALT_SDMMC_CTL_SEND_CCSD_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SDMMC_CTL_SEND_CCSD register field value. */ +#define ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SDMMC_CTL_SEND_CCSD register field. */ +#define ALT_SDMMC_CTL_SEND_CCSD_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_SEND_CCSD field value from a register. */ +#define ALT_SDMMC_CTL_SEND_CCSD_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SDMMC_CTL_SEND_CCSD register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_SEND_CCSD_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Send Auto Stop CCSD - send_auto_stop_ccsd + * + * Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd + * should not be set independent of send_ccsd. When set, SD/MMC automatically sends + * internally generated STOP command (CMD12) to CE-ATA device. After sending + * internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set + * and generates interrupt to host if Auto CommandDone interrupt is not masked. + * After sending the CCSD, SD/MMC automatically clears send_auto_stop_ccsd bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT | 0x0 | Clear bit if SD/MMC does not reset the bit + * ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT | 0x1 | Send internally generated STOP. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD + * + * Clear bit if SD/MMC does not reset the bit + */ +#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD + * + * Send internally generated STOP. + */ +#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */ +#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */ +#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB 10 +/* The width in bits of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */ +#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value. */ +#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value. */ +#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */ +#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD field value from a register. */ +#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Ceata Device Interrupt Status - ceata_device_interrupt_status + * + * Software should appropriately write to this bit after power-on reset or any + * other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is + * disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software + * should set this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------------- + * ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD | 0x0 | Interrupts not enabled in CE-ATA device + * ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END | 0x1 | Interrupts are enabled in CE-ATA device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT + * + * Interrupts not enabled in CE-ATA device + */ +#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT + * + * Interrupts are enabled in CE-ATA device + */ +#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */ +#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */ +#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB 11 +/* The width in bits of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */ +#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value. */ +#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value. */ +#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */ +#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT field value from a register. */ +#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Use Internal DMAC - use_internal_dmac + * + * Enable and Disable Internal DMA transfers. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------------------- + * ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD | 0x0 | The host performs data transfers thru slave + * : | | interface + * ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END | 0x1 | Internal DMAC used for data transfer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTL_USE_INTERNAL_DMAC + * + * The host performs data transfers thru slave interface + */ +#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTL_USE_INTERNAL_DMAC + * + * Internal DMAC used for data transfer + */ +#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */ +#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */ +#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB 25 +/* The width in bits of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */ +#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value. */ +#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK 0x02000000 +/* The mask used to clear the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value. */ +#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff +/* The reset value of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */ +#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET 0x0 +/* Extracts the ALT_SDMMC_CTL_USE_INTERNAL_DMAC field value from a register. */ +#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value suitable for setting the register. */ +#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_CTL. + */ +struct ALT_SDMMC_CTL_s +{ + uint32_t controller_reset : 1; /* Controller Reset */ + uint32_t fifo_reset : 1; /* FIFO Reset */ + uint32_t dma_reset : 1; /* Dma Reset */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t int_enable : 1; /* Int Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t read_wait : 1; /* Read Wait */ + uint32_t send_irq_response : 1; /* Send Irq Response */ + uint32_t abort_read_data : 1; /* Abort Read Data */ + uint32_t send_ccsd : 1; /* Send CCSD */ + uint32_t send_auto_stop_ccsd : 1; /* Send Auto Stop CCSD */ + uint32_t ceata_device_interrupt_status : 1; /* Ceata Device Interrupt Status */ + uint32_t : 13; /* *UNDEFINED* */ + uint32_t use_internal_dmac : 1; /* Use Internal DMAC */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_CTL. */ +typedef volatile struct ALT_SDMMC_CTL_s ALT_SDMMC_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_CTL register from the beginning of the component. */ +#define ALT_SDMMC_CTL_OFST 0x0 + +/* + * Register : Power Enable Register - pwren + * + * Power on/off switch for card; once power is turned on, firmware should wait for + * regulator/switch ramp-up time before trying to initialize card. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Power Enable + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Power Enable - power_enable + * + * Power on/off switch for one card; for example, bit[0] controls the card. Once + * power is turned on, firmware should wait for regulator/switch ramp-up time + * before trying to initialize card. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------ + * ALT_SDMMC_PWREN_POWER_EN_E_OFF | 0x0 | Power Off + * ALT_SDMMC_PWREN_POWER_EN_E_ON | 0x1 | Power On + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_PWREN_POWER_EN + * + * Power Off + */ +#define ALT_SDMMC_PWREN_POWER_EN_E_OFF 0x0 +/* + * Enumerated value for register field ALT_SDMMC_PWREN_POWER_EN + * + * Power On + */ +#define ALT_SDMMC_PWREN_POWER_EN_E_ON 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_PWREN_POWER_EN register field. */ +#define ALT_SDMMC_PWREN_POWER_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_PWREN_POWER_EN register field. */ +#define ALT_SDMMC_PWREN_POWER_EN_MSB 0 +/* The width in bits of the ALT_SDMMC_PWREN_POWER_EN register field. */ +#define ALT_SDMMC_PWREN_POWER_EN_WIDTH 1 +/* The mask used to set the ALT_SDMMC_PWREN_POWER_EN register field value. */ +#define ALT_SDMMC_PWREN_POWER_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_PWREN_POWER_EN register field value. */ +#define ALT_SDMMC_PWREN_POWER_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_PWREN_POWER_EN register field. */ +#define ALT_SDMMC_PWREN_POWER_EN_RESET 0x0 +/* Extracts the ALT_SDMMC_PWREN_POWER_EN field value from a register. */ +#define ALT_SDMMC_PWREN_POWER_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_PWREN_POWER_EN register field value suitable for setting the register. */ +#define ALT_SDMMC_PWREN_POWER_EN_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_PWREN. + */ +struct ALT_SDMMC_PWREN_s +{ + uint32_t power_enable : 1; /* Power Enable */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_PWREN. */ +typedef volatile struct ALT_SDMMC_PWREN_s ALT_SDMMC_PWREN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_PWREN register from the beginning of the component. */ +#define ALT_SDMMC_PWREN_OFST 0x4 + +/* + * Register : Clock Divider Register - clkdiv + * + * Divides Clock sdmmc_clk. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [7:0] | RW | 0x0 | Clk Divider 0 + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clk Divider 0 - clk_divider0 + * + * Clock divider-0 value. Clock division is 2*n. For example, value of 0 means + * divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, + * value of ff means divide by 2*255 = 510, and so on. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */ +#define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */ +#define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB 7 +/* The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */ +#define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH 8 +/* The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value. */ +#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value. */ +#define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */ +#define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET 0x0 +/* Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR0 field value from a register. */ +#define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value suitable for setting the register. */ +#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_CLKDIV. + */ +struct ALT_SDMMC_CLKDIV_s +{ + uint32_t clk_divider0 : 8; /* Clk Divider 0 */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_CLKDIV. */ +typedef volatile struct ALT_SDMMC_CLKDIV_s ALT_SDMMC_CLKDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_CLKDIV register from the beginning of the component. */ +#define ALT_SDMMC_CLKDIV_OFST 0x8 + +/* + * Register : SD Clock Source Register - clksrc + * + * Selects among available clock dividers. The sdmmc_cclk_out is always from clock + * divider 0. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [1:0] | RW | 0x0 | Clock Source + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clock Source - clk_source + * + * Selects among available clock dividers. The SD/MMC module is configured with + * just one clock divider so this register should always be set to choose clkdiv0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 | 0x0 | Clock divider 0 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CLKSRC_CLK_SRC + * + * Clock divider 0 + */ +#define ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */ +#define ALT_SDMMC_CLKSRC_CLK_SRC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */ +#define ALT_SDMMC_CLKSRC_CLK_SRC_MSB 1 +/* The width in bits of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */ +#define ALT_SDMMC_CLKSRC_CLK_SRC_WIDTH 2 +/* The mask used to set the ALT_SDMMC_CLKSRC_CLK_SRC register field value. */ +#define ALT_SDMMC_CLKSRC_CLK_SRC_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SDMMC_CLKSRC_CLK_SRC register field value. */ +#define ALT_SDMMC_CLKSRC_CLK_SRC_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */ +#define ALT_SDMMC_CLKSRC_CLK_SRC_RESET 0x0 +/* Extracts the ALT_SDMMC_CLKSRC_CLK_SRC field value from a register. */ +#define ALT_SDMMC_CLKSRC_CLK_SRC_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SDMMC_CLKSRC_CLK_SRC register field value suitable for setting the register. */ +#define ALT_SDMMC_CLKSRC_CLK_SRC_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_CLKSRC. + */ +struct ALT_SDMMC_CLKSRC_s +{ + uint32_t clk_source : 2; /* Clock Source */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_CLKSRC. */ +typedef volatile struct ALT_SDMMC_CLKSRC_s ALT_SDMMC_CLKSRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_CLKSRC register from the beginning of the component. */ +#define ALT_SDMMC_CLKSRC_OFST 0xc + +/* + * Register : Clock Enable Register - clkena + * + * Controls external SD/MMC Clock Enable. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------- + * [0] | RW | 0x0 | Cclk Enable + * [15:1] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | Cclk Low Power + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Cclk Enable - cclk_enable + * + * Enables sdmmc_cclk_out. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:--------------- + * ALT_SDMMC_CLKENA_CCLK_EN_E_DISD | 0x0 | SD/MMC Disable + * ALT_SDMMC_CLKENA_CCLK_EN_E_END | 0x1 | SD/MMC Enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_EN + * + * SD/MMC Disable + */ +#define ALT_SDMMC_CLKENA_CCLK_EN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_EN + * + * SD/MMC Enable + */ +#define ALT_SDMMC_CLKENA_CCLK_EN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKENA_CCLK_EN register field. */ +#define ALT_SDMMC_CLKENA_CCLK_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKENA_CCLK_EN register field. */ +#define ALT_SDMMC_CLKENA_CCLK_EN_MSB 0 +/* The width in bits of the ALT_SDMMC_CLKENA_CCLK_EN register field. */ +#define ALT_SDMMC_CLKENA_CCLK_EN_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CLKENA_CCLK_EN register field value. */ +#define ALT_SDMMC_CLKENA_CCLK_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_CLKENA_CCLK_EN register field value. */ +#define ALT_SDMMC_CLKENA_CCLK_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_CLKENA_CCLK_EN register field. */ +#define ALT_SDMMC_CLKENA_CCLK_EN_RESET 0x0 +/* Extracts the ALT_SDMMC_CLKENA_CCLK_EN field value from a register. */ +#define ALT_SDMMC_CLKENA_CCLK_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_CLKENA_CCLK_EN register field value suitable for setting the register. */ +#define ALT_SDMMC_CLKENA_CCLK_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Cclk Low Power - cclk_low_power + * + * In low-power mode, stop sdmmc_cclk_out when card in IDLE (should be normally set + * to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, + * clock should not be stopped). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------- + * ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD | 0x0 | Non-low-power mode + * ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END | 0x1 | Low-power mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_LOW_POWER + * + * Non-low-power mode + */ +#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_LOW_POWER + * + * Low-power mode + */ +#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */ +#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */ +#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_MSB 16 +/* The width in bits of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */ +#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value. */ +#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET_MSK 0x00010000 +/* The mask used to clear the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value. */ +#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_CLR_MSK 0xfffeffff +/* The reset value of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */ +#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_RESET 0x0 +/* Extracts the ALT_SDMMC_CLKENA_CCLK_LOW_POWER field value from a register. */ +#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value suitable for setting the register. */ +#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_CLKENA. + */ +struct ALT_SDMMC_CLKENA_s +{ + uint32_t cclk_enable : 1; /* Cclk Enable */ + uint32_t : 15; /* *UNDEFINED* */ + uint32_t cclk_low_power : 1; /* Cclk Low Power */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_CLKENA. */ +typedef volatile struct ALT_SDMMC_CLKENA_s ALT_SDMMC_CLKENA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_CLKENA register from the beginning of the component. */ +#define ALT_SDMMC_CLKENA_OFST 0x10 + +/* + * Register : Timeout Register - tmout + * + * Sets timeout values + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:---------|:----------------- + * [7:0] | RW | 0x40 | Response Timeout + * [31:8] | RW | 0xffffff | Data Timeout + * + */ +/* + * Field : Response Timeout - response_timeout + * + * Response timeout value. Value is in number of card output clocks sdmmc_cclk_out. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */ +#define ALT_SDMMC_TMOUT_RESPONSE_TMO_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */ +#define ALT_SDMMC_TMOUT_RESPONSE_TMO_MSB 7 +/* The width in bits of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */ +#define ALT_SDMMC_TMOUT_RESPONSE_TMO_WIDTH 8 +/* The mask used to set the ALT_SDMMC_TMOUT_RESPONSE_TMO register field value. */ +#define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDMMC_TMOUT_RESPONSE_TMO register field value. */ +#define ALT_SDMMC_TMOUT_RESPONSE_TMO_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */ +#define ALT_SDMMC_TMOUT_RESPONSE_TMO_RESET 0x40 +/* Extracts the ALT_SDMMC_TMOUT_RESPONSE_TMO field value from a register. */ +#define ALT_SDMMC_TMOUT_RESPONSE_TMO_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDMMC_TMOUT_RESPONSE_TMO register field value suitable for setting the register. */ +#define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Data Timeout - data_timeout + * + * Value for card Data Read Timeout; same value also used for Data Starvation by + * Host timeout. Value is in number of card output clocks sdmmc_cclk_out of + * selected card. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_TMOUT_DATA_TMO register field. */ +#define ALT_SDMMC_TMOUT_DATA_TMO_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_TMOUT_DATA_TMO register field. */ +#define ALT_SDMMC_TMOUT_DATA_TMO_MSB 31 +/* The width in bits of the ALT_SDMMC_TMOUT_DATA_TMO register field. */ +#define ALT_SDMMC_TMOUT_DATA_TMO_WIDTH 24 +/* The mask used to set the ALT_SDMMC_TMOUT_DATA_TMO register field value. */ +#define ALT_SDMMC_TMOUT_DATA_TMO_SET_MSK 0xffffff00 +/* The mask used to clear the ALT_SDMMC_TMOUT_DATA_TMO register field value. */ +#define ALT_SDMMC_TMOUT_DATA_TMO_CLR_MSK 0x000000ff +/* The reset value of the ALT_SDMMC_TMOUT_DATA_TMO register field. */ +#define ALT_SDMMC_TMOUT_DATA_TMO_RESET 0xffffff +/* Extracts the ALT_SDMMC_TMOUT_DATA_TMO field value from a register. */ +#define ALT_SDMMC_TMOUT_DATA_TMO_GET(value) (((value) & 0xffffff00) >> 8) +/* Produces a ALT_SDMMC_TMOUT_DATA_TMO register field value suitable for setting the register. */ +#define ALT_SDMMC_TMOUT_DATA_TMO_SET(value) (((value) << 8) & 0xffffff00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_TMOUT. + */ +struct ALT_SDMMC_TMOUT_s +{ + uint32_t response_timeout : 8; /* Response Timeout */ + uint32_t data_timeout : 24; /* Data Timeout */ +}; + +/* The typedef declaration for register ALT_SDMMC_TMOUT. */ +typedef volatile struct ALT_SDMMC_TMOUT_s ALT_SDMMC_TMOUT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_TMOUT register from the beginning of the component. */ +#define ALT_SDMMC_TMOUT_OFST 0x14 + +/* + * Register : Card Type Register - ctype + * + * Describes card formats. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [0] | RW | 0x0 | Card Width 1 or 4 Bits + * [15:1] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | Card Width 8 Bit + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Card Width 1 or 4 Bits - card_width2 + * + * Ignored if card_width1 is MODE8BIT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------ + * ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT | 0x0 | 1-bit mode + * ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT | 0x1 | 4-bit mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH2 + * + * 1-bit mode + */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH2 + * + * 4-bit mode + */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH2_MSB 0 +/* The width in bits of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH2_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field value. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field value. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH2_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH2_RESET 0x0 +/* Extracts the ALT_SDMMC_CTYPE_CARD_WIDTH2 field value from a register. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH2_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_CTYPE_CARD_WIDTH2 register field value suitable for setting the register. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Card Width 8 Bit - card_width1 + * + * Indicates if card is 8 bit or othersize. If not 8-bit, card_width2 specifies the + * width. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:--------------- + * ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT | 0x0 | Non 8-bit mode + * ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT | 0x1 | 8-bit mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH1 + * + * Non 8-bit mode + */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH1 + * + * 8-bit mode + */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH1_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH1_MSB 16 +/* The width in bits of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH1_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field value. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET_MSK 0x00010000 +/* The mask used to clear the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field value. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH1_CLR_MSK 0xfffeffff +/* The reset value of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH1_RESET 0x0 +/* Extracts the ALT_SDMMC_CTYPE_CARD_WIDTH1 field value from a register. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH1_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_SDMMC_CTYPE_CARD_WIDTH1 register field value suitable for setting the register. */ +#define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_CTYPE. + */ +struct ALT_SDMMC_CTYPE_s +{ + uint32_t card_width2 : 1; /* Card Width 1 or 4 Bits */ + uint32_t : 15; /* *UNDEFINED* */ + uint32_t card_width1 : 1; /* Card Width 8 Bit */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_CTYPE. */ +typedef volatile struct ALT_SDMMC_CTYPE_s ALT_SDMMC_CTYPE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_CTYPE register from the beginning of the component. */ +#define ALT_SDMMC_CTYPE_OFST 0x18 + +/* + * Register : Block Size Register - blksiz + * + * The Block Size. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [15:0] | RW | 0x200 | Block Size + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Block Size - block_size + * + * The size of a block in bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */ +#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */ +#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_MSB 15 +/* The width in bits of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */ +#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_WIDTH 16 +/* The mask used to set the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value. */ +#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value. */ +#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */ +#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_RESET 0x200 +/* Extracts the ALT_SDMMC_BLKSIZ_BLOCK_SIZE field value from a register. */ +#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value suitable for setting the register. */ +#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_BLKSIZ. + */ +struct ALT_SDMMC_BLKSIZ_s +{ + uint32_t block_size : 16; /* Block Size */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_BLKSIZ. */ +typedef volatile struct ALT_SDMMC_BLKSIZ_s ALT_SDMMC_BLKSIZ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_BLKSIZ register from the beginning of the component. */ +#define ALT_SDMMC_BLKSIZ_OFST 0x1c + +/* + * Register : Byte Count Register - bytcnt + * + * The number of bytes to be transferred. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x200 | Byte Count + * + */ +/* + * Field : Byte Count - byte_count + * + * This value should be an integer multiple of the Block Size for block transfers. + * For undefined number of byte transfers, byte count should be set to 0. When byte + * count is set to 0, it is responsibility of host to explicitly send stop/abort + * command to terminate data transfer. + * + * Note: In SDIO mode, if a single transfer is greater than 4 bytes and non-DWORD- + * aligned, the transfer should be broken where only the last transfer is non- + * DWORD-aligned and less than 4 bytes. For example, if a transfer of 129 bytes + * must occur, then the driver should start at least two transfers; one with 128 + * bytes and the other with 1 byte. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */ +#define ALT_SDMMC_BYTCNT_BYTE_COUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */ +#define ALT_SDMMC_BYTCNT_BYTE_COUNT_MSB 31 +/* The width in bits of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */ +#define ALT_SDMMC_BYTCNT_BYTE_COUNT_WIDTH 32 +/* The mask used to set the ALT_SDMMC_BYTCNT_BYTE_COUNT register field value. */ +#define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_BYTCNT_BYTE_COUNT register field value. */ +#define ALT_SDMMC_BYTCNT_BYTE_COUNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */ +#define ALT_SDMMC_BYTCNT_BYTE_COUNT_RESET 0x200 +/* Extracts the ALT_SDMMC_BYTCNT_BYTE_COUNT field value from a register. */ +#define ALT_SDMMC_BYTCNT_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_BYTCNT_BYTE_COUNT register field value suitable for setting the register. */ +#define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_BYTCNT. + */ +struct ALT_SDMMC_BYTCNT_s +{ + uint32_t byte_count : 32; /* Byte Count */ +}; + +/* The typedef declaration for register ALT_SDMMC_BYTCNT. */ +typedef volatile struct ALT_SDMMC_BYTCNT_s ALT_SDMMC_BYTCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_BYTCNT register from the beginning of the component. */ +#define ALT_SDMMC_BYTCNT_OFST 0x20 + +/* + * Register : Interrupt Mask Register - intmask + * + * Allows Masking of Various Interrupts + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------- + * [0] | RW | 0x0 | Card Detected + * [1] | RW | 0x0 | Response Error + * [2] | RW | 0x0 | Command Done + * [3] | RW | 0x0 | Data Transfer Over + * [4] | RW | 0x0 | Transmit FIFO Data Request + * [5] | RW | 0x0 | Receive FIFO Data Request ( + * [6] | RW | 0x0 | Response CRC Error + * [7] | RW | 0x0 | Data CRC Error + * [8] | RW | 0x0 | Response Timeout + * [9] | RW | 0x0 | Data Read Timeout + * [10] | RW | 0x0 | Data Starvation Host Timeout + * [11] | RW | 0x0 | FIFO Underrun Overrun Error + * [12] | RW | 0x0 | Hardware Locked Write Error + * [13] | RW | 0x0 | Start-bit Error + * [14] | RW | 0x0 | Auto Command Done + * [15] | RW | 0x0 | End-bit Error Read Write no CRC + * [16] | RW | 0x0 | SDIO Interrupt Mask + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Card Detected - cd + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------- + * ALT_SDMMC_INTMSK_CD_E_MSK | 0x0 | Card Detected Mask + * ALT_SDMMC_INTMSK_CD_E_NOMSK | 0x1 | Card Detect No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_CD + * + * Card Detected Mask + */ +#define ALT_SDMMC_INTMSK_CD_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_CD + * + * Card Detect No Mask + */ +#define ALT_SDMMC_INTMSK_CD_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_CD register field. */ +#define ALT_SDMMC_INTMSK_CD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_CD register field. */ +#define ALT_SDMMC_INTMSK_CD_MSB 0 +/* The width in bits of the ALT_SDMMC_INTMSK_CD register field. */ +#define ALT_SDMMC_INTMSK_CD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_CD register field value. */ +#define ALT_SDMMC_INTMSK_CD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_INTMSK_CD register field value. */ +#define ALT_SDMMC_INTMSK_CD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_INTMSK_CD register field. */ +#define ALT_SDMMC_INTMSK_CD_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_CD field value from a register. */ +#define ALT_SDMMC_INTMSK_CD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_INTMSK_CD register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_CD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Response Error - re + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------- + * ALT_SDMMC_INTMSK_RE_E_MSK | 0x0 | Response error Mask + * ALT_SDMMC_INTMSK_RE_E_NOMSK | 0x1 | Response error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_RE + * + * Response error Mask + */ +#define ALT_SDMMC_INTMSK_RE_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_RE + * + * Response error No Mask + */ +#define ALT_SDMMC_INTMSK_RE_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RE register field. */ +#define ALT_SDMMC_INTMSK_RE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RE register field. */ +#define ALT_SDMMC_INTMSK_RE_MSB 1 +/* The width in bits of the ALT_SDMMC_INTMSK_RE register field. */ +#define ALT_SDMMC_INTMSK_RE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_RE register field value. */ +#define ALT_SDMMC_INTMSK_RE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDMMC_INTMSK_RE register field value. */ +#define ALT_SDMMC_INTMSK_RE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDMMC_INTMSK_RE register field. */ +#define ALT_SDMMC_INTMSK_RE_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_RE field value from a register. */ +#define ALT_SDMMC_INTMSK_RE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDMMC_INTMSK_RE register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_RE_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Command Done - cmd + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:--------------------- + * ALT_SDMMC_INTMSK_CMD_E_MSK | 0x0 | Command Done Mask + * ALT_SDMMC_INTMSK_CMD_E_NOMSK | 0x1 | Command Done No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_CMD + * + * Command Done Mask + */ +#define ALT_SDMMC_INTMSK_CMD_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_CMD + * + * Command Done No Mask + */ +#define ALT_SDMMC_INTMSK_CMD_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_CMD register field. */ +#define ALT_SDMMC_INTMSK_CMD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_CMD register field. */ +#define ALT_SDMMC_INTMSK_CMD_MSB 2 +/* The width in bits of the ALT_SDMMC_INTMSK_CMD register field. */ +#define ALT_SDMMC_INTMSK_CMD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_CMD register field value. */ +#define ALT_SDMMC_INTMSK_CMD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDMMC_INTMSK_CMD register field value. */ +#define ALT_SDMMC_INTMSK_CMD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDMMC_INTMSK_CMD register field. */ +#define ALT_SDMMC_INTMSK_CMD_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_CMD field value from a register. */ +#define ALT_SDMMC_INTMSK_CMD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDMMC_INTMSK_CMD register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_CMD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Data Transfer Over - dto + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:--------------------------- + * ALT_SDMMC_INTMSK_DTO_E_MSK | 0x0 | Data transfer over Mask + * ALT_SDMMC_INTMSK_DTO_E_NOMSK | 0x1 | Data transfer over No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_DTO + * + * Data transfer over Mask + */ +#define ALT_SDMMC_INTMSK_DTO_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_DTO + * + * Data transfer over No Mask + */ +#define ALT_SDMMC_INTMSK_DTO_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DTO register field. */ +#define ALT_SDMMC_INTMSK_DTO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DTO register field. */ +#define ALT_SDMMC_INTMSK_DTO_MSB 3 +/* The width in bits of the ALT_SDMMC_INTMSK_DTO register field. */ +#define ALT_SDMMC_INTMSK_DTO_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_DTO register field value. */ +#define ALT_SDMMC_INTMSK_DTO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDMMC_INTMSK_DTO register field value. */ +#define ALT_SDMMC_INTMSK_DTO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDMMC_INTMSK_DTO register field. */ +#define ALT_SDMMC_INTMSK_DTO_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_DTO field value from a register. */ +#define ALT_SDMMC_INTMSK_DTO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDMMC_INTMSK_DTO register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_DTO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Transmit FIFO Data Request - txdr + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------------- + * ALT_SDMMC_INTMSK_TXDR_E_MSK | 0x0 | Transmit FIFO data request Mask + * ALT_SDMMC_INTMSK_TXDR_E_NOMSK | 0x1 | Transmit FIFO data request No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_TXDR + * + * Transmit FIFO data request Mask + */ +#define ALT_SDMMC_INTMSK_TXDR_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_TXDR + * + * Transmit FIFO data request No Mask + */ +#define ALT_SDMMC_INTMSK_TXDR_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_TXDR register field. */ +#define ALT_SDMMC_INTMSK_TXDR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_TXDR register field. */ +#define ALT_SDMMC_INTMSK_TXDR_MSB 4 +/* The width in bits of the ALT_SDMMC_INTMSK_TXDR register field. */ +#define ALT_SDMMC_INTMSK_TXDR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_TXDR register field value. */ +#define ALT_SDMMC_INTMSK_TXDR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDMMC_INTMSK_TXDR register field value. */ +#define ALT_SDMMC_INTMSK_TXDR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDMMC_INTMSK_TXDR register field. */ +#define ALT_SDMMC_INTMSK_TXDR_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_TXDR field value from a register. */ +#define ALT_SDMMC_INTMSK_TXDR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDMMC_INTMSK_TXDR register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_TXDR_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Receive FIFO Data Request ( - rxdr + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------------------- + * ALT_SDMMC_INTMSK_RXDR_E_MSK | 0x0 | Receive FIFO data request Mask + * ALT_SDMMC_INTMSK_RXDR_E_NOMSK | 0x1 | Receive FIFO data request No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_RXDR + * + * Receive FIFO data request Mask + */ +#define ALT_SDMMC_INTMSK_RXDR_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_RXDR + * + * Receive FIFO data request No Mask + */ +#define ALT_SDMMC_INTMSK_RXDR_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RXDR register field. */ +#define ALT_SDMMC_INTMSK_RXDR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RXDR register field. */ +#define ALT_SDMMC_INTMSK_RXDR_MSB 5 +/* The width in bits of the ALT_SDMMC_INTMSK_RXDR register field. */ +#define ALT_SDMMC_INTMSK_RXDR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_RXDR register field value. */ +#define ALT_SDMMC_INTMSK_RXDR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SDMMC_INTMSK_RXDR register field value. */ +#define ALT_SDMMC_INTMSK_RXDR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SDMMC_INTMSK_RXDR register field. */ +#define ALT_SDMMC_INTMSK_RXDR_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_RXDR field value from a register. */ +#define ALT_SDMMC_INTMSK_RXDR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SDMMC_INTMSK_RXDR register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_RXDR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Response CRC Error - rcrc + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:--------------------------- + * ALT_SDMMC_INTMSK_RCRC_E_MSK | 0x0 | Response CRC error Mask + * ALT_SDMMC_INTMSK_RCRC_E_NOMSK | 0x1 | Response CRC error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_RCRC + * + * Response CRC error Mask + */ +#define ALT_SDMMC_INTMSK_RCRC_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_RCRC + * + * Response CRC error No Mask + */ +#define ALT_SDMMC_INTMSK_RCRC_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RCRC register field. */ +#define ALT_SDMMC_INTMSK_RCRC_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RCRC register field. */ +#define ALT_SDMMC_INTMSK_RCRC_MSB 6 +/* The width in bits of the ALT_SDMMC_INTMSK_RCRC register field. */ +#define ALT_SDMMC_INTMSK_RCRC_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_RCRC register field value. */ +#define ALT_SDMMC_INTMSK_RCRC_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SDMMC_INTMSK_RCRC register field value. */ +#define ALT_SDMMC_INTMSK_RCRC_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SDMMC_INTMSK_RCRC register field. */ +#define ALT_SDMMC_INTMSK_RCRC_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_RCRC field value from a register. */ +#define ALT_SDMMC_INTMSK_RCRC_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SDMMC_INTMSK_RCRC register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_RCRC_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Data CRC Error - dcrc + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------- + * ALT_SDMMC_INTMSK_DCRC_E_MSK | 0x0 | Data CRC error Mask + * ALT_SDMMC_INTMSK_DCRC_E_NOMSK | 0x1 | Data CRC error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_DCRC + * + * Data CRC error Mask + */ +#define ALT_SDMMC_INTMSK_DCRC_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_DCRC + * + * Data CRC error No Mask + */ +#define ALT_SDMMC_INTMSK_DCRC_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DCRC register field. */ +#define ALT_SDMMC_INTMSK_DCRC_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DCRC register field. */ +#define ALT_SDMMC_INTMSK_DCRC_MSB 7 +/* The width in bits of the ALT_SDMMC_INTMSK_DCRC register field. */ +#define ALT_SDMMC_INTMSK_DCRC_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_DCRC register field value. */ +#define ALT_SDMMC_INTMSK_DCRC_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SDMMC_INTMSK_DCRC register field value. */ +#define ALT_SDMMC_INTMSK_DCRC_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SDMMC_INTMSK_DCRC register field. */ +#define ALT_SDMMC_INTMSK_DCRC_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_DCRC field value from a register. */ +#define ALT_SDMMC_INTMSK_DCRC_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SDMMC_INTMSK_DCRC register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_DCRC_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Response Timeout - rto + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------------- + * ALT_SDMMC_INTMSK_RTO_E_MSK | 0x0 | Response timeout Mask + * ALT_SDMMC_INTMSK_RTO_E_NOMSK | 0x1 | Response timeout No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_RTO + * + * Response timeout Mask + */ +#define ALT_SDMMC_INTMSK_RTO_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_RTO + * + * Response timeout No Mask + */ +#define ALT_SDMMC_INTMSK_RTO_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RTO register field. */ +#define ALT_SDMMC_INTMSK_RTO_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RTO register field. */ +#define ALT_SDMMC_INTMSK_RTO_MSB 8 +/* The width in bits of the ALT_SDMMC_INTMSK_RTO register field. */ +#define ALT_SDMMC_INTMSK_RTO_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_RTO register field value. */ +#define ALT_SDMMC_INTMSK_RTO_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SDMMC_INTMSK_RTO register field value. */ +#define ALT_SDMMC_INTMSK_RTO_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SDMMC_INTMSK_RTO register field. */ +#define ALT_SDMMC_INTMSK_RTO_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_RTO field value from a register. */ +#define ALT_SDMMC_INTMSK_RTO_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SDMMC_INTMSK_RTO register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_RTO_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Data Read Timeout - drt + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------- + * ALT_SDMMC_INTMSK_DRT_E_MSK | 0x0 | Data read timeout Mask + * ALT_SDMMC_INTMSK_DRT_E_NOMSK | 0x1 | Data read timeout No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_DRT + * + * Data read timeout Mask + */ +#define ALT_SDMMC_INTMSK_DRT_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_DRT + * + * Data read timeout No Mask + */ +#define ALT_SDMMC_INTMSK_DRT_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DRT register field. */ +#define ALT_SDMMC_INTMSK_DRT_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DRT register field. */ +#define ALT_SDMMC_INTMSK_DRT_MSB 9 +/* The width in bits of the ALT_SDMMC_INTMSK_DRT register field. */ +#define ALT_SDMMC_INTMSK_DRT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_DRT register field value. */ +#define ALT_SDMMC_INTMSK_DRT_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SDMMC_INTMSK_DRT register field value. */ +#define ALT_SDMMC_INTMSK_DRT_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SDMMC_INTMSK_DRT register field. */ +#define ALT_SDMMC_INTMSK_DRT_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_DRT field value from a register. */ +#define ALT_SDMMC_INTMSK_DRT_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SDMMC_INTMSK_DRT register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_DRT_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Starvation Host Timeout - hto + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------------------------- + * ALT_SDMMC_INTMSK_HTO_E_MSK | 0x0 | Data starvation by host timeout Mask + * ALT_SDMMC_INTMSK_HTO_E_NOMSK | 0x1 | Data starvation by host timeout No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_HTO + * + * Data starvation by host timeout Mask + */ +#define ALT_SDMMC_INTMSK_HTO_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_HTO + * + * Data starvation by host timeout No Mask + */ +#define ALT_SDMMC_INTMSK_HTO_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_HTO register field. */ +#define ALT_SDMMC_INTMSK_HTO_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_HTO register field. */ +#define ALT_SDMMC_INTMSK_HTO_MSB 10 +/* The width in bits of the ALT_SDMMC_INTMSK_HTO register field. */ +#define ALT_SDMMC_INTMSK_HTO_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_HTO register field value. */ +#define ALT_SDMMC_INTMSK_HTO_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SDMMC_INTMSK_HTO register field value. */ +#define ALT_SDMMC_INTMSK_HTO_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SDMMC_INTMSK_HTO register field. */ +#define ALT_SDMMC_INTMSK_HTO_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_HTO field value from a register. */ +#define ALT_SDMMC_INTMSK_HTO_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SDMMC_INTMSK_HTO register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_HTO_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : FIFO Underrun Overrun Error - frun + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------ + * ALT_SDMMC_INTMSK_FRUN_E_MSK | 0x0 | FIFO underrun/overrun error Mask + * ALT_SDMMC_INTMSK_FRUN_E_NOMSK | 0x1 | FIFO underrun/overrun error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_FRUN + * + * FIFO underrun/overrun error Mask + */ +#define ALT_SDMMC_INTMSK_FRUN_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_FRUN + * + * FIFO underrun/overrun error No Mask + */ +#define ALT_SDMMC_INTMSK_FRUN_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_FRUN register field. */ +#define ALT_SDMMC_INTMSK_FRUN_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_FRUN register field. */ +#define ALT_SDMMC_INTMSK_FRUN_MSB 11 +/* The width in bits of the ALT_SDMMC_INTMSK_FRUN register field. */ +#define ALT_SDMMC_INTMSK_FRUN_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_FRUN register field value. */ +#define ALT_SDMMC_INTMSK_FRUN_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SDMMC_INTMSK_FRUN register field value. */ +#define ALT_SDMMC_INTMSK_FRUN_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SDMMC_INTMSK_FRUN register field. */ +#define ALT_SDMMC_INTMSK_FRUN_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_FRUN field value from a register. */ +#define ALT_SDMMC_INTMSK_FRUN_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SDMMC_INTMSK_FRUN register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_FRUN_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Hardware Locked Write Error - hle + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------------------------ + * ALT_SDMMC_INTMSK_HLE_E_MSK | 0x0 | Hardware locked write error Mask + * ALT_SDMMC_INTMSK_HLE_E_NOMSK | 0x1 | Hardware locked write error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_HLE + * + * Hardware locked write error Mask + */ +#define ALT_SDMMC_INTMSK_HLE_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_HLE + * + * Hardware locked write error No Mask + */ +#define ALT_SDMMC_INTMSK_HLE_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_HLE register field. */ +#define ALT_SDMMC_INTMSK_HLE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_HLE register field. */ +#define ALT_SDMMC_INTMSK_HLE_MSB 12 +/* The width in bits of the ALT_SDMMC_INTMSK_HLE register field. */ +#define ALT_SDMMC_INTMSK_HLE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_HLE register field value. */ +#define ALT_SDMMC_INTMSK_HLE_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SDMMC_INTMSK_HLE register field value. */ +#define ALT_SDMMC_INTMSK_HLE_CLR_MSK 0xffffefff +/* The reset value of the ALT_SDMMC_INTMSK_HLE register field. */ +#define ALT_SDMMC_INTMSK_HLE_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_HLE field value from a register. */ +#define ALT_SDMMC_INTMSK_HLE_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SDMMC_INTMSK_HLE register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_HLE_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Start-bit Error - sbe + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------------ + * ALT_SDMMC_INTMSK_SBE_E_MSK | 0x0 | Start-bit error Mask + * ALT_SDMMC_INTMSK_SBE_E_NOMSK | 0x1 | Start-bit error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_SBE + * + * Start-bit error Mask + */ +#define ALT_SDMMC_INTMSK_SBE_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_SBE + * + * Start-bit error No Mask + */ +#define ALT_SDMMC_INTMSK_SBE_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_SBE register field. */ +#define ALT_SDMMC_INTMSK_SBE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_SBE register field. */ +#define ALT_SDMMC_INTMSK_SBE_MSB 13 +/* The width in bits of the ALT_SDMMC_INTMSK_SBE register field. */ +#define ALT_SDMMC_INTMSK_SBE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_SBE register field value. */ +#define ALT_SDMMC_INTMSK_SBE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SDMMC_INTMSK_SBE register field value. */ +#define ALT_SDMMC_INTMSK_SBE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SDMMC_INTMSK_SBE register field. */ +#define ALT_SDMMC_INTMSK_SBE_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_SBE field value from a register. */ +#define ALT_SDMMC_INTMSK_SBE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SDMMC_INTMSK_SBE register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_SBE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Auto Command Done - acd + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------- + * ALT_SDMMC_INTMSK_ACD_E_MSK | 0x0 | Auto command done Mask + * ALT_SDMMC_INTMSK_ACD_E_NOMSK | 0x1 | Auto command done No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_ACD + * + * Auto command done Mask + */ +#define ALT_SDMMC_INTMSK_ACD_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_ACD + * + * Auto command done No Mask + */ +#define ALT_SDMMC_INTMSK_ACD_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_ACD register field. */ +#define ALT_SDMMC_INTMSK_ACD_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_ACD register field. */ +#define ALT_SDMMC_INTMSK_ACD_MSB 14 +/* The width in bits of the ALT_SDMMC_INTMSK_ACD register field. */ +#define ALT_SDMMC_INTMSK_ACD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_ACD register field value. */ +#define ALT_SDMMC_INTMSK_ACD_SET_MSK 0x00004000 +/* The mask used to clear the ALT_SDMMC_INTMSK_ACD register field value. */ +#define ALT_SDMMC_INTMSK_ACD_CLR_MSK 0xffffbfff +/* The reset value of the ALT_SDMMC_INTMSK_ACD register field. */ +#define ALT_SDMMC_INTMSK_ACD_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_ACD field value from a register. */ +#define ALT_SDMMC_INTMSK_ACD_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_SDMMC_INTMSK_ACD register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_ACD_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : End-bit Error Read Write no CRC - ebe + * + * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 + * enables interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------- + * ALT_SDMMC_INTMSK_EBE_E_MSK | 0x0 | End-bit error Mask + * ALT_SDMMC_INTMSK_EBE_E_NOMSK | 0x1 | End-bit error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_EBE + * + * End-bit error Mask + */ +#define ALT_SDMMC_INTMSK_EBE_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_EBE + * + * End-bit error No Mask + */ +#define ALT_SDMMC_INTMSK_EBE_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_EBE register field. */ +#define ALT_SDMMC_INTMSK_EBE_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_EBE register field. */ +#define ALT_SDMMC_INTMSK_EBE_MSB 15 +/* The width in bits of the ALT_SDMMC_INTMSK_EBE register field. */ +#define ALT_SDMMC_INTMSK_EBE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_EBE register field value. */ +#define ALT_SDMMC_INTMSK_EBE_SET_MSK 0x00008000 +/* The mask used to clear the ALT_SDMMC_INTMSK_EBE register field value. */ +#define ALT_SDMMC_INTMSK_EBE_CLR_MSK 0xffff7fff +/* The reset value of the ALT_SDMMC_INTMSK_EBE register field. */ +#define ALT_SDMMC_INTMSK_EBE_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_EBE field value from a register. */ +#define ALT_SDMMC_INTMSK_EBE_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_SDMMC_INTMSK_EBE register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_EBE_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : SDIO Interrupt Mask - sdio_int_mask + * + * In current application, MMC-Ver3.3 only Bit 16 of this field is used. Bits 17 to + * 31 are unused and return 0 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------- + * ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD | 0x0 | SDIO Mask Interrupt Disabled + * ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END | 0x1 | SDIO Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_SDIO_INT_MSK + * + * SDIO Mask Interrupt Disabled + */ +#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_INTMSK_SDIO_INT_MSK + * + * SDIO Interrupt Enabled + */ +#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */ +#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */ +#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_MSB 16 +/* The width in bits of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */ +#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_WIDTH 1 +/* The mask used to set the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value. */ +#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET_MSK 0x00010000 +/* The mask used to clear the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value. */ +#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_CLR_MSK 0xfffeffff +/* The reset value of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */ +#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_RESET 0x0 +/* Extracts the ALT_SDMMC_INTMSK_SDIO_INT_MSK field value from a register. */ +#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value suitable for setting the register. */ +#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_INTMSK. + */ +struct ALT_SDMMC_INTMSK_s +{ + uint32_t cd : 1; /* Card Detected */ + uint32_t re : 1; /* Response Error */ + uint32_t cmd : 1; /* Command Done */ + uint32_t dto : 1; /* Data Transfer Over */ + uint32_t txdr : 1; /* Transmit FIFO Data Request */ + uint32_t rxdr : 1; /* Receive FIFO Data Request ( */ + uint32_t rcrc : 1; /* Response CRC Error */ + uint32_t dcrc : 1; /* Data CRC Error */ + uint32_t rto : 1; /* Response Timeout */ + uint32_t drt : 1; /* Data Read Timeout */ + uint32_t hto : 1; /* Data Starvation Host Timeout */ + uint32_t frun : 1; /* FIFO Underrun Overrun Error */ + uint32_t hle : 1; /* Hardware Locked Write Error */ + uint32_t sbe : 1; /* Start-bit Error */ + uint32_t acd : 1; /* Auto Command Done */ + uint32_t ebe : 1; /* End-bit Error Read Write no CRC */ + uint32_t sdio_int_mask : 1; /* SDIO Interrupt Mask */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_INTMSK. */ +typedef volatile struct ALT_SDMMC_INTMSK_s ALT_SDMMC_INTMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_INTMSK register from the beginning of the component. */ +#define ALT_SDMMC_INTMSK_OFST 0x24 + +/* + * Register : Command Argument Register - cmdarg + * + * See Field Description. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | Cmd Arg + * + */ +/* + * Field : Cmd Arg - cmd_arg + * + * Values indicates command argument to be passed to card. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMDARG_CMD_ARG register field. */ +#define ALT_SDMMC_CMDARG_CMD_ARG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMDARG_CMD_ARG register field. */ +#define ALT_SDMMC_CMDARG_CMD_ARG_MSB 31 +/* The width in bits of the ALT_SDMMC_CMDARG_CMD_ARG register field. */ +#define ALT_SDMMC_CMDARG_CMD_ARG_WIDTH 32 +/* The mask used to set the ALT_SDMMC_CMDARG_CMD_ARG register field value. */ +#define ALT_SDMMC_CMDARG_CMD_ARG_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_CMDARG_CMD_ARG register field value. */ +#define ALT_SDMMC_CMDARG_CMD_ARG_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_CMDARG_CMD_ARG register field. */ +#define ALT_SDMMC_CMDARG_CMD_ARG_RESET 0x0 +/* Extracts the ALT_SDMMC_CMDARG_CMD_ARG field value from a register. */ +#define ALT_SDMMC_CMDARG_CMD_ARG_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_CMDARG_CMD_ARG register field value suitable for setting the register. */ +#define ALT_SDMMC_CMDARG_CMD_ARG_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_CMDARG. + */ +struct ALT_SDMMC_CMDARG_s +{ + uint32_t cmd_arg : 32; /* Cmd Arg */ +}; + +/* The typedef declaration for register ALT_SDMMC_CMDARG. */ +typedef volatile struct ALT_SDMMC_CMDARG_s ALT_SDMMC_CMDARG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_CMDARG register from the beginning of the component. */ +#define ALT_SDMMC_CMDARG_OFST 0x28 + +/* + * Register : Command Register - cmd + * + * This register issues various commands. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [5:0] | RW | 0x0 | Cmd Index + * [6] | RW | 0x0 | Response Expect + * [7] | RW | 0x0 | Response Length + * [8] | RW | 0x0 | Check Response Crc + * [9] | RW | 0x0 | Data Transfer Expected + * [10] | RW | 0x0 | Read Write + * [11] | RW | 0x0 | Transfer Mode + * [12] | RW | 0x0 | Send Auto Stop + * [13] | RW | 0x0 | Wait Previous Data Complete + * [14] | RW | 0x0 | Stop Abort Cmd + * [15] | RW | 0x0 | Send Initialization + * [20:16] | RW | 0x0 | Card Number + * [21] | RW | 0x0 | Update Clock Registers Only + * [22] | RW | 0x0 | Read CE-ATA Device + * [23] | RW | 0x0 | Command Completion Signal Expected + * [24] | RW | 0x0 | Enable Boot + * [25] | RW | 0x0 | Expect Boot Ack + * [26] | RW | 0x0 | Disable Boot + * [27] | RW | 0x0 | Boot Mode + * [28] | RW | 0x0 | Volt Switch + * [29] | RW | 0x1 | Use Hold Reg + * [30] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Start Cmd + * + */ +/* + * Field : Cmd Index - cmd_index + * + * Tracks the command index number. Values from 0-31. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CMD_INDEX register field. */ +#define ALT_SDMMC_CMD_CMD_INDEX_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CMD_INDEX register field. */ +#define ALT_SDMMC_CMD_CMD_INDEX_MSB 5 +/* The width in bits of the ALT_SDMMC_CMD_CMD_INDEX register field. */ +#define ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6 +/* The mask used to set the ALT_SDMMC_CMD_CMD_INDEX register field value. */ +#define ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f +/* The mask used to clear the ALT_SDMMC_CMD_CMD_INDEX register field value. */ +#define ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0 +/* The reset value of the ALT_SDMMC_CMD_CMD_INDEX register field. */ +#define ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_CMD_INDEX field value from a register. */ +#define ALT_SDMMC_CMD_CMD_INDEX_GET(value) (((value) & 0x0000003f) >> 0) +/* Produces a ALT_SDMMC_CMD_CMD_INDEX register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_CMD_INDEX_SET(value) (((value) << 0) & 0x0000003f) + +/* + * Field : Response Expect - response_expect + * + * Response expected from card. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------- + * ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP | 0x0 | No response expected from card + * ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP | 0x1 | Response expected from card + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_EXPECT + * + * No response expected from card + */ +#define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_EXPECT + * + * Response expected from card + */ +#define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */ +#define ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */ +#define ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6 +/* The width in bits of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */ +#define ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_RESPONSE_EXPECT register field value. */ +#define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SDMMC_CMD_RESPONSE_EXPECT register field value. */ +#define ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */ +#define ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_RESPONSE_EXPECT field value from a register. */ +#define ALT_SDMMC_CMD_RESPONSE_EXPECT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SDMMC_CMD_RESPONSE_EXPECT register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Response Length - response_length + * + * Provides long and short response + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------------- + * ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT | 0x0 | Short response expected from card + * ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG | 0x1 | Long response expected from card + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_LEN + * + * Short response expected from card + */ +#define ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_LEN + * + * Long response expected from card + */ +#define ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */ +#define ALT_SDMMC_CMD_RESPONSE_LEN_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */ +#define ALT_SDMMC_CMD_RESPONSE_LEN_MSB 7 +/* The width in bits of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */ +#define ALT_SDMMC_CMD_RESPONSE_LEN_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_RESPONSE_LEN register field value. */ +#define ALT_SDMMC_CMD_RESPONSE_LEN_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SDMMC_CMD_RESPONSE_LEN register field value. */ +#define ALT_SDMMC_CMD_RESPONSE_LEN_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */ +#define ALT_SDMMC_CMD_RESPONSE_LEN_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_RESPONSE_LEN field value from a register. */ +#define ALT_SDMMC_CMD_RESPONSE_LEN_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SDMMC_CMD_RESPONSE_LEN register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_RESPONSE_LEN_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Check Response Crc - check_response_crc + * + * Some of command responses do not return valid CRC bits. Software should disable + * CRC checks for those commands in order to disable CRC checking by controller. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------- + * ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK | 0x0 | Do not check response CRC + * ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK | 0x1 | Check Response CRC + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_CHECK_RESPONSE_CRC + * + * Do not check response CRC + */ +#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_CHECK_RESPONSE_CRC + * + * Check Response CRC + */ +#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */ +#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */ +#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8 +/* The width in bits of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */ +#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value. */ +#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value. */ +#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */ +#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC field value from a register. */ +#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Data Transfer Expected - data_expected + * + * Set decision on data transfer expecetd or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:--------------------------------------- + * ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP | 0x0 | No data transfer expected (read/write) + * ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP | 0x1 | Data transfer expected (read/write) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_DATA_EXPECTED + * + * No data transfer expected (read/write) + */ +#define ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_DATA_EXPECTED + * + * Data transfer expected (read/write) + */ +#define ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */ +#define ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */ +#define ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9 +/* The width in bits of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */ +#define ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_DATA_EXPECTED register field value. */ +#define ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SDMMC_CMD_DATA_EXPECTED register field value. */ +#define ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */ +#define ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_DATA_EXPECTED field value from a register. */ +#define ALT_SDMMC_CMD_DATA_EXPECTED_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SDMMC_CMD_DATA_EXPECTED register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_DATA_EXPECTED_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Read Write - read_write + * + * Read/Write from card. Don't care if no data transfer expected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:--------------- + * ALT_SDMMC_CMD_RD_WR_E_RD | 0x0 | Read from card + * ALT_SDMMC_CMD_RD_WR_E_WR | 0x1 | Write to card + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_RD_WR + * + * Read from card + */ +#define ALT_SDMMC_CMD_RD_WR_E_RD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_RD_WR + * + * Write to card + */ +#define ALT_SDMMC_CMD_RD_WR_E_WR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RD_WR register field. */ +#define ALT_SDMMC_CMD_RD_WR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RD_WR register field. */ +#define ALT_SDMMC_CMD_RD_WR_MSB 10 +/* The width in bits of the ALT_SDMMC_CMD_RD_WR register field. */ +#define ALT_SDMMC_CMD_RD_WR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_RD_WR register field value. */ +#define ALT_SDMMC_CMD_RD_WR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SDMMC_CMD_RD_WR register field value. */ +#define ALT_SDMMC_CMD_RD_WR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SDMMC_CMD_RD_WR register field. */ +#define ALT_SDMMC_CMD_RD_WR_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_RD_WR field value from a register. */ +#define ALT_SDMMC_CMD_RD_WR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SDMMC_CMD_RD_WR register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_RD_WR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Transfer Mode - transfer_mode + * + * Block transfer command. Don't care if no data expected + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------------- + * ALT_SDMMC_CMD_TFR_MOD_E_BLK | 0x0 | Block data transfer command + * ALT_SDMMC_CMD_TFR_MOD_E_STR | 0x1 | Stream data transfer command + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_TFR_MOD + * + * Block data transfer command + */ +#define ALT_SDMMC_CMD_TFR_MOD_E_BLK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_TFR_MOD + * + * Stream data transfer command + */ +#define ALT_SDMMC_CMD_TFR_MOD_E_STR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_TFR_MOD register field. */ +#define ALT_SDMMC_CMD_TFR_MOD_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_TFR_MOD register field. */ +#define ALT_SDMMC_CMD_TFR_MOD_MSB 11 +/* The width in bits of the ALT_SDMMC_CMD_TFR_MOD register field. */ +#define ALT_SDMMC_CMD_TFR_MOD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_TFR_MOD register field value. */ +#define ALT_SDMMC_CMD_TFR_MOD_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SDMMC_CMD_TFR_MOD register field value. */ +#define ALT_SDMMC_CMD_TFR_MOD_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SDMMC_CMD_TFR_MOD register field. */ +#define ALT_SDMMC_CMD_TFR_MOD_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_TFR_MOD field value from a register. */ +#define ALT_SDMMC_CMD_TFR_MOD_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SDMMC_CMD_TFR_MOD register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_TFR_MOD_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Send Auto Stop - send_auto_stop + * + * When set, SD/MMC sends stop command to SD_MMC_CEATA cards at end of data + * transfer. Determine the following: + * + * * -when send_auto_stop bit should be set, since some data transfers do not + * need explicit stop commands. *-open-ended transfers that software should + * explicitly send to stop command. + * + * Additionally, when resume is sent to resume- suspended memory access of SD-Combo + * card, bit should be set correctly if suspended data transfer needs + * send_auto_stop. Don't care if no data expected from card. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:--------------------------------------------- + * ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND | 0x0 | No stop command sent at end of data transfer + * ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND | 0x1 | Send stop command at end of data transfer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_SEND_AUTO_STOP + * + * No stop command sent at end of data transfer + */ +#define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_SEND_AUTO_STOP + * + * Send stop command at end of data transfer + */ +#define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */ +#define ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */ +#define ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12 +/* The width in bits of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */ +#define ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_SEND_AUTO_STOP register field value. */ +#define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SDMMC_CMD_SEND_AUTO_STOP register field value. */ +#define ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff +/* The reset value of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */ +#define ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_SEND_AUTO_STOP field value from a register. */ +#define ALT_SDMMC_CMD_SEND_AUTO_STOP_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SDMMC_CMD_SEND_AUTO_STOP register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Wait Previous Data Complete - wait_prvdata_complete + * + * Determines when command is sent. The send command at once option is typically + * used to query status of card during data transfer or to stop current data + * transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT | 0x0 | Send command at once + * ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT | 0x1 | Wait for previous data transfer completion + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE + * + * Send command at once + */ +#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE + * + * Wait for previous data transfer completion + */ +#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */ +#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */ +#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13 +/* The width in bits of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */ +#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value. */ +#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value. */ +#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */ +#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE field value from a register. */ +#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Stop Abort Cmd - stop_abort_cmd + * + * When open-ended or predefined data transfer is in progress, and host issues stop + * or abort command to stop data transfer, bit should be set so that command/data + * state-machines of CIU can return correctly to idle state. This is also + * applicable for Boot mode transfers. To Abort boot mode, this bit should be set + * along with CMD[26] = disable_boot. + * + * Note: If abort is sent to function-number currently selected or not in data- + * transfer mode, then bit should be set to 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT | 0x0 | Don't stop or abort command to stop current data + * : | | transfer in progress + * ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT | 0x1 | Stop or Abort command, intended to stop current + * : | | data transfer in progress + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_STOP_ABT_CMD + * + * Don't stop or abort command to stop current data transfer in progress + */ +#define ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_STOP_ABT_CMD + * + * Stop or Abort command, intended to stop current data transfer in progress + */ +#define ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */ +#define ALT_SDMMC_CMD_STOP_ABT_CMD_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */ +#define ALT_SDMMC_CMD_STOP_ABT_CMD_MSB 14 +/* The width in bits of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */ +#define ALT_SDMMC_CMD_STOP_ABT_CMD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_STOP_ABT_CMD register field value. */ +#define ALT_SDMMC_CMD_STOP_ABT_CMD_SET_MSK 0x00004000 +/* The mask used to clear the ALT_SDMMC_CMD_STOP_ABT_CMD register field value. */ +#define ALT_SDMMC_CMD_STOP_ABT_CMD_CLR_MSK 0xffffbfff +/* The reset value of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */ +#define ALT_SDMMC_CMD_STOP_ABT_CMD_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_STOP_ABT_CMD field value from a register. */ +#define ALT_SDMMC_CMD_STOP_ABT_CMD_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_SDMMC_CMD_STOP_ABT_CMD register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_STOP_ABT_CMD_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Send Initialization - send_initialization + * + * After power on, 80 clocks must be sent to the card for initialization before + * sending any commands to card. Bit should be set while sending first command to + * card so that controller will initialize clocks before sending command to card. + * This bit should not be set for either of the boot modes (alternate or + * mandatory). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------- + * ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT | 0x0 | Do not send initialization sequence (80 clocks + * : | | of 1) before sending this command + * ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT | 0x1 | Send initialization sequence before sending this + * : | | command + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_SEND_INITIALIZATION + * + * Do not send initialization sequence (80 clocks of 1) before sending this command + */ +#define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_SEND_INITIALIZATION + * + * Send initialization sequence before sending this command + */ +#define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */ +#define ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */ +#define ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15 +/* The width in bits of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */ +#define ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_SEND_INITIALIZATION register field value. */ +#define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000 +/* The mask used to clear the ALT_SDMMC_CMD_SEND_INITIALIZATION register field value. */ +#define ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff +/* The reset value of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */ +#define ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_SEND_INITIALIZATION field value from a register. */ +#define ALT_SDMMC_CMD_SEND_INITIALIZATION_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_SDMMC_CMD_SEND_INITIALIZATION register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Card Number - card_number + * + * Card number in use must always be 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CARD_NUMBER register field. */ +#define ALT_SDMMC_CMD_CARD_NUMBER_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CARD_NUMBER register field. */ +#define ALT_SDMMC_CMD_CARD_NUMBER_MSB 20 +/* The width in bits of the ALT_SDMMC_CMD_CARD_NUMBER register field. */ +#define ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5 +/* The mask used to set the ALT_SDMMC_CMD_CARD_NUMBER register field value. */ +#define ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000 +/* The mask used to clear the ALT_SDMMC_CMD_CARD_NUMBER register field value. */ +#define ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff +/* The reset value of the ALT_SDMMC_CMD_CARD_NUMBER register field. */ +#define ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_CARD_NUMBER field value from a register. */ +#define ALT_SDMMC_CMD_CARD_NUMBER_GET(value) (((value) & 0x001f0000) >> 16) +/* Produces a ALT_SDMMC_CMD_CARD_NUMBER register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_CARD_NUMBER_SET(value) (((value) << 16) & 0x001f0000) + +/* + * Field : Update Clock Registers Only - update_clock_registers_only + * + * Following register values transferred into card clock domain: CLKDIV, CLRSRC, + * CLKENA. + * + * Changes card clocks (change frequency, truncate off or on, and set low-frequency + * mode); provided in order to change clock frequency or stop clock without having + * to send command to cards. During normal command sequence, when + * update_clock_registers_only = 0, following control registers are transferred + * from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new + * register values for new command sequence to card(s). When bit is set, there are + * no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:------------------------------------------------- + * ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD | 0x0 | Normal command sequence + * ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG | 0x1 | Do not send commands, just update clock register + * : | | value into card clock domain + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY + * + * Normal command sequence + */ +#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY + * + * Do not send commands, just update clock register value into card clock domain + */ +#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */ +#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */ +#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_MSB 21 +/* The width in bits of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */ +#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value. */ +#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET_MSK 0x00200000 +/* The mask used to clear the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value. */ +#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_CLR_MSK 0xffdfffff +/* The reset value of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */ +#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY field value from a register. */ +#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Read CE-ATA Device - read_ceata_device + * + * Software should set this bit to indicate that CE-ATA device is being accessed + * for read transfer. This bit is used to disable read data timeout indication + * while performing CE-ATA read transfers. Maximum value of I/O transmission delay + * can be no less than 10 seconds. SD/MMC should not indicate read data timeout + * while waiting for data from CE-ATA device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD | 0x0 | Host is not performing read access (RW_REG or + * : | | RW_BLK) towards CE-ATA device + * ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD | 0x1 | Host is performing read access (RW_REG or + * : | | RW_BLK) towards CE-ATA device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_RD_CEATA_DEVICE + * + * Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device + */ +#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_RD_CEATA_DEVICE + * + * Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device + */ +#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */ +#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */ +#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_MSB 22 +/* The width in bits of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */ +#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value. */ +#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET_MSK 0x00400000 +/* The mask used to clear the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value. */ +#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_CLR_MSK 0xffbfffff +/* The reset value of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */ +#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_RD_CEATA_DEVICE field value from a register. */ +#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : Command Completion Signal Expected - ccs_expected + * + * If the command expects Command Completion Signal (CCS) from the CE-ATA device, + * the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) + * bit in RINTSTS register and generates interrupt to host if Data Transfer Over + * interrupt is not masked. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------ + * ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD | 0x0 | Interrupts are not enabled in CE-ATA device + * : | | (nIEN = 1 in ATA control register), or command + * : | | does not expect CCS from device + * ALT_SDMMC_CMD_CCS_EXPECTED_E_END | 0x1 | Interrupts are enabled in CE-ATA device (nIEN = + * : | | 0), and RW_BLK command expects command + * : | | completion signal from CE-ATA device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_CCS_EXPECTED + * + * Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), + * or command does not expect CCS from device + */ +#define ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_CCS_EXPECTED + * + * Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects + * command completion signal from CE-ATA device + */ +#define ALT_SDMMC_CMD_CCS_EXPECTED_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */ +#define ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */ +#define ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23 +/* The width in bits of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */ +#define ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_CCS_EXPECTED register field value. */ +#define ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000 +/* The mask used to clear the ALT_SDMMC_CMD_CCS_EXPECTED register field value. */ +#define ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff +/* The reset value of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */ +#define ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_CCS_EXPECTED field value from a register. */ +#define ALT_SDMMC_CMD_CCS_EXPECTED_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_SDMMC_CMD_CCS_EXPECTED register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_CCS_EXPECTED_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Enable Boot - enable_boot + * + * This bit should be set only for mandatory boot mode. When Software sets this bit + * along with start_cmd, CIU starts the boot sequence for the corresponding card by + * asserting the CMD line low. Do NOT set disable_boot and enable_boot together + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------- + * ALT_SDMMC_CMD_EN_BOOT_E_DISD | 0x0 | Disable Boot + * ALT_SDMMC_CMD_EN_BOOT_E_END | 0x1 | Enable Boot + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_EN_BOOT + * + * Disable Boot + */ +#define ALT_SDMMC_CMD_EN_BOOT_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_EN_BOOT + * + * Enable Boot + */ +#define ALT_SDMMC_CMD_EN_BOOT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_EN_BOOT register field. */ +#define ALT_SDMMC_CMD_EN_BOOT_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_EN_BOOT register field. */ +#define ALT_SDMMC_CMD_EN_BOOT_MSB 24 +/* The width in bits of the ALT_SDMMC_CMD_EN_BOOT register field. */ +#define ALT_SDMMC_CMD_EN_BOOT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_EN_BOOT register field value. */ +#define ALT_SDMMC_CMD_EN_BOOT_SET_MSK 0x01000000 +/* The mask used to clear the ALT_SDMMC_CMD_EN_BOOT register field value. */ +#define ALT_SDMMC_CMD_EN_BOOT_CLR_MSK 0xfeffffff +/* The reset value of the ALT_SDMMC_CMD_EN_BOOT register field. */ +#define ALT_SDMMC_CMD_EN_BOOT_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_EN_BOOT field value from a register. */ +#define ALT_SDMMC_CMD_EN_BOOT_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_SDMMC_CMD_EN_BOOT register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_EN_BOOT_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Expect Boot Ack - expect_boot_ack + * + * When Software sets this bit along with enable_boot, CIU expects a boot + * acknowledge start pattern of 0-1-0 from the selected card. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------- + * ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK | 0x0 | No Boot ACK + * ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK | 0x1 | Expect Boot ACK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_EXPECT_BOOT_ACK + * + * No Boot ACK + */ +#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_EXPECT_BOOT_ACK + * + * Expect Boot ACK + */ +#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */ +#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */ +#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25 +/* The width in bits of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */ +#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value. */ +#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000 +/* The mask used to clear the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value. */ +#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff +/* The reset value of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */ +#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_EXPECT_BOOT_ACK field value from a register. */ +#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Disable Boot - disable_boot + * + * When software sets this bit along with start_cmd, CIU terminates the boot + * operation. Do NOT set disable_boot and enable_boot together. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT | 0x0 | Boot not Terminated + * ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT | 0x1 | Terminate Boot + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_DIS_BOOT + * + * Boot not Terminated + */ +#define ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_DIS_BOOT + * + * Terminate Boot + */ +#define ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_DIS_BOOT register field. */ +#define ALT_SDMMC_CMD_DIS_BOOT_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_DIS_BOOT register field. */ +#define ALT_SDMMC_CMD_DIS_BOOT_MSB 26 +/* The width in bits of the ALT_SDMMC_CMD_DIS_BOOT register field. */ +#define ALT_SDMMC_CMD_DIS_BOOT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_DIS_BOOT register field value. */ +#define ALT_SDMMC_CMD_DIS_BOOT_SET_MSK 0x04000000 +/* The mask used to clear the ALT_SDMMC_CMD_DIS_BOOT register field value. */ +#define ALT_SDMMC_CMD_DIS_BOOT_CLR_MSK 0xfbffffff +/* The reset value of the ALT_SDMMC_CMD_DIS_BOOT register field. */ +#define ALT_SDMMC_CMD_DIS_BOOT_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_DIS_BOOT field value from a register. */ +#define ALT_SDMMC_CMD_DIS_BOOT_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_SDMMC_CMD_DIS_BOOT register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_DIS_BOOT_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Boot Mode - boot_mode + * + * Type of Boot Mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY | 0x0 | Mandatory Boot Operation + * ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE | 0x1 | Alternate Boot Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_BOOT_MOD + * + * Mandatory Boot Operation + */ +#define ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_BOOT_MOD + * + * Alternate Boot Operation + */ +#define ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_BOOT_MOD register field. */ +#define ALT_SDMMC_CMD_BOOT_MOD_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_BOOT_MOD register field. */ +#define ALT_SDMMC_CMD_BOOT_MOD_MSB 27 +/* The width in bits of the ALT_SDMMC_CMD_BOOT_MOD register field. */ +#define ALT_SDMMC_CMD_BOOT_MOD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_BOOT_MOD register field value. */ +#define ALT_SDMMC_CMD_BOOT_MOD_SET_MSK 0x08000000 +/* The mask used to clear the ALT_SDMMC_CMD_BOOT_MOD register field value. */ +#define ALT_SDMMC_CMD_BOOT_MOD_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_SDMMC_CMD_BOOT_MOD register field. */ +#define ALT_SDMMC_CMD_BOOT_MOD_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_BOOT_MOD field value from a register. */ +#define ALT_SDMMC_CMD_BOOT_MOD_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_SDMMC_CMD_BOOT_MOD register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_BOOT_MOD_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Volt Switch - volt_switch + * + * Voltage switch bit. When set must be set for CMD11 only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------- + * ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW | 0x0 | No voltage switching - default + * ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW | 0x1 | Voltage switching enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_VOLT_SWITCH + * + * No voltage switching - default + */ +#define ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_VOLT_SWITCH + * + * Voltage switching enabled + */ +#define ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */ +#define ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */ +#define ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28 +/* The width in bits of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */ +#define ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_VOLT_SWITCH register field value. */ +#define ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000 +/* The mask used to clear the ALT_SDMMC_CMD_VOLT_SWITCH register field value. */ +#define ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff +/* The reset value of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */ +#define ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_VOLT_SWITCH field value from a register. */ +#define ALT_SDMMC_CMD_VOLT_SWITCH_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_SDMMC_CMD_VOLT_SWITCH register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_VOLT_SWITCH_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Use Hold Reg - use_hold_reg + * + * Set to one for SDR12 and SDR25 (with non-zero phase-shifted cclk_in_drv); zero + * phase shift is not allowed in these modes. + * + * * Set to 1'b0 for SDR50, SDR104, and DDR50 (with zero phase-shifted + * cclk_in_drv). + * + * * Set to 1'b1 for SDR50, SDR104, and DDR50 (with non-zero phase-shifted + * cclk_in_drv). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------- + * ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS | 0x0 | CMD and DATA sent to card bypassing HOLD + * : | | Register + * ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS | 0x1 | CMD and DATA sent to card through the HOLD + * : | | Register + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_USE_HOLD_REG + * + * CMD and DATA sent to card bypassing HOLD Register + */ +#define ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_USE_HOLD_REG + * + * CMD and DATA sent to card through the HOLD Register + */ +#define ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */ +#define ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */ +#define ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29 +/* The width in bits of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */ +#define ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_USE_HOLD_REG register field value. */ +#define ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000 +/* The mask used to clear the ALT_SDMMC_CMD_USE_HOLD_REG register field value. */ +#define ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff +/* The reset value of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */ +#define ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1 +/* Extracts the ALT_SDMMC_CMD_USE_HOLD_REG field value from a register. */ +#define ALT_SDMMC_CMD_USE_HOLD_REG_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_SDMMC_CMD_USE_HOLD_REG register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_USE_HOLD_REG_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Start Cmd - start_cmd + * + * Once command is taken by CIU, bit is cleared. If Start Cmd issued host should + * not attempt to write to any command registers. If write is attempted, hardware + * lock error is set in raw interrupt register. Once command is sent and response + * is received from SD_MMC_CEATA cards, Command Done bit is set in raw interrupt + * register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------- + * ALT_SDMMC_CMD_START_CMD_E_NOSTART | 0x0 | No Start Cmd + * ALT_SDMMC_CMD_START_CMD_E_START | 0x1 | Start Cmd Issued + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CMD_START_CMD + * + * No Start Cmd + */ +#define ALT_SDMMC_CMD_START_CMD_E_NOSTART 0x0 +/* + * Enumerated value for register field ALT_SDMMC_CMD_START_CMD + * + * Start Cmd Issued + */ +#define ALT_SDMMC_CMD_START_CMD_E_START 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_START_CMD register field. */ +#define ALT_SDMMC_CMD_START_CMD_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_START_CMD register field. */ +#define ALT_SDMMC_CMD_START_CMD_MSB 31 +/* The width in bits of the ALT_SDMMC_CMD_START_CMD register field. */ +#define ALT_SDMMC_CMD_START_CMD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CMD_START_CMD register field value. */ +#define ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000 +/* The mask used to clear the ALT_SDMMC_CMD_START_CMD register field value. */ +#define ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff +/* The reset value of the ALT_SDMMC_CMD_START_CMD register field. */ +#define ALT_SDMMC_CMD_START_CMD_RESET 0x0 +/* Extracts the ALT_SDMMC_CMD_START_CMD field value from a register. */ +#define ALT_SDMMC_CMD_START_CMD_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_SDMMC_CMD_START_CMD register field value suitable for setting the register. */ +#define ALT_SDMMC_CMD_START_CMD_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_CMD. + */ +struct ALT_SDMMC_CMD_s +{ + uint32_t cmd_index : 6; /* Cmd Index */ + uint32_t response_expect : 1; /* Response Expect */ + uint32_t response_length : 1; /* Response Length */ + uint32_t check_response_crc : 1; /* Check Response Crc */ + uint32_t data_expected : 1; /* Data Transfer Expected */ + uint32_t read_write : 1; /* Read Write */ + uint32_t transfer_mode : 1; /* Transfer Mode */ + uint32_t send_auto_stop : 1; /* Send Auto Stop */ + uint32_t wait_prvdata_complete : 1; /* Wait Previous Data Complete */ + uint32_t stop_abort_cmd : 1; /* Stop Abort Cmd */ + uint32_t send_initialization : 1; /* Send Initialization */ + uint32_t card_number : 5; /* Card Number */ + uint32_t update_clock_registers_only : 1; /* Update Clock Registers Only */ + uint32_t read_ceata_device : 1; /* Read CE-ATA Device */ + uint32_t ccs_expected : 1; /* Command Completion Signal Expected */ + uint32_t enable_boot : 1; /* Enable Boot */ + uint32_t expect_boot_ack : 1; /* Expect Boot Ack */ + uint32_t disable_boot : 1; /* Disable Boot */ + uint32_t boot_mode : 1; /* Boot Mode */ + uint32_t volt_switch : 1; /* Volt Switch */ + uint32_t use_hold_reg : 1; /* Use Hold Reg */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t start_cmd : 1; /* Start Cmd */ +}; + +/* The typedef declaration for register ALT_SDMMC_CMD. */ +typedef volatile struct ALT_SDMMC_CMD_s ALT_SDMMC_CMD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_CMD register from the beginning of the component. */ +#define ALT_SDMMC_CMD_OFST 0x2c + +/* + * Register : Response Register 0 - resp0 + * + * Preserves previous command. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | Response 0 + * + */ +/* + * Field : Response 0 - response0 + * + * Bit[31:0] of response. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP0_RESPONSE0 register field. */ +#define ALT_SDMMC_RESP0_RESPONSE0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP0_RESPONSE0 register field. */ +#define ALT_SDMMC_RESP0_RESPONSE0_MSB 31 +/* The width in bits of the ALT_SDMMC_RESP0_RESPONSE0 register field. */ +#define ALT_SDMMC_RESP0_RESPONSE0_WIDTH 32 +/* The mask used to set the ALT_SDMMC_RESP0_RESPONSE0 register field value. */ +#define ALT_SDMMC_RESP0_RESPONSE0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_RESP0_RESPONSE0 register field value. */ +#define ALT_SDMMC_RESP0_RESPONSE0_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_RESP0_RESPONSE0 register field. */ +#define ALT_SDMMC_RESP0_RESPONSE0_RESET 0x0 +/* Extracts the ALT_SDMMC_RESP0_RESPONSE0 field value from a register. */ +#define ALT_SDMMC_RESP0_RESPONSE0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_RESP0_RESPONSE0 register field value suitable for setting the register. */ +#define ALT_SDMMC_RESP0_RESPONSE0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_RESP0. + */ +struct ALT_SDMMC_RESP0_s +{ + const uint32_t response0 : 32; /* Response 0 */ +}; + +/* The typedef declaration for register ALT_SDMMC_RESP0. */ +typedef volatile struct ALT_SDMMC_RESP0_s ALT_SDMMC_RESP0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_RESP0 register from the beginning of the component. */ +#define ALT_SDMMC_RESP0_OFST 0x30 + +/* + * Register : Response Register 1 - resp1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | Response 1 + * + */ +/* + * Field : Response 1 - response1 + * + * Register represents bit[63:32] of long response. When CIU sends auto-stop + * command, then response is saved in register. Response for previous command sent + * by host is still preserved in Response 0 register. Additional auto-stop issued + * only for data transfer commands, and response type is always short for them. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP1_RESPONSE1 register field. */ +#define ALT_SDMMC_RESP1_RESPONSE1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP1_RESPONSE1 register field. */ +#define ALT_SDMMC_RESP1_RESPONSE1_MSB 31 +/* The width in bits of the ALT_SDMMC_RESP1_RESPONSE1 register field. */ +#define ALT_SDMMC_RESP1_RESPONSE1_WIDTH 32 +/* The mask used to set the ALT_SDMMC_RESP1_RESPONSE1 register field value. */ +#define ALT_SDMMC_RESP1_RESPONSE1_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_RESP1_RESPONSE1 register field value. */ +#define ALT_SDMMC_RESP1_RESPONSE1_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_RESP1_RESPONSE1 register field. */ +#define ALT_SDMMC_RESP1_RESPONSE1_RESET 0x0 +/* Extracts the ALT_SDMMC_RESP1_RESPONSE1 field value from a register. */ +#define ALT_SDMMC_RESP1_RESPONSE1_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_RESP1_RESPONSE1 register field value suitable for setting the register. */ +#define ALT_SDMMC_RESP1_RESPONSE1_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_RESP1. + */ +struct ALT_SDMMC_RESP1_s +{ + const uint32_t response1 : 32; /* Response 1 */ +}; + +/* The typedef declaration for register ALT_SDMMC_RESP1. */ +typedef volatile struct ALT_SDMMC_RESP1_s ALT_SDMMC_RESP1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_RESP1 register from the beginning of the component. */ +#define ALT_SDMMC_RESP1_OFST 0x34 + +/* + * Register : Response Register 2 - resp2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | Response 2 + * + */ +/* + * Field : Response 2 - response2 + * + * Bit[95:64] of long response + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP2_RESPONSE2 register field. */ +#define ALT_SDMMC_RESP2_RESPONSE2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP2_RESPONSE2 register field. */ +#define ALT_SDMMC_RESP2_RESPONSE2_MSB 31 +/* The width in bits of the ALT_SDMMC_RESP2_RESPONSE2 register field. */ +#define ALT_SDMMC_RESP2_RESPONSE2_WIDTH 32 +/* The mask used to set the ALT_SDMMC_RESP2_RESPONSE2 register field value. */ +#define ALT_SDMMC_RESP2_RESPONSE2_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_RESP2_RESPONSE2 register field value. */ +#define ALT_SDMMC_RESP2_RESPONSE2_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_RESP2_RESPONSE2 register field. */ +#define ALT_SDMMC_RESP2_RESPONSE2_RESET 0x0 +/* Extracts the ALT_SDMMC_RESP2_RESPONSE2 field value from a register. */ +#define ALT_SDMMC_RESP2_RESPONSE2_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_RESP2_RESPONSE2 register field value suitable for setting the register. */ +#define ALT_SDMMC_RESP2_RESPONSE2_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_RESP2. + */ +struct ALT_SDMMC_RESP2_s +{ + const uint32_t response2 : 32; /* Response 2 */ +}; + +/* The typedef declaration for register ALT_SDMMC_RESP2. */ +typedef volatile struct ALT_SDMMC_RESP2_s ALT_SDMMC_RESP2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_RESP2 register from the beginning of the component. */ +#define ALT_SDMMC_RESP2_OFST 0x38 + +/* + * Register : Response Register 3 - resp3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | Response 3 + * + */ +/* + * Field : Response 3 - response3 + * + * Bit[127:96] of long response + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP3_RESPONSE3 register field. */ +#define ALT_SDMMC_RESP3_RESPONSE3_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP3_RESPONSE3 register field. */ +#define ALT_SDMMC_RESP3_RESPONSE3_MSB 31 +/* The width in bits of the ALT_SDMMC_RESP3_RESPONSE3 register field. */ +#define ALT_SDMMC_RESP3_RESPONSE3_WIDTH 32 +/* The mask used to set the ALT_SDMMC_RESP3_RESPONSE3 register field value. */ +#define ALT_SDMMC_RESP3_RESPONSE3_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_RESP3_RESPONSE3 register field value. */ +#define ALT_SDMMC_RESP3_RESPONSE3_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_RESP3_RESPONSE3 register field. */ +#define ALT_SDMMC_RESP3_RESPONSE3_RESET 0x0 +/* Extracts the ALT_SDMMC_RESP3_RESPONSE3 field value from a register. */ +#define ALT_SDMMC_RESP3_RESPONSE3_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_RESP3_RESPONSE3 register field value suitable for setting the register. */ +#define ALT_SDMMC_RESP3_RESPONSE3_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_RESP3. + */ +struct ALT_SDMMC_RESP3_s +{ + const uint32_t response3 : 32; /* Response 3 */ +}; + +/* The typedef declaration for register ALT_SDMMC_RESP3. */ +typedef volatile struct ALT_SDMMC_RESP3_s ALT_SDMMC_RESP3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_RESP3 register from the beginning of the component. */ +#define ALT_SDMMC_RESP3_OFST 0x3c + +/* + * Register : Masked Interrupt Status Register - mintsts + * + * Describes state of Masked Interrupt Register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [0] | R | 0x0 | Card Detect + * [1] | R | 0x0 | Response Error + * [2] | R | 0x0 | Command Done + * [3] | R | 0x0 | Data Transfer Over + * [4] | R | 0x0 | Data TX FIFO Data Request + * [5] | R | 0x0 | Receive FIFO Data Request + * [6] | R | 0x0 | Response CRC Error + * [7] | R | 0x0 | Data CRC Error + * [8] | R | 0x0 | Response Timeout + * [9] | R | 0x0 | Data Read Timeout + * [10] | R | 0x0 | Data Starvation Host Timeout + * [11] | R | 0x0 | FIFO Underrun Overrun Error + * [12] | R | 0x0 | Hardware Locked Write Error + * [13] | R | 0x0 | Start-bit Error + * [14] | R | 0x0 | Auto Command Done + * [15] | R | 0x0 | End-bit Error + * [16] | R | 0x0 | SDIO Interrupts + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Card Detect - cd + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------- + * ALT_SDMMC_MINTSTS_CD_E_MSK | 0x0 | Card Detected Mask + * ALT_SDMMC_MINTSTS_CD_E_NOMSK | 0x1 | Card Detected No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_CD + * + * Card Detected Mask + */ +#define ALT_SDMMC_MINTSTS_CD_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_CD + * + * Card Detected No Mask + */ +#define ALT_SDMMC_MINTSTS_CD_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_CD register field. */ +#define ALT_SDMMC_MINTSTS_CD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_CD register field. */ +#define ALT_SDMMC_MINTSTS_CD_MSB 0 +/* The width in bits of the ALT_SDMMC_MINTSTS_CD register field. */ +#define ALT_SDMMC_MINTSTS_CD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_CD register field value. */ +#define ALT_SDMMC_MINTSTS_CD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_MINTSTS_CD register field value. */ +#define ALT_SDMMC_MINTSTS_CD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_MINTSTS_CD register field. */ +#define ALT_SDMMC_MINTSTS_CD_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_CD field value from a register. */ +#define ALT_SDMMC_MINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_MINTSTS_CD register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_CD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Response Error - resp + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------- + * ALT_SDMMC_MINTSTS_RESP_E_MSK | 0x0 | Response error Mask + * ALT_SDMMC_MINTSTS_RESP_E_NOMSK | 0x1 | Response error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_RESP + * + * Response error Mask + */ +#define ALT_SDMMC_MINTSTS_RESP_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_RESP + * + * Response error No Mask + */ +#define ALT_SDMMC_MINTSTS_RESP_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESP register field. */ +#define ALT_SDMMC_MINTSTS_RESP_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESP register field. */ +#define ALT_SDMMC_MINTSTS_RESP_MSB 1 +/* The width in bits of the ALT_SDMMC_MINTSTS_RESP register field. */ +#define ALT_SDMMC_MINTSTS_RESP_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_RESP register field value. */ +#define ALT_SDMMC_MINTSTS_RESP_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDMMC_MINTSTS_RESP register field value. */ +#define ALT_SDMMC_MINTSTS_RESP_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDMMC_MINTSTS_RESP register field. */ +#define ALT_SDMMC_MINTSTS_RESP_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_RESP field value from a register. */ +#define ALT_SDMMC_MINTSTS_RESP_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDMMC_MINTSTS_RESP register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_RESP_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Command Done - cmd_done + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------------- + * ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK | 0x0 | Command Done Mask + * ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK | 0x1 | Command Done No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_CMD_DONE + * + * Command Done Mask + */ +#define ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_CMD_DONE + * + * Command Done No Mask + */ +#define ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */ +#define ALT_SDMMC_MINTSTS_CMD_DONE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */ +#define ALT_SDMMC_MINTSTS_CMD_DONE_MSB 2 +/* The width in bits of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */ +#define ALT_SDMMC_MINTSTS_CMD_DONE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_CMD_DONE register field value. */ +#define ALT_SDMMC_MINTSTS_CMD_DONE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDMMC_MINTSTS_CMD_DONE register field value. */ +#define ALT_SDMMC_MINTSTS_CMD_DONE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */ +#define ALT_SDMMC_MINTSTS_CMD_DONE_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_CMD_DONE field value from a register. */ +#define ALT_SDMMC_MINTSTS_CMD_DONE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDMMC_MINTSTS_CMD_DONE register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_CMD_DONE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Data Transfer Over - dt + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:--------------------------- + * ALT_SDMMC_MINTSTS_DT_E_MSK | 0x0 | Data transfer over Mask + * ALT_SDMMC_MINTSTS_DT_E_NOMSK | 0x1 | Data transfer over No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_DT + * + * Data transfer over Mask + */ +#define ALT_SDMMC_MINTSTS_DT_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_DT + * + * Data transfer over No Mask + */ +#define ALT_SDMMC_MINTSTS_DT_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DT register field. */ +#define ALT_SDMMC_MINTSTS_DT_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DT register field. */ +#define ALT_SDMMC_MINTSTS_DT_MSB 3 +/* The width in bits of the ALT_SDMMC_MINTSTS_DT register field. */ +#define ALT_SDMMC_MINTSTS_DT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_DT register field value. */ +#define ALT_SDMMC_MINTSTS_DT_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDMMC_MINTSTS_DT register field value. */ +#define ALT_SDMMC_MINTSTS_DT_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDMMC_MINTSTS_DT register field. */ +#define ALT_SDMMC_MINTSTS_DT_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_DT field value from a register. */ +#define ALT_SDMMC_MINTSTS_DT_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDMMC_MINTSTS_DT register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_DT_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Data TX FIFO Data Request - dttxfifodr + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------------- + * ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK | 0x0 | Transmit FIFO data request Mask + * ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK | 0x1 | Transmit FIFO data request No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_DTTXFIFODR + * + * Transmit FIFO data request Mask + */ +#define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_DTTXFIFODR + * + * Transmit FIFO data request No Mask + */ +#define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */ +#define ALT_SDMMC_MINTSTS_DTTXFIFODR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */ +#define ALT_SDMMC_MINTSTS_DTTXFIFODR_MSB 4 +/* The width in bits of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */ +#define ALT_SDMMC_MINTSTS_DTTXFIFODR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_DTTXFIFODR register field value. */ +#define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDMMC_MINTSTS_DTTXFIFODR register field value. */ +#define ALT_SDMMC_MINTSTS_DTTXFIFODR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */ +#define ALT_SDMMC_MINTSTS_DTTXFIFODR_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_DTTXFIFODR field value from a register. */ +#define ALT_SDMMC_MINTSTS_DTTXFIFODR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDMMC_MINTSTS_DTTXFIFODR register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Receive FIFO Data Request - rxfifodr + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------------- + * ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK | 0x0 | Receive FIFO data request Mask + * ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK | 0x1 | Receive FIFO data request No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_RXFIFODR + * + * Receive FIFO data request Mask + */ +#define ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_RXFIFODR + * + * Receive FIFO data request No Mask + */ +#define ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */ +#define ALT_SDMMC_MINTSTS_RXFIFODR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */ +#define ALT_SDMMC_MINTSTS_RXFIFODR_MSB 5 +/* The width in bits of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */ +#define ALT_SDMMC_MINTSTS_RXFIFODR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_RXFIFODR register field value. */ +#define ALT_SDMMC_MINTSTS_RXFIFODR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SDMMC_MINTSTS_RXFIFODR register field value. */ +#define ALT_SDMMC_MINTSTS_RXFIFODR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */ +#define ALT_SDMMC_MINTSTS_RXFIFODR_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_RXFIFODR field value from a register. */ +#define ALT_SDMMC_MINTSTS_RXFIFODR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SDMMC_MINTSTS_RXFIFODR register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_RXFIFODR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Response CRC Error - respcrcerr + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------- + * ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK | 0x0 | Response CRC error Mask + * ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK | 0x1 | Response CRC error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPCRCERR + * + * Response CRC error Mask + */ +#define ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPCRCERR + * + * Response CRC error No Mask + */ +#define ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */ +#define ALT_SDMMC_MINTSTS_RESPCRCERR_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */ +#define ALT_SDMMC_MINTSTS_RESPCRCERR_MSB 6 +/* The width in bits of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */ +#define ALT_SDMMC_MINTSTS_RESPCRCERR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_RESPCRCERR register field value. */ +#define ALT_SDMMC_MINTSTS_RESPCRCERR_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SDMMC_MINTSTS_RESPCRCERR register field value. */ +#define ALT_SDMMC_MINTSTS_RESPCRCERR_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */ +#define ALT_SDMMC_MINTSTS_RESPCRCERR_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_RESPCRCERR field value from a register. */ +#define ALT_SDMMC_MINTSTS_RESPCRCERR_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SDMMC_MINTSTS_RESPCRCERR register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_RESPCRCERR_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Data CRC Error - datacrcerr + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK | 0x0 | Data CRC error Mask + * ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK | 0x1 | Data CRC error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_DATACRCERR + * + * Data CRC error Mask + */ +#define ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_DATACRCERR + * + * Data CRC error No Mask + */ +#define ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */ +#define ALT_SDMMC_MINTSTS_DATACRCERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */ +#define ALT_SDMMC_MINTSTS_DATACRCERR_MSB 7 +/* The width in bits of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */ +#define ALT_SDMMC_MINTSTS_DATACRCERR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_DATACRCERR register field value. */ +#define ALT_SDMMC_MINTSTS_DATACRCERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SDMMC_MINTSTS_DATACRCERR register field value. */ +#define ALT_SDMMC_MINTSTS_DATACRCERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */ +#define ALT_SDMMC_MINTSTS_DATACRCERR_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_DATACRCERR field value from a register. */ +#define ALT_SDMMC_MINTSTS_DATACRCERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SDMMC_MINTSTS_DATACRCERR register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_DATACRCERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Response Timeout - respto + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------- + * ALT_SDMMC_MINTSTS_RESPTO_E_MSK | 0x0 | Response timeout Mask + * ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK | 0x1 | Response timeout No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPTO + * + * Response timeout Mask + */ +#define ALT_SDMMC_MINTSTS_RESPTO_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPTO + * + * Response timeout No Mask + */ +#define ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPTO register field. */ +#define ALT_SDMMC_MINTSTS_RESPTO_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPTO register field. */ +#define ALT_SDMMC_MINTSTS_RESPTO_MSB 8 +/* The width in bits of the ALT_SDMMC_MINTSTS_RESPTO register field. */ +#define ALT_SDMMC_MINTSTS_RESPTO_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_RESPTO register field value. */ +#define ALT_SDMMC_MINTSTS_RESPTO_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SDMMC_MINTSTS_RESPTO register field value. */ +#define ALT_SDMMC_MINTSTS_RESPTO_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SDMMC_MINTSTS_RESPTO register field. */ +#define ALT_SDMMC_MINTSTS_RESPTO_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_RESPTO field value from a register. */ +#define ALT_SDMMC_MINTSTS_RESPTO_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SDMMC_MINTSTS_RESPTO register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_RESPTO_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Data Read Timeout - datardto + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------- + * ALT_SDMMC_MINTSTS_DATARDTO_E_MSK | 0x0 | Data read timeout Mask + * ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK | 0x1 | Data read timeout No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_DATARDTO + * + * Data read timeout Mask + */ +#define ALT_SDMMC_MINTSTS_DATARDTO_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_DATARDTO + * + * Data read timeout No Mask + */ +#define ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATARDTO register field. */ +#define ALT_SDMMC_MINTSTS_DATARDTO_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATARDTO register field. */ +#define ALT_SDMMC_MINTSTS_DATARDTO_MSB 9 +/* The width in bits of the ALT_SDMMC_MINTSTS_DATARDTO register field. */ +#define ALT_SDMMC_MINTSTS_DATARDTO_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_DATARDTO register field value. */ +#define ALT_SDMMC_MINTSTS_DATARDTO_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SDMMC_MINTSTS_DATARDTO register field value. */ +#define ALT_SDMMC_MINTSTS_DATARDTO_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SDMMC_MINTSTS_DATARDTO register field. */ +#define ALT_SDMMC_MINTSTS_DATARDTO_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_DATARDTO field value from a register. */ +#define ALT_SDMMC_MINTSTS_DATARDTO_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SDMMC_MINTSTS_DATARDTO register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_DATARDTO_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Starvation Host Timeout - dshto + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------------------- + * ALT_SDMMC_MINTSTS_DSHTO_E_MSK | 0x0 | Data starvation by host timeout Mask + * ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK | 0x1 | Data starvation by host timeout No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_DSHTO + * + * Data starvation by host timeout Mask + */ +#define ALT_SDMMC_MINTSTS_DSHTO_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_DSHTO + * + * Data starvation by host timeout No Mask + */ +#define ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DSHTO register field. */ +#define ALT_SDMMC_MINTSTS_DSHTO_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DSHTO register field. */ +#define ALT_SDMMC_MINTSTS_DSHTO_MSB 10 +/* The width in bits of the ALT_SDMMC_MINTSTS_DSHTO register field. */ +#define ALT_SDMMC_MINTSTS_DSHTO_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_DSHTO register field value. */ +#define ALT_SDMMC_MINTSTS_DSHTO_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SDMMC_MINTSTS_DSHTO register field value. */ +#define ALT_SDMMC_MINTSTS_DSHTO_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SDMMC_MINTSTS_DSHTO register field. */ +#define ALT_SDMMC_MINTSTS_DSHTO_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_DSHTO field value from a register. */ +#define ALT_SDMMC_MINTSTS_DSHTO_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SDMMC_MINTSTS_DSHTO register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_DSHTO_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : FIFO Underrun Overrun Error - fifoovunerr + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------ + * ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK | 0x0 | FIFO underrun/overrun error Mask + * ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK | 0x1 | FIFO underrun/overrun error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_FIFOOVUNERR + * + * FIFO underrun/overrun error Mask + */ +#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_FIFOOVUNERR + * + * FIFO underrun/overrun error No Mask + */ +#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */ +#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */ +#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_MSB 11 +/* The width in bits of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */ +#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value. */ +#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value. */ +#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */ +#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_FIFOOVUNERR field value from a register. */ +#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Hardware Locked Write Error - hlwerr + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_SDMMC_MINTSTS_HLWERR_E_MSK | 0x0 | Hardware locked write error Mask + * ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK | 0x1 | Hardware locked write error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_HLWERR + * + * Hardware locked write error Mask + */ +#define ALT_SDMMC_MINTSTS_HLWERR_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_HLWERR + * + * Hardware locked write error No Mask + */ +#define ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_HLWERR register field. */ +#define ALT_SDMMC_MINTSTS_HLWERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_HLWERR register field. */ +#define ALT_SDMMC_MINTSTS_HLWERR_MSB 12 +/* The width in bits of the ALT_SDMMC_MINTSTS_HLWERR register field. */ +#define ALT_SDMMC_MINTSTS_HLWERR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_HLWERR register field value. */ +#define ALT_SDMMC_MINTSTS_HLWERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SDMMC_MINTSTS_HLWERR register field value. */ +#define ALT_SDMMC_MINTSTS_HLWERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_SDMMC_MINTSTS_HLWERR register field. */ +#define ALT_SDMMC_MINTSTS_HLWERR_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_HLWERR field value from a register. */ +#define ALT_SDMMC_MINTSTS_HLWERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SDMMC_MINTSTS_HLWERR register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_HLWERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Start-bit Error - strerr + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------ + * ALT_SDMMC_MINTSTS_STRERR_E_MSK | 0x0 | Start-bit error Mask + * ALT_SDMMC_MINTSTS_STRERR_E_NOMSK | 0x1 | Start-bit error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_STRERR + * + * Start-bit error Mask + */ +#define ALT_SDMMC_MINTSTS_STRERR_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_STRERR + * + * Start-bit error No Mask + */ +#define ALT_SDMMC_MINTSTS_STRERR_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_STRERR register field. */ +#define ALT_SDMMC_MINTSTS_STRERR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_STRERR register field. */ +#define ALT_SDMMC_MINTSTS_STRERR_MSB 13 +/* The width in bits of the ALT_SDMMC_MINTSTS_STRERR register field. */ +#define ALT_SDMMC_MINTSTS_STRERR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_STRERR register field value. */ +#define ALT_SDMMC_MINTSTS_STRERR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SDMMC_MINTSTS_STRERR register field value. */ +#define ALT_SDMMC_MINTSTS_STRERR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SDMMC_MINTSTS_STRERR register field. */ +#define ALT_SDMMC_MINTSTS_STRERR_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_STRERR field value from a register. */ +#define ALT_SDMMC_MINTSTS_STRERR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SDMMC_MINTSTS_STRERR register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_STRERR_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Auto Command Done - acd + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:-------------------------- + * ALT_SDMMC_MINTSTS_ACD_E_MSK | 0x0 | Auto command done Mask + * ALT_SDMMC_MINTSTS_ACD_E_NOMSK | 0x1 | Auto command done No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_ACD + * + * Auto command done Mask + */ +#define ALT_SDMMC_MINTSTS_ACD_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_ACD + * + * Auto command done No Mask + */ +#define ALT_SDMMC_MINTSTS_ACD_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_ACD register field. */ +#define ALT_SDMMC_MINTSTS_ACD_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_ACD register field. */ +#define ALT_SDMMC_MINTSTS_ACD_MSB 14 +/* The width in bits of the ALT_SDMMC_MINTSTS_ACD register field. */ +#define ALT_SDMMC_MINTSTS_ACD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_ACD register field value. */ +#define ALT_SDMMC_MINTSTS_ACD_SET_MSK 0x00004000 +/* The mask used to clear the ALT_SDMMC_MINTSTS_ACD register field value. */ +#define ALT_SDMMC_MINTSTS_ACD_CLR_MSK 0xffffbfff +/* The reset value of the ALT_SDMMC_MINTSTS_ACD register field. */ +#define ALT_SDMMC_MINTSTS_ACD_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_ACD field value from a register. */ +#define ALT_SDMMC_MINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_SDMMC_MINTSTS_ACD register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : End-bit Error - ebe + * + * Interrupt enabled only if corresponding bit in interrupt mask register is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------- + * ALT_SDMMC_MINTSTS_EBE_E_MSK | 0x0 | End-bit error Mask + * ALT_SDMMC_MINTSTS_EBE_E_NOMSK | 0x1 | End-bit error No Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_EBE + * + * End-bit error Mask + */ +#define ALT_SDMMC_MINTSTS_EBE_E_MSK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_EBE + * + * End-bit error No Mask + */ +#define ALT_SDMMC_MINTSTS_EBE_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_EBE register field. */ +#define ALT_SDMMC_MINTSTS_EBE_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_EBE register field. */ +#define ALT_SDMMC_MINTSTS_EBE_MSB 15 +/* The width in bits of the ALT_SDMMC_MINTSTS_EBE register field. */ +#define ALT_SDMMC_MINTSTS_EBE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_EBE register field value. */ +#define ALT_SDMMC_MINTSTS_EBE_SET_MSK 0x00008000 +/* The mask used to clear the ALT_SDMMC_MINTSTS_EBE register field value. */ +#define ALT_SDMMC_MINTSTS_EBE_CLR_MSK 0xffff7fff +/* The reset value of the ALT_SDMMC_MINTSTS_EBE register field. */ +#define ALT_SDMMC_MINTSTS_EBE_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_EBE field value from a register. */ +#define ALT_SDMMC_MINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_SDMMC_MINTSTS_EBE register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : SDIO Interrupts - sdio_interrupt + * + * Interrupt from SDIO card: one bit for each card. Bit[16] is for Card[0]. SDIO + * interrupt for card enabled only if corresponding sdio_int_mask bit is set in + * Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt). In + * MMC-Ver3.3-only mode, bits always 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT | 0x1 | SDIO interrupt from card + * ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT | 0x0 | No SDIO interrupt from card + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INT + * + * SDIO interrupt from card + */ +#define ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT 0x1 +/* + * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INT + * + * No SDIO interrupt from card + */ +#define ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */ +#define ALT_SDMMC_MINTSTS_SDIO_INT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */ +#define ALT_SDMMC_MINTSTS_SDIO_INT_MSB 16 +/* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */ +#define ALT_SDMMC_MINTSTS_SDIO_INT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INT register field value. */ +#define ALT_SDMMC_MINTSTS_SDIO_INT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INT register field value. */ +#define ALT_SDMMC_MINTSTS_SDIO_INT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */ +#define ALT_SDMMC_MINTSTS_SDIO_INT_RESET 0x0 +/* Extracts the ALT_SDMMC_MINTSTS_SDIO_INT field value from a register. */ +#define ALT_SDMMC_MINTSTS_SDIO_INT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_SDMMC_MINTSTS_SDIO_INT register field value suitable for setting the register. */ +#define ALT_SDMMC_MINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_MINTSTS. + */ +struct ALT_SDMMC_MINTSTS_s +{ + const uint32_t cd : 1; /* Card Detect */ + const uint32_t resp : 1; /* Response Error */ + const uint32_t cmd_done : 1; /* Command Done */ + const uint32_t dt : 1; /* Data Transfer Over */ + const uint32_t dttxfifodr : 1; /* Data TX FIFO Data Request */ + const uint32_t rxfifodr : 1; /* Receive FIFO Data Request */ + const uint32_t respcrcerr : 1; /* Response CRC Error */ + const uint32_t datacrcerr : 1; /* Data CRC Error */ + const uint32_t respto : 1; /* Response Timeout */ + const uint32_t datardto : 1; /* Data Read Timeout */ + const uint32_t dshto : 1; /* Data Starvation Host Timeout */ + const uint32_t fifoovunerr : 1; /* FIFO Underrun Overrun Error */ + const uint32_t hlwerr : 1; /* Hardware Locked Write Error */ + const uint32_t strerr : 1; /* Start-bit Error */ + const uint32_t acd : 1; /* Auto Command Done */ + const uint32_t ebe : 1; /* End-bit Error */ + const uint32_t sdio_interrupt : 1; /* SDIO Interrupts */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_MINTSTS. */ +typedef volatile struct ALT_SDMMC_MINTSTS_s ALT_SDMMC_MINTSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_MINTSTS register from the beginning of the component. */ +#define ALT_SDMMC_MINTSTS_OFST 0x40 + +/* + * Register : Raw Interrupt Status Register - rintsts + * + * Interrupt Status Before Masking. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------------- + * [0] | RW | 0x0 | Card Detect + * [1] | RW | 0x0 | Response Error + * [2] | RW | 0x0 | Command Done + * [3] | RW | 0x0 | Data Transfer Over + * [4] | RW | 0x0 | Transmit FIFO Data Request + * [5] | RW | 0x0 | Receive FIFO Data Request + * [6] | RW | 0x0 | Response CRC Error + * [7] | RW | 0x0 | Data CRC Error + * [8] | RW | 0x0 | Response Timeout Boot Ack Received + * [9] | RW | 0x0 | Data Read Timeout Boot Data Start + * [10] | RW | 0x0 | Data Starvation Host Timeout Volt Switch_int + * [11] | RW | 0x0 | FIFO Underrun Overrun Error + * [12] | RW | 0x0 | Hardware Locked Write Error + * [13] | RW | 0x0 | Start-bit error (SBE) + * [14] | RW | 0x0 | Auto Cmommand Done + * [15] | RW | 0x0 | End-bit Error + * [16] | RW | 0x0 | SDIO Interrupt + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Card Detect - cd + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------------ + * ALT_SDMMC_RINTSTS_CD_E_INACT | 0x0 | Card detect (CD) + * ALT_SDMMC_RINTSTS_CD_E_ACT | 0x1 | Clears Card detect (CD) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_CD + * + * Card detect (CD) + */ +#define ALT_SDMMC_RINTSTS_CD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_CD + * + * Clears Card detect (CD) + */ +#define ALT_SDMMC_RINTSTS_CD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_CD register field. */ +#define ALT_SDMMC_RINTSTS_CD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_CD register field. */ +#define ALT_SDMMC_RINTSTS_CD_MSB 0 +/* The width in bits of the ALT_SDMMC_RINTSTS_CD register field. */ +#define ALT_SDMMC_RINTSTS_CD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_CD register field value. */ +#define ALT_SDMMC_RINTSTS_CD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_RINTSTS_CD register field value. */ +#define ALT_SDMMC_RINTSTS_CD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_RINTSTS_CD register field. */ +#define ALT_SDMMC_RINTSTS_CD_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_CD field value from a register. */ +#define ALT_SDMMC_RINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_RINTSTS_CD register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_CD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Response Error - re + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:--------------------------- + * ALT_SDMMC_RINTSTS_RE_E_INACT | 0x0 | Response error (RE) + * ALT_SDMMC_RINTSTS_RE_E_ACT | 0x1 | Clears Response error (RE) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_RE + * + * Response error (RE) + */ +#define ALT_SDMMC_RINTSTS_RE_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_RE + * + * Clears Response error (RE) + */ +#define ALT_SDMMC_RINTSTS_RE_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RE register field. */ +#define ALT_SDMMC_RINTSTS_RE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RE register field. */ +#define ALT_SDMMC_RINTSTS_RE_MSB 1 +/* The width in bits of the ALT_SDMMC_RINTSTS_RE register field. */ +#define ALT_SDMMC_RINTSTS_RE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_RE register field value. */ +#define ALT_SDMMC_RINTSTS_RE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDMMC_RINTSTS_RE register field value. */ +#define ALT_SDMMC_RINTSTS_RE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDMMC_RINTSTS_RE register field. */ +#define ALT_SDMMC_RINTSTS_RE_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_RE field value from a register. */ +#define ALT_SDMMC_RINTSTS_RE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDMMC_RINTSTS_RE register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_RE_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Command Done - cmd + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------- + * ALT_SDMMC_RINTSTS_CMD_E_INACT | 0x0 | Command done (CD) + * ALT_SDMMC_RINTSTS_CMD_E_ACT | 0x1 | Clears Command done (CD) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_CMD + * + * Command done (CD) + */ +#define ALT_SDMMC_RINTSTS_CMD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_CMD + * + * Clears Command done (CD) + */ +#define ALT_SDMMC_RINTSTS_CMD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_CMD register field. */ +#define ALT_SDMMC_RINTSTS_CMD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_CMD register field. */ +#define ALT_SDMMC_RINTSTS_CMD_MSB 2 +/* The width in bits of the ALT_SDMMC_RINTSTS_CMD register field. */ +#define ALT_SDMMC_RINTSTS_CMD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_CMD register field value. */ +#define ALT_SDMMC_RINTSTS_CMD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDMMC_RINTSTS_CMD register field value. */ +#define ALT_SDMMC_RINTSTS_CMD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDMMC_RINTSTS_CMD register field. */ +#define ALT_SDMMC_RINTSTS_CMD_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_CMD field value from a register. */ +#define ALT_SDMMC_RINTSTS_CMD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDMMC_RINTSTS_CMD register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_CMD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Data Transfer Over - dto + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:-------------------------------- + * ALT_SDMMC_RINTSTS_DTO_E_INACT | 0x0 | Data transfer over (DTO) + * ALT_SDMMC_RINTSTS_DTO_E_ACT | 0x1 | Clears Data transfer over (DTO) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_DTO + * + * Data transfer over (DTO) + */ +#define ALT_SDMMC_RINTSTS_DTO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_DTO + * + * Clears Data transfer over (DTO) + */ +#define ALT_SDMMC_RINTSTS_DTO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_DTO register field. */ +#define ALT_SDMMC_RINTSTS_DTO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_DTO register field. */ +#define ALT_SDMMC_RINTSTS_DTO_MSB 3 +/* The width in bits of the ALT_SDMMC_RINTSTS_DTO register field. */ +#define ALT_SDMMC_RINTSTS_DTO_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_DTO register field value. */ +#define ALT_SDMMC_RINTSTS_DTO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDMMC_RINTSTS_DTO register field value. */ +#define ALT_SDMMC_RINTSTS_DTO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDMMC_RINTSTS_DTO register field. */ +#define ALT_SDMMC_RINTSTS_DTO_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_DTO field value from a register. */ +#define ALT_SDMMC_RINTSTS_DTO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDMMC_RINTSTS_DTO register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_DTO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Transmit FIFO Data Request - txdr + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------------------------- + * ALT_SDMMC_RINTSTS_TXDR_E_INACT | 0x0 | Transmit FIFO data request (TXDR) + * ALT_SDMMC_RINTSTS_TXDR_E_ACT | 0x1 | Clears Transmit FIFO data request (TXDR) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_TXDR + * + * Transmit FIFO data request (TXDR) + */ +#define ALT_SDMMC_RINTSTS_TXDR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_TXDR + * + * Clears Transmit FIFO data request (TXDR) + */ +#define ALT_SDMMC_RINTSTS_TXDR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_TXDR register field. */ +#define ALT_SDMMC_RINTSTS_TXDR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_TXDR register field. */ +#define ALT_SDMMC_RINTSTS_TXDR_MSB 4 +/* The width in bits of the ALT_SDMMC_RINTSTS_TXDR register field. */ +#define ALT_SDMMC_RINTSTS_TXDR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_TXDR register field value. */ +#define ALT_SDMMC_RINTSTS_TXDR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDMMC_RINTSTS_TXDR register field value. */ +#define ALT_SDMMC_RINTSTS_TXDR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDMMC_RINTSTS_TXDR register field. */ +#define ALT_SDMMC_RINTSTS_TXDR_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_TXDR field value from a register. */ +#define ALT_SDMMC_RINTSTS_TXDR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDMMC_RINTSTS_TXDR register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_TXDR_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Receive FIFO Data Request - rxdr + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------------------------- + * ALT_SDMMC_RINTSTS_RXDR_E_INACT | 0x0 | Receive FIFO data request (RXDR) + * ALT_SDMMC_RINTSTS_RXDR_E_ACT | 0x1 | Clears Receive FIFO data request (RXDR) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_RXDR + * + * Receive FIFO data request (RXDR) + */ +#define ALT_SDMMC_RINTSTS_RXDR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_RXDR + * + * Clears Receive FIFO data request (RXDR) + */ +#define ALT_SDMMC_RINTSTS_RXDR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RXDR register field. */ +#define ALT_SDMMC_RINTSTS_RXDR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RXDR register field. */ +#define ALT_SDMMC_RINTSTS_RXDR_MSB 5 +/* The width in bits of the ALT_SDMMC_RINTSTS_RXDR register field. */ +#define ALT_SDMMC_RINTSTS_RXDR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_RXDR register field value. */ +#define ALT_SDMMC_RINTSTS_RXDR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SDMMC_RINTSTS_RXDR register field value. */ +#define ALT_SDMMC_RINTSTS_RXDR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SDMMC_RINTSTS_RXDR register field. */ +#define ALT_SDMMC_RINTSTS_RXDR_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_RXDR field value from a register. */ +#define ALT_SDMMC_RINTSTS_RXDR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SDMMC_RINTSTS_RXDR register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_RXDR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Response CRC Error - rcrc + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:--------------------------------- + * ALT_SDMMC_RINTSTS_RCRC_E_INACT | 0x0 | Response CRC error (RCRC) + * ALT_SDMMC_RINTSTS_RCRC_E_ACT | 0x1 | Clears Response CRC error (RCRC) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_RCRC + * + * Response CRC error (RCRC) + */ +#define ALT_SDMMC_RINTSTS_RCRC_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_RCRC + * + * Clears Response CRC error (RCRC) + */ +#define ALT_SDMMC_RINTSTS_RCRC_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RCRC register field. */ +#define ALT_SDMMC_RINTSTS_RCRC_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RCRC register field. */ +#define ALT_SDMMC_RINTSTS_RCRC_MSB 6 +/* The width in bits of the ALT_SDMMC_RINTSTS_RCRC register field. */ +#define ALT_SDMMC_RINTSTS_RCRC_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_RCRC register field value. */ +#define ALT_SDMMC_RINTSTS_RCRC_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SDMMC_RINTSTS_RCRC register field value. */ +#define ALT_SDMMC_RINTSTS_RCRC_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SDMMC_RINTSTS_RCRC register field. */ +#define ALT_SDMMC_RINTSTS_RCRC_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_RCRC field value from a register. */ +#define ALT_SDMMC_RINTSTS_RCRC_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SDMMC_RINTSTS_RCRC register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_RCRC_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Data CRC Error - dcrc + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------------- + * ALT_SDMMC_RINTSTS_DCRC_E_INACT | 0x0 | Data CRC error (DCRC) + * ALT_SDMMC_RINTSTS_DCRC_E_ACT | 0x1 | Clears Data CRC error (DCRC) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_DCRC + * + * Data CRC error (DCRC) + */ +#define ALT_SDMMC_RINTSTS_DCRC_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_DCRC + * + * Clears Data CRC error (DCRC) + */ +#define ALT_SDMMC_RINTSTS_DCRC_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_DCRC register field. */ +#define ALT_SDMMC_RINTSTS_DCRC_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_DCRC register field. */ +#define ALT_SDMMC_RINTSTS_DCRC_MSB 7 +/* The width in bits of the ALT_SDMMC_RINTSTS_DCRC register field. */ +#define ALT_SDMMC_RINTSTS_DCRC_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_DCRC register field value. */ +#define ALT_SDMMC_RINTSTS_DCRC_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SDMMC_RINTSTS_DCRC register field value. */ +#define ALT_SDMMC_RINTSTS_DCRC_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SDMMC_RINTSTS_DCRC register field. */ +#define ALT_SDMMC_RINTSTS_DCRC_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_DCRC field value from a register. */ +#define ALT_SDMMC_RINTSTS_DCRC_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SDMMC_RINTSTS_DCRC register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_DCRC_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Response Timeout Boot Ack Received - bar + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------ + * ALT_SDMMC_RINTSTS_BAR_E_INACT | 0x0 | Response timeout (RTO)/Boot Ack Received (BAR) + * ALT_SDMMC_RINTSTS_BAR_E_ACT | 0x1 | Clears Response timeout (RTO)/Boot Ack Received + * : | | (BAR) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_BAR + * + * Response timeout (RTO)/Boot Ack Received (BAR) + */ +#define ALT_SDMMC_RINTSTS_BAR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_BAR + * + * Clears Response timeout (RTO)/Boot Ack Received (BAR) + */ +#define ALT_SDMMC_RINTSTS_BAR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_BAR register field. */ +#define ALT_SDMMC_RINTSTS_BAR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_BAR register field. */ +#define ALT_SDMMC_RINTSTS_BAR_MSB 8 +/* The width in bits of the ALT_SDMMC_RINTSTS_BAR register field. */ +#define ALT_SDMMC_RINTSTS_BAR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_BAR register field value. */ +#define ALT_SDMMC_RINTSTS_BAR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SDMMC_RINTSTS_BAR register field value. */ +#define ALT_SDMMC_RINTSTS_BAR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SDMMC_RINTSTS_BAR register field. */ +#define ALT_SDMMC_RINTSTS_BAR_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_BAR field value from a register. */ +#define ALT_SDMMC_RINTSTS_BAR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SDMMC_RINTSTS_BAR register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_BAR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Data Read Timeout Boot Data Start - bds + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------ + * ALT_SDMMC_RINTSTS_BDS_E_INACT | 0x0 | Data read timeout (DRTO)/Boot Data Start (BDS) + * ALT_SDMMC_RINTSTS_BDS_E_ACT | 0x1 | Clears Data read timeout (DRTO)/Boot Data Start + * : | | (BDS) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_BDS + * + * Data read timeout (DRTO)/Boot Data Start (BDS) + */ +#define ALT_SDMMC_RINTSTS_BDS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_BDS + * + * Clears Data read timeout (DRTO)/Boot Data Start (BDS) + */ +#define ALT_SDMMC_RINTSTS_BDS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_BDS register field. */ +#define ALT_SDMMC_RINTSTS_BDS_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_BDS register field. */ +#define ALT_SDMMC_RINTSTS_BDS_MSB 9 +/* The width in bits of the ALT_SDMMC_RINTSTS_BDS register field. */ +#define ALT_SDMMC_RINTSTS_BDS_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_BDS register field value. */ +#define ALT_SDMMC_RINTSTS_BDS_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SDMMC_RINTSTS_BDS register field value. */ +#define ALT_SDMMC_RINTSTS_BDS_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SDMMC_RINTSTS_BDS register field. */ +#define ALT_SDMMC_RINTSTS_BDS_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_BDS field value from a register. */ +#define ALT_SDMMC_RINTSTS_BDS_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SDMMC_RINTSTS_BDS register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_BDS_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Starvation Host Timeout Volt Switch_int - hto + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:--------------------------------------------- + * ALT_SDMMC_RINTSTS_HTO_E_INACT | 0x0 | Data starvation-by-host timeout (HTO) + * : | | /Volt_switch_int + * ALT_SDMMC_RINTSTS_HTO_E_ACT | 0x1 | Clears Data starvation-by-host timeout (HTO) + * : | | /Volt_switch_int + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_HTO + * + * Data starvation-by-host timeout (HTO) /Volt_switch_int + */ +#define ALT_SDMMC_RINTSTS_HTO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_HTO + * + * Clears Data starvation-by-host timeout (HTO) /Volt_switch_int + */ +#define ALT_SDMMC_RINTSTS_HTO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_HTO register field. */ +#define ALT_SDMMC_RINTSTS_HTO_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_HTO register field. */ +#define ALT_SDMMC_RINTSTS_HTO_MSB 10 +/* The width in bits of the ALT_SDMMC_RINTSTS_HTO register field. */ +#define ALT_SDMMC_RINTSTS_HTO_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_HTO register field value. */ +#define ALT_SDMMC_RINTSTS_HTO_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SDMMC_RINTSTS_HTO register field value. */ +#define ALT_SDMMC_RINTSTS_HTO_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SDMMC_RINTSTS_HTO register field. */ +#define ALT_SDMMC_RINTSTS_HTO_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_HTO field value from a register. */ +#define ALT_SDMMC_RINTSTS_HTO_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SDMMC_RINTSTS_HTO register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_HTO_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : FIFO Underrun Overrun Error - frun + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------------------------- + * ALT_SDMMC_RINTSTS_FRUN_E_INACT | 0x0 | FIFO underrun/overrun error (FRUN) + * ALT_SDMMC_RINTSTS_FRUN_E_ACT | 0x1 | Clear FIFO underrun/overrun error (FRUN) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_FRUN + * + * FIFO underrun/overrun error (FRUN) + */ +#define ALT_SDMMC_RINTSTS_FRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_FRUN + * + * Clear FIFO underrun/overrun error (FRUN) + */ +#define ALT_SDMMC_RINTSTS_FRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_FRUN register field. */ +#define ALT_SDMMC_RINTSTS_FRUN_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_FRUN register field. */ +#define ALT_SDMMC_RINTSTS_FRUN_MSB 11 +/* The width in bits of the ALT_SDMMC_RINTSTS_FRUN register field. */ +#define ALT_SDMMC_RINTSTS_FRUN_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_FRUN register field value. */ +#define ALT_SDMMC_RINTSTS_FRUN_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SDMMC_RINTSTS_FRUN register field value. */ +#define ALT_SDMMC_RINTSTS_FRUN_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SDMMC_RINTSTS_FRUN register field. */ +#define ALT_SDMMC_RINTSTS_FRUN_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_FRUN field value from a register. */ +#define ALT_SDMMC_RINTSTS_FRUN_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SDMMC_RINTSTS_FRUN register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_FRUN_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Hardware Locked Write Error - hle + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------------------- + * ALT_SDMMC_RINTSTS_HLE_E_INACT | 0x0 | Hardware locked write error (HLE) + * ALT_SDMMC_RINTSTS_HLE_E_ACT | 0x1 | Clears Hardware locked write error (HLE) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_HLE + * + * Hardware locked write error (HLE) + */ +#define ALT_SDMMC_RINTSTS_HLE_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_HLE + * + * Clears Hardware locked write error (HLE) + */ +#define ALT_SDMMC_RINTSTS_HLE_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_HLE register field. */ +#define ALT_SDMMC_RINTSTS_HLE_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_HLE register field. */ +#define ALT_SDMMC_RINTSTS_HLE_MSB 12 +/* The width in bits of the ALT_SDMMC_RINTSTS_HLE register field. */ +#define ALT_SDMMC_RINTSTS_HLE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_HLE register field value. */ +#define ALT_SDMMC_RINTSTS_HLE_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SDMMC_RINTSTS_HLE register field value. */ +#define ALT_SDMMC_RINTSTS_HLE_CLR_MSK 0xffffefff +/* The reset value of the ALT_SDMMC_RINTSTS_HLE register field. */ +#define ALT_SDMMC_RINTSTS_HLE_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_HLE field value from a register. */ +#define ALT_SDMMC_RINTSTS_HLE_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SDMMC_RINTSTS_HLE register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_HLE_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Start-bit error (SBE) - sbe + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_SDMMC_RINTSTS_SBE_E_INACT | 0x0 | Start-bit error (SBE) + * ALT_SDMMC_RINTSTS_SBE_E_ACT | 0x1 | Clears Start-bit error (SBE) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_SBE + * + * Start-bit error (SBE) + */ +#define ALT_SDMMC_RINTSTS_SBE_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_SBE + * + * Clears Start-bit error (SBE) + */ +#define ALT_SDMMC_RINTSTS_SBE_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SBE register field. */ +#define ALT_SDMMC_RINTSTS_SBE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SBE register field. */ +#define ALT_SDMMC_RINTSTS_SBE_MSB 13 +/* The width in bits of the ALT_SDMMC_RINTSTS_SBE register field. */ +#define ALT_SDMMC_RINTSTS_SBE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_SBE register field value. */ +#define ALT_SDMMC_RINTSTS_SBE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SDMMC_RINTSTS_SBE register field value. */ +#define ALT_SDMMC_RINTSTS_SBE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SDMMC_RINTSTS_SBE register field. */ +#define ALT_SDMMC_RINTSTS_SBE_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_SBE field value from a register. */ +#define ALT_SDMMC_RINTSTS_SBE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SDMMC_RINTSTS_SBE register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_SBE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Auto Cmommand Done - acd + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------- + * ALT_SDMMC_RINTSTS_ACD_E_INACT | 0x0 | Auto command done (ACD) + * ALT_SDMMC_RINTSTS_ACD_E_ACT | 0x1 | Clear Auto command done (ACD + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_ACD + * + * Auto command done (ACD) + */ +#define ALT_SDMMC_RINTSTS_ACD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_ACD + * + * Clear Auto command done (ACD + */ +#define ALT_SDMMC_RINTSTS_ACD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_ACD register field. */ +#define ALT_SDMMC_RINTSTS_ACD_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_ACD register field. */ +#define ALT_SDMMC_RINTSTS_ACD_MSB 14 +/* The width in bits of the ALT_SDMMC_RINTSTS_ACD register field. */ +#define ALT_SDMMC_RINTSTS_ACD_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_ACD register field value. */ +#define ALT_SDMMC_RINTSTS_ACD_SET_MSK 0x00004000 +/* The mask used to clear the ALT_SDMMC_RINTSTS_ACD register field value. */ +#define ALT_SDMMC_RINTSTS_ACD_CLR_MSK 0xffffbfff +/* The reset value of the ALT_SDMMC_RINTSTS_ACD register field. */ +#define ALT_SDMMC_RINTSTS_ACD_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_ACD field value from a register. */ +#define ALT_SDMMC_RINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_SDMMC_RINTSTS_ACD register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : End-bit Error - ebe + * + * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 + * leaves bit intact. Bits are logged regardless of interrupt mask status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:----------------------------------------------- + * ALT_SDMMC_RINTSTS_EBE_E_INACT | 0x0 | End-bit error (read)/write no CRC (EBE) + * ALT_SDMMC_RINTSTS_EBE_E_ACT | 0x1 | Clears End-bit error (read)/write no CRC (EBE) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_EBE + * + * End-bit error (read)/write no CRC (EBE) + */ +#define ALT_SDMMC_RINTSTS_EBE_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_EBE + * + * Clears End-bit error (read)/write no CRC (EBE) + */ +#define ALT_SDMMC_RINTSTS_EBE_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_EBE register field. */ +#define ALT_SDMMC_RINTSTS_EBE_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_EBE register field. */ +#define ALT_SDMMC_RINTSTS_EBE_MSB 15 +/* The width in bits of the ALT_SDMMC_RINTSTS_EBE register field. */ +#define ALT_SDMMC_RINTSTS_EBE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_EBE register field value. */ +#define ALT_SDMMC_RINTSTS_EBE_SET_MSK 0x00008000 +/* The mask used to clear the ALT_SDMMC_RINTSTS_EBE register field value. */ +#define ALT_SDMMC_RINTSTS_EBE_CLR_MSK 0xffff7fff +/* The reset value of the ALT_SDMMC_RINTSTS_EBE register field. */ +#define ALT_SDMMC_RINTSTS_EBE_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_EBE field value from a register. */ +#define ALT_SDMMC_RINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_SDMMC_RINTSTS_EBE register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : SDIO Interrupt - sdio_interrupt + * + * Interrupt from SDIO card. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------- + * ALT_SDMMC_RINTSTS_SDIO_INT_E_ACT | 0x1 | SDIO interrupt from card bit + * ALT_SDMMC_RINTSTS_SDIO_INT_E_INACT | 0x0 | No SDIO interrupt from card bi + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INT + * + * SDIO interrupt from card bit + */ +#define ALT_SDMMC_RINTSTS_SDIO_INT_E_ACT 0x1 +/* + * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INT + * + * No SDIO interrupt from card bi + */ +#define ALT_SDMMC_RINTSTS_SDIO_INT_E_INACT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */ +#define ALT_SDMMC_RINTSTS_SDIO_INT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */ +#define ALT_SDMMC_RINTSTS_SDIO_INT_MSB 16 +/* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */ +#define ALT_SDMMC_RINTSTS_SDIO_INT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INT register field value. */ +#define ALT_SDMMC_RINTSTS_SDIO_INT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INT register field value. */ +#define ALT_SDMMC_RINTSTS_SDIO_INT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */ +#define ALT_SDMMC_RINTSTS_SDIO_INT_RESET 0x0 +/* Extracts the ALT_SDMMC_RINTSTS_SDIO_INT field value from a register. */ +#define ALT_SDMMC_RINTSTS_SDIO_INT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_SDMMC_RINTSTS_SDIO_INT register field value suitable for setting the register. */ +#define ALT_SDMMC_RINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_RINTSTS. + */ +struct ALT_SDMMC_RINTSTS_s +{ + uint32_t cd : 1; /* Card Detect */ + uint32_t re : 1; /* Response Error */ + uint32_t cmd : 1; /* Command Done */ + uint32_t dto : 1; /* Data Transfer Over */ + uint32_t txdr : 1; /* Transmit FIFO Data Request */ + uint32_t rxdr : 1; /* Receive FIFO Data Request */ + uint32_t rcrc : 1; /* Response CRC Error */ + uint32_t dcrc : 1; /* Data CRC Error */ + uint32_t bar : 1; /* Response Timeout Boot Ack Received */ + uint32_t bds : 1; /* Data Read Timeout Boot Data Start */ + uint32_t hto : 1; /* Data Starvation Host Timeout Volt Switch_int */ + uint32_t frun : 1; /* FIFO Underrun Overrun Error */ + uint32_t hle : 1; /* Hardware Locked Write Error */ + uint32_t sbe : 1; /* Start-bit error (SBE) */ + uint32_t acd : 1; /* Auto Cmommand Done */ + uint32_t ebe : 1; /* End-bit Error */ + uint32_t sdio_interrupt : 1; /* SDIO Interrupt */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_RINTSTS. */ +typedef volatile struct ALT_SDMMC_RINTSTS_s ALT_SDMMC_RINTSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_RINTSTS register from the beginning of the component. */ +#define ALT_SDMMC_RINTSTS_OFST 0x44 + +/* + * Register : Status Register - status + * + * Reports various operting status conditions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [0] | R | 0x0 | FIFO Rx Watermark + * [1] | R | 0x1 | FIFO Tx Watermark + * [2] | R | 0x1 | FIFO Empty + * [3] | R | 0x0 | FIFO Full + * [7:4] | R | 0x0 | Command FSM States + * [8] | R | 0x1 | Data 3 Status + * [9] | R | 0x0 | Data Busy + * [10] | R | 0x0 | Data State MC Busy + * [16:11] | R | 0x0 | Response Index + * [29:17] | R | 0x0 | FIFO Count + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FIFO Rx Watermark - fifo_rx_watermark + * + * FIFO reached Receive watermark level; not qualified with data transfer + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:------------------------------------------------- + * ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK | 0x0 | FIFO reached watermark level; not qualified with + * : | | data transfer. + * ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_NORXWATERMARK | 0x1 | FIFO not at watermark Level + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_STAT_FIFO_RX_WATERMARK + * + * FIFO reached watermark level; not qualified with data transfer. + */ +#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK 0x0 +/* + * Enumerated value for register field ALT_SDMMC_STAT_FIFO_RX_WATERMARK + * + * FIFO not at watermark Level + */ +#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_NORXWATERMARK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */ +#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */ +#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_MSB 0 +/* The width in bits of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */ +#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_WIDTH 1 +/* The mask used to set the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field value. */ +#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field value. */ +#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */ +#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_RESET 0x0 +/* Extracts the ALT_SDMMC_STAT_FIFO_RX_WATERMARK field value from a register. */ +#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field value suitable for setting the register. */ +#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : FIFO Tx Watermark - fifo_tx_watermark + * + * FIFO reached Transmit watermark level; not qualified with data transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------|:------|:------------------------------------------- + * ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK | 0x1 | FIFO reached transmit watermark level: not + * : | | qualified with data transfer. + * ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_NOTXWATERMARK | 0x0 | FIFO not at transmit watermark Level + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_STAT_FIFO_TX_WATERMARK + * + * FIFO reached transmit watermark level: not qualified with data transfer. + */ +#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK 0x1 +/* + * Enumerated value for register field ALT_SDMMC_STAT_FIFO_TX_WATERMARK + * + * FIFO not at transmit watermark Level + */ +#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_NOTXWATERMARK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */ +#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */ +#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_MSB 1 +/* The width in bits of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */ +#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_WIDTH 1 +/* The mask used to set the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field value. */ +#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field value. */ +#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */ +#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_RESET 0x1 +/* Extracts the ALT_SDMMC_STAT_FIFO_TX_WATERMARK field value from a register. */ +#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field value suitable for setting the register. */ +#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : FIFO Empty - fifo_empty + * + * FIFO is empty status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY | 0x1 | FIFO is empty + * ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFONOTEMPTY | 0x0 | FIFO not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_STAT_FIFO_EMPTY + * + * FIFO is empty + */ +#define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY 0x1 +/* + * Enumerated value for register field ALT_SDMMC_STAT_FIFO_EMPTY + * + * FIFO not empty + */ +#define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFONOTEMPTY 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */ +#define ALT_SDMMC_STAT_FIFO_EMPTY_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */ +#define ALT_SDMMC_STAT_FIFO_EMPTY_MSB 2 +/* The width in bits of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */ +#define ALT_SDMMC_STAT_FIFO_EMPTY_WIDTH 1 +/* The mask used to set the ALT_SDMMC_STAT_FIFO_EMPTY register field value. */ +#define ALT_SDMMC_STAT_FIFO_EMPTY_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDMMC_STAT_FIFO_EMPTY register field value. */ +#define ALT_SDMMC_STAT_FIFO_EMPTY_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */ +#define ALT_SDMMC_STAT_FIFO_EMPTY_RESET 0x1 +/* Extracts the ALT_SDMMC_STAT_FIFO_EMPTY field value from a register. */ +#define ALT_SDMMC_STAT_FIFO_EMPTY_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDMMC_STAT_FIFO_EMPTY register field value suitable for setting the register. */ +#define ALT_SDMMC_STAT_FIFO_EMPTY_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : FIFO Full - fifo_full + * + * FIFO is full status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------- + * ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL | 0x0 | FIFO is full + * ALT_SDMMC_STAT_FIFO_FULL_E_FIFONOTFULL | 0x1 | FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_STAT_FIFO_FULL + * + * FIFO is full + */ +#define ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL 0x0 +/* + * Enumerated value for register field ALT_SDMMC_STAT_FIFO_FULL + * + * FIFO is not full + */ +#define ALT_SDMMC_STAT_FIFO_FULL_E_FIFONOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_FULL register field. */ +#define ALT_SDMMC_STAT_FIFO_FULL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_FULL register field. */ +#define ALT_SDMMC_STAT_FIFO_FULL_MSB 3 +/* The width in bits of the ALT_SDMMC_STAT_FIFO_FULL register field. */ +#define ALT_SDMMC_STAT_FIFO_FULL_WIDTH 1 +/* The mask used to set the ALT_SDMMC_STAT_FIFO_FULL register field value. */ +#define ALT_SDMMC_STAT_FIFO_FULL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDMMC_STAT_FIFO_FULL register field value. */ +#define ALT_SDMMC_STAT_FIFO_FULL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDMMC_STAT_FIFO_FULL register field. */ +#define ALT_SDMMC_STAT_FIFO_FULL_RESET 0x0 +/* Extracts the ALT_SDMMC_STAT_FIFO_FULL field value from a register. */ +#define ALT_SDMMC_STAT_FIFO_FULL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDMMC_STAT_FIFO_FULL register field value suitable for setting the register. */ +#define ALT_SDMMC_STAT_FIFO_FULL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Command FSM States - command_fsm_states + * + * The command FSM state. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:-------------------------------------------- + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_IDLEANDOTHERS | 0x0 | Idle, Wait for CCS, Send CCSD, or Boot Mode + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_SENDINITSEQ | 0x1 | Send init sequence + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDSTART | 0x2 | Tx cmd start bit + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDTXBIT | 0x3 | Tx cmd tx bit + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDINDXARG | 0x4 | Tx cmd index + arg + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDCRC7 | 0x5 | Tx cmd crc7 + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDEND | 0x6 | Tx cmd end bit + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPSTART | 0x7 | Rx resp start bit + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPIRQ | 0x8 | Rx resp IRQ response + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPTX | 0x9 | Rx resp tx bit + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCMDIDX | 0xa | Rx resp cmd idx + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPDATA | 0xb | Rx resp data + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCRC7 | 0xc | Rx resp crc7 + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPEND | 0xd | Rx resp end bit + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_CMDPATHWAIT | 0xe | Cmd path wait NCC + * ALT_SDMMC_STAT_CMD_FSM_STATES_E_WAITCMDTURN | 0xf | Wait: CMD-to-reponse turnaround + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Idle, Wait for CCS, Send CCSD, or Boot Mode + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_IDLEANDOTHERS 0x0 +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Send init sequence + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_SENDINITSEQ 0x1 +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Tx cmd start bit + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDSTART 0x2 +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Tx cmd tx bit + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDTXBIT 0x3 +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Tx cmd index + arg + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDINDXARG 0x4 +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Tx cmd crc7 + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDCRC7 0x5 +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Tx cmd end bit + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDEND 0x6 +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Rx resp start bit + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPSTART 0x7 +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Rx resp IRQ response + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPIRQ 0x8 +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Rx resp tx bit + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPTX 0x9 +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Rx resp cmd idx + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCMDIDX 0xa +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Rx resp data + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPDATA 0xb +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Rx resp crc7 + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCRC7 0xc +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Rx resp end bit + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPEND 0xd +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Cmd path wait NCC + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_CMDPATHWAIT 0xe +/* + * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES + * + * Wait: CMD-to-reponse turnaround + */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_WAITCMDTURN 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_MSB 7 +/* The width in bits of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_WIDTH 4 +/* The mask used to set the ALT_SDMMC_STAT_CMD_FSM_STATES register field value. */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_SDMMC_STAT_CMD_FSM_STATES register field value. */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_CLR_MSK 0xffffff0f +/* The reset value of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_RESET 0x0 +/* Extracts the ALT_SDMMC_STAT_CMD_FSM_STATES field value from a register. */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_SDMMC_STAT_CMD_FSM_STATES register field value suitable for setting the register. */ +#define ALT_SDMMC_STAT_CMD_FSM_STATES_SET(value) (((value) << 4) & 0x000000f0) + +/* + * Field : Data 3 Status - data_3_status + * + * Raw selected card_data[3]; checks whether card is present. The default can be + * cardpresent or not present depend on cdata_in. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:----------------- + * ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT | 0x1 | Card Present + * ALT_SDMMC_STAT_DATA_3_STAT_E_CARDNOTPRESENT | 0x0 | Card Not Present + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_STAT_DATA_3_STAT + * + * Card Present + */ +#define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT 0x1 +/* + * Enumerated value for register field ALT_SDMMC_STAT_DATA_3_STAT + * + * Card Not Present + */ +#define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDNOTPRESENT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DATA_3_STAT register field. */ +#define ALT_SDMMC_STAT_DATA_3_STAT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DATA_3_STAT register field. */ +#define ALT_SDMMC_STAT_DATA_3_STAT_MSB 8 +/* The width in bits of the ALT_SDMMC_STAT_DATA_3_STAT register field. */ +#define ALT_SDMMC_STAT_DATA_3_STAT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_STAT_DATA_3_STAT register field value. */ +#define ALT_SDMMC_STAT_DATA_3_STAT_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SDMMC_STAT_DATA_3_STAT register field value. */ +#define ALT_SDMMC_STAT_DATA_3_STAT_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SDMMC_STAT_DATA_3_STAT register field. */ +#define ALT_SDMMC_STAT_DATA_3_STAT_RESET 0x1 +/* Extracts the ALT_SDMMC_STAT_DATA_3_STAT field value from a register. */ +#define ALT_SDMMC_STAT_DATA_3_STAT_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SDMMC_STAT_DATA_3_STAT register field value suitable for setting the register. */ +#define ALT_SDMMC_STAT_DATA_3_STAT_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Data Busy - data_busy + * + * Inverted version of raw selected card_data[0]. The default can be cardpresent or + * not present depend on cdata_in. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------- + * ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY | 0x1 | card data busy + * ALT_SDMMC_STAT_DATA_BUSY_E_CARDNOTBUSY | 0x0 | card data not busy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_STAT_DATA_BUSY + * + * card data busy + */ +#define ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY 0x1 +/* + * Enumerated value for register field ALT_SDMMC_STAT_DATA_BUSY + * + * card data not busy + */ +#define ALT_SDMMC_STAT_DATA_BUSY_E_CARDNOTBUSY 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DATA_BUSY register field. */ +#define ALT_SDMMC_STAT_DATA_BUSY_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DATA_BUSY register field. */ +#define ALT_SDMMC_STAT_DATA_BUSY_MSB 9 +/* The width in bits of the ALT_SDMMC_STAT_DATA_BUSY register field. */ +#define ALT_SDMMC_STAT_DATA_BUSY_WIDTH 1 +/* The mask used to set the ALT_SDMMC_STAT_DATA_BUSY register field value. */ +#define ALT_SDMMC_STAT_DATA_BUSY_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SDMMC_STAT_DATA_BUSY register field value. */ +#define ALT_SDMMC_STAT_DATA_BUSY_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SDMMC_STAT_DATA_BUSY register field. */ +#define ALT_SDMMC_STAT_DATA_BUSY_RESET 0x0 +/* Extracts the ALT_SDMMC_STAT_DATA_BUSY field value from a register. */ +#define ALT_SDMMC_STAT_DATA_BUSY_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SDMMC_STAT_DATA_BUSY register field value suitable for setting the register. */ +#define ALT_SDMMC_STAT_DATA_BUSY_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data State MC Busy - data_state_mc_busy + * + * Data transmit or receive state-machine is busy. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:----------------------- + * ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATEBSY | 0x1 | Data State MC busy + * ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATENOTBSY | 0x0 | Data State MC not busy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_STAT_DATA_STATE_MC_BUSY + * + * Data State MC busy + */ +#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATEBSY 0x1 +/* + * Enumerated value for register field ALT_SDMMC_STAT_DATA_STATE_MC_BUSY + * + * Data State MC not busy + */ +#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATENOTBSY 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */ +#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */ +#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_MSB 10 +/* The width in bits of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */ +#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_WIDTH 1 +/* The mask used to set the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field value. */ +#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field value. */ +#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */ +#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_RESET 0x0 +/* Extracts the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY field value from a register. */ +#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field value suitable for setting the register. */ +#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Response Index - response_index + * + * Index of previous response, including any auto-stop sent by core + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */ +#define ALT_SDMMC_STAT_RESPONSE_INDEX_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */ +#define ALT_SDMMC_STAT_RESPONSE_INDEX_MSB 16 +/* The width in bits of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */ +#define ALT_SDMMC_STAT_RESPONSE_INDEX_WIDTH 6 +/* The mask used to set the ALT_SDMMC_STAT_RESPONSE_INDEX register field value. */ +#define ALT_SDMMC_STAT_RESPONSE_INDEX_SET_MSK 0x0001f800 +/* The mask used to clear the ALT_SDMMC_STAT_RESPONSE_INDEX register field value. */ +#define ALT_SDMMC_STAT_RESPONSE_INDEX_CLR_MSK 0xfffe07ff +/* The reset value of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */ +#define ALT_SDMMC_STAT_RESPONSE_INDEX_RESET 0x0 +/* Extracts the ALT_SDMMC_STAT_RESPONSE_INDEX field value from a register. */ +#define ALT_SDMMC_STAT_RESPONSE_INDEX_GET(value) (((value) & 0x0001f800) >> 11) +/* Produces a ALT_SDMMC_STAT_RESPONSE_INDEX register field value suitable for setting the register. */ +#define ALT_SDMMC_STAT_RESPONSE_INDEX_SET(value) (((value) << 11) & 0x0001f800) + +/* + * Field : FIFO Count - fifo_count + * + * FIFO count - Number of filled locations in FIFO + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_COUNT register field. */ +#define ALT_SDMMC_STAT_FIFO_COUNT_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_COUNT register field. */ +#define ALT_SDMMC_STAT_FIFO_COUNT_MSB 29 +/* The width in bits of the ALT_SDMMC_STAT_FIFO_COUNT register field. */ +#define ALT_SDMMC_STAT_FIFO_COUNT_WIDTH 13 +/* The mask used to set the ALT_SDMMC_STAT_FIFO_COUNT register field value. */ +#define ALT_SDMMC_STAT_FIFO_COUNT_SET_MSK 0x3ffe0000 +/* The mask used to clear the ALT_SDMMC_STAT_FIFO_COUNT register field value. */ +#define ALT_SDMMC_STAT_FIFO_COUNT_CLR_MSK 0xc001ffff +/* The reset value of the ALT_SDMMC_STAT_FIFO_COUNT register field. */ +#define ALT_SDMMC_STAT_FIFO_COUNT_RESET 0x0 +/* Extracts the ALT_SDMMC_STAT_FIFO_COUNT field value from a register. */ +#define ALT_SDMMC_STAT_FIFO_COUNT_GET(value) (((value) & 0x3ffe0000) >> 17) +/* Produces a ALT_SDMMC_STAT_FIFO_COUNT register field value suitable for setting the register. */ +#define ALT_SDMMC_STAT_FIFO_COUNT_SET(value) (((value) << 17) & 0x3ffe0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_STAT. + */ +struct ALT_SDMMC_STAT_s +{ + const uint32_t fifo_rx_watermark : 1; /* FIFO Rx Watermark */ + const uint32_t fifo_tx_watermark : 1; /* FIFO Tx Watermark */ + const uint32_t fifo_empty : 1; /* FIFO Empty */ + const uint32_t fifo_full : 1; /* FIFO Full */ + const uint32_t command_fsm_states : 4; /* Command FSM States */ + const uint32_t data_3_status : 1; /* Data 3 Status */ + const uint32_t data_busy : 1; /* Data Busy */ + const uint32_t data_state_mc_busy : 1; /* Data State MC Busy */ + const uint32_t response_index : 6; /* Response Index */ + const uint32_t fifo_count : 13; /* FIFO Count */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_STAT. */ +typedef volatile struct ALT_SDMMC_STAT_s ALT_SDMMC_STAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_STAT register from the beginning of the component. */ +#define ALT_SDMMC_STAT_OFST 0x48 + +/* + * Register : FIFO Threshold Watermark Register - fifoth + * + * DMA and FIFO Control Fields. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------ + * [11:0] | RW | 0x0 | Tx WMark + * [15:12] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x3ff | Rx WMark + * [30:28] | RW | 0x0 | DMA Multiple Transaction Size + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Tx WMark - tx_wmark + * + * FIFO threshold watermark level when transmitting data to card. When FIFO data + * count is less than or equal to this number, DMA/FIFO request is raised. If + * Interrupt is enabled, then interrupt occurs. During end of packet, request or + * interrupt is generated, regardless of threshold programming. In non-DMA mode, + * when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is + * generated instead of DMA request. During end of packet, on last interrupt, host + * is responsible for filling FIFO with only required remaining bytes (not before + * FIFO is full or after CIU completes data transfers, because FIFO may not be + * empty). In DMA mode, at end of packet, if last transfer is less than burst size, + * DMA controller does single cycles until required bytes are transferred. 12 bits + * - 1 bit less than FIFO-count of status register, which is 13 bits. + * + * Limitation: TX_WMark >= 1; + * + * Recommended: FIFO_DEPTH/2 = 512; (means less than or equal to 512) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */ +#define ALT_SDMMC_FIFOTH_TX_WMARK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */ +#define ALT_SDMMC_FIFOTH_TX_WMARK_MSB 11 +/* The width in bits of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */ +#define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH 12 +/* The mask used to set the ALT_SDMMC_FIFOTH_TX_WMARK register field value. */ +#define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK 0x00000fff +/* The mask used to clear the ALT_SDMMC_FIFOTH_TX_WMARK register field value. */ +#define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK 0xfffff000 +/* The reset value of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */ +#define ALT_SDMMC_FIFOTH_TX_WMARK_RESET 0x0 +/* Extracts the ALT_SDMMC_FIFOTH_TX_WMARK field value from a register. */ +#define ALT_SDMMC_FIFOTH_TX_WMARK_GET(value) (((value) & 0x00000fff) >> 0) +/* Produces a ALT_SDMMC_FIFOTH_TX_WMARK register field value suitable for setting the register. */ +#define ALT_SDMMC_FIFOTH_TX_WMARK_SET(value) (((value) << 0) & 0x00000fff) + +/* + * Field : Rx WMark - rx_wmark + * + * FIFO threshold watermark level when receiving data to card. When FIFO data count + * reaches greater than this number, DMA/FIFO request is raised. During end of + * packet, request is generated regardless of threshold programming in order to + * complete any remaining data. In non-DMA mode, when receiver FIFO threshold + * (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. + * During end of packet, interrupt is not generated if threshold programming is + * larger than any remaining data. It is responsibility of host to read remaining + * bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, + * even if remaining bytes are less than threshold, DMA request does single + * transfers to flush out any remaining bytes before Data Transfer Done interrupt + * is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 + * bits. + * + * Limitation: RX_WMark <= 1022 + * + * Recommended: 511; means greater than (FIFO_DEPTH/2) - 1) + * + * NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at + * the end of packet, even if remaining bytes are less than threshold. In this + * case, there will be some data left in the FIFO. It is the responsibility of the + * application to reset the FIFO after the CCS timeout. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */ +#define ALT_SDMMC_FIFOTH_RX_WMARK_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */ +#define ALT_SDMMC_FIFOTH_RX_WMARK_MSB 27 +/* The width in bits of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */ +#define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH 12 +/* The mask used to set the ALT_SDMMC_FIFOTH_RX_WMARK register field value. */ +#define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_SDMMC_FIFOTH_RX_WMARK register field value. */ +#define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK 0xf000ffff +/* The reset value of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */ +#define ALT_SDMMC_FIFOTH_RX_WMARK_RESET 0x3ff +/* Extracts the ALT_SDMMC_FIFOTH_RX_WMARK field value from a register. */ +#define ALT_SDMMC_FIFOTH_RX_WMARK_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_SDMMC_FIFOTH_RX_WMARK register field value suitable for setting the register. */ +#define ALT_SDMMC_FIFOTH_RX_WMARK_SET(value) (((value) << 16) & 0x0fff0000) + +/* + * Field : DMA Multiple Transaction Size - dw_dma_multiple_transaction_size + * + * Burst size of multiple transaction; should be programmed same as DMA controller + * multiple-transaction-size SRC/DEST_MSIZE. + * + * The units for transfers is 32 bits. A single transfer would be signalled based + * on this value. Value should be sub-multiple of 512. Allowed combinations for + * MSize and TX_WMark. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------------|:------|:---------------------------- + * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 | 0x0 | Msize 1 and TX_WMARK 1-1023 + * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 | 0x1 | Msize 4 and TX_WMARK 256 + * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 | 0x2 | Msize 8 and TX_WMARK 128 + * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 | 0x3 | Msize 16 and TX_WMARK 64 + * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 | 0x5 | Msize 1 and RX_WMARK 512 + * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 | 0x6 | Msize 4 and RX_WMARK 128 + * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 | 0x7 | Msize 8 and RX_WMARK 64 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE + * + * Msize 1 and TX_WMARK 1-1023 + */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 0x0 +/* + * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE + * + * Msize 4 and TX_WMARK 256 + */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 0x1 +/* + * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE + * + * Msize 8 and TX_WMARK 128 + */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 0x2 +/* + * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE + * + * Msize 16 and TX_WMARK 64 + */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 0x3 +/* + * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE + * + * Msize 1 and RX_WMARK 512 + */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 0x5 +/* + * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE + * + * Msize 4 and RX_WMARK 128 + */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 0x6 +/* + * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE + * + * Msize 8 and RX_WMARK 64 + */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_MSB 30 +/* The width in bits of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_WIDTH 3 +/* The mask used to set the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value. */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET_MSK 0x70000000 +/* The mask used to clear the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value. */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_CLR_MSK 0x8fffffff +/* The reset value of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_RESET 0x0 +/* Extracts the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE field value from a register. */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_GET(value) (((value) & 0x70000000) >> 28) +/* Produces a ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value suitable for setting the register. */ +#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET(value) (((value) << 28) & 0x70000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_FIFOTH. + */ +struct ALT_SDMMC_FIFOTH_s +{ + uint32_t tx_wmark : 12; /* Tx WMark */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t rx_wmark : 12; /* Rx WMark */ + uint32_t dw_dma_multiple_transaction_size : 3; /* DMA Multiple Transaction Size */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_FIFOTH. */ +typedef volatile struct ALT_SDMMC_FIFOTH_s ALT_SDMMC_FIFOTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_FIFOTH register from the beginning of the component. */ +#define ALT_SDMMC_FIFOTH_OFST 0x4c + +/* + * Register : Card Detect Register - cdetect + * + * Determines if card is present. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | R | 0x1 | Card Detect + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Card Detect - card_detect_n + * + * Value on sdmmc_cd_i input port. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------ + * ALT_SDMMC_CDETECT_CARD_DETECT_N_E_NOTDETECTED | 0x1 | Card not Detected + * ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED | 0x0 | Card Detected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CDETECT_CARD_DETECT_N + * + * Card not Detected + */ +#define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_NOTDETECTED 0x1 +/* + * Enumerated value for register field ALT_SDMMC_CDETECT_CARD_DETECT_N + * + * Card Detected + */ +#define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */ +#define ALT_SDMMC_CDETECT_CARD_DETECT_N_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */ +#define ALT_SDMMC_CDETECT_CARD_DETECT_N_MSB 0 +/* The width in bits of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */ +#define ALT_SDMMC_CDETECT_CARD_DETECT_N_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CDETECT_CARD_DETECT_N register field value. */ +#define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_CDETECT_CARD_DETECT_N register field value. */ +#define ALT_SDMMC_CDETECT_CARD_DETECT_N_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */ +#define ALT_SDMMC_CDETECT_CARD_DETECT_N_RESET 0x1 +/* Extracts the ALT_SDMMC_CDETECT_CARD_DETECT_N field value from a register. */ +#define ALT_SDMMC_CDETECT_CARD_DETECT_N_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_CDETECT_CARD_DETECT_N register field value suitable for setting the register. */ +#define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_CDETECT. + */ +struct ALT_SDMMC_CDETECT_s +{ + const uint32_t card_detect_n : 1; /* Card Detect */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_CDETECT. */ +typedef volatile struct ALT_SDMMC_CDETECT_s ALT_SDMMC_CDETECT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_CDETECT register from the beginning of the component. */ +#define ALT_SDMMC_CDETECT_OFST 0x50 + +/* + * Register : Write Protect Register - wrtprt + * + * See Field Description. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [0] | R | 0x1 | Write Protect + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write Protect - write_protect + * + * Value on sdmmc_wp_i input port. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------- + * ALT_SDMMC_WRTPRT_WR_PROTECT_E_END | 0x1 | Write Protect Enabled + * ALT_SDMMC_WRTPRT_WR_PROTECT_E_DISD | 0x0 | Write Protect Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_WRTPRT_WR_PROTECT + * + * Write Protect Enabled + */ +#define ALT_SDMMC_WRTPRT_WR_PROTECT_E_END 0x1 +/* + * Enumerated value for register field ALT_SDMMC_WRTPRT_WR_PROTECT + * + * Write Protect Disabled + */ +#define ALT_SDMMC_WRTPRT_WR_PROTECT_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */ +#define ALT_SDMMC_WRTPRT_WR_PROTECT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */ +#define ALT_SDMMC_WRTPRT_WR_PROTECT_MSB 0 +/* The width in bits of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */ +#define ALT_SDMMC_WRTPRT_WR_PROTECT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_WRTPRT_WR_PROTECT register field value. */ +#define ALT_SDMMC_WRTPRT_WR_PROTECT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_WRTPRT_WR_PROTECT register field value. */ +#define ALT_SDMMC_WRTPRT_WR_PROTECT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */ +#define ALT_SDMMC_WRTPRT_WR_PROTECT_RESET 0x1 +/* Extracts the ALT_SDMMC_WRTPRT_WR_PROTECT field value from a register. */ +#define ALT_SDMMC_WRTPRT_WR_PROTECT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_WRTPRT_WR_PROTECT register field value suitable for setting the register. */ +#define ALT_SDMMC_WRTPRT_WR_PROTECT_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_WRTPRT. + */ +struct ALT_SDMMC_WRTPRT_s +{ + const uint32_t write_protect : 1; /* Write Protect */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_WRTPRT. */ +typedef volatile struct ALT_SDMMC_WRTPRT_s ALT_SDMMC_WRTPRT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_WRTPRT register from the beginning of the component. */ +#define ALT_SDMMC_WRTPRT_OFST 0x54 + +/* + * Register : Transferred CIU Card Byte Count Register - tcbcnt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [31:0] | R | 0x0 | Trans Card Byte Count + * + */ +/* + * Field : Trans Card Byte Count - trans_card_byte_count + * + * Number of bytes transferred by CIU unit to card. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */ +#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */ +#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MSB 31 +/* The width in bits of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */ +#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_WIDTH 32 +/* The mask used to set the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value. */ +#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value. */ +#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */ +#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_RESET 0x0 +/* Extracts the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT field value from a register. */ +#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value suitable for setting the register. */ +#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_TCBCNT. + */ +struct ALT_SDMMC_TCBCNT_s +{ + const uint32_t trans_card_byte_count : 32; /* Trans Card Byte Count */ +}; + +/* The typedef declaration for register ALT_SDMMC_TCBCNT. */ +typedef volatile struct ALT_SDMMC_TCBCNT_s ALT_SDMMC_TCBCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_TCBCNT register from the beginning of the component. */ +#define ALT_SDMMC_TCBCNT_OFST 0x5c + +/* + * Register : Transferred Host to BIU-FIFO Byte Count Register - tbbcnt + * + * Tracks number of bytes transferred between Host and FIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [31:0] | R | 0x0 | Trans FIFO Byte Count + * + */ +/* + * Field : Trans FIFO Byte Count - trans_fifo_byte_count + * + * Number of bytes transferred between Host/DMA memory and BIU FIFO. In 32-bit AMBA + * data-bus-width modes, register should be accessed in full to avoid read- + * coherency problems. Both TCBCNT and TBBCNT share same coherency register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */ +#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */ +#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MSB 31 +/* The width in bits of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */ +#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_WIDTH 32 +/* The mask used to set the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value. */ +#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value. */ +#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */ +#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_RESET 0x0 +/* Extracts the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT field value from a register. */ +#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value suitable for setting the register. */ +#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_TBBCNT. + */ +struct ALT_SDMMC_TBBCNT_s +{ + const uint32_t trans_fifo_byte_count : 32; /* Trans FIFO Byte Count */ +}; + +/* The typedef declaration for register ALT_SDMMC_TBBCNT. */ +typedef volatile struct ALT_SDMMC_TBBCNT_s ALT_SDMMC_TBBCNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_TBBCNT register from the beginning of the component. */ +#define ALT_SDMMC_TBBCNT_OFST 0x60 + +/* + * Register : Debounce Count Register - debnce + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:---------|:--------------- + * [23:0] | RW | 0xffffff | Debounce Count + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debounce Count - debounce_count + * + * Number of host clocks l4_mp_clk used by debounce filter logic; typical debounce + * time is 5-25 ms. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */ +#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */ +#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_MSB 23 +/* The width in bits of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */ +#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_WIDTH 24 +/* The mask used to set the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value. */ +#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET_MSK 0x00ffffff +/* The mask used to clear the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value. */ +#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_CLR_MSK 0xff000000 +/* The reset value of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */ +#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_RESET 0xffffff +/* Extracts the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT field value from a register. */ +#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_GET(value) (((value) & 0x00ffffff) >> 0) +/* Produces a ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value suitable for setting the register. */ +#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET(value) (((value) << 0) & 0x00ffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_DEBNCE. + */ +struct ALT_SDMMC_DEBNCE_s +{ + uint32_t debounce_count : 24; /* Debounce Count */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_DEBNCE. */ +typedef volatile struct ALT_SDMMC_DEBNCE_s ALT_SDMMC_DEBNCE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_DEBNCE register from the beginning of the component. */ +#define ALT_SDMMC_DEBNCE_OFST 0x64 + +/* + * Register : User ID Register - usrid + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:----------|:------------ + * [31:0] | RW | 0x7967797 | User ID + * + */ +/* + * Field : User ID - usr_id + * + * User identification field; Value is 0x7967797. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_USRID_USR_ID register field. */ +#define ALT_SDMMC_USRID_USR_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_USRID_USR_ID register field. */ +#define ALT_SDMMC_USRID_USR_ID_MSB 31 +/* The width in bits of the ALT_SDMMC_USRID_USR_ID register field. */ +#define ALT_SDMMC_USRID_USR_ID_WIDTH 32 +/* The mask used to set the ALT_SDMMC_USRID_USR_ID register field value. */ +#define ALT_SDMMC_USRID_USR_ID_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_USRID_USR_ID register field value. */ +#define ALT_SDMMC_USRID_USR_ID_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_USRID_USR_ID register field. */ +#define ALT_SDMMC_USRID_USR_ID_RESET 0x7967797 +/* Extracts the ALT_SDMMC_USRID_USR_ID field value from a register. */ +#define ALT_SDMMC_USRID_USR_ID_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_USRID_USR_ID register field value suitable for setting the register. */ +#define ALT_SDMMC_USRID_USR_ID_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_USRID. + */ +struct ALT_SDMMC_USRID_s +{ + uint32_t usr_id : 32; /* User ID */ +}; + +/* The typedef declaration for register ALT_SDMMC_USRID. */ +typedef volatile struct ALT_SDMMC_USRID_s ALT_SDMMC_USRID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_USRID register from the beginning of the component. */ +#define ALT_SDMMC_USRID_OFST 0x68 + +/* + * Register : Version ID Register - verid + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------ + * [31:0] | R | 0x5342240a | Version ID + * + */ +/* + * Field : Version ID - ver_id + * + * Synopsys version id. Current value is 32'h5342240a + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_VERID_VER_ID register field. */ +#define ALT_SDMMC_VERID_VER_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_VERID_VER_ID register field. */ +#define ALT_SDMMC_VERID_VER_ID_MSB 31 +/* The width in bits of the ALT_SDMMC_VERID_VER_ID register field. */ +#define ALT_SDMMC_VERID_VER_ID_WIDTH 32 +/* The mask used to set the ALT_SDMMC_VERID_VER_ID register field value. */ +#define ALT_SDMMC_VERID_VER_ID_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_VERID_VER_ID register field value. */ +#define ALT_SDMMC_VERID_VER_ID_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_VERID_VER_ID register field. */ +#define ALT_SDMMC_VERID_VER_ID_RESET 0x5342240a +/* Extracts the ALT_SDMMC_VERID_VER_ID field value from a register. */ +#define ALT_SDMMC_VERID_VER_ID_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_VERID_VER_ID register field value suitable for setting the register. */ +#define ALT_SDMMC_VERID_VER_ID_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_VERID. + */ +struct ALT_SDMMC_VERID_s +{ + const uint32_t ver_id : 32; /* Version ID */ +}; + +/* The typedef declaration for register ALT_SDMMC_VERID. */ +typedef volatile struct ALT_SDMMC_VERID_s ALT_SDMMC_VERID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_VERID register from the beginning of the component. */ +#define ALT_SDMMC_VERID_OFST 0x6c + +/* + * Register : Hardware Configuration Register - hcon + * + * Hardware configurations registers. Register can be used to develop + * configuration-independent software drivers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | R | 0x1 | Card Type + * [5:1] | R | 0x0 | Number of Cards + * [6] | R | 0x0 | Slave Bus Type + * [9:7] | R | 0x1 | Slave Bus Data Width + * [15:10] | R | 0xc | Slave Bus Address Width + * [17:16] | R | 0x0 | DMA Interface Type + * [20:18] | R | 0x1 | Generic DMA Data Width + * [21] | R | 0x0 | FIFO RAM Location + * [22] | R | 0x1 | Implement Hold Register + * [23] | R | 0x1 | Clock False Path + * [25:24] | R | 0x0 | Number of Clock Dividers + * [26] | R | 0x0 | Area Optimized + * [31:27] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Card Type - ct + * + * Supported card types + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------- + * ALT_SDMMC_HCON_CT_E_SDMMC | 0x1 | Card Type SD/MMC + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_CT + * + * Card Type SD/MMC + */ +#define ALT_SDMMC_HCON_CT_E_SDMMC 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_CT register field. */ +#define ALT_SDMMC_HCON_CT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_CT register field. */ +#define ALT_SDMMC_HCON_CT_MSB 0 +/* The width in bits of the ALT_SDMMC_HCON_CT register field. */ +#define ALT_SDMMC_HCON_CT_WIDTH 1 +/* The mask used to set the ALT_SDMMC_HCON_CT register field value. */ +#define ALT_SDMMC_HCON_CT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_HCON_CT register field value. */ +#define ALT_SDMMC_HCON_CT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_HCON_CT register field. */ +#define ALT_SDMMC_HCON_CT_RESET 0x1 +/* Extracts the ALT_SDMMC_HCON_CT field value from a register. */ +#define ALT_SDMMC_HCON_CT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_HCON_CT register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_CT_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Number of Cards - nc + * + * Maximum number of cards less one + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------ + * ALT_SDMMC_HCON_NC_E_NUMCARD | 0x0 | 1 Card + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_NC + * + * 1 Card + */ +#define ALT_SDMMC_HCON_NC_E_NUMCARD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_NC register field. */ +#define ALT_SDMMC_HCON_NC_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_NC register field. */ +#define ALT_SDMMC_HCON_NC_MSB 5 +/* The width in bits of the ALT_SDMMC_HCON_NC register field. */ +#define ALT_SDMMC_HCON_NC_WIDTH 5 +/* The mask used to set the ALT_SDMMC_HCON_NC register field value. */ +#define ALT_SDMMC_HCON_NC_SET_MSK 0x0000003e +/* The mask used to clear the ALT_SDMMC_HCON_NC register field value. */ +#define ALT_SDMMC_HCON_NC_CLR_MSK 0xffffffc1 +/* The reset value of the ALT_SDMMC_HCON_NC register field. */ +#define ALT_SDMMC_HCON_NC_RESET 0x0 +/* Extracts the ALT_SDMMC_HCON_NC field value from a register. */ +#define ALT_SDMMC_HCON_NC_GET(value) (((value) & 0x0000003e) >> 1) +/* Produces a ALT_SDMMC_HCON_NC register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_NC_SET(value) (((value) << 1) & 0x0000003e) + +/* + * Field : Slave Bus Type - hbus + * + * Slave bus type. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------ + * ALT_SDMMC_HCON_HBUS_E_APB | 0x0 | APB Bus + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_HBUS + * + * APB Bus + */ +#define ALT_SDMMC_HCON_HBUS_E_APB 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HBUS register field. */ +#define ALT_SDMMC_HCON_HBUS_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HBUS register field. */ +#define ALT_SDMMC_HCON_HBUS_MSB 6 +/* The width in bits of the ALT_SDMMC_HCON_HBUS register field. */ +#define ALT_SDMMC_HCON_HBUS_WIDTH 1 +/* The mask used to set the ALT_SDMMC_HCON_HBUS register field value. */ +#define ALT_SDMMC_HCON_HBUS_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SDMMC_HCON_HBUS register field value. */ +#define ALT_SDMMC_HCON_HBUS_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SDMMC_HCON_HBUS register field. */ +#define ALT_SDMMC_HCON_HBUS_RESET 0x0 +/* Extracts the ALT_SDMMC_HCON_HBUS field value from a register. */ +#define ALT_SDMMC_HCON_HBUS_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SDMMC_HCON_HBUS register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_HBUS_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Slave Bus Data Width - hdatawidth + * + * Slave bus data width + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS | 0x1 | Width 32 Bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_HDATAWIDTH + * + * Width 32 Bits + */ +#define ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HDATAWIDTH register field. */ +#define ALT_SDMMC_HCON_HDATAWIDTH_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HDATAWIDTH register field. */ +#define ALT_SDMMC_HCON_HDATAWIDTH_MSB 9 +/* The width in bits of the ALT_SDMMC_HCON_HDATAWIDTH register field. */ +#define ALT_SDMMC_HCON_HDATAWIDTH_WIDTH 3 +/* The mask used to set the ALT_SDMMC_HCON_HDATAWIDTH register field value. */ +#define ALT_SDMMC_HCON_HDATAWIDTH_SET_MSK 0x00000380 +/* The mask used to clear the ALT_SDMMC_HCON_HDATAWIDTH register field value. */ +#define ALT_SDMMC_HCON_HDATAWIDTH_CLR_MSK 0xfffffc7f +/* The reset value of the ALT_SDMMC_HCON_HDATAWIDTH register field. */ +#define ALT_SDMMC_HCON_HDATAWIDTH_RESET 0x1 +/* Extracts the ALT_SDMMC_HCON_HDATAWIDTH field value from a register. */ +#define ALT_SDMMC_HCON_HDATAWIDTH_GET(value) (((value) & 0x00000380) >> 7) +/* Produces a ALT_SDMMC_HCON_HDATAWIDTH register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_HDATAWIDTH_SET(value) (((value) << 7) & 0x00000380) + +/* + * Field : Slave Bus Address Width - haddrwidth + * + * Slave bus address width less one + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS | 0xc | Width 13 Bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_HADDRWIDTH + * + * Width 13 Bits + */ +#define ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS 0xc + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HADDRWIDTH register field. */ +#define ALT_SDMMC_HCON_HADDRWIDTH_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HADDRWIDTH register field. */ +#define ALT_SDMMC_HCON_HADDRWIDTH_MSB 15 +/* The width in bits of the ALT_SDMMC_HCON_HADDRWIDTH register field. */ +#define ALT_SDMMC_HCON_HADDRWIDTH_WIDTH 6 +/* The mask used to set the ALT_SDMMC_HCON_HADDRWIDTH register field value. */ +#define ALT_SDMMC_HCON_HADDRWIDTH_SET_MSK 0x0000fc00 +/* The mask used to clear the ALT_SDMMC_HCON_HADDRWIDTH register field value. */ +#define ALT_SDMMC_HCON_HADDRWIDTH_CLR_MSK 0xffff03ff +/* The reset value of the ALT_SDMMC_HCON_HADDRWIDTH register field. */ +#define ALT_SDMMC_HCON_HADDRWIDTH_RESET 0xc +/* Extracts the ALT_SDMMC_HCON_HADDRWIDTH field value from a register. */ +#define ALT_SDMMC_HCON_HADDRWIDTH_GET(value) (((value) & 0x0000fc00) >> 10) +/* Produces a ALT_SDMMC_HCON_HADDRWIDTH register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_HADDRWIDTH_SET(value) (((value) << 10) & 0x0000fc00) + +/* + * Field : DMA Interface Type - dmaintf + * + * DMA interface type + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------- + * ALT_SDMMC_HCON_DMAINTF_E_NONE | 0x0 | No External DMA Controller Interface (SD/MMC has + * : | | its own internal DMA Controller + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_DMAINTF + * + * No External DMA Controller Interface (SD/MMC has its own internal DMA Controller + */ +#define ALT_SDMMC_HCON_DMAINTF_E_NONE 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_DMAINTF register field. */ +#define ALT_SDMMC_HCON_DMAINTF_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_DMAINTF register field. */ +#define ALT_SDMMC_HCON_DMAINTF_MSB 17 +/* The width in bits of the ALT_SDMMC_HCON_DMAINTF register field. */ +#define ALT_SDMMC_HCON_DMAINTF_WIDTH 2 +/* The mask used to set the ALT_SDMMC_HCON_DMAINTF register field value. */ +#define ALT_SDMMC_HCON_DMAINTF_SET_MSK 0x00030000 +/* The mask used to clear the ALT_SDMMC_HCON_DMAINTF register field value. */ +#define ALT_SDMMC_HCON_DMAINTF_CLR_MSK 0xfffcffff +/* The reset value of the ALT_SDMMC_HCON_DMAINTF register field. */ +#define ALT_SDMMC_HCON_DMAINTF_RESET 0x0 +/* Extracts the ALT_SDMMC_HCON_DMAINTF field value from a register. */ +#define ALT_SDMMC_HCON_DMAINTF_GET(value) (((value) & 0x00030000) >> 16) +/* Produces a ALT_SDMMC_HCON_DMAINTF register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_DMAINTF_SET(value) (((value) << 16) & 0x00030000) + +/* + * Field : Generic DMA Data Width - dmadatawidth + * + * Encodes bit width of external DMA controller interface. Doesn't apply to the + * SD/MMC because it has no external DMA controller interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS | 0x1 | 32-bits wide + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_DMADATAWIDTH + * + * 32-bits wide + */ +#define ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */ +#define ALT_SDMMC_HCON_DMADATAWIDTH_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */ +#define ALT_SDMMC_HCON_DMADATAWIDTH_MSB 20 +/* The width in bits of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */ +#define ALT_SDMMC_HCON_DMADATAWIDTH_WIDTH 3 +/* The mask used to set the ALT_SDMMC_HCON_DMADATAWIDTH register field value. */ +#define ALT_SDMMC_HCON_DMADATAWIDTH_SET_MSK 0x001c0000 +/* The mask used to clear the ALT_SDMMC_HCON_DMADATAWIDTH register field value. */ +#define ALT_SDMMC_HCON_DMADATAWIDTH_CLR_MSK 0xffe3ffff +/* The reset value of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */ +#define ALT_SDMMC_HCON_DMADATAWIDTH_RESET 0x1 +/* Extracts the ALT_SDMMC_HCON_DMADATAWIDTH field value from a register. */ +#define ALT_SDMMC_HCON_DMADATAWIDTH_GET(value) (((value) & 0x001c0000) >> 18) +/* Produces a ALT_SDMMC_HCON_DMADATAWIDTH register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_DMADATAWIDTH_SET(value) (((value) << 18) & 0x001c0000) + +/* + * Field : FIFO RAM Location - rios + * + * FIFO RAM location + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------- + * ALT_SDMMC_HCON_RIOS_E_OUTSIDE | 0x0 | FIFO RAM Outside IP Core + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_RIOS + * + * FIFO RAM Outside IP Core + */ +#define ALT_SDMMC_HCON_RIOS_E_OUTSIDE 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_RIOS register field. */ +#define ALT_SDMMC_HCON_RIOS_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_RIOS register field. */ +#define ALT_SDMMC_HCON_RIOS_MSB 21 +/* The width in bits of the ALT_SDMMC_HCON_RIOS register field. */ +#define ALT_SDMMC_HCON_RIOS_WIDTH 1 +/* The mask used to set the ALT_SDMMC_HCON_RIOS register field value. */ +#define ALT_SDMMC_HCON_RIOS_SET_MSK 0x00200000 +/* The mask used to clear the ALT_SDMMC_HCON_RIOS register field value. */ +#define ALT_SDMMC_HCON_RIOS_CLR_MSK 0xffdfffff +/* The reset value of the ALT_SDMMC_HCON_RIOS register field. */ +#define ALT_SDMMC_HCON_RIOS_RESET 0x0 +/* Extracts the ALT_SDMMC_HCON_RIOS field value from a register. */ +#define ALT_SDMMC_HCON_RIOS_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_SDMMC_HCON_RIOS register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_RIOS_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Implement Hold Register - ihr + * + * Implement hold register + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------- + * ALT_SDMMC_HCON_IHR_E_IMPLEMENTED | 0x1 | Implements Hold Register + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_IHR + * + * Implements Hold Register + */ +#define ALT_SDMMC_HCON_IHR_E_IMPLEMENTED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_IHR register field. */ +#define ALT_SDMMC_HCON_IHR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_IHR register field. */ +#define ALT_SDMMC_HCON_IHR_MSB 22 +/* The width in bits of the ALT_SDMMC_HCON_IHR register field. */ +#define ALT_SDMMC_HCON_IHR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_HCON_IHR register field value. */ +#define ALT_SDMMC_HCON_IHR_SET_MSK 0x00400000 +/* The mask used to clear the ALT_SDMMC_HCON_IHR register field value. */ +#define ALT_SDMMC_HCON_IHR_CLR_MSK 0xffbfffff +/* The reset value of the ALT_SDMMC_HCON_IHR register field. */ +#define ALT_SDMMC_HCON_IHR_RESET 0x1 +/* Extracts the ALT_SDMMC_HCON_IHR field value from a register. */ +#define ALT_SDMMC_HCON_IHR_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_SDMMC_HCON_IHR register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_IHR_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : Clock False Path - scfp + * + * Clock False Path + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:--------------------- + * ALT_SDMMC_HCON_SCFP_E_SET | 0x1 | Clock False Path Set + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_SCFP + * + * Clock False Path Set + */ +#define ALT_SDMMC_HCON_SCFP_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_SCFP register field. */ +#define ALT_SDMMC_HCON_SCFP_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_SCFP register field. */ +#define ALT_SDMMC_HCON_SCFP_MSB 23 +/* The width in bits of the ALT_SDMMC_HCON_SCFP register field. */ +#define ALT_SDMMC_HCON_SCFP_WIDTH 1 +/* The mask used to set the ALT_SDMMC_HCON_SCFP register field value. */ +#define ALT_SDMMC_HCON_SCFP_SET_MSK 0x00800000 +/* The mask used to clear the ALT_SDMMC_HCON_SCFP register field value. */ +#define ALT_SDMMC_HCON_SCFP_CLR_MSK 0xff7fffff +/* The reset value of the ALT_SDMMC_HCON_SCFP register field. */ +#define ALT_SDMMC_HCON_SCFP_RESET 0x1 +/* Extracts the ALT_SDMMC_HCON_SCFP field value from a register. */ +#define ALT_SDMMC_HCON_SCFP_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_SDMMC_HCON_SCFP register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_SCFP_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Number of Clock Dividers - ncd + * + * Number of clock dividers less one + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------ + * ALT_SDMMC_HCON_NCD_E_ONEDIV | 0x0 | One Clock Divider + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_NCD + * + * One Clock Divider + */ +#define ALT_SDMMC_HCON_NCD_E_ONEDIV 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_NCD register field. */ +#define ALT_SDMMC_HCON_NCD_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_NCD register field. */ +#define ALT_SDMMC_HCON_NCD_MSB 25 +/* The width in bits of the ALT_SDMMC_HCON_NCD register field. */ +#define ALT_SDMMC_HCON_NCD_WIDTH 2 +/* The mask used to set the ALT_SDMMC_HCON_NCD register field value. */ +#define ALT_SDMMC_HCON_NCD_SET_MSK 0x03000000 +/* The mask used to clear the ALT_SDMMC_HCON_NCD register field value. */ +#define ALT_SDMMC_HCON_NCD_CLR_MSK 0xfcffffff +/* The reset value of the ALT_SDMMC_HCON_NCD register field. */ +#define ALT_SDMMC_HCON_NCD_RESET 0x0 +/* Extracts the ALT_SDMMC_HCON_NCD field value from a register. */ +#define ALT_SDMMC_HCON_NCD_GET(value) (((value) & 0x03000000) >> 24) +/* Produces a ALT_SDMMC_HCON_NCD register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_NCD_SET(value) (((value) << 24) & 0x03000000) + +/* + * Field : Area Optimized - aro + * + * Area optimized + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------- + * ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA | 0x0 | Not Optimized For Area + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_HCON_ARO + * + * Not Optimized For Area + */ +#define ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_ARO register field. */ +#define ALT_SDMMC_HCON_ARO_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_ARO register field. */ +#define ALT_SDMMC_HCON_ARO_MSB 26 +/* The width in bits of the ALT_SDMMC_HCON_ARO register field. */ +#define ALT_SDMMC_HCON_ARO_WIDTH 1 +/* The mask used to set the ALT_SDMMC_HCON_ARO register field value. */ +#define ALT_SDMMC_HCON_ARO_SET_MSK 0x04000000 +/* The mask used to clear the ALT_SDMMC_HCON_ARO register field value. */ +#define ALT_SDMMC_HCON_ARO_CLR_MSK 0xfbffffff +/* The reset value of the ALT_SDMMC_HCON_ARO register field. */ +#define ALT_SDMMC_HCON_ARO_RESET 0x0 +/* Extracts the ALT_SDMMC_HCON_ARO field value from a register. */ +#define ALT_SDMMC_HCON_ARO_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_SDMMC_HCON_ARO register field value suitable for setting the register. */ +#define ALT_SDMMC_HCON_ARO_SET(value) (((value) << 26) & 0x04000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_HCON. + */ +struct ALT_SDMMC_HCON_s +{ + const uint32_t ct : 1; /* Card Type */ + const uint32_t nc : 5; /* Number of Cards */ + const uint32_t hbus : 1; /* Slave Bus Type */ + const uint32_t hdatawidth : 3; /* Slave Bus Data Width */ + const uint32_t haddrwidth : 6; /* Slave Bus Address Width */ + const uint32_t dmaintf : 2; /* DMA Interface Type */ + const uint32_t dmadatawidth : 3; /* Generic DMA Data Width */ + const uint32_t rios : 1; /* FIFO RAM Location */ + const uint32_t ihr : 1; /* Implement Hold Register */ + const uint32_t scfp : 1; /* Clock False Path */ + const uint32_t ncd : 2; /* Number of Clock Dividers */ + const uint32_t aro : 1; /* Area Optimized */ + uint32_t : 5; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_HCON. */ +typedef volatile struct ALT_SDMMC_HCON_s ALT_SDMMC_HCON_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_HCON register from the beginning of the component. */ +#define ALT_SDMMC_HCON_OFST 0x70 + +/* + * Register : UHS-1 Register - uhs_reg + * + * UHS-1 Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------ + * [0] | RW | 0x0 | High Voltage Mode + * [15:1] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | DDR Mode + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : High Voltage Mode - volt_reg + * + * Determines the voltage fed to the buffers by an external voltage regulator. + * These bits function as the output of the host controller and are fed to an + * external voltage regulator. The voltage regulator must switch the voltage of the + * buffers of a particular card to either 3.3V or 1.8V, depending on the value + * programmed in the register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------- + * ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V | 0x0 | Buffers supplied with 3.3V Vdd + * ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V | 0x1 | Buffers supplied with 1.8V Vdd + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG + * + * Buffers supplied with 3.3V Vdd + */ +#define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V 0x0 +/* + * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG + * + * Buffers supplied with 1.8V Vdd + */ +#define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */ +#define ALT_SDMMC_UHS_REG_VOLT_REG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */ +#define ALT_SDMMC_UHS_REG_VOLT_REG_MSB 0 +/* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */ +#define ALT_SDMMC_UHS_REG_VOLT_REG_WIDTH 1 +/* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG register field value. */ +#define ALT_SDMMC_UHS_REG_VOLT_REG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG register field value. */ +#define ALT_SDMMC_UHS_REG_VOLT_REG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */ +#define ALT_SDMMC_UHS_REG_VOLT_REG_RESET 0x0 +/* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG field value from a register. */ +#define ALT_SDMMC_UHS_REG_VOLT_REG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_UHS_REG_VOLT_REG register field value suitable for setting the register. */ +#define ALT_SDMMC_UHS_REG_VOLT_REG_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : DDR Mode - ddr_reg + * + * Determines the voltage fed to the buffers by an external voltage regulator. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR | 0x0 | Non-DDR mode + * ALT_SDMMC_UHS_REG_DDR_REG_E_DDR | 0x1 | DDR mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG + * + * Non-DDR mode + */ +#define ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR 0x0 +/* + * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG + * + * DDR mode + */ +#define ALT_SDMMC_UHS_REG_DDR_REG_E_DDR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG register field. */ +#define ALT_SDMMC_UHS_REG_DDR_REG_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG register field. */ +#define ALT_SDMMC_UHS_REG_DDR_REG_MSB 16 +/* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG register field. */ +#define ALT_SDMMC_UHS_REG_DDR_REG_WIDTH 1 +/* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG register field value. */ +#define ALT_SDMMC_UHS_REG_DDR_REG_SET_MSK 0x00010000 +/* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG register field value. */ +#define ALT_SDMMC_UHS_REG_DDR_REG_CLR_MSK 0xfffeffff +/* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG register field. */ +#define ALT_SDMMC_UHS_REG_DDR_REG_RESET 0x0 +/* Extracts the ALT_SDMMC_UHS_REG_DDR_REG field value from a register. */ +#define ALT_SDMMC_UHS_REG_DDR_REG_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_SDMMC_UHS_REG_DDR_REG register field value suitable for setting the register. */ +#define ALT_SDMMC_UHS_REG_DDR_REG_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_UHS_REG. + */ +struct ALT_SDMMC_UHS_REG_s +{ + uint32_t volt_reg : 1; /* High Voltage Mode */ + uint32_t : 15; /* *UNDEFINED* */ + uint32_t ddr_reg : 1; /* DDR Mode */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_UHS_REG. */ +typedef volatile struct ALT_SDMMC_UHS_REG_s ALT_SDMMC_UHS_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_UHS_REG register from the beginning of the component. */ +#define ALT_SDMMC_UHS_REG_OFST 0x74 + +/* + * Register : Hardware Reset Register - rst_n + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x1 | Card Reset + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Card Reset - card_reset + * + * This bit causes the cards to enter pre-idle state, which requires it to be re- + * initialized. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_SDMMC_RST_N_CARD_RST_E_ASSERT | 0x1 | Active Mode + * ALT_SDMMC_RST_N_CARD_RST_E_DEASSERT | 0x0 | Not Active Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_RST_N_CARD_RST + * + * Active Mode + */ +#define ALT_SDMMC_RST_N_CARD_RST_E_ASSERT 0x1 +/* + * Enumerated value for register field ALT_SDMMC_RST_N_CARD_RST + * + * Not Active Mode + */ +#define ALT_SDMMC_RST_N_CARD_RST_E_DEASSERT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_RST_N_CARD_RST register field. */ +#define ALT_SDMMC_RST_N_CARD_RST_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_RST_N_CARD_RST register field. */ +#define ALT_SDMMC_RST_N_CARD_RST_MSB 0 +/* The width in bits of the ALT_SDMMC_RST_N_CARD_RST register field. */ +#define ALT_SDMMC_RST_N_CARD_RST_WIDTH 1 +/* The mask used to set the ALT_SDMMC_RST_N_CARD_RST register field value. */ +#define ALT_SDMMC_RST_N_CARD_RST_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_RST_N_CARD_RST register field value. */ +#define ALT_SDMMC_RST_N_CARD_RST_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_RST_N_CARD_RST register field. */ +#define ALT_SDMMC_RST_N_CARD_RST_RESET 0x1 +/* Extracts the ALT_SDMMC_RST_N_CARD_RST field value from a register. */ +#define ALT_SDMMC_RST_N_CARD_RST_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_RST_N_CARD_RST register field value suitable for setting the register. */ +#define ALT_SDMMC_RST_N_CARD_RST_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_RST_N. + */ +struct ALT_SDMMC_RST_N_s +{ + uint32_t card_reset : 1; /* Card Reset */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_RST_N. */ +typedef volatile struct ALT_SDMMC_RST_N_s ALT_SDMMC_RST_N_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_RST_N register from the beginning of the component. */ +#define ALT_SDMMC_RST_N_OFST 0x78 + +/* + * Register : Bus Mode Register - bmod + * + * Details different bus operating modes. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------- + * [0] | RW | 0x0 | Software Reset + * [1] | RW | 0x0 | Fixed Burst + * [6:2] | RW | 0x0 | Descriptor Skip Length + * [7] | RW | 0x0 | IDMAC Enable + * [10:8] | R | 0x0 | Programmable Burst Length + * [31:11] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Software Reset - swr + * + * This bit resets all internal registers of the DMA Controller. It is + * automatically cleared after 1 clock cycle. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------ + * ALT_SDMMC_BMOD_SWR_E_SFTRST | 0x1 | Resets DMA Internal Registers + * ALT_SDMMC_BMOD_SWR_E_NOSFTRST | 0x0 | No reset - default + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_BMOD_SWR + * + * Resets DMA Internal Registers + */ +#define ALT_SDMMC_BMOD_SWR_E_SFTRST 0x1 +/* + * Enumerated value for register field ALT_SDMMC_BMOD_SWR + * + * No reset - default + */ +#define ALT_SDMMC_BMOD_SWR_E_NOSFTRST 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_SWR register field. */ +#define ALT_SDMMC_BMOD_SWR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_SWR register field. */ +#define ALT_SDMMC_BMOD_SWR_MSB 0 +/* The width in bits of the ALT_SDMMC_BMOD_SWR register field. */ +#define ALT_SDMMC_BMOD_SWR_WIDTH 1 +/* The mask used to set the ALT_SDMMC_BMOD_SWR register field value. */ +#define ALT_SDMMC_BMOD_SWR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_BMOD_SWR register field value. */ +#define ALT_SDMMC_BMOD_SWR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_BMOD_SWR register field. */ +#define ALT_SDMMC_BMOD_SWR_RESET 0x0 +/* Extracts the ALT_SDMMC_BMOD_SWR field value from a register. */ +#define ALT_SDMMC_BMOD_SWR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_BMOD_SWR register field value suitable for setting the register. */ +#define ALT_SDMMC_BMOD_SWR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Fixed Burst - fb + * + * Controls whether the AHB Master interface performs fixed burst transfers or not. + * Will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst + * transfers. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:-------------------------- + * ALT_SDMMC_BMOD_FB_E_FIXEDBRST | 0x1 | AHB Master Fixed Burst + * ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST | 0x0 | Non Fixed Burst - default + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_BMOD_FB + * + * AHB Master Fixed Burst + */ +#define ALT_SDMMC_BMOD_FB_E_FIXEDBRST 0x1 +/* + * Enumerated value for register field ALT_SDMMC_BMOD_FB + * + * Non Fixed Burst - default + */ +#define ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_FB register field. */ +#define ALT_SDMMC_BMOD_FB_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_FB register field. */ +#define ALT_SDMMC_BMOD_FB_MSB 1 +/* The width in bits of the ALT_SDMMC_BMOD_FB register field. */ +#define ALT_SDMMC_BMOD_FB_WIDTH 1 +/* The mask used to set the ALT_SDMMC_BMOD_FB register field value. */ +#define ALT_SDMMC_BMOD_FB_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDMMC_BMOD_FB register field value. */ +#define ALT_SDMMC_BMOD_FB_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDMMC_BMOD_FB register field. */ +#define ALT_SDMMC_BMOD_FB_RESET 0x0 +/* Extracts the ALT_SDMMC_BMOD_FB field value from a register. */ +#define ALT_SDMMC_BMOD_FB_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDMMC_BMOD_FB register field value suitable for setting the register. */ +#define ALT_SDMMC_BMOD_FB_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Descriptor Skip Length - dsl + * + * Specifies the number of HWord/Word/Dword (depending on 16/32/64-bit bus) to skip + * between two unchained descriptors. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_DSL register field. */ +#define ALT_SDMMC_BMOD_DSL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_DSL register field. */ +#define ALT_SDMMC_BMOD_DSL_MSB 6 +/* The width in bits of the ALT_SDMMC_BMOD_DSL register field. */ +#define ALT_SDMMC_BMOD_DSL_WIDTH 5 +/* The mask used to set the ALT_SDMMC_BMOD_DSL register field value. */ +#define ALT_SDMMC_BMOD_DSL_SET_MSK 0x0000007c +/* The mask used to clear the ALT_SDMMC_BMOD_DSL register field value. */ +#define ALT_SDMMC_BMOD_DSL_CLR_MSK 0xffffff83 +/* The reset value of the ALT_SDMMC_BMOD_DSL register field. */ +#define ALT_SDMMC_BMOD_DSL_RESET 0x0 +/* Extracts the ALT_SDMMC_BMOD_DSL field value from a register. */ +#define ALT_SDMMC_BMOD_DSL_GET(value) (((value) & 0x0000007c) >> 2) +/* Produces a ALT_SDMMC_BMOD_DSL register field value suitable for setting the register. */ +#define ALT_SDMMC_BMOD_DSL_SET(value) (((value) << 2) & 0x0000007c) + +/* + * Field : IDMAC Enable - de + * + * Enables and Disables Internal DMA. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:-------------- + * ALT_SDMMC_BMOD_DE_E_END | 0x1 | IDMAC Enable + * ALT_SDMMC_BMOD_DE_E_DISD | 0x0 | IDMAC Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_BMOD_DE + * + * IDMAC Enable + */ +#define ALT_SDMMC_BMOD_DE_E_END 0x1 +/* + * Enumerated value for register field ALT_SDMMC_BMOD_DE + * + * IDMAC Disable + */ +#define ALT_SDMMC_BMOD_DE_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_DE register field. */ +#define ALT_SDMMC_BMOD_DE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_DE register field. */ +#define ALT_SDMMC_BMOD_DE_MSB 7 +/* The width in bits of the ALT_SDMMC_BMOD_DE register field. */ +#define ALT_SDMMC_BMOD_DE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_BMOD_DE register field value. */ +#define ALT_SDMMC_BMOD_DE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SDMMC_BMOD_DE register field value. */ +#define ALT_SDMMC_BMOD_DE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SDMMC_BMOD_DE register field. */ +#define ALT_SDMMC_BMOD_DE_RESET 0x0 +/* Extracts the ALT_SDMMC_BMOD_DE field value from a register. */ +#define ALT_SDMMC_BMOD_DE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SDMMC_BMOD_DE register field value suitable for setting the register. */ +#define ALT_SDMMC_BMOD_DE_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Programmable Burst Length - pbl + * + * These bits indicate the maximum number of beats to be performed in one IDMAC + * transaction. The IDMAC will always attempt to burst as specified in PBL each + * time it starts a Burst transfer on the host bus. This value is the mirror of + * MSIZE of FIFOTH register. In order to change this value, write the required + * value to FIFOTH register. This is an encode value as follows. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------- + * ALT_SDMMC_BMOD_PBL_E_TRANS1 | 0x0 | Transfer 1 + * ALT_SDMMC_BMOD_PBL_E_TRANS4 | 0x1 | Transfer 4 + * ALT_SDMMC_BMOD_PBL_E_TRANS8 | 0x2 | Transfer 8 + * ALT_SDMMC_BMOD_PBL_E_TRANS16 | 0x3 | Transfer 16 + * ALT_SDMMC_BMOD_PBL_E_TRANS32 | 0x4 | Transfer 32 + * ALT_SDMMC_BMOD_PBL_E_TRANS64 | 0x5 | Transfer 64 + * ALT_SDMMC_BMOD_PBL_E_TRANS128 | 0x6 | Transfer 128 + * ALT_SDMMC_BMOD_PBL_E_TRANS256 | 0x7 | Transfer 256 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_BMOD_PBL + * + * Transfer 1 + */ +#define ALT_SDMMC_BMOD_PBL_E_TRANS1 0x0 +/* + * Enumerated value for register field ALT_SDMMC_BMOD_PBL + * + * Transfer 4 + */ +#define ALT_SDMMC_BMOD_PBL_E_TRANS4 0x1 +/* + * Enumerated value for register field ALT_SDMMC_BMOD_PBL + * + * Transfer 8 + */ +#define ALT_SDMMC_BMOD_PBL_E_TRANS8 0x2 +/* + * Enumerated value for register field ALT_SDMMC_BMOD_PBL + * + * Transfer 16 + */ +#define ALT_SDMMC_BMOD_PBL_E_TRANS16 0x3 +/* + * Enumerated value for register field ALT_SDMMC_BMOD_PBL + * + * Transfer 32 + */ +#define ALT_SDMMC_BMOD_PBL_E_TRANS32 0x4 +/* + * Enumerated value for register field ALT_SDMMC_BMOD_PBL + * + * Transfer 64 + */ +#define ALT_SDMMC_BMOD_PBL_E_TRANS64 0x5 +/* + * Enumerated value for register field ALT_SDMMC_BMOD_PBL + * + * Transfer 128 + */ +#define ALT_SDMMC_BMOD_PBL_E_TRANS128 0x6 +/* + * Enumerated value for register field ALT_SDMMC_BMOD_PBL + * + * Transfer 256 + */ +#define ALT_SDMMC_BMOD_PBL_E_TRANS256 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_PBL register field. */ +#define ALT_SDMMC_BMOD_PBL_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_PBL register field. */ +#define ALT_SDMMC_BMOD_PBL_MSB 10 +/* The width in bits of the ALT_SDMMC_BMOD_PBL register field. */ +#define ALT_SDMMC_BMOD_PBL_WIDTH 3 +/* The mask used to set the ALT_SDMMC_BMOD_PBL register field value. */ +#define ALT_SDMMC_BMOD_PBL_SET_MSK 0x00000700 +/* The mask used to clear the ALT_SDMMC_BMOD_PBL register field value. */ +#define ALT_SDMMC_BMOD_PBL_CLR_MSK 0xfffff8ff +/* The reset value of the ALT_SDMMC_BMOD_PBL register field. */ +#define ALT_SDMMC_BMOD_PBL_RESET 0x0 +/* Extracts the ALT_SDMMC_BMOD_PBL field value from a register. */ +#define ALT_SDMMC_BMOD_PBL_GET(value) (((value) & 0x00000700) >> 8) +/* Produces a ALT_SDMMC_BMOD_PBL register field value suitable for setting the register. */ +#define ALT_SDMMC_BMOD_PBL_SET(value) (((value) << 8) & 0x00000700) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_BMOD. + */ +struct ALT_SDMMC_BMOD_s +{ + uint32_t swr : 1; /* Software Reset */ + uint32_t fb : 1; /* Fixed Burst */ + uint32_t dsl : 5; /* Descriptor Skip Length */ + uint32_t de : 1; /* IDMAC Enable */ + const uint32_t pbl : 3; /* Programmable Burst Length */ + uint32_t : 21; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_BMOD. */ +typedef volatile struct ALT_SDMMC_BMOD_s ALT_SDMMC_BMOD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_BMOD register from the beginning of the component. */ +#define ALT_SDMMC_BMOD_OFST 0x80 + +/* + * Register : Poll Demand Register - pldmnd + * + * See Field Description. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | W | 0x0 | Poll Demand + * + */ +/* + * Field : Poll Demand - pd + * + * If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. + * The host needs to write any value into this register for the IDMAC FSM to resume + * normal descriptor fetch operation. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_PLDMND_PD register field. */ +#define ALT_SDMMC_PLDMND_PD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_PLDMND_PD register field. */ +#define ALT_SDMMC_PLDMND_PD_MSB 31 +/* The width in bits of the ALT_SDMMC_PLDMND_PD register field. */ +#define ALT_SDMMC_PLDMND_PD_WIDTH 32 +/* The mask used to set the ALT_SDMMC_PLDMND_PD register field value. */ +#define ALT_SDMMC_PLDMND_PD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_PLDMND_PD register field value. */ +#define ALT_SDMMC_PLDMND_PD_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_PLDMND_PD register field. */ +#define ALT_SDMMC_PLDMND_PD_RESET 0x0 +/* Extracts the ALT_SDMMC_PLDMND_PD field value from a register. */ +#define ALT_SDMMC_PLDMND_PD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_PLDMND_PD register field value suitable for setting the register. */ +#define ALT_SDMMC_PLDMND_PD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_PLDMND. + */ +struct ALT_SDMMC_PLDMND_s +{ + uint32_t pd : 32; /* Poll Demand */ +}; + +/* The typedef declaration for register ALT_SDMMC_PLDMND. */ +typedef volatile struct ALT_SDMMC_PLDMND_s ALT_SDMMC_PLDMND_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_PLDMND register from the beginning of the component. */ +#define ALT_SDMMC_PLDMND_OFST 0x84 + +/* + * Register : Descriptor List Base Address Register - dbaddr + * + * See Field Descriptor + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [1:0] | ??? | 0x0 | *UNDEFINED* + * [31:2] | RW | 0x0 | Start of Descriptor List + * + */ +/* + * Field : Start of Descriptor List - sdl + * + * Contains the base address of the First Descriptor. This is the byte address + * divided by 4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_DBADDR_SDL register field. */ +#define ALT_SDMMC_DBADDR_SDL_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_DBADDR_SDL register field. */ +#define ALT_SDMMC_DBADDR_SDL_MSB 31 +/* The width in bits of the ALT_SDMMC_DBADDR_SDL register field. */ +#define ALT_SDMMC_DBADDR_SDL_WIDTH 30 +/* The mask used to set the ALT_SDMMC_DBADDR_SDL register field value. */ +#define ALT_SDMMC_DBADDR_SDL_SET_MSK 0xfffffffc +/* The mask used to clear the ALT_SDMMC_DBADDR_SDL register field value. */ +#define ALT_SDMMC_DBADDR_SDL_CLR_MSK 0x00000003 +/* The reset value of the ALT_SDMMC_DBADDR_SDL register field. */ +#define ALT_SDMMC_DBADDR_SDL_RESET 0x0 +/* Extracts the ALT_SDMMC_DBADDR_SDL field value from a register. */ +#define ALT_SDMMC_DBADDR_SDL_GET(value) (((value) & 0xfffffffc) >> 2) +/* Produces a ALT_SDMMC_DBADDR_SDL register field value suitable for setting the register. */ +#define ALT_SDMMC_DBADDR_SDL_SET(value) (((value) << 2) & 0xfffffffc) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_DBADDR. + */ +struct ALT_SDMMC_DBADDR_s +{ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t sdl : 30; /* Start of Descriptor List */ +}; + +/* The typedef declaration for register ALT_SDMMC_DBADDR. */ +typedef volatile struct ALT_SDMMC_DBADDR_s ALT_SDMMC_DBADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_DBADDR register from the beginning of the component. */ +#define ALT_SDMMC_DBADDR_OFST 0x88 + +/* + * Register : Internal DMAC Status Register - idsts + * + * Sets Internal DMAC Status Fields + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------- + * [0] | RW | 0x0 | Transmit Interrupt + * [1] | RW | 0x0 | Receive Interrupt + * [2] | RW | 0x0 | Fatal Bus Error Interrupt + * [3] | ??? | 0x0 | *UNDEFINED* + * [4] | RW | 0x0 | Descriptor Unavailable Interrupt + * [5] | RW | 0x0 | Card Error Summary + * [7:6] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | Normal Interrupt Summary + * [9] | RW | 0x0 | Abnormal Interrupt Summary + * [12:10] | R | 0x0 | Error Bits + * [16:13] | R | 0x0 | Finite State Machine + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit Interrupt - ti + * + * Indicates that data transmission is finished for a descriptor. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------------------------------------ + * ALT_SDMMC_IDSTS_TI_E_CLR | 0x1 | Clears Transmit Interrupt Status Bit + * ALT_SDMMC_IDSTS_TI_E_NOCLR | 0x0 | No Clear of Transmit Interrupt Status Bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_TI + * + * Clears Transmit Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_TI_E_CLR 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_TI + * + * No Clear of Transmit Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_TI_E_NOCLR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_TI register field. */ +#define ALT_SDMMC_IDSTS_TI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_TI register field. */ +#define ALT_SDMMC_IDSTS_TI_MSB 0 +/* The width in bits of the ALT_SDMMC_IDSTS_TI register field. */ +#define ALT_SDMMC_IDSTS_TI_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDSTS_TI register field value. */ +#define ALT_SDMMC_IDSTS_TI_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_IDSTS_TI register field value. */ +#define ALT_SDMMC_IDSTS_TI_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_IDSTS_TI register field. */ +#define ALT_SDMMC_IDSTS_TI_RESET 0x0 +/* Extracts the ALT_SDMMC_IDSTS_TI field value from a register. */ +#define ALT_SDMMC_IDSTS_TI_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_IDSTS_TI register field value suitable for setting the register. */ +#define ALT_SDMMC_IDSTS_TI_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Receive Interrupt - ri + * + * Indicates the completion of data reception for a descriptor + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------------------------- + * ALT_SDMMC_IDSTS_RI_E_CLR | 0x1 | Clears Receive Interrupt Status Bit + * ALT_SDMMC_IDSTS_RI_E_NOCLR | 0x0 | No Clear of Receive Interrupt Status Bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_RI + * + * Clears Receive Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_RI_E_CLR 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_RI + * + * No Clear of Receive Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_RI_E_NOCLR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_RI register field. */ +#define ALT_SDMMC_IDSTS_RI_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_RI register field. */ +#define ALT_SDMMC_IDSTS_RI_MSB 1 +/* The width in bits of the ALT_SDMMC_IDSTS_RI register field. */ +#define ALT_SDMMC_IDSTS_RI_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDSTS_RI register field value. */ +#define ALT_SDMMC_IDSTS_RI_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDMMC_IDSTS_RI register field value. */ +#define ALT_SDMMC_IDSTS_RI_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDMMC_IDSTS_RI register field. */ +#define ALT_SDMMC_IDSTS_RI_RESET 0x0 +/* Extracts the ALT_SDMMC_IDSTS_RI field value from a register. */ +#define ALT_SDMMC_IDSTS_RI_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDMMC_IDSTS_RI register field value suitable for setting the register. */ +#define ALT_SDMMC_IDSTS_RI_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Fatal Bus Error Interrupt - fbe + * + * Indicates that a Bus Error occurred (IDSTS[12:10]). When setthe DMA disables all + * its bus accesses. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------------------------------- + * ALT_SDMMC_IDSTS_FBE_E_CLR | 0x1 | Clears Fatal Bus Error Interrupt Status Bit + * ALT_SDMMC_IDSTS_FBE_E_NOCLR | 0x0 | No Clear of Fatal Bus Error Interrupt Status Bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FBE + * + * Clears Fatal Bus Error Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_FBE_E_CLR 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FBE + * + * No Clear of Fatal Bus Error Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_FBE_E_NOCLR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_FBE register field. */ +#define ALT_SDMMC_IDSTS_FBE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_FBE register field. */ +#define ALT_SDMMC_IDSTS_FBE_MSB 2 +/* The width in bits of the ALT_SDMMC_IDSTS_FBE register field. */ +#define ALT_SDMMC_IDSTS_FBE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDSTS_FBE register field value. */ +#define ALT_SDMMC_IDSTS_FBE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDMMC_IDSTS_FBE register field value. */ +#define ALT_SDMMC_IDSTS_FBE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDMMC_IDSTS_FBE register field. */ +#define ALT_SDMMC_IDSTS_FBE_RESET 0x0 +/* Extracts the ALT_SDMMC_IDSTS_FBE field value from a register. */ +#define ALT_SDMMC_IDSTS_FBE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDMMC_IDSTS_FBE register field value suitable for setting the register. */ +#define ALT_SDMMC_IDSTS_FBE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Descriptor Unavailable Interrupt - du + * + * This status bit is set when the descriptor is unavailable due to OWN bit = 0 + * (DES0[31] =0). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------------------------------- + * ALT_SDMMC_IDSTS_DU_E_CLR | 0x1 | Clears Descriptor Unavailable Interrupt Status + * : | | Bit + * ALT_SDMMC_IDSTS_DU_E_NOCLR | 0x0 | No Clear of Descriptor Unavailable Interrupt + * : | | Status Bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_DU + * + * Clears Descriptor Unavailable Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_DU_E_CLR 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_DU + * + * No Clear of Descriptor Unavailable Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_DU_E_NOCLR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_DU register field. */ +#define ALT_SDMMC_IDSTS_DU_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_DU register field. */ +#define ALT_SDMMC_IDSTS_DU_MSB 4 +/* The width in bits of the ALT_SDMMC_IDSTS_DU register field. */ +#define ALT_SDMMC_IDSTS_DU_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDSTS_DU register field value. */ +#define ALT_SDMMC_IDSTS_DU_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDMMC_IDSTS_DU register field value. */ +#define ALT_SDMMC_IDSTS_DU_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDMMC_IDSTS_DU register field. */ +#define ALT_SDMMC_IDSTS_DU_RESET 0x0 +/* Extracts the ALT_SDMMC_IDSTS_DU field value from a register. */ +#define ALT_SDMMC_IDSTS_DU_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDMMC_IDSTS_DU register field value suitable for setting the register. */ +#define ALT_SDMMC_IDSTS_DU_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Card Error Summary - ces + * + * Indicates the status of the transaction to/from the card; also present in + * RINTSTS. Indicates the logical OR of the following bits: + * + * EBE - End Bit Error + * + * RTO - Response Timeout/Boot Ack Timeout + * + * RCRC - Response CRC + * + * SBE - Start Bit Error + * + * DRTO - Data Read Timeout/BDS timeout + * + * DCRC - Data CRC for Receive + * + * RE - Response Error + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------------------------------- + * ALT_SDMMC_IDSTS_CES_E_CLR | 0x1 | Clears Card Error Summary Interrupt Status Bit + * ALT_SDMMC_IDSTS_CES_E_NOCLR | 0x0 | No Clear Card Error Summary Interrupt Status Bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_CES + * + * Clears Card Error Summary Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_CES_E_CLR 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_CES + * + * No Clear Card Error Summary Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_CES_E_NOCLR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_CES register field. */ +#define ALT_SDMMC_IDSTS_CES_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_CES register field. */ +#define ALT_SDMMC_IDSTS_CES_MSB 5 +/* The width in bits of the ALT_SDMMC_IDSTS_CES register field. */ +#define ALT_SDMMC_IDSTS_CES_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDSTS_CES register field value. */ +#define ALT_SDMMC_IDSTS_CES_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SDMMC_IDSTS_CES register field value. */ +#define ALT_SDMMC_IDSTS_CES_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SDMMC_IDSTS_CES register field. */ +#define ALT_SDMMC_IDSTS_CES_RESET 0x0 +/* Extracts the ALT_SDMMC_IDSTS_CES field value from a register. */ +#define ALT_SDMMC_IDSTS_CES_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SDMMC_IDSTS_CES register field value suitable for setting the register. */ +#define ALT_SDMMC_IDSTS_CES_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Normal Interrupt Summary - nis + * + * Logical OR of the following: + * + * IDSTS[0] - Transmit Interrupt + * + * IDSTS[1] - Receive Interrupt + * + * Only unmasked bits affect this bit. This is a sticky bit and must be cleared + * each time a corresponding bit that causes NIS to be set is cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------------------------- + * ALT_SDMMC_IDSTS_NIS_E_CLR | 0x1 | Clears Normal Interrupt Summary Status Bit + * ALT_SDMMC_IDSTS_NIS_E_NOCLR | 0x0 | No Clear Normal Interrupt Summary Status Bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_NIS + * + * Clears Normal Interrupt Summary Status Bit + */ +#define ALT_SDMMC_IDSTS_NIS_E_CLR 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_NIS + * + * No Clear Normal Interrupt Summary Status Bit + */ +#define ALT_SDMMC_IDSTS_NIS_E_NOCLR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_NIS register field. */ +#define ALT_SDMMC_IDSTS_NIS_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_NIS register field. */ +#define ALT_SDMMC_IDSTS_NIS_MSB 8 +/* The width in bits of the ALT_SDMMC_IDSTS_NIS register field. */ +#define ALT_SDMMC_IDSTS_NIS_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDSTS_NIS register field value. */ +#define ALT_SDMMC_IDSTS_NIS_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SDMMC_IDSTS_NIS register field value. */ +#define ALT_SDMMC_IDSTS_NIS_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SDMMC_IDSTS_NIS register field. */ +#define ALT_SDMMC_IDSTS_NIS_RESET 0x0 +/* Extracts the ALT_SDMMC_IDSTS_NIS field value from a register. */ +#define ALT_SDMMC_IDSTS_NIS_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SDMMC_IDSTS_NIS register field value suitable for setting the register. */ +#define ALT_SDMMC_IDSTS_NIS_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Abnormal Interrupt Summary - ais + * + * Logical OR of the following: + * + * IDSTS[2] - Fatal Bus Interrupt + * + * IDSTS[4] - DU bit Interrupt + * + * IDSTS[5] - Card Error Summary Interrupt + * + * Only unmasked bits affect this bit. This is a sticky bit and must be cleared + * each time a corresponding bit that causes AIS to be set is cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------------------------------- + * ALT_SDMMC_IDSTS_AIS_E_CLR | 0x1 | Clears Abnormal Summary Interrupt Status Bit + * ALT_SDMMC_IDSTS_AIS_E_NOCLR | 0x0 | No Clear Abnormal Summary Interrupt Status Bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_AIS + * + * Clears Abnormal Summary Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_AIS_E_CLR 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_AIS + * + * No Clear Abnormal Summary Interrupt Status Bit + */ +#define ALT_SDMMC_IDSTS_AIS_E_NOCLR 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_AIS register field. */ +#define ALT_SDMMC_IDSTS_AIS_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_AIS register field. */ +#define ALT_SDMMC_IDSTS_AIS_MSB 9 +/* The width in bits of the ALT_SDMMC_IDSTS_AIS register field. */ +#define ALT_SDMMC_IDSTS_AIS_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDSTS_AIS register field value. */ +#define ALT_SDMMC_IDSTS_AIS_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SDMMC_IDSTS_AIS register field value. */ +#define ALT_SDMMC_IDSTS_AIS_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SDMMC_IDSTS_AIS register field. */ +#define ALT_SDMMC_IDSTS_AIS_RESET 0x0 +/* Extracts the ALT_SDMMC_IDSTS_AIS field value from a register. */ +#define ALT_SDMMC_IDSTS_AIS_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SDMMC_IDSTS_AIS register field value suitable for setting the register. */ +#define ALT_SDMMC_IDSTS_AIS_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Error Bits - eb + * + * Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus + * Error bit (IDSTS[2]) set. This field does not generate an interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------ + * ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX | 0x1 | Host Abort during transmission Status Bit + * ALT_SDMMC_IDSTS_EB_E_HOSTARBRX | 0x2 | Host Abort received during reception Status Bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_EB + * + * Host Abort during transmission Status Bit + */ +#define ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_EB + * + * Host Abort received during reception Status Bit + */ +#define ALT_SDMMC_IDSTS_EB_E_HOSTARBRX 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_EB register field. */ +#define ALT_SDMMC_IDSTS_EB_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_EB register field. */ +#define ALT_SDMMC_IDSTS_EB_MSB 12 +/* The width in bits of the ALT_SDMMC_IDSTS_EB register field. */ +#define ALT_SDMMC_IDSTS_EB_WIDTH 3 +/* The mask used to set the ALT_SDMMC_IDSTS_EB register field value. */ +#define ALT_SDMMC_IDSTS_EB_SET_MSK 0x00001c00 +/* The mask used to clear the ALT_SDMMC_IDSTS_EB register field value. */ +#define ALT_SDMMC_IDSTS_EB_CLR_MSK 0xffffe3ff +/* The reset value of the ALT_SDMMC_IDSTS_EB register field. */ +#define ALT_SDMMC_IDSTS_EB_RESET 0x0 +/* Extracts the ALT_SDMMC_IDSTS_EB field value from a register. */ +#define ALT_SDMMC_IDSTS_EB_GET(value) (((value) & 0x00001c00) >> 10) +/* Produces a ALT_SDMMC_IDSTS_EB register field value suitable for setting the register. */ +#define ALT_SDMMC_IDSTS_EB_SET(value) (((value) << 10) & 0x00001c00) + +/* + * Field : Finite State Machine - fsm + * + * DMAC FSM present state. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_SDMMC_IDSTS_FSM_E_DMAIDLE | 0x0 | DMA IDLE + * ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND | 0x1 | DMA SUSPEND + * ALT_SDMMC_IDSTS_FSM_E_DESCRD | 0x2 | DESC_RD + * ALT_SDMMC_IDSTS_FSM_E_DESCCHK | 0x3 | DESC_CHK + * ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT | 0x4 | DMA RD REQ WAIT + * ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT | 0x5 | DMA WR REQ WAIT + * ALT_SDMMC_IDSTS_FSM_E_DMARD | 0x6 | DMA RD + * ALT_SDMMC_IDSTS_FSM_E_DMAWR | 0x7 | DMA WR + * ALT_SDMMC_IDSTS_FSM_E_DECCLOSE | 0x8 | DESC CLOSE + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FSM + * + * DMA IDLE + */ +#define ALT_SDMMC_IDSTS_FSM_E_DMAIDLE 0x0 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FSM + * + * DMA SUSPEND + */ +#define ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FSM + * + * DESC_RD + */ +#define ALT_SDMMC_IDSTS_FSM_E_DESCRD 0x2 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FSM + * + * DESC_CHK + */ +#define ALT_SDMMC_IDSTS_FSM_E_DESCCHK 0x3 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FSM + * + * DMA RD REQ WAIT + */ +#define ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT 0x4 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FSM + * + * DMA WR REQ WAIT + */ +#define ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT 0x5 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FSM + * + * DMA RD + */ +#define ALT_SDMMC_IDSTS_FSM_E_DMARD 0x6 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FSM + * + * DMA WR + */ +#define ALT_SDMMC_IDSTS_FSM_E_DMAWR 0x7 +/* + * Enumerated value for register field ALT_SDMMC_IDSTS_FSM + * + * DESC CLOSE + */ +#define ALT_SDMMC_IDSTS_FSM_E_DECCLOSE 0x8 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_FSM register field. */ +#define ALT_SDMMC_IDSTS_FSM_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_FSM register field. */ +#define ALT_SDMMC_IDSTS_FSM_MSB 16 +/* The width in bits of the ALT_SDMMC_IDSTS_FSM register field. */ +#define ALT_SDMMC_IDSTS_FSM_WIDTH 4 +/* The mask used to set the ALT_SDMMC_IDSTS_FSM register field value. */ +#define ALT_SDMMC_IDSTS_FSM_SET_MSK 0x0001e000 +/* The mask used to clear the ALT_SDMMC_IDSTS_FSM register field value. */ +#define ALT_SDMMC_IDSTS_FSM_CLR_MSK 0xfffe1fff +/* The reset value of the ALT_SDMMC_IDSTS_FSM register field. */ +#define ALT_SDMMC_IDSTS_FSM_RESET 0x0 +/* Extracts the ALT_SDMMC_IDSTS_FSM field value from a register. */ +#define ALT_SDMMC_IDSTS_FSM_GET(value) (((value) & 0x0001e000) >> 13) +/* Produces a ALT_SDMMC_IDSTS_FSM register field value suitable for setting the register. */ +#define ALT_SDMMC_IDSTS_FSM_SET(value) (((value) << 13) & 0x0001e000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_IDSTS. + */ +struct ALT_SDMMC_IDSTS_s +{ + uint32_t ti : 1; /* Transmit Interrupt */ + uint32_t ri : 1; /* Receive Interrupt */ + uint32_t fbe : 1; /* Fatal Bus Error Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t du : 1; /* Descriptor Unavailable Interrupt */ + uint32_t ces : 1; /* Card Error Summary */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t nis : 1; /* Normal Interrupt Summary */ + uint32_t ais : 1; /* Abnormal Interrupt Summary */ + const uint32_t eb : 3; /* Error Bits */ + const uint32_t fsm : 4; /* Finite State Machine */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_IDSTS. */ +typedef volatile struct ALT_SDMMC_IDSTS_s ALT_SDMMC_IDSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_IDSTS register from the beginning of the component. */ +#define ALT_SDMMC_IDSTS_OFST 0x8c + +/* + * Register : Internal DMAC Interrupt Enable Register - idinten + * + * Various DMA Interrupt Enable Status + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------ + * [0] | RW | 0x0 | Transmit Interrupt Enable + * [1] | RW | 0x0 | Receive Interrupt Enable + * [2] | RW | 0x0 | Fatal Bus Error + * [3] | ??? | 0x0 | *UNDEFINED* + * [4] | RW | 0x0 | Descriptor Unavailable Interrupt + * [5] | RW | 0x0 | Card Error Summary Interrupt Enable + * [7:6] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | Normal Interrupt Summary Enable + * [9] | RW | 0x0 | Abnormal Interrupt Summary Enable. + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit Interrupt Enable - ti + * + * Enables and Disables Transmit Interrupt when Normal Interrupt Summary Enable is + * set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------------- + * ALT_SDMMC_IDINTEN_TI_E_END | 0x1 | Transmit Interrupt is enabled + * ALT_SDMMC_IDINTEN_TI_E_DISD | 0x0 | Transmit Interrupt is disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_TI + * + * Transmit Interrupt is enabled + */ +#define ALT_SDMMC_IDINTEN_TI_E_END 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_TI + * + * Transmit Interrupt is disabled + */ +#define ALT_SDMMC_IDINTEN_TI_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_TI register field. */ +#define ALT_SDMMC_IDINTEN_TI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_TI register field. */ +#define ALT_SDMMC_IDINTEN_TI_MSB 0 +/* The width in bits of the ALT_SDMMC_IDINTEN_TI register field. */ +#define ALT_SDMMC_IDINTEN_TI_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDINTEN_TI register field value. */ +#define ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_IDINTEN_TI register field value. */ +#define ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_IDINTEN_TI register field. */ +#define ALT_SDMMC_IDINTEN_TI_RESET 0x0 +/* Extracts the ALT_SDMMC_IDINTEN_TI field value from a register. */ +#define ALT_SDMMC_IDINTEN_TI_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_IDINTEN_TI register field value suitable for setting the register. */ +#define ALT_SDMMC_IDINTEN_TI_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Receive Interrupt Enable - ri + * + * Enables and Disables Receive Interrupt when Normal Interrupt Summary Enable is + * set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------------ + * ALT_SDMMC_IDINTEN_RI_E_END | 0x1 | Receive Interrupt is enabled + * ALT_SDMMC_IDINTEN_RI_E_DISD | 0x0 | Receive Interrupt is disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_RI + * + * Receive Interrupt is enabled + */ +#define ALT_SDMMC_IDINTEN_RI_E_END 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_RI + * + * Receive Interrupt is disabled + */ +#define ALT_SDMMC_IDINTEN_RI_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_RI register field. */ +#define ALT_SDMMC_IDINTEN_RI_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_RI register field. */ +#define ALT_SDMMC_IDINTEN_RI_MSB 1 +/* The width in bits of the ALT_SDMMC_IDINTEN_RI register field. */ +#define ALT_SDMMC_IDINTEN_RI_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDINTEN_RI register field value. */ +#define ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDMMC_IDINTEN_RI register field value. */ +#define ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDMMC_IDINTEN_RI register field. */ +#define ALT_SDMMC_IDINTEN_RI_RESET 0x0 +/* Extracts the ALT_SDMMC_IDINTEN_RI field value from a register. */ +#define ALT_SDMMC_IDINTEN_RI_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDMMC_IDINTEN_RI register field value suitable for setting the register. */ +#define ALT_SDMMC_IDINTEN_RI_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Fatal Bus Error - fbe + * + * When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt + * is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------------------- + * ALT_SDMMC_IDINTEN_FBE_E_END | 0x1 | Fatal Bus Error Interrupt is enabled + * ALT_SDMMC_IDINTEN_FBE_E_DISD | 0x0 | Fatal Bus Error Interrupt is disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_FBE + * + * Fatal Bus Error Interrupt is enabled + */ +#define ALT_SDMMC_IDINTEN_FBE_E_END 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_FBE + * + * Fatal Bus Error Interrupt is disabled + */ +#define ALT_SDMMC_IDINTEN_FBE_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_FBE register field. */ +#define ALT_SDMMC_IDINTEN_FBE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_FBE register field. */ +#define ALT_SDMMC_IDINTEN_FBE_MSB 2 +/* The width in bits of the ALT_SDMMC_IDINTEN_FBE register field. */ +#define ALT_SDMMC_IDINTEN_FBE_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDINTEN_FBE register field value. */ +#define ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDMMC_IDINTEN_FBE register field value. */ +#define ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDMMC_IDINTEN_FBE register field. */ +#define ALT_SDMMC_IDINTEN_FBE_RESET 0x0 +/* Extracts the ALT_SDMMC_IDINTEN_FBE field value from a register. */ +#define ALT_SDMMC_IDINTEN_FBE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDMMC_IDINTEN_FBE register field value suitable for setting the register. */ +#define ALT_SDMMC_IDINTEN_FBE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Descriptor Unavailable Interrupt - du + * + * When set along with Abnormal Interrupt Summary Enable, the DU interrupt is + * enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------------------------- + * ALT_SDMMC_IDINTEN_DU_E_END | 0x1 | Descriptor Unavailable Interrupt is enabled + * ALT_SDMMC_IDINTEN_DU_E_DISD | 0x0 | Descriptor Unavailable Interrupt is disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_DU + * + * Descriptor Unavailable Interrupt is enabled + */ +#define ALT_SDMMC_IDINTEN_DU_E_END 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_DU + * + * Descriptor Unavailable Interrupt is disabled + */ +#define ALT_SDMMC_IDINTEN_DU_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_DU register field. */ +#define ALT_SDMMC_IDINTEN_DU_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_DU register field. */ +#define ALT_SDMMC_IDINTEN_DU_MSB 4 +/* The width in bits of the ALT_SDMMC_IDINTEN_DU register field. */ +#define ALT_SDMMC_IDINTEN_DU_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDINTEN_DU register field value. */ +#define ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDMMC_IDINTEN_DU register field value. */ +#define ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDMMC_IDINTEN_DU register field. */ +#define ALT_SDMMC_IDINTEN_DU_RESET 0x0 +/* Extracts the ALT_SDMMC_IDINTEN_DU field value from a register. */ +#define ALT_SDMMC_IDINTEN_DU_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDMMC_IDINTEN_DU register field value suitable for setting the register. */ +#define ALT_SDMMC_IDINTEN_DU_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Card Error Summary Interrupt Enable - ces + * + * Enable and disable Card Error Interrupt Summary + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:----------------------------------------- + * ALT_SDMMC_IDINTEN_CES_E_END | 0x1 | Card Error Summary Interrupt is enabled + * ALT_SDMMC_IDINTEN_CES_E_DISD | 0x0 | Card Error Summary Interrupt is disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_CES + * + * Card Error Summary Interrupt is enabled + */ +#define ALT_SDMMC_IDINTEN_CES_E_END 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_CES + * + * Card Error Summary Interrupt is disabled + */ +#define ALT_SDMMC_IDINTEN_CES_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_CES register field. */ +#define ALT_SDMMC_IDINTEN_CES_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_CES register field. */ +#define ALT_SDMMC_IDINTEN_CES_MSB 5 +/* The width in bits of the ALT_SDMMC_IDINTEN_CES register field. */ +#define ALT_SDMMC_IDINTEN_CES_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDINTEN_CES register field value. */ +#define ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SDMMC_IDINTEN_CES register field value. */ +#define ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SDMMC_IDINTEN_CES register field. */ +#define ALT_SDMMC_IDINTEN_CES_RESET 0x0 +/* Extracts the ALT_SDMMC_IDINTEN_CES field value from a register. */ +#define ALT_SDMMC_IDINTEN_CES_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SDMMC_IDINTEN_CES register field value suitable for setting the register. */ +#define ALT_SDMMC_IDINTEN_CES_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Normal Interrupt Summary Enable - ni + * + * Enable and Disable Normal Interrupt Summary + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------------------- + * ALT_SDMMC_IDINTEN_NI_E_END | 0x1 | Normal Interrupt Summary is enabled + * ALT_SDMMC_IDINTEN_NI_E_DISD | 0x0 | Normal Interrupt Summary is disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_NI + * + * Normal Interrupt Summary is enabled + */ +#define ALT_SDMMC_IDINTEN_NI_E_END 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_NI + * + * Normal Interrupt Summary is disabled + */ +#define ALT_SDMMC_IDINTEN_NI_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_NI register field. */ +#define ALT_SDMMC_IDINTEN_NI_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_NI register field. */ +#define ALT_SDMMC_IDINTEN_NI_MSB 8 +/* The width in bits of the ALT_SDMMC_IDINTEN_NI register field. */ +#define ALT_SDMMC_IDINTEN_NI_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDINTEN_NI register field value. */ +#define ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SDMMC_IDINTEN_NI register field value. */ +#define ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SDMMC_IDINTEN_NI register field. */ +#define ALT_SDMMC_IDINTEN_NI_RESET 0x0 +/* Extracts the ALT_SDMMC_IDINTEN_NI field value from a register. */ +#define ALT_SDMMC_IDINTEN_NI_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SDMMC_IDINTEN_NI register field value suitable for setting the register. */ +#define ALT_SDMMC_IDINTEN_NI_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Abnormal Interrupt Summary Enable. - ai + * + * This bit enables the following bits: + * + * IDINTEN[2] - Fatal Bus Error Interrupt + * + * IDINTEN[4] - DU Interrupt + * + * IDINTEN[5] - Card Error Summary Interrupt + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------------------- + * ALT_SDMMC_IDINTEN_AI_E_END | 0x1 | Abnormal Interrupt Summary is enabled + * ALT_SDMMC_IDINTEN_AI_E_DISD | 0x0 | Abnormal Interrupt Summary is disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_AI + * + * Abnormal Interrupt Summary is enabled + */ +#define ALT_SDMMC_IDINTEN_AI_E_END 0x1 +/* + * Enumerated value for register field ALT_SDMMC_IDINTEN_AI + * + * Abnormal Interrupt Summary is disabled + */ +#define ALT_SDMMC_IDINTEN_AI_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_AI register field. */ +#define ALT_SDMMC_IDINTEN_AI_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_AI register field. */ +#define ALT_SDMMC_IDINTEN_AI_MSB 9 +/* The width in bits of the ALT_SDMMC_IDINTEN_AI register field. */ +#define ALT_SDMMC_IDINTEN_AI_WIDTH 1 +/* The mask used to set the ALT_SDMMC_IDINTEN_AI register field value. */ +#define ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SDMMC_IDINTEN_AI register field value. */ +#define ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SDMMC_IDINTEN_AI register field. */ +#define ALT_SDMMC_IDINTEN_AI_RESET 0x0 +/* Extracts the ALT_SDMMC_IDINTEN_AI field value from a register. */ +#define ALT_SDMMC_IDINTEN_AI_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SDMMC_IDINTEN_AI register field value suitable for setting the register. */ +#define ALT_SDMMC_IDINTEN_AI_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_IDINTEN. + */ +struct ALT_SDMMC_IDINTEN_s +{ + uint32_t ti : 1; /* Transmit Interrupt Enable */ + uint32_t ri : 1; /* Receive Interrupt Enable */ + uint32_t fbe : 1; /* Fatal Bus Error */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t du : 1; /* Descriptor Unavailable Interrupt */ + uint32_t ces : 1; /* Card Error Summary Interrupt Enable */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t ni : 1; /* Normal Interrupt Summary Enable */ + uint32_t ai : 1; /* Abnormal Interrupt Summary Enable. */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_IDINTEN. */ +typedef volatile struct ALT_SDMMC_IDINTEN_s ALT_SDMMC_IDINTEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_IDINTEN register from the beginning of the component. */ +#define ALT_SDMMC_IDINTEN_OFST 0x90 + +/* + * Register : Current Host Descriptor Address Register - dscaddr + * + * See Field Description. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [31:0] | R | 0x0 | Current Host Descriptor Address Register + * + */ +/* + * Field : Current Host Descriptor Address Register - hda + * + * Cleared on reset. Pointer updated by IDMAC during operation. This register + * points to the start address of the current descriptor read by the IDMAC. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_DSCADDR_HDA register field. */ +#define ALT_SDMMC_DSCADDR_HDA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_DSCADDR_HDA register field. */ +#define ALT_SDMMC_DSCADDR_HDA_MSB 31 +/* The width in bits of the ALT_SDMMC_DSCADDR_HDA register field. */ +#define ALT_SDMMC_DSCADDR_HDA_WIDTH 32 +/* The mask used to set the ALT_SDMMC_DSCADDR_HDA register field value. */ +#define ALT_SDMMC_DSCADDR_HDA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_DSCADDR_HDA register field value. */ +#define ALT_SDMMC_DSCADDR_HDA_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_DSCADDR_HDA register field. */ +#define ALT_SDMMC_DSCADDR_HDA_RESET 0x0 +/* Extracts the ALT_SDMMC_DSCADDR_HDA field value from a register. */ +#define ALT_SDMMC_DSCADDR_HDA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_DSCADDR_HDA register field value suitable for setting the register. */ +#define ALT_SDMMC_DSCADDR_HDA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_DSCADDR. + */ +struct ALT_SDMMC_DSCADDR_s +{ + const uint32_t hda : 32; /* Current Host Descriptor Address Register */ +}; + +/* The typedef declaration for register ALT_SDMMC_DSCADDR. */ +typedef volatile struct ALT_SDMMC_DSCADDR_s ALT_SDMMC_DSCADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_DSCADDR register from the beginning of the component. */ +#define ALT_SDMMC_DSCADDR_OFST 0x94 + +/* + * Register : Current Buffer Descriptor Address Register - bufaddr + * + * See Field Description. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [31:0] | R | 0x0 | Host Buffer Address Pointer + * + */ +/* + * Field : Host Buffer Address Pointer - hba + * + * Cleared on Reset. Pointer updated by IDMAC during operation. This register + * points to the current Data Buffer Address being accessed by the IDMAC. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_BUFADDR_HBA register field. */ +#define ALT_SDMMC_BUFADDR_HBA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_BUFADDR_HBA register field. */ +#define ALT_SDMMC_BUFADDR_HBA_MSB 31 +/* The width in bits of the ALT_SDMMC_BUFADDR_HBA register field. */ +#define ALT_SDMMC_BUFADDR_HBA_WIDTH 32 +/* The mask used to set the ALT_SDMMC_BUFADDR_HBA register field value. */ +#define ALT_SDMMC_BUFADDR_HBA_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_BUFADDR_HBA register field value. */ +#define ALT_SDMMC_BUFADDR_HBA_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_BUFADDR_HBA register field. */ +#define ALT_SDMMC_BUFADDR_HBA_RESET 0x0 +/* Extracts the ALT_SDMMC_BUFADDR_HBA field value from a register. */ +#define ALT_SDMMC_BUFADDR_HBA_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_BUFADDR_HBA register field value suitable for setting the register. */ +#define ALT_SDMMC_BUFADDR_HBA_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_BUFADDR. + */ +struct ALT_SDMMC_BUFADDR_s +{ + const uint32_t hba : 32; /* Host Buffer Address Pointer */ +}; + +/* The typedef declaration for register ALT_SDMMC_BUFADDR. */ +typedef volatile struct ALT_SDMMC_BUFADDR_s ALT_SDMMC_BUFADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_BUFADDR register from the beginning of the component. */ +#define ALT_SDMMC_BUFADDR_OFST 0x98 + +/* + * Register : Card Threshold Control Register - cardthrctl + * + * See Field descriptions + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Card Read Threshold Enable + * [15:1] | ??? | 0x0 | *UNDEFINED* + * [27:16] | RW | 0x0 | Card Read Threshold + * [31:28] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Card Read Threshold Enable - cardrdthren + * + * Host Controller initiates Read Transfer only if CardRdThreshold amount of space + * is available in receive FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------- + * ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END | 0x1 | Card Read Threshold is enabled + * ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISD | 0x0 | Card Read Threshold is disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_CARDRDTHREN + * + * Card Read Threshold is enabled + */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END 0x1 +/* + * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_CARDRDTHREN + * + * Card Read Threshold is disabled + */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_MSB 0 +/* The width in bits of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_WIDTH 1 +/* The mask used to set the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_RESET 0x0 +/* Extracts the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN field value from a register. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value suitable for setting the register. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Card Read Threshold - cardrdthreshold + * + * Card Read Threshold size + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_MSB 27 +/* The width in bits of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_WIDTH 12 +/* The mask used to set the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET_MSK 0x0fff0000 +/* The mask used to clear the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_CLR_MSK 0xf000ffff +/* The reset value of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_RESET 0x0 +/* Extracts the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD field value from a register. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_GET(value) (((value) & 0x0fff0000) >> 16) +/* Produces a ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value suitable for setting the register. */ +#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET(value) (((value) << 16) & 0x0fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_CARDTHRCTL. + */ +struct ALT_SDMMC_CARDTHRCTL_s +{ + uint32_t cardrdthren : 1; /* Card Read Threshold Enable */ + uint32_t : 15; /* *UNDEFINED* */ + uint32_t cardrdthreshold : 12; /* Card Read Threshold */ + uint32_t : 4; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_CARDTHRCTL. */ +typedef volatile struct ALT_SDMMC_CARDTHRCTL_s ALT_SDMMC_CARDTHRCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_CARDTHRCTL register from the beginning of the component. */ +#define ALT_SDMMC_CARDTHRCTL_OFST 0x100 + +/* + * Register : Back End Power Register - back_end_power_r + * + * See Field Description + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------- + * [15:0] | RW | 0x0 | Back End Power + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Back End Power - back_end_power + * + * Back end power operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------------|:------|:-------------------------------------------- + * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND1 | 0x1 | Back-end Power supplied to card only 1 card + * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND0 | 0x0 | Off Reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER + * + * Back-end Power supplied to card only 1 card + */ +#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND1 0x1 +/* + * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER + * + * Off Reset + */ +#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND0 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */ +#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */ +#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_MSB 15 +/* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */ +#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_WIDTH 16 +/* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field value. */ +#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field value. */ +#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */ +#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_RESET 0x0 +/* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER field value from a register. */ +#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field value suitable for setting the register. */ +#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_BACK_END_POWER_R. + */ +struct ALT_SDMMC_BACK_END_POWER_R_s +{ + uint32_t back_end_power : 16; /* Back End Power */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDMMC_BACK_END_POWER_R. */ +typedef volatile struct ALT_SDMMC_BACK_END_POWER_R_s ALT_SDMMC_BACK_END_POWER_R_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_BACK_END_POWER_R register from the beginning of the component. */ +#define ALT_SDMMC_BACK_END_POWER_R_OFST 0x104 + +/* + * Register : Data FIFO Access - data + * + * Provides read/write access to data FIFO. Addresses 0x200 and above are mapped to + * the data FIFO. More than one address is mapped to data FIFO so that FIFO can be + * accessed using bursts. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | FIFO Data + * + */ +/* + * Field : FIFO Data - value + * + * Provides read/write access to data FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDMMC_DATA_VALUE register field. */ +#define ALT_SDMMC_DATA_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDMMC_DATA_VALUE register field. */ +#define ALT_SDMMC_DATA_VALUE_MSB 31 +/* The width in bits of the ALT_SDMMC_DATA_VALUE register field. */ +#define ALT_SDMMC_DATA_VALUE_WIDTH 32 +/* The mask used to set the ALT_SDMMC_DATA_VALUE register field value. */ +#define ALT_SDMMC_DATA_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDMMC_DATA_VALUE register field value. */ +#define ALT_SDMMC_DATA_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDMMC_DATA_VALUE register field is UNKNOWN. */ +#define ALT_SDMMC_DATA_VALUE_RESET 0x0 +/* Extracts the ALT_SDMMC_DATA_VALUE field value from a register. */ +#define ALT_SDMMC_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDMMC_DATA_VALUE register field value suitable for setting the register. */ +#define ALT_SDMMC_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDMMC_DATA. + */ +struct ALT_SDMMC_DATA_s +{ + uint32_t value : 32; /* FIFO Data */ +}; + +/* The typedef declaration for register ALT_SDMMC_DATA. */ +typedef volatile struct ALT_SDMMC_DATA_s ALT_SDMMC_DATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDMMC_DATA register from the beginning of the component. */ +#define ALT_SDMMC_DATA_OFST 0x200 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SDMMC. + */ +struct ALT_SDMMC_s +{ + volatile ALT_SDMMC_CTL_t ctrl; /* ALT_SDMMC_CTL */ + volatile ALT_SDMMC_PWREN_t pwren; /* ALT_SDMMC_PWREN */ + volatile ALT_SDMMC_CLKDIV_t clkdiv; /* ALT_SDMMC_CLKDIV */ + volatile ALT_SDMMC_CLKSRC_t clksrc; /* ALT_SDMMC_CLKSRC */ + volatile ALT_SDMMC_CLKENA_t clkena; /* ALT_SDMMC_CLKENA */ + volatile ALT_SDMMC_TMOUT_t tmout; /* ALT_SDMMC_TMOUT */ + volatile ALT_SDMMC_CTYPE_t ctype; /* ALT_SDMMC_CTYPE */ + volatile ALT_SDMMC_BLKSIZ_t blksiz; /* ALT_SDMMC_BLKSIZ */ + volatile ALT_SDMMC_BYTCNT_t bytcnt; /* ALT_SDMMC_BYTCNT */ + volatile ALT_SDMMC_INTMSK_t intmask; /* ALT_SDMMC_INTMSK */ + volatile ALT_SDMMC_CMDARG_t cmdarg; /* ALT_SDMMC_CMDARG */ + volatile ALT_SDMMC_CMD_t cmd; /* ALT_SDMMC_CMD */ + volatile ALT_SDMMC_RESP0_t resp0; /* ALT_SDMMC_RESP0 */ + volatile ALT_SDMMC_RESP1_t resp1; /* ALT_SDMMC_RESP1 */ + volatile ALT_SDMMC_RESP2_t resp2; /* ALT_SDMMC_RESP2 */ + volatile ALT_SDMMC_RESP3_t resp3; /* ALT_SDMMC_RESP3 */ + volatile ALT_SDMMC_MINTSTS_t mintsts; /* ALT_SDMMC_MINTSTS */ + volatile ALT_SDMMC_RINTSTS_t rintsts; /* ALT_SDMMC_RINTSTS */ + volatile ALT_SDMMC_STAT_t status; /* ALT_SDMMC_STAT */ + volatile ALT_SDMMC_FIFOTH_t fifoth; /* ALT_SDMMC_FIFOTH */ + volatile ALT_SDMMC_CDETECT_t cdetect; /* ALT_SDMMC_CDETECT */ + volatile ALT_SDMMC_WRTPRT_t wrtprt; /* ALT_SDMMC_WRTPRT */ + volatile uint32_t _pad_0x58_0x5b; /* *UNDEFINED* */ + volatile ALT_SDMMC_TCBCNT_t tcbcnt; /* ALT_SDMMC_TCBCNT */ + volatile ALT_SDMMC_TBBCNT_t tbbcnt; /* ALT_SDMMC_TBBCNT */ + volatile ALT_SDMMC_DEBNCE_t debnce; /* ALT_SDMMC_DEBNCE */ + volatile ALT_SDMMC_USRID_t usrid; /* ALT_SDMMC_USRID */ + volatile ALT_SDMMC_VERID_t verid; /* ALT_SDMMC_VERID */ + volatile ALT_SDMMC_HCON_t hcon; /* ALT_SDMMC_HCON */ + volatile ALT_SDMMC_UHS_REG_t uhs_reg; /* ALT_SDMMC_UHS_REG */ + volatile ALT_SDMMC_RST_N_t rst_n; /* ALT_SDMMC_RST_N */ + volatile uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */ + volatile ALT_SDMMC_BMOD_t bmod; /* ALT_SDMMC_BMOD */ + volatile ALT_SDMMC_PLDMND_t pldmnd; /* ALT_SDMMC_PLDMND */ + volatile ALT_SDMMC_DBADDR_t dbaddr; /* ALT_SDMMC_DBADDR */ + volatile ALT_SDMMC_IDSTS_t idsts; /* ALT_SDMMC_IDSTS */ + volatile ALT_SDMMC_IDINTEN_t idinten; /* ALT_SDMMC_IDINTEN */ + volatile ALT_SDMMC_DSCADDR_t dscaddr; /* ALT_SDMMC_DSCADDR */ + volatile ALT_SDMMC_BUFADDR_t bufaddr; /* ALT_SDMMC_BUFADDR */ + volatile uint32_t _pad_0x9c_0xff[25]; /* *UNDEFINED* */ + volatile ALT_SDMMC_CARDTHRCTL_t cardthrctl; /* ALT_SDMMC_CARDTHRCTL */ + volatile ALT_SDMMC_BACK_END_POWER_R_t back_end_power_r; /* ALT_SDMMC_BACK_END_POWER_R */ + volatile uint32_t _pad_0x108_0x1ff[62]; /* *UNDEFINED* */ + volatile ALT_SDMMC_DATA_t data; /* ALT_SDMMC_DATA */ + volatile uint32_t _pad_0x204_0x400[127]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SDMMC. */ +typedef volatile struct ALT_SDMMC_s ALT_SDMMC_t; +/* The struct declaration for the raw register contents of register group ALT_SDMMC. */ +struct ALT_SDMMC_raw_s +{ + volatile uint32_t ctrl; /* ALT_SDMMC_CTL */ + volatile uint32_t pwren; /* ALT_SDMMC_PWREN */ + volatile uint32_t clkdiv; /* ALT_SDMMC_CLKDIV */ + volatile uint32_t clksrc; /* ALT_SDMMC_CLKSRC */ + volatile uint32_t clkena; /* ALT_SDMMC_CLKENA */ + volatile uint32_t tmout; /* ALT_SDMMC_TMOUT */ + volatile uint32_t ctype; /* ALT_SDMMC_CTYPE */ + volatile uint32_t blksiz; /* ALT_SDMMC_BLKSIZ */ + volatile uint32_t bytcnt; /* ALT_SDMMC_BYTCNT */ + volatile uint32_t intmask; /* ALT_SDMMC_INTMSK */ + volatile uint32_t cmdarg; /* ALT_SDMMC_CMDARG */ + volatile uint32_t cmd; /* ALT_SDMMC_CMD */ + volatile uint32_t resp0; /* ALT_SDMMC_RESP0 */ + volatile uint32_t resp1; /* ALT_SDMMC_RESP1 */ + volatile uint32_t resp2; /* ALT_SDMMC_RESP2 */ + volatile uint32_t resp3; /* ALT_SDMMC_RESP3 */ + volatile uint32_t mintsts; /* ALT_SDMMC_MINTSTS */ + volatile uint32_t rintsts; /* ALT_SDMMC_RINTSTS */ + volatile uint32_t status; /* ALT_SDMMC_STAT */ + volatile uint32_t fifoth; /* ALT_SDMMC_FIFOTH */ + volatile uint32_t cdetect; /* ALT_SDMMC_CDETECT */ + volatile uint32_t wrtprt; /* ALT_SDMMC_WRTPRT */ + volatile uint32_t _pad_0x58_0x5b; /* *UNDEFINED* */ + volatile uint32_t tcbcnt; /* ALT_SDMMC_TCBCNT */ + volatile uint32_t tbbcnt; /* ALT_SDMMC_TBBCNT */ + volatile uint32_t debnce; /* ALT_SDMMC_DEBNCE */ + volatile uint32_t usrid; /* ALT_SDMMC_USRID */ + volatile uint32_t verid; /* ALT_SDMMC_VERID */ + volatile uint32_t hcon; /* ALT_SDMMC_HCON */ + volatile uint32_t uhs_reg; /* ALT_SDMMC_UHS_REG */ + volatile uint32_t rst_n; /* ALT_SDMMC_RST_N */ + volatile uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */ + volatile uint32_t bmod; /* ALT_SDMMC_BMOD */ + volatile uint32_t pldmnd; /* ALT_SDMMC_PLDMND */ + volatile uint32_t dbaddr; /* ALT_SDMMC_DBADDR */ + volatile uint32_t idsts; /* ALT_SDMMC_IDSTS */ + volatile uint32_t idinten; /* ALT_SDMMC_IDINTEN */ + volatile uint32_t dscaddr; /* ALT_SDMMC_DSCADDR */ + volatile uint32_t bufaddr; /* ALT_SDMMC_BUFADDR */ + volatile uint32_t _pad_0x9c_0xff[25]; /* *UNDEFINED* */ + volatile uint32_t cardthrctl; /* ALT_SDMMC_CARDTHRCTL */ + volatile uint32_t back_end_power_r; /* ALT_SDMMC_BACK_END_POWER_R */ + volatile uint32_t _pad_0x108_0x1ff[62]; /* *UNDEFINED* */ + volatile uint32_t data; /* ALT_SDMMC_DATA */ + volatile uint32_t _pad_0x204_0x400[127]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SDMMC. */ +typedef volatile struct ALT_SDMMC_raw_s ALT_SDMMC_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_SDMMC_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdr.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdr.h new file mode 100644 index 000000000..62ad5b253 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdr.h @@ -0,0 +1,4149 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_SDR */ + +#ifndef __ALTERA_ALT_SDR_H__ +#define __ALTERA_ALT_SDR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : SDRAM Controller - ALT_SDR + * SDRAM Controller + * + * Address map for the SDRAM Interface registers + * + */ +/* + * Register Group : SDRAM Controller Module - ALT_SDR_CTL + * SDRAM Controller Module + * + * Address map for the SDRAM controller and multi-port front-end. + * + * All registers in this group reset to zero. + * + */ +/* + * Register : Controller Configuration Register - ctrlcfg + * + * The Controller Configuration Register determines the behavior of the controller. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [2:0] | RW | Unknown | DRAM Memory Type + * [7:3] | RW | Unknown | DRAM Memory Burst Length + * [9:8] | RW | Unknown | Address Interleaving Order + * [10] | RW | Unknown | ECC Enable + * [11] | RW | Unknown | ECC Auto-Correction Enable + * [12] | RW | Unknown | TBD + * [13] | RW | Unknown | Generate Single Bit Errors + * [14] | RW | Unknown | Generate Double Bit Errors + * [15] | RW | Unknown | Command Reorder Enable + * [21:16] | RW | Unknown | Starvation Limit + * [22] | RW | Unknown | DQS Tracking Enable + * [23] | RW | Unknown | No DM Pins Present + * [24] | RW | Unknown | Burst Interrupt Enable + * [25] | RW | Unknown | Burst Terminate Enable + * [31:26] | ??? | Unknown | *UNDEFINED* + * + */ +/* + * Field : DRAM Memory Type - memtype + * + * Selects memory type. Program this field with one of the following binary values, + * "001" for DDR2 SDRAM, "010" for DDR3 SDRAM, "011" + * for LPDDR1 SDRAM or "100" for LPDDR2 SDRAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB 2 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH 3 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK 0x00000007 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_MEMTYPE field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_SDR_CTL_CTLCFG_MEMTYPE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : DRAM Memory Burst Length - membl + * + * Configures burst length as a static decimal value. Legal values are valid for + * JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, this + * should be programmed with 8 (binary "01000"), for DDR2 it can be + * either 4 or 8 depending on the exact DRAM chip. LPDDR2 can be programmed with + * 4, 8, or 16 and LPDDR can be programmed with 2, 4, or 8. You must also program + * the membl field in the staticcfg register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_MSB 7 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK 0x000000f8 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK 0xffffff07 +/* The reset value of the ALT_SDR_CTL_CTLCFG_MEMBL register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_MEMBL field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_GET(value) (((value) & 0x000000f8) >> 3) +/* Produces a ALT_SDR_CTL_CTLCFG_MEMBL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_MEMBL_SET(value) (((value) << 3) & 0x000000f8) + +/* + * Field : Address Interleaving Order - addrorder + * + * Selects the order for address interleaving. Programming this field with + * different values gives different mappings between the AXI or Avalon-MM address + * and the SDRAM address. Program this field with the following binary values to + * select the ordering. "00" - chip, row, bank, column, "01" - + * chip, bank, row, column, "10"-row, chip, bank, column + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB 9 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK 0x00000300 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK 0xfffffcff +/* The reset value of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_ADDRORDER field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_SDR_CTL_CTLCFG_ADDRORDER register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : ECC Enable - eccen + * + * Enable the generation and checking of ECC. This bit must only be set if the + * memory connected to the SDRAM interface is 24 or 40 bits wide. If you set this, + * you must clear the useeccasdata field in the staticcfg register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_MSB 10 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SDR_CTL_CTLCFG_ECCEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_ECCEN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SDR_CTL_CTLCFG_ECCEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_ECCEN_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : ECC Auto-Correction Enable - ecccorren + * + * Enable auto correction of the read data returned when single bit error is + * detected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB 11 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_ECCCORREN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SDR_CTL_CTLCFG_ECCCORREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : TBD - cfg_enable_ecc_code_overwrites + * + * Set to a one to enable ECC overwrites. ECC overwrites occur when a correctable + * ECC error is seen and cause a new read/modify/write to be scheduled for that + * location to clear the ECC error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB 12 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK 0xffffefff +/* The reset value of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Generate Single Bit Errors - gensbe + * + * Enable the deliberate insertion of single bit errors in data written to memory. + * This should only be used for testing purposes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_MSB 13 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SDR_CTL_CTLCFG_GENSBE register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_GENSBE field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SDR_CTL_CTLCFG_GENSBE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_GENSBE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Generate Double Bit Errors - gendbe + * + * Enable the deliberate insertion of double bit errors in data written to memory. + * This should only be used for testing purposes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_MSB 14 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK 0x00004000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK 0xffffbfff +/* The reset value of the ALT_SDR_CTL_CTLCFG_GENDBE register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_GENDBE field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_SDR_CTL_CTLCFG_GENDBE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_GENDBE_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Command Reorder Enable - reorderen + * + * This bit controls whether the controller can re-order operations to optimize + * SDRAM bandwidth. It should generally be set to a one. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_MSB 15 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK 0x00008000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK 0xffff7fff +/* The reset value of the ALT_SDR_CTL_CTLCFG_REORDEREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_REORDEREN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_SDR_CTL_CTLCFG_REORDEREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Starvation Limit - starvelimit + * + * Specifies the number of DRAM burst transactions an individual transaction will + * allow to reorder ahead of it before its priority is raised in the memory + * controller. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB 21 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH 6 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_STARVELIMIT field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : DQS Tracking Enable - dqstrken + * + * Enables DQS tracking in the PHY. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB 22 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK 0x00400000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK 0xffbfffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_DQSTRKEN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : No DM Pins Present - nodmpins + * + * Set to a one to enable DRAM operation if no DM pins are connected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_MSB 23 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK 0x00800000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK 0xff7fffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_NODMPINS register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_NODMPINS field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_SDR_CTL_CTLCFG_NODMPINS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Burst Interrupt Enable - burstintren + * + * Set to a one to enable the controller to issue burst interrupt commands. This + * must only be set when the DRAM memory type is LPDDR2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB 24 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK 0x01000000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK 0xfeffffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_BURSTINTREN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Burst Terminate Enable - bursttermen + * + * Set to a one to enable the controller to issue burst terminate commands. This + * must only be set when the DRAM memory type is LPDDR2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB 25 +/* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK 0x02000000 +/* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK 0xfdffffff +/* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLCFG_BURSTTERMEN field value from a register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value) (((value) << 25) & 0x02000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_CTLCFG. + */ +struct ALT_SDR_CTL_CTLCFG_s +{ + uint32_t memtype : 3; /* DRAM Memory Type */ + uint32_t membl : 5; /* DRAM Memory Burst Length */ + uint32_t addrorder : 2; /* Address Interleaving Order */ + uint32_t eccen : 1; /* ECC Enable */ + uint32_t ecccorren : 1; /* ECC Auto-Correction Enable */ + uint32_t cfg_enable_ecc_code_overwrites : 1; /* TBD */ + uint32_t gensbe : 1; /* Generate Single Bit Errors */ + uint32_t gendbe : 1; /* Generate Double Bit Errors */ + uint32_t reorderen : 1; /* Command Reorder Enable */ + uint32_t starvelimit : 6; /* Starvation Limit */ + uint32_t dqstrken : 1; /* DQS Tracking Enable */ + uint32_t nodmpins : 1; /* No DM Pins Present */ + uint32_t burstintren : 1; /* Burst Interrupt Enable */ + uint32_t bursttermen : 1; /* Burst Terminate Enable */ + uint32_t : 6; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_CTLCFG. */ +typedef volatile struct ALT_SDR_CTL_CTLCFG_s ALT_SDR_CTL_CTLCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_CTLCFG register from the beginning of the component. */ +#define ALT_SDR_CTL_CTLCFG_OFST 0x0 + +/* + * Register : DRAM Timings 1 Register - dramtiming1 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [3:0] | RW | Unknown | CAS Write Latency + * [8:4] | RW | Unknown | Additive Latency + * [13:9] | RW | Unknown | CAS Read Latency + * [17:14] | RW | Unknown | Activate to Activate Delay + * [23:18] | RW | Unknown | Four Activate Window Time + * [31:24] | RW | Unknown | Refresh Cycle Time + * + */ +/* + * Field : CAS Write Latency - tcwl + * + * Memory write latency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCWL field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TCWL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Additive Latency - tal + * + * Memory additive latency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_MSB 8 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TAL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TAL field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TAL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : CAS Read Latency - tcl + * + * Memory read latency. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_MSB 13 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK 0x00003e00 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK 0xffffc1ff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCL field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value) (((value) & 0x00003e00) >> 9) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TCL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value) (((value) << 9) & 0x00003e00) + +/* + * Field : Activate to Activate Delay - trrd + * + * The activate to activate, different banks timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB 17 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK 0x0003c000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK 0xfffc3fff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRRD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value) (((value) & 0x0003c000) >> 14) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TRRD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value) (((value) << 14) & 0x0003c000) + +/* + * Field : Four Activate Window Time - tfaw + * + * The four-activate window timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB 23 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH 6 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK 0x00fc0000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK 0xff03ffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TFAW field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value) (((value) & 0x00fc0000) >> 18) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TFAW register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value) (((value) << 18) & 0x00fc0000) + +/* + * Field : Refresh Cycle Time - trfc + * + * The refresh cycle timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB 31 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK 0xff000000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK 0x00ffffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRFC field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value) (((value) & 0xff000000) >> 24) +/* Produces a ALT_SDR_CTL_DRAMTIMING1_TRFC register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value) (((value) << 24) & 0xff000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING1. + */ +struct ALT_SDR_CTL_DRAMTIMING1_s +{ + uint32_t tcwl : 4; /* CAS Write Latency */ + uint32_t tal : 5; /* Additive Latency */ + uint32_t tcl : 5; /* CAS Read Latency */ + uint32_t trrd : 4; /* Activate to Activate Delay */ + uint32_t tfaw : 6; /* Four Activate Window Time */ + uint32_t trfc : 8; /* Refresh Cycle Time */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING1. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING1_s ALT_SDR_CTL_DRAMTIMING1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING1 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING1_OFST 0x4 + +/* + * Register : DRAM Timings 2 Register - dramtiming2 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------- + * [12:0] | RW | Unknown | Refresh Interval + * [16:13] | RW | Unknown | Activate to Read or Write Delay + * [20:17] | RW | Unknown | Row Precharge Time + * [24:21] | RW | Unknown | Write Recovery Time + * [28:25] | RW | Unknown | Write to Read Time + * [31:29] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Refresh Interval - trefi + * + * The refresh interval timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB 12 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH 13 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK 0x00001fff +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK 0xffffe000 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TREFI field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value) (((value) & 0x00001fff) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TREFI register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value) (((value) << 0) & 0x00001fff) + +/* + * Field : Activate to Read or Write Delay - trcd + * + * The activate to read/write timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB 16 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK 0x0001e000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK 0xfffe1fff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRCD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value) (((value) & 0x0001e000) >> 13) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TRCD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value) (((value) << 13) & 0x0001e000) + +/* + * Field : Row Precharge Time - trp + * + * The precharge to activate timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_MSB 20 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK 0x001e0000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK 0xffe1ffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRP field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value) (((value) & 0x001e0000) >> 17) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TRP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value) (((value) << 17) & 0x001e0000) + +/* + * Field : Write Recovery Time - twr + * + * The write recovery timing. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_MSB 24 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK 0x01e00000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK 0xfe1fffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWR field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value) (((value) & 0x01e00000) >> 21) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TWR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value) (((value) << 21) & 0x01e00000) + +/* + * Field : Write to Read Time - twtr + * + * The write to read timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB 28 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK 0x1e000000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK 0xe1ffffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWTR field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value) (((value) & 0x1e000000) >> 25) +/* Produces a ALT_SDR_CTL_DRAMTIMING2_TWTR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value) (((value) << 25) & 0x1e000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING2. + */ +struct ALT_SDR_CTL_DRAMTIMING2_s +{ + uint32_t trefi : 13; /* Refresh Interval */ + uint32_t trcd : 4; /* Activate to Read or Write Delay */ + uint32_t trp : 4; /* Row Precharge Time */ + uint32_t twr : 4; /* Write Recovery Time */ + uint32_t twtr : 4; /* Write to Read Time */ + uint32_t : 3; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING2. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING2_s ALT_SDR_CTL_DRAMTIMING2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING2 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING2_OFST 0x8 + +/* + * Register : DRAM Timings 3 Register - dramtiming3 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------------------- + * [3:0] | RW | Unknown | Read to Precharge Time + * [8:4] | RW | Unknown | Activate to Precharge Time + * [14:9] | RW | Unknown | Row Cycle Time + * [18:15] | RW | Unknown | Mode Register Programming Delay + * [22:19] | RW | Unknown | CAS to CAS Delay + * [31:23] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Read to Precharge Time - trtp + * + * The read to precharge timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRTP field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRTP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Activate to Precharge Time - tras + * + * The activate to precharge timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB 8 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK 0x000001f0 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK 0xfffffe0f +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRAS field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value) (((value) & 0x000001f0) >> 4) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRAS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value) (((value) << 4) & 0x000001f0) + +/* + * Field : Row Cycle Time - trc + * + * The activate to activate timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB 14 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH 6 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK 0x00007e00 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK 0xffff81ff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRC register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRC field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value) (((value) & 0x00007e00) >> 9) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRC register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value) (((value) << 9) & 0x00007e00) + +/* + * Field : Mode Register Programming Delay - tmrd + * + * Mode register timing parameter. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB 18 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK 0x00078000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK 0xfff87fff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TMRD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value) (((value) & 0x00078000) >> 15) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TMRD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value) (((value) << 15) & 0x00078000) + +/* + * Field : CAS to CAS Delay - tccd + * + * The CAS to CAS delay time. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB 22 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK 0x00780000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK 0xff87ffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TCCD field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value) (((value) & 0x00780000) >> 19) +/* Produces a ALT_SDR_CTL_DRAMTIMING3_TCCD register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value) (((value) << 19) & 0x00780000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING3. + */ +struct ALT_SDR_CTL_DRAMTIMING3_s +{ + uint32_t trtp : 4; /* Read to Precharge Time */ + uint32_t tras : 5; /* Activate to Precharge Time */ + uint32_t trc : 6; /* Row Cycle Time */ + uint32_t tmrd : 4; /* Mode Register Programming Delay */ + uint32_t tccd : 4; /* CAS to CAS Delay */ + uint32_t : 9; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING3. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING3_s ALT_SDR_CTL_DRAMTIMING3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING3 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING3_OFST 0xc + +/* + * Register : DRAM Timings 4 Register - dramtiming4 + * + * This register implements JEDEC standardized timing parameters. It should be + * programmed in clock cycles, for the value specified by the memory vendor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------------- + * [9:0] | RW | Unknown | Self-refresh Exit + * [19:10] | RW | Unknown | Power Down Exit + * [23:20] | RW | Unknown | Minimum Low Power State Cycles + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Self-refresh Exit - selfrfshexit + * + * The self refresh exit cycles, tXS. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB 9 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK 0x000003ff +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value) (((value) << 0) & 0x000003ff) + +/* + * Field : Power Down Exit - pwrdownexit + * + * The power down exit cycles, tXPDLL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB 19 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK 0x000ffc00 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK 0xfff003ff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value) (((value) & 0x000ffc00) >> 10) +/* Produces a ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value) (((value) << 10) & 0x000ffc00) + +/* + * Field : Minimum Low Power State Cycles - minpwrsavecycles + * + * The minimum number of cycles to stay in a low power state. This applies to both + * power down and self-refresh and should be set to the greater of tPD and tCKESR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB 23 +/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK 0x00f00000 +/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK 0xff0fffff +/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES field value from a register. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value) (((value) & 0x00f00000) >> 20) +/* Produces a ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value) (((value) << 20) & 0x00f00000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMTIMING4. + */ +struct ALT_SDR_CTL_DRAMTIMING4_s +{ + uint32_t selfrfshexit : 10; /* Self-refresh Exit */ + uint32_t pwrdownexit : 10; /* Power Down Exit */ + uint32_t minpwrsavecycles : 4; /* Minimum Low Power State Cycles */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING4. */ +typedef volatile struct ALT_SDR_CTL_DRAMTIMING4_s ALT_SDR_CTL_DRAMTIMING4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMTIMING4 register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMTIMING4_OFST 0x10 + +/* + * Register : Lower Power Timing Register - lowpwrtiming + * + * This register controls the behavior of the low power logic in the controller. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [15:0] | RW | Unknown | Auto-power Down Cycles + * [19:16] | RW | Unknown | Clock Disable Delay Cycles + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Auto-power Down Cycles - autopdcycles + * + * The number of idle clock cycles after which the controller should place the + * memory into power-down mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB 15 +/* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH 16 +/* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES field value from a register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Clock Disable Delay Cycles - clkdisablecycles + * + * Set to a the number of clocks after the execution of an self-refresh to stop the + * clock. This register is generally set based on PHY design latency and should + * generally not be changed. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB 19 +/* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK 0x000f0000 +/* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK 0xfff0ffff +/* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES field value from a register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value) (((value) & 0x000f0000) >> 16) +/* Produces a ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value) (((value) << 16) & 0x000f0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_LOWPWRTIMING. + */ +struct ALT_SDR_CTL_LOWPWRTIMING_s +{ + uint32_t autopdcycles : 16; /* Auto-power Down Cycles */ + uint32_t clkdisablecycles : 4; /* Clock Disable Delay Cycles */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_LOWPWRTIMING. */ +typedef volatile struct ALT_SDR_CTL_LOWPWRTIMING_s ALT_SDR_CTL_LOWPWRTIMING_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_LOWPWRTIMING register from the beginning of the component. */ +#define ALT_SDR_CTL_LOWPWRTIMING_OFST 0x14 + +/* + * Register : ODT Control Register - dramodt + * + * This register controls which ODT pin is asserted during reads or writes. Bits + * [1:0] control which ODT pin is asserted during to accesses to chip select 0, + * bits [3:2] which ODT pin is asserted during accesses to chip select 1. For + * example, a value of "1001" will cause ODT[0] to be asserted for + * accesses to CS[0], and ODT[1] to be asserted for access to CS[1] pin. Set this + * to "0001" if there is only one chip select available. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------ + * [3:0] | RW | Unknown | Write ODT Control + * [7:4] | RW | Unknown | Read ODT Control + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Write ODT Control - cfg_write_odt_chip + * + * This register controls which ODT pin is asserted during writes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP field value from a register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Read ODT Control - cfg_read_odt_chip + * + * This register controls which ODT pin is asserted during reads. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK 0xffffff0f +/* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP field value from a register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMODT. + */ +struct ALT_SDR_CTL_DRAMODT_s +{ + uint32_t cfg_write_odt_chip : 4; /* Write ODT Control */ + uint32_t cfg_read_odt_chip : 4; /* Read ODT Control */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMODT. */ +typedef volatile struct ALT_SDR_CTL_DRAMODT_s ALT_SDR_CTL_DRAMODT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMODT register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMODT_OFST 0x18 + +/* + * Register : DRAM Address Widths Register - dramaddrw + * + * This register configures the width of the various address fields of the DRAM. + * The values specified in this register must match the memory devices being used. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------- + * [4:0] | RW | Unknown | DRAM Column Address Bits + * [9:5] | RW | Unknown | DRAM Row Address Bits + * [12:10] | RW | Unknown | DRAM Bank Address Bits + * [15:13] | RW | Unknown | DRAM Chip Address Bits + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DRAM Column Address Bits - colbits + * + * The number of column address bits for the memory devices in your memory + * interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_MSB 4 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET_MSK 0x0000001f +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_COLBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMADDRW_COLBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET(value) (((value) << 0) & 0x0000001f) + +/* + * Field : DRAM Row Address Bits - rowbits + * + * The number of row address bits for the memory devices in your memory interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_MSB 9 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET_MSK 0x000003e0 +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_CLR_MSK 0xfffffc1f +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_ROWBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_GET(value) (((value) & 0x000003e0) >> 5) +/* Produces a ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET(value) (((value) << 5) & 0x000003e0) + +/* + * Field : DRAM Bank Address Bits - bankbits + * + * The number of bank address bits for the memory devices in your memory interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_MSB 12 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_WIDTH 3 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET_MSK 0x00001c00 +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_CLR_MSK 0xffffe3ff +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_BANKBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_GET(value) (((value) & 0x00001c00) >> 10) +/* Produces a ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET(value) (((value) << 10) & 0x00001c00) + +/* + * Field : DRAM Chip Address Bits - csbits + * + * The number of chip select address bits for the memory devices in your memory + * interface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_MSB 15 +/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_WIDTH 3 +/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET_MSK 0x0000e000 +/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_CLR_MSK 0xffff1fff +/* The reset value of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMADDRW_CSBITS field value from a register. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_GET(value) (((value) & 0x0000e000) >> 13) +/* Produces a ALT_SDR_CTL_DRAMADDRW_CSBITS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET(value) (((value) << 13) & 0x0000e000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMADDRW. + */ +struct ALT_SDR_CTL_DRAMADDRW_s +{ + uint32_t colbits : 5; /* DRAM Column Address Bits */ + uint32_t rowbits : 5; /* DRAM Row Address Bits */ + uint32_t bankbits : 3; /* DRAM Bank Address Bits */ + uint32_t csbits : 3; /* DRAM Chip Address Bits */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMADDRW. */ +typedef volatile struct ALT_SDR_CTL_DRAMADDRW_s ALT_SDR_CTL_DRAMADDRW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMADDRW register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMADDRW_OFST 0x2c + +/* + * Register : DRAM Interface Data Width Register - dramifwidth + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------- + * [7:0] | RW | Unknown | DRAM Interface Data Width + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DRAM Interface Data Width - ifwidth + * + * This register controls the interface width of the SDRAM interface, including any + * bits used for ECC. For example, for a 32-bit interface with ECC, program this + * register with 0x28. You must also program the ctrlwidth register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH field value from a register. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMIFWIDTH. + */ +struct ALT_SDR_CTL_DRAMIFWIDTH_s +{ + uint32_t ifwidth : 8; /* DRAM Interface Data Width */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMIFWIDTH. */ +typedef volatile struct ALT_SDR_CTL_DRAMIFWIDTH_s ALT_SDR_CTL_DRAMIFWIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMIFWIDTH register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_OFST 0x30 + +/* + * Register : DRAM Devices Data Width Register - dramdevwidth + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------------ + * [3:0] | RW | Unknown | DRAM Devices Data Width + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DRAM Devices Data Width - devwidth + * + * This register specifies the width of the physical DRAM chips, for example 8 or + * 16. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_WIDTH 4 +/* The mask used to set the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH field value from a register. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. + */ +struct ALT_SDR_CTL_DRAMDEVWIDTH_s +{ + uint32_t devwidth : 4; /* DRAM Devices Data Width */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. */ +typedef volatile struct ALT_SDR_CTL_DRAMDEVWIDTH_s ALT_SDR_CTL_DRAMDEVWIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMDEVWIDTH register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_OFST 0x34 + +/* + * Register : DRAM Status Register - dramsts + * + * This register provides the status of the calibration and ECC logic. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:---------------------------- + * [0] | RW | Unknown | PHY Calibration Successful + * [1] | RW | Unknown | PHY Calibration Failed + * [2] | RW | Unknown | Single Bit Error Seen + * [3] | RW | Unknown | Double Bit Error Seen + * [4] | RW | Unknown | ECC Auto-Correction Dropped + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : PHY Calibration Successful - calsuccess + * + * This bit will be set to 1 if the PHY was able to successfully calibrate. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_MSB 0 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_CALSUCCESS field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : PHY Calibration Failed - calfail + * + * This bit will be set to 1 if the PHY was unable to calibrate. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_MSB 1 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_CALFAIL field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDR_CTL_DRAMSTS_CALFAIL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Single Bit Error Seen - sbeerr + * + * This bit will be set to 1 if there have been any ECC single bit errors detected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_MSB 2 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_DRAMSTS_SBEERR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_SBEERR field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_DRAMSTS_SBEERR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_SBEERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Double Bit Error Seen - dbeerr + * + * This bit will be set to 1 if there have been any ECC double bit errors detected. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_DRAMSTS_DBEERR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_DBEERR field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_DRAMSTS_DBEERR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_DBEERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : ECC Auto-Correction Dropped - corrdrop + * + * This bit will be set to 1 if there any auto-corrections have been dropped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_MSB 4 +/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMSTS_CORRDROP field value from a register. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDR_CTL_DRAMSTS_CORRDROP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMSTS. + */ +struct ALT_SDR_CTL_DRAMSTS_s +{ + uint32_t calsuccess : 1; /* PHY Calibration Successful */ + uint32_t calfail : 1; /* PHY Calibration Failed */ + uint32_t sbeerr : 1; /* Single Bit Error Seen */ + uint32_t dbeerr : 1; /* Double Bit Error Seen */ + uint32_t corrdrop : 1; /* ECC Auto-Correction Dropped */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMSTS. */ +typedef volatile struct ALT_SDR_CTL_DRAMSTS_s ALT_SDR_CTL_DRAMSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMSTS register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMSTS_OFST 0x38 + +/* + * Register : ECC Interrupt Register - dramintr + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------------- + * [0] | RW | Unknown | Interrupt Enable + * [1] | RW | Unknown | Mask Single Bit Error Interrupt + * [2] | RW | Unknown | Mask Double Bit Error Interrupt + * [3] | RW | Unknown | Mask Dropped Auto-correction Interrupt + * [4] | RW | Unknown | Clear Interrupt Signal + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt Enable - intren + * + * Enable the interrupt output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_MSB 0 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_DRAMINTR_INTREN register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_INTREN field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_DRAMINTR_INTREN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_INTREN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Mask Single Bit Error Interrupt - sbemask + * + * Mask the single bit error interrupt. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB 1 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_SBEMSK field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDR_CTL_DRAMINTR_SBEMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Mask Double Bit Error Interrupt - dbemask + * + * Mask the double bit error interrupt. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB 2 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_DBEMSK field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_DRAMINTR_DBEMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Mask Dropped Auto-correction Interrupt - corrdropmask + * + * Set this bit to a one to mask interrupts for an ECC correction write back + * needing to be dropped. This indicates a burst of memory errors in a short + * period of time. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB 3 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Clear Interrupt Signal - intrclr + * + * Writing to this self-clearing bit clears the interrupt signal. Writing to this + * bit also clears the error count and error address registers. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB 4 +/* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DRAMINTR_INTRCLR field value from a register. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SDR_CTL_DRAMINTR_INTRCLR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DRAMINTR. + */ +struct ALT_SDR_CTL_DRAMINTR_s +{ + uint32_t intren : 1; /* Interrupt Enable */ + uint32_t sbemask : 1; /* Mask Single Bit Error Interrupt */ + uint32_t dbemask : 1; /* Mask Double Bit Error Interrupt */ + uint32_t corrdropmask : 1; /* Mask Dropped Auto-correction Interrupt */ + uint32_t intrclr : 1; /* Clear Interrupt Signal */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DRAMINTR. */ +typedef volatile struct ALT_SDR_CTL_DRAMINTR_s ALT_SDR_CTL_DRAMINTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DRAMINTR register from the beginning of the component. */ +#define ALT_SDR_CTL_DRAMINTR_OFST 0x3c + +/* + * Register : ECC Single Bit Error Count Register - sbecount + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------- + * [7:0] | RW | Unknown | Single Bit Error Count + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Single Bit Error Count - count + * + * Reports the number of single bit errors that have occurred since the status + * register counters were last cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_MSB 7 +/* The width in bits of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_SBECOUNT_COUNT register field is UNKNOWN. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_SBECOUNT_COUNT field value from a register. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_SBECOUNT_COUNT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_SBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_SBECOUNT. + */ +struct ALT_SDR_CTL_SBECOUNT_s +{ + uint32_t count : 8; /* Single Bit Error Count */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_SBECOUNT. */ +typedef volatile struct ALT_SDR_CTL_SBECOUNT_s ALT_SDR_CTL_SBECOUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_SBECOUNT register from the beginning of the component. */ +#define ALT_SDR_CTL_SBECOUNT_OFST 0x40 + +/* + * Register : ECC Double Bit Error Count Register - dbecount + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------- + * [7:0] | RW | Unknown | Double Bit Error Count + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Double Bit Error Count - count + * + * Reports the number of double bit errors that have occurred since the status + * register counters were last cleared. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_DBECOUNT_COUNT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DBECOUNT_COUNT field value from a register. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_DBECOUNT_COUNT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DBECOUNT. + */ +struct ALT_SDR_CTL_DBECOUNT_s +{ + uint32_t count : 8; /* Double Bit Error Count */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DBECOUNT. */ +typedef volatile struct ALT_SDR_CTL_DBECOUNT_s ALT_SDR_CTL_DBECOUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DBECOUNT register from the beginning of the component. */ +#define ALT_SDR_CTL_DBECOUNT_OFST 0x44 + +/* + * Register : ECC Error Address Register - erraddr + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------ + * [31:0] | RW | Unknown | ECC Error Address + * + */ +/* + * Field : ECC Error Address - addr + * + * The address of the most recent ECC error. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_MSB 31 +/* The width in bits of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_ERRADDR_ADDR register field value. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_ERRADDR_ADDR register field value. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_ERRADDR_ADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_ERRADDR_ADDR field value from a register. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_ERRADDR_ADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_ERRADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_ERRADDR. + */ +struct ALT_SDR_CTL_ERRADDR_s +{ + uint32_t addr : 32; /* ECC Error Address */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_ERRADDR. */ +typedef volatile struct ALT_SDR_CTL_ERRADDR_s ALT_SDR_CTL_ERRADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_ERRADDR register from the beginning of the component. */ +#define ALT_SDR_CTL_ERRADDR_OFST 0x48 + +/* + * Register : ECC Auto-correction Dropped Count Register - dropcount + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------------------ + * [7:0] | RW | Unknown | Dropped Auto-correction Count + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Dropped Auto-correction Count - corrdropcount + * + * This gives the count of the number of ECC write back transactions dropped due to + * the internal FIFO overflowing. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_MSB 7 +/* The width in bits of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field is UNKNOWN. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT field value from a register. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DROPCOUNT. + */ +struct ALT_SDR_CTL_DROPCOUNT_s +{ + uint32_t corrdropcount : 8; /* Dropped Auto-correction Count */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DROPCOUNT. */ +typedef volatile struct ALT_SDR_CTL_DROPCOUNT_s ALT_SDR_CTL_DROPCOUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DROPCOUNT register from the beginning of the component. */ +#define ALT_SDR_CTL_DROPCOUNT_OFST 0x4c + +/* + * Register : ECC Auto-correction Dropped Address Register - dropaddr + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------------- + * [31:0] | RW | Unknown | Dropped Auto-correction Address + * + */ +/* + * Field : Dropped Auto-correction Address - corrdropaddr + * + * This register gives the last address which was dropped. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_MSB 31 +/* The width in bits of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_DROPADDR_CORRDROPADDR field value from a register. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_DROPADDR. + */ +struct ALT_SDR_CTL_DROPADDR_s +{ + uint32_t corrdropaddr : 32; /* Dropped Auto-correction Address */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_DROPADDR. */ +typedef volatile struct ALT_SDR_CTL_DROPADDR_s ALT_SDR_CTL_DROPADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_DROPADDR register from the beginning of the component. */ +#define ALT_SDR_CTL_DROPADDR_OFST 0x50 + +/* + * Register : Low Power Control Register - lowpwreq + * + * This register instructs the controller to put the DRAM into a power down state. + * Note that some commands are only valid for certain memory types. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------------- + * [0] | RW | Unknown | Deep Power Down Request + * [2:1] | RW | Unknown | Deep Power Down Chip Select Mask + * [3] | RW | Unknown | Self-refresh Request + * [5:4] | RW | Unknown | Self-refresh Chip Select Mask + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Deep Power Down Request - deeppwrdnreq + * + * Write a one to this bit to request a deep power down. This bit should only be + * written with LPDDR2 DRAMs, DDR3 DRAMs do not support deep power down. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB 0 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Deep Power Down Chip Select Mask - deeppwrdnmask + * + * Write ones to this register to select which DRAM chip selects will be powered + * down. Typical usage is to set both of these bits when deeppwrdnreq is set but + * the controller does support putting a single chip into deep power down and + * keeping the other chip running. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB 2 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK 0x00000006 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : Self-refresh Request - selfrshreq + * + * Write a one to this bit to request the RAM be put into a self refresh state. + * This bit is treated as a static value so the RAM will remain in self-refresh as + * long as this register bit is set to a one. This power down mode can be selected + * for all DRAMs supported by the controller. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB 3 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Self-refresh Chip Select Mask - selfrfshmask + * + * Write a one to each bit of this field to have a self refresh request apply to + * both chips. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB 5 +/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK 0x00000030 +/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK 0xffffffcf +/* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK field value from a register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value) (((value) << 4) & 0x00000030) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_LOWPWREQ. + */ +struct ALT_SDR_CTL_LOWPWREQ_s +{ + uint32_t deeppwrdnreq : 1; /* Deep Power Down Request */ + uint32_t deeppwrdnmask : 2; /* Deep Power Down Chip Select Mask */ + uint32_t selfrshreq : 1; /* Self-refresh Request */ + uint32_t selfrfshmask : 2; /* Self-refresh Chip Select Mask */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_LOWPWREQ. */ +typedef volatile struct ALT_SDR_CTL_LOWPWREQ_s ALT_SDR_CTL_LOWPWREQ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_LOWPWREQ register from the beginning of the component. */ +#define ALT_SDR_CTL_LOWPWREQ_OFST 0x54 + +/* + * Register : Low Power Acknowledge Register - lowpwrack + * + * This register gives the status of the power down commands requested by the Low + * Power Control register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:---------------------------- + * [0] | RW | Unknown | Deep Power Down Acknowledge + * [1] | RW | Unknown | Self-refresh Acknowledge + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Deep Power Down Acknowledge - deeppwrdnack + * + * This bit is set to a one after a deep power down has been executed + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB 0 +/* The width in bits of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK field value from a register. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Self-refresh Acknowledge - selfrfshack + * + * This bit is a one to indicate that the controller is in a self-refresh state. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB 1 +/* The width in bits of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field is UNKNOWN. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK field value from a register. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_LOWPWRACK. + */ +struct ALT_SDR_CTL_LOWPWRACK_s +{ + uint32_t deeppwrdnack : 1; /* Deep Power Down Acknowledge */ + uint32_t selfrfshack : 1; /* Self-refresh Acknowledge */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_LOWPWRACK. */ +typedef volatile struct ALT_SDR_CTL_LOWPWRACK_s ALT_SDR_CTL_LOWPWRACK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_LOWPWRACK register from the beginning of the component. */ +#define ALT_SDR_CTL_LOWPWRACK_OFST 0x58 + +/* + * Register : Static Configuration Register - staticcfg + * + * This register controls configuration values which cannot be updated while + * transactions are flowing. + * + * You should write once to this register with the membl and eccen fields set to + * your desired configuration, and then write to the register again with membl and + * eccen and the applycfg bit set. The applycfg bit is write only. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:---------------------------- + * [1:0] | RW | Unknown | Memory Burst Length + * [2] | RW | Unknown | Use ECC Bits As Data + * [3] | RW | Unknown | Apply Configuration Changes + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Memory Burst Length - membl + * + * This field specifies the DRAM burst length. Write the following values to set + * the a burst length appropriate for the specific DRAM being used. "00" + * for burst length 2, "01" for burst length 4, "10" for burst + * length 8. If you set this, you must also set the membl field in the ctrlcfg + * register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_MSB 1 +/* The width in bits of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SDR_CTL_STATICCFG_MEMBL register field is UNKNOWN. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_STATICCFG_MEMBL field value from a register. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SDR_CTL_STATICCFG_MEMBL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_STATICCFG_MEMBL_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Use ECC Bits As Data - useeccasdata + * + * This field allows the FPGA ports to directly access the extra data bits that are + * normally used to hold the ECC code. The interface width must be set to 24 or 40 + * in the dramifwidth register. If you set this, you must clear the eccen field in + * the ctrlcfg register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_MSB 2 +/* The width in bits of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field is UNKNOWN. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_RESET 0x0 +/* Extracts the ALT_SDR_CTL_STATICCFG_USEECCASDATA field value from a register. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value suitable for setting the register. */ +#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Apply Configuration Changes - applycfg + * + * Write with this bit set to apply all the settings loaded in SDR registers to the + * memory interface. This bit is write-only and always returns 0 if read. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_MSB 3 +/* The width in bits of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field is UNKNOWN. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_RESET 0x0 +/* Extracts the ALT_SDR_CTL_STATICCFG_APPLYCFG field value from a register. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SDR_CTL_STATICCFG_APPLYCFG register field value suitable for setting the register. */ +#define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_STATICCFG. + */ +struct ALT_SDR_CTL_STATICCFG_s +{ + uint32_t membl : 2; /* Memory Burst Length */ + uint32_t useeccasdata : 1; /* Use ECC Bits As Data */ + uint32_t applycfg : 1; /* Apply Configuration Changes */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_STATICCFG. */ +typedef volatile struct ALT_SDR_CTL_STATICCFG_s ALT_SDR_CTL_STATICCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_STATICCFG register from the beginning of the component. */ +#define ALT_SDR_CTL_STATICCFG_OFST 0x5c + +/* + * Register : Memory Controller Width Register - ctrlwidth + * + * This register controls the width of the physical DRAM interface. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------- + * [1:0] | RW | Unknown | Controller Interface Width + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Controller Interface Width - ctrlwidth + * + * Specifies controller DRAM interface width, with the following encoding. + * "00" for 8-bit, "01" for 16-bit (no ECC) or 24-bit (ECC + * enabled), "10" for 32-bit (no ECC) or 40-bit (ECC enabled). You must + * also program the dramifwidth register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_MSB 1 +/* The width in bits of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field is UNKNOWN. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_RESET 0x0 +/* Extracts the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH field value from a register. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value suitable for setting the register. */ +#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_CTLWIDTH. + */ +struct ALT_SDR_CTL_CTLWIDTH_s +{ + uint32_t ctrlwidth : 2; /* Controller Interface Width */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_CTLWIDTH. */ +typedef volatile struct ALT_SDR_CTL_CTLWIDTH_s ALT_SDR_CTL_CTLWIDTH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_CTLWIDTH register from the beginning of the component. */ +#define ALT_SDR_CTL_CTLWIDTH_OFST 0x60 + +/* + * Register : Port Configuration Register - portcfg + * + * This register should be set to a zero in any bit which corresponds to a port + * which does mostly sequential memory accesses. For ports with highly random + * accesses, the bit should be set to a one. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:---------------------- + * [9:0] | ??? | Unknown | *UNDEFINED* + * [19:10] | RW | Unknown | Auto-precharge Enable + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Auto-precharge Enable - autopchen + * + * One bit per control port. Set bit N to a 1 to have the controller request an + * automatic precharge following bus command completion (close the row + * automatically). Set to a zero to request that the controller attempt to keep a + * row open. For random dominated operations this register should be set to a 1 + * for all active ports. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_MSB 19 +/* The width in bits of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET_MSK 0x000ffc00 +/* The mask used to clear the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_CLR_MSK 0xfff003ff +/* The reset value of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PORTCFG_AUTOPCHEN field value from a register. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_GET(value) (((value) & 0x000ffc00) >> 10) +/* Produces a ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET(value) (((value) << 10) & 0x000ffc00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PORTCFG. + */ +struct ALT_SDR_CTL_PORTCFG_s +{ + uint32_t : 10; /* *UNDEFINED* */ + uint32_t autopchen : 10; /* Auto-precharge Enable */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PORTCFG. */ +typedef volatile struct ALT_SDR_CTL_PORTCFG_s ALT_SDR_CTL_PORTCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PORTCFG register from the beginning of the component. */ +#define ALT_SDR_CTL_PORTCFG_OFST 0x7c + +/* + * Register : FPGA Ports Reset Control Register - fpgaportrst + * + * This register implements functionality to allow the CPU to control when the MPFE + * will enable the ports to the FPGA fabric. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------- + * [13:0] | RW | Unknown | Port Reset Control + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port Reset Control - portrstn + * + * This register should be written to with a 1 to enable the selected FPGA port to + * exit reset. Writing a bit to a zero will stretch the port reset until the + * register is written. Read data ports are connected to bits 3:0, with read data + * port 0 at bit 0 to read data port 3 at bit 3. Write data ports 0 to 3 are mapped + * to 4 to 7, with write data port 0 connected to bit 4 to write data port 3 at bit + * 7. Command ports are connected to bits 8 to 13, with command port 0 at bit 8 to + * command port 5 at bit 13. Expected usage would be to set all the bits at the + * same time but setting some bits to a zero and others to a one is supported. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB 13 +/* The width in bits of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH 14 +/* The mask used to set the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK 0x00003fff +/* The mask used to clear the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK 0xffffc000 +/* The reset value of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field is UNKNOWN. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN field value from a register. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value) (((value) & 0x00003fff) >> 0) +/* Produces a ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value) (((value) << 0) & 0x00003fff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_FPGAPORTRST. + */ +struct ALT_SDR_CTL_FPGAPORTRST_s +{ + uint32_t portrstn : 14; /* Port Reset Control */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_FPGAPORTRST. */ +typedef volatile struct ALT_SDR_CTL_FPGAPORTRST_s ALT_SDR_CTL_FPGAPORTRST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_FPGAPORTRST register from the beginning of the component. */ +#define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80 + +/* + * Register : Memory Protection Port Default Register - protportdefault + * + * This register controls the default protection assignment for a port. Ports + * which have explicit rules which define regions which are illegal to access + * should set the bits to pass by default. Ports which have explicit rules which + * define legal areas should set the bit to force all transactions to fail. + * Leaving this register to all zeros should be used for systems which do not + * desire any protection from the memory controller. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------- + * [9:0] | RW | Unknown | Port Default Action + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port Default Action - portdefault + * + * Determines the default action for a transactions from a port. Set a bit to a + * zero to indicate that all accesses from the port should pass by default, set a + * bit to a one if the default protection is to fail the access. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_MSB 9 +/* The width in bits of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET_MSK 0x000003ff +/* The mask used to clear the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT field value from a register. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. + */ +struct ALT_SDR_CTL_PROTPORTDEFAULT_s +{ + uint32_t portdefault : 10; /* Port Default Action */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. */ +typedef volatile struct ALT_SDR_CTL_PROTPORTDEFAULT_s ALT_SDR_CTL_PROTPORTDEFAULT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTPORTDEFAULT register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_OFST 0x8c + +/* + * Register : Memory Protection Address Register - protruleaddr + * + * This register is used to control the memory protection for port 0 transactions. + * Address ranges can either be used to allow access to memory regions or disallow + * access to memory regions. If trustzone is being used, access can be enabled for + * protected transactions or disabled for unprotected transactions. The default + * state of this register is to allow all access. Address values used for + * protection are only physical addresses. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------- + * [11:0] | RW | Unknown | Low Address + * [23:12] | RW | Unknown | High Address + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Low Address - lowaddr + * + * Lower 12 bits of the address for a check. Address is compared to be less than + * or equal to the address of a transaction. Note that since AXI transactions + * cannot cross a 4K byte boundary, the transaction start and transaction end + * address must also fall within the same 1MByte block pointed to by this address + * pointer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_MSB 11 +/* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET_MSK 0x00000fff +/* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_CLR_MSK 0xfffff000 +/* The reset value of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEADDR_LOWADDR field value from a register. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_GET(value) (((value) & 0x00000fff) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET(value) (((value) << 0) & 0x00000fff) + +/* + * Field : High Address - highaddr + * + * Upper 12 bits of the address for a check. Address is compared to be greater + * than or equal to the address of a transaction. Note that since AXI transactions + * cannot cross a 4K byte boundary, the transaction start and transaction end + * address must also fall within the same 1MByte block pointed to by this address + * pointer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_MSB 23 +/* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET_MSK 0x00fff000 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_CLR_MSK 0xff000fff +/* The reset value of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR field value from a register. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_GET(value) (((value) & 0x00fff000) >> 12) +/* Produces a ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET(value) (((value) << 12) & 0x00fff000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULEADDR. + */ +struct ALT_SDR_CTL_PROTRULEADDR_s +{ + uint32_t lowaddr : 12; /* Low Address */ + uint32_t highaddr : 12; /* High Address */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULEADDR. */ +typedef volatile struct ALT_SDR_CTL_PROTRULEADDR_s ALT_SDR_CTL_PROTRULEADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULEADDR register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULEADDR_OFST 0x90 + +/* + * Register : Memory Protection ID Register - protruleid + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------ + * [11:0] | RW | Unknown | Low ID + * [23:12] | RW | Unknown | High ID + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Low ID - lowid + * + * AxID for the protection rule. Incoming AxID needs to be greater than or equal + * to this value. For all AxIDs from a port, AxID high should be programmed to all + * ones. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_MSB 11 +/* The width in bits of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_SET_MSK 0x00000fff +/* The mask used to clear the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_CLR_MSK 0xfffff000 +/* The reset value of the ALT_SDR_CTL_PROTRULEID_LOWID register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEID_LOWID field value from a register. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_GET(value) (((value) & 0x00000fff) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULEID_LOWID register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEID_LOWID_SET(value) (((value) << 0) & 0x00000fff) + +/* + * Field : High ID - highid + * + * AxID for the protection rule. Incoming AxID needs to be less than or equal to + * this value. For all AxIDs from a port, AxID high should be programmed to all + * ones. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_MSB 23 +/* The width in bits of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_WIDTH 12 +/* The mask used to set the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_SET_MSK 0x00fff000 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_CLR_MSK 0xff000fff +/* The reset value of the ALT_SDR_CTL_PROTRULEID_HIGHID register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEID_HIGHID field value from a register. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_GET(value) (((value) & 0x00fff000) >> 12) +/* Produces a ALT_SDR_CTL_PROTRULEID_HIGHID register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEID_HIGHID_SET(value) (((value) << 12) & 0x00fff000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULEID. + */ +struct ALT_SDR_CTL_PROTRULEID_s +{ + uint32_t lowid : 12; /* Low ID */ + uint32_t highid : 12; /* High ID */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULEID. */ +typedef volatile struct ALT_SDR_CTL_PROTRULEID_s ALT_SDR_CTL_PROTRULEID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULEID register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULEID_OFST 0x94 + +/* + * Register : Memory Protection Rule Data Register - protruledata + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:---------------------- + * [1:0] | RW | Unknown | Security Bit Behavior + * [2] | RW | Unknown | Valid Rule + * [12:3] | RW | Unknown | Port Mask + * [13] | RW | Unknown | Rule Results + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Security Bit Behavior - security + * + * A value of 2'b00 will make the rule apply to secure transactions. + * + * A value of 2'b01 will make the rule apply to non-secure transactions. + * + * A value of 2'b10 or 2'b11 will make the rule apply to secure and non-secure + * transactions. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_MSB 1 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_WIDTH 2 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_SECURITY field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Valid Rule - validrule + * + * Set to bit to a one to make a rule valid, set to a zero to invalidate a rule. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_MSB 2 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Port Mask - portmask + * + * Set bit x to a one to have this rule apply to port x, set bit x to a zero to + * have the rule not apply to a port. Note that port 0-port 5 are the FPGA + * fabric ports, port 6 is L3 read, port 7 is CPU read, port 8 is L3 write, port 9 + * is CPU write. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_MSB 12 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET_MSK 0x00001ff8 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_CLR_MSK 0xffffe007 +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_PORTMSK field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_GET(value) (((value) & 0x00001ff8) >> 3) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET(value) (((value) << 3) & 0x00001ff8) + +/* + * Field : Rule Results - ruleresult + * + * Set this bit to a one to force a protection failure, zero to allow the access + * the succeed + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_MSB 13 +/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULEDATA_RULERESULT field value from a register. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULEDATA. + */ +struct ALT_SDR_CTL_PROTRULEDATA_s +{ + uint32_t security : 2; /* Security Bit Behavior */ + uint32_t validrule : 1; /* Valid Rule */ + uint32_t portmask : 10; /* Port Mask */ + uint32_t ruleresult : 1; /* Rule Results */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULEDATA. */ +typedef volatile struct ALT_SDR_CTL_PROTRULEDATA_s ALT_SDR_CTL_PROTRULEDATA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULEDATA register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULEDATA_OFST 0x98 + +/* + * Register : Memory Protection Rule Read-Write Register - protrulerdwr + * + * This register is used to perform read and write operations to the internal + * protection table. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [4:0] | RW | Unknown | Rule Offset + * [5] | RW | Unknown | Rule Write + * [6] | RW | Unknown | Rule Read + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Rule Offset - ruleoffset + * + * This field defines which of the 20 rules in the protection table you want to + * read or write. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB 4 +/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH 5 +/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK 0x0000001f +/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET field value from a register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value) (((value) << 0) & 0x0000001f) + +/* + * Field : Rule Write - writerule + * + * Write to this bit to have the memory_prot_data register to the table at the + * offset specified by port_offset. Bit automatically clears after a single cycle + * and the write operation is complete. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB 5 +/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULERDWR_WRRULE field value from a register. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Rule Read - readrule + * + * Write to this bit to have the memory_prot_data register loaded with the value + * from the internal protection table at offset. Table value will be loaded before + * a rdy is returned so read data from the register will be correct for any follow- + * on reads to the memory_prot_data register. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB 6 +/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH 1 +/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field is UNKNOWN. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET 0x0 +/* Extracts the ALT_SDR_CTL_PROTRULERDWR_RDRULE field value from a register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value suitable for setting the register. */ +#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_PROTRULERDWR. + */ +struct ALT_SDR_CTL_PROTRULERDWR_s +{ + uint32_t ruleoffset : 5; /* Rule Offset */ + uint32_t writerule : 1; /* Rule Write */ + uint32_t readrule : 1; /* Rule Read */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_PROTRULERDWR. */ +typedef volatile struct ALT_SDR_CTL_PROTRULERDWR_s ALT_SDR_CTL_PROTRULERDWR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_PROTRULERDWR register from the beginning of the component. */ +#define ALT_SDR_CTL_PROTRULERDWR_OFST 0x9c + +/* + * Register : QOS Control Register - qoslowpri + * + * This register controls the mapping of AXI4 QOS received from the FPGA fabric to + * the internal priority used for traffic prioritization. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:----------------------- + * [19:0] | RW | Unknown | Low Priority QoS Value + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Low Priority QoS Value - lowpriorityval + * + * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for + * each port in this register controls the priority used for a port + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_MSB 19 +/* The width in bits of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_WIDTH 20 +/* The mask used to set the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET_MSK 0x000fffff +/* The mask used to clear the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_CLR_MSK 0xfff00000 +/* The reset value of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field is UNKNOWN. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL field value from a register. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0) +/* Produces a ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_QOSLOWPRI. + */ +struct ALT_SDR_CTL_QOSLOWPRI_s +{ + uint32_t lowpriorityval : 20; /* Low Priority QoS Value */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_QOSLOWPRI. */ +typedef volatile struct ALT_SDR_CTL_QOSLOWPRI_s ALT_SDR_CTL_QOSLOWPRI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_QOSLOWPRI register from the beginning of the component. */ +#define ALT_SDR_CTL_QOSLOWPRI_OFST 0xa0 + +/* + * Register : qoshighpri Register - qoshighpri + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:------------------------ + * [19:0] | RW | Unknown | High Priority QoS Value + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : High Priority QoS Value - highpriorityval + * + * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for + * each port in this register controls the priority used for a port + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_MSB 19 +/* The width in bits of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_WIDTH 20 +/* The mask used to set the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET_MSK 0x000fffff +/* The mask used to clear the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_CLR_MSK 0xfff00000 +/* The reset value of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field is UNKNOWN. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_RESET 0x0 +/* Extracts the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL field value from a register. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0) +/* Produces a ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value suitable for setting the register. */ +#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_QOSHIGHPRI. + */ +struct ALT_SDR_CTL_QOSHIGHPRI_s +{ + uint32_t highpriorityval : 20; /* High Priority QoS Value */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_QOSHIGHPRI. */ +typedef volatile struct ALT_SDR_CTL_QOSHIGHPRI_s ALT_SDR_CTL_QOSHIGHPRI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_QOSHIGHPRI register from the beginning of the component. */ +#define ALT_SDR_CTL_QOSHIGHPRI_OFST 0xa4 + +/* + * Register : qospriorityen Register - qospriorityen + * + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:-------------------- + * [9:0] | RW | Unknown | Per-Port QoS Enable + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Per-Port QoS Enable - priorityen + * + * This 10 bit field is set to a one to enable QOS usage for a port. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_MSB 9 +/* The width in bits of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_WIDTH 10 +/* The mask used to set the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET_MSK 0x000003ff +/* The mask used to clear the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_CLR_MSK 0xfffffc00 +/* The reset value of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field is UNKNOWN. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_RESET 0x0 +/* Extracts the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN field value from a register. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_GET(value) (((value) & 0x000003ff) >> 0) +/* Produces a ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value suitable for setting the register. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET(value) (((value) << 0) & 0x000003ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_QOSPRIORITYEN. + */ +struct ALT_SDR_CTL_QOSPRIORITYEN_s +{ + uint32_t priorityen : 10; /* Per-Port QoS Enable */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_QOSPRIORITYEN. */ +typedef volatile struct ALT_SDR_CTL_QOSPRIORITYEN_s ALT_SDR_CTL_QOSPRIORITYEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_QOSPRIORITYEN register from the beginning of the component. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_OFST 0xa8 + +/* + * Register : Scheduler priority Register - mppriority + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------- + * [29:0] | RW | Unknown | Port User Priorities + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port User Priorities - userpriority + * + * Set absolute user priority of the port. Each port is represented by a 3 bit + * value, 000=lowest priority, 111=highest priority. Port 0 is bits 2:0. Port + * number offset corresponds to the control port assignment. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_MSB 29 +/* The width in bits of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_WIDTH 30 +/* The mask used to set the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET_MSK 0x3fffffff +/* The mask used to clear the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_CLR_MSK 0xc0000000 +/* The reset value of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY field value from a register. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_GET(value) (((value) & 0x3fffffff) >> 0) +/* Produces a ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET(value) (((value) << 0) & 0x3fffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPPRIORITY. + */ +struct ALT_SDR_CTL_MPPRIORITY_s +{ + uint32_t userpriority : 30; /* Port User Priorities */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPPRIORITY. */ +typedef volatile struct ALT_SDR_CTL_MPPRIORITY_s ALT_SDR_CTL_MPPRIORITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPPRIORITY register from the beginning of the component. */ +#define ALT_SDR_CTL_MPPRIORITY_OFST 0xac + +/* + * Register : Controller Command Pool Priority Remap Register - remappriority + * + * This register controls the priority for transactions in the controller command + * pool. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------- + * [7:0] | RW | Unknown | Priority Remap + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Priority Remap - priorityremap + * + * Set bit N of this register to the value to a one to enable the controller + * command pool priority bit of a transaction from MPFE priority N + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_MSB 7 +/* The width in bits of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_WIDTH 8 +/* The mask used to set the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field is UNKNOWN. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_RESET 0x0 +/* Extracts the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP field value from a register. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value suitable for setting the register. */ +#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_REMAPPRIORITY. + */ +struct ALT_SDR_CTL_REMAPPRIORITY_s +{ + uint32_t priorityremap : 8; /* Priority Remap */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_REMAPPRIORITY. */ +typedef volatile struct ALT_SDR_CTL_REMAPPRIORITY_s ALT_SDR_CTL_REMAPPRIORITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_REMAPPRIORITY register from the beginning of the component. */ +#define ALT_SDR_CTL_REMAPPRIORITY_OFST 0xe0 + +/* + * Register Group : Port Sum of Weight Register - ALT_SDR_CTL_MPWT + * Port Sum of Weight Register + * + * This register is used to configure the DRAM burst operation scheduling. + * + */ +/* + * Register : Port Sum of Weight Register[1/4] - mpweight_0_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:-------------------------- + * [31:0] | RW | Unknown | Port Static Weights[31:0] + * + */ +/* + * Field : Port Static Weights[31:0] - staticweight_31_0 + * + * Set static weight of the port. Each port is programmed with a 5 bit value. + * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_MSB 31 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s +{ + uint32_t staticweight_31_0 : 32; /* Port Static Weights[31:0] */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST 0x0 +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST)) + +/* + * Register : Port Sum of Weight Register[2/4] - mpweight_1_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [17:0] | RW | Unknown | Port Static Weights[49:32] + * [31:18] | RW | Unknown | Port Sum of Weights[13:0] + * + */ +/* + * Field : Port Static Weights[49:32] - staticweight_49_32 + * + * Set static weight of the port. Each port is programmed with a 5 bit value. + * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_MSB 17 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_WIDTH 18 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET_MSK 0x0003ffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_CLR_MSK 0xfffc0000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_GET(value) (((value) & 0x0003ffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET(value) (((value) << 0) & 0x0003ffff) + +/* + * Field : Port Sum of Weights[13:0] - sumofweights_13_0 + * + * Set the sum of static weights for particular user priority. This register is + * used as part of the deficit round robin implementation. It should be set to the + * sum of the weights for the ports + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_MSB 31 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_WIDTH 14 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET_MSK 0xfffc0000 +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_CLR_MSK 0x0003ffff +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_GET(value) (((value) & 0xfffc0000) >> 18) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET(value) (((value) << 18) & 0xfffc0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s +{ + uint32_t staticweight_49_32 : 18; /* Port Static Weights[49:32] */ + uint32_t sumofweights_13_0 : 14; /* Port Sum of Weights[13:0] */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST 0x4 +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST)) + +/* + * Register : Port Sum of Weight Register[3/4] - mpweight_2_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:--------------------------- + * [31:0] | RW | Unknown | Port Sum of Weights[45:14] + * + */ +/* + * Field : Port Sum of Weights[45:14] - sumofweights_45_14 + * + * Set the sum of static weights for particular user priority. This register is + * used as part of the deficit round robin implementation. It should be set to the + * sum of the weights for the ports + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_MSB 31 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_WIDTH 32 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_CLR_MSK 0x00000000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s +{ + uint32_t sumofweights_45_14 : 32; /* Port Sum of Weights[45:14] */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST 0x8 +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST)) + +/* + * Register : Port Sum of Weight Register[4/4] - mpweight_3_4 + * + * This register is used to configure the DRAM burst operation scheduling. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------------- + * [17:0] | RW | Unknown | Port Sum of Weights[63:46] + * [31:18] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port Sum of Weights[63:46] - sumofweights_63_46 + * + * Set the sum of static weights for particular user priority. This register is + * used as part of the deficit round robin implementation. It should be set to the + * sum of the weights for the ports + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_MSB 17 +/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_WIDTH 18 +/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET_MSK 0x0003ffff +/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_CLR_MSK 0xfffc0000 +/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field is UNKNOWN. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_RESET 0x0 +/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 field value from a register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_GET(value) (((value) & 0x0003ffff) >> 0) +/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value suitable for setting the register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET(value) (((value) << 0) & 0x0003ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. + */ +struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s +{ + uint32_t sumofweights_63_46 : 18; /* Port Sum of Weights[63:46] */ + uint32_t : 14; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. */ +typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register from the beginning of the component. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST 0xc +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register. */ +#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SDR_CTL_MPWT. + */ +struct ALT_SDR_CTL_MPWT_s +{ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */ + volatile ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */ +}; + +/* The typedef declaration for register group ALT_SDR_CTL_MPWT. */ +typedef volatile struct ALT_SDR_CTL_MPWT_s ALT_SDR_CTL_MPWT_t; +/* The struct declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */ +struct ALT_SDR_CTL_MPWT_raw_s +{ + volatile uint32_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */ + volatile uint32_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */ + volatile uint32_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */ + volatile uint32_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */ +typedef volatile struct ALT_SDR_CTL_MPWT_raw_s ALT_SDR_CTL_MPWT_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SDR_CTL. + */ +struct ALT_SDR_CTL_s +{ + volatile ALT_SDR_CTL_CTLCFG_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */ + volatile ALT_SDR_CTL_DRAMTIMING1_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */ + volatile ALT_SDR_CTL_DRAMTIMING2_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */ + volatile ALT_SDR_CTL_DRAMTIMING3_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */ + volatile ALT_SDR_CTL_DRAMTIMING4_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */ + volatile ALT_SDR_CTL_LOWPWRTIMING_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */ + volatile ALT_SDR_CTL_DRAMODT_t dramodt; /* ALT_SDR_CTL_DRAMODT */ + volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_DRAMADDRW_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */ + volatile ALT_SDR_CTL_DRAMIFWIDTH_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */ + volatile ALT_SDR_CTL_DRAMDEVWIDTH_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */ + volatile ALT_SDR_CTL_DRAMSTS_t dramsts; /* ALT_SDR_CTL_DRAMSTS */ + volatile ALT_SDR_CTL_DRAMINTR_t dramintr; /* ALT_SDR_CTL_DRAMINTR */ + volatile ALT_SDR_CTL_SBECOUNT_t sbecount; /* ALT_SDR_CTL_SBECOUNT */ + volatile ALT_SDR_CTL_DBECOUNT_t dbecount; /* ALT_SDR_CTL_DBECOUNT */ + volatile ALT_SDR_CTL_ERRADDR_t erraddr; /* ALT_SDR_CTL_ERRADDR */ + volatile ALT_SDR_CTL_DROPCOUNT_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */ + volatile ALT_SDR_CTL_DROPADDR_t dropaddr; /* ALT_SDR_CTL_DROPADDR */ + volatile ALT_SDR_CTL_LOWPWREQ_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */ + volatile ALT_SDR_CTL_LOWPWRACK_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */ + volatile ALT_SDR_CTL_STATICCFG_t staticcfg; /* ALT_SDR_CTL_STATICCFG */ + volatile ALT_SDR_CTL_CTLWIDTH_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */ + volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_PORTCFG_t portcfg; /* ALT_SDR_CTL_PORTCFG */ + volatile ALT_SDR_CTL_FPGAPORTRST_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */ + volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_PROTPORTDEFAULT_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */ + volatile ALT_SDR_CTL_PROTRULEADDR_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */ + volatile ALT_SDR_CTL_PROTRULEID_t protruleid; /* ALT_SDR_CTL_PROTRULEID */ + volatile ALT_SDR_CTL_PROTRULEDATA_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */ + volatile ALT_SDR_CTL_PROTRULERDWR_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */ + volatile ALT_SDR_CTL_QOSLOWPRI_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */ + volatile ALT_SDR_CTL_QOSHIGHPRI_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */ + volatile ALT_SDR_CTL_QOSPRIORITYEN_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */ + volatile ALT_SDR_CTL_MPPRIORITY_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */ + volatile ALT_SDR_CTL_MPWT_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */ + volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_REMAPPRIORITY_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */ + volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SDR_CTL. */ +typedef volatile struct ALT_SDR_CTL_s ALT_SDR_CTL_t; +/* The struct declaration for the raw register contents of register group ALT_SDR_CTL. */ +struct ALT_SDR_CTL_raw_s +{ + volatile uint32_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */ + volatile uint32_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */ + volatile uint32_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */ + volatile uint32_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */ + volatile uint32_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */ + volatile uint32_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */ + volatile uint32_t dramodt; /* ALT_SDR_CTL_DRAMODT */ + volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */ + volatile uint32_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */ + volatile uint32_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */ + volatile uint32_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */ + volatile uint32_t dramsts; /* ALT_SDR_CTL_DRAMSTS */ + volatile uint32_t dramintr; /* ALT_SDR_CTL_DRAMINTR */ + volatile uint32_t sbecount; /* ALT_SDR_CTL_SBECOUNT */ + volatile uint32_t dbecount; /* ALT_SDR_CTL_DBECOUNT */ + volatile uint32_t erraddr; /* ALT_SDR_CTL_ERRADDR */ + volatile uint32_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */ + volatile uint32_t dropaddr; /* ALT_SDR_CTL_DROPADDR */ + volatile uint32_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */ + volatile uint32_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */ + volatile uint32_t staticcfg; /* ALT_SDR_CTL_STATICCFG */ + volatile uint32_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */ + volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */ + volatile uint32_t portcfg; /* ALT_SDR_CTL_PORTCFG */ + volatile uint32_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */ + volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */ + volatile uint32_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */ + volatile uint32_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */ + volatile uint32_t protruleid; /* ALT_SDR_CTL_PROTRULEID */ + volatile uint32_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */ + volatile uint32_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */ + volatile uint32_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */ + volatile uint32_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */ + volatile uint32_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */ + volatile uint32_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */ + volatile ALT_SDR_CTL_MPWT_raw_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */ + volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */ + volatile uint32_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */ + volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SDR_CTL. */ +typedef volatile struct ALT_SDR_CTL_raw_s ALT_SDR_CTL_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SDR. + */ +struct ALT_SDR_s +{ + volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_t ctrlgrp; /* ALT_SDR_CTL */ + volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SDR. */ +typedef volatile struct ALT_SDR_s ALT_SDR_t; +/* The struct declaration for the raw register contents of register group ALT_SDR. */ +struct ALT_SDR_raw_s +{ + volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */ + volatile ALT_SDR_CTL_raw_t ctrlgrp; /* ALT_SDR_CTL */ + volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SDR. */ +typedef volatile struct ALT_SDR_raw_s ALT_SDR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_SDR_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_spim.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_spim.h new file mode 100644 index 000000000..fa1c38dec --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_spim.h @@ -0,0 +1,3293 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_SPIM */ + +#ifndef __ALTERA_ALT_SPIM_H__ +#define __ALTERA_ALT_SPIM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : SPI Master Module - ALT_SPIM + * SPI Master Module + * + * Registers in the SPI Master module + * + */ +/* + * Register : Control Register 0 - ctrlr0 + * + * This register controls the serial data transfer. It is impossible to write to + * this register when the SPI Master is enabled. The SPI Master is enabled and + * disabled by writing to the SPIENR register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------- + * [3:0] | RW | 0x7 | Data Frame Size + * [5:4] | RW | 0x0 | Frame Format + * [6] | RW | 0x0 | Serial Clock Phase + * [7] | RW | 0x0 | Serial Clock Polarity + * [9:8] | RW | 0x0 | Transfer Mode + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | Shift Register Loop + * [15:12] | RW | 0x0 | Control Frame Size + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Frame Size - dfs + * + * Selects the data frame length. When the data frame size is programmed to be less + * than 16 bits, the receive data are automatically right-justified by the receive + * logic, with the upper bits of the receive FIFO zero-padded. You must right- + * justify transmit data before writing into the transmit FIFO. The transmit logic + * ignores the upper unused bits when transmitting the data. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------- + * ALT_SPIM_CTLR0_DFS_E_WIDTH4BIT | 0x3 | 4-bit serial data transfer + * ALT_SPIM_CTLR0_DFS_E_WIDTH5BIT | 0x4 | 5-bit serial data transfer + * ALT_SPIM_CTLR0_DFS_E_WIDTH6BIT | 0x5 | 6-bit serial data transfer + * ALT_SPIM_CTLR0_DFS_E_WIDTH7BIT | 0x6 | 7-bit serial data transfer + * ALT_SPIM_CTLR0_DFS_E_WIDTH8BIT | 0x7 | 8-bit serial data transfer + * ALT_SPIM_CTLR0_DFS_E_WIDTH9BIT | 0x8 | 9-bit serial data transfer + * ALT_SPIM_CTLR0_DFS_E_WIDTH10BIT | 0x9 | 10-bit serial data transfer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_CTLR0_DFS + * + * 4-bit serial data transfer + */ +#define ALT_SPIM_CTLR0_DFS_E_WIDTH4BIT 0x3 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_DFS + * + * 5-bit serial data transfer + */ +#define ALT_SPIM_CTLR0_DFS_E_WIDTH5BIT 0x4 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_DFS + * + * 6-bit serial data transfer + */ +#define ALT_SPIM_CTLR0_DFS_E_WIDTH6BIT 0x5 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_DFS + * + * 7-bit serial data transfer + */ +#define ALT_SPIM_CTLR0_DFS_E_WIDTH7BIT 0x6 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_DFS + * + * 8-bit serial data transfer + */ +#define ALT_SPIM_CTLR0_DFS_E_WIDTH8BIT 0x7 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_DFS + * + * 9-bit serial data transfer + */ +#define ALT_SPIM_CTLR0_DFS_E_WIDTH9BIT 0x8 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_DFS + * + * 10-bit serial data transfer + */ +#define ALT_SPIM_CTLR0_DFS_E_WIDTH10BIT 0x9 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_DFS register field. */ +#define ALT_SPIM_CTLR0_DFS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_DFS register field. */ +#define ALT_SPIM_CTLR0_DFS_MSB 3 +/* The width in bits of the ALT_SPIM_CTLR0_DFS register field. */ +#define ALT_SPIM_CTLR0_DFS_WIDTH 4 +/* The mask used to set the ALT_SPIM_CTLR0_DFS register field value. */ +#define ALT_SPIM_CTLR0_DFS_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SPIM_CTLR0_DFS register field value. */ +#define ALT_SPIM_CTLR0_DFS_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SPIM_CTLR0_DFS register field. */ +#define ALT_SPIM_CTLR0_DFS_RESET 0x7 +/* Extracts the ALT_SPIM_CTLR0_DFS field value from a register. */ +#define ALT_SPIM_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SPIM_CTLR0_DFS register field value suitable for setting the register. */ +#define ALT_SPIM_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Frame Format - frf + * + * Selects which serial protocol transfers the data. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------ + * ALT_SPIM_CTLR0_FRF_E_MOTSPI | 0x0 | Motorola SPI + * ALT_SPIM_CTLR0_FRF_E_TISSP | 0x1 | Texas Instruments SSP + * ALT_SPIM_CTLR0_FRF_E_NATMW | 0x2 | National Semi Microwire + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_CTLR0_FRF + * + * Motorola SPI + */ +#define ALT_SPIM_CTLR0_FRF_E_MOTSPI 0x0 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_FRF + * + * Texas Instruments SSP + */ +#define ALT_SPIM_CTLR0_FRF_E_TISSP 0x1 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_FRF + * + * National Semi Microwire + */ +#define ALT_SPIM_CTLR0_FRF_E_NATMW 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_FRF register field. */ +#define ALT_SPIM_CTLR0_FRF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_FRF register field. */ +#define ALT_SPIM_CTLR0_FRF_MSB 5 +/* The width in bits of the ALT_SPIM_CTLR0_FRF register field. */ +#define ALT_SPIM_CTLR0_FRF_WIDTH 2 +/* The mask used to set the ALT_SPIM_CTLR0_FRF register field value. */ +#define ALT_SPIM_CTLR0_FRF_SET_MSK 0x00000030 +/* The mask used to clear the ALT_SPIM_CTLR0_FRF register field value. */ +#define ALT_SPIM_CTLR0_FRF_CLR_MSK 0xffffffcf +/* The reset value of the ALT_SPIM_CTLR0_FRF register field. */ +#define ALT_SPIM_CTLR0_FRF_RESET 0x0 +/* Extracts the ALT_SPIM_CTLR0_FRF field value from a register. */ +#define ALT_SPIM_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_SPIM_CTLR0_FRF register field value suitable for setting the register. */ +#define ALT_SPIM_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030) + +/* + * Field : Serial Clock Phase - scph + * + * Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase + * selects the relationship of the serial clock with the slave select signal. When + * SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = + * 1, the serial clock starts toggling one cycle after the slave select line is + * activated, and data are captured on the second edge of the serial clock. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------------------------------------- + * ALT_SPIM_CTLR0_SCPH_E_MIDBIT | 0x0 | Serial clock toggles in middle of first data bit + * ALT_SPIM_CTLR0_SCPH_E_STARTBIT | 0x1 | Serial clock toggles at start of first data bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_CTLR0_SCPH + * + * Serial clock toggles in middle of first data bit + */ +#define ALT_SPIM_CTLR0_SCPH_E_MIDBIT 0x0 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_SCPH + * + * Serial clock toggles at start of first data bit + */ +#define ALT_SPIM_CTLR0_SCPH_E_STARTBIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_SCPH register field. */ +#define ALT_SPIM_CTLR0_SCPH_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_SCPH register field. */ +#define ALT_SPIM_CTLR0_SCPH_MSB 6 +/* The width in bits of the ALT_SPIM_CTLR0_SCPH register field. */ +#define ALT_SPIM_CTLR0_SCPH_WIDTH 1 +/* The mask used to set the ALT_SPIM_CTLR0_SCPH register field value. */ +#define ALT_SPIM_CTLR0_SCPH_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SPIM_CTLR0_SCPH register field value. */ +#define ALT_SPIM_CTLR0_SCPH_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SPIM_CTLR0_SCPH register field. */ +#define ALT_SPIM_CTLR0_SCPH_RESET 0x0 +/* Extracts the ALT_SPIM_CTLR0_SCPH field value from a register. */ +#define ALT_SPIM_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SPIM_CTLR0_SCPH register field value suitable for setting the register. */ +#define ALT_SPIM_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Serial Clock Polarity - scpol + * + * Valid when the frame format (FRF) is set to Motorola SPI. Used to select the + * polarity of the inactive serial clock, which is held inactive when the SPI + * Master is not actively transferring data on the serial bus. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:--------------------------------------- + * ALT_SPIM_CTLR0_SCPOL_E_INACTLOW | 0x0 | Inactive state of serial clock is low + * ALT_SPIM_CTLR0_SCPOL_E_INACTHIGH | 0x1 | Inactive state of serial clock is high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_CTLR0_SCPOL + * + * Inactive state of serial clock is low + */ +#define ALT_SPIM_CTLR0_SCPOL_E_INACTLOW 0x0 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_SCPOL + * + * Inactive state of serial clock is high + */ +#define ALT_SPIM_CTLR0_SCPOL_E_INACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_SCPOL register field. */ +#define ALT_SPIM_CTLR0_SCPOL_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_SCPOL register field. */ +#define ALT_SPIM_CTLR0_SCPOL_MSB 7 +/* The width in bits of the ALT_SPIM_CTLR0_SCPOL register field. */ +#define ALT_SPIM_CTLR0_SCPOL_WIDTH 1 +/* The mask used to set the ALT_SPIM_CTLR0_SCPOL register field value. */ +#define ALT_SPIM_CTLR0_SCPOL_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SPIM_CTLR0_SCPOL register field value. */ +#define ALT_SPIM_CTLR0_SCPOL_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SPIM_CTLR0_SCPOL register field. */ +#define ALT_SPIM_CTLR0_SCPOL_RESET 0x0 +/* Extracts the ALT_SPIM_CTLR0_SCPOL field value from a register. */ +#define ALT_SPIM_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SPIM_CTLR0_SCPOL register field value suitable for setting the register. */ +#define ALT_SPIM_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transfer Mode - tmod + * + * Selects the mode of transfer for serial communication. This field does not + * affect the transfer duplicity. Only indicates whether the receive or transmit + * data are valid. In transmit-only mode, data received from the external device is + * not valid and is not stored in the receive FIFO memory. It is overwritten on the + * next transfer. In receive-only mode, transmitted data are not valid. After the + * first write to the transmit FIFO, the same word is retransmitted for the + * duration of the transfer. In transmit-and-receive mode, both transmit and + * receive data are valid. The transfer continues until the transmit FIFO is empty. + * Data received from the external device are stored into the receive FIFO memory, + * where it can be accessed by the host processor. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:----------------------- + * ALT_SPIM_CTLR0_TMOD_E_TXRX | 0x0 | Transmit & and Receive + * ALT_SPIM_CTLR0_TMOD_E_TXONLY | 0x1 | Transmit Only + * ALT_SPIM_CTLR0_TMOD_E_RXONLY | 0x2 | Receive Only + * ALT_SPIM_CTLR0_TMOD_E_EERD | 0x3 | EEPROM Read + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_CTLR0_TMOD + * + * Transmit & and Receive + */ +#define ALT_SPIM_CTLR0_TMOD_E_TXRX 0x0 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_TMOD + * + * Transmit Only + */ +#define ALT_SPIM_CTLR0_TMOD_E_TXONLY 0x1 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_TMOD + * + * Receive Only + */ +#define ALT_SPIM_CTLR0_TMOD_E_RXONLY 0x2 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_TMOD + * + * EEPROM Read + */ +#define ALT_SPIM_CTLR0_TMOD_E_EERD 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_TMOD register field. */ +#define ALT_SPIM_CTLR0_TMOD_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_TMOD register field. */ +#define ALT_SPIM_CTLR0_TMOD_MSB 9 +/* The width in bits of the ALT_SPIM_CTLR0_TMOD register field. */ +#define ALT_SPIM_CTLR0_TMOD_WIDTH 2 +/* The mask used to set the ALT_SPIM_CTLR0_TMOD register field value. */ +#define ALT_SPIM_CTLR0_TMOD_SET_MSK 0x00000300 +/* The mask used to clear the ALT_SPIM_CTLR0_TMOD register field value. */ +#define ALT_SPIM_CTLR0_TMOD_CLR_MSK 0xfffffcff +/* The reset value of the ALT_SPIM_CTLR0_TMOD register field. */ +#define ALT_SPIM_CTLR0_TMOD_RESET 0x0 +/* Extracts the ALT_SPIM_CTLR0_TMOD field value from a register. */ +#define ALT_SPIM_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_SPIM_CTLR0_TMOD register field value suitable for setting the register. */ +#define ALT_SPIM_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : Shift Register Loop - srl + * + * Used for testing purposes only. When internally active, connects the transmit + * shift register output to the receive shift register input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------- + * ALT_SPIM_CTLR0_SRL_E_NORMMOD | 0x0 | Normal Mode Operation + * ALT_SPIM_CTLR0_SRL_E_TESTMOD | 0x1 | Test Mode Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_CTLR0_SRL + * + * Normal Mode Operation + */ +#define ALT_SPIM_CTLR0_SRL_E_NORMMOD 0x0 +/* + * Enumerated value for register field ALT_SPIM_CTLR0_SRL + * + * Test Mode Operation + */ +#define ALT_SPIM_CTLR0_SRL_E_TESTMOD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_SRL register field. */ +#define ALT_SPIM_CTLR0_SRL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_SRL register field. */ +#define ALT_SPIM_CTLR0_SRL_MSB 11 +/* The width in bits of the ALT_SPIM_CTLR0_SRL register field. */ +#define ALT_SPIM_CTLR0_SRL_WIDTH 1 +/* The mask used to set the ALT_SPIM_CTLR0_SRL register field value. */ +#define ALT_SPIM_CTLR0_SRL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SPIM_CTLR0_SRL register field value. */ +#define ALT_SPIM_CTLR0_SRL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SPIM_CTLR0_SRL register field. */ +#define ALT_SPIM_CTLR0_SRL_RESET 0x0 +/* Extracts the ALT_SPIM_CTLR0_SRL field value from a register. */ +#define ALT_SPIM_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SPIM_CTLR0_SRL register field value suitable for setting the register. */ +#define ALT_SPIM_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Control Frame Size - cfs + * + * Selects the length of the control word for the Microwire frame format. The + * length (in bits) is the value of this field plus 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_CFS register field. */ +#define ALT_SPIM_CTLR0_CFS_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_CFS register field. */ +#define ALT_SPIM_CTLR0_CFS_MSB 15 +/* The width in bits of the ALT_SPIM_CTLR0_CFS register field. */ +#define ALT_SPIM_CTLR0_CFS_WIDTH 4 +/* The mask used to set the ALT_SPIM_CTLR0_CFS register field value. */ +#define ALT_SPIM_CTLR0_CFS_SET_MSK 0x0000f000 +/* The mask used to clear the ALT_SPIM_CTLR0_CFS register field value. */ +#define ALT_SPIM_CTLR0_CFS_CLR_MSK 0xffff0fff +/* The reset value of the ALT_SPIM_CTLR0_CFS register field. */ +#define ALT_SPIM_CTLR0_CFS_RESET 0x0 +/* Extracts the ALT_SPIM_CTLR0_CFS field value from a register. */ +#define ALT_SPIM_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12) +/* Produces a ALT_SPIM_CTLR0_CFS register field value suitable for setting the register. */ +#define ALT_SPIM_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_CTLR0. + */ +struct ALT_SPIM_CTLR0_s +{ + uint32_t dfs : 4; /* Data Frame Size */ + uint32_t frf : 2; /* Frame Format */ + uint32_t scph : 1; /* Serial Clock Phase */ + uint32_t scpol : 1; /* Serial Clock Polarity */ + uint32_t tmod : 2; /* Transfer Mode */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t srl : 1; /* Shift Register Loop */ + uint32_t cfs : 4; /* Control Frame Size */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_CTLR0. */ +typedef volatile struct ALT_SPIM_CTLR0_s ALT_SPIM_CTLR0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_CTLR0 register from the beginning of the component. */ +#define ALT_SPIM_CTLR0_OFST 0x0 +/* The address of the ALT_SPIM_CTLR0 register. */ +#define ALT_SPIM_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR0_OFST)) + +/* + * Register : Control Register 1 - ctrlr1 + * + * Control register 1 controls the end of serial transfers when in receive-only + * mode. It is impossible to write to this register when the SPI Master is + * enabled.The SPI Master is enabled and disabled by writing to the SPIENR + * register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------- + * [15:0] | RW | 0x0 | Number of Data Frames + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Number of Data Frames - ndf + * + * When TMOD = 10 or TMOD =11, this register field sets the number of data frames + * to be continuously received by the SPI Master. The SPI Master continues to + * receive serial data until the number of data frames received is equal to this + * register value plus 1, which enables you to receive up to 64 KB of data in a + * continuous transfer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR1_NDF register field. */ +#define ALT_SPIM_CTLR1_NDF_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR1_NDF register field. */ +#define ALT_SPIM_CTLR1_NDF_MSB 15 +/* The width in bits of the ALT_SPIM_CTLR1_NDF register field. */ +#define ALT_SPIM_CTLR1_NDF_WIDTH 16 +/* The mask used to set the ALT_SPIM_CTLR1_NDF register field value. */ +#define ALT_SPIM_CTLR1_NDF_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SPIM_CTLR1_NDF register field value. */ +#define ALT_SPIM_CTLR1_NDF_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SPIM_CTLR1_NDF register field. */ +#define ALT_SPIM_CTLR1_NDF_RESET 0x0 +/* Extracts the ALT_SPIM_CTLR1_NDF field value from a register. */ +#define ALT_SPIM_CTLR1_NDF_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SPIM_CTLR1_NDF register field value suitable for setting the register. */ +#define ALT_SPIM_CTLR1_NDF_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_CTLR1. + */ +struct ALT_SPIM_CTLR1_s +{ + uint32_t ndf : 16; /* Number of Data Frames */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_CTLR1. */ +typedef volatile struct ALT_SPIM_CTLR1_s ALT_SPIM_CTLR1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_CTLR1 register from the beginning of the component. */ +#define ALT_SPIM_CTLR1_OFST 0x4 +/* The address of the ALT_SPIM_CTLR1 register. */ +#define ALT_SPIM_CTLR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR1_OFST)) + +/* + * Register : Enable Register - spienr + * + * Enables and Disables all SPI operations. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x0 | Enable + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable - spi_en + * + * Enables and disables all SPI Master operations. When disabled, all serial + * transfers are halted immediately. Transmit and receive FIFO buffers are cleared + * when the device is disabled. It is impossible to program some of the SPI Master + * control registers when enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------ + * ALT_SPIM_SPIENR_SPI_EN_E_DISD | 0x0 | Disables serial transfer operations + * ALT_SPIM_SPIENR_SPI_EN_E_END | 0x1 | Enables serial transfer operations + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_SPIENR_SPI_EN + * + * Disables serial transfer operations + */ +#define ALT_SPIM_SPIENR_SPI_EN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SPIM_SPIENR_SPI_EN + * + * Enables serial transfer operations + */ +#define ALT_SPIM_SPIENR_SPI_EN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_SPIENR_SPI_EN register field. */ +#define ALT_SPIM_SPIENR_SPI_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_SPIENR_SPI_EN register field. */ +#define ALT_SPIM_SPIENR_SPI_EN_MSB 0 +/* The width in bits of the ALT_SPIM_SPIENR_SPI_EN register field. */ +#define ALT_SPIM_SPIENR_SPI_EN_WIDTH 1 +/* The mask used to set the ALT_SPIM_SPIENR_SPI_EN register field value. */ +#define ALT_SPIM_SPIENR_SPI_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_SPIENR_SPI_EN register field value. */ +#define ALT_SPIM_SPIENR_SPI_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_SPIENR_SPI_EN register field. */ +#define ALT_SPIM_SPIENR_SPI_EN_RESET 0x0 +/* Extracts the ALT_SPIM_SPIENR_SPI_EN field value from a register. */ +#define ALT_SPIM_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_SPIENR_SPI_EN register field value suitable for setting the register. */ +#define ALT_SPIM_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_SPIENR. + */ +struct ALT_SPIM_SPIENR_s +{ + uint32_t spi_en : 1; /* Enable */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_SPIENR. */ +typedef volatile struct ALT_SPIM_SPIENR_s ALT_SPIM_SPIENR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_SPIENR register from the beginning of the component. */ +#define ALT_SPIM_SPIENR_OFST 0x8 +/* The address of the ALT_SPIM_SPIENR register. */ +#define ALT_SPIM_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SPIENR_OFST)) + +/* + * Register : Microwire Control Register - mwcr + * + * This register controls the direction of the data word for the half-duplex + * Microwire serial protocol. It is impossible to write to this register when the + * SPI Master is enabled. The SPI Master is enabled and disabled by writing to the + * SPIENR register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | Microwire Transfer Mode + * [1] | RW | 0x0 | Microwire Control + * [2] | RW | 0x0 | Microwire Handshaking + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Microwire Transfer Mode - mwmod + * + * Defines whether the Microwire transfer is sequential or non-sequential. When + * sequential mode is used, only one control word is needed to transmit or receive + * a block of data words. When non-sequential mode is used, there must be a control + * word for each data word that is transmitted or received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------------ + * ALT_SPIM_MWCR_MWMOD_E_NONSEQ | 0x0 | non-sequential transfer + * ALT_SPIM_MWCR_MWMOD_E_SEQ | 0x1 | sequential transfer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_MWCR_MWMOD + * + * non-sequential transfer + */ +#define ALT_SPIM_MWCR_MWMOD_E_NONSEQ 0x0 +/* + * Enumerated value for register field ALT_SPIM_MWCR_MWMOD + * + * sequential transfer + */ +#define ALT_SPIM_MWCR_MWMOD_E_SEQ 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MWMOD register field. */ +#define ALT_SPIM_MWCR_MWMOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MWMOD register field. */ +#define ALT_SPIM_MWCR_MWMOD_MSB 0 +/* The width in bits of the ALT_SPIM_MWCR_MWMOD register field. */ +#define ALT_SPIM_MWCR_MWMOD_WIDTH 1 +/* The mask used to set the ALT_SPIM_MWCR_MWMOD register field value. */ +#define ALT_SPIM_MWCR_MWMOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_MWCR_MWMOD register field value. */ +#define ALT_SPIM_MWCR_MWMOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_MWCR_MWMOD register field. */ +#define ALT_SPIM_MWCR_MWMOD_RESET 0x0 +/* Extracts the ALT_SPIM_MWCR_MWMOD field value from a register. */ +#define ALT_SPIM_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_MWCR_MWMOD register field value suitable for setting the register. */ +#define ALT_SPIM_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Microwire Control - mdd + * + * Defines the direction of the data word when the Microwire serial protocol is + * used. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:-------------------------- + * ALT_SPIM_MWCR_MDD_E_RXMOD | 0x0 | SPI Master receives data + * ALT_SPIM_MWCR_MDD_E_TXMOD | 0x1 | SPI Master transmits data + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_MWCR_MDD + * + * SPI Master receives data + */ +#define ALT_SPIM_MWCR_MDD_E_RXMOD 0x0 +/* + * Enumerated value for register field ALT_SPIM_MWCR_MDD + * + * SPI Master transmits data + */ +#define ALT_SPIM_MWCR_MDD_E_TXMOD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MDD register field. */ +#define ALT_SPIM_MWCR_MDD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MDD register field. */ +#define ALT_SPIM_MWCR_MDD_MSB 1 +/* The width in bits of the ALT_SPIM_MWCR_MDD register field. */ +#define ALT_SPIM_MWCR_MDD_WIDTH 1 +/* The mask used to set the ALT_SPIM_MWCR_MDD register field value. */ +#define ALT_SPIM_MWCR_MDD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIM_MWCR_MDD register field value. */ +#define ALT_SPIM_MWCR_MDD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIM_MWCR_MDD register field. */ +#define ALT_SPIM_MWCR_MDD_RESET 0x0 +/* Extracts the ALT_SPIM_MWCR_MDD field value from a register. */ +#define ALT_SPIM_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIM_MWCR_MDD register field value suitable for setting the register. */ +#define ALT_SPIM_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Microwire Handshaking - mhs + * + * Used to enable and disable the busy/ready handshaking interface for the + * Microwire protocol. When enabled, the SPI Master checks for a ready status from + * the target slave, after the transfer of the last data/control bit, before + * clearing the BUSY status in the SR register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:---------------------------------- + * ALT_SPIM_MWCR_MHS_E_DISD | 0x0 | Handshaking interface is disabled + * ALT_SPIM_MWCR_MHS_E_END | 0x1 | Handshaking interface is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_MWCR_MHS + * + * Handshaking interface is disabled + */ +#define ALT_SPIM_MWCR_MHS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SPIM_MWCR_MHS + * + * Handshaking interface is enabled + */ +#define ALT_SPIM_MWCR_MHS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MHS register field. */ +#define ALT_SPIM_MWCR_MHS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MHS register field. */ +#define ALT_SPIM_MWCR_MHS_MSB 2 +/* The width in bits of the ALT_SPIM_MWCR_MHS register field. */ +#define ALT_SPIM_MWCR_MHS_WIDTH 1 +/* The mask used to set the ALT_SPIM_MWCR_MHS register field value. */ +#define ALT_SPIM_MWCR_MHS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SPIM_MWCR_MHS register field value. */ +#define ALT_SPIM_MWCR_MHS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SPIM_MWCR_MHS register field. */ +#define ALT_SPIM_MWCR_MHS_RESET 0x0 +/* Extracts the ALT_SPIM_MWCR_MHS field value from a register. */ +#define ALT_SPIM_MWCR_MHS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SPIM_MWCR_MHS register field value suitable for setting the register. */ +#define ALT_SPIM_MWCR_MHS_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_MWCR. + */ +struct ALT_SPIM_MWCR_s +{ + uint32_t mwmod : 1; /* Microwire Transfer Mode */ + uint32_t mdd : 1; /* Microwire Control */ + uint32_t mhs : 1; /* Microwire Handshaking */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_MWCR. */ +typedef volatile struct ALT_SPIM_MWCR_s ALT_SPIM_MWCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_MWCR register from the beginning of the component. */ +#define ALT_SPIM_MWCR_OFST 0xc +/* The address of the ALT_SPIM_MWCR register. */ +#define ALT_SPIM_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MWCR_OFST)) + +/* + * Register : Slave Enable Register - ser + * + * The register enables the individual slave select output lines from the SPI + * Master. Up to 4 slave-select output pins are available on the SPI Master. You + * cannot write to this register when SPI Master is busy and when SPI_EN = 1. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [3:0] | RW | 0x0 | Slave Select Enable Flag + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Slave Select Enable Flag - ser + * + * Each bit in this register corresponds to a slave select line (spim_ss_x_n] from + * the SPI Master. When a bit in this register is set (1), the corresponding slave + * select line from the master is activated when a serial transfer begins. It + * should be noted that setting or clearing bits in this register have no effect on + * the corresponding slave select outputs until a transfer is started. Before + * beginning a transfer, you should enable the bit in this register that + * corresponds to the slave device with which the master wants to communicate. When + * not operating in broadcast mode, only one bit in this field should be set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:--------------------- + * ALT_SPIM_SER_SER_E_NOTSELECTED | 0x0 | Slave x Not Selected + * ALT_SPIM_SER_SER_E_SELECTED | 0x1 | Slave x Selected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_SER_SER + * + * Slave x Not Selected + */ +#define ALT_SPIM_SER_SER_E_NOTSELECTED 0x0 +/* + * Enumerated value for register field ALT_SPIM_SER_SER + * + * Slave x Selected + */ +#define ALT_SPIM_SER_SER_E_SELECTED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_SER_SER register field. */ +#define ALT_SPIM_SER_SER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_SER_SER register field. */ +#define ALT_SPIM_SER_SER_MSB 3 +/* The width in bits of the ALT_SPIM_SER_SER register field. */ +#define ALT_SPIM_SER_SER_WIDTH 4 +/* The mask used to set the ALT_SPIM_SER_SER register field value. */ +#define ALT_SPIM_SER_SER_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SPIM_SER_SER register field value. */ +#define ALT_SPIM_SER_SER_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SPIM_SER_SER register field. */ +#define ALT_SPIM_SER_SER_RESET 0x0 +/* Extracts the ALT_SPIM_SER_SER field value from a register. */ +#define ALT_SPIM_SER_SER_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SPIM_SER_SER register field value suitable for setting the register. */ +#define ALT_SPIM_SER_SER_SET(value) (((value) << 0) & 0x0000000f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_SER. + */ +struct ALT_SPIM_SER_s +{ + uint32_t ser : 4; /* Slave Select Enable Flag */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_SER. */ +typedef volatile struct ALT_SPIM_SER_s ALT_SPIM_SER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_SER register from the beginning of the component. */ +#define ALT_SPIM_SER_OFST 0x10 +/* The address of the ALT_SPIM_SER register. */ +#define ALT_SPIM_SER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SER_OFST)) + +/* + * Register : Baud Rate Select Register - baudr + * + * This register derives the frequency of the serial clock that regulates the data + * transfer. The 16-bit field in this register defines the spi_m_clk divider value. + * It is impossible to write to this register when the SPI Master is enabled. The + * SPI Master is enabled and disabled by writing to the SPIENR register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------ + * [15:0] | RW | 0x0 | SPI Clock Divider + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SPI Clock Divider - sckdv + * + * The LSB for this field is always set to 0 and is unaffected by a write + * operation, which ensures an even value is held in this register. If the value is + * 0, the serial output clock (spim_sclk_out) is disabled. The frequency of the + * spim_sclk_out is derived from the following equation: + * + * Fspim_sclk_out = Fspi_m_clk/SCKDV + * + * where SCKDV is any even value between 2 and 65534. For example: + * + * for Fspi_m_clk = 3.6864MHz and SCKDV =2 + * + * Fspim_sclk_out = 3.6864/2 = 1.8432MHz + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_BAUDR_SCKDV register field. */ +#define ALT_SPIM_BAUDR_SCKDV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_BAUDR_SCKDV register field. */ +#define ALT_SPIM_BAUDR_SCKDV_MSB 15 +/* The width in bits of the ALT_SPIM_BAUDR_SCKDV register field. */ +#define ALT_SPIM_BAUDR_SCKDV_WIDTH 16 +/* The mask used to set the ALT_SPIM_BAUDR_SCKDV register field value. */ +#define ALT_SPIM_BAUDR_SCKDV_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SPIM_BAUDR_SCKDV register field value. */ +#define ALT_SPIM_BAUDR_SCKDV_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SPIM_BAUDR_SCKDV register field. */ +#define ALT_SPIM_BAUDR_SCKDV_RESET 0x0 +/* Extracts the ALT_SPIM_BAUDR_SCKDV field value from a register. */ +#define ALT_SPIM_BAUDR_SCKDV_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SPIM_BAUDR_SCKDV register field value suitable for setting the register. */ +#define ALT_SPIM_BAUDR_SCKDV_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_BAUDR. + */ +struct ALT_SPIM_BAUDR_s +{ + uint32_t sckdv : 16; /* SPI Clock Divider */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_BAUDR. */ +typedef volatile struct ALT_SPIM_BAUDR_s ALT_SPIM_BAUDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_BAUDR register from the beginning of the component. */ +#define ALT_SPIM_BAUDR_OFST 0x14 +/* The address of the ALT_SPIM_BAUDR register. */ +#define ALT_SPIM_BAUDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_BAUDR_OFST)) + +/* + * Register : Transmit FIFO Threshold Level Register - txftlr + * + * This register controls the threshold value for the transmit FIFO memory. It is + * impossible to write to this register when the SPI Master is enabled. The SPI + * Master is enabled and disabled by writing to the SPIENR register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [7:0] | RW | 0x0 | Transmit FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Threshold Level - tft + * + * Controls the level of entries (or below) at which the transmit FIFO controller + * triggers an interrupt. When the number of transmit FIFO entries is less than or + * equal to this value, the transmit FIFO empty interrupt is triggered. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_TXFTLR_TFT register field. */ +#define ALT_SPIM_TXFTLR_TFT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_TXFTLR_TFT register field. */ +#define ALT_SPIM_TXFTLR_TFT_MSB 7 +/* The width in bits of the ALT_SPIM_TXFTLR_TFT register field. */ +#define ALT_SPIM_TXFTLR_TFT_WIDTH 8 +/* The mask used to set the ALT_SPIM_TXFTLR_TFT register field value. */ +#define ALT_SPIM_TXFTLR_TFT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SPIM_TXFTLR_TFT register field value. */ +#define ALT_SPIM_TXFTLR_TFT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SPIM_TXFTLR_TFT register field. */ +#define ALT_SPIM_TXFTLR_TFT_RESET 0x0 +/* Extracts the ALT_SPIM_TXFTLR_TFT field value from a register. */ +#define ALT_SPIM_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SPIM_TXFTLR_TFT register field value suitable for setting the register. */ +#define ALT_SPIM_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_TXFTLR. + */ +struct ALT_SPIM_TXFTLR_s +{ + uint32_t tft : 8; /* Transmit FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_TXFTLR. */ +typedef volatile struct ALT_SPIM_TXFTLR_s ALT_SPIM_TXFTLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_TXFTLR register from the beginning of the component. */ +#define ALT_SPIM_TXFTLR_OFST 0x18 +/* The address of the ALT_SPIM_TXFTLR register. */ +#define ALT_SPIM_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFTLR_OFST)) + +/* + * Register : Receive FIFO Threshold Level Register - rxftlr + * + * This register controls the threshold value for the receive FIFO memory. It is + * impossible to write to this register when the SPI Master is enabled. The SPI + * Master is enabled and disabled by writing to the SPIENR register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [7:0] | RW | 0x0 | Receive FIFO Threshold Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Threshold Level - rft + * + * Controls the level of entries (or above) at which the receive FIFO controller + * triggers an interrupt. When the number of receive FIFO entries is greater than + * or equal to this value + 1, the receive FIFO full interrupt is triggered. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_RXFTLR_RFT register field. */ +#define ALT_SPIM_RXFTLR_RFT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_RXFTLR_RFT register field. */ +#define ALT_SPIM_RXFTLR_RFT_MSB 7 +/* The width in bits of the ALT_SPIM_RXFTLR_RFT register field. */ +#define ALT_SPIM_RXFTLR_RFT_WIDTH 8 +/* The mask used to set the ALT_SPIM_RXFTLR_RFT register field value. */ +#define ALT_SPIM_RXFTLR_RFT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SPIM_RXFTLR_RFT register field value. */ +#define ALT_SPIM_RXFTLR_RFT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SPIM_RXFTLR_RFT register field. */ +#define ALT_SPIM_RXFTLR_RFT_RESET 0x0 +/* Extracts the ALT_SPIM_RXFTLR_RFT field value from a register. */ +#define ALT_SPIM_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SPIM_RXFTLR_RFT register field value suitable for setting the register. */ +#define ALT_SPIM_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_RXFTLR. + */ +struct ALT_SPIM_RXFTLR_s +{ + uint32_t rft : 8; /* Receive FIFO Threshold Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_RXFTLR. */ +typedef volatile struct ALT_SPIM_RXFTLR_s ALT_SPIM_RXFTLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_RXFTLR register from the beginning of the component. */ +#define ALT_SPIM_RXFTLR_OFST 0x1c +/* The address of the ALT_SPIM_RXFTLR register. */ +#define ALT_SPIM_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFTLR_OFST)) + +/* + * Register : Transmit FIFO Level Register - txflr + * + * This register contains the number of valid data entries in the transmit FIFO + * memory. Ranges from 0 to 256. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [8:0] | R | 0x0 | Transmit FIFO Level + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Level - txtfl + * + * Contains the number of valid data entries in the transmit FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_TXFLR_TXTFL register field. */ +#define ALT_SPIM_TXFLR_TXTFL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_TXFLR_TXTFL register field. */ +#define ALT_SPIM_TXFLR_TXTFL_MSB 8 +/* The width in bits of the ALT_SPIM_TXFLR_TXTFL register field. */ +#define ALT_SPIM_TXFLR_TXTFL_WIDTH 9 +/* The mask used to set the ALT_SPIM_TXFLR_TXTFL register field value. */ +#define ALT_SPIM_TXFLR_TXTFL_SET_MSK 0x000001ff +/* The mask used to clear the ALT_SPIM_TXFLR_TXTFL register field value. */ +#define ALT_SPIM_TXFLR_TXTFL_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_SPIM_TXFLR_TXTFL register field. */ +#define ALT_SPIM_TXFLR_TXTFL_RESET 0x0 +/* Extracts the ALT_SPIM_TXFLR_TXTFL field value from a register. */ +#define ALT_SPIM_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_SPIM_TXFLR_TXTFL register field value suitable for setting the register. */ +#define ALT_SPIM_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_TXFLR. + */ +struct ALT_SPIM_TXFLR_s +{ + const uint32_t txtfl : 9; /* Transmit FIFO Level */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_TXFLR. */ +typedef volatile struct ALT_SPIM_TXFLR_s ALT_SPIM_TXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_TXFLR register from the beginning of the component. */ +#define ALT_SPIM_TXFLR_OFST 0x20 +/* The address of the ALT_SPIM_TXFLR register. */ +#define ALT_SPIM_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFLR_OFST)) + +/* + * Register : Receive FIFO Level Register - rxflr + * + * This register contains the number of valid data entries in the receive FIFO + * memory. This register can be read at any time. Ranges from 0 to 256. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [8:0] | R | 0x0 | Receive FIFO Level + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Level - rxtfl + * + * Contains the number of valid data entries in the receive FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_RXFLR_RXTFL register field. */ +#define ALT_SPIM_RXFLR_RXTFL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_RXFLR_RXTFL register field. */ +#define ALT_SPIM_RXFLR_RXTFL_MSB 8 +/* The width in bits of the ALT_SPIM_RXFLR_RXTFL register field. */ +#define ALT_SPIM_RXFLR_RXTFL_WIDTH 9 +/* The mask used to set the ALT_SPIM_RXFLR_RXTFL register field value. */ +#define ALT_SPIM_RXFLR_RXTFL_SET_MSK 0x000001ff +/* The mask used to clear the ALT_SPIM_RXFLR_RXTFL register field value. */ +#define ALT_SPIM_RXFLR_RXTFL_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_SPIM_RXFLR_RXTFL register field. */ +#define ALT_SPIM_RXFLR_RXTFL_RESET 0x0 +/* Extracts the ALT_SPIM_RXFLR_RXTFL field value from a register. */ +#define ALT_SPIM_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_SPIM_RXFLR_RXTFL register field value suitable for setting the register. */ +#define ALT_SPIM_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_RXFLR. + */ +struct ALT_SPIM_RXFLR_s +{ + const uint32_t rxtfl : 9; /* Receive FIFO Level */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_RXFLR. */ +typedef volatile struct ALT_SPIM_RXFLR_s ALT_SPIM_RXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_RXFLR register from the beginning of the component. */ +#define ALT_SPIM_RXFLR_OFST 0x24 +/* The address of the ALT_SPIM_RXFLR register. */ +#define ALT_SPIM_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFLR_OFST)) + +/* + * Register : Status Register - sr + * + * This register is used to indicate the current transfer status, FIFO status, and + * any transmission/reception errors that may have occurred. The status register + * may be read at any time. None of the bits in this register request an interrupt. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | SPI Busy Flag + * [1] | R | 0x1 | Transmit FIFO Not Full + * [2] | R | 0x1 | Transmit FIFO Empty + * [3] | R | 0x0 | Receive FIFO Not Empty + * [4] | R | 0x0 | Receive FIFO Full + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SPI Busy Flag - busy + * + * Reports the staus of a serial transfer + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:------------------------------------------ + * ALT_SPIM_SR_BUSY_E_INACT | 0x0 | SPI Master is inactive (idle or disabled) + * ALT_SPIM_SR_BUSY_E_ACT | 0x1 | SPI Master is actively transferring data + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_SR_BUSY + * + * SPI Master is inactive (idle or disabled) + */ +#define ALT_SPIM_SR_BUSY_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_SR_BUSY + * + * SPI Master is actively transferring data + */ +#define ALT_SPIM_SR_BUSY_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_BUSY register field. */ +#define ALT_SPIM_SR_BUSY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_BUSY register field. */ +#define ALT_SPIM_SR_BUSY_MSB 0 +/* The width in bits of the ALT_SPIM_SR_BUSY register field. */ +#define ALT_SPIM_SR_BUSY_WIDTH 1 +/* The mask used to set the ALT_SPIM_SR_BUSY register field value. */ +#define ALT_SPIM_SR_BUSY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_SR_BUSY register field value. */ +#define ALT_SPIM_SR_BUSY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_SR_BUSY register field. */ +#define ALT_SPIM_SR_BUSY_RESET 0x0 +/* Extracts the ALT_SPIM_SR_BUSY field value from a register. */ +#define ALT_SPIM_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_SR_BUSY register field value suitable for setting the register. */ +#define ALT_SPIM_SR_BUSY_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit FIFO Not Full - tfnf + * + * Reports transmit FIFO condition. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------- + * ALT_SPIM_SR_TFNF_E_FULL | 0x0 | Transmit FIFO is full + * ALT_SPIM_SR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_SR_TFNF + * + * Transmit FIFO is full + */ +#define ALT_SPIM_SR_TFNF_E_FULL 0x0 +/* + * Enumerated value for register field ALT_SPIM_SR_TFNF + * + * Transmit FIFO is not full + */ +#define ALT_SPIM_SR_TFNF_E_NOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_TFNF register field. */ +#define ALT_SPIM_SR_TFNF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_TFNF register field. */ +#define ALT_SPIM_SR_TFNF_MSB 1 +/* The width in bits of the ALT_SPIM_SR_TFNF register field. */ +#define ALT_SPIM_SR_TFNF_WIDTH 1 +/* The mask used to set the ALT_SPIM_SR_TFNF register field value. */ +#define ALT_SPIM_SR_TFNF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIM_SR_TFNF register field value. */ +#define ALT_SPIM_SR_TFNF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIM_SR_TFNF register field. */ +#define ALT_SPIM_SR_TFNF_RESET 0x1 +/* Extracts the ALT_SPIM_SR_TFNF field value from a register. */ +#define ALT_SPIM_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIM_SR_TFNF register field value suitable for setting the register. */ +#define ALT_SPIM_SR_TFNF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Transmit FIFO Empty - tfe + * + * Reports transmit FIFO condition. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------------- + * ALT_SPIM_SR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty + * ALT_SPIM_SR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_SR_TFE + * + * Transmit FIFO is empty + */ +#define ALT_SPIM_SR_TFE_E_EMPTY 0x1 +/* + * Enumerated value for register field ALT_SPIM_SR_TFE + * + * Transmit FIFO is not empty + */ +#define ALT_SPIM_SR_TFE_E_NOTEMPTY 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_TFE register field. */ +#define ALT_SPIM_SR_TFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_TFE register field. */ +#define ALT_SPIM_SR_TFE_MSB 2 +/* The width in bits of the ALT_SPIM_SR_TFE register field. */ +#define ALT_SPIM_SR_TFE_WIDTH 1 +/* The mask used to set the ALT_SPIM_SR_TFE register field value. */ +#define ALT_SPIM_SR_TFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SPIM_SR_TFE register field value. */ +#define ALT_SPIM_SR_TFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SPIM_SR_TFE register field. */ +#define ALT_SPIM_SR_TFE_RESET 0x1 +/* Extracts the ALT_SPIM_SR_TFE field value from a register. */ +#define ALT_SPIM_SR_TFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SPIM_SR_TFE register field value suitable for setting the register. */ +#define ALT_SPIM_SR_TFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Not Empty - rfne + * + * Reports receive FIFO condition. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------------- + * ALT_SPIM_SR_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty + * ALT_SPIM_SR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_SR_RFNE + * + * Receive FIFO is empty + */ +#define ALT_SPIM_SR_RFNE_E_EMPTY 0x0 +/* + * Enumerated value for register field ALT_SPIM_SR_RFNE + * + * Receive FIFO is not empty + */ +#define ALT_SPIM_SR_RFNE_E_NOTEMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_RFNE register field. */ +#define ALT_SPIM_SR_RFNE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_RFNE register field. */ +#define ALT_SPIM_SR_RFNE_MSB 3 +/* The width in bits of the ALT_SPIM_SR_RFNE register field. */ +#define ALT_SPIM_SR_RFNE_WIDTH 1 +/* The mask used to set the ALT_SPIM_SR_RFNE register field value. */ +#define ALT_SPIM_SR_RFNE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SPIM_SR_RFNE register field value. */ +#define ALT_SPIM_SR_RFNE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SPIM_SR_RFNE register field. */ +#define ALT_SPIM_SR_RFNE_RESET 0x0 +/* Extracts the ALT_SPIM_SR_RFNE field value from a register. */ +#define ALT_SPIM_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SPIM_SR_RFNE register field value suitable for setting the register. */ +#define ALT_SPIM_SR_RFNE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full - rff + * + * Reports receive FIFO condition. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------- + * ALT_SPIM_SR_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full + * ALT_SPIM_SR_RFF_E_FULL | 0x1 | Receive FIFO is full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_SR_RFF + * + * Receive FIFO is not full + */ +#define ALT_SPIM_SR_RFF_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_SPIM_SR_RFF + * + * Receive FIFO is full + */ +#define ALT_SPIM_SR_RFF_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_RFF register field. */ +#define ALT_SPIM_SR_RFF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_RFF register field. */ +#define ALT_SPIM_SR_RFF_MSB 4 +/* The width in bits of the ALT_SPIM_SR_RFF register field. */ +#define ALT_SPIM_SR_RFF_WIDTH 1 +/* The mask used to set the ALT_SPIM_SR_RFF register field value. */ +#define ALT_SPIM_SR_RFF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SPIM_SR_RFF register field value. */ +#define ALT_SPIM_SR_RFF_CLR_MSK 0xffffffef +/* The reset value of the ALT_SPIM_SR_RFF register field. */ +#define ALT_SPIM_SR_RFF_RESET 0x0 +/* Extracts the ALT_SPIM_SR_RFF field value from a register. */ +#define ALT_SPIM_SR_RFF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SPIM_SR_RFF register field value suitable for setting the register. */ +#define ALT_SPIM_SR_RFF_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_SR. + */ +struct ALT_SPIM_SR_s +{ + const uint32_t busy : 1; /* SPI Busy Flag */ + const uint32_t tfnf : 1; /* Transmit FIFO Not Full */ + const uint32_t tfe : 1; /* Transmit FIFO Empty */ + const uint32_t rfne : 1; /* Receive FIFO Not Empty */ + const uint32_t rff : 1; /* Receive FIFO Full */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_SR. */ +typedef volatile struct ALT_SPIM_SR_s ALT_SPIM_SR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_SR register from the beginning of the component. */ +#define ALT_SPIM_SR_OFST 0x28 +/* The address of the ALT_SPIM_SR register. */ +#define ALT_SPIM_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SR_OFST)) + +/* + * Register : Interrupt Mask Register - imr + * + * This register masks or enables all interrupts generated by the SPI Master. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x1 | Transmit FIFO Empty Interrupt Mask + * [1] | RW | 0x1 | Transmit FIFO Overflow Interrupt Mask + * [2] | RW | 0x1 | Receive FIFO Underflow Interrupt Mask + * [3] | RW | 0x1 | Receive FIFO Overflow Interrupt Mask + * [4] | RW | 0x1 | Receive FIFO Full Interrupt Mask + * [31:5] | ??? | 0x1 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Empty Interrupt Mask - txeim + * + * Empty mask. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIM_IMR_TXEIM_E_MSKED | 0x0 | spi_txe_intr interrupt is masked (disabled) + * ALT_SPIM_IMR_TXEIM_E_END | 0x1 | spi_txe_intr interrupt is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_IMR_TXEIM + * + * spi_txe_intr interrupt is masked (disabled) + */ +#define ALT_SPIM_IMR_TXEIM_E_MSKED 0x0 +/* + * Enumerated value for register field ALT_SPIM_IMR_TXEIM + * + * spi_txe_intr interrupt is enabled + */ +#define ALT_SPIM_IMR_TXEIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_TXEIM register field. */ +#define ALT_SPIM_IMR_TXEIM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_TXEIM register field. */ +#define ALT_SPIM_IMR_TXEIM_MSB 0 +/* The width in bits of the ALT_SPIM_IMR_TXEIM register field. */ +#define ALT_SPIM_IMR_TXEIM_WIDTH 1 +/* The mask used to set the ALT_SPIM_IMR_TXEIM register field value. */ +#define ALT_SPIM_IMR_TXEIM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_IMR_TXEIM register field value. */ +#define ALT_SPIM_IMR_TXEIM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_IMR_TXEIM register field. */ +#define ALT_SPIM_IMR_TXEIM_RESET 0x1 +/* Extracts the ALT_SPIM_IMR_TXEIM field value from a register. */ +#define ALT_SPIM_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_IMR_TXEIM register field value suitable for setting the register. */ +#define ALT_SPIM_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit FIFO Overflow Interrupt Mask - txoim + * + * Overflow Mask + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIM_IMR_TXOIM_E_MSKED | 0x0 | spi_txo_intr interrupt is masked (disabled) + * ALT_SPIM_IMR_TXOIM_E_END | 0x1 | spi_txo_intr interrupt is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_IMR_TXOIM + * + * spi_txo_intr interrupt is masked (disabled) + */ +#define ALT_SPIM_IMR_TXOIM_E_MSKED 0x0 +/* + * Enumerated value for register field ALT_SPIM_IMR_TXOIM + * + * spi_txo_intr interrupt is enabled + */ +#define ALT_SPIM_IMR_TXOIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_TXOIM register field. */ +#define ALT_SPIM_IMR_TXOIM_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_TXOIM register field. */ +#define ALT_SPIM_IMR_TXOIM_MSB 1 +/* The width in bits of the ALT_SPIM_IMR_TXOIM register field. */ +#define ALT_SPIM_IMR_TXOIM_WIDTH 1 +/* The mask used to set the ALT_SPIM_IMR_TXOIM register field value. */ +#define ALT_SPIM_IMR_TXOIM_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIM_IMR_TXOIM register field value. */ +#define ALT_SPIM_IMR_TXOIM_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIM_IMR_TXOIM register field. */ +#define ALT_SPIM_IMR_TXOIM_RESET 0x1 +/* Extracts the ALT_SPIM_IMR_TXOIM field value from a register. */ +#define ALT_SPIM_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIM_IMR_TXOIM register field value suitable for setting the register. */ +#define ALT_SPIM_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive FIFO Underflow Interrupt Mask - rxuim + * + * Underflow Mask + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIM_IMR_RXUIM_E_MSKED | 0x0 | spi_rxu_intr interrupt is masked (disabled) + * ALT_SPIM_IMR_RXUIM_E_END | 0x1 | spi_rxu_intr interrupt is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_IMR_RXUIM + * + * spi_rxu_intr interrupt is masked (disabled) + */ +#define ALT_SPIM_IMR_RXUIM_E_MSKED 0x0 +/* + * Enumerated value for register field ALT_SPIM_IMR_RXUIM + * + * spi_rxu_intr interrupt is enabled + */ +#define ALT_SPIM_IMR_RXUIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXUIM register field. */ +#define ALT_SPIM_IMR_RXUIM_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXUIM register field. */ +#define ALT_SPIM_IMR_RXUIM_MSB 2 +/* The width in bits of the ALT_SPIM_IMR_RXUIM register field. */ +#define ALT_SPIM_IMR_RXUIM_WIDTH 1 +/* The mask used to set the ALT_SPIM_IMR_RXUIM register field value. */ +#define ALT_SPIM_IMR_RXUIM_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SPIM_IMR_RXUIM register field value. */ +#define ALT_SPIM_IMR_RXUIM_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SPIM_IMR_RXUIM register field. */ +#define ALT_SPIM_IMR_RXUIM_RESET 0x1 +/* Extracts the ALT_SPIM_IMR_RXUIM field value from a register. */ +#define ALT_SPIM_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SPIM_IMR_RXUIM register field value suitable for setting the register. */ +#define ALT_SPIM_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Overflow Interrupt Mask - rxoim + * + * Overflow Mask. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIM_IMR_RXOIM_E_MSKED | 0x0 | spi_rxo_intr interrupt is masked (disabled) + * ALT_SPIM_IMR_RXOIM_E_END | 0x1 | spi_rxo_intr interrupt is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_IMR_RXOIM + * + * spi_rxo_intr interrupt is masked (disabled) + */ +#define ALT_SPIM_IMR_RXOIM_E_MSKED 0x0 +/* + * Enumerated value for register field ALT_SPIM_IMR_RXOIM + * + * spi_rxo_intr interrupt is enabled + */ +#define ALT_SPIM_IMR_RXOIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXOIM register field. */ +#define ALT_SPIM_IMR_RXOIM_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXOIM register field. */ +#define ALT_SPIM_IMR_RXOIM_MSB 3 +/* The width in bits of the ALT_SPIM_IMR_RXOIM register field. */ +#define ALT_SPIM_IMR_RXOIM_WIDTH 1 +/* The mask used to set the ALT_SPIM_IMR_RXOIM register field value. */ +#define ALT_SPIM_IMR_RXOIM_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SPIM_IMR_RXOIM register field value. */ +#define ALT_SPIM_IMR_RXOIM_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SPIM_IMR_RXOIM register field. */ +#define ALT_SPIM_IMR_RXOIM_RESET 0x1 +/* Extracts the ALT_SPIM_IMR_RXOIM field value from a register. */ +#define ALT_SPIM_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SPIM_IMR_RXOIM register field value suitable for setting the register. */ +#define ALT_SPIM_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full Interrupt Mask - rxfim + * + * Full Mask + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIM_IMR_RXFIM_E_MSKED | 0x0 | spi_rxf_intr interrupt is masked (disabled) + * ALT_SPIM_IMR_RXFIM_E_END | 0x1 | spi_rxf_intr interrupt is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_IMR_RXFIM + * + * spi_rxf_intr interrupt is masked (disabled) + */ +#define ALT_SPIM_IMR_RXFIM_E_MSKED 0x0 +/* + * Enumerated value for register field ALT_SPIM_IMR_RXFIM + * + * spi_rxf_intr interrupt is enabled + */ +#define ALT_SPIM_IMR_RXFIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXFIM register field. */ +#define ALT_SPIM_IMR_RXFIM_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXFIM register field. */ +#define ALT_SPIM_IMR_RXFIM_MSB 4 +/* The width in bits of the ALT_SPIM_IMR_RXFIM register field. */ +#define ALT_SPIM_IMR_RXFIM_WIDTH 1 +/* The mask used to set the ALT_SPIM_IMR_RXFIM register field value. */ +#define ALT_SPIM_IMR_RXFIM_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SPIM_IMR_RXFIM register field value. */ +#define ALT_SPIM_IMR_RXFIM_CLR_MSK 0xffffffef +/* The reset value of the ALT_SPIM_IMR_RXFIM register field. */ +#define ALT_SPIM_IMR_RXFIM_RESET 0x1 +/* Extracts the ALT_SPIM_IMR_RXFIM field value from a register. */ +#define ALT_SPIM_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SPIM_IMR_RXFIM register field value suitable for setting the register. */ +#define ALT_SPIM_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_IMR. + */ +struct ALT_SPIM_IMR_s +{ + uint32_t txeim : 1; /* Transmit FIFO Empty Interrupt Mask */ + uint32_t txoim : 1; /* Transmit FIFO Overflow Interrupt Mask */ + uint32_t rxuim : 1; /* Receive FIFO Underflow Interrupt Mask */ + uint32_t rxoim : 1; /* Receive FIFO Overflow Interrupt Mask */ + uint32_t rxfim : 1; /* Receive FIFO Full Interrupt Mask */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_IMR. */ +typedef volatile struct ALT_SPIM_IMR_s ALT_SPIM_IMR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_IMR register from the beginning of the component. */ +#define ALT_SPIM_IMR_OFST 0x2c +/* The address of the ALT_SPIM_IMR register. */ +#define ALT_SPIM_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IMR_OFST)) + +/* + * Register : Interrupt Status Register - isr + * + * This register reports the status of the SPI Master interrupts after they have + * been masked. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | R | 0x0 | Transmit FIFO Empty Interrupt Status + * [1] | R | 0x0 | Transmit FIFO Overflow Interrupt Status + * [2] | R | 0x0 | Receive FIFO Underflow Interrupt Status + * [3] | R | 0x0 | Receive FIFO Overflow Interrupt Status + * [4] | R | 0x0 | Receive FIFO Full Interrupt Status + * [5] | R | 0x0 | Multi-Master Contention Interrupt Status + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Empty Interrupt Status - txeis + * + * Empty status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------------------------------- + * ALT_SPIM_ISR_TXEIS_E_INACT | 0x0 | spi_txe_intr interrupt is not active after + * : | | masking + * ALT_SPIM_ISR_TXEIS_E_ACT | 0x1 | spi_txe_intr interrupt is active after masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_ISR_TXEIS + * + * spi_txe_intr interrupt is not active after masking + */ +#define ALT_SPIM_ISR_TXEIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_ISR_TXEIS + * + * spi_txe_intr interrupt is active after masking + */ +#define ALT_SPIM_ISR_TXEIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_TXEIS register field. */ +#define ALT_SPIM_ISR_TXEIS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_TXEIS register field. */ +#define ALT_SPIM_ISR_TXEIS_MSB 0 +/* The width in bits of the ALT_SPIM_ISR_TXEIS register field. */ +#define ALT_SPIM_ISR_TXEIS_WIDTH 1 +/* The mask used to set the ALT_SPIM_ISR_TXEIS register field value. */ +#define ALT_SPIM_ISR_TXEIS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_ISR_TXEIS register field value. */ +#define ALT_SPIM_ISR_TXEIS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_ISR_TXEIS register field. */ +#define ALT_SPIM_ISR_TXEIS_RESET 0x0 +/* Extracts the ALT_SPIM_ISR_TXEIS field value from a register. */ +#define ALT_SPIM_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_ISR_TXEIS register field value suitable for setting the register. */ +#define ALT_SPIM_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit FIFO Overflow Interrupt Status - txois + * + * Overflow Status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------------------------------- + * ALT_SPIM_ISR_TXOIS_E_INACT | 0x0 | spi_txo_intr interrupt is not active after + * : | | masking + * ALT_SPIM_ISR_TXOIS_E_ACT | 0x1 | spi_txo_intr interrupt is active after masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_ISR_TXOIS + * + * spi_txo_intr interrupt is not active after masking + */ +#define ALT_SPIM_ISR_TXOIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_ISR_TXOIS + * + * spi_txo_intr interrupt is active after masking + */ +#define ALT_SPIM_ISR_TXOIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_TXOIS register field. */ +#define ALT_SPIM_ISR_TXOIS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_TXOIS register field. */ +#define ALT_SPIM_ISR_TXOIS_MSB 1 +/* The width in bits of the ALT_SPIM_ISR_TXOIS register field. */ +#define ALT_SPIM_ISR_TXOIS_WIDTH 1 +/* The mask used to set the ALT_SPIM_ISR_TXOIS register field value. */ +#define ALT_SPIM_ISR_TXOIS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIM_ISR_TXOIS register field value. */ +#define ALT_SPIM_ISR_TXOIS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIM_ISR_TXOIS register field. */ +#define ALT_SPIM_ISR_TXOIS_RESET 0x0 +/* Extracts the ALT_SPIM_ISR_TXOIS field value from a register. */ +#define ALT_SPIM_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIM_ISR_TXOIS register field value suitable for setting the register. */ +#define ALT_SPIM_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive FIFO Underflow Interrupt Status - rxuis + * + * Underflow Status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------------------------------- + * ALT_SPIM_ISR_RXUIS_E_INACT | 0x0 | spi_rxu_intr interrupt is not active after + * : | | masking + * ALT_SPIM_ISR_RXUIS_E_ACT | 0x1 | spi_rxu_intr interrupt is active after masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_ISR_RXUIS + * + * spi_rxu_intr interrupt is not active after masking + */ +#define ALT_SPIM_ISR_RXUIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_ISR_RXUIS + * + * spi_rxu_intr interrupt is active after masking + */ +#define ALT_SPIM_ISR_RXUIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXUIS register field. */ +#define ALT_SPIM_ISR_RXUIS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXUIS register field. */ +#define ALT_SPIM_ISR_RXUIS_MSB 2 +/* The width in bits of the ALT_SPIM_ISR_RXUIS register field. */ +#define ALT_SPIM_ISR_RXUIS_WIDTH 1 +/* The mask used to set the ALT_SPIM_ISR_RXUIS register field value. */ +#define ALT_SPIM_ISR_RXUIS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SPIM_ISR_RXUIS register field value. */ +#define ALT_SPIM_ISR_RXUIS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SPIM_ISR_RXUIS register field. */ +#define ALT_SPIM_ISR_RXUIS_RESET 0x0 +/* Extracts the ALT_SPIM_ISR_RXUIS field value from a register. */ +#define ALT_SPIM_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SPIM_ISR_RXUIS register field value suitable for setting the register. */ +#define ALT_SPIM_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Overflow Interrupt Status - rxois + * + * Overflow Status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------------------------------- + * ALT_SPIM_ISR_RXOIS_E_INACT | 0x0 | spi_rxo_intr interrupt is not active after + * : | | masking + * ALT_SPIM_ISR_RXOIS_E_ACT | 0x1 | spi_rxo_intr interrupt is active after masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_ISR_RXOIS + * + * spi_rxo_intr interrupt is not active after masking + */ +#define ALT_SPIM_ISR_RXOIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_ISR_RXOIS + * + * spi_rxo_intr interrupt is active after masking + */ +#define ALT_SPIM_ISR_RXOIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXOIS register field. */ +#define ALT_SPIM_ISR_RXOIS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXOIS register field. */ +#define ALT_SPIM_ISR_RXOIS_MSB 3 +/* The width in bits of the ALT_SPIM_ISR_RXOIS register field. */ +#define ALT_SPIM_ISR_RXOIS_WIDTH 1 +/* The mask used to set the ALT_SPIM_ISR_RXOIS register field value. */ +#define ALT_SPIM_ISR_RXOIS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SPIM_ISR_RXOIS register field value. */ +#define ALT_SPIM_ISR_RXOIS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SPIM_ISR_RXOIS register field. */ +#define ALT_SPIM_ISR_RXOIS_RESET 0x0 +/* Extracts the ALT_SPIM_ISR_RXOIS field value from a register. */ +#define ALT_SPIM_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SPIM_ISR_RXOIS register field value suitable for setting the register. */ +#define ALT_SPIM_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full Interrupt Status - rxfis + * + * Full Status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------------------------------- + * ALT_SPIM_ISR_RXFIS_E_INACT | 0x0 | spi_rxf_intr interrupt is not active after + * : | | masking + * ALT_SPIM_ISR_RXFIS_E_ACT | 0x1 | spi_rxf_intr interrupt is full after masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_ISR_RXFIS + * + * spi_rxf_intr interrupt is not active after masking + */ +#define ALT_SPIM_ISR_RXFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_ISR_RXFIS + * + * spi_rxf_intr interrupt is full after masking + */ +#define ALT_SPIM_ISR_RXFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXFIS register field. */ +#define ALT_SPIM_ISR_RXFIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXFIS register field. */ +#define ALT_SPIM_ISR_RXFIS_MSB 4 +/* The width in bits of the ALT_SPIM_ISR_RXFIS register field. */ +#define ALT_SPIM_ISR_RXFIS_WIDTH 1 +/* The mask used to set the ALT_SPIM_ISR_RXFIS register field value. */ +#define ALT_SPIM_ISR_RXFIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SPIM_ISR_RXFIS register field value. */ +#define ALT_SPIM_ISR_RXFIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_SPIM_ISR_RXFIS register field. */ +#define ALT_SPIM_ISR_RXFIS_RESET 0x0 +/* Extracts the ALT_SPIM_ISR_RXFIS field value from a register. */ +#define ALT_SPIM_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SPIM_ISR_RXFIS register field value suitable for setting the register. */ +#define ALT_SPIM_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Multi-Master Contention Interrupt Status - mstis + * + * Multi-master contention status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIM_ISR_MSTIS_E_INACT | 0x0 | 0 = ssi_mst_intr interrupt not active after + * : | | masking + * ALT_SPIM_ISR_MSTIS_E_ACT | 0x1 | 1 = ssi_mst_intr interrupt is active after + * : | | masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_ISR_MSTIS + * + * 0 = ssi_mst_intr interrupt not active after masking + */ +#define ALT_SPIM_ISR_MSTIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_ISR_MSTIS + * + * 1 = ssi_mst_intr interrupt is active after masking + */ +#define ALT_SPIM_ISR_MSTIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_MSTIS register field. */ +#define ALT_SPIM_ISR_MSTIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_MSTIS register field. */ +#define ALT_SPIM_ISR_MSTIS_MSB 5 +/* The width in bits of the ALT_SPIM_ISR_MSTIS register field. */ +#define ALT_SPIM_ISR_MSTIS_WIDTH 1 +/* The mask used to set the ALT_SPIM_ISR_MSTIS register field value. */ +#define ALT_SPIM_ISR_MSTIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SPIM_ISR_MSTIS register field value. */ +#define ALT_SPIM_ISR_MSTIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SPIM_ISR_MSTIS register field. */ +#define ALT_SPIM_ISR_MSTIS_RESET 0x0 +/* Extracts the ALT_SPIM_ISR_MSTIS field value from a register. */ +#define ALT_SPIM_ISR_MSTIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SPIM_ISR_MSTIS register field value suitable for setting the register. */ +#define ALT_SPIM_ISR_MSTIS_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_ISR. + */ +struct ALT_SPIM_ISR_s +{ + const uint32_t txeis : 1; /* Transmit FIFO Empty Interrupt Status */ + const uint32_t txois : 1; /* Transmit FIFO Overflow Interrupt Status */ + const uint32_t rxuis : 1; /* Receive FIFO Underflow Interrupt Status */ + const uint32_t rxois : 1; /* Receive FIFO Overflow Interrupt Status */ + const uint32_t rxfis : 1; /* Receive FIFO Full Interrupt Status */ + const uint32_t mstis : 1; /* Multi-Master Contention Interrupt Status */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_ISR. */ +typedef volatile struct ALT_SPIM_ISR_s ALT_SPIM_ISR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_ISR register from the beginning of the component. */ +#define ALT_SPIM_ISR_OFST 0x30 +/* The address of the ALT_SPIM_ISR register. */ +#define ALT_SPIM_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ISR_OFST)) + +/* + * Register : Raw Interrupt Status Register - risr + * + * This register reports the status of the SPI Master interrupts prior to masking. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transmit FIFO Empty Raw Interrupt Status + * [1] | R | 0x0 | Transmit FIFO Overflow Raw Interrupt Status + * [2] | R | 0x0 | Receive FIFO Underflow Raw Interrupt Status + * [3] | R | 0x0 | Receive FIFO Overflow Raw Interrupt Status + * [4] | R | 0x0 | Receive FIFO Full Raw Interrupt Status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Empty Raw Interrupt Status - txeir + * + * The interrupt is active or inactive prior to masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------------------------------- + * ALT_SPIM_RISR_TXEIR_E_INACT | 0x0 | spi_txe_intr interrupt is not active prior to + * : | | masking + * ALT_SPIM_RISR_TXEIR_E_ACT | 0x1 | spi_txe_intr interrupt is active prior masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_RISR_TXEIR + * + * spi_txe_intr interrupt is not active prior to masking + */ +#define ALT_SPIM_RISR_TXEIR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_RISR_TXEIR + * + * spi_txe_intr interrupt is active prior masking + */ +#define ALT_SPIM_RISR_TXEIR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_TXEIR register field. */ +#define ALT_SPIM_RISR_TXEIR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_TXEIR register field. */ +#define ALT_SPIM_RISR_TXEIR_MSB 0 +/* The width in bits of the ALT_SPIM_RISR_TXEIR register field. */ +#define ALT_SPIM_RISR_TXEIR_WIDTH 1 +/* The mask used to set the ALT_SPIM_RISR_TXEIR register field value. */ +#define ALT_SPIM_RISR_TXEIR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_RISR_TXEIR register field value. */ +#define ALT_SPIM_RISR_TXEIR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_RISR_TXEIR register field. */ +#define ALT_SPIM_RISR_TXEIR_RESET 0x0 +/* Extracts the ALT_SPIM_RISR_TXEIR field value from a register. */ +#define ALT_SPIM_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_RISR_TXEIR register field value suitable for setting the register. */ +#define ALT_SPIM_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit FIFO Overflow Raw Interrupt Status - txoir + * + * The interrupt is active or inactive prior to masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------------------------------- + * ALT_SPIM_RISR_TXOIR_E_INACT | 0x0 | spi_txo_intr interrupt is not active prior to + * : | | masking + * ALT_SPIM_RISR_TXOIR_E_ACT | 0x1 | spi_txo_intr interrupt is active prior masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_RISR_TXOIR + * + * spi_txo_intr interrupt is not active prior to masking + */ +#define ALT_SPIM_RISR_TXOIR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_RISR_TXOIR + * + * spi_txo_intr interrupt is active prior masking + */ +#define ALT_SPIM_RISR_TXOIR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_TXOIR register field. */ +#define ALT_SPIM_RISR_TXOIR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_TXOIR register field. */ +#define ALT_SPIM_RISR_TXOIR_MSB 1 +/* The width in bits of the ALT_SPIM_RISR_TXOIR register field. */ +#define ALT_SPIM_RISR_TXOIR_WIDTH 1 +/* The mask used to set the ALT_SPIM_RISR_TXOIR register field value. */ +#define ALT_SPIM_RISR_TXOIR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIM_RISR_TXOIR register field value. */ +#define ALT_SPIM_RISR_TXOIR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIM_RISR_TXOIR register field. */ +#define ALT_SPIM_RISR_TXOIR_RESET 0x0 +/* Extracts the ALT_SPIM_RISR_TXOIR field value from a register. */ +#define ALT_SPIM_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIM_RISR_TXOIR register field value suitable for setting the register. */ +#define ALT_SPIM_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive FIFO Underflow Raw Interrupt Status - rxuir + * + * The interrupt is active or inactive prior to masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------------------------- + * ALT_SPIM_RISR_RXUIR_E_INACT | 0x0 | spi_rxu_intr interrupt is not active prior to + * : | | masking + * ALT_SPIM_RISR_RXUIR_E_ACT | 0x1 | spi_rxu_intr interrupt is active prior to + * : | | masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_RISR_RXUIR + * + * spi_rxu_intr interrupt is not active prior to masking + */ +#define ALT_SPIM_RISR_RXUIR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_RISR_RXUIR + * + * spi_rxu_intr interrupt is active prior to masking + */ +#define ALT_SPIM_RISR_RXUIR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXUIR register field. */ +#define ALT_SPIM_RISR_RXUIR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXUIR register field. */ +#define ALT_SPIM_RISR_RXUIR_MSB 2 +/* The width in bits of the ALT_SPIM_RISR_RXUIR register field. */ +#define ALT_SPIM_RISR_RXUIR_WIDTH 1 +/* The mask used to set the ALT_SPIM_RISR_RXUIR register field value. */ +#define ALT_SPIM_RISR_RXUIR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SPIM_RISR_RXUIR register field value. */ +#define ALT_SPIM_RISR_RXUIR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SPIM_RISR_RXUIR register field. */ +#define ALT_SPIM_RISR_RXUIR_RESET 0x0 +/* Extracts the ALT_SPIM_RISR_RXUIR field value from a register. */ +#define ALT_SPIM_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SPIM_RISR_RXUIR register field value suitable for setting the register. */ +#define ALT_SPIM_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Overflow Raw Interrupt Status - rxoir + * + * The interrupt is active or inactive prior to masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------------------------------- + * ALT_SPIM_RISR_RXOIR_E_INACTOVE | 0x0 | spi_rxo_intr interrupt is not active prior to + * : | | masking + * ALT_SPIM_RISR_RXOIR_E_ACT | 0x1 | spi_rxo_intr interrupt is active prior masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_RISR_RXOIR + * + * spi_rxo_intr interrupt is not active prior to masking + */ +#define ALT_SPIM_RISR_RXOIR_E_INACTOVE 0x0 +/* + * Enumerated value for register field ALT_SPIM_RISR_RXOIR + * + * spi_rxo_intr interrupt is active prior masking + */ +#define ALT_SPIM_RISR_RXOIR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXOIR register field. */ +#define ALT_SPIM_RISR_RXOIR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXOIR register field. */ +#define ALT_SPIM_RISR_RXOIR_MSB 3 +/* The width in bits of the ALT_SPIM_RISR_RXOIR register field. */ +#define ALT_SPIM_RISR_RXOIR_WIDTH 1 +/* The mask used to set the ALT_SPIM_RISR_RXOIR register field value. */ +#define ALT_SPIM_RISR_RXOIR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SPIM_RISR_RXOIR register field value. */ +#define ALT_SPIM_RISR_RXOIR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SPIM_RISR_RXOIR register field. */ +#define ALT_SPIM_RISR_RXOIR_RESET 0x0 +/* Extracts the ALT_SPIM_RISR_RXOIR field value from a register. */ +#define ALT_SPIM_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SPIM_RISR_RXOIR register field value suitable for setting the register. */ +#define ALT_SPIM_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full Raw Interrupt Status - rxfir + * + * The interrupt is active or inactive prior to masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------------------------- + * ALT_SPIM_RISR_RXFIR_E_INACT | 0x0 | spi_rxf_intr interrupt is not active prior to + * : | | masking + * ALT_SPIM_RISR_RXFIR_E_ACT | 0x1 | spi_rxf_intr interrupt is active prior to + * : | | masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_RISR_RXFIR + * + * spi_rxf_intr interrupt is not active prior to masking + */ +#define ALT_SPIM_RISR_RXFIR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIM_RISR_RXFIR + * + * spi_rxf_intr interrupt is active prior to masking + */ +#define ALT_SPIM_RISR_RXFIR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXFIR register field. */ +#define ALT_SPIM_RISR_RXFIR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXFIR register field. */ +#define ALT_SPIM_RISR_RXFIR_MSB 4 +/* The width in bits of the ALT_SPIM_RISR_RXFIR register field. */ +#define ALT_SPIM_RISR_RXFIR_WIDTH 1 +/* The mask used to set the ALT_SPIM_RISR_RXFIR register field value. */ +#define ALT_SPIM_RISR_RXFIR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SPIM_RISR_RXFIR register field value. */ +#define ALT_SPIM_RISR_RXFIR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SPIM_RISR_RXFIR register field. */ +#define ALT_SPIM_RISR_RXFIR_RESET 0x0 +/* Extracts the ALT_SPIM_RISR_RXFIR field value from a register. */ +#define ALT_SPIM_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SPIM_RISR_RXFIR register field value suitable for setting the register. */ +#define ALT_SPIM_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_RISR. + */ +struct ALT_SPIM_RISR_s +{ + const uint32_t txeir : 1; /* Transmit FIFO Empty Raw Interrupt Status */ + const uint32_t txoir : 1; /* Transmit FIFO Overflow Raw Interrupt Status */ + const uint32_t rxuir : 1; /* Receive FIFO Underflow Raw Interrupt Status */ + const uint32_t rxoir : 1; /* Receive FIFO Overflow Raw Interrupt Status */ + const uint32_t rxfir : 1; /* Receive FIFO Full Raw Interrupt Status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_RISR. */ +typedef volatile struct ALT_SPIM_RISR_s ALT_SPIM_RISR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_RISR register from the beginning of the component. */ +#define ALT_SPIM_RISR_OFST 0x34 +/* The address of the ALT_SPIM_RISR register. */ +#define ALT_SPIM_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RISR_OFST)) + +/* + * Register : Transmit FIFO Overflow Interrupt Clear Register - txoicr + * + * Transmit FIFO Overflow Interrupt Clear Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Clear Transmit FIFO Overflow Interrupt + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Transmit FIFO Overflow Interrupt - txoicr + * + * This register reflects the status of the interrupt. A read from this register + * clears the spi_txo_intr interrupt; writing has no effect. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_TXOICR_TXOICR register field. */ +#define ALT_SPIM_TXOICR_TXOICR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_TXOICR_TXOICR register field. */ +#define ALT_SPIM_TXOICR_TXOICR_MSB 0 +/* The width in bits of the ALT_SPIM_TXOICR_TXOICR register field. */ +#define ALT_SPIM_TXOICR_TXOICR_WIDTH 1 +/* The mask used to set the ALT_SPIM_TXOICR_TXOICR register field value. */ +#define ALT_SPIM_TXOICR_TXOICR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_TXOICR_TXOICR register field value. */ +#define ALT_SPIM_TXOICR_TXOICR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_TXOICR_TXOICR register field. */ +#define ALT_SPIM_TXOICR_TXOICR_RESET 0x0 +/* Extracts the ALT_SPIM_TXOICR_TXOICR field value from a register. */ +#define ALT_SPIM_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_TXOICR_TXOICR register field value suitable for setting the register. */ +#define ALT_SPIM_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_TXOICR. + */ +struct ALT_SPIM_TXOICR_s +{ + const uint32_t txoicr : 1; /* Clear Transmit FIFO Overflow Interrupt */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_TXOICR. */ +typedef volatile struct ALT_SPIM_TXOICR_s ALT_SPIM_TXOICR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_TXOICR register from the beginning of the component. */ +#define ALT_SPIM_TXOICR_OFST 0x38 +/* The address of the ALT_SPIM_TXOICR register. */ +#define ALT_SPIM_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXOICR_OFST)) + +/* + * Register : Receive FIFO Overflow Interrupt Clear Register - rxoicr + * + * Receive FIFO Overflow Interrupt Clear Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------- + * [0] | R | 0x0 | Clear Receive FIFO Overflow Interrupt + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Receive FIFO Overflow Interrupt - rxoicr + * + * This register reflects the status of the interrupt. A read from this register + * clears the spi_rxo_intr interrupt; writing has no effect. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_RXOICR_RXOICR register field. */ +#define ALT_SPIM_RXOICR_RXOICR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_RXOICR_RXOICR register field. */ +#define ALT_SPIM_RXOICR_RXOICR_MSB 0 +/* The width in bits of the ALT_SPIM_RXOICR_RXOICR register field. */ +#define ALT_SPIM_RXOICR_RXOICR_WIDTH 1 +/* The mask used to set the ALT_SPIM_RXOICR_RXOICR register field value. */ +#define ALT_SPIM_RXOICR_RXOICR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_RXOICR_RXOICR register field value. */ +#define ALT_SPIM_RXOICR_RXOICR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_RXOICR_RXOICR register field. */ +#define ALT_SPIM_RXOICR_RXOICR_RESET 0x0 +/* Extracts the ALT_SPIM_RXOICR_RXOICR field value from a register. */ +#define ALT_SPIM_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_RXOICR_RXOICR register field value suitable for setting the register. */ +#define ALT_SPIM_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_RXOICR. + */ +struct ALT_SPIM_RXOICR_s +{ + const uint32_t rxoicr : 1; /* Clear Receive FIFO Overflow Interrupt */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_RXOICR. */ +typedef volatile struct ALT_SPIM_RXOICR_s ALT_SPIM_RXOICR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_RXOICR register from the beginning of the component. */ +#define ALT_SPIM_RXOICR_OFST 0x3c +/* The address of the ALT_SPIM_RXOICR register. */ +#define ALT_SPIM_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXOICR_OFST)) + +/* + * Register : Receive FIFO Underflow Interrupt Clear Register - rxuicr + * + * Receive FIFO Underflow Interrupt Clear Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Clear Receive FIFO Underflow Interrupt + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Receive FIFO Underflow Interrupt - rxuicr + * + * This register reflects the status of the interrupt. A read from this register + * clears the spi_rxu_intr interrupt; writing has no effect. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_RXUICR_RXUICR register field. */ +#define ALT_SPIM_RXUICR_RXUICR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_RXUICR_RXUICR register field. */ +#define ALT_SPIM_RXUICR_RXUICR_MSB 0 +/* The width in bits of the ALT_SPIM_RXUICR_RXUICR register field. */ +#define ALT_SPIM_RXUICR_RXUICR_WIDTH 1 +/* The mask used to set the ALT_SPIM_RXUICR_RXUICR register field value. */ +#define ALT_SPIM_RXUICR_RXUICR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_RXUICR_RXUICR register field value. */ +#define ALT_SPIM_RXUICR_RXUICR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_RXUICR_RXUICR register field. */ +#define ALT_SPIM_RXUICR_RXUICR_RESET 0x0 +/* Extracts the ALT_SPIM_RXUICR_RXUICR field value from a register. */ +#define ALT_SPIM_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_RXUICR_RXUICR register field value suitable for setting the register. */ +#define ALT_SPIM_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_RXUICR. + */ +struct ALT_SPIM_RXUICR_s +{ + const uint32_t rxuicr : 1; /* Clear Receive FIFO Underflow Interrupt */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_RXUICR. */ +typedef volatile struct ALT_SPIM_RXUICR_s ALT_SPIM_RXUICR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_RXUICR register from the beginning of the component. */ +#define ALT_SPIM_RXUICR_OFST 0x40 +/* The address of the ALT_SPIM_RXUICR register. */ +#define ALT_SPIM_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXUICR_OFST)) + +/* + * Register : Interrupt Clear Register - icr + * + * Clear Interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | R | 0x0 | Clear Interrupt + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Interrupt - icr + * + * This register is set if any of the interrupts are active. A read clears the + * spi_txo_intr, spi_rxu_intr, spi_rxo_intr, and the spi_mst_intr interrupts. + * Writing to this register has no effect. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_ICR_ICR register field. */ +#define ALT_SPIM_ICR_ICR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_ICR_ICR register field. */ +#define ALT_SPIM_ICR_ICR_MSB 0 +/* The width in bits of the ALT_SPIM_ICR_ICR register field. */ +#define ALT_SPIM_ICR_ICR_WIDTH 1 +/* The mask used to set the ALT_SPIM_ICR_ICR register field value. */ +#define ALT_SPIM_ICR_ICR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_ICR_ICR register field value. */ +#define ALT_SPIM_ICR_ICR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_ICR_ICR register field. */ +#define ALT_SPIM_ICR_ICR_RESET 0x0 +/* Extracts the ALT_SPIM_ICR_ICR field value from a register. */ +#define ALT_SPIM_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_ICR_ICR register field value suitable for setting the register. */ +#define ALT_SPIM_ICR_ICR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_ICR. + */ +struct ALT_SPIM_ICR_s +{ + const uint32_t icr : 1; /* Clear Interrupt */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_ICR. */ +typedef volatile struct ALT_SPIM_ICR_s ALT_SPIM_ICR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_ICR register from the beginning of the component. */ +#define ALT_SPIM_ICR_OFST 0x48 +/* The address of the ALT_SPIM_ICR register. */ +#define ALT_SPIM_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ICR_OFST)) + +/* + * Register : DMA Control Register - dmacr + * + * This register is used to enable the DMA Controller interface operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [0] | RW | 0x0 | Receive DMA Enable + * [1] | RW | 0x0 | Transmit DMA Enable + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive DMA Enable - rdmae + * + * This bit enables/disables the receive FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------- + * ALT_SPIM_DMACR_RDMAE_E_DISD | 0x0 | Receive DMA disabled + * ALT_SPIM_DMACR_RDMAE_E_END | 0x1 | Receive DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_DMACR_RDMAE + * + * Receive DMA disabled + */ +#define ALT_SPIM_DMACR_RDMAE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SPIM_DMACR_RDMAE + * + * Receive DMA enabled + */ +#define ALT_SPIM_DMACR_RDMAE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_DMACR_RDMAE register field. */ +#define ALT_SPIM_DMACR_RDMAE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_DMACR_RDMAE register field. */ +#define ALT_SPIM_DMACR_RDMAE_MSB 0 +/* The width in bits of the ALT_SPIM_DMACR_RDMAE register field. */ +#define ALT_SPIM_DMACR_RDMAE_WIDTH 1 +/* The mask used to set the ALT_SPIM_DMACR_RDMAE register field value. */ +#define ALT_SPIM_DMACR_RDMAE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIM_DMACR_RDMAE register field value. */ +#define ALT_SPIM_DMACR_RDMAE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIM_DMACR_RDMAE register field. */ +#define ALT_SPIM_DMACR_RDMAE_RESET 0x0 +/* Extracts the ALT_SPIM_DMACR_RDMAE field value from a register. */ +#define ALT_SPIM_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIM_DMACR_RDMAE register field value suitable for setting the register. */ +#define ALT_SPIM_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit DMA Enable - tdmae + * + * This bit enables/disables the transmit FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------- + * ALT_SPIM_DMACR_TDMAE_E_DISD | 0x0 | Transmit DMA disabled + * ALT_SPIM_DMACR_TDMAE_E_END | 0x1 | Transmit DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIM_DMACR_TDMAE + * + * Transmit DMA disabled + */ +#define ALT_SPIM_DMACR_TDMAE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SPIM_DMACR_TDMAE + * + * Transmit DMA enabled + */ +#define ALT_SPIM_DMACR_TDMAE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIM_DMACR_TDMAE register field. */ +#define ALT_SPIM_DMACR_TDMAE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_DMACR_TDMAE register field. */ +#define ALT_SPIM_DMACR_TDMAE_MSB 1 +/* The width in bits of the ALT_SPIM_DMACR_TDMAE register field. */ +#define ALT_SPIM_DMACR_TDMAE_WIDTH 1 +/* The mask used to set the ALT_SPIM_DMACR_TDMAE register field value. */ +#define ALT_SPIM_DMACR_TDMAE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIM_DMACR_TDMAE register field value. */ +#define ALT_SPIM_DMACR_TDMAE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIM_DMACR_TDMAE register field. */ +#define ALT_SPIM_DMACR_TDMAE_RESET 0x0 +/* Extracts the ALT_SPIM_DMACR_TDMAE field value from a register. */ +#define ALT_SPIM_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIM_DMACR_TDMAE register field value suitable for setting the register. */ +#define ALT_SPIM_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_DMACR. + */ +struct ALT_SPIM_DMACR_s +{ + uint32_t rdmae : 1; /* Receive DMA Enable */ + uint32_t tdmae : 1; /* Transmit DMA Enable */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_DMACR. */ +typedef volatile struct ALT_SPIM_DMACR_s ALT_SPIM_DMACR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_DMACR register from the beginning of the component. */ +#define ALT_SPIM_DMACR_OFST 0x4c +/* The address of the ALT_SPIM_DMACR register. */ +#define ALT_SPIM_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMACR_OFST)) + +/* + * Register : DMA Transmit Data Level Register - dmatdlr + * + * Controls the FIFO Level for a DMA transmit request + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [7:0] | RW | 0x0 | Transmit Data Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit Data Level - dmatdl + * + * This bit field controls the level at which a DMA request is made by the transmit + * logic. It is equal to the watermark level; that is, the dma_tx_req signal is + * generated when the number of valid data entries in the transmit FIFO is equal to + * or below this field value, and TDMAE = 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_DMATDLR_DMATDL register field. */ +#define ALT_SPIM_DMATDLR_DMATDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_DMATDLR_DMATDL register field. */ +#define ALT_SPIM_DMATDLR_DMATDL_MSB 7 +/* The width in bits of the ALT_SPIM_DMATDLR_DMATDL register field. */ +#define ALT_SPIM_DMATDLR_DMATDL_WIDTH 8 +/* The mask used to set the ALT_SPIM_DMATDLR_DMATDL register field value. */ +#define ALT_SPIM_DMATDLR_DMATDL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SPIM_DMATDLR_DMATDL register field value. */ +#define ALT_SPIM_DMATDLR_DMATDL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SPIM_DMATDLR_DMATDL register field. */ +#define ALT_SPIM_DMATDLR_DMATDL_RESET 0x0 +/* Extracts the ALT_SPIM_DMATDLR_DMATDL field value from a register. */ +#define ALT_SPIM_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SPIM_DMATDLR_DMATDL register field value suitable for setting the register. */ +#define ALT_SPIM_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_DMATDLR. + */ +struct ALT_SPIM_DMATDLR_s +{ + uint32_t dmatdl : 8; /* Transmit Data Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_DMATDLR. */ +typedef volatile struct ALT_SPIM_DMATDLR_s ALT_SPIM_DMATDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_DMATDLR register from the beginning of the component. */ +#define ALT_SPIM_DMATDLR_OFST 0x50 +/* The address of the ALT_SPIM_DMATDLR register. */ +#define ALT_SPIM_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMATDLR_OFST)) + +/* + * Register : DMA Receive Data Level Register - dmardlr + * + * Controls the FIFO Level for a DMA receeive request + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [7:0] | RW | 0x0 | Receive Data Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive Data Level - dmardl + * + * This bit field controls the level at which a DMA request is made by the receive + * logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the + * number of valid data entries in the receive FIFO is equal to or above this field + * value + 1, and RDMAE=1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_DMARDLR_DMARDL register field. */ +#define ALT_SPIM_DMARDLR_DMARDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_DMARDLR_DMARDL register field. */ +#define ALT_SPIM_DMARDLR_DMARDL_MSB 7 +/* The width in bits of the ALT_SPIM_DMARDLR_DMARDL register field. */ +#define ALT_SPIM_DMARDLR_DMARDL_WIDTH 8 +/* The mask used to set the ALT_SPIM_DMARDLR_DMARDL register field value. */ +#define ALT_SPIM_DMARDLR_DMARDL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SPIM_DMARDLR_DMARDL register field value. */ +#define ALT_SPIM_DMARDLR_DMARDL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SPIM_DMARDLR_DMARDL register field. */ +#define ALT_SPIM_DMARDLR_DMARDL_RESET 0x0 +/* Extracts the ALT_SPIM_DMARDLR_DMARDL field value from a register. */ +#define ALT_SPIM_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SPIM_DMARDLR_DMARDL register field value suitable for setting the register. */ +#define ALT_SPIM_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_DMARDLR. + */ +struct ALT_SPIM_DMARDLR_s +{ + uint32_t dmardl : 8; /* Receive Data Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_DMARDLR. */ +typedef volatile struct ALT_SPIM_DMARDLR_s ALT_SPIM_DMARDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_DMARDLR register from the beginning of the component. */ +#define ALT_SPIM_DMARDLR_OFST 0x54 +/* The address of the ALT_SPIM_DMARDLR register. */ +#define ALT_SPIM_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMARDLR_OFST)) + +/* + * Register : Identification Register - idr + * + * This register contains the peripherals identification code, which is 0x05510000. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:----------|:------------------------ + * [31:0] | R | 0x5510000 | Identification Register + * + */ +/* + * Field : Identification Register - idr + * + * This register contains the peripherals identification code + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_IDR_IDR register field. */ +#define ALT_SPIM_IDR_IDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_IDR_IDR register field. */ +#define ALT_SPIM_IDR_IDR_MSB 31 +/* The width in bits of the ALT_SPIM_IDR_IDR register field. */ +#define ALT_SPIM_IDR_IDR_WIDTH 32 +/* The mask used to set the ALT_SPIM_IDR_IDR register field value. */ +#define ALT_SPIM_IDR_IDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SPIM_IDR_IDR register field value. */ +#define ALT_SPIM_IDR_IDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_SPIM_IDR_IDR register field. */ +#define ALT_SPIM_IDR_IDR_RESET 0x5510000 +/* Extracts the ALT_SPIM_IDR_IDR field value from a register. */ +#define ALT_SPIM_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SPIM_IDR_IDR register field value suitable for setting the register. */ +#define ALT_SPIM_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_IDR. + */ +struct ALT_SPIM_IDR_s +{ + const uint32_t idr : 32; /* Identification Register */ +}; + +/* The typedef declaration for register ALT_SPIM_IDR. */ +typedef volatile struct ALT_SPIM_IDR_s ALT_SPIM_IDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_IDR register from the beginning of the component. */ +#define ALT_SPIM_IDR_OFST 0x58 +/* The address of the ALT_SPIM_IDR register. */ +#define ALT_SPIM_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IDR_OFST)) + +/* + * Register : Component Version Register - spi_version_id + * + * Version ID Register value + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:---------------- + * [31:0] | RW | 0x3332302a | Version ID Code + * + */ +/* + * Field : Version ID Code - spi_version_id + * + * Contains the hex representation of the Synopsys component version. Consists of + * ASCII value for each number in the version. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */ +#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */ +#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_MSB 31 +/* The width in bits of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */ +#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_WIDTH 32 +/* The mask used to set the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field value. */ +#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field value. */ +#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000 +/* The reset value of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */ +#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_RESET 0x3332302a +/* Extracts the ALT_SPIM_SPI_VER_ID_SPI_VER_ID field value from a register. */ +#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field value suitable for setting the register. */ +#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_SPI_VER_ID. + */ +struct ALT_SPIM_SPI_VER_ID_s +{ + uint32_t spi_version_id : 32; /* Version ID Code */ +}; + +/* The typedef declaration for register ALT_SPIM_SPI_VER_ID. */ +typedef volatile struct ALT_SPIM_SPI_VER_ID_s ALT_SPIM_SPI_VER_ID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_SPI_VER_ID register from the beginning of the component. */ +#define ALT_SPIM_SPI_VER_ID_OFST 0x5c +/* The address of the ALT_SPIM_SPI_VER_ID register. */ +#define ALT_SPIM_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SPI_VER_ID_OFST)) + +/* + * Register : Data Register - dr + * + * This register is a 16-bit read/write buffer for the transmit/receive FIFOs. When + * the register is read, data in the receive FIFO buffer is accessed. When it is + * written to, data are moved into the transmit FIFO buffer; a write can occur only + * when SPI_EN = 1. FIFOs are reset when SPI_EN = 0. + * + * The data register occupies 36 32-bit locations in the address map (0x60 to + * 0xec). These are all aliases for the same data register. This is done to support + * burst accesses. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [15:0] | RW | 0x0 | Data + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data - dr + * + * When writing to this register, you must right-justify the data. Read data are + * automatically right-justified. + * + * Read = Receive FIFO buffer + * + * Write = Transmit FIFO buffer + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_DR_DR register field. */ +#define ALT_SPIM_DR_DR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_DR_DR register field. */ +#define ALT_SPIM_DR_DR_MSB 15 +/* The width in bits of the ALT_SPIM_DR_DR register field. */ +#define ALT_SPIM_DR_DR_WIDTH 16 +/* The mask used to set the ALT_SPIM_DR_DR register field value. */ +#define ALT_SPIM_DR_DR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SPIM_DR_DR register field value. */ +#define ALT_SPIM_DR_DR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SPIM_DR_DR register field. */ +#define ALT_SPIM_DR_DR_RESET 0x0 +/* Extracts the ALT_SPIM_DR_DR field value from a register. */ +#define ALT_SPIM_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SPIM_DR_DR register field value suitable for setting the register. */ +#define ALT_SPIM_DR_DR_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_DR. + */ +struct ALT_SPIM_DR_s +{ + uint32_t dr : 16; /* Data */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_DR. */ +typedef volatile struct ALT_SPIM_DR_s ALT_SPIM_DR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_DR register from the beginning of the component. */ +#define ALT_SPIM_DR_OFST 0x60 +/* The address of the ALT_SPIM_DR register. */ +#define ALT_SPIM_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR_OFST)) + +/* + * Register : RX Sample Delay Register - rx_sample_dly + * + * This register controls the number of spi_m_clk cycles that are delayed (from the + * default sample time) before the actual sample of the rxd input occurs. It is + * impossible to write to this register when the SPI Master is enabled. The SPI + * Master is enabled and disabled by writing to the SPIENR register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [6:0] | RW | 0x0 | Receive Data Sample Delay + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive Data Sample Delay - rsd + * + * This register is used to delay the sample of the rxd input port. Each value + * represents a single spi_m_clk delay on the sample of rxd. + * + * Note; If this register is programmed with a value that exceeds 64, a 0 delay + * will be applied to the receive sample. The maximum delay is 64 spi_m_clk cycles. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */ +#define ALT_SPIM_RX_SMPL_DLY_RSD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */ +#define ALT_SPIM_RX_SMPL_DLY_RSD_MSB 6 +/* The width in bits of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */ +#define ALT_SPIM_RX_SMPL_DLY_RSD_WIDTH 7 +/* The mask used to set the ALT_SPIM_RX_SMPL_DLY_RSD register field value. */ +#define ALT_SPIM_RX_SMPL_DLY_RSD_SET_MSK 0x0000007f +/* The mask used to clear the ALT_SPIM_RX_SMPL_DLY_RSD register field value. */ +#define ALT_SPIM_RX_SMPL_DLY_RSD_CLR_MSK 0xffffff80 +/* The reset value of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */ +#define ALT_SPIM_RX_SMPL_DLY_RSD_RESET 0x0 +/* Extracts the ALT_SPIM_RX_SMPL_DLY_RSD field value from a register. */ +#define ALT_SPIM_RX_SMPL_DLY_RSD_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_SPIM_RX_SMPL_DLY_RSD register field value suitable for setting the register. */ +#define ALT_SPIM_RX_SMPL_DLY_RSD_SET(value) (((value) << 0) & 0x0000007f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIM_RX_SMPL_DLY. + */ +struct ALT_SPIM_RX_SMPL_DLY_s +{ + uint32_t rsd : 7; /* Receive Data Sample Delay */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIM_RX_SMPL_DLY. */ +typedef volatile struct ALT_SPIM_RX_SMPL_DLY_s ALT_SPIM_RX_SMPL_DLY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIM_RX_SMPL_DLY register from the beginning of the component. */ +#define ALT_SPIM_RX_SMPL_DLY_OFST 0xfc +/* The address of the ALT_SPIM_RX_SMPL_DLY register. */ +#define ALT_SPIM_RX_SMPL_DLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RX_SMPL_DLY_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SPIM. + */ +struct ALT_SPIM_s +{ + volatile ALT_SPIM_CTLR0_t ctrlr0; /* ALT_SPIM_CTLR0 */ + volatile ALT_SPIM_CTLR1_t ctrlr1; /* ALT_SPIM_CTLR1 */ + volatile ALT_SPIM_SPIENR_t spienr; /* ALT_SPIM_SPIENR */ + volatile ALT_SPIM_MWCR_t mwcr; /* ALT_SPIM_MWCR */ + volatile ALT_SPIM_SER_t ser; /* ALT_SPIM_SER */ + volatile ALT_SPIM_BAUDR_t baudr; /* ALT_SPIM_BAUDR */ + volatile ALT_SPIM_TXFTLR_t txftlr; /* ALT_SPIM_TXFTLR */ + volatile ALT_SPIM_RXFTLR_t rxftlr; /* ALT_SPIM_RXFTLR */ + volatile ALT_SPIM_TXFLR_t txflr; /* ALT_SPIM_TXFLR */ + volatile ALT_SPIM_RXFLR_t rxflr; /* ALT_SPIM_RXFLR */ + volatile ALT_SPIM_SR_t sr; /* ALT_SPIM_SR */ + volatile ALT_SPIM_IMR_t imr; /* ALT_SPIM_IMR */ + volatile ALT_SPIM_ISR_t isr; /* ALT_SPIM_ISR */ + volatile ALT_SPIM_RISR_t risr; /* ALT_SPIM_RISR */ + volatile ALT_SPIM_TXOICR_t txoicr; /* ALT_SPIM_TXOICR */ + volatile ALT_SPIM_RXOICR_t rxoicr; /* ALT_SPIM_RXOICR */ + volatile ALT_SPIM_RXUICR_t rxuicr; /* ALT_SPIM_RXUICR */ + volatile uint32_t _pad_0x44_0x47; /* *UNDEFINED* */ + volatile ALT_SPIM_ICR_t icr; /* ALT_SPIM_ICR */ + volatile ALT_SPIM_DMACR_t dmacr; /* ALT_SPIM_DMACR */ + volatile ALT_SPIM_DMATDLR_t dmatdlr; /* ALT_SPIM_DMATDLR */ + volatile ALT_SPIM_DMARDLR_t dmardlr; /* ALT_SPIM_DMARDLR */ + volatile ALT_SPIM_IDR_t idr; /* ALT_SPIM_IDR */ + volatile ALT_SPIM_SPI_VER_ID_t spi_version_id; /* ALT_SPIM_SPI_VER_ID */ + volatile ALT_SPIM_DR_t dr; /* ALT_SPIM_DR */ + volatile uint32_t _pad_0x64_0xfb[38]; /* *UNDEFINED* */ + volatile ALT_SPIM_RX_SMPL_DLY_t rx_sample_dly; /* ALT_SPIM_RX_SMPL_DLY */ +}; + +/* The typedef declaration for register group ALT_SPIM. */ +typedef volatile struct ALT_SPIM_s ALT_SPIM_t; +/* The struct declaration for the raw register contents of register group ALT_SPIM. */ +struct ALT_SPIM_raw_s +{ + volatile uint32_t ctrlr0; /* ALT_SPIM_CTLR0 */ + volatile uint32_t ctrlr1; /* ALT_SPIM_CTLR1 */ + volatile uint32_t spienr; /* ALT_SPIM_SPIENR */ + volatile uint32_t mwcr; /* ALT_SPIM_MWCR */ + volatile uint32_t ser; /* ALT_SPIM_SER */ + volatile uint32_t baudr; /* ALT_SPIM_BAUDR */ + volatile uint32_t txftlr; /* ALT_SPIM_TXFTLR */ + volatile uint32_t rxftlr; /* ALT_SPIM_RXFTLR */ + volatile uint32_t txflr; /* ALT_SPIM_TXFLR */ + volatile uint32_t rxflr; /* ALT_SPIM_RXFLR */ + volatile uint32_t sr; /* ALT_SPIM_SR */ + volatile uint32_t imr; /* ALT_SPIM_IMR */ + volatile uint32_t isr; /* ALT_SPIM_ISR */ + volatile uint32_t risr; /* ALT_SPIM_RISR */ + volatile uint32_t txoicr; /* ALT_SPIM_TXOICR */ + volatile uint32_t rxoicr; /* ALT_SPIM_RXOICR */ + volatile uint32_t rxuicr; /* ALT_SPIM_RXUICR */ + volatile uint32_t _pad_0x44_0x47; /* *UNDEFINED* */ + volatile uint32_t icr; /* ALT_SPIM_ICR */ + volatile uint32_t dmacr; /* ALT_SPIM_DMACR */ + volatile uint32_t dmatdlr; /* ALT_SPIM_DMATDLR */ + volatile uint32_t dmardlr; /* ALT_SPIM_DMARDLR */ + volatile uint32_t idr; /* ALT_SPIM_IDR */ + volatile uint32_t spi_version_id; /* ALT_SPIM_SPI_VER_ID */ + volatile uint32_t dr; /* ALT_SPIM_DR */ + volatile uint32_t _pad_0x64_0xfb[38]; /* *UNDEFINED* */ + volatile uint32_t rx_sample_dly; /* ALT_SPIM_RX_SMPL_DLY */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SPIM. */ +typedef volatile struct ALT_SPIM_raw_s ALT_SPIM_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_SPIM_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_spis.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_spis.h new file mode 100644 index 000000000..9ba3fe083 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_spis.h @@ -0,0 +1,2958 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_SPIS */ + +#ifndef __ALTERA_ALT_SPIS_H__ +#define __ALTERA_ALT_SPIS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : SPI Slave Module - ALT_SPIS + * SPI Slave Module + * + * Registers in the SPI Slave module + * + */ +/* + * Register : Control Register 0 - ctrlr0 + * + * This register controls the serial data transfer. It is impossible to write to + * this register when the SPI Slave is enabled. The SPI Slave is enabled and + * disabled by writing to the SPIENR register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------- + * [3:0] | RW | 0x7 | Data Frame Size + * [5:4] | RW | 0x0 | Frame Format + * [6] | RW | 0x0 | Serial Clock Phase + * [7] | RW | 0x0 | Serial Clock Polarity + * [9:8] | RW | 0x0 | Transfer Mode + * [10] | RW | 0x0 | Slave Output Enable + * [11] | RW | 0x0 | Shift Register Loop + * [15:12] | RW | 0x0 | Control Frame Size + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Frame Size - dfs + * + * Selects the data frame length. When the data frame size is programmed to be less + * than 16 bits, the receive data are automatically right-justified by the receive + * logic, with the upper bits of the receiver FIFO zero-padded. You must right- + * justify transmit data before writing into the transmit FIFO. The transmit logic + * ignores the upper unused bits when transmitting the data. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:---------------------------- + * ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT | 0x3 | 4-bit serial data transfer + * ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT | 0x4 | 5-bit serial data transfer + * ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT | 0x5 | 6-bit serial data transfer + * ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT | 0x6 | 7-bit serial data transfer + * ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT | 0x7 | 8-bit serial data transfer + * ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT | 0x8 | 9-bit serial data transfer + * ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT | 0x9 | 10-bit serial data transfer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_CTLR0_DFS + * + * 4-bit serial data transfer + */ +#define ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT 0x3 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_DFS + * + * 5-bit serial data transfer + */ +#define ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT 0x4 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_DFS + * + * 6-bit serial data transfer + */ +#define ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT 0x5 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_DFS + * + * 7-bit serial data transfer + */ +#define ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT 0x6 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_DFS + * + * 8-bit serial data transfer + */ +#define ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT 0x7 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_DFS + * + * 9-bit serial data transfer + */ +#define ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT 0x8 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_DFS + * + * 10-bit serial data transfer + */ +#define ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT 0x9 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_DFS register field. */ +#define ALT_SPIS_CTLR0_DFS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_DFS register field. */ +#define ALT_SPIS_CTLR0_DFS_MSB 3 +/* The width in bits of the ALT_SPIS_CTLR0_DFS register field. */ +#define ALT_SPIS_CTLR0_DFS_WIDTH 4 +/* The mask used to set the ALT_SPIS_CTLR0_DFS register field value. */ +#define ALT_SPIS_CTLR0_DFS_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SPIS_CTLR0_DFS register field value. */ +#define ALT_SPIS_CTLR0_DFS_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SPIS_CTLR0_DFS register field. */ +#define ALT_SPIS_CTLR0_DFS_RESET 0x7 +/* Extracts the ALT_SPIS_CTLR0_DFS field value from a register. */ +#define ALT_SPIS_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SPIS_CTLR0_DFS register field value suitable for setting the register. */ +#define ALT_SPIS_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Frame Format - frf + * + * Selects which serial protocol transfers the data. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------ + * ALT_SPIS_CTLR0_FRF_E_MOTSPI | 0x0 | Motorola SPI + * ALT_SPIS_CTLR0_FRF_E_TISSP | 0x1 | Texas instruments SSP + * ALT_SPIS_CTLR0_FRF_E_NATMW | 0x2 | National Semi Microwire + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_CTLR0_FRF + * + * Motorola SPI + */ +#define ALT_SPIS_CTLR0_FRF_E_MOTSPI 0x0 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_FRF + * + * Texas instruments SSP + */ +#define ALT_SPIS_CTLR0_FRF_E_TISSP 0x1 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_FRF + * + * National Semi Microwire + */ +#define ALT_SPIS_CTLR0_FRF_E_NATMW 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_FRF register field. */ +#define ALT_SPIS_CTLR0_FRF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_FRF register field. */ +#define ALT_SPIS_CTLR0_FRF_MSB 5 +/* The width in bits of the ALT_SPIS_CTLR0_FRF register field. */ +#define ALT_SPIS_CTLR0_FRF_WIDTH 2 +/* The mask used to set the ALT_SPIS_CTLR0_FRF register field value. */ +#define ALT_SPIS_CTLR0_FRF_SET_MSK 0x00000030 +/* The mask used to clear the ALT_SPIS_CTLR0_FRF register field value. */ +#define ALT_SPIS_CTLR0_FRF_CLR_MSK 0xffffffcf +/* The reset value of the ALT_SPIS_CTLR0_FRF register field. */ +#define ALT_SPIS_CTLR0_FRF_RESET 0x0 +/* Extracts the ALT_SPIS_CTLR0_FRF field value from a register. */ +#define ALT_SPIS_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_SPIS_CTLR0_FRF register field value suitable for setting the register. */ +#define ALT_SPIS_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030) + +/* + * Field : Serial Clock Phase - scph + * + * Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase + * selects the relationship of the serial clock with the slave select signal. When + * SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = + * 1, the serial clock starts toggling one cycle after the slave select line is + * activated, and data are captured on the second edge of the serial clock. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:--------------------------------------- + * ALT_SPIS_CTLR0_SCPH_E_INACTLOW | 0x0 | Inactive state of serial clock is low + * ALT_SPIS_CTLR0_SCPH_E_INACTHIGH | 0x1 | Inactive state of serial clock is high + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_CTLR0_SCPH + * + * Inactive state of serial clock is low + */ +#define ALT_SPIS_CTLR0_SCPH_E_INACTLOW 0x0 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_SCPH + * + * Inactive state of serial clock is high + */ +#define ALT_SPIS_CTLR0_SCPH_E_INACTHIGH 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SCPH register field. */ +#define ALT_SPIS_CTLR0_SCPH_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SCPH register field. */ +#define ALT_SPIS_CTLR0_SCPH_MSB 6 +/* The width in bits of the ALT_SPIS_CTLR0_SCPH register field. */ +#define ALT_SPIS_CTLR0_SCPH_WIDTH 1 +/* The mask used to set the ALT_SPIS_CTLR0_SCPH register field value. */ +#define ALT_SPIS_CTLR0_SCPH_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SPIS_CTLR0_SCPH register field value. */ +#define ALT_SPIS_CTLR0_SCPH_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SPIS_CTLR0_SCPH register field. */ +#define ALT_SPIS_CTLR0_SCPH_RESET 0x0 +/* Extracts the ALT_SPIS_CTLR0_SCPH field value from a register. */ +#define ALT_SPIS_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SPIS_CTLR0_SCPH register field value suitable for setting the register. */ +#define ALT_SPIS_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Serial Clock Polarity - scpol + * + * Valid when the frame format (FRF) is set to Motorola SPI. Used to select the + * polarity of the inactive serial clock, which is held inactive when the spi + * master is not actively transferring data on the serial bus. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_SPIS_CTLR0_SCPOL_E_MIDBIT | 0x0 | Serial clock toggles in middle of first data bit + * ALT_SPIS_CTLR0_SCPOL_E_STARTBIT | 0x1 | Serial clock toggles at start of first data bit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_CTLR0_SCPOL + * + * Serial clock toggles in middle of first data bit + */ +#define ALT_SPIS_CTLR0_SCPOL_E_MIDBIT 0x0 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_SCPOL + * + * Serial clock toggles at start of first data bit + */ +#define ALT_SPIS_CTLR0_SCPOL_E_STARTBIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SCPOL register field. */ +#define ALT_SPIS_CTLR0_SCPOL_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SCPOL register field. */ +#define ALT_SPIS_CTLR0_SCPOL_MSB 7 +/* The width in bits of the ALT_SPIS_CTLR0_SCPOL register field. */ +#define ALT_SPIS_CTLR0_SCPOL_WIDTH 1 +/* The mask used to set the ALT_SPIS_CTLR0_SCPOL register field value. */ +#define ALT_SPIS_CTLR0_SCPOL_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SPIS_CTLR0_SCPOL register field value. */ +#define ALT_SPIS_CTLR0_SCPOL_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SPIS_CTLR0_SCPOL register field. */ +#define ALT_SPIS_CTLR0_SCPOL_RESET 0x0 +/* Extracts the ALT_SPIS_CTLR0_SCPOL field value from a register. */ +#define ALT_SPIS_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SPIS_CTLR0_SCPOL register field value suitable for setting the register. */ +#define ALT_SPIS_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Transfer Mode - tmod + * + * Selects the mode of transfer for serial communication. This field does not + * affect the transfer duplicity. Only indicates whether the receive or transmit + * data are valid. In transmit-only mode, data received from the external device is + * not valid and is not stored in the receive FIFO memory; it is overwritten on the + * next transfer. In receive-only mode, transmitted data are not valid. After the + * first write to the transmit FIFO, the same word is retransmitted for the + * duration of the transfer. In transmit-and-receive mode, both transmit and + * receive data are valid. The transfer continues until the transmit FIFO is empty. + * Data received from the external device are stored into the receive FIFO memory + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:----------------------- + * ALT_SPIS_CTLR0_TMOD_E_TXRX | 0x0 | Transmit & and Receive + * ALT_SPIS_CTLR0_TMOD_E_TXONLY | 0x1 | Transmit Only + * ALT_SPIS_CTLR0_TMOD_E_RXONLY | 0x2 | Receive Only + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_CTLR0_TMOD + * + * Transmit & and Receive + */ +#define ALT_SPIS_CTLR0_TMOD_E_TXRX 0x0 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_TMOD + * + * Transmit Only + */ +#define ALT_SPIS_CTLR0_TMOD_E_TXONLY 0x1 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_TMOD + * + * Receive Only + */ +#define ALT_SPIS_CTLR0_TMOD_E_RXONLY 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_TMOD register field. */ +#define ALT_SPIS_CTLR0_TMOD_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_TMOD register field. */ +#define ALT_SPIS_CTLR0_TMOD_MSB 9 +/* The width in bits of the ALT_SPIS_CTLR0_TMOD register field. */ +#define ALT_SPIS_CTLR0_TMOD_WIDTH 2 +/* The mask used to set the ALT_SPIS_CTLR0_TMOD register field value. */ +#define ALT_SPIS_CTLR0_TMOD_SET_MSK 0x00000300 +/* The mask used to clear the ALT_SPIS_CTLR0_TMOD register field value. */ +#define ALT_SPIS_CTLR0_TMOD_CLR_MSK 0xfffffcff +/* The reset value of the ALT_SPIS_CTLR0_TMOD register field. */ +#define ALT_SPIS_CTLR0_TMOD_RESET 0x0 +/* Extracts the ALT_SPIS_CTLR0_TMOD field value from a register. */ +#define ALT_SPIS_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_SPIS_CTLR0_TMOD register field value suitable for setting the register. */ +#define ALT_SPIS_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : Slave Output Enable - slv_oe + * + * This bit enables or disables the setting of the spis0_ssi_oe_n output from the + * SPI Slave. When SLV_OE = 1, the spis0_ssi_oe_n output can never be active. When + * the spis0_ssi_oe_n output controls the tri-state buffer on the txd output from + * the slave, a high impedance state is always present on the slave spis0_txd + * output when SLV_OE = 1. This is useful when the master transmits in broadcast + * mode (master transmits data to all slave devices). Only one slave may respond + * with data on the master spis0_rxd line. This bit is enabled after reset and must + * be disabled by software (when broadcast mode is used), if you do not want this + * device to respond with data. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------- + * ALT_SPIS_CTLR0_SLV_OE_E_END | 0x0 | Slave txd is enabled + * ALT_SPIS_CTLR0_SLV_OE_E_DISD | 0x1 | Slave txd is disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_CTLR0_SLV_OE + * + * Slave txd is enabled + */ +#define ALT_SPIS_CTLR0_SLV_OE_E_END 0x0 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_SLV_OE + * + * Slave txd is disabled + */ +#define ALT_SPIS_CTLR0_SLV_OE_E_DISD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SLV_OE register field. */ +#define ALT_SPIS_CTLR0_SLV_OE_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SLV_OE register field. */ +#define ALT_SPIS_CTLR0_SLV_OE_MSB 10 +/* The width in bits of the ALT_SPIS_CTLR0_SLV_OE register field. */ +#define ALT_SPIS_CTLR0_SLV_OE_WIDTH 1 +/* The mask used to set the ALT_SPIS_CTLR0_SLV_OE register field value. */ +#define ALT_SPIS_CTLR0_SLV_OE_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SPIS_CTLR0_SLV_OE register field value. */ +#define ALT_SPIS_CTLR0_SLV_OE_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SPIS_CTLR0_SLV_OE register field. */ +#define ALT_SPIS_CTLR0_SLV_OE_RESET 0x0 +/* Extracts the ALT_SPIS_CTLR0_SLV_OE field value from a register. */ +#define ALT_SPIS_CTLR0_SLV_OE_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SPIS_CTLR0_SLV_OE register field value suitable for setting the register. */ +#define ALT_SPIS_CTLR0_SLV_OE_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Shift Register Loop - srl + * + * Used for testing purposes only. When internally active, connects the transmit + * shift register output to the receive shift register input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:---------------------- + * ALT_SPIS_CTLR0_SRL_E_NORMMOD | 0x0 | Normal Mode Operation + * ALT_SPIS_CTLR0_SRL_E_TESTMOD | 0x1 | Test Mode Operation + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_CTLR0_SRL + * + * Normal Mode Operation + */ +#define ALT_SPIS_CTLR0_SRL_E_NORMMOD 0x0 +/* + * Enumerated value for register field ALT_SPIS_CTLR0_SRL + * + * Test Mode Operation + */ +#define ALT_SPIS_CTLR0_SRL_E_TESTMOD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SRL register field. */ +#define ALT_SPIS_CTLR0_SRL_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SRL register field. */ +#define ALT_SPIS_CTLR0_SRL_MSB 11 +/* The width in bits of the ALT_SPIS_CTLR0_SRL register field. */ +#define ALT_SPIS_CTLR0_SRL_WIDTH 1 +/* The mask used to set the ALT_SPIS_CTLR0_SRL register field value. */ +#define ALT_SPIS_CTLR0_SRL_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SPIS_CTLR0_SRL register field value. */ +#define ALT_SPIS_CTLR0_SRL_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SPIS_CTLR0_SRL register field. */ +#define ALT_SPIS_CTLR0_SRL_RESET 0x0 +/* Extracts the ALT_SPIS_CTLR0_SRL field value from a register. */ +#define ALT_SPIS_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SPIS_CTLR0_SRL register field value suitable for setting the register. */ +#define ALT_SPIS_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Control Frame Size - cfs + * + * Selects the length of the control word for the Microwire frame format. The + * length (in bits) is the value of this field plus 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_CFS register field. */ +#define ALT_SPIS_CTLR0_CFS_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_CFS register field. */ +#define ALT_SPIS_CTLR0_CFS_MSB 15 +/* The width in bits of the ALT_SPIS_CTLR0_CFS register field. */ +#define ALT_SPIS_CTLR0_CFS_WIDTH 4 +/* The mask used to set the ALT_SPIS_CTLR0_CFS register field value. */ +#define ALT_SPIS_CTLR0_CFS_SET_MSK 0x0000f000 +/* The mask used to clear the ALT_SPIS_CTLR0_CFS register field value. */ +#define ALT_SPIS_CTLR0_CFS_CLR_MSK 0xffff0fff +/* The reset value of the ALT_SPIS_CTLR0_CFS register field. */ +#define ALT_SPIS_CTLR0_CFS_RESET 0x0 +/* Extracts the ALT_SPIS_CTLR0_CFS field value from a register. */ +#define ALT_SPIS_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12) +/* Produces a ALT_SPIS_CTLR0_CFS register field value suitable for setting the register. */ +#define ALT_SPIS_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_CTLR0. + */ +struct ALT_SPIS_CTLR0_s +{ + uint32_t dfs : 4; /* Data Frame Size */ + uint32_t frf : 2; /* Frame Format */ + uint32_t scph : 1; /* Serial Clock Phase */ + uint32_t scpol : 1; /* Serial Clock Polarity */ + uint32_t tmod : 2; /* Transfer Mode */ + uint32_t slv_oe : 1; /* Slave Output Enable */ + uint32_t srl : 1; /* Shift Register Loop */ + uint32_t cfs : 4; /* Control Frame Size */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_CTLR0. */ +typedef volatile struct ALT_SPIS_CTLR0_s ALT_SPIS_CTLR0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_CTLR0 register from the beginning of the component. */ +#define ALT_SPIS_CTLR0_OFST 0x0 +/* The address of the ALT_SPIS_CTLR0 register. */ +#define ALT_SPIS_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTLR0_OFST)) + +/* + * Register : Enable Register - spienr + * + * Enables and disables all SPI operations. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [0] | RW | 0x0 | Enable + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Enable - spi_en + * + * When disabled, all serial transfers are halted immediately. Transmit and receive + * FIFO buffers are cleared when the device is disabled. It is impossible to + * program some of the SPI Slave control registers when enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------ + * ALT_SPIS_SPIENR_SPI_EN_E_DISD | 0x0 | Disables serial transfer operations + * ALT_SPIS_SPIENR_SPI_EN_E_END | 0x1 | Enables serial transfer operations + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_SPIENR_SPI_EN + * + * Disables serial transfer operations + */ +#define ALT_SPIS_SPIENR_SPI_EN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SPIS_SPIENR_SPI_EN + * + * Enables serial transfer operations + */ +#define ALT_SPIS_SPIENR_SPI_EN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_SPIENR_SPI_EN register field. */ +#define ALT_SPIS_SPIENR_SPI_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_SPIENR_SPI_EN register field. */ +#define ALT_SPIS_SPIENR_SPI_EN_MSB 0 +/* The width in bits of the ALT_SPIS_SPIENR_SPI_EN register field. */ +#define ALT_SPIS_SPIENR_SPI_EN_WIDTH 1 +/* The mask used to set the ALT_SPIS_SPIENR_SPI_EN register field value. */ +#define ALT_SPIS_SPIENR_SPI_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_SPIENR_SPI_EN register field value. */ +#define ALT_SPIS_SPIENR_SPI_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_SPIENR_SPI_EN register field. */ +#define ALT_SPIS_SPIENR_SPI_EN_RESET 0x0 +/* Extracts the ALT_SPIS_SPIENR_SPI_EN field value from a register. */ +#define ALT_SPIS_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_SPIENR_SPI_EN register field value suitable for setting the register. */ +#define ALT_SPIS_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_SPIENR. + */ +struct ALT_SPIS_SPIENR_s +{ + uint32_t spi_en : 1; /* Enable */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_SPIENR. */ +typedef volatile struct ALT_SPIS_SPIENR_s ALT_SPIS_SPIENR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_SPIENR register from the beginning of the component. */ +#define ALT_SPIS_SPIENR_OFST 0x8 +/* The address of the ALT_SPIS_SPIENR register. */ +#define ALT_SPIS_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPIENR_OFST)) + +/* + * Register : Microwire Control Register - mwcr + * + * This register controls the direction of the data word for the half-duplex + * Microwire serial protocol. It is impossible to write to this register when the + * SPI Slave is enabled. The SPI Slave is enabled and disabled by writing to the + * SPIENR register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | Microwire Transfer Mode + * [1] | RW | 0x0 | Microwire Control + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Microwire Transfer Mode - mwmod + * + * Defines whether the Microwire transfer is sequential or non-sequential. When + * sequential mode is used, only one control word is needed to transmit or receive + * a block of data words. When non-sequential mode is used, there must be a control + * word for each data word that is transmitted or received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:------------------------ + * ALT_SPIS_MWCR_MWMOD_E_NONSEQ | 0x0 | non-sequential transfer + * ALT_SPIS_MWCR_MWMOD_E_SEQ | 0x1 | sequential transfer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_MWCR_MWMOD + * + * non-sequential transfer + */ +#define ALT_SPIS_MWCR_MWMOD_E_NONSEQ 0x0 +/* + * Enumerated value for register field ALT_SPIS_MWCR_MWMOD + * + * sequential transfer + */ +#define ALT_SPIS_MWCR_MWMOD_E_SEQ 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_MWCR_MWMOD register field. */ +#define ALT_SPIS_MWCR_MWMOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_MWCR_MWMOD register field. */ +#define ALT_SPIS_MWCR_MWMOD_MSB 0 +/* The width in bits of the ALT_SPIS_MWCR_MWMOD register field. */ +#define ALT_SPIS_MWCR_MWMOD_WIDTH 1 +/* The mask used to set the ALT_SPIS_MWCR_MWMOD register field value. */ +#define ALT_SPIS_MWCR_MWMOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_MWCR_MWMOD register field value. */ +#define ALT_SPIS_MWCR_MWMOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_MWCR_MWMOD register field. */ +#define ALT_SPIS_MWCR_MWMOD_RESET 0x0 +/* Extracts the ALT_SPIS_MWCR_MWMOD field value from a register. */ +#define ALT_SPIS_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_MWCR_MWMOD register field value suitable for setting the register. */ +#define ALT_SPIS_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Microwire Control - mdd + * + * Defines the direction of the data word when the Microwire serial protocol is + * used. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------- + * ALT_SPIS_MWCR_MDD_E_RXMOD | 0x0 | SPI Slave receives data + * ALT_SPIS_MWCR_MDD_E_TXMOD | 0x1 | SPI Slave transmits data + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_MWCR_MDD + * + * SPI Slave receives data + */ +#define ALT_SPIS_MWCR_MDD_E_RXMOD 0x0 +/* + * Enumerated value for register field ALT_SPIS_MWCR_MDD + * + * SPI Slave transmits data + */ +#define ALT_SPIS_MWCR_MDD_E_TXMOD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_MWCR_MDD register field. */ +#define ALT_SPIS_MWCR_MDD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_MWCR_MDD register field. */ +#define ALT_SPIS_MWCR_MDD_MSB 1 +/* The width in bits of the ALT_SPIS_MWCR_MDD register field. */ +#define ALT_SPIS_MWCR_MDD_WIDTH 1 +/* The mask used to set the ALT_SPIS_MWCR_MDD register field value. */ +#define ALT_SPIS_MWCR_MDD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIS_MWCR_MDD register field value. */ +#define ALT_SPIS_MWCR_MDD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIS_MWCR_MDD register field. */ +#define ALT_SPIS_MWCR_MDD_RESET 0x0 +/* Extracts the ALT_SPIS_MWCR_MDD field value from a register. */ +#define ALT_SPIS_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIS_MWCR_MDD register field value suitable for setting the register. */ +#define ALT_SPIS_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_MWCR. + */ +struct ALT_SPIS_MWCR_s +{ + uint32_t mwmod : 1; /* Microwire Transfer Mode */ + uint32_t mdd : 1; /* Microwire Control */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_MWCR. */ +typedef volatile struct ALT_SPIS_MWCR_s ALT_SPIS_MWCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_MWCR register from the beginning of the component. */ +#define ALT_SPIS_MWCR_OFST 0xc +/* The address of the ALT_SPIS_MWCR register. */ +#define ALT_SPIS_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MWCR_OFST)) + +/* + * Register : Transmit FIFO Threshold Level Register - txftlr + * + * This register controls the threshold value for the transmit FIFO memory. It is + * impossible to write to this register when the SPI Slave is enabled. The SPI + * Slave is enabled and disabled by writing to the SPIENR register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [7:0] | RW | 0x0 | Transmit FIFO Threshold + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Threshold - tft + * + * Controls the level of entries (or below) at which the transmit FIFO controller + * triggers an interrupt. When the number of transmit FIFO entries is less than or + * equal to this value, the transmit FIFO empty interrupt is triggered. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_TXFTLR_TFT register field. */ +#define ALT_SPIS_TXFTLR_TFT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_TXFTLR_TFT register field. */ +#define ALT_SPIS_TXFTLR_TFT_MSB 7 +/* The width in bits of the ALT_SPIS_TXFTLR_TFT register field. */ +#define ALT_SPIS_TXFTLR_TFT_WIDTH 8 +/* The mask used to set the ALT_SPIS_TXFTLR_TFT register field value. */ +#define ALT_SPIS_TXFTLR_TFT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SPIS_TXFTLR_TFT register field value. */ +#define ALT_SPIS_TXFTLR_TFT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SPIS_TXFTLR_TFT register field. */ +#define ALT_SPIS_TXFTLR_TFT_RESET 0x0 +/* Extracts the ALT_SPIS_TXFTLR_TFT field value from a register. */ +#define ALT_SPIS_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SPIS_TXFTLR_TFT register field value suitable for setting the register. */ +#define ALT_SPIS_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_TXFTLR. + */ +struct ALT_SPIS_TXFTLR_s +{ + uint32_t tft : 8; /* Transmit FIFO Threshold */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_TXFTLR. */ +typedef volatile struct ALT_SPIS_TXFTLR_s ALT_SPIS_TXFTLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_TXFTLR register from the beginning of the component. */ +#define ALT_SPIS_TXFTLR_OFST 0x18 +/* The address of the ALT_SPIS_TXFTLR register. */ +#define ALT_SPIS_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST)) + +/* + * Register : Receive FIFO Threshold Level Register - rxftlr + * + * This register controls the threshold value for the receive FIFO memory. It is + * impossible to write to this register when the SPI Slave is enabled. The SPI + * Slave is enabled and disabled by writing to the SPIENR register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [7:0] | RW | 0x0 | Receive FIFO Threshold + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Threshold - rft + * + * Controls the level of entries (or above) at which the receive FIFO controller + * triggers an interrupt. When the number of receive FIFO entries is greater than + * or equal to this value + 1, the receive FIFO full interrupt is triggered. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_RXFTLR_RFT register field. */ +#define ALT_SPIS_RXFTLR_RFT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_RXFTLR_RFT register field. */ +#define ALT_SPIS_RXFTLR_RFT_MSB 7 +/* The width in bits of the ALT_SPIS_RXFTLR_RFT register field. */ +#define ALT_SPIS_RXFTLR_RFT_WIDTH 8 +/* The mask used to set the ALT_SPIS_RXFTLR_RFT register field value. */ +#define ALT_SPIS_RXFTLR_RFT_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SPIS_RXFTLR_RFT register field value. */ +#define ALT_SPIS_RXFTLR_RFT_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SPIS_RXFTLR_RFT register field. */ +#define ALT_SPIS_RXFTLR_RFT_RESET 0x0 +/* Extracts the ALT_SPIS_RXFTLR_RFT field value from a register. */ +#define ALT_SPIS_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SPIS_RXFTLR_RFT register field value suitable for setting the register. */ +#define ALT_SPIS_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_RXFTLR. + */ +struct ALT_SPIS_RXFTLR_s +{ + uint32_t rft : 8; /* Receive FIFO Threshold */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_RXFTLR. */ +typedef volatile struct ALT_SPIS_RXFTLR_s ALT_SPIS_RXFTLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_RXFTLR register from the beginning of the component. */ +#define ALT_SPIS_RXFTLR_OFST 0x1c +/* The address of the ALT_SPIS_RXFTLR register. */ +#define ALT_SPIS_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFTLR_OFST)) + +/* + * Register : Transmit FIFO Level Register - txflr + * + * This register contains the number of valid data entries in the transmit FIFO + * memory. Ranges from 0 to 256. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [8:0] | R | 0x0 | Transmit FIFO Level + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Level - txtfl + * + * Contains the number of valid data entries in the transmit FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_TXFLR_TXTFL register field. */ +#define ALT_SPIS_TXFLR_TXTFL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_TXFLR_TXTFL register field. */ +#define ALT_SPIS_TXFLR_TXTFL_MSB 8 +/* The width in bits of the ALT_SPIS_TXFLR_TXTFL register field. */ +#define ALT_SPIS_TXFLR_TXTFL_WIDTH 9 +/* The mask used to set the ALT_SPIS_TXFLR_TXTFL register field value. */ +#define ALT_SPIS_TXFLR_TXTFL_SET_MSK 0x000001ff +/* The mask used to clear the ALT_SPIS_TXFLR_TXTFL register field value. */ +#define ALT_SPIS_TXFLR_TXTFL_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_SPIS_TXFLR_TXTFL register field. */ +#define ALT_SPIS_TXFLR_TXTFL_RESET 0x0 +/* Extracts the ALT_SPIS_TXFLR_TXTFL field value from a register. */ +#define ALT_SPIS_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_SPIS_TXFLR_TXTFL register field value suitable for setting the register. */ +#define ALT_SPIS_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_TXFLR. + */ +struct ALT_SPIS_TXFLR_s +{ + const uint32_t txtfl : 9; /* Transmit FIFO Level */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_TXFLR. */ +typedef volatile struct ALT_SPIS_TXFLR_s ALT_SPIS_TXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_TXFLR register from the beginning of the component. */ +#define ALT_SPIS_TXFLR_OFST 0x20 +/* The address of the ALT_SPIS_TXFLR register. */ +#define ALT_SPIS_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFLR_OFST)) + +/* + * Register : Receive FIFO Level Register - rxflr + * + * This register contains the number of valid data entriesin the receive FIFO + * memory. This register can be read at any time. Ranges from 0 to 256. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [8:0] | R | 0x0 | Receive FIFO Level + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Level - rxtfl + * + * Contains the number of valid data entries in the receive FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_RXFLR_RXTFL register field. */ +#define ALT_SPIS_RXFLR_RXTFL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_RXFLR_RXTFL register field. */ +#define ALT_SPIS_RXFLR_RXTFL_MSB 8 +/* The width in bits of the ALT_SPIS_RXFLR_RXTFL register field. */ +#define ALT_SPIS_RXFLR_RXTFL_WIDTH 9 +/* The mask used to set the ALT_SPIS_RXFLR_RXTFL register field value. */ +#define ALT_SPIS_RXFLR_RXTFL_SET_MSK 0x000001ff +/* The mask used to clear the ALT_SPIS_RXFLR_RXTFL register field value. */ +#define ALT_SPIS_RXFLR_RXTFL_CLR_MSK 0xfffffe00 +/* The reset value of the ALT_SPIS_RXFLR_RXTFL register field. */ +#define ALT_SPIS_RXFLR_RXTFL_RESET 0x0 +/* Extracts the ALT_SPIS_RXFLR_RXTFL field value from a register. */ +#define ALT_SPIS_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0) +/* Produces a ALT_SPIS_RXFLR_RXTFL register field value suitable for setting the register. */ +#define ALT_SPIS_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_RXFLR. + */ +struct ALT_SPIS_RXFLR_s +{ + const uint32_t rxtfl : 9; /* Receive FIFO Level */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_RXFLR. */ +typedef volatile struct ALT_SPIS_RXFLR_s ALT_SPIS_RXFLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_RXFLR register from the beginning of the component. */ +#define ALT_SPIS_RXFLR_OFST 0x24 +/* The address of the ALT_SPIS_RXFLR register. */ +#define ALT_SPIS_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFLR_OFST)) + +/* + * Register : Status Register - sr + * + * Reports FIFO transfer status, and any transmission/reception errors that may + * have occurred. The status register may be read at any time. None of the bits in + * this register request an interrupt. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | R | 0x0 | SPI Busy Flag + * [1] | R | 0x1 | Transmit FIFO Not Full + * [2] | R | 0x1 | Transmit FIFO Empty + * [3] | R | 0x0 | Receive FIFO Not Empty + * [4] | R | 0x0 | Receive FIFO Full + * [5] | R | 0x0 | Transmission Error + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SPI Busy Flag - busy + * + * Reports the status of a serial transfer + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------------------------------- + * ALT_SPIS_SR_BUSY_E_INACT | 0x0 | SPI Slave is inactive (idle or disabled) + * ALT_SPIS_SR_BUSY_E_ACT | 0x1 | SPI Slave is actively transferring data + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_SR_BUSY + * + * SPI Slave is inactive (idle or disabled) + */ +#define ALT_SPIS_SR_BUSY_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_SR_BUSY + * + * SPI Slave is actively transferring data + */ +#define ALT_SPIS_SR_BUSY_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_BUSY register field. */ +#define ALT_SPIS_SR_BUSY_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_BUSY register field. */ +#define ALT_SPIS_SR_BUSY_MSB 0 +/* The width in bits of the ALT_SPIS_SR_BUSY register field. */ +#define ALT_SPIS_SR_BUSY_WIDTH 1 +/* The mask used to set the ALT_SPIS_SR_BUSY register field value. */ +#define ALT_SPIS_SR_BUSY_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_SR_BUSY register field value. */ +#define ALT_SPIS_SR_BUSY_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_SR_BUSY register field. */ +#define ALT_SPIS_SR_BUSY_RESET 0x0 +/* Extracts the ALT_SPIS_SR_BUSY field value from a register. */ +#define ALT_SPIS_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_SR_BUSY register field value suitable for setting the register. */ +#define ALT_SPIS_SR_BUSY_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit FIFO Not Full - tfnf + * + * Reports the status of the transmit FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------- + * ALT_SPIS_SR_TFNF_E_FULL | 0x0 | Transmit FIFO is full + * ALT_SPIS_SR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_SR_TFNF + * + * Transmit FIFO is full + */ +#define ALT_SPIS_SR_TFNF_E_FULL 0x0 +/* + * Enumerated value for register field ALT_SPIS_SR_TFNF + * + * Transmit FIFO is not full + */ +#define ALT_SPIS_SR_TFNF_E_NOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TFNF register field. */ +#define ALT_SPIS_SR_TFNF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TFNF register field. */ +#define ALT_SPIS_SR_TFNF_MSB 1 +/* The width in bits of the ALT_SPIS_SR_TFNF register field. */ +#define ALT_SPIS_SR_TFNF_WIDTH 1 +/* The mask used to set the ALT_SPIS_SR_TFNF register field value. */ +#define ALT_SPIS_SR_TFNF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIS_SR_TFNF register field value. */ +#define ALT_SPIS_SR_TFNF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIS_SR_TFNF register field. */ +#define ALT_SPIS_SR_TFNF_RESET 0x1 +/* Extracts the ALT_SPIS_SR_TFNF field value from a register. */ +#define ALT_SPIS_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIS_SR_TFNF register field value suitable for setting the register. */ +#define ALT_SPIS_SR_TFNF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Transmit FIFO Empty - tfe + * + * Reports the status of transmit FIFO empty. This bit field does not request an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------------- + * ALT_SPIS_SR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty + * ALT_SPIS_SR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_SR_TFE + * + * Transmit FIFO is empty + */ +#define ALT_SPIS_SR_TFE_E_EMPTY 0x1 +/* + * Enumerated value for register field ALT_SPIS_SR_TFE + * + * Transmit FIFO is not empty + */ +#define ALT_SPIS_SR_TFE_E_NOTEMPTY 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TFE register field. */ +#define ALT_SPIS_SR_TFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TFE register field. */ +#define ALT_SPIS_SR_TFE_MSB 2 +/* The width in bits of the ALT_SPIS_SR_TFE register field. */ +#define ALT_SPIS_SR_TFE_WIDTH 1 +/* The mask used to set the ALT_SPIS_SR_TFE register field value. */ +#define ALT_SPIS_SR_TFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SPIS_SR_TFE register field value. */ +#define ALT_SPIS_SR_TFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SPIS_SR_TFE register field. */ +#define ALT_SPIS_SR_TFE_RESET 0x1 +/* Extracts the ALT_SPIS_SR_TFE field value from a register. */ +#define ALT_SPIS_SR_TFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SPIS_SR_TFE register field value suitable for setting the register. */ +#define ALT_SPIS_SR_TFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Not Empty - rfne + * + * Reports the status of receive FIFO empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------------- + * ALT_SPIS_SR_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty + * ALT_SPIS_SR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_SR_RFNE + * + * Receive FIFO is empty + */ +#define ALT_SPIS_SR_RFNE_E_EMPTY 0x0 +/* + * Enumerated value for register field ALT_SPIS_SR_RFNE + * + * Receive FIFO is not empty + */ +#define ALT_SPIS_SR_RFNE_E_NOTEMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RFNE register field. */ +#define ALT_SPIS_SR_RFNE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RFNE register field. */ +#define ALT_SPIS_SR_RFNE_MSB 3 +/* The width in bits of the ALT_SPIS_SR_RFNE register field. */ +#define ALT_SPIS_SR_RFNE_WIDTH 1 +/* The mask used to set the ALT_SPIS_SR_RFNE register field value. */ +#define ALT_SPIS_SR_RFNE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SPIS_SR_RFNE register field value. */ +#define ALT_SPIS_SR_RFNE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SPIS_SR_RFNE register field. */ +#define ALT_SPIS_SR_RFNE_RESET 0x0 +/* Extracts the ALT_SPIS_SR_RFNE field value from a register. */ +#define ALT_SPIS_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SPIS_SR_RFNE register field value suitable for setting the register. */ +#define ALT_SPIS_SR_RFNE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full - rff + * + * Reports the status of receive FIFO Full + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------- + * ALT_SPIS_SR_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full + * ALT_SPIS_SR_RFF_E_FULL | 0x1 | Receive FIFO is full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_SR_RFF + * + * Receive FIFO is not full + */ +#define ALT_SPIS_SR_RFF_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_SPIS_SR_RFF + * + * Receive FIFO is full + */ +#define ALT_SPIS_SR_RFF_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RFF register field. */ +#define ALT_SPIS_SR_RFF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RFF register field. */ +#define ALT_SPIS_SR_RFF_MSB 4 +/* The width in bits of the ALT_SPIS_SR_RFF register field. */ +#define ALT_SPIS_SR_RFF_WIDTH 1 +/* The mask used to set the ALT_SPIS_SR_RFF register field value. */ +#define ALT_SPIS_SR_RFF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SPIS_SR_RFF register field value. */ +#define ALT_SPIS_SR_RFF_CLR_MSK 0xffffffef +/* The reset value of the ALT_SPIS_SR_RFF register field. */ +#define ALT_SPIS_SR_RFF_RESET 0x0 +/* Extracts the ALT_SPIS_SR_RFF field value from a register. */ +#define ALT_SPIS_SR_RFF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SPIS_SR_RFF register field value suitable for setting the register. */ +#define ALT_SPIS_SR_RFF_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Transmission Error - txe + * + * Data from the previous transmission is resent on the txd line. This bit is + * cleared when read. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------- + * ALT_SPIS_SR_TXE_E_NOERROR | 0x0 | No Error + * ALT_SPIS_SR_TXE_E_ERROR | 0x1 | Transmission Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_SR_TXE + * + * No Error + */ +#define ALT_SPIS_SR_TXE_E_NOERROR 0x0 +/* + * Enumerated value for register field ALT_SPIS_SR_TXE + * + * Transmission Error + */ +#define ALT_SPIS_SR_TXE_E_ERROR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TXE register field. */ +#define ALT_SPIS_SR_TXE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TXE register field. */ +#define ALT_SPIS_SR_TXE_MSB 5 +/* The width in bits of the ALT_SPIS_SR_TXE register field. */ +#define ALT_SPIS_SR_TXE_WIDTH 1 +/* The mask used to set the ALT_SPIS_SR_TXE register field value. */ +#define ALT_SPIS_SR_TXE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SPIS_SR_TXE register field value. */ +#define ALT_SPIS_SR_TXE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SPIS_SR_TXE register field. */ +#define ALT_SPIS_SR_TXE_RESET 0x0 +/* Extracts the ALT_SPIS_SR_TXE field value from a register. */ +#define ALT_SPIS_SR_TXE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SPIS_SR_TXE register field value suitable for setting the register. */ +#define ALT_SPIS_SR_TXE_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_SR. + */ +struct ALT_SPIS_SR_s +{ + const uint32_t busy : 1; /* SPI Busy Flag */ + const uint32_t tfnf : 1; /* Transmit FIFO Not Full */ + const uint32_t tfe : 1; /* Transmit FIFO Empty */ + const uint32_t rfne : 1; /* Receive FIFO Not Empty */ + const uint32_t rff : 1; /* Receive FIFO Full */ + const uint32_t txe : 1; /* Transmission Error */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_SR. */ +typedef volatile struct ALT_SPIS_SR_s ALT_SPIS_SR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_SR register from the beginning of the component. */ +#define ALT_SPIS_SR_OFST 0x28 +/* The address of the ALT_SPIS_SR register. */ +#define ALT_SPIS_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST)) + +/* + * Register : Interrupt Mask Register - imr + * + * This register masks or enables all interrupts generated by the SPI Slave. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x1 | Transmit FIFO Empty Interrupt Mask + * [1] | RW | 0x1 | Transmit FIFO Overflow Interrupt Mask + * [2] | RW | 0x1 | Receive FIFO Underflow Interrupt Mask + * [3] | RW | 0x1 | Receive FIFO Overflow Interrupt Mask + * [4] | RW | 0x1 | Receive FIFO Full Interrupt Mask + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Empty Interrupt Mask - txeim + * + * Empty mask. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIS_IMR_TXEIM_E_MSKED | 0x0 | spi_txe_intr interrupt is masked (disabled) + * ALT_SPIS_IMR_TXEIM_E_END | 0x1 | spi_txe_intr interrupt is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_IMR_TXEIM + * + * spi_txe_intr interrupt is masked (disabled) + */ +#define ALT_SPIS_IMR_TXEIM_E_MSKED 0x0 +/* + * Enumerated value for register field ALT_SPIS_IMR_TXEIM + * + * spi_txe_intr interrupt is enabled + */ +#define ALT_SPIS_IMR_TXEIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_TXEIM register field. */ +#define ALT_SPIS_IMR_TXEIM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_TXEIM register field. */ +#define ALT_SPIS_IMR_TXEIM_MSB 0 +/* The width in bits of the ALT_SPIS_IMR_TXEIM register field. */ +#define ALT_SPIS_IMR_TXEIM_WIDTH 1 +/* The mask used to set the ALT_SPIS_IMR_TXEIM register field value. */ +#define ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_IMR_TXEIM register field value. */ +#define ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_IMR_TXEIM register field. */ +#define ALT_SPIS_IMR_TXEIM_RESET 0x1 +/* Extracts the ALT_SPIS_IMR_TXEIM field value from a register. */ +#define ALT_SPIS_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_IMR_TXEIM register field value suitable for setting the register. */ +#define ALT_SPIS_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit FIFO Overflow Interrupt Mask - txoim + * + * Overflow mask. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIS_IMR_TXOIM_E_MSKED | 0x0 | spi_txo_intr interrupt is masked (disabled) + * ALT_SPIS_IMR_TXOIM_E_END | 0x1 | spi_txo_intr interrupt is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_IMR_TXOIM + * + * spi_txo_intr interrupt is masked (disabled) + */ +#define ALT_SPIS_IMR_TXOIM_E_MSKED 0x0 +/* + * Enumerated value for register field ALT_SPIS_IMR_TXOIM + * + * spi_txo_intr interrupt is enabled + */ +#define ALT_SPIS_IMR_TXOIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_TXOIM register field. */ +#define ALT_SPIS_IMR_TXOIM_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_TXOIM register field. */ +#define ALT_SPIS_IMR_TXOIM_MSB 1 +/* The width in bits of the ALT_SPIS_IMR_TXOIM register field. */ +#define ALT_SPIS_IMR_TXOIM_WIDTH 1 +/* The mask used to set the ALT_SPIS_IMR_TXOIM register field value. */ +#define ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIS_IMR_TXOIM register field value. */ +#define ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIS_IMR_TXOIM register field. */ +#define ALT_SPIS_IMR_TXOIM_RESET 0x1 +/* Extracts the ALT_SPIS_IMR_TXOIM field value from a register. */ +#define ALT_SPIS_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIS_IMR_TXOIM register field value suitable for setting the register. */ +#define ALT_SPIS_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive FIFO Underflow Interrupt Mask - rxuim + * + * Underfow Mask + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIS_IMR_RXUIM_E_MSKED | 0x0 | spi_rxu_intr interrupt is masked (disabled) + * ALT_SPIS_IMR_RXUIM_E_END | 0x1 | spi_rxu_intr interrupt is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_IMR_RXUIM + * + * spi_rxu_intr interrupt is masked (disabled) + */ +#define ALT_SPIS_IMR_RXUIM_E_MSKED 0x0 +/* + * Enumerated value for register field ALT_SPIS_IMR_RXUIM + * + * spi_rxu_intr interrupt is enabled + */ +#define ALT_SPIS_IMR_RXUIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXUIM register field. */ +#define ALT_SPIS_IMR_RXUIM_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXUIM register field. */ +#define ALT_SPIS_IMR_RXUIM_MSB 2 +/* The width in bits of the ALT_SPIS_IMR_RXUIM register field. */ +#define ALT_SPIS_IMR_RXUIM_WIDTH 1 +/* The mask used to set the ALT_SPIS_IMR_RXUIM register field value. */ +#define ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SPIS_IMR_RXUIM register field value. */ +#define ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SPIS_IMR_RXUIM register field. */ +#define ALT_SPIS_IMR_RXUIM_RESET 0x1 +/* Extracts the ALT_SPIS_IMR_RXUIM field value from a register. */ +#define ALT_SPIS_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SPIS_IMR_RXUIM register field value suitable for setting the register. */ +#define ALT_SPIS_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Overflow Interrupt Mask - rxoim + * + * Overflow Mask. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIS_IMR_RXOIM_E_MSKED | 0x0 | spi_rxo_intr interrupt is masked (disabled) + * ALT_SPIS_IMR_RXOIM_E_END | 0x1 | spi_rxo_intr interrupt is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_IMR_RXOIM + * + * spi_rxo_intr interrupt is masked (disabled) + */ +#define ALT_SPIS_IMR_RXOIM_E_MSKED 0x0 +/* + * Enumerated value for register field ALT_SPIS_IMR_RXOIM + * + * spi_rxo_intr interrupt is enabled + */ +#define ALT_SPIS_IMR_RXOIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXOIM register field. */ +#define ALT_SPIS_IMR_RXOIM_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXOIM register field. */ +#define ALT_SPIS_IMR_RXOIM_MSB 3 +/* The width in bits of the ALT_SPIS_IMR_RXOIM register field. */ +#define ALT_SPIS_IMR_RXOIM_WIDTH 1 +/* The mask used to set the ALT_SPIS_IMR_RXOIM register field value. */ +#define ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SPIS_IMR_RXOIM register field value. */ +#define ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SPIS_IMR_RXOIM register field. */ +#define ALT_SPIS_IMR_RXOIM_RESET 0x1 +/* Extracts the ALT_SPIS_IMR_RXOIM field value from a register. */ +#define ALT_SPIS_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SPIS_IMR_RXOIM register field value suitable for setting the register. */ +#define ALT_SPIS_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full Interrupt Mask - rxfim + * + * FIFO Full Mask. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------------------------------------- + * ALT_SPIS_IMR_RXFIM_E_MSKED | 0x0 | spi_rxf_intr interrupt is masked (disabled) + * ALT_SPIS_IMR_RXFIM_E_END | 0x1 | spi_rxf_intr interrupt is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_IMR_RXFIM + * + * spi_rxf_intr interrupt is masked (disabled) + */ +#define ALT_SPIS_IMR_RXFIM_E_MSKED 0x0 +/* + * Enumerated value for register field ALT_SPIS_IMR_RXFIM + * + * spi_rxf_intr interrupt is enabled + */ +#define ALT_SPIS_IMR_RXFIM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXFIM register field. */ +#define ALT_SPIS_IMR_RXFIM_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXFIM register field. */ +#define ALT_SPIS_IMR_RXFIM_MSB 4 +/* The width in bits of the ALT_SPIS_IMR_RXFIM register field. */ +#define ALT_SPIS_IMR_RXFIM_WIDTH 1 +/* The mask used to set the ALT_SPIS_IMR_RXFIM register field value. */ +#define ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SPIS_IMR_RXFIM register field value. */ +#define ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef +/* The reset value of the ALT_SPIS_IMR_RXFIM register field. */ +#define ALT_SPIS_IMR_RXFIM_RESET 0x1 +/* Extracts the ALT_SPIS_IMR_RXFIM field value from a register. */ +#define ALT_SPIS_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SPIS_IMR_RXFIM register field value suitable for setting the register. */ +#define ALT_SPIS_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_IMR. + */ +struct ALT_SPIS_IMR_s +{ + uint32_t txeim : 1; /* Transmit FIFO Empty Interrupt Mask */ + uint32_t txoim : 1; /* Transmit FIFO Overflow Interrupt Mask */ + uint32_t rxuim : 1; /* Receive FIFO Underflow Interrupt Mask */ + uint32_t rxoim : 1; /* Receive FIFO Overflow Interrupt Mask */ + uint32_t rxfim : 1; /* Receive FIFO Full Interrupt Mask */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_IMR. */ +typedef volatile struct ALT_SPIS_IMR_s ALT_SPIS_IMR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_IMR register from the beginning of the component. */ +#define ALT_SPIS_IMR_OFST 0x2c +/* The address of the ALT_SPIS_IMR register. */ +#define ALT_SPIS_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST)) + +/* + * Register : Interrupt Status Register - isr + * + * This register reports the status of the SPI Slave interrupts after they have + * been masked. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | R | 0x0 | Transmit FIFO Empty Interrupt Status + * [1] | R | 0x0 | Transmit FIFO Overflow Interrupt Status + * [2] | R | 0x0 | Receive FIFO Underflow Interrupt Status + * [3] | R | 0x0 | Receive FIFO Overflow Interrupt Status + * [4] | R | 0x0 | Receive FIFO Full Interrupt Status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Empty Interrupt Status - txeis + * + * Empty Status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------------------------------- + * ALT_SPIS_ISR_TXEIS_E_INACT | 0x0 | spi_txe_intr interrupt is not active after + * : | | masking + * ALT_SPIS_ISR_TXEIS_E_ACT | 0x1 | spi_txe_intr interrupt is active after masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_ISR_TXEIS + * + * spi_txe_intr interrupt is not active after masking + */ +#define ALT_SPIS_ISR_TXEIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_ISR_TXEIS + * + * spi_txe_intr interrupt is active after masking + */ +#define ALT_SPIS_ISR_TXEIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_TXEIS register field. */ +#define ALT_SPIS_ISR_TXEIS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_TXEIS register field. */ +#define ALT_SPIS_ISR_TXEIS_MSB 0 +/* The width in bits of the ALT_SPIS_ISR_TXEIS register field. */ +#define ALT_SPIS_ISR_TXEIS_WIDTH 1 +/* The mask used to set the ALT_SPIS_ISR_TXEIS register field value. */ +#define ALT_SPIS_ISR_TXEIS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_ISR_TXEIS register field value. */ +#define ALT_SPIS_ISR_TXEIS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_ISR_TXEIS register field. */ +#define ALT_SPIS_ISR_TXEIS_RESET 0x0 +/* Extracts the ALT_SPIS_ISR_TXEIS field value from a register. */ +#define ALT_SPIS_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_ISR_TXEIS register field value suitable for setting the register. */ +#define ALT_SPIS_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit FIFO Overflow Interrupt Status - txois + * + * Overflow Status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------------------------------- + * ALT_SPIS_ISR_TXOIS_E_INACT | 0x0 | spi_txo_intr interrupt is not active after + * : | | masking + * ALT_SPIS_ISR_TXOIS_E_ACT | 0x1 | spi_txo_intr interrupt is active after masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_ISR_TXOIS + * + * spi_txo_intr interrupt is not active after masking + */ +#define ALT_SPIS_ISR_TXOIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_ISR_TXOIS + * + * spi_txo_intr interrupt is active after masking + */ +#define ALT_SPIS_ISR_TXOIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_TXOIS register field. */ +#define ALT_SPIS_ISR_TXOIS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_TXOIS register field. */ +#define ALT_SPIS_ISR_TXOIS_MSB 1 +/* The width in bits of the ALT_SPIS_ISR_TXOIS register field. */ +#define ALT_SPIS_ISR_TXOIS_WIDTH 1 +/* The mask used to set the ALT_SPIS_ISR_TXOIS register field value. */ +#define ALT_SPIS_ISR_TXOIS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIS_ISR_TXOIS register field value. */ +#define ALT_SPIS_ISR_TXOIS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIS_ISR_TXOIS register field. */ +#define ALT_SPIS_ISR_TXOIS_RESET 0x0 +/* Extracts the ALT_SPIS_ISR_TXOIS field value from a register. */ +#define ALT_SPIS_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIS_ISR_TXOIS register field value suitable for setting the register. */ +#define ALT_SPIS_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive FIFO Underflow Interrupt Status - rxuis + * + * Underflow Status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------------------------------- + * ALT_SPIS_ISR_RXUIS_E_INACT | 0x0 | spi_rxu_intr interrupt is not active after + * : | | masking + * ALT_SPIS_ISR_RXUIS_E_ACT | 0x1 | spi_rxu_intr interrupt is active after masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_ISR_RXUIS + * + * spi_rxu_intr interrupt is not active after masking + */ +#define ALT_SPIS_ISR_RXUIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_ISR_RXUIS + * + * spi_rxu_intr interrupt is active after masking + */ +#define ALT_SPIS_ISR_RXUIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXUIS register field. */ +#define ALT_SPIS_ISR_RXUIS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXUIS register field. */ +#define ALT_SPIS_ISR_RXUIS_MSB 2 +/* The width in bits of the ALT_SPIS_ISR_RXUIS register field. */ +#define ALT_SPIS_ISR_RXUIS_WIDTH 1 +/* The mask used to set the ALT_SPIS_ISR_RXUIS register field value. */ +#define ALT_SPIS_ISR_RXUIS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SPIS_ISR_RXUIS register field value. */ +#define ALT_SPIS_ISR_RXUIS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SPIS_ISR_RXUIS register field. */ +#define ALT_SPIS_ISR_RXUIS_RESET 0x0 +/* Extracts the ALT_SPIS_ISR_RXUIS field value from a register. */ +#define ALT_SPIS_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SPIS_ISR_RXUIS register field value suitable for setting the register. */ +#define ALT_SPIS_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Overflow Interrupt Status - rxois + * + * Overflow Status. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------------------------------- + * ALT_SPIS_ISR_RXOIS_E_INACT | 0x0 | spi_rxo_intr interrupt is not active after + * : | | masking + * ALT_SPIS_ISR_RXOIS_E_ACT | 0x1 | spi_rxo_intr interrupt is active after masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_ISR_RXOIS + * + * spi_rxo_intr interrupt is not active after masking + */ +#define ALT_SPIS_ISR_RXOIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_ISR_RXOIS + * + * spi_rxo_intr interrupt is active after masking + */ +#define ALT_SPIS_ISR_RXOIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXOIS register field. */ +#define ALT_SPIS_ISR_RXOIS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXOIS register field. */ +#define ALT_SPIS_ISR_RXOIS_MSB 3 +/* The width in bits of the ALT_SPIS_ISR_RXOIS register field. */ +#define ALT_SPIS_ISR_RXOIS_WIDTH 1 +/* The mask used to set the ALT_SPIS_ISR_RXOIS register field value. */ +#define ALT_SPIS_ISR_RXOIS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SPIS_ISR_RXOIS register field value. */ +#define ALT_SPIS_ISR_RXOIS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SPIS_ISR_RXOIS register field. */ +#define ALT_SPIS_ISR_RXOIS_RESET 0x0 +/* Extracts the ALT_SPIS_ISR_RXOIS field value from a register. */ +#define ALT_SPIS_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SPIS_ISR_RXOIS register field value suitable for setting the register. */ +#define ALT_SPIS_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full Interrupt Status - rxfis + * + * Full Status + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------------------------------- + * ALT_SPIS_ISR_RXFIS_E_INACT | 0x0 | spi_rxf_intr interrupt is not active after + * : | | masking + * ALT_SPIS_ISR_RXFIS_E_ACT | 0x1 | spi_rxf_intr interrupt is full after masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_ISR_RXFIS + * + * spi_rxf_intr interrupt is not active after masking + */ +#define ALT_SPIS_ISR_RXFIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_ISR_RXFIS + * + * spi_rxf_intr interrupt is full after masking + */ +#define ALT_SPIS_ISR_RXFIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXFIS register field. */ +#define ALT_SPIS_ISR_RXFIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXFIS register field. */ +#define ALT_SPIS_ISR_RXFIS_MSB 4 +/* The width in bits of the ALT_SPIS_ISR_RXFIS register field. */ +#define ALT_SPIS_ISR_RXFIS_WIDTH 1 +/* The mask used to set the ALT_SPIS_ISR_RXFIS register field value. */ +#define ALT_SPIS_ISR_RXFIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SPIS_ISR_RXFIS register field value. */ +#define ALT_SPIS_ISR_RXFIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_SPIS_ISR_RXFIS register field. */ +#define ALT_SPIS_ISR_RXFIS_RESET 0x0 +/* Extracts the ALT_SPIS_ISR_RXFIS field value from a register. */ +#define ALT_SPIS_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SPIS_ISR_RXFIS register field value suitable for setting the register. */ +#define ALT_SPIS_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_ISR. + */ +struct ALT_SPIS_ISR_s +{ + const uint32_t txeis : 1; /* Transmit FIFO Empty Interrupt Status */ + const uint32_t txois : 1; /* Transmit FIFO Overflow Interrupt Status */ + const uint32_t rxuis : 1; /* Receive FIFO Underflow Interrupt Status */ + const uint32_t rxois : 1; /* Receive FIFO Overflow Interrupt Status */ + const uint32_t rxfis : 1; /* Receive FIFO Full Interrupt Status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_ISR. */ +typedef volatile struct ALT_SPIS_ISR_s ALT_SPIS_ISR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_ISR register from the beginning of the component. */ +#define ALT_SPIS_ISR_OFST 0x30 +/* The address of the ALT_SPIS_ISR register. */ +#define ALT_SPIS_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ISR_OFST)) + +/* + * Register : Raw Interrupt Status Register - risr + * + * This register reports the status of the SPI Slave interrupts prior to masking. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transmit FIFO Empty Raw Interrupt Status + * [1] | R | 0x0 | Transmit FIFO Overflow Raw Interrupt Status + * [2] | R | 0x0 | Receive FIFO Underflow Raw Interrupt Status + * [3] | R | 0x0 | Receive FIFO Overflow Raw Interrupt Status + * [4] | R | 0x0 | Receive FIFO Full Raw Interrupt Status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Empty Raw Interrupt Status - txeir + * + * The interrupt is active or inactive prior to masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------------------------------- + * ALT_SPIS_RISR_TXEIR_E_INACT | 0x0 | spi_txe_intr interrupt is not active prior to + * : | | masking + * ALT_SPIS_RISR_TXEIR_E_ACT | 0x1 | spi_txe_intr interrupt is active prior masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_RISR_TXEIR + * + * spi_txe_intr interrupt is not active prior to masking + */ +#define ALT_SPIS_RISR_TXEIR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_RISR_TXEIR + * + * spi_txe_intr interrupt is active prior masking + */ +#define ALT_SPIS_RISR_TXEIR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_TXEIR register field. */ +#define ALT_SPIS_RISR_TXEIR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_TXEIR register field. */ +#define ALT_SPIS_RISR_TXEIR_MSB 0 +/* The width in bits of the ALT_SPIS_RISR_TXEIR register field. */ +#define ALT_SPIS_RISR_TXEIR_WIDTH 1 +/* The mask used to set the ALT_SPIS_RISR_TXEIR register field value. */ +#define ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_RISR_TXEIR register field value. */ +#define ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_RISR_TXEIR register field. */ +#define ALT_SPIS_RISR_TXEIR_RESET 0x0 +/* Extracts the ALT_SPIS_RISR_TXEIR field value from a register. */ +#define ALT_SPIS_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_RISR_TXEIR register field value suitable for setting the register. */ +#define ALT_SPIS_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit FIFO Overflow Raw Interrupt Status - txoir + * + * The interrupt is active or inactive prior to masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------------------------------- + * ALT_SPIS_RISR_TXOIR_E_INACT | 0x0 | spi_txo_intr interrupt is not active prior to + * : | | masking + * ALT_SPIS_RISR_TXOIR_E_ACT | 0x1 | spi_txo_intr interrupt is active prior masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_RISR_TXOIR + * + * spi_txo_intr interrupt is not active prior to masking + */ +#define ALT_SPIS_RISR_TXOIR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_RISR_TXOIR + * + * spi_txo_intr interrupt is active prior masking + */ +#define ALT_SPIS_RISR_TXOIR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_TXOIR register field. */ +#define ALT_SPIS_RISR_TXOIR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_TXOIR register field. */ +#define ALT_SPIS_RISR_TXOIR_MSB 1 +/* The width in bits of the ALT_SPIS_RISR_TXOIR register field. */ +#define ALT_SPIS_RISR_TXOIR_WIDTH 1 +/* The mask used to set the ALT_SPIS_RISR_TXOIR register field value. */ +#define ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIS_RISR_TXOIR register field value. */ +#define ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIS_RISR_TXOIR register field. */ +#define ALT_SPIS_RISR_TXOIR_RESET 0x0 +/* Extracts the ALT_SPIS_RISR_TXOIR field value from a register. */ +#define ALT_SPIS_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIS_RISR_TXOIR register field value suitable for setting the register. */ +#define ALT_SPIS_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Receive FIFO Underflow Raw Interrupt Status - rxuir + * + * The interrupt is active or inactive prior to masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------------------------- + * ALT_SPIS_RISR_RXUIR_E_INACT | 0x0 | spi_rxu_intr interrupt is not active prior to + * : | | masking + * ALT_SPIS_RISR_RXUIR_E_ACT | 0x1 | spi_rxu_intr interrupt is active prior to + * : | | masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_RISR_RXUIR + * + * spi_rxu_intr interrupt is not active prior to masking + */ +#define ALT_SPIS_RISR_RXUIR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_RISR_RXUIR + * + * spi_rxu_intr interrupt is active prior to masking + */ +#define ALT_SPIS_RISR_RXUIR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXUIR register field. */ +#define ALT_SPIS_RISR_RXUIR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXUIR register field. */ +#define ALT_SPIS_RISR_RXUIR_MSB 2 +/* The width in bits of the ALT_SPIS_RISR_RXUIR register field. */ +#define ALT_SPIS_RISR_RXUIR_WIDTH 1 +/* The mask used to set the ALT_SPIS_RISR_RXUIR register field value. */ +#define ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SPIS_RISR_RXUIR register field value. */ +#define ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SPIS_RISR_RXUIR register field. */ +#define ALT_SPIS_RISR_RXUIR_RESET 0x0 +/* Extracts the ALT_SPIS_RISR_RXUIR field value from a register. */ +#define ALT_SPIS_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SPIS_RISR_RXUIR register field value suitable for setting the register. */ +#define ALT_SPIS_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Overflow Raw Interrupt Status - rxoir + * + * The interrupt is active or inactive prior to masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------------------------------- + * ALT_SPIS_RISR_RXOIR_E_INACT | 0x0 | spi_rxo_intr interrupt is not active prior to + * : | | masking + * ALT_SPIS_RISR_RXOIR_E_ACT | 0x1 | spi_rxo_intr interrupt is active prior masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_RISR_RXOIR + * + * spi_rxo_intr interrupt is not active prior to masking + */ +#define ALT_SPIS_RISR_RXOIR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_RISR_RXOIR + * + * spi_rxo_intr interrupt is active prior masking + */ +#define ALT_SPIS_RISR_RXOIR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXOIR register field. */ +#define ALT_SPIS_RISR_RXOIR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXOIR register field. */ +#define ALT_SPIS_RISR_RXOIR_MSB 3 +/* The width in bits of the ALT_SPIS_RISR_RXOIR register field. */ +#define ALT_SPIS_RISR_RXOIR_WIDTH 1 +/* The mask used to set the ALT_SPIS_RISR_RXOIR register field value. */ +#define ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SPIS_RISR_RXOIR register field value. */ +#define ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SPIS_RISR_RXOIR register field. */ +#define ALT_SPIS_RISR_RXOIR_RESET 0x0 +/* Extracts the ALT_SPIS_RISR_RXOIR field value from a register. */ +#define ALT_SPIS_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SPIS_RISR_RXOIR register field value suitable for setting the register. */ +#define ALT_SPIS_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full Raw Interrupt Status - rxfir + * + * The interrupt is active or inactive prior to masking. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------------------------- + * ALT_SPIS_RISR_RXFIR_E_INACT | 0x0 | spi_rxf_intr interrupt is not active prior to + * : | | masking + * ALT_SPIS_RISR_RXFIR_E_ACT | 0x1 | spi_rxf_intr interrupt is active prior to + * : | | masking + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_RISR_RXFIR + * + * spi_rxf_intr interrupt is not active prior to masking + */ +#define ALT_SPIS_RISR_RXFIR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_SPIS_RISR_RXFIR + * + * spi_rxf_intr interrupt is active prior to masking + */ +#define ALT_SPIS_RISR_RXFIR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXFIR register field. */ +#define ALT_SPIS_RISR_RXFIR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXFIR register field. */ +#define ALT_SPIS_RISR_RXFIR_MSB 4 +/* The width in bits of the ALT_SPIS_RISR_RXFIR register field. */ +#define ALT_SPIS_RISR_RXFIR_WIDTH 1 +/* The mask used to set the ALT_SPIS_RISR_RXFIR register field value. */ +#define ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SPIS_RISR_RXFIR register field value. */ +#define ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SPIS_RISR_RXFIR register field. */ +#define ALT_SPIS_RISR_RXFIR_RESET 0x0 +/* Extracts the ALT_SPIS_RISR_RXFIR field value from a register. */ +#define ALT_SPIS_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SPIS_RISR_RXFIR register field value suitable for setting the register. */ +#define ALT_SPIS_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_RISR. + */ +struct ALT_SPIS_RISR_s +{ + const uint32_t txeir : 1; /* Transmit FIFO Empty Raw Interrupt Status */ + const uint32_t txoir : 1; /* Transmit FIFO Overflow Raw Interrupt Status */ + const uint32_t rxuir : 1; /* Receive FIFO Underflow Raw Interrupt Status */ + const uint32_t rxoir : 1; /* Receive FIFO Overflow Raw Interrupt Status */ + const uint32_t rxfir : 1; /* Receive FIFO Full Raw Interrupt Status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_RISR. */ +typedef volatile struct ALT_SPIS_RISR_s ALT_SPIS_RISR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_RISR register from the beginning of the component. */ +#define ALT_SPIS_RISR_OFST 0x34 +/* The address of the ALT_SPIS_RISR register. */ +#define ALT_SPIS_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST)) + +/* + * Register : Transmit FIFO Overflow Interrupt Clear Register - txoicr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Clear Transmit FIFO Overflow Interrupt + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Transmit FIFO Overflow Interrupt - txoicr + * + * This register reflects the status of the interrupt. A read from this register + * clears the ssi_txo_intr interrupt; writing has no effect. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_TXOICR_TXOICR register field. */ +#define ALT_SPIS_TXOICR_TXOICR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_TXOICR_TXOICR register field. */ +#define ALT_SPIS_TXOICR_TXOICR_MSB 0 +/* The width in bits of the ALT_SPIS_TXOICR_TXOICR register field. */ +#define ALT_SPIS_TXOICR_TXOICR_WIDTH 1 +/* The mask used to set the ALT_SPIS_TXOICR_TXOICR register field value. */ +#define ALT_SPIS_TXOICR_TXOICR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_TXOICR_TXOICR register field value. */ +#define ALT_SPIS_TXOICR_TXOICR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_TXOICR_TXOICR register field. */ +#define ALT_SPIS_TXOICR_TXOICR_RESET 0x0 +/* Extracts the ALT_SPIS_TXOICR_TXOICR field value from a register. */ +#define ALT_SPIS_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_TXOICR_TXOICR register field value suitable for setting the register. */ +#define ALT_SPIS_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_TXOICR. + */ +struct ALT_SPIS_TXOICR_s +{ + const uint32_t txoicr : 1; /* Clear Transmit FIFO Overflow Interrupt */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_TXOICR. */ +typedef volatile struct ALT_SPIS_TXOICR_s ALT_SPIS_TXOICR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_TXOICR register from the beginning of the component. */ +#define ALT_SPIS_TXOICR_OFST 0x38 +/* The address of the ALT_SPIS_TXOICR register. */ +#define ALT_SPIS_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXOICR_OFST)) + +/* + * Register : Receive FIFO Overflow Interrupt Clear Register - rxoicr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------- + * [0] | R | 0x0 | Clear Receive FIFO Overflow Interrupt + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Receive FIFO Overflow Interrupt - rxoicr + * + * This register reflects the status of the interrupt. A read from this register + * clears the ssi_rxo_intr interrupt; writing has no effect. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_RXOICR_RXOICR register field. */ +#define ALT_SPIS_RXOICR_RXOICR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_RXOICR_RXOICR register field. */ +#define ALT_SPIS_RXOICR_RXOICR_MSB 0 +/* The width in bits of the ALT_SPIS_RXOICR_RXOICR register field. */ +#define ALT_SPIS_RXOICR_RXOICR_WIDTH 1 +/* The mask used to set the ALT_SPIS_RXOICR_RXOICR register field value. */ +#define ALT_SPIS_RXOICR_RXOICR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_RXOICR_RXOICR register field value. */ +#define ALT_SPIS_RXOICR_RXOICR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_RXOICR_RXOICR register field. */ +#define ALT_SPIS_RXOICR_RXOICR_RESET 0x0 +/* Extracts the ALT_SPIS_RXOICR_RXOICR field value from a register. */ +#define ALT_SPIS_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_RXOICR_RXOICR register field value suitable for setting the register. */ +#define ALT_SPIS_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_RXOICR. + */ +struct ALT_SPIS_RXOICR_s +{ + const uint32_t rxoicr : 1; /* Clear Receive FIFO Overflow Interrupt */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_RXOICR. */ +typedef volatile struct ALT_SPIS_RXOICR_s ALT_SPIS_RXOICR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_RXOICR register from the beginning of the component. */ +#define ALT_SPIS_RXOICR_OFST 0x3c +/* The address of the ALT_SPIS_RXOICR register. */ +#define ALT_SPIS_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXOICR_OFST)) + +/* + * Register : Receive FIFO Underflow Interrupt Clear Register - rxuicr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Clear Receive FIFO Underflow Interrupt + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Receive FIFO Underflow Interrupt - rxuicr + * + * This register reflects the status of the interrupt. A read from this register + * clears the ssi_rxu_intr interrupt; writing has no effect. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_RXUICR_RXUICR register field. */ +#define ALT_SPIS_RXUICR_RXUICR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_RXUICR_RXUICR register field. */ +#define ALT_SPIS_RXUICR_RXUICR_MSB 0 +/* The width in bits of the ALT_SPIS_RXUICR_RXUICR register field. */ +#define ALT_SPIS_RXUICR_RXUICR_WIDTH 1 +/* The mask used to set the ALT_SPIS_RXUICR_RXUICR register field value. */ +#define ALT_SPIS_RXUICR_RXUICR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_RXUICR_RXUICR register field value. */ +#define ALT_SPIS_RXUICR_RXUICR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_RXUICR_RXUICR register field. */ +#define ALT_SPIS_RXUICR_RXUICR_RESET 0x0 +/* Extracts the ALT_SPIS_RXUICR_RXUICR field value from a register. */ +#define ALT_SPIS_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_RXUICR_RXUICR register field value suitable for setting the register. */ +#define ALT_SPIS_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_RXUICR. + */ +struct ALT_SPIS_RXUICR_s +{ + const uint32_t rxuicr : 1; /* Clear Receive FIFO Underflow Interrupt */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_RXUICR. */ +typedef volatile struct ALT_SPIS_RXUICR_s ALT_SPIS_RXUICR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_RXUICR register from the beginning of the component. */ +#define ALT_SPIS_RXUICR_OFST 0x40 +/* The address of the ALT_SPIS_RXUICR register. */ +#define ALT_SPIS_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXUICR_OFST)) + +/* + * Register : Interrupt Clear Register - icr + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | R | 0x0 | Clear Interrupts + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Clear Interrupts - icr + * + * This register is set if any of the interrupts below are active. A read clears + * the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts. + * Writing to this register has no effect. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_ICR_ICR register field. */ +#define ALT_SPIS_ICR_ICR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_ICR_ICR register field. */ +#define ALT_SPIS_ICR_ICR_MSB 0 +/* The width in bits of the ALT_SPIS_ICR_ICR register field. */ +#define ALT_SPIS_ICR_ICR_WIDTH 1 +/* The mask used to set the ALT_SPIS_ICR_ICR register field value. */ +#define ALT_SPIS_ICR_ICR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_ICR_ICR register field value. */ +#define ALT_SPIS_ICR_ICR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_ICR_ICR register field. */ +#define ALT_SPIS_ICR_ICR_RESET 0x0 +/* Extracts the ALT_SPIS_ICR_ICR field value from a register. */ +#define ALT_SPIS_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_ICR_ICR register field value suitable for setting the register. */ +#define ALT_SPIS_ICR_ICR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_ICR. + */ +struct ALT_SPIS_ICR_s +{ + const uint32_t icr : 1; /* Clear Interrupts */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_ICR. */ +typedef volatile struct ALT_SPIS_ICR_s ALT_SPIS_ICR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_ICR register from the beginning of the component. */ +#define ALT_SPIS_ICR_OFST 0x48 +/* The address of the ALT_SPIS_ICR register. */ +#define ALT_SPIS_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ICR_OFST)) + +/* + * Register : DMA Control Register - dmacr + * + * The register is used to enable the DMA Controller interface operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [0] | RW | 0x0 | Receive DMA Enable + * [1] | RW | 0x0 | Transmit DMA Enable + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive DMA Enable - rdmae + * + * This bit enables/disables the receive FIFO DMA channel + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------- + * ALT_SPIS_DMACR_RDMAE_E_DISD | 0x0 | Receive DMA disabled + * ALT_SPIS_DMACR_RDMAE_E_END | 0x1 | Receive DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_DMACR_RDMAE + * + * Receive DMA disabled + */ +#define ALT_SPIS_DMACR_RDMAE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SPIS_DMACR_RDMAE + * + * Receive DMA enabled + */ +#define ALT_SPIS_DMACR_RDMAE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_DMACR_RDMAE register field. */ +#define ALT_SPIS_DMACR_RDMAE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_DMACR_RDMAE register field. */ +#define ALT_SPIS_DMACR_RDMAE_MSB 0 +/* The width in bits of the ALT_SPIS_DMACR_RDMAE register field. */ +#define ALT_SPIS_DMACR_RDMAE_WIDTH 1 +/* The mask used to set the ALT_SPIS_DMACR_RDMAE register field value. */ +#define ALT_SPIS_DMACR_RDMAE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SPIS_DMACR_RDMAE register field value. */ +#define ALT_SPIS_DMACR_RDMAE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SPIS_DMACR_RDMAE register field. */ +#define ALT_SPIS_DMACR_RDMAE_RESET 0x0 +/* Extracts the ALT_SPIS_DMACR_RDMAE field value from a register. */ +#define ALT_SPIS_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SPIS_DMACR_RDMAE register field value suitable for setting the register. */ +#define ALT_SPIS_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Transmit DMA Enable - tdmae + * + * This bit enables/disables the transmit FIFO DMA channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------- + * ALT_SPIS_DMACR_TDMAE_E_DISD | 0x0 | Transmit DMA disabled + * ALT_SPIS_DMACR_TDMAE_E_END | 0x1 | Transmit DMA enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SPIS_DMACR_TDMAE + * + * Transmit DMA disabled + */ +#define ALT_SPIS_DMACR_TDMAE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SPIS_DMACR_TDMAE + * + * Transmit DMA enabled + */ +#define ALT_SPIS_DMACR_TDMAE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SPIS_DMACR_TDMAE register field. */ +#define ALT_SPIS_DMACR_TDMAE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_DMACR_TDMAE register field. */ +#define ALT_SPIS_DMACR_TDMAE_MSB 1 +/* The width in bits of the ALT_SPIS_DMACR_TDMAE register field. */ +#define ALT_SPIS_DMACR_TDMAE_WIDTH 1 +/* The mask used to set the ALT_SPIS_DMACR_TDMAE register field value. */ +#define ALT_SPIS_DMACR_TDMAE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SPIS_DMACR_TDMAE register field value. */ +#define ALT_SPIS_DMACR_TDMAE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SPIS_DMACR_TDMAE register field. */ +#define ALT_SPIS_DMACR_TDMAE_RESET 0x0 +/* Extracts the ALT_SPIS_DMACR_TDMAE field value from a register. */ +#define ALT_SPIS_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SPIS_DMACR_TDMAE register field value suitable for setting the register. */ +#define ALT_SPIS_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_DMACR. + */ +struct ALT_SPIS_DMACR_s +{ + uint32_t rdmae : 1; /* Receive DMA Enable */ + uint32_t tdmae : 1; /* Transmit DMA Enable */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_DMACR. */ +typedef volatile struct ALT_SPIS_DMACR_s ALT_SPIS_DMACR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_DMACR register from the beginning of the component. */ +#define ALT_SPIS_DMACR_OFST 0x4c +/* The address of the ALT_SPIS_DMACR register. */ +#define ALT_SPIS_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMACR_OFST)) + +/* + * Register : DMA Transmit Data Level Regoster - dmatdlr + * + * Controls DMA Transmit FIFO Threshold + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [7:0] | RW | 0x0 | Transmit Data Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit Data Level - dmatdl + * + * This bit field controls the level at which a DMA request is made by the transmit + * logic. It is equal to the watermark level; that is, the dma_tx_req signal is + * generated when the number of valid data entries in the transmit FIFO is equal to + * or below this field value, and TDMAE = 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_DMATDLR_DMATDL register field. */ +#define ALT_SPIS_DMATDLR_DMATDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_DMATDLR_DMATDL register field. */ +#define ALT_SPIS_DMATDLR_DMATDL_MSB 7 +/* The width in bits of the ALT_SPIS_DMATDLR_DMATDL register field. */ +#define ALT_SPIS_DMATDLR_DMATDL_WIDTH 8 +/* The mask used to set the ALT_SPIS_DMATDLR_DMATDL register field value. */ +#define ALT_SPIS_DMATDLR_DMATDL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SPIS_DMATDLR_DMATDL register field value. */ +#define ALT_SPIS_DMATDLR_DMATDL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SPIS_DMATDLR_DMATDL register field. */ +#define ALT_SPIS_DMATDLR_DMATDL_RESET 0x0 +/* Extracts the ALT_SPIS_DMATDLR_DMATDL field value from a register. */ +#define ALT_SPIS_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SPIS_DMATDLR_DMATDL register field value suitable for setting the register. */ +#define ALT_SPIS_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_DMATDLR. + */ +struct ALT_SPIS_DMATDLR_s +{ + uint32_t dmatdl : 8; /* Transmit Data Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_DMATDLR. */ +typedef volatile struct ALT_SPIS_DMATDLR_s ALT_SPIS_DMATDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_DMATDLR register from the beginning of the component. */ +#define ALT_SPIS_DMATDLR_OFST 0x50 +/* The address of the ALT_SPIS_DMATDLR register. */ +#define ALT_SPIS_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMATDLR_OFST)) + +/* + * Register : DMA Receive Data Level Register - dmardlr + * + * Controls DMA Receive FIFO Threshold + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [7:0] | RW | 0x0 | Receive Data Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive Data Level - dmardl + * + * This bit field controls the level at which a DMA request is made by the receive + * logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the + * number of valid data entries in the receive FIFO is equal to or above this field + * value + 1, and RDMAE=1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_DMARDLR_DMARDL register field. */ +#define ALT_SPIS_DMARDLR_DMARDL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_DMARDLR_DMARDL register field. */ +#define ALT_SPIS_DMARDLR_DMARDL_MSB 7 +/* The width in bits of the ALT_SPIS_DMARDLR_DMARDL register field. */ +#define ALT_SPIS_DMARDLR_DMARDL_WIDTH 8 +/* The mask used to set the ALT_SPIS_DMARDLR_DMARDL register field value. */ +#define ALT_SPIS_DMARDLR_DMARDL_SET_MSK 0x000000ff +/* The mask used to clear the ALT_SPIS_DMARDLR_DMARDL register field value. */ +#define ALT_SPIS_DMARDLR_DMARDL_CLR_MSK 0xffffff00 +/* The reset value of the ALT_SPIS_DMARDLR_DMARDL register field. */ +#define ALT_SPIS_DMARDLR_DMARDL_RESET 0x0 +/* Extracts the ALT_SPIS_DMARDLR_DMARDL field value from a register. */ +#define ALT_SPIS_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_SPIS_DMARDLR_DMARDL register field value suitable for setting the register. */ +#define ALT_SPIS_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_DMARDLR. + */ +struct ALT_SPIS_DMARDLR_s +{ + uint32_t dmardl : 8; /* Receive Data Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_DMARDLR. */ +typedef volatile struct ALT_SPIS_DMARDLR_s ALT_SPIS_DMARDLR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_DMARDLR register from the beginning of the component. */ +#define ALT_SPIS_DMARDLR_OFST 0x54 +/* The address of the ALT_SPIS_DMARDLR register. */ +#define ALT_SPIS_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMARDLR_OFST)) + +/* + * Register : Identification Register - idr + * + * This register stores a peripheral identification code + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:----------|:-------------------- + * [31:0] | R | 0x5510005 | Identification Code + * + */ +/* + * Field : Identification Code - idr + * + * This filed contains the peripherals identification code, 0x05510005. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_IDR_IDR register field. */ +#define ALT_SPIS_IDR_IDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_IDR_IDR register field. */ +#define ALT_SPIS_IDR_IDR_MSB 31 +/* The width in bits of the ALT_SPIS_IDR_IDR register field. */ +#define ALT_SPIS_IDR_IDR_WIDTH 32 +/* The mask used to set the ALT_SPIS_IDR_IDR register field value. */ +#define ALT_SPIS_IDR_IDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SPIS_IDR_IDR register field value. */ +#define ALT_SPIS_IDR_IDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_SPIS_IDR_IDR register field. */ +#define ALT_SPIS_IDR_IDR_RESET 0x5510005 +/* Extracts the ALT_SPIS_IDR_IDR field value from a register. */ +#define ALT_SPIS_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SPIS_IDR_IDR register field value suitable for setting the register. */ +#define ALT_SPIS_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_IDR. + */ +struct ALT_SPIS_IDR_s +{ + const uint32_t idr : 32; /* Identification Code */ +}; + +/* The typedef declaration for register ALT_SPIS_IDR. */ +typedef volatile struct ALT_SPIS_IDR_s ALT_SPIS_IDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_IDR register from the beginning of the component. */ +#define ALT_SPIS_IDR_OFST 0x58 +/* The address of the ALT_SPIS_IDR register. */ +#define ALT_SPIS_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IDR_OFST)) + +/* + * Register : Component Version Register - spi_version_id + * + * This read-only register stores the specific SPI Slave component version. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------------ + * [31:0] | RW | 0x3332302a | Component Version + * + */ +/* + * Field : Component Version - spi_version_id + * + * Contains the hex representation of the Synopsys component version. Consists of + * ASCII value for each number in the version. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */ +#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */ +#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_MSB 31 +/* The width in bits of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */ +#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_WIDTH 32 +/* The mask used to set the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field value. */ +#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field value. */ +#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000 +/* The reset value of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */ +#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_RESET 0x3332302a +/* Extracts the ALT_SPIS_SPI_VER_ID_SPI_VER_ID field value from a register. */ +#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field value suitable for setting the register. */ +#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_SPI_VER_ID. + */ +struct ALT_SPIS_SPI_VER_ID_s +{ + uint32_t spi_version_id : 32; /* Component Version */ +}; + +/* The typedef declaration for register ALT_SPIS_SPI_VER_ID. */ +typedef volatile struct ALT_SPIS_SPI_VER_ID_s ALT_SPIS_SPI_VER_ID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_SPI_VER_ID register from the beginning of the component. */ +#define ALT_SPIS_SPI_VER_ID_OFST 0x5c +/* The address of the ALT_SPIS_SPI_VER_ID register. */ +#define ALT_SPIS_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPI_VER_ID_OFST)) + +/* + * Register : Data Register - dr + * + * The data register is a 16-bit read/write buffer for the transmit/receive FIFOs. + * When the register is read, data in the receive FIFO buffer is accessed. When it + * is written to, data are moved into the transmit FIFO buffer; a write can occur + * only when SPI_EN = 1. FIFOs are reset when SPI_EN = 0. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [15:0] | RW | 0x0 | Data + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data - dr + * + * When writing to this register, you must right-justify the data. Read data are + * automatically right-justified. + * + * Read = Receive FIFO buffer + * + * Write = Transmit FIFO buffer + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SPIS_DR_DR register field. */ +#define ALT_SPIS_DR_DR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SPIS_DR_DR register field. */ +#define ALT_SPIS_DR_DR_MSB 15 +/* The width in bits of the ALT_SPIS_DR_DR register field. */ +#define ALT_SPIS_DR_DR_WIDTH 16 +/* The mask used to set the ALT_SPIS_DR_DR register field value. */ +#define ALT_SPIS_DR_DR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SPIS_DR_DR register field value. */ +#define ALT_SPIS_DR_DR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SPIS_DR_DR register field. */ +#define ALT_SPIS_DR_DR_RESET 0x0 +/* Extracts the ALT_SPIS_DR_DR field value from a register. */ +#define ALT_SPIS_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SPIS_DR_DR register field value suitable for setting the register. */ +#define ALT_SPIS_DR_DR_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SPIS_DR. + */ +struct ALT_SPIS_DR_s +{ + uint32_t dr : 16; /* Data */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SPIS_DR. */ +typedef volatile struct ALT_SPIS_DR_s ALT_SPIS_DR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SPIS_DR register from the beginning of the component. */ +#define ALT_SPIS_DR_OFST 0x60 +/* The address of the ALT_SPIS_DR register. */ +#define ALT_SPIS_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SPIS. + */ +struct ALT_SPIS_s +{ + volatile ALT_SPIS_CTLR0_t ctrlr0; /* ALT_SPIS_CTLR0 */ + volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */ + volatile ALT_SPIS_SPIENR_t spienr; /* ALT_SPIS_SPIENR */ + volatile ALT_SPIS_MWCR_t mwcr; /* ALT_SPIS_MWCR */ + volatile uint32_t _pad_0x10_0x17[2]; /* *UNDEFINED* */ + volatile ALT_SPIS_TXFTLR_t txftlr; /* ALT_SPIS_TXFTLR */ + volatile ALT_SPIS_RXFTLR_t rxftlr; /* ALT_SPIS_RXFTLR */ + volatile ALT_SPIS_TXFLR_t txflr; /* ALT_SPIS_TXFLR */ + volatile ALT_SPIS_RXFLR_t rxflr; /* ALT_SPIS_RXFLR */ + volatile ALT_SPIS_SR_t sr; /* ALT_SPIS_SR */ + volatile ALT_SPIS_IMR_t imr; /* ALT_SPIS_IMR */ + volatile ALT_SPIS_ISR_t isr; /* ALT_SPIS_ISR */ + volatile ALT_SPIS_RISR_t risr; /* ALT_SPIS_RISR */ + volatile ALT_SPIS_TXOICR_t txoicr; /* ALT_SPIS_TXOICR */ + volatile ALT_SPIS_RXOICR_t rxoicr; /* ALT_SPIS_RXOICR */ + volatile ALT_SPIS_RXUICR_t rxuicr; /* ALT_SPIS_RXUICR */ + volatile uint32_t _pad_0x44_0x47; /* *UNDEFINED* */ + volatile ALT_SPIS_ICR_t icr; /* ALT_SPIS_ICR */ + volatile ALT_SPIS_DMACR_t dmacr; /* ALT_SPIS_DMACR */ + volatile ALT_SPIS_DMATDLR_t dmatdlr; /* ALT_SPIS_DMATDLR */ + volatile ALT_SPIS_DMARDLR_t dmardlr; /* ALT_SPIS_DMARDLR */ + volatile ALT_SPIS_IDR_t idr; /* ALT_SPIS_IDR */ + volatile ALT_SPIS_SPI_VER_ID_t spi_version_id; /* ALT_SPIS_SPI_VER_ID */ + volatile ALT_SPIS_DR_t dr; /* ALT_SPIS_DR */ + volatile uint32_t _pad_0x64_0x80[7]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SPIS. */ +typedef volatile struct ALT_SPIS_s ALT_SPIS_t; +/* The struct declaration for the raw register contents of register group ALT_SPIS. */ +struct ALT_SPIS_raw_s +{ + volatile uint32_t ctrlr0; /* ALT_SPIS_CTLR0 */ + volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */ + volatile uint32_t spienr; /* ALT_SPIS_SPIENR */ + volatile uint32_t mwcr; /* ALT_SPIS_MWCR */ + volatile uint32_t _pad_0x10_0x17[2]; /* *UNDEFINED* */ + volatile uint32_t txftlr; /* ALT_SPIS_TXFTLR */ + volatile uint32_t rxftlr; /* ALT_SPIS_RXFTLR */ + volatile uint32_t txflr; /* ALT_SPIS_TXFLR */ + volatile uint32_t rxflr; /* ALT_SPIS_RXFLR */ + volatile uint32_t sr; /* ALT_SPIS_SR */ + volatile uint32_t imr; /* ALT_SPIS_IMR */ + volatile uint32_t isr; /* ALT_SPIS_ISR */ + volatile uint32_t risr; /* ALT_SPIS_RISR */ + volatile uint32_t txoicr; /* ALT_SPIS_TXOICR */ + volatile uint32_t rxoicr; /* ALT_SPIS_RXOICR */ + volatile uint32_t rxuicr; /* ALT_SPIS_RXUICR */ + volatile uint32_t _pad_0x44_0x47; /* *UNDEFINED* */ + volatile uint32_t icr; /* ALT_SPIS_ICR */ + volatile uint32_t dmacr; /* ALT_SPIS_DMACR */ + volatile uint32_t dmatdlr; /* ALT_SPIS_DMATDLR */ + volatile uint32_t dmardlr; /* ALT_SPIS_DMARDLR */ + volatile uint32_t idr; /* ALT_SPIS_IDR */ + volatile uint32_t spi_version_id; /* ALT_SPIS_SPI_VER_ID */ + volatile uint32_t dr; /* ALT_SPIS_DR */ + volatile uint32_t _pad_0x64_0x80[7]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SPIS. */ +typedef volatile struct ALT_SPIS_raw_s ALT_SPIS_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_SPIS_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_stm.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_stm.h new file mode 100644 index 000000000..46ed892f8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_stm.h @@ -0,0 +1,144 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_STM */ + +#ifndef __ALTERA_ALT_STM_H__ +#define __ALTERA_ALT_STM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : STM Module Address Space - ALT_STM + * STM Module Address Space + * + * Address space allocated to the STM. For detailed information about the use of + * this address space, [url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm + * .doc.ddi0444b/index.html]click here[/url] to access the ARM documentation for + * the CoreSight STM-101. + * + */ +/* + * Register : Empty - reg + * + * Placeholder + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | Empty + * + */ +/* + * Field : Empty - fld + * + * Placeholder + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_STM_REG_FLD register field. */ +#define ALT_STM_REG_FLD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_STM_REG_FLD register field. */ +#define ALT_STM_REG_FLD_MSB 31 +/* The width in bits of the ALT_STM_REG_FLD register field. */ +#define ALT_STM_REG_FLD_WIDTH 32 +/* The mask used to set the ALT_STM_REG_FLD register field value. */ +#define ALT_STM_REG_FLD_SET_MSK 0xffffffff +/* The mask used to clear the ALT_STM_REG_FLD register field value. */ +#define ALT_STM_REG_FLD_CLR_MSK 0x00000000 +/* The reset value of the ALT_STM_REG_FLD register field is UNKNOWN. */ +#define ALT_STM_REG_FLD_RESET 0x0 +/* Extracts the ALT_STM_REG_FLD field value from a register. */ +#define ALT_STM_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_STM_REG_FLD register field value suitable for setting the register. */ +#define ALT_STM_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_STM_REG. + */ +struct ALT_STM_REG_s +{ + uint32_t fld : 32; /* Empty */ +}; + +/* The typedef declaration for register ALT_STM_REG. */ +typedef volatile struct ALT_STM_REG_s ALT_STM_REG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_STM_REG register from the beginning of the component. */ +#define ALT_STM_REG_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_STM. + */ +struct ALT_STM_s +{ + volatile ALT_STM_REG_t reg; /* ALT_STM_REG */ +}; + +/* The typedef declaration for register group ALT_STM. */ +typedef volatile struct ALT_STM_s ALT_STM_t; +/* The struct declaration for the raw register contents of register group ALT_STM. */ +struct ALT_STM_raw_s +{ + volatile uint32_t reg; /* ALT_STM_REG */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_STM. */ +typedef volatile struct ALT_STM_raw_s ALT_STM_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_STM_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sysmgr.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sysmgr.h new file mode 100644 index 000000000..7733cdd22 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sysmgr.h @@ -0,0 +1,24810 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_SYSMGR */ + +#ifndef __ALTERA_ALT_SYSMGR_H__ +#define __ALTERA_ALT_SYSMGR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : System Manager Module - ALT_SYSMGR + * System Manager Module + * + * Registers in the System Manager module + * + */ +/* + * Register : Silicon ID1 Register - siliconid1 + * + * Specifies Silicon ID and revision number. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------- + * [15:0] | R | 0x1 | Silicon Revision + * [31:16] | R | 0x0 | Silicon ID + * + */ +/* + * Field : Silicon Revision - rev + * + * Silicon revision number. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_SYSMGR_SILICONID1_REV_E_REV1 | 0x1 | Revision 1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SILICONID1_REV + * + * Revision 1 + */ +#define ALT_SYSMGR_SILICONID1_REV_E_REV1 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_MSB 15 +/* The width in bits of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_SILICONID1_REV register field value. */ +#define ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_SILICONID1_REV register field value. */ +#define ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_SILICONID1_REV register field. */ +#define ALT_SYSMGR_SILICONID1_REV_RESET 0x1 +/* Extracts the ALT_SYSMGR_SILICONID1_REV field value from a register. */ +#define ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_SILICONID1_REV register field value suitable for setting the register. */ +#define ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Silicon ID - id + * + * Silicon ID + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV | 0x0 | HPS in Cyclone V and Arria V SoC FPGA devices + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SILICONID1_ID + * + * HPS in Cyclone V and Arria V SoC FPGA devices + */ +#define ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_MSB 31 +/* The width in bits of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_SILICONID1_ID register field value. */ +#define ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_SYSMGR_SILICONID1_ID register field value. */ +#define ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff +/* The reset value of the ALT_SYSMGR_SILICONID1_ID register field. */ +#define ALT_SYSMGR_SILICONID1_ID_RESET 0x0 +/* Extracts the ALT_SYSMGR_SILICONID1_ID field value from a register. */ +#define ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_SYSMGR_SILICONID1_ID register field value suitable for setting the register. */ +#define ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SILICONID1. + */ +struct ALT_SYSMGR_SILICONID1_s +{ + const uint32_t rev : 16; /* Silicon Revision */ + const uint32_t id : 16; /* Silicon ID */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SILICONID1. */ +typedef volatile struct ALT_SYSMGR_SILICONID1_s ALT_SYSMGR_SILICONID1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SILICONID1 register from the beginning of the component. */ +#define ALT_SYSMGR_SILICONID1_OFST 0x0 + +/* + * Register : Silicon ID2 Register - siliconid2 + * + * Reserved for future use. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | R | 0x0 | Reserved + * + */ +/* + * Field : Reserved - rsv + * + * Reserved for future use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_MSB 31 +/* The width in bits of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_SILICONID2_RSV register field value. */ +#define ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_SILICONID2_RSV register field value. */ +#define ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_SILICONID2_RSV register field. */ +#define ALT_SYSMGR_SILICONID2_RSV_RESET 0x0 +/* Extracts the ALT_SYSMGR_SILICONID2_RSV field value from a register. */ +#define ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_SILICONID2_RSV register field value suitable for setting the register. */ +#define ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SILICONID2. + */ +struct ALT_SYSMGR_SILICONID2_s +{ + const uint32_t rsv : 32; /* Reserved */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SILICONID2. */ +typedef volatile struct ALT_SYSMGR_SILICONID2_s ALT_SYSMGR_SILICONID2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SILICONID2 register from the beginning of the component. */ +#define ALT_SYSMGR_SILICONID2_OFST 0x4 + +/* + * Register : L4 Watchdog Debug Register - wddbg + * + * Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These + * control registers are used to drive the pause input signal of the L4 watchdogs. + * Note that the watchdogs built into the MPU automatically are paused when their + * associated CPU enters debug mode. Only reset by a cold reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [1:0] | RW | 0x3 | Debug Mode + * [3:2] | RW | 0x3 | Debug Mode + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Debug Mode - mode_0 + * + * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index + * matches L4 watchdog index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of + * : | | CPUs + * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in + * : | | debug mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Continue normal operation ignoring debug mode of CPUs + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Pause normal operation only if CPU0 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Pause normal operation only if CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 + * + * Pause normal operation if CPU0 or CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_MSB 1 +/* The width in bits of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_WDDBG_MOD_0 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_0 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3 +/* Extracts the ALT_SYSMGR_WDDBG_MOD_0 field value from a register. */ +#define ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_WDDBG_MOD_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Debug Mode - mode_1 + * + * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index + * matches L4 watchdog index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of + * : | | CPUs + * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug + * : | | mode + * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in + * : | | debug mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Continue normal operation ignoring debug mode of CPUs + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Pause normal operation only if CPU0 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Pause normal operation only if CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 + * + * Pause normal operation if CPU0 or CPU1 is in debug mode + */ +#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_WDDBG_MOD_1 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c +/* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_1 register field value. */ +#define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ +#define ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3 +/* Extracts the ALT_SYSMGR_WDDBG_MOD_1 field value from a register. */ +#define ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_SYSMGR_WDDBG_MOD_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_WDDBG. + */ +struct ALT_SYSMGR_WDDBG_s +{ + uint32_t mode_0 : 2; /* Debug Mode */ + uint32_t mode_1 : 2; /* Debug Mode */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_WDDBG. */ +typedef volatile struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_WDDBG register from the beginning of the component. */ +#define ALT_SYSMGR_WDDBG_OFST 0x10 + +/* + * Register : Boot Info Register - bootinfo + * + * Provides access to boot configuration information. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:--------|:--------------------- + * [2:0] | R | Unknown | Boot Select + * [4:3] | R | Unknown | Clock Select + * [7:5] | R | Unknown | HPS Pin Boot Select + * [9:8] | R | Unknown | HPS Pin Clock Select + * [31:10] | ??? | Unknown | *UNDEFINED* + * + */ +/* + * Field : Boot Select - bsel + * + * The boot select field specifies the boot source. It is read by the Boot ROM code + * on a cold or warm reset to determine the boot source. + * + * The HPS BSEL pins value are sampled upon deassertion of cold reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------------|:------|:----------------------------------- + * ALT_SYSMGR_BOOT_BSEL_E_RSVD | 0x0 | Reserved + * ALT_SYSMGR_BOOT_BSEL_E_FPGA | 0x1 | FPGA (HPS2FPGA Bridge) + * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V | 0x2 | NAND Flash (1.8v) + * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V | 0x3 | NAND Flash (3.0v) + * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 | SD/MMC External Transceiver (1.8v) + * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 | SD/MMC Internal Transceiver (3.0v) + * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V | 0x6 | QSPI Flash (1.8v) + * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V | 0x7 | QSPI Flash (3.0v) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * Reserved + */ +#define ALT_SYSMGR_BOOT_BSEL_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * FPGA (HPS2FPGA Bridge) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * NAND Flash (1.8v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * NAND Flash (3.0v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * SD/MMC External Transceiver (1.8v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * SD/MMC Internal Transceiver (3.0v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * QSPI Flash (1.8v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL + * + * QSPI Flash (3.0v) + */ +#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */ +#define ALT_SYSMGR_BOOT_BSEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */ +#define ALT_SYSMGR_BOOT_BSEL_MSB 2 +/* The width in bits of the ALT_SYSMGR_BOOT_BSEL register field. */ +#define ALT_SYSMGR_BOOT_BSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_BOOT_BSEL register field value. */ +#define ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00000007 +/* The mask used to clear the ALT_SYSMGR_BOOT_BSEL register field value. */ +#define ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_SYSMGR_BOOT_BSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_BSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_BSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_SYSMGR_BOOT_BSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : Clock Select - csel + * + * The clock select field specifies clock information for booting. The clock select + * encoding is a function of the CSEL value. The clock select field is read by the + * Boot ROM code on a cold or warm reset when booting from a flash device to get + * information about how to setup the HPS clocking to boot from the specified clock + * device. + * + * The encoding of the clock select field is specified by the enum associated with + * this field. + * + * The HPS CSEL pins value are sampled upon deassertion of cold reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:------------------------------------------------ + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 | 0x0 | QSPI device clock is osc1_clk divided by 4, + * : | | SD/MMC device clock is osc1_clk divided by 4, + * : | | NAND device operation is osc1_clk divided by 25 + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 | 0x1 | QSPI device clock is osc1_clk divided by 2, + * : | | SD/MMC device clock is osc1_clk divided by 1, + * : | | NAND device operation is osc1_clk multiplied by + * : | | 20/25 + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 | 0x2 | QSPI device clock is osc1_clk divided by 1, + * : | | SD/MMC device clock is osc1_clk divided by 2, + * : | | NAND device operation is osc1_clk multiplied by + * : | | 10/25 + * ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 | 0x3 | QSPI device clock is osc1_clk multiplied by 2, + * : | | SD/MMC device clock is osc1_clk divided by 4, + * : | | NAND device operation is osc1_clk multiplied by + * : | | 5/25 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk divided by 4, SD/MMC device clock is osc1_clk + * divided by 4, NAND device operation is osc1_clk divided by 25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk divided by 2, SD/MMC device clock is osc1_clk + * divided by 1, NAND device operation is osc1_clk multiplied by 20/25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk divided by 1, SD/MMC device clock is osc1_clk + * divided by 2, NAND device operation is osc1_clk multiplied by 10/25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL + * + * QSPI device clock is osc1_clk multiplied by 2, SD/MMC device clock is osc1_clk + * divided by 4, NAND device operation is osc1_clk multiplied by 5/25 + */ +#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */ +#define ALT_SYSMGR_BOOT_CSEL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */ +#define ALT_SYSMGR_BOOT_CSEL_MSB 4 +/* The width in bits of the ALT_SYSMGR_BOOT_CSEL register field. */ +#define ALT_SYSMGR_BOOT_CSEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_BOOT_CSEL register field value. */ +#define ALT_SYSMGR_BOOT_CSEL_SET_MSK 0x00000018 +/* The mask used to clear the ALT_SYSMGR_BOOT_CSEL register field value. */ +#define ALT_SYSMGR_BOOT_CSEL_CLR_MSK 0xffffffe7 +/* The reset value of the ALT_SYSMGR_BOOT_CSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_CSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_CSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_CSEL_GET(value) (((value) & 0x00000018) >> 3) +/* Produces a ALT_SYSMGR_BOOT_CSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_CSEL_SET(value) (((value) << 3) & 0x00000018) + +/* + * Field : HPS Pin Boot Select - pinbsel + * + * Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are + * sampled upon deassertion of cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */ +#define ALT_SYSMGR_BOOT_PINBSEL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */ +#define ALT_SYSMGR_BOOT_PINBSEL_MSB 7 +/* The width in bits of the ALT_SYSMGR_BOOT_PINBSEL register field. */ +#define ALT_SYSMGR_BOOT_PINBSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_BOOT_PINBSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINBSEL_SET_MSK 0x000000e0 +/* The mask used to clear the ALT_SYSMGR_BOOT_PINBSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINBSEL_CLR_MSK 0xffffff1f +/* The reset value of the ALT_SYSMGR_BOOT_PINBSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_PINBSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_PINBSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_PINBSEL_GET(value) (((value) & 0x000000e0) >> 5) +/* Produces a ALT_SYSMGR_BOOT_PINBSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_PINBSEL_SET(value) (((value) << 5) & 0x000000e0) + +/* + * Field : HPS Pin Clock Select - pincsel + * + * Specifies the sampled value of the HPS CSEL pins. The value of HPS CSEL pins are + * sampled upon deassertion of cold reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */ +#define ALT_SYSMGR_BOOT_PINCSEL_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */ +#define ALT_SYSMGR_BOOT_PINCSEL_MSB 9 +/* The width in bits of the ALT_SYSMGR_BOOT_PINCSEL register field. */ +#define ALT_SYSMGR_BOOT_PINCSEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_BOOT_PINCSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINCSEL_SET_MSK 0x00000300 +/* The mask used to clear the ALT_SYSMGR_BOOT_PINCSEL register field value. */ +#define ALT_SYSMGR_BOOT_PINCSEL_CLR_MSK 0xfffffcff +/* The reset value of the ALT_SYSMGR_BOOT_PINCSEL register field is UNKNOWN. */ +#define ALT_SYSMGR_BOOT_PINCSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_BOOT_PINCSEL field value from a register. */ +#define ALT_SYSMGR_BOOT_PINCSEL_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_SYSMGR_BOOT_PINCSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_BOOT_PINCSEL_SET(value) (((value) << 8) & 0x00000300) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_BOOT. + */ +struct ALT_SYSMGR_BOOT_s +{ + const uint32_t bsel : 3; /* Boot Select */ + const uint32_t csel : 2; /* Clock Select */ + const uint32_t pinbsel : 3; /* HPS Pin Boot Select */ + const uint32_t pincsel : 2; /* HPS Pin Clock Select */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_BOOT. */ +typedef volatile struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_BOOT register from the beginning of the component. */ +#define ALT_SYSMGR_BOOT_OFST 0x14 + +/* + * Register : HPS Info Register - hpsinfo + * + * Provides information about the HPS capabilities. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [0] | R | Unknown | Dual Core + * [1] | R | Unknown | CAN + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Dual Core - dualcore + * + * Indicates if CPU1 is available in MPU or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE | 0x0 | Not dual-core (only CPU0 available). + * ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE | 0x1 | Is dual-core (CPU0 and CPU1 both available). + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE + * + * Not dual-core (only CPU0 available). + */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE + * + * Is dual-core (CPU0 and CPU1 both available). + */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_MSB 0 +/* The width in bits of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_HPSINFO_DUALCORE register field is UNKNOWN. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_RESET 0x0 +/* Extracts the ALT_SYSMGR_HPSINFO_DUALCORE field value from a register. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_HPSINFO_DUALCORE register field value suitable for setting the register. */ +#define ALT_SYSMGR_HPSINFO_DUALCORE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CAN - can + * + * Indicates if CAN0 and CAN1 controllers are available or not. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------- + * ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE | 0x0 | CAN0 and CAN1 are not available. + * ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE | 0x1 | CAN0 and CAN1 are available. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN + * + * CAN0 and CAN1 are not available. + */ +#define ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN + * + * CAN0 and CAN1 are available. + */ +#define ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */ +#define ALT_SYSMGR_HPSINFO_CAN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */ +#define ALT_SYSMGR_HPSINFO_CAN_MSB 1 +/* The width in bits of the ALT_SYSMGR_HPSINFO_CAN register field. */ +#define ALT_SYSMGR_HPSINFO_CAN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_HPSINFO_CAN register field value. */ +#define ALT_SYSMGR_HPSINFO_CAN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_HPSINFO_CAN register field value. */ +#define ALT_SYSMGR_HPSINFO_CAN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_HPSINFO_CAN register field is UNKNOWN. */ +#define ALT_SYSMGR_HPSINFO_CAN_RESET 0x0 +/* Extracts the ALT_SYSMGR_HPSINFO_CAN field value from a register. */ +#define ALT_SYSMGR_HPSINFO_CAN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_HPSINFO_CAN register field value suitable for setting the register. */ +#define ALT_SYSMGR_HPSINFO_CAN_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_HPSINFO. + */ +struct ALT_SYSMGR_HPSINFO_s +{ + const uint32_t dualcore : 1; /* Dual Core */ + const uint32_t can : 1; /* CAN */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_HPSINFO. */ +typedef volatile struct ALT_SYSMGR_HPSINFO_s ALT_SYSMGR_HPSINFO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_HPSINFO register from the beginning of the component. */ +#define ALT_SYSMGR_HPSINFO_OFST 0x18 + +/* + * Register : Parity Fail Injection Register - parityinj + * + * Inject parity failures into the parity-protected RAMs in the MPU. Allows + * software to test the parity failure interrupt handler. The field array index + * corresponds to the CPU index. + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------------------- + * [0] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM + * [1] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM + * [2] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM + * [3] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM + * [4] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM + * [5] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM + * [6] | RW | 0x0 | Parity Fail Injection for Main TLB RAM + * [7] | RW | 0x0 | Parity Fail Injection for Main TLB RAM + * [8] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM + * [9] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM + * [10] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM + * [11] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM + * [12] | RW | 0x0 | Parity Fail Injection for GHB RAM + * [13] | RW | 0x0 | Parity Fail Injection for GHB RAM + * [14] | RW | 0x0 | Parity Fail Injection for BTAC RAM + * [15] | RW | 0x0 | Parity Fail Injection for BTAC RAM + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_0 + * + * If 1, injecting parity error to Data Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_1 + * + * If 1, injecting parity error to Data Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_MSB 1 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_0 + * + * If 1, injecting parity error to Data Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_1 + * + * If 1, injecting parity error to Data Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_0 + * + * If 1, injecting parity error to Data Cache Outer RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_MSB 4 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_1 + * + * If 1, injecting parity error to Data Cache Outer RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_MSB 5 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Parity Fail Injection for Main TLB RAM - maintlb_0 + * + * If 1, injecting parity error to Main TLB RAM.The field array index corresponds + * to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_MSB 6 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Parity Fail Injection for Main TLB RAM - maintlb_1 + * + * If 1, injecting parity error to Main TLB RAM.The field array index corresponds + * to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_MSB 7 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_0 + * + * If 1, injecting parity error to Instruction Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_MSB 8 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_1 + * + * If 1, injecting parity error to Instruction Cache Data RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_MSB 9 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_0 + * + * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_MSB 10 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_1 + * + * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index + * corresponds to the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_MSB 11 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Parity Fail Injection for GHB RAM - ghb_0 + * + * If 1, injecting parity error to GHB RAM.The field array index corresponds to the + * CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_MSB 12 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_CLR_MSK 0xffffefff +/* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_GHB_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SYSMGR_PARITYINJ_GHB_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_0_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Parity Fail Injection for GHB RAM - ghb_1 + * + * If 1, injecting parity error to GHB RAM.The field array index corresponds to the + * CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_MSB 13 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_SET_MSK 0x00002000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_CLR_MSK 0xffffdfff +/* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_GHB_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_SYSMGR_PARITYINJ_GHB_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_GHB_1_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Parity Fail Injection for BTAC RAM - btac_0 + * + * If 1, injecting parity error to BTAC RAM.The field array index corresponds to + * the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_MSB 14 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_SET_MSK 0x00004000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_CLR_MSK 0xffffbfff +/* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_0 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_SYSMGR_PARITYINJ_BTAC_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_0_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Parity Fail Injection for BTAC RAM - btac_1 + * + * If 1, injecting parity error to BTAC RAM.The field array index corresponds to + * the CPU index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_MSB 15 +/* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_SET_MSK 0x00008000 +/* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_CLR_MSK 0xffff7fff +/* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_1 field value from a register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_SYSMGR_PARITYINJ_BTAC_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_PARITYINJ_BTAC_1_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PARITYINJ. + */ +struct ALT_SYSMGR_PARITYINJ_s +{ + uint32_t dcdata_0 : 1; /* Parity Fail Injection for Data Cache Data RAM */ + uint32_t dcdata_1 : 1; /* Parity Fail Injection for Data Cache Data RAM */ + uint32_t dctag_0 : 1; /* Parity Fail Injection for Data Cache Tag RAM */ + uint32_t dctag_1 : 1; /* Parity Fail Injection for Data Cache Tag RAM */ + uint32_t dcouter_0 : 1; /* Parity Fail Injection for Data Cache Outer RAM */ + uint32_t dcouter_1 : 1; /* Parity Fail Injection for Data Cache Outer RAM */ + uint32_t maintlb_0 : 1; /* Parity Fail Injection for Main TLB RAM */ + uint32_t maintlb_1 : 1; /* Parity Fail Injection for Main TLB RAM */ + uint32_t icdata_0 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */ + uint32_t icdata_1 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */ + uint32_t ictag_0 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */ + uint32_t ictag_1 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */ + uint32_t ghb_0 : 1; /* Parity Fail Injection for GHB RAM */ + uint32_t ghb_1 : 1; /* Parity Fail Injection for GHB RAM */ + uint32_t btac_0 : 1; /* Parity Fail Injection for BTAC RAM */ + uint32_t btac_1 : 1; /* Parity Fail Injection for BTAC RAM */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PARITYINJ. */ +typedef volatile struct ALT_SYSMGR_PARITYINJ_s ALT_SYSMGR_PARITYINJ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PARITYINJ register from the beginning of the component. */ +#define ALT_SYSMGR_PARITYINJ_OFST 0x1c + +/* + * Register Group : FPGA Interface Group - ALT_SYSMGR_FPGAINTF + * FPGA Interface Group + * + * Registers used to enable/disable interfaces between the FPGA and HPS. Required + * for either of the following situations:[list][*]Interfaces that cannot be + * disabled by putting an HPS module associated with the interface into + * reset.[*]HPS modules that accept signals from the FPGA fabric and those signals + * might interfere with the normal operation of the module.[/list]. + * + * All registers are only reset by a cold reset (ignore warm reset). + * + */ +/* + * Register : Global Disable Register - gbl + * + * Used to disable all interfaces between the FPGA and HPS. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x1 | Global Interface + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Global Interface - intf + * + * Used to disable all interfaces between the FPGA and HPS. Software must ensure + * that all interfaces between the FPGA and HPS are inactive before disabling them. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS | 0x0 | All interfaces between FPGA and HPS are + * : | | disabled. + * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN | 0x1 | Interfaces between FPGA and HPS are not all + * : | | disabled. Interfaces can be indivdually disabled + * : | | by putting the HPS module associated with the + * : | | interface in reset using registers in the Reset + * : | | Manager or by using registers in this register + * : | | group of the System Manager for interfaces + * : | | without an associated module. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF + * + * All interfaces between FPGA and HPS are disabled. + */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF + * + * Interfaces between FPGA and HPS are not all disabled. Interfaces can be + * indivdually disabled by putting the HPS module associated with the interface in + * reset using registers in the Reset Manager or by using registers in this + * register group of the System Manager for interfaces without an associated + * module. + */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_MSB 0 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_GBL_INTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FPGAINTF_GBL_INTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FPGAINTF_GBL. + */ +struct ALT_SYSMGR_FPGAINTF_GBL_s +{ + uint32_t intf : 1; /* Global Interface */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_GBL. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_GBL_s ALT_SYSMGR_FPGAINTF_GBL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FPGAINTF_GBL register from the beginning of the component. */ +#define ALT_SYSMGR_FPGAINTF_GBL_OFST 0x0 + +/* + * Register : Individual Disable Register - indiv + * + * Used to disable individual interfaces between the FPGA and HPS. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | RW | 0x1 | Reset Request Interface + * [1] | RW | 0x1 | JTAG Enable Interface + * [2] | RW | 0x1 | CONFIG_IO Interface + * [3] | RW | 0x1 | Boundary-Scan Interface + * [4] | RW | 0x1 | Trace Interface + * [5] | ??? | 0x1 | *UNDEFINED* + * [6] | RW | 0x1 | STM Event Interface + * [7] | RW | 0x1 | Cross Trigger Interface (CTI) + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Reset Request Interface - rstreqintf + * + * Used to disable the reset request interface. This interface allows logic in the + * FPGA fabric to request HPS resets. This field disables the following reset + * request signals from the FPGA fabric to HPS:[list][*]f2h_cold_rst_req_n - + * Triggers a cold reset of the HPS[*]f2h_warm_rst_req_n - Triggers a warm reset of + * the HPS[*]f2h_dbg_rst_req_n - Triggers a debug reset of the HPS[/list] + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS | 0x0 | Reset request interface is disabled. Logic in + * : | | the FPGA fabric cannot reset the HPS. + * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN | 0x1 | Reset request interface is enabled. Logic in the + * : | | FPGA fabric can reset the HPS. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF + * + * Reset request interface is disabled. Logic in the FPGA fabric cannot reset the + * HPS. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF + * + * Reset request interface is enabled. Logic in the FPGA fabric can reset the HPS. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_MSB 0 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : JTAG Enable Interface - jtagenintf + * + * Used to disable the JTAG enable interface. This interface allows logic in the + * FPGA fabric to disable the HPS JTAG operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------ + * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS | 0x0 | JTAG enable interface is disabled. Logic in the + * : | | FPGA fabric cannot disable the HPS JTAG. + * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN | 0x1 | JTAG enable interface is enabled. Logic in the + * : | | FPGA fabric can disable the HPS JTAG. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF + * + * JTAG enable interface is disabled. Logic in the FPGA fabric cannot disable the + * HPS JTAG. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF + * + * JTAG enable interface is enabled. Logic in the FPGA fabric can disable the HPS + * JTAG. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_MSB 1 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : CONFIG_IO Interface - configiointf + * + * Used to disable the CONFIG_IO interface. This interface allows the FPGA JTAG TAP + * controller to execute the CONFIG_IO instruction and configure all device I/Os + * (FPGA and HPS). This is typically done before executing boundary-scan + * instructions. The CONFIG_IO interface must be enabled before attempting to send + * the CONFIG_IO instruction to the FPGA JTAG TAP controller. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS | 0x0 | CONFIG_IO interface is disabled. Execution of + * : | | the CONFIG_IO instruction in the FPGA JTAG TAP + * : | | controller is unsupported and produces undefined + * : | | results. + * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN | 0x1 | CONFIG_IO interface is enabled. Execution of the + * : | | CONFIG_IO instruction in the FPGA JTAG TAP + * : | | controller is supported. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF + * + * CONFIG_IO interface is disabled. Execution of the CONFIG_IO instruction in the + * FPGA JTAG TAP controller is unsupported and produces undefined results. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF + * + * CONFIG_IO interface is enabled. Execution of the CONFIG_IO instruction in the + * FPGA JTAG TAP controller is supported. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_MSB 2 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Boundary-Scan Interface - bscanintf + * + * Used to disable the boundary-scan interface. This interface allows the FPGA JTAG + * TAP controller to execute boundary-scan instructions such as SAMPLE/PRELOAD, + * EXTEST, and HIGHZ. The boundary-scan interface must be enabled before attempting + * to send the boundary-scan instructions to the FPGA JTAG TAP controller. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS | 0x0 | Boundary-scan interface is disabled. Execution + * : | | of boundary-scan instructions in the FPGA JTAG + * : | | TAP controller is unsupported and produces + * : | | undefined results. + * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN | 0x1 | Boundary-scan interface is enabled. Execution of + * : | | the boundary-scan instructions in the FPGA JTAG + * : | | TAP controller is supported. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF + * + * Boundary-scan interface is disabled. Execution of boundary-scan instructions in + * the FPGA JTAG TAP controller is unsupported and produces undefined results. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF + * + * Boundary-scan interface is enabled. Execution of the boundary-scan instructions + * in the FPGA JTAG TAP controller is supported. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_MSB 3 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Trace Interface - traceintf + * + * Used to disable the trace interface. This interface allows the HPS debug logic + * to send trace data to logic in the FPGA fabric. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS | 0x0 | Trace interface is disabled. HPS debug logic + * : | | cannot send trace data to the FPGA fabric. + * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN | 0x1 | Trace interface is enabled. Other registers in + * : | | the HPS debug logic must be programmmed to + * : | | actually send trace data to the FPGA fabric. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF + * + * Trace interface is disabled. HPS debug logic cannot send trace data to the FPGA + * fabric. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF + * + * Trace interface is enabled. Other registers in the HPS debug logic must be + * programmmed to actually send trace data to the FPGA fabric. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_MSB 4 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : STM Event Interface - stmeventintf + * + * Used to disable the STM event interface. This interface allows logic in the FPGA + * fabric to trigger events to the STM debug module in the HPS. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS | 0x0 | STM event interface is disabled. Logic in the + * : | | FPGA fabric cannot trigger STM events. + * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN | 0x1 | STM event interface is enabled. Logic in the + * : | | FPGA fabric can trigger STM events. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF + * + * STM event interface is disabled. Logic in the FPGA fabric cannot trigger STM + * events. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF + * + * STM event interface is enabled. Logic in the FPGA fabric can trigger STM + * events. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_MSB 6 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Cross Trigger Interface (CTI) - crosstrigintf + * + * Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note + * that this doesn't prevent the HPS debug logic from sending triggers to the FPGA + * Fabric. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:---------------------------------- + * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS | 0x0 | FPGA Fabric cannot send triggers. + * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN | 0x1 | FPGA Fabric can send triggers. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF + * + * FPGA Fabric cannot send triggers. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF + * + * FPGA Fabric can send triggers. + */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_MSB 7 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_RESET 0x1 +/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FPGAINTF_INDIV. + */ +struct ALT_SYSMGR_FPGAINTF_INDIV_s +{ + uint32_t rstreqintf : 1; /* Reset Request Interface */ + uint32_t jtagenintf : 1; /* JTAG Enable Interface */ + uint32_t configiointf : 1; /* CONFIG_IO Interface */ + uint32_t bscanintf : 1; /* Boundary-Scan Interface */ + uint32_t traceintf : 1; /* Trace Interface */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t stmeventintf : 1; /* STM Event Interface */ + uint32_t crosstrigintf : 1; /* Cross Trigger Interface (CTI) */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_INDIV. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_INDIV_s ALT_SYSMGR_FPGAINTF_INDIV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FPGAINTF_INDIV register from the beginning of the component. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_OFST 0x4 + +/* + * Register : Module Disable Register - module + * + * Used to disable signals from the FPGA fabric to individual HPS modules. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [1:0] | ??? | 0x0 | *UNDEFINED* + * [2] | RW | 0x0 | EMAC Module + * [3] | RW | 0x0 | EMAC Module + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC Module - emac_0 + * + * Used to disable signals from the FPGA fabric to the EMAC modules that could + * potentially interfere with their normal operation. + * + * The array index corresponds to the EMAC module instance. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation + * : | | of the EMAC module. + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN | 0x1 | Signals from FPGA fabric can potentially affect + * : | | operation of the EMAC module. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 + * + * Signals from FPGA fabric cannot affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 + * + * Signals from FPGA fabric can potentially affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : EMAC Module - emac_1 + * + * Used to disable signals from the FPGA fabric to the EMAC modules that could + * potentially interfere with their normal operation. + * + * The array index corresponds to the EMAC module instance. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation + * : | | of the EMAC module. + * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN | 0x1 | Signals from FPGA fabric can potentially affect + * : | | operation of the EMAC module. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 + * + * Signals from FPGA fabric cannot affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 + * + * Signals from FPGA fabric can potentially affect operation of the EMAC module. + */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 field value from a register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FPGAINTF_MODULE. + */ +struct ALT_SYSMGR_FPGAINTF_MODULE_s +{ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t emac_0 : 1; /* EMAC Module */ + uint32_t emac_1 : 1; /* EMAC Module */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_MODULE. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_MODULE_s ALT_SYSMGR_FPGAINTF_MODULE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FPGAINTF_MODULE register from the beginning of the component. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_OFST 0x8 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_FPGAINTF. + */ +struct ALT_SYSMGR_FPGAINTF_s +{ + volatile ALT_SYSMGR_FPGAINTF_GBL_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */ + volatile ALT_SYSMGR_FPGAINTF_INDIV_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */ + volatile ALT_SYSMGR_FPGAINTF_MODULE_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */ + volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_FPGAINTF. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_s ALT_SYSMGR_FPGAINTF_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */ +struct ALT_SYSMGR_FPGAINTF_raw_s +{ + volatile uint32_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */ + volatile uint32_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */ + volatile uint32_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */ + volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */ +typedef volatile struct ALT_SYSMGR_FPGAINTF_raw_s ALT_SYSMGR_FPGAINTF_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Scan Manager Group - ALT_SYSMGR_SCANMGR + * Scan Manager Group + * + * Registers related to the Scan Manager that aren't located inside the Scan + * Manager itself. + * + */ +/* + * Register : Scan Manager Control Register - ctrl + * + * Controls behaviors of Scan Manager not controlled by registers in the Scan + * Manager itself. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | FPGA JTAG Enable + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FPGA JTAG Enable - fpgajtagen + * + * Controls whether FPGA JTAG pins or Scan Manager drives JTAG signals to the FPGA. + * + * Only reset by a cold reset (ignores warm reset). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------ + * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS | 0x0 | FPGA JTAG pins drive JTAG signals to FPGA + * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR | 0x1 | Scan Manager drives JTAG signals to FPGA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN + * + * FPGA JTAG pins drive JTAG signals to FPGA + */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN + * + * Scan Manager drives JTAG signals to FPGA + */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_MSB 0 +/* The width in bits of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_RESET 0x0 +/* Extracts the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN field value from a register. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value suitable for setting the register. */ +#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SCANMGR_CTL. + */ +struct ALT_SYSMGR_SCANMGR_CTL_s +{ + uint32_t fpgajtagen : 1; /* FPGA JTAG Enable */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SCANMGR_CTL. */ +typedef volatile struct ALT_SYSMGR_SCANMGR_CTL_s ALT_SYSMGR_SCANMGR_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SCANMGR_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_SCANMGR_CTL_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_SCANMGR. + */ +struct ALT_SYSMGR_SCANMGR_s +{ + volatile ALT_SYSMGR_SCANMGR_CTL_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_SCANMGR. */ +typedef volatile struct ALT_SYSMGR_SCANMGR_s ALT_SYSMGR_SCANMGR_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */ +struct ALT_SYSMGR_SCANMGR_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */ +typedef volatile struct ALT_SYSMGR_SCANMGR_raw_s ALT_SYSMGR_SCANMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Freeze Control Group - ALT_SYSMGR_FRZCTL + * Freeze Control Group + * + * Registers used to generate HPS IO freeze signals. + * + * All registers are only reset by a cold reset (ignore warm reset). + * + */ +/* + * Register : VIO Control Register - vioctrl + * + * Used to drive freeze signals to HPS VIO banks. + * + * The register array index corresponds to the freeze channel. + * + * Freeze channel 0 provides freeze signals to VIO bank 0 and 1. + * + * Freeze channel 1 provides freeze signals to VIO bank 2 and 3. Only drives freeze + * signals when SRC.VIO1 is set to SW. + * + * Freeze channel 2 provides freeze signals to VIO bank 4. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * The following equation determines when the weak pullup resistor is enabled: + * + * enabled = ~wkpullup | (CFF & cfg & tristate) + * + * where CFF is the value of weak pullup as set by IO configuration + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------- + * [0] | RW | 0x0 | IO Configuration + * [1] | RW | 0x0 | IO Bus Hold + * [2] | RW | 0x0 | IO Tri-State + * [3] | RW | 0x0 | IO Weak Pullup + * [4] | RW | 0x0 | IO Slew-rate + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IO Configuration - cfg + * + * Controls IO configuration + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe + * : | | value). + * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously + * : | | configured by software using the Scan Manager. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG + * + * Disable IO configuration (forced to a safe value). + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG + * + * Enables IO configuration as previously configured by software using the Scan + * Manager. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_CFG field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IO Bus Hold - bushold + * + * Controls bus hold circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit. + * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD + * + * Disable bus hold circuit. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD + * + * Bus hold circuit controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_MSB 1 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IO Tri-State - tristate + * + * Controls IO tri-state + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled. + * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE + * + * IO tri-state enabled. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE + * + * IO tri-state controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_MSB 2 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IO Weak Pullup - wkpullup + * + * Controls weak pullup resistor + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled. + * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO + * : | | configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP + * + * Weak pullup resistor enabled. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP + * + * Weak pullup resistor enable controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_MSB 3 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IO Slew-rate - slew + * + * Controls IO slew-rate + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------ + * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow. + * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW + * + * Slew-rate forced to slow. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW + * + * Slew-rate controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_MSB 4 +/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW field value from a register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_VIOCTL. + */ +struct ALT_SYSMGR_FRZCTL_VIOCTL_s +{ + uint32_t cfg : 1; /* IO Configuration */ + uint32_t bushold : 1; /* IO Bus Hold */ + uint32_t tristate : 1; /* IO Tri-State */ + uint32_t wkpullup : 1; /* IO Weak Pullup */ + uint32_t slew : 1; /* IO Slew-rate */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_VIOCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_VIOCTL_s ALT_SYSMGR_FRZCTL_VIOCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_VIOCTL register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_OFST 0x0 + +/* + * Register : HIO Control Register - hioctrl + * + * Used to drive freeze signals to HPS HIO bank (DDR SDRAM). + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * The following equation determines when the weak pullup resistor is enabled: + * + * enabled = ~wkpullup | (CFF & cfg & tristate) + * + * where CFF is the value of weak pullup as set by IO configuration + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------------- + * [0] | RW | 0x0 | IO Configuration + * [1] | RW | 0x0 | IO Bus Hold + * [2] | RW | 0x0 | IO Tri-State + * [3] | RW | 0x0 | IO Weak Pullup + * [4] | RW | 0x0 | IO Slew-rate + * [5] | RW | 0x1 | DLL Reset + * [6] | RW | 0x1 | OCT Reset + * [7] | RW | 0x1 | IO and DQS Reset + * [8] | RW | 0x0 | OCT Calibration and Configuration Enable + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IO Configuration - cfg + * + * Controls IO configuration + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe + * : | | value). + * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously + * : | | configured by software using the Scan Manager. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG + * + * Disable IO configuration (forced to a safe value). + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG + * + * Enables IO configuration as previously configured by software using the Scan + * Manager. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_CFG field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IO Bus Hold - bushold + * + * Controls bus hold circuit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit. + * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD + * + * Disable bus hold circuit. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD + * + * Bus hold circuit controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_MSB 1 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IO Tri-State - tristate + * + * Controls IO tri-state + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled. + * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE + * + * IO tri-state enabled. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE + * + * IO tri-state controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_MSB 2 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IO Weak Pullup - wkpullup + * + * Controls weak pullup resistor + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled. + * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO + * : | | configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP + * + * Weak pullup resistor enabled. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP + * + * Weak pullup resistor enable controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_MSB 3 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IO Slew-rate - slew + * + * Controls IO slew-rate + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------ + * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow. + * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW + * + * Slew-rate forced to slow. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW + * + * Slew-rate controlled by IO configuration. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_MSB 4 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : DLL Reset - dllrst + * + * Controls DLL (Delay-Locked Loop) reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS | 0x0 | No reset or clock gating. + * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN | 0x1 | Resets registers in the DLL and gates off DLL + * : | | clock. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST + * + * No reset or clock gating. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST + * + * Resets registers in the DLL and gates off DLL clock. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_MSB 5 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : OCT Reset - octrst + * + * Controls OCT reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS | 0x0 | No reset. + * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN | 0x1 | Resets registers in the OCT. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST + * + * No reset. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST + * + * Resets registers in the OCT. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_MSB 6 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IO and DQS Reset - regrst + * + * Controls IO and DQS reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS | 0x0 | No reset. + * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN | 0x1 | Resets all IO registers and DQS registers. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST + * + * No reset. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST + * + * Resets all IO registers and DQS registers. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_MSB 7 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : OCT Calibration and Configuration Enable - oct_cfgen_calstart + * + * Controls OCT calibration and OCT IO configuration enable. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS | 0x0 | Disables IO configuration (forced to a safe + * : | | value) in OCT calibration block. + * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN | 0x1 | Starts OCT calibration state machine and enables + * : | | IO configuration in OCT calibration block. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART + * + * Disables IO configuration (forced to a safe value) in OCT calibration block. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART + * + * Starts OCT calibration state machine and enables IO configuration in OCT + * calibration block. + */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_MSB 8 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_HIOCTL. + */ +struct ALT_SYSMGR_FRZCTL_HIOCTL_s +{ + uint32_t cfg : 1; /* IO Configuration */ + uint32_t bushold : 1; /* IO Bus Hold */ + uint32_t tristate : 1; /* IO Tri-State */ + uint32_t wkpullup : 1; /* IO Weak Pullup */ + uint32_t slew : 1; /* IO Slew-rate */ + uint32_t dllrst : 1; /* DLL Reset */ + uint32_t octrst : 1; /* OCT Reset */ + uint32_t regrst : 1; /* IO and DQS Reset */ + uint32_t oct_cfgen_calstart : 1; /* OCT Calibration and Configuration Enable */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_HIOCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_HIOCTL_s ALT_SYSMGR_FRZCTL_HIOCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_HIOCTL register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_OFST 0x10 + +/* + * Register : Source Register - src + * + * Contains register field to choose between software state machine (vioctrl array + * index [1] register) or hardware state machine in the Freeze Controller as the + * freeze signal source for VIO channel 1. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [0] | RW | 0x0 | VIO1 Freeze Signal Source + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : VIO1 Freeze Signal Source - vio1 + * + * The freeze signal source for VIO channel 1 (VIO bank 2 and bank 3). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW | 0x0 | VIO1 freeze signals are driven by software + * : | | writing to the VIOCTRL[1] register. The + * : | | VIO1-related fields in the hwctrl register are + * : | | active but don't effect the VIO1 freeze signals. + * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW | 0x1 | VIO1 freeze signals are driven by the hardware + * : | | state machine in the Freeze Controller. The + * : | | VIO1-related fields in the hwctrl register are + * : | | active and effect the VIO1 freeze signals. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1 + * + * VIO1 freeze signals are driven by software writing to the VIOCTRL[1] register. + * The VIO1-related fields in the hwctrl register are active but don't effect the + * VIO1 freeze signals. + */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1 + * + * VIO1 freeze signals are driven by the hardware state machine in the Freeze + * Controller. The VIO1-related fields in the hwctrl register are active and effect + * the VIO1 freeze signals. + */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_RESET 0x0 +/* Extracts the ALT_SYSMGR_FRZCTL_SRC_VIO1 field value from a register. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_SRC. + */ +struct ALT_SYSMGR_FRZCTL_SRC_s +{ + uint32_t vio1 : 1; /* VIO1 Freeze Signal Source */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_SRC. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_SRC_s ALT_SYSMGR_FRZCTL_SRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_SRC register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_SRC_OFST 0x14 + +/* + * Register : Hardware Control Register - hwctrl + * + * Activate freeze or thaw operations on VIO channel 1 (HPS IO bank 2 and bank 3) + * and monitor for completeness and the current state. + * + * These fields interact with the hardware state machine in the Freeze Controller. + * These fields can be accessed independent of the value of SRC1.VIO1 although they + * only have an effect on the VIO channel 1 freeze signals when SRC1.VIO1 is setup + * to have the hardware state machine be the freeze signal source. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [0] | RW | 0x1 | VIO channel 1 Freeze/Thaw request + * [2:1] | R | 0x2 | VIO channel 1 State + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : VIO channel 1 Freeze/Thaw request - vio1req + * + * Requests hardware state machine to generate freeze signal sequence to transition + * between frozen and thawed states. + * + * If this field is read by software, it contains the value previously written by + * software (i.e. this field is not written by hardware). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------------- + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW | 0x0 | Requests a thaw (unfreeze) operation. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ | 0x1 | Requests a freeze operation. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ + * + * Requests a thaw (unfreeze) operation. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ + * + * Requests a freeze operation. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_MSB 0 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_RESET 0x1 +/* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : VIO channel 1 State - vio1state + * + * Software reads this field to determine the current frozen/thawed state of the + * VIO channel 1 or to determine when a freeze/thaw request is made by writing the + * corresponding *REQ field in this register has completed. + * + * Reset by a cold reset (ignores warm reset). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN | 0x0 | Transitioning from thawed state to frozen state. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED | 0x1 | Thawed state. I/Os behave as configured. I/Os + * : | | must be configured by the Scan Manager before + * : | | entering this state. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN | 0x2 | Frozen state. I/O configuration is ignored. + * : | | Instead, I/Os are in tri-state mode with a weak + * : | | pull-up. Scan Manager can be used to configure + * : | | the I/Os while they are frozen. + * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED | 0x3 | Transitioning from frozen state to thawed state. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Transitioning from thawed state to frozen state. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Thawed state. I/Os behave as configured. I/Os must be configured by the Scan + * Manager before entering this state. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Frozen state. I/O configuration is ignored. Instead, I/Os are in tri-state mode + * with a weak pull-up. Scan Manager can be used to configure the I/Os while they + * are frozen. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE + * + * Transitioning from frozen state to thawed state. + */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_MSB 2 +/* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET_MSK 0x00000006 +/* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_RESET 0x2 +/* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE field value from a register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET(value) (((value) << 1) & 0x00000006) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_FRZCTL_HWCTL. + */ +struct ALT_SYSMGR_FRZCTL_HWCTL_s +{ + uint32_t vio1req : 1; /* VIO channel 1 Freeze/Thaw request */ + const uint32_t vio1state : 2; /* VIO channel 1 State */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_FRZCTL_HWCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_HWCTL_s ALT_SYSMGR_FRZCTL_HWCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_FRZCTL_HWCTL register from the beginning of the component. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_OFST 0x18 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_FRZCTL. + */ +struct ALT_SYSMGR_FRZCTL_s +{ + volatile ALT_SYSMGR_FRZCTL_VIOCTL_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_SYSMGR_FRZCTL_HIOCTL_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */ + volatile ALT_SYSMGR_FRZCTL_SRC_t src; /* ALT_SYSMGR_FRZCTL_SRC */ + volatile ALT_SYSMGR_FRZCTL_HWCTL_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */ + volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_FRZCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_s ALT_SYSMGR_FRZCTL_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */ +struct ALT_SYSMGR_FRZCTL_raw_s +{ + volatile uint32_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */ + volatile uint32_t src; /* ALT_SYSMGR_FRZCTL_SRC */ + volatile uint32_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */ + volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */ +typedef volatile struct ALT_SYSMGR_FRZCTL_raw_s ALT_SYSMGR_FRZCTL_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : EMAC Group - ALT_SYSMGR_EMAC + * EMAC Group + * + * External control registers for the EMACs + * + */ +/* + * Register : Control Register - ctrl + * + * Registers used by the EMACs. All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [1:0] | RW | 0x2 | PHY Interface Select + * [3:2] | RW | 0x2 | PHY Interface Select + * [4] | RW | 0x0 | PTP Clock Select + * [5] | RW | 0x0 | PTP Clock Select + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : PHY Interface Select - physel_0 + * + * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC + * module when it exits from reset. The associated enum defines the allowed values. + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------ + * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII | 0x0 | Select GMII/MII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII | 0x1 | Select RGMII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII | 0x2 | Select RMII PHY interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 + * + * Select GMII/MII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 + * + * Select RGMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 + * + * Select RMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_MSB 1 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_RESET 0x2 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : PHY Interface Select - physel_1 + * + * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC + * module when it exits from reset. The associated enum defines the allowed values. + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------ + * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII | 0x0 | Select GMII/MII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII | 0x1 | Select RGMII PHY interface + * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII | 0x2 | Select RMII PHY interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 + * + * Select GMII/MII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 + * + * Select RGMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 + * + * Select RMII PHY interface + */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET_MSK 0x0000000c +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_CLR_MSK 0xfffffff3 +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_RESET 0x2 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_GET(value) (((value) & 0x0000000c) >> 2) +/* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET(value) (((value) << 2) & 0x0000000c) + +/* + * Field : PTP Clock Select - ptpclksel_0 + * + * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC + * module when it exits from reset. The field array index corresponds to the EMAC + * index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------------- + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK | 0x0 | Selects osc1_clk + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 + * + * Selects osc1_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 + * + * Selects fpga_ptp_ref_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_MSB 4 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : PTP Clock Select - ptpclksel_1 + * + * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC + * module when it exits from reset. The field array index corresponds to the EMAC + * index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------------------- + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK | 0x0 | Selects osc1_clk + * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 + * + * Selects osc1_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 + * + * Selects fpga_ptp_ref_clk + */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_MSB 5 +/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_EMAC_CTL. + */ +struct ALT_SYSMGR_EMAC_CTL_s +{ + uint32_t physel_0 : 2; /* PHY Interface Select */ + uint32_t physel_1 : 2; /* PHY Interface Select */ + uint32_t ptpclksel_0 : 1; /* PTP Clock Select */ + uint32_t ptpclksel_1 : 1; /* PTP Clock Select */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_EMAC_CTL. */ +typedef volatile struct ALT_SYSMGR_EMAC_CTL_s ALT_SYSMGR_EMAC_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_EMAC_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_EMAC_CTL_OFST 0x0 + +/* + * Register : EMAC L3 Master AxCACHE Register - l3master + * + * Controls the L3 master ARCACHE and AWCACHE AXI signals. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------- + * [3:0] | RW | 0x0 | EMAC ARCACHE + * [7:4] | RW | 0x0 | EMAC ARCACHE + * [11:8] | RW | 0x0 | EMAC AWCACHE + * [15:12] | RW | 0x0 | EMAC AWCACHE + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC ARCACHE - arcache_0 + * + * Specifies the values of the 2 EMAC ARCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_MSB 3 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : EMAC ARCACHE - arcache_1 + * + * Specifies the values of the 2 EMAC ARCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_MSB 7 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK 0xffffff0f +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET(value) (((value) << 4) & 0x000000f0) + +/* + * Field : EMAC AWCACHE - awcache_0 + * + * Specifies the values of the 2 EMAC AWCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_MSB 11 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET_MSK 0x00000f00 +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_CLR_MSK 0xfffff0ff +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_GET(value) (((value) & 0x00000f00) >> 8) +/* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET(value) (((value) << 8) & 0x00000f00) + +/* + * Field : EMAC AWCACHE - awcache_1 + * + * Specifies the values of the 2 EMAC AWCACHE signals. + * + * The field array index corresponds to the EMAC index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Bufferable only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Reserved. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_MSB 15 +/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET_MSK 0x0000f000 +/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK 0xffff0fff +/* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 field value from a register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_GET(value) (((value) & 0x0000f000) >> 12) +/* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET(value) (((value) << 12) & 0x0000f000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_EMAC_L3MST. + */ +struct ALT_SYSMGR_EMAC_L3MST_s +{ + uint32_t arcache_0 : 4; /* EMAC ARCACHE */ + uint32_t arcache_1 : 4; /* EMAC ARCACHE */ + uint32_t awcache_0 : 4; /* EMAC AWCACHE */ + uint32_t awcache_1 : 4; /* EMAC AWCACHE */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_EMAC_L3MST. */ +typedef volatile struct ALT_SYSMGR_EMAC_L3MST_s ALT_SYSMGR_EMAC_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_EMAC_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_EMAC_L3MST_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_EMAC. + */ +struct ALT_SYSMGR_EMAC_s +{ + volatile ALT_SYSMGR_EMAC_CTL_t ctrl; /* ALT_SYSMGR_EMAC_CTL */ + volatile ALT_SYSMGR_EMAC_L3MST_t l3master; /* ALT_SYSMGR_EMAC_L3MST */ + volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_EMAC. */ +typedef volatile struct ALT_SYSMGR_EMAC_s ALT_SYSMGR_EMAC_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */ +struct ALT_SYSMGR_EMAC_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_EMAC_CTL */ + volatile uint32_t l3master; /* ALT_SYSMGR_EMAC_L3MST */ + volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */ +typedef volatile struct ALT_SYSMGR_EMAC_raw_s ALT_SYSMGR_EMAC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : DMA Controller Group - ALT_SYSMGR_DMA + * DMA Controller Group + * + * Registers used by the DMA Controller to enable secured system support and select + * DMA channels. + * + */ +/* + * Register : Control Register - ctrl + * + * Registers used by the DMA Controller. All fields are reset by a cold or warm + * reset. + * + * These register bits should be updated during system initialization prior to + * removing the DMA controller from reset. They may not be changed dynamically + * during DMA operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [0] | RW | 0x0 | Channel Select + * [1] | RW | 0x0 | Channel Select + * [2] | RW | 0x0 | Channel Select + * [3] | RW | 0x0 | Channel Select + * [4] | RW | 0x0 | Manager Thread Security + * [12:5] | RW | 0x0 | IRQ Security + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Channel Select - chansel_0 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_0 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Select - chansel_1 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_MSB 1 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_1 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Channel Select - chansel_2 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_MSB 2 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_2 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Channel Select - chansel_3 + * + * Controls mux that selects whether FPGA or CAN connects to one of the DMA + * peripheral request interfaces.The peripheral request interface index equals the + * array index + 4. For example, array index 0 is for peripheral request index 4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------- + * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA | 0x0 | FPGA drives peripheral request interface + * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN | 0x1 | CAN drives peripheral request interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3 + * + * FPGA drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3 + * + * CAN drives peripheral request interface + */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_MSB 3 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_3 field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Manager Thread Security - mgrnonsecure + * + * Specifies the security state of the DMA manager thread. + * + * 0 = assigns DMA manager to the Secure state. + * + * 1 = assigns DMA manager to the Non-secure state. + * + * Sampled by the DMA controller when it exits from reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_MSB 4 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_MGRNONSECURE field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IRQ Security - irqnonsecure + * + * Specifies the security state of an event-interrupt resource. + * + * If bit index [x] is 0, the DMAC assigns event or irq[x] to the Secure state. + * + * If bit index [x] is 1, the DMAC assigns event or irq[x] to the Non-secure + * state. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_MSB 12 +/* The width in bits of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH 8 +/* The mask used to set the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET_MSK 0x00001fe0 +/* The mask used to clear the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_CLR_MSK 0xffffe01f +/* The reset value of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_CTL_IRQNONSECURE field value from a register. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_GET(value) (((value) & 0x00001fe0) >> 5) +/* Produces a ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET(value) (((value) << 5) & 0x00001fe0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_DMA_CTL. + */ +struct ALT_SYSMGR_DMA_CTL_s +{ + uint32_t chansel_0 : 1; /* Channel Select */ + uint32_t chansel_1 : 1; /* Channel Select */ + uint32_t chansel_2 : 1; /* Channel Select */ + uint32_t chansel_3 : 1; /* Channel Select */ + uint32_t mgrnonsecure : 1; /* Manager Thread Security */ + uint32_t irqnonsecure : 8; /* IRQ Security */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_DMA_CTL. */ +typedef volatile struct ALT_SYSMGR_DMA_CTL_s ALT_SYSMGR_DMA_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_DMA_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_DMA_CTL_OFST 0x0 + +/* + * Register : Peripheral Security Register - persecurity + * + * Controls the security state of a peripheral request interface. Sampled by the + * DMA controller when it exits from reset. + * + * These register bits should be updated during system initialization prior to + * removing the DMA controller from reset. They may not be changed dynamically + * during DMA operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [31:0] | RW | 0x0 | Peripheral Non-Secure + * + */ +/* + * Field : Peripheral Non-Secure - nonsecure + * + * If bit index [x] is 0, the DMA controller assigns peripheral request interface x + * to the Secure state. + * + * If bit index [x] is 1, the DMA controller assigns peripheral request interface x + * to the Non-secure state. + * + * Reset by a cold or warm reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_MSB 31 +/* The width in bits of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_RESET 0x0 +/* Extracts the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE field value from a register. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value suitable for setting the register. */ +#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_DMA_PERSECURITY. + */ +struct ALT_SYSMGR_DMA_PERSECURITY_s +{ + uint32_t nonsecure : 32; /* Peripheral Non-Secure */ +}; + +/* The typedef declaration for register ALT_SYSMGR_DMA_PERSECURITY. */ +typedef volatile struct ALT_SYSMGR_DMA_PERSECURITY_s ALT_SYSMGR_DMA_PERSECURITY_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_DMA_PERSECURITY register from the beginning of the component. */ +#define ALT_SYSMGR_DMA_PERSECURITY_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_DMA. + */ +struct ALT_SYSMGR_DMA_s +{ + volatile ALT_SYSMGR_DMA_CTL_t ctrl; /* ALT_SYSMGR_DMA_CTL */ + volatile ALT_SYSMGR_DMA_PERSECURITY_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_DMA. */ +typedef volatile struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_DMA. */ +struct ALT_SYSMGR_DMA_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_DMA_CTL */ + volatile uint32_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_DMA. */ +typedef volatile struct ALT_SYSMGR_DMA_raw_s ALT_SYSMGR_DMA_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Preloader (initial software) Group - ALT_SYSMGR_ISW + * Preloader (initial software) Group + * + * Registers used by preloader code and the OS. + * + * All registers are only reset by a cold reset (ignore warm reset). + * + */ +/* + * Register : Preloader to OS Handoff Information - handoff + * + * These registers are used to store handoff infomation between the preloader and + * the OS. These 8 registers can be used to store any information. The contents of + * these registers have no impact on the state of the HPS hardware. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [31:0] | RW | 0x0 | Preloader Handoff Information + * + */ +/* + * Field : Preloader Handoff Information - value + * + * Preloader Handoff Information. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ISW_HANDOFF_VALUE field value from a register. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ISW_HANDOFF_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ISW_HANDOFF. + */ +struct ALT_SYSMGR_ISW_HANDOFF_s +{ + uint32_t value : 32; /* Preloader Handoff Information */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ISW_HANDOFF. */ +typedef volatile struct ALT_SYSMGR_ISW_HANDOFF_s ALT_SYSMGR_ISW_HANDOFF_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ISW_HANDOFF register from the beginning of the component. */ +#define ALT_SYSMGR_ISW_HANDOFF_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ISW. + */ +struct ALT_SYSMGR_ISW_s +{ + volatile ALT_SYSMGR_ISW_HANDOFF_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ISW. */ +typedef volatile struct ALT_SYSMGR_ISW_s ALT_SYSMGR_ISW_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ISW. */ +struct ALT_SYSMGR_ISW_raw_s +{ + volatile uint32_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ISW. */ +typedef volatile struct ALT_SYSMGR_ISW_raw_s ALT_SYSMGR_ISW_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Boot ROM Code Register Group - ALT_SYSMGR_ROMCODE + * Boot ROM Code Register Group + * + * Registers used by the Boot ROM code. All fields are only reset by a cold reset + * (ignore warm reset). + * + */ +/* + * Register : Control Register - ctrl + * + * Contains information used to control Boot ROM code. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | Warm Reset Configure Pin Mux for Boot Pins + * [1] | RW | 0x0 | Warm Reset Configure IOs for Boot Pins + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Warm Reset Configure Pin Mux for Boot Pins - warmrstcfgpinmux + * + * Specifies whether the Boot ROM code configures the pin mux for boot pins after a + * warm reset. Note that the Boot ROM code always configures the pin mux for boot + * pins after a cold reset. After the Boot ROM code configures the pin mux for boot + * pins, it always disables this field. It is up to user software to enable this + * field if it wants a different behavior. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD | 0x0 | Boot ROM code will not configure pin mux for + * : | | boot pins after a warm reset + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END | 0x1 | Boot ROM code will configure pin mux for boot + * : | | pins after a warm reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX + * + * Boot ROM code will not configure pin mux for boot pins after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX + * + * Boot ROM code will configure pin mux for boot pins after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0 +/* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX field value from a register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Warm Reset Configure IOs for Boot Pins - warmrstcfgio + * + * Specifies whether the Boot ROM code configures the IOs used by boot after a warm + * reset. Note that the Boot ROM code always configures the IOs used by boot after + * a cold reset. After the Boot ROM code configures the IOs used by boot, it always + * disables this field. It is up to user software to enable this field if it wants + * a different behavior. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------------------- + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD | 0x0 | Boot ROM code will not configure IOs used by + * : | | boot after a warm reset + * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END | 0x1 | Boot ROM code will configure IOs used by boot + * : | | after a warm reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO + * + * Boot ROM code will not configure IOs used by boot after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO + * + * Boot ROM code will configure IOs used by boot after a warm reset + */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_MSB 1 +/* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO field value from a register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_CTL. + */ +struct ALT_SYSMGR_ROMCODE_CTL_s +{ + uint32_t warmrstcfgpinmux : 1; /* Warm Reset Configure Pin Mux for Boot Pins */ + uint32_t warmrstcfgio : 1; /* Warm Reset Configure IOs for Boot Pins */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_CTL. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_CTL_s ALT_SYSMGR_ROMCODE_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_CTL_OFST 0x0 + +/* + * Register : CPU1 Start Address Register - cpu1startaddr + * + * When CPU1 is released from reset and the Boot ROM is located at the CPU1 reset + * exception address (the typical case), the Boot ROM reset handler code reads the + * address stored in this register and jumps it to hand off execution to user + * software. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | Address + * + */ +/* + * Field : Address - value + * + * Address for CPU1 to start executing at after coming out of reset. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR. + */ +struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s +{ + uint32_t value : 32; /* Address */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST 0x4 + +/* + * Register : Preloader (initial software) State Register - initswstate + * + * The preloader software (loaded by the Boot ROM) writes the magic value + * 0x49535756 (ISWV in ASCII) to this register when it has reached a valid state. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | Value + * + */ +/* + * Field : Value - value + * + * Written with magic value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:-----------|:------------ + * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID | 0x0 | + * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID | 0x49535756 | + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE + * + */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE + * + */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE. + */ +struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s +{ + uint32_t value : 32; /* Value */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s ALT_SYSMGR_ROMCODE_INITSWSTATE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWSTATE register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST 0x8 + +/* + * Register : Preloader (initial software) Last Image Loaded Register - initswlastld + * + * Contains the index of the last preloader software image loaded by the Boot ROM + * from the boot device. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [1:0] | RW | 0x0 | Index + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Index - index + * + * Index of last image loaded. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_MSB 1 +/* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX field value from a register. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD. + */ +struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s +{ + uint32_t index : 2; /* Index */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s ALT_SYSMGR_ROMCODE_INITSWLASTLD_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWLASTLD register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST 0xc + +/* + * Register : Boot ROM Software State Register - bootromswstate + * + * 32-bits general purpose register used by the Boot ROM code. Actual usage is + * defined in the Boot ROM source code. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [31:0] | RW | 0x0 | Boot ROM Software State + * + */ +/* + * Field : Boot ROM Software State - value + * + * Reserved for Boot ROM use. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE. + */ +struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s +{ + uint32_t value : 32; /* Boot ROM Software State */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST 0x10 + +/* + * Register Group : Warm Boot from On-Chip RAM Group - ALT_SYSMGR_ROMCODE_WARMRAM + * Warm Boot from On-Chip RAM Group + * + * Registers used by the Boot ROM code to support booting from the On-chip RAM on a + * warm reset. All these registers must be written by user software before a warm + * reset occurs to make use of this feature. + * + */ +/* + * Register : Enable Register - enable + * + * Enables or disables the warm reset from On-chip RAM feature. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [31:0] | RW | 0x0 | Warm Reset from On-chip RAM + * + */ +/* + * Field : Warm Reset from On-chip RAM - magic + * + * Controls whether Boot ROM will attempt to boot from the contents of the On-chip + * RAM on a warm reset. When this feature is enabled, the Boot ROM code will not + * configure boot IOs, the pin mux, or clocks. + * + * Note that the enable value is a 32-bit magic value (provided by the enum). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:-----------|:------------------------------------------------ + * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD | 0x0 | Boot ROM code will not attempt to boot from On- + * : | | chip RAM on a warm reset + * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END | 0xae9efebc | Boot ROM code will attempt to boot from On-chip + * : | | RAM on a warm reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC + * + * Boot ROM code will not attempt to boot from On-chip RAM on a warm reset + */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC + * + * Boot ROM code will attempt to boot from On-chip RAM on a warm reset + */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END 0xae9efebc + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s +{ + uint32_t magic : 32; /* Warm Reset from On-chip RAM */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s ALT_SYSMGR_ROMCODE_WARMRAM_EN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST 0x0 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST)) + +/* + * Register : Data Start Register - datastart + * + * Offset into On-chip RAM of the start of the region for CRC validation + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------ + * [15:0] | RW | 0x0 | Data Start Offset + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Start Offset - offset + * + * Contains the byte offset into the On-chip RAM of the start of the On-chip RAM + * region for the warm boot CRC validation. The offset must be an integer multiple + * of 4 (i.e. aligned to a word). The Boot ROM code will set the top 16 bits to + * 0xFFFF and clear the bottom 2 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_MSB 15 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s +{ + uint32_t offset : 16; /* Data Start Offset */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST 0x4 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST)) + +/* + * Register : Length Register - length + * + * Length of region in On-chip RAM for CRC validation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------ + * [15:0] | RW | 0x0 | Size + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Size - size + * + * Contains the length (in bytes) of the region in the On-chip RAM for the warm + * boot CRC validation. + * + * If the length is 0, the Boot ROM won't perform CRC calculation and CRC check to + * avoid overhead caused by CRC validation. + * + * If the START + LENGTH exceeds the maximum offset into the On-chip RAM, the Boot + * ROM won't boot from the On-chip RAM. + * + * The length must be an integer multiple of 4. + * + * The Boot ROM code will clear the top 16 bits and the bottom 2 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_MSB 15 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s +{ + uint32_t size : 16; /* Size */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST 0x8 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST)) + +/* + * Register : Execution Register - execution + * + * Offset into On-chip RAM to enter to on a warm boot. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------- + * [15:0] | RW | 0x0 | Execution Offset + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Execution Offset - offset + * + * Contains the byte offset into the On-chip RAM that the Boot ROM will jump to if + * the CRC validation succeeds. + * + * The Boot ROM code will set the top 16 bits to 0xFFFF. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_MSB 15 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_WIDTH 16 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0xffff0000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s +{ + uint32_t offset : 16; /* Execution Offset */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST 0xc +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST)) + +/* + * Register : Expected CRC Register - crc + * + * Length of region in On-chip RAM for CRC validation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------- + * [31:0] | RW | 0xe763552a | Expected CRC + * + */ +/* + * Field : Expected CRC - expected + * + * Contains the expected CRC of the region in the On-chip RAM.The Boot ROM code + * calculates the actual CRC for all bytes in the region specified by the DATA + * START an LENGTH registers. The contents of the EXECUTION register (after it has + * been read and modified by the Boot ROM code) is also included in the CRC + * calculation. The contents of the EXECUTION register is added to the CRC + * accumulator a byte at a time starting with the least significant byte. If the + * actual CRC doesn't match the expected CRC value in this register, the Boot ROM + * won't boot from the On-chip RAM. + * + * The CRC is a standard CRC32 with the polynomial: + * + * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + + * x^2 + x + 1 + * + * There is no reflection of the bits and the initial value of the remainder is + * 0xFFFFFFFF and the final value is exclusive ORed with 0xFFFFFFFF. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_MSB 31 +/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_WIDTH 32 +/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff +/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000 +/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_RESET 0xe763552a +/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED field value from a register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s +{ + uint32_t expected : 32; /* Expected CRC */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register from the beginning of the component. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST 0x10 +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register. */ +#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM. + */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_s +{ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_EN_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */ + volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_s ALT_SYSMGR_ROMCODE_WARMRAM_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */ +struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s +{ + volatile uint32_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */ + volatile uint32_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */ + volatile uint32_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */ + volatile uint32_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */ + volatile uint32_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */ + volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s ALT_SYSMGR_ROMCODE_WARMRAM_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ROMCODE. + */ +struct ALT_SYSMGR_ROMCODE_s +{ + volatile ALT_SYSMGR_ROMCODE_CTL_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */ + volatile ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */ + volatile ALT_SYSMGR_ROMCODE_INITSWSTATE_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */ + volatile ALT_SYSMGR_ROMCODE_INITSWLASTLD_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */ + volatile ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ROMCODE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_s ALT_SYSMGR_ROMCODE_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */ +struct ALT_SYSMGR_ROMCODE_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */ + volatile uint32_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */ + volatile uint32_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */ + volatile uint32_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */ + volatile uint32_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */ + volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_WARMRAM_raw_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */ +typedef volatile struct ALT_SYSMGR_ROMCODE_raw_s ALT_SYSMGR_ROMCODE_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Boot ROM Hardware Register Group - ALT_SYSMGR_ROMHW + * Boot ROM Hardware Register Group + * + * Registers used by the Boot ROM hardware, not the code within it. + * + */ +/* + * Register : Boot ROM Hardware Control Register - ctrl + * + * Controls behavior of Boot ROM hardware. + * + * All fields are only reset by a cold reset (ignore warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | Wait State + * [1] | RW | 0x1 | Enable Safe Mode Warm Reset Update + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Wait State - waitstate + * + * Controls the number of wait states applied to the Boot ROM's read operation. + * + * This field is cleared on a cold reset and optionally updated by hardware upon + * deassertion of warm reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS | 0x0 | No wait states are applied to the Boom ROM's + * : | | read operation. + * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN | 0x1 | A single wait state is applied to the Boot ROM's + * : | | read operation. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE + * + * No wait states are applied to the Boom ROM's read operation. + */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE + * + * A single wait state is applied to the Boot ROM's read operation. + */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_MSB 0 +/* The width in bits of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_RESET 0x0 +/* Extracts the ALT_SYSMGR_ROMHW_CTL_WAITSTATE field value from a register. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enable Safe Mode Warm Reset Update - ensfmdwru + * + * Controls whether the wait state bit is updated upon deassertion of warm reset. + * + * This field is set on a cold reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------------------------- + * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS | 0x0 | Wait state bit is not updated upon deassertion + * : | | of warm reset. + * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN | 0x1 | Wait state bit is updated upon deassertion of + * : | | warm reset. It's value is updated based on the + * : | | control bit from clock manager which specifies + * : | | whether clock manager will be in safe mode or + * : | | not after warm reset. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU + * + * Wait state bit is not updated upon deassertion of warm reset. + */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU + * + * Wait state bit is updated upon deassertion of warm reset. + * + * It's value is updated based on the control bit from clock manager which + * specifies whether clock manager will be in safe mode or not after warm reset. + */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_MSB 1 +/* The width in bits of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_RESET 0x1 +/* Extracts the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU field value from a register. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value suitable for setting the register. */ +#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET(value) (((value) << 1) & 0x00000002) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ROMHW_CTL. + */ +struct ALT_SYSMGR_ROMHW_CTL_s +{ + uint32_t waitstate : 1; /* Wait State */ + uint32_t ensfmdwru : 1; /* Enable Safe Mode Warm Reset Update */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ROMHW_CTL. */ +typedef volatile struct ALT_SYSMGR_ROMHW_CTL_s ALT_SYSMGR_ROMHW_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ROMHW_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_ROMHW_CTL_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ROMHW. + */ +struct ALT_SYSMGR_ROMHW_s +{ + volatile ALT_SYSMGR_ROMHW_CTL_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ROMHW. */ +typedef volatile struct ALT_SYSMGR_ROMHW_s ALT_SYSMGR_ROMHW_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */ +struct ALT_SYSMGR_ROMHW_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */ +typedef volatile struct ALT_SYSMGR_ROMHW_raw_s ALT_SYSMGR_ROMHW_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : SDMMC Controller Group - ALT_SYSMGR_SDMMC + * SDMMC Controller Group + * + * Registers related to SDMMC Controller which aren't located inside the SDMMC + * itself. + * + */ +/* + * Register : Control Register - ctrl + * + * Registers used by the SDMMC Controller. All fields are reset by a cold or warm + * reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [2:0] | RW | 0x0 | Drive Clock Phase Shift Select + * [5:3] | RW | 0x0 | Sample Clock Phase Shift Select + * [6] | RW | 0x0 | Feedback Clock Select + * [31:7] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Drive Clock Phase Shift Select - drvsel + * + * Select which phase shift of the clock for cclk_in_drv. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------------------------------------- + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 0 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 45 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 90 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 135 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 180 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 225 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 270 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL + * + * 315 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_MSB 2 +/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET_MSK 0x00000007 +/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_CTL_DRVSEL field value from a register. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : Sample Clock Phase Shift Select - smplsel + * + * Select which phase shift of the clock for cclk_in_sample. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------------------- + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected + * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 0 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 45 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 90 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 135 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 180 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 225 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 270 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL + * + * 315 degrees phase shifted clock is selected + */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_MSB 5 +/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_WIDTH 3 +/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET_MSK 0x00000038 +/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_CLR_MSK 0xffffffc7 +/* The reset value of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_CTL_SMPLSEL field value from a register. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_GET(value) (((value) & 0x00000038) >> 3) +/* Produces a ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET(value) (((value) << 3) & 0x00000038) + +/* + * Field : Feedback Clock Select - fbclksel + * + * Select which fb_clk to be used as cclk_in_sample. + * + * If 0, cclk_in_sample is driven by internal phase shifted cclk_in. + * + * If 1, cclk_in_sample is driven by fb_clk_in. No phase shifting is provided + * internally on cclk_in_sample. + * + * Note: Using the feedback clock (setting this bit to 1) is not a supported use + * model. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_MSB 6 +/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL field value from a register. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET(value) (((value) << 6) & 0x00000040) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SDMMC_CTL. + */ +struct ALT_SYSMGR_SDMMC_CTL_s +{ + uint32_t drvsel : 3; /* Drive Clock Phase Shift Select */ + uint32_t smplsel : 3; /* Sample Clock Phase Shift Select */ + uint32_t fbclksel : 1; /* Feedback Clock Select */ + uint32_t : 25; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SDMMC_CTL. */ +typedef volatile struct ALT_SYSMGR_SDMMC_CTL_s ALT_SYSMGR_SDMMC_CTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SDMMC_CTL register from the beginning of the component. */ +#define ALT_SYSMGR_SDMMC_CTL_OFST 0x0 + +/* + * Register : SD/MMC L3 Master HPROT Register - l3master + * + * Controls the L3 master HPROT AHB-Lite signal. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x1 | SD/MMC HPROT Data/Opcode + * [1] | RW | 0x1 | SD/MMC HPROT Privileged + * [2] | RW | 0x0 | SD/MMC HPROT Bufferable + * [3] | RW | 0x0 | SD/MMC HPROT Cacheable + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SD/MMC HPROT Data/Opcode - hprotdata_0 + * + * Specifies if the L3 master access is for data or opcode for the SD/MMC module. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------- + * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch + * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 + * + * Opcode fetch + */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 + * + * Data access + */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SD/MMC HPROT Privileged - hprotpriv_0 + * + * If 1, L3 master accesses for the SD/MMC module are privileged. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_MSB 1 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SD/MMC HPROT Bufferable - hprotbuff_0 + * + * If 1, L3 master accesses for the SD/MMC module are bufferable. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SD/MMC HPROT Cacheable - hprotcache_0 + * + * If 1, L3 master accesses for the SD/MMC module are cacheable. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_MSB 3 +/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 field value from a register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_SDMMC_L3MST. + */ +struct ALT_SYSMGR_SDMMC_L3MST_s +{ + uint32_t hprotdata_0 : 1; /* SD/MMC HPROT Data/Opcode */ + uint32_t hprotpriv_0 : 1; /* SD/MMC HPROT Privileged */ + uint32_t hprotbuff_0 : 1; /* SD/MMC HPROT Bufferable */ + uint32_t hprotcache_0 : 1; /* SD/MMC HPROT Cacheable */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_SDMMC_L3MST. */ +typedef volatile struct ALT_SYSMGR_SDMMC_L3MST_s ALT_SYSMGR_SDMMC_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_SDMMC_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_SDMMC_L3MST_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_SDMMC. + */ +struct ALT_SYSMGR_SDMMC_s +{ + volatile ALT_SYSMGR_SDMMC_CTL_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */ + volatile ALT_SYSMGR_SDMMC_L3MST_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_SDMMC. */ +typedef volatile struct ALT_SYSMGR_SDMMC_s ALT_SYSMGR_SDMMC_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */ +struct ALT_SYSMGR_SDMMC_raw_s +{ + volatile uint32_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */ + volatile uint32_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */ +typedef volatile struct ALT_SYSMGR_SDMMC_raw_s ALT_SYSMGR_SDMMC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : NAND Flash Controller Register Group - ALT_SYSMGR_NAND + * NAND Flash Controller Register Group + * + * Registers related to NAND Flash Controller which aren't located in the NAND + * Flash Controller itself. + * + */ +/* + * Register : Bootstrap Control Register - bootstrap + * + * Bootstrap fields sampled by NAND Flash Controller when released from reset. + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x0 | Bootstrap Inhibit Initialization + * [1] | RW | 0x0 | Bootstrap 512 Byte Device + * [2] | RW | 0x0 | Bootstrap Inhibit Load Block 0 Page 0 + * [3] | RW | 0x0 | Bootstrap Two Row Address Cycles + * [31:4] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Bootstrap Inhibit Initialization - noinit + * + * If 1, inhibits NAND Flash Controller from performing initialization when coming + * out of reset. Instead, software must program all registers pertaining to device + * parameters like page size, width, etc. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Bootstrap 512 Byte Device - page512 + * + * If 1, NAND device has a 512 byte page size. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 1 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Bootstrap Inhibit Load Block 0 Page 0 - noloadb0p0 + * + * If 1, inhibits NAND Flash Controller from loading page 0 of block 0 of the NAND + * device as part of the initialization procedure. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 2 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Bootstrap Two Row Address Cycles - tworowaddr + * + * If 1, NAND device requires only 2 row address cycles instead of the normal 3 row + * address cycles. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 3 +/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR field value from a register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 3) & 0x00000008) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. + */ +struct ALT_SYSMGR_NAND_BOOTSTRAP_s +{ + uint32_t noinit : 1; /* Bootstrap Inhibit Initialization */ + uint32_t page512 : 1; /* Bootstrap 512 Byte Device */ + uint32_t noloadb0p0 : 1; /* Bootstrap Inhibit Load Block 0 Page 0 */ + uint32_t tworowaddr : 1; /* Bootstrap Two Row Address Cycles */ + uint32_t : 28; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. */ +typedef volatile struct ALT_SYSMGR_NAND_BOOTSTRAP_s ALT_SYSMGR_NAND_BOOTSTRAP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_NAND_BOOTSTRAP register from the beginning of the component. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x0 + +/* + * Register : NAND L3 Master AxCACHE Register - l3master + * + * Controls the L3 master ARCACHE and AWCACHE AXI signals. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [3:0] | RW | 0x0 | NAND ARCACHE + * [7:4] | RW | 0x0 | NAND AWCACHE + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND ARCACHE - arcache_0 + * + * Specifies the value of the module ARCACHE signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3 +/* The width in bits of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f +/* The mask used to clear the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 field value from a register. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : NAND AWCACHE - awcache_0 + * + * Specifies the value of the module AWCACHE signal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------------------|:------|:------------------------------------------------- + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes + * : | | only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads + * : | | and writes. + * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and + * : | | writes. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Noncacheable and nonbufferable. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Bufferable only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable and bufferable, but do not allocate. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on reads only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9 +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on writes only. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Reserved. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-through, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe +/* + * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 + * + * Cacheable write-back, allocate on both reads and writes. + */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7 +/* The width in bits of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4 +/* The mask used to set the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0 +/* The mask used to clear the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f +/* The reset value of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 field value from a register. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4) +/* Produces a ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_NAND_L3MST. + */ +struct ALT_SYSMGR_NAND_L3MST_s +{ + uint32_t arcache_0 : 4; /* NAND ARCACHE */ + uint32_t awcache_0 : 4; /* NAND AWCACHE */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_NAND_L3MST. */ +typedef volatile struct ALT_SYSMGR_NAND_L3MST_s ALT_SYSMGR_NAND_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_NAND_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_NAND_L3MST_OFST 0x4 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_NAND. + */ +struct ALT_SYSMGR_NAND_s +{ + volatile ALT_SYSMGR_NAND_BOOTSTRAP_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */ + volatile ALT_SYSMGR_NAND_L3MST_t l3master; /* ALT_SYSMGR_NAND_L3MST */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_NAND. */ +typedef volatile struct ALT_SYSMGR_NAND_s ALT_SYSMGR_NAND_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_NAND. */ +struct ALT_SYSMGR_NAND_raw_s +{ + volatile uint32_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */ + volatile uint32_t l3master; /* ALT_SYSMGR_NAND_L3MST */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_NAND. */ +typedef volatile struct ALT_SYSMGR_NAND_raw_s ALT_SYSMGR_NAND_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : USB Controller Group - ALT_SYSMGR_USB + * USB Controller Group + * + * Registers related to USB Controllers which aren't located inside the USB + * controllers themselves. + * + */ +/* + * Register : USB L3 Master HPROT Register - l3master + * + * Controls the L3 master HPROT AHB-Lite signal. + * + * These register bits should be updated only during system initialization prior to + * removing the peripheral from reset. They may not be changed dynamically during + * peripheral operation + * + * All fields are reset by a cold or warm reset. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | RW | 0x1 | USB HPROT Data/Opcode + * [1] | RW | 0x1 | USB HPROT Data/Opcode + * [2] | RW | 0x1 | USB HPROT Privileged + * [3] | RW | 0x1 | USB HPROT Privileged + * [4] | RW | 0x0 | USB HPROT Bufferable + * [5] | RW | 0x0 | USB HPROT Bufferable + * [6] | RW | 0x0 | USB HPROT Cacheable + * [7] | RW | 0x0 | USB HPROT Cacheable + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB HPROT Data/Opcode - hprotdata_0 + * + * Specifies if the L3 master access is for data or opcode for the USB modules. + * + * The field array index corresponds to the USB index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch + * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0 + * + * Opcode fetch + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0 + * + * Data access + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_MSB 0 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : USB HPROT Data/Opcode - hprotdata_1 + * + * Specifies if the L3 master access is for data or opcode for the USB modules. + * + * The field array index corresponds to the USB index. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------- + * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE | 0x0 | Opcode fetch + * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA | 0x1 | Data access + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1 + * + * Opcode fetch + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE 0x0 +/* + * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1 + * + * Data access + */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_MSB 1 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB HPROT Privileged - hprotpriv_0 + * + * If 1, L3 master accesses for the USB modules are privileged. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_MSB 2 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB HPROT Privileged - hprotpriv_1 + * + * If 1, L3 master accesses for the USB modules are privileged. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_MSB 3 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_RESET 0x1 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : USB HPROT Bufferable - hprotbuff_0 + * + * If 1, L3 master accesses for the USB modules are bufferable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_MSB 4 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : USB HPROT Bufferable - hprotbuff_1 + * + * If 1, L3 master accesses for the USB modules are bufferable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_MSB 5 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : USB HPROT Cacheable - hprotcache_0 + * + * If 1, L3 master accesses for the USB modules are cacheable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_MSB 6 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : USB HPROT Cacheable - hprotcache_1 + * + * If 1, L3 master accesses for the USB modules are cacheable. + * + * The field array index corresponds to the USB index. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_MSB 7 +/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_RESET 0x0 +/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 field value from a register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value suitable for setting the register. */ +#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_USB_L3MST. + */ +struct ALT_SYSMGR_USB_L3MST_s +{ + uint32_t hprotdata_0 : 1; /* USB HPROT Data/Opcode */ + uint32_t hprotdata_1 : 1; /* USB HPROT Data/Opcode */ + uint32_t hprotpriv_0 : 1; /* USB HPROT Privileged */ + uint32_t hprotpriv_1 : 1; /* USB HPROT Privileged */ + uint32_t hprotbuff_0 : 1; /* USB HPROT Bufferable */ + uint32_t hprotbuff_1 : 1; /* USB HPROT Bufferable */ + uint32_t hprotcache_0 : 1; /* USB HPROT Cacheable */ + uint32_t hprotcache_1 : 1; /* USB HPROT Cacheable */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_USB_L3MST. */ +typedef volatile struct ALT_SYSMGR_USB_L3MST_s ALT_SYSMGR_USB_L3MST_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_USB_L3MST register from the beginning of the component. */ +#define ALT_SYSMGR_USB_L3MST_OFST 0x0 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_USB. + */ +struct ALT_SYSMGR_USB_s +{ + volatile ALT_SYSMGR_USB_L3MST_t l3master; /* ALT_SYSMGR_USB_L3MST */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_USB. */ +typedef volatile struct ALT_SYSMGR_USB_s ALT_SYSMGR_USB_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_USB. */ +struct ALT_SYSMGR_USB_raw_s +{ + volatile uint32_t l3master; /* ALT_SYSMGR_USB_L3MST */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_USB. */ +typedef volatile struct ALT_SYSMGR_USB_raw_s ALT_SYSMGR_USB_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : ECC Management Register Group - ALT_SYSMGR_ECC + * ECC Management Register Group + * + * ECC error status and control for all ECC-protected HPS RAM blocks. + * + */ +/* + * Register : L2 Data RAM ECC Enable Register - l2 + * + * This register is used to enable ECC on the L2 Data RAM. ECC errors can be + * injected into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------------------------- + * [0] | RW | 0x0 | L2 Data RAM ECC Enable + * [1] | RW | 0x0 | L2 Data RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | L2 Data RAM ECC inject double bit, non-correctable error + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : L2 Data RAM ECC Enable - en + * + * Enable ECC for L2 Data RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_L2_EN register field value. */ +#define ALT_SYSMGR_ECC_L2_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_L2_EN register field value. */ +#define ALT_SYSMGR_ECC_L2_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_L2_EN register field. */ +#define ALT_SYSMGR_ECC_L2_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_L2_EN field value from a register. */ +#define ALT_SYSMGR_ECC_L2_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_L2_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_L2_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : L2 Data RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * L2 Data RAM. This only injects one error into the L2 Data RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_L2_INJS register field value. */ +#define ALT_SYSMGR_ECC_L2_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_L2_INJS register field value. */ +#define ALT_SYSMGR_ECC_L2_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_L2_INJS register field. */ +#define ALT_SYSMGR_ECC_L2_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_L2_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_L2_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_L2_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_L2_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : L2 Data RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the L2 Data RAM. This only injects one double bit error into the L2 Data RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_L2_INJD register field value. */ +#define ALT_SYSMGR_ECC_L2_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_L2_INJD register field value. */ +#define ALT_SYSMGR_ECC_L2_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_L2_INJD register field. */ +#define ALT_SYSMGR_ECC_L2_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_L2_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_L2_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_L2_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_L2_INJD_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_L2. + */ +struct ALT_SYSMGR_ECC_L2_s +{ + uint32_t en : 1; /* L2 Data RAM ECC Enable */ + uint32_t injs : 1; /* L2 Data RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* L2 Data RAM ECC inject double bit, non-correctable error */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_L2. */ +typedef volatile struct ALT_SYSMGR_ECC_L2_s ALT_SYSMGR_ECC_L2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_L2 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_L2_OFST 0x0 + +/* + * Register : On-chip RAM ECC Enable Register - ocram + * + * This register is used to enable ECC on the On-chip RAM. ECC errors can be + * injected into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------- + * [0] | RW | 0x0 | On-chip RAM ECC Enable + * [1] | RW | 0x0 | On-chip RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | On-chip RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | On-chip RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | On-chip RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : On-chip RAM ECC Enable - en + * + * Enable ECC for On-chip RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_EN register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_EN register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_EN field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_OCRAM_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : On-chip RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * On-chip RAM. This only injects one error into the On-chip RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_OCRAM_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : On-chip RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the On-chip RAM. This only injects one double bit error into the On-chip RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_OCRAM_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : On-chip RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for On-chip RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in On-chip + * RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_OCRAM_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : On-chip RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for On-chip RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in On-chip RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_OCRAM_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_OCRAM_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_OCRAM_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_OCRAM. + */ +struct ALT_SYSMGR_ECC_OCRAM_s +{ + uint32_t en : 1; /* On-chip RAM ECC Enable */ + uint32_t injs : 1; /* On-chip RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* On-chip RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* On-chip RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* On-chip RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_OCRAM. */ +typedef volatile struct ALT_SYSMGR_ECC_OCRAM_s ALT_SYSMGR_ECC_OCRAM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_OCRAM register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_OCRAM_OFST 0x4 + +/* + * Register : USB0 RAM ECC Enable Register - usb0 + * + * This register is used to enable ECC on the USB0 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | USB0 RAM ECC Enable + * [1] | RW | 0x0 | USB0 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | USB0 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | USB0 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | USB0 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB0 RAM ECC Enable - en + * + * Enable ECC for USB0 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_EN register field value. */ +#define ALT_SYSMGR_ECC_USB0_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_EN register field value. */ +#define ALT_SYSMGR_ECC_USB0_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_USB0_EN register field. */ +#define ALT_SYSMGR_ECC_USB0_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_EN field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_USB0_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : USB0 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * USB0 RAM. This only injects one error into the USB0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_USB0_INJS register field. */ +#define ALT_SYSMGR_ECC_USB0_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_USB0_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB0 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the USB0 RAM. This only injects one double bit error into the USB0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB0_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_USB0_INJD register field. */ +#define ALT_SYSMGR_ECC_USB0_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_USB0_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB0 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for USB0 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in USB0 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_USB0_SERR register field. */ +#define ALT_SYSMGR_ECC_USB0_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_USB0_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : USB0 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for USB0 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * USB0 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB0_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_USB0_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB0_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_USB0_DERR register field. */ +#define ALT_SYSMGR_ECC_USB0_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB0_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB0_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_USB0_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB0_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_USB0. + */ +struct ALT_SYSMGR_ECC_USB0_s +{ + uint32_t en : 1; /* USB0 RAM ECC Enable */ + uint32_t injs : 1; /* USB0 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* USB0 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* USB0 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* USB0 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_USB0. */ +typedef volatile struct ALT_SYSMGR_ECC_USB0_s ALT_SYSMGR_ECC_USB0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_USB0 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_USB0_OFST 0x8 + +/* + * Register : USB1 RAM ECC Enable Register - usb1 + * + * This register is used to enable ECC on the USB1 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | USB1 RAM ECC Enable + * [1] | RW | 0x0 | USB1 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | USB1 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | USB1 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | USB1 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : USB1 RAM ECC Enable - en + * + * Enable ECC for USB1 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_EN register field value. */ +#define ALT_SYSMGR_ECC_USB1_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_EN register field value. */ +#define ALT_SYSMGR_ECC_USB1_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_USB1_EN register field. */ +#define ALT_SYSMGR_ECC_USB1_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_EN field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_USB1_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : USB1 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * USB1 RAM. This only injects one error into the USB1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJS register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_USB1_INJS register field. */ +#define ALT_SYSMGR_ECC_USB1_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_USB1_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : USB1 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the USB1 RAM. This only injects one double bit error into the USB1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJD register field value. */ +#define ALT_SYSMGR_ECC_USB1_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_USB1_INJD register field. */ +#define ALT_SYSMGR_ECC_USB1_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_USB1_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : USB1 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for USB1 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in USB1 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_SERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_USB1_SERR register field. */ +#define ALT_SYSMGR_ECC_USB1_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_USB1_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : USB1 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for USB1 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * USB1 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_USB1_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_USB1_DERR register field value. */ +#define ALT_SYSMGR_ECC_USB1_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_USB1_DERR register field. */ +#define ALT_SYSMGR_ECC_USB1_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_USB1_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_USB1_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_USB1_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_USB1_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_USB1. + */ +struct ALT_SYSMGR_ECC_USB1_s +{ + uint32_t en : 1; /* USB1 RAM ECC Enable */ + uint32_t injs : 1; /* USB1 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* USB1 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* USB1 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* USB1 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_USB1. */ +typedef volatile struct ALT_SYSMGR_ECC_USB1_s ALT_SYSMGR_ECC_USB1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_USB1 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_USB1_OFST 0xc + +/* + * Register : EMAC0 RAM ECC Enable Register - emac0 + * + * This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------------ + * [0] | RW | 0x0 | EMAC0 RAM ECC Enable + * [1] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject single, correctable Error + * [4] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error + * [5] | RW | 0x0 | EMAC0 TXFIFO RAM ECC single, correctable error interrupt status + * [6] | RW | 0x0 | EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status + * [7] | RW | 0x0 | EMAC0 RXFIFO RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC0 RAM ECC Enable - en + * + * Enable ECC for EMAC0 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_EN field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_EMAC0_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : EMAC0 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC0 TXFIFO RAM. This only injects one error into the EMAC0 TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC0 TXFIFO RAM. This only injects one double bit error into the EMAC0 + * TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : EMAC0 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC0 RXFIFO RAM. This only injects one error into the EMAC0 RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC0 RXFIFO RAM. This only injects one double bit error into the EMAC0 + * RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : EMAC0 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr + * + * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC0 + * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr + * + * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : EMAC0 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr + * + * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC0 + * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr + * + * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC0 RXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_EMAC0. + */ +struct ALT_SYSMGR_ECC_EMAC0_s +{ + uint32_t en : 1; /* EMAC0 RAM ECC Enable */ + uint32_t txfifoinjs : 1; /* EMAC0 TXFIFO RAM ECC inject single, correctable Error */ + uint32_t txfifoinjd : 1; /* EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t rxfifoinjs : 1; /* EMAC0 RXFIFO RAM ECC inject single, correctable Error */ + uint32_t rxfifoinjd : 1; /* EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t txfifoserr : 1; /* EMAC0 TXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t txfifoderr : 1; /* EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t rxfifoserr : 1; /* EMAC0 RXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t rxfifoderr : 1; /* EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_EMAC0. */ +typedef volatile struct ALT_SYSMGR_ECC_EMAC0_s ALT_SYSMGR_ECC_EMAC0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_EMAC0 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_EMAC0_OFST 0x10 + +/* + * Register : EMAC1 RAM ECC Enable Register - emac1 + * + * This register is used to enable ECC on the EMAC1 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------------ + * [0] | RW | 0x0 | EMAC1 RAM ECC Enable + * [1] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject single, correctable Error + * [4] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error + * [5] | RW | 0x0 | EMAC1 TXFIFO RAM ECC single, correctable error interrupt status + * [6] | RW | 0x0 | EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status + * [7] | RW | 0x0 | EMAC1 RXFIFO RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : EMAC1 RAM ECC Enable - en + * + * Enable ECC for EMAC1 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_EN register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_EN field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_EMAC1_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : EMAC1 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC1 TXFIFO RAM. This only injects one error into the EMAC1 TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC1 TXFIFO RAM. This only injects one double bit error into the EMAC1 + * TXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : EMAC1 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * EMAC1 RXFIFO RAM. This only injects one error into the EMAC1 RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the EMAC1 RXFIFO RAM. This only injects one double bit error into the EMAC1 + * RXFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : EMAC1 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr + * + * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC1 + * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr + * + * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC1 TXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : EMAC1 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr + * + * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in EMAC1 + * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr + * + * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in EMAC1 RXFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_EMAC1. + */ +struct ALT_SYSMGR_ECC_EMAC1_s +{ + uint32_t en : 1; /* EMAC1 RAM ECC Enable */ + uint32_t txfifoinjs : 1; /* EMAC1 TXFIFO RAM ECC inject single, correctable Error */ + uint32_t txfifoinjd : 1; /* EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t rxfifoinjs : 1; /* EMAC1 RXFIFO RAM ECC inject single, correctable Error */ + uint32_t rxfifoinjd : 1; /* EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t txfifoserr : 1; /* EMAC1 TXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t txfifoderr : 1; /* EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t rxfifoserr : 1; /* EMAC1 RXFIFO RAM ECC single, correctable error interrupt status */ + uint32_t rxfifoderr : 1; /* EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_EMAC1. */ +typedef volatile struct ALT_SYSMGR_ECC_EMAC1_s ALT_SYSMGR_ECC_EMAC1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_EMAC1 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_EMAC1_OFST 0x14 + +/* + * Register : DMA RAM ECC Enable Register - dma + * + * This register is used to enable ECC on the DMA RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------------------------------- + * [0] | RW | 0x0 | DMA RAM ECC Enable + * [1] | RW | 0x0 | DMA RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | DMA RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | DMA RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | DMA RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA RAM ECC Enable - en + * + * Enable ECC for DMA RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_EN register field value. */ +#define ALT_SYSMGR_ECC_DMA_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_EN register field value. */ +#define ALT_SYSMGR_ECC_DMA_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_DMA_EN register field. */ +#define ALT_SYSMGR_ECC_DMA_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_EN field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_DMA_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : DMA RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * DMA RAM. This only injects one error into the DMA RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_INJS register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJS register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_DMA_INJS register field. */ +#define ALT_SYSMGR_ECC_DMA_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_DMA_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : DMA RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the DMA RAM. This only injects one double bit error into the DMA RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_INJD register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJD register field value. */ +#define ALT_SYSMGR_ECC_DMA_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_DMA_INJD register field. */ +#define ALT_SYSMGR_ECC_DMA_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_DMA_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DMA RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for DMA RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in DMA RAM. Software + * needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_SERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_SERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_DMA_SERR register field. */ +#define ALT_SYSMGR_ECC_DMA_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_DMA_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : DMA RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for DMA RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * DMA RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_DMA_DERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_DMA_DERR register field value. */ +#define ALT_SYSMGR_ECC_DMA_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_DMA_DERR register field. */ +#define ALT_SYSMGR_ECC_DMA_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_DMA_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_DMA_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_DMA_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_DMA_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_DMA. + */ +struct ALT_SYSMGR_ECC_DMA_s +{ + uint32_t en : 1; /* DMA RAM ECC Enable */ + uint32_t injs : 1; /* DMA RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* DMA RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* DMA RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* DMA RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_DMA. */ +typedef volatile struct ALT_SYSMGR_ECC_DMA_s ALT_SYSMGR_ECC_DMA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_DMA register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_DMA_OFST 0x18 + +/* + * Register : CAN0 RAM ECC Enable Register - can0 + * + * This register is used to enable ECC on the CAN0 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | CAN0 RAM ECC Enable + * [1] | RW | 0x0 | CAN0 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | CAN0 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | CAN0 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | CAN0 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : CAN0 RAM ECC Enable - en + * + * Enable ECC for CAN0 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN0_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN0_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_CAN0_EN register field. */ +#define ALT_SYSMGR_ECC_CAN0_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_EN field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_CAN0_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CAN0 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * CAN0 RAM. This only injects one error into the CAN0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_CAN0_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : CAN0 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the CAN0 RAM. This only injects one double bit error into the CAN0 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_CAN0_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : CAN0 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for CAN0 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in CAN0 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_CAN0_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : CAN0 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for CAN0 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * CAN0 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN0_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN0_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_CAN0_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN0_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_CAN0. + */ +struct ALT_SYSMGR_ECC_CAN0_s +{ + uint32_t en : 1; /* CAN0 RAM ECC Enable */ + uint32_t injs : 1; /* CAN0 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* CAN0 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* CAN0 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* CAN0 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_CAN0. */ +typedef volatile struct ALT_SYSMGR_ECC_CAN0_s ALT_SYSMGR_ECC_CAN0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_CAN0 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_CAN0_OFST 0x1c + +/* + * Register : CAN1 RAM ECC Enable Register - can1 + * + * This register is used to enable ECC on the CAN1 RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | CAN1 RAM ECC Enable + * [1] | RW | 0x0 | CAN1 RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | CAN1 RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | CAN1 RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | CAN1 RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : CAN1 RAM ECC Enable - en + * + * Enable ECC for CAN1 RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN1_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_EN register field value. */ +#define ALT_SYSMGR_ECC_CAN1_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_CAN1_EN register field. */ +#define ALT_SYSMGR_ECC_CAN1_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_EN field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_CAN1_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : CAN1 RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * CAN1 RAM. This only injects one error into the CAN1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJS register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_CAN1_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : CAN1 RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the CAN1 RAM. This only injects one double bit error into the CAN1 RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJD register field value. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_CAN1_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : CAN1 RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for CAN1 RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in CAN1 RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_SERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_CAN1_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : CAN1 RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for CAN1 RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * CAN1 RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_CAN1_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_DERR register field value. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_CAN1_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_CAN1_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_CAN1_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_CAN1. + */ +struct ALT_SYSMGR_ECC_CAN1_s +{ + uint32_t en : 1; /* CAN1 RAM ECC Enable */ + uint32_t injs : 1; /* CAN1 RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* CAN1 RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* CAN1 RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* CAN1 RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_CAN1. */ +typedef volatile struct ALT_SYSMGR_ECC_CAN1_s ALT_SYSMGR_ECC_CAN1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_CAN1 register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_CAN1_OFST 0x20 + +/* + * Register : NAND RAM ECC Enable Register - nand + * + * This register is used to enable ECC on the NAND RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------------------------------------- + * [0] | RW | 0x0 | NAND RAM ECC Enable + * [1] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | NAND WRFIFO RAM ECC inject single, correctable Error + * [4] | RW | 0x0 | NAND WRFIFO RAM ECC inject double bit, non-correctable error + * [5] | RW | 0x0 | NAND RDFIFO RAM ECC inject single, correctable Error + * [6] | RW | 0x0 | NAND RDFIFO RAM ECC inject double bit, non-correctable error + * [7] | RW | 0x0 | NAND ECCBUFFER RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status + * [9] | RW | 0x0 | NAND WRFIFO RAM ECC single, correctable error interrupt status + * [10] | RW | 0x0 | NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status + * [11] | RW | 0x0 | NAND RDFIFO RAM ECC single, correctable error interrupt status + * [12] | RW | 0x0 | NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status + * [31:13] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : NAND RAM ECC Enable - en + * + * Enable ECC for NAND RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_EN register field value. */ +#define ALT_SYSMGR_ECC_NAND_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_EN register field value. */ +#define ALT_SYSMGR_ECC_NAND_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_NAND_EN register field. */ +#define ALT_SYSMGR_ECC_NAND_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_EN field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_NAND_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : NAND ECCBUFFER RAM ECC inject single, correctable Error - eccbufinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * NAND ECCBUFFER RAM. This only injects one error into the NAND ECCBUFFER RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJS field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : NAND ECCBUFFER RAM ECC inject double bit, non-correctable error - eccbufinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the NAND ECCBUFFER RAM. This only injects one double bit error into the NAND + * ECCBUFFER RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJD field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : NAND WRFIFO RAM ECC inject single, correctable Error - wrfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * NAND WRFIFO RAM. This only injects one error into the NAND WRFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAND WRFIFO RAM ECC inject double bit, non-correctable error - wrfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the NAND WRFIFO RAM. This only injects one double bit error into the NAND WRFIFO + * RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : NAND RDFIFO RAM ECC inject single, correctable Error - rdfifoinjs + * + * Changing this bit from zero to one injects a single, correctable error into the + * NAND RDFIFO RAM. This only injects one error into the NAND RDFIFO RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJS field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NAND RDFIFO RAM ECC inject double bit, non-correctable error - rdfifoinjd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the NAND RDFIFO RAM. This only injects one double bit error into the NAND RDFIFO + * RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJD field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : NAND ECCBUFFER RAM ECC single, correctable error interrupt status - eccbufserr + * + * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC single, + * correctable error. It is set by hardware when single, correctable error occurs + * in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFSERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status - eccbufderr + * + * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear + * the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFDERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : NAND WRFIFO RAM ECC single, correctable error interrupt status - wrfifoserr + * + * This bit is an interrupt status bit for NAND WRFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in NAND + * WRFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_MSB 9 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status - wrfifoderr + * + * This bit is an interrupt status bit for NAND WRFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in NAND WRFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_MSB 10 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : NAND RDFIFO RAM ECC single, correctable error interrupt status - rdfifoserr + * + * This bit is an interrupt status bit for NAND RDFIFO RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in NAND + * RDFIFO RAM. Software needs to write 1 into this bit to clear the interrupt + * status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_MSB 11 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOSERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status - rdfifoderr + * + * This bit is an interrupt status bit for NAND RDFIFO RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in NAND RDFIFO RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_MSB 12 +/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFODERR field value from a register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET(value) (((value) << 12) & 0x00001000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_NAND. + */ +struct ALT_SYSMGR_ECC_NAND_s +{ + uint32_t en : 1; /* NAND RAM ECC Enable */ + uint32_t eccbufinjs : 1; /* NAND ECCBUFFER RAM ECC inject single, correctable Error */ + uint32_t eccbufinjd : 1; /* NAND ECCBUFFER RAM ECC inject double bit, non-correctable error */ + uint32_t wrfifoinjs : 1; /* NAND WRFIFO RAM ECC inject single, correctable Error */ + uint32_t wrfifoinjd : 1; /* NAND WRFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t rdfifoinjs : 1; /* NAND RDFIFO RAM ECC inject single, correctable Error */ + uint32_t rdfifoinjd : 1; /* NAND RDFIFO RAM ECC inject double bit, non-correctable error */ + uint32_t eccbufserr : 1; /* NAND ECCBUFFER RAM ECC single, correctable error interrupt status */ + uint32_t eccbufderr : 1; /* NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status */ + uint32_t wrfifoserr : 1; /* NAND WRFIFO RAM ECC single, correctable error interrupt status */ + uint32_t wrfifoderr : 1; /* NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t rdfifoserr : 1; /* NAND RDFIFO RAM ECC single, correctable error interrupt status */ + uint32_t rdfifoderr : 1; /* NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 19; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_NAND. */ +typedef volatile struct ALT_SYSMGR_ECC_NAND_s ALT_SYSMGR_ECC_NAND_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_NAND register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_NAND_OFST 0x24 + +/* + * Register : QSPI RAM ECC Enable Register - qspi + * + * This register is used to enable ECC on the QSPI RAM. ECC errors can be injected + * into the write path using bits in this register. This register contains + * interrupt status of the ECC single/double bit error. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------------------------------- + * [0] | RW | 0x0 | QSPI RAM ECC Enable + * [1] | RW | 0x0 | QSPI RAM ECC inject single, correctable Error + * [2] | RW | 0x0 | QSPI RAM ECC inject double bit, non-correctable error + * [3] | RW | 0x0 | QSPI RAM ECC single, correctable error interrupt status + * [4] | RW | 0x0 | QSPI RAM ECC double bit, non-correctable error interrupt status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : QSPI RAM ECC Enable - en + * + * Enable ECC for QSPI RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_EN register field value. */ +#define ALT_SYSMGR_ECC_QSPI_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_EN register field value. */ +#define ALT_SYSMGR_ECC_QSPI_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_QSPI_EN register field. */ +#define ALT_SYSMGR_ECC_QSPI_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_EN field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_QSPI_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : QSPI RAM ECC inject single, correctable Error - injs + * + * Changing this bit from zero to one injects a single, correctable error into the + * QSPI RAM. This only injects one error into the QSPI RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJS register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJS register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_INJS field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_QSPI_INJS register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_INJS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : QSPI RAM ECC inject double bit, non-correctable error - injd + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the QSPI RAM. This only injects one double bit error into the QSPI RAM. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJD register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJD register field value. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_INJD field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_QSPI_INJD register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_INJD_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : QSPI RAM ECC single, correctable error interrupt status - serr + * + * This bit is an interrupt status bit for QSPI RAM ECC single, correctable error. + * It is set by hardware when single, correctable error occurs in QSPI RAM. + * Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_SERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_SERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_SERR field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_QSPI_SERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_SERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : QSPI RAM ECC double bit, non-correctable error interrupt status - derr + * + * This bit is an interrupt status bit for QSPI RAM ECC double bit, non-correctable + * error. It is set by hardware when double bit, non-correctable error occurs in + * QSPI RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_QSPI_DERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_DERR register field value. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_QSPI_DERR field value from a register. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_QSPI_DERR register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_QSPI_DERR_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_QSPI. + */ +struct ALT_SYSMGR_ECC_QSPI_s +{ + uint32_t en : 1; /* QSPI RAM ECC Enable */ + uint32_t injs : 1; /* QSPI RAM ECC inject single, correctable Error */ + uint32_t injd : 1; /* QSPI RAM ECC inject double bit, non-correctable error */ + uint32_t serr : 1; /* QSPI RAM ECC single, correctable error interrupt status */ + uint32_t derr : 1; /* QSPI RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_QSPI. */ +typedef volatile struct ALT_SYSMGR_ECC_QSPI_s ALT_SYSMGR_ECC_QSPI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_QSPI register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_QSPI_OFST 0x28 + +/* + * Register : SDMMC RAM ECC Enable Register - sdmmc + * + * This register is used to enable ECC on the SDMMC RAM.ECC errors can be injected + * into the write path using bits in this register. + * + * Only reset by a cold reset (ignores warm reset). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------------------------------------------ + * [0] | RW | 0x0 | SDMMC RAM ECC Enable + * [1] | RW | 0x0 | SDMMC Port A RAM ECC inject single, correctable Error at Port A + * [2] | RW | 0x0 | SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A + * [3] | RW | 0x0 | SDMMC Port B RAM ECC inject single, correctable Error at Port B + * [4] | RW | 0x0 | SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B + * [5] | RW | 0x0 | SDMMC Port A RAM ECC single, correctable error interrupt status + * [6] | RW | 0x0 | SDMMC Port A RAM ECC double bit, non-correctable error interrupt status + * [7] | RW | 0x0 | SDMMC Port B RAM ECC single, correctable error interrupt status + * [8] | RW | 0x0 | SDMMC Port B RAM ECC double bit, non-correctable error interrupt status + * [31:9] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : SDMMC RAM ECC Enable - en + * + * Enable ECC for SDMMC RAM + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_MSB 0 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_EN register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_EN register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_EN field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_ECC_SDMMC_EN register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : SDMMC Port A RAM ECC inject single, correctable Error at Port A - injsporta + * + * Changing this bit from zero to one injects a single, correctable error into the + * SDMMC RAM at Port A. This only injects one error into the SDMMC RAM at Port A. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_MSB 1 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET_MSK 0x00000002 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_CLR_MSK 0xfffffffd +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A - injdporta + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the SDMMC RAM at Port A. This only injects one double bit error into the SDMMC + * RAM at Port A. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_MSB 2 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK 0x00000004 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_CLR_MSK 0xfffffffb +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SDMMC Port B RAM ECC inject single, correctable Error at Port B - injsportb + * + * Changing this bit from zero to one injects a single, correctable error into the + * SDMMC RAM at Port B. This only injects one error into the SDMMC RAM at Port B. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_MSB 3 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET_MSK 0x00000008 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B - injdportb + * + * Changing this bit from zero to one injects a double, non-correctable error into + * the SDMMC RAM at Port B. This only injects one double bit error into the SDMMC + * RAM at Port B. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_MSB 4 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK 0x00000010 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_CLR_MSK 0xffffffef +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : SDMMC Port A RAM ECC single, correctable error interrupt status - serrporta + * + * This bit is an interrupt status bit for SDMMC Port A RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in SDMMC Port + * A RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_MSB 5 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK 0x00000020 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_CLR_MSK 0xffffffdf +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : SDMMC Port A RAM ECC double bit, non-correctable error interrupt status - derrporta + * + * This bit is an interrupt status bit for SDMMC Port A RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in SDMMC Port A RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_MSB 6 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK 0x00000040 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_CLR_MSK 0xffffffbf +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTA field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : SDMMC Port B RAM ECC single, correctable error interrupt status - serrportb + * + * This bit is an interrupt status bit for SDMMC Port B RAM ECC single, correctable + * error. It is set by hardware when single, correctable error occurs in SDMMC Port + * B RAM. Software needs to write 1 into this bit to clear the interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_MSB 7 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK 0x00000080 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_CLR_MSK 0xffffff7f +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : SDMMC Port B RAM ECC double bit, non-correctable error interrupt status - derrportb + * + * This bit is an interrupt status bit for SDMMC Port B RAM ECC double bit, non- + * correctable error. It is set by hardware when double bit, non-correctable error + * occurs in SDMMC Port B RAM. Software needs to write 1 into this bit to clear the + * interrupt status. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_MSB 8 +/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK 0x00000100 +/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_CLR_MSK 0xfffffeff +/* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_RESET 0x0 +/* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTB field value from a register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value suitable for setting the register. */ +#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET(value) (((value) << 8) & 0x00000100) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_ECC_SDMMC. + */ +struct ALT_SYSMGR_ECC_SDMMC_s +{ + uint32_t en : 1; /* SDMMC RAM ECC Enable */ + uint32_t injsporta : 1; /* SDMMC Port A RAM ECC inject single, correctable Error at Port A */ + uint32_t injdporta : 1; /* SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A */ + uint32_t injsportb : 1; /* SDMMC Port B RAM ECC inject single, correctable Error at Port B */ + uint32_t injdportb : 1; /* SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B */ + uint32_t serrporta : 1; /* SDMMC Port A RAM ECC single, correctable error interrupt status */ + uint32_t derrporta : 1; /* SDMMC Port A RAM ECC double bit, non-correctable error interrupt status */ + uint32_t serrportb : 1; /* SDMMC Port B RAM ECC single, correctable error interrupt status */ + uint32_t derrportb : 1; /* SDMMC Port B RAM ECC double bit, non-correctable error interrupt status */ + uint32_t : 23; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_ECC_SDMMC. */ +typedef volatile struct ALT_SYSMGR_ECC_SDMMC_s ALT_SYSMGR_ECC_SDMMC_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_ECC_SDMMC register from the beginning of the component. */ +#define ALT_SYSMGR_ECC_SDMMC_OFST 0x2c + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_ECC. + */ +struct ALT_SYSMGR_ECC_s +{ + volatile ALT_SYSMGR_ECC_L2_t l2; /* ALT_SYSMGR_ECC_L2 */ + volatile ALT_SYSMGR_ECC_OCRAM_t ocram; /* ALT_SYSMGR_ECC_OCRAM */ + volatile ALT_SYSMGR_ECC_USB0_t usb0; /* ALT_SYSMGR_ECC_USB0 */ + volatile ALT_SYSMGR_ECC_USB1_t usb1; /* ALT_SYSMGR_ECC_USB1 */ + volatile ALT_SYSMGR_ECC_EMAC0_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */ + volatile ALT_SYSMGR_ECC_EMAC1_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */ + volatile ALT_SYSMGR_ECC_DMA_t dma; /* ALT_SYSMGR_ECC_DMA */ + volatile ALT_SYSMGR_ECC_CAN0_t can0; /* ALT_SYSMGR_ECC_CAN0 */ + volatile ALT_SYSMGR_ECC_CAN1_t can1; /* ALT_SYSMGR_ECC_CAN1 */ + volatile ALT_SYSMGR_ECC_NAND_t nand; /* ALT_SYSMGR_ECC_NAND */ + volatile ALT_SYSMGR_ECC_QSPI_t qspi; /* ALT_SYSMGR_ECC_QSPI */ + volatile ALT_SYSMGR_ECC_SDMMC_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */ + volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_ECC. */ +typedef volatile struct ALT_SYSMGR_ECC_s ALT_SYSMGR_ECC_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ECC. */ +struct ALT_SYSMGR_ECC_raw_s +{ + volatile uint32_t l2; /* ALT_SYSMGR_ECC_L2 */ + volatile uint32_t ocram; /* ALT_SYSMGR_ECC_OCRAM */ + volatile uint32_t usb0; /* ALT_SYSMGR_ECC_USB0 */ + volatile uint32_t usb1; /* ALT_SYSMGR_ECC_USB1 */ + volatile uint32_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */ + volatile uint32_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */ + volatile uint32_t dma; /* ALT_SYSMGR_ECC_DMA */ + volatile uint32_t can0; /* ALT_SYSMGR_ECC_CAN0 */ + volatile uint32_t can1; /* ALT_SYSMGR_ECC_CAN1 */ + volatile uint32_t nand; /* ALT_SYSMGR_ECC_NAND */ + volatile uint32_t qspi; /* ALT_SYSMGR_ECC_QSPI */ + volatile uint32_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */ + volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ECC. */ +typedef volatile struct ALT_SYSMGR_ECC_raw_s ALT_SYSMGR_ECC_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Pin Mux Control Group - ALT_SYSMGR_PINMUX + * Pin Mux Control Group + * + * Controls Pin Mux selections + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + */ +/* + * Register : emac0_tx_clk Mux Selection Register - EMACIO0 + * + * This register is used to control the peripherals connected to emac0_tx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 0. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO0. + */ +struct ALT_SYSMGR_PINMUX_EMACIO0_s +{ + uint32_t sel : 2; /* emac0_tx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO0_s ALT_SYSMGR_PINMUX_EMACIO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_OFST 0x0 + +/* + * Register : emac0_tx_d0 Mux Selection Register - EMACIO1 + * + * This register is used to control the peripherals connected to emac0_tx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 1. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D0. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO1. + */ +struct ALT_SYSMGR_PINMUX_EMACIO1_s +{ + uint32_t sel : 2; /* emac0_tx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO1_s ALT_SYSMGR_PINMUX_EMACIO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_OFST 0x4 + +/* + * Register : emac0_tx_d1 Mux Selection Register - EMACIO2 + * + * This register is used to control the peripherals connected to emac0_tx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 2. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D1. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO2. + */ +struct ALT_SYSMGR_PINMUX_EMACIO2_s +{ + uint32_t sel : 2; /* emac0_tx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO2_s ALT_SYSMGR_PINMUX_EMACIO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_OFST 0x8 + +/* + * Register : emac0_tx_d2 Mux Selection Register - EMACIO3 + * + * This register is used to control the peripherals connected to emac0_tx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 3. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D2. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO3. + */ +struct ALT_SYSMGR_PINMUX_EMACIO3_s +{ + uint32_t sel : 2; /* emac0_tx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO3_s ALT_SYSMGR_PINMUX_EMACIO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_OFST 0xc + +/* + * Register : emac0_tx_d3 Mux Selection Register - EMACIO4 + * + * This register is used to control the peripherals connected to emac0_tx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 4. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D3. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO4. + */ +struct ALT_SYSMGR_PINMUX_EMACIO4_s +{ + uint32_t sel : 2; /* emac0_tx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO4_s ALT_SYSMGR_PINMUX_EMACIO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_OFST 0x10 + +/* + * Register : emac0_rx_d0 Mux Selection Register - EMACIO5 + * + * This register is used to control the peripherals connected to emac0_rx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 5. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D4. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO5. + */ +struct ALT_SYSMGR_PINMUX_EMACIO5_s +{ + uint32_t sel : 2; /* emac0_rx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO5_s ALT_SYSMGR_PINMUX_EMACIO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_OFST 0x14 + +/* + * Register : emac0_mdio Mux Selection Register - EMACIO6 + * + * This register is used to control the peripherals connected to emac0_mdio + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | emac0_mdio Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_mdio Mux Selection Field - sel + * + * Select peripheral signals connected emac0_mdio. + * + * 0 : Pin is connected to GPIO/LoanIO number 6. + * + * 1 : Pin is connected to Peripheral signal I2C2.SDA. + * + * 2 : Pin is connected to Peripheral signal USB1.D5. + * + * 3 : Pin is connected to Peripheral signal RGMII0.MDIO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO6. + */ +struct ALT_SYSMGR_PINMUX_EMACIO6_s +{ + uint32_t sel : 2; /* emac0_mdio Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO6_s ALT_SYSMGR_PINMUX_EMACIO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_OFST 0x18 + +/* + * Register : emac0_mdc Mux Selection Register - EMACIO7 + * + * This register is used to control the peripherals connected to emac0_mdc + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | emac0_mdc Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_mdc Mux Selection Field - sel + * + * Select peripheral signals connected emac0_mdc. + * + * 0 : Pin is connected to GPIO/LoanIO number 7. + * + * 1 : Pin is connected to Peripheral signal I2C2.SCL. + * + * 2 : Pin is connected to Peripheral signal USB1.D6. + * + * 3 : Pin is connected to Peripheral signal RGMII0.MDC. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO7. + */ +struct ALT_SYSMGR_PINMUX_EMACIO7_s +{ + uint32_t sel : 2; /* emac0_mdc Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO7_s ALT_SYSMGR_PINMUX_EMACIO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_OFST 0x1c + +/* + * Register : emac0_rx_ctl Mux Selection Register - EMACIO8 + * + * This register is used to control the peripherals connected to emac0_rx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 8. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.D7. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO8. + */ +struct ALT_SYSMGR_PINMUX_EMACIO8_s +{ + uint32_t sel : 2; /* emac0_rx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO8_s ALT_SYSMGR_PINMUX_EMACIO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_OFST 0x20 + +/* + * Register : emac0_tx_ctl Mux Selection Register - EMACIO9 + * + * This register is used to control the peripherals connected to emac0_tx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_tx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_tx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac0_tx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 9. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII0.TX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO9. + */ +struct ALT_SYSMGR_PINMUX_EMACIO9_s +{ + uint32_t sel : 2; /* emac0_tx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO9_s ALT_SYSMGR_PINMUX_EMACIO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_OFST 0x24 + +/* + * Register : emac0_rx_clk Mux Selection Register - EMACIO10 + * + * This register is used to control the peripherals connected to emac0_rx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 10. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.CLK. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO10. + */ +struct ALT_SYSMGR_PINMUX_EMACIO10_s +{ + uint32_t sel : 2; /* emac0_rx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO10_s ALT_SYSMGR_PINMUX_EMACIO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_OFST 0x28 + +/* + * Register : emac0_rx_d1 Mux Selection Register - EMACIO11 + * + * This register is used to control the peripherals connected to emac0_rx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 11. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.STP. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO11. + */ +struct ALT_SYSMGR_PINMUX_EMACIO11_s +{ + uint32_t sel : 2; /* emac0_rx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO11_s ALT_SYSMGR_PINMUX_EMACIO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_OFST 0x2c + +/* + * Register : emac0_rx_d2 Mux Selection Register - EMACIO12 + * + * This register is used to control the peripherals connected to emac0_rx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 12. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.DIR. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO12. + */ +struct ALT_SYSMGR_PINMUX_EMACIO12_s +{ + uint32_t sel : 2; /* emac0_rx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO12_s ALT_SYSMGR_PINMUX_EMACIO12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_OFST 0x30 + +/* + * Register : emac0_rx_d3 Mux Selection Register - EMACIO13 + * + * This register is used to control the peripherals connected to emac0_rx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac0_rx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac0_rx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac0_rx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 13. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB1.NXT. + * + * 3 : Pin is connected to Peripheral signal RGMII0.RXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO13. + */ +struct ALT_SYSMGR_PINMUX_EMACIO13_s +{ + uint32_t sel : 2; /* emac0_rx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO13_s ALT_SYSMGR_PINMUX_EMACIO13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_OFST 0x34 + +/* + * Register : emac1_tx_clk Mux Selection Register - EMACIO14 + * + * This register is used to control the peripherals connected to emac1_tx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 48. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO14. + */ +struct ALT_SYSMGR_PINMUX_EMACIO14_s +{ + uint32_t sel : 2; /* emac1_tx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO14_s ALT_SYSMGR_PINMUX_EMACIO14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_OFST 0x38 + +/* + * Register : emac1_tx_d0 Mux Selection Register - EMACIO15 + * + * This register is used to control the peripherals connected to emac1_tx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 49. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO15. + */ +struct ALT_SYSMGR_PINMUX_EMACIO15_s +{ + uint32_t sel : 2; /* emac1_tx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO15_s ALT_SYSMGR_PINMUX_EMACIO15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_OFST 0x3c + +/* + * Register : emac1_tx_d1 Mux Selection Register - EMACIO16 + * + * This register is used to control the peripherals connected to emac1_tx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 50. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO16. + */ +struct ALT_SYSMGR_PINMUX_EMACIO16_s +{ + uint32_t sel : 2; /* emac1_tx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO16_s ALT_SYSMGR_PINMUX_EMACIO16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_OFST 0x40 + +/* + * Register : emac1_tx_ctl Mux Selection Register - EMACIO17 + * + * This register is used to control the peripherals connected to emac1_tx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 51. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO17. + */ +struct ALT_SYSMGR_PINMUX_EMACIO17_s +{ + uint32_t sel : 2; /* emac1_tx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO17_s ALT_SYSMGR_PINMUX_EMACIO17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_OFST 0x44 + +/* + * Register : emac1_rx_d0 Mux Selection Register - EMACIO18 + * + * This register is used to control the peripherals connected to emac1_rx_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d0 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 52. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO18. + */ +struct ALT_SYSMGR_PINMUX_EMACIO18_s +{ + uint32_t sel : 2; /* emac1_rx_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO18_s ALT_SYSMGR_PINMUX_EMACIO18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_OFST 0x48 + +/* + * Register : emac1_rx_d1 Mux Selection Register - EMACIO19 + * + * This register is used to control the peripherals connected to emac1_rx_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d1 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 53. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_EMACIO19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO19. + */ +struct ALT_SYSMGR_PINMUX_EMACIO19_s +{ + uint32_t sel : 2; /* emac1_rx_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO19_s ALT_SYSMGR_PINMUX_EMACIO19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_OFST 0x4c + +/* + * Register : sdmmc_cmd Mux Selection Register - FLASHIO0 + * + * This register is used to control the peripherals connected to sdmmc_cmd + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | sdmmc_cmd Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_cmd Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_cmd. + * + * 0 : Pin is connected to GPIO/LoanIO number 36. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D0. + * + * 3 : Pin is connected to Peripheral signal SDMMC.CMD. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO0. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO0_s +{ + uint32_t sel : 2; /* sdmmc_cmd Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO0_s ALT_SYSMGR_PINMUX_FLSHIO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_OFST 0x50 + +/* + * Register : sdmmc_pwren Mux Selection Register - FLASHIO1 + * + * This register is used to control the peripherals connected to sdmmc_pwren + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | sdmmc_pwren Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_pwren Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_pwren. + * + * 0 : Pin is connected to GPIO/LoanIO number 37. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D1. + * + * 3 : Pin is connected to Peripheral signal SDMMC.PWREN. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO1. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO1_s +{ + uint32_t sel : 2; /* sdmmc_pwren Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO1_s ALT_SYSMGR_PINMUX_FLSHIO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_OFST 0x54 + +/* + * Register : sdmmc_d0 Mux Selection Register - FLASHIO2 + * + * This register is used to control the peripherals connected to sdmmc_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d0 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 38. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D2. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO2. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO2_s +{ + uint32_t sel : 2; /* sdmmc_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO2_s ALT_SYSMGR_PINMUX_FLSHIO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_OFST 0x58 + +/* + * Register : sdmmc_d1 Mux Selection Register - FLASHIO3 + * + * This register is used to control the peripherals connected to sdmmc_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d1 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 39. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D3. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO3. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO3_s +{ + uint32_t sel : 2; /* sdmmc_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO3_s ALT_SYSMGR_PINMUX_FLSHIO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_OFST 0x5c + +/* + * Register : sdmmc_d4 Mux Selection Register - FLASHIO4 + * + * This register is used to control the peripherals connected to sdmmc_d4 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d4 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d4 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d4. + * + * 0 : Pin is connected to GPIO/LoanIO number 40. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D4. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO4. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO4_s +{ + uint32_t sel : 2; /* sdmmc_d4 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO4_s ALT_SYSMGR_PINMUX_FLSHIO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_OFST 0x60 + +/* + * Register : sdmmc_d5 Mux Selection Register - FLASHIO5 + * + * This register is used to control the peripherals connected to sdmmc_d5 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d5 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d5 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d5. + * + * 0 : Pin is connected to GPIO/LoanIO number 41. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D5. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO5. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO5_s +{ + uint32_t sel : 2; /* sdmmc_d5 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO5_s ALT_SYSMGR_PINMUX_FLSHIO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_OFST 0x64 + +/* + * Register : sdmmc_d6 Mux Selection Register - FLASHIO6 + * + * This register is used to control the peripherals connected to sdmmc_d6 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d6 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d6 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d6. + * + * 0 : Pin is connected to GPIO/LoanIO number 42. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D6. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO6. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO6_s +{ + uint32_t sel : 2; /* sdmmc_d6 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO6_s ALT_SYSMGR_PINMUX_FLSHIO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_OFST 0x68 + +/* + * Register : sdmmc_d7 Mux Selection Register - FLASHIO7 + * + * This register is used to control the peripherals connected to sdmmc_d7 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d7 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d7 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d7. + * + * 0 : Pin is connected to GPIO/LoanIO number 43. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.D7. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO7. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO7_s +{ + uint32_t sel : 2; /* sdmmc_d7 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO7_s ALT_SYSMGR_PINMUX_FLSHIO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_OFST 0x6c + +/* + * Register : sdmmc_clk_in Mux Selection Register - FLASHIO8 + * + * This register is used to control the peripherals connected to sdmmc_clk_in + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | sdmmc_clk_in Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_clk_in Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_clk_in. + * + * 0 : Pin is connected to GPIO/LoanIO number 44. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.CLK. + * + * 3 : Pin is connected to Peripheral signal SDMMC.CLK_IN. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO8. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO8_s +{ + uint32_t sel : 2; /* sdmmc_clk_in Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO8_s ALT_SYSMGR_PINMUX_FLSHIO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_OFST 0x70 + +/* + * Register : sdmmc_clk Mux Selection Register - FLASHIO9 + * + * This register is used to control the peripherals connected to sdmmc_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | sdmmc_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_clk Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 45. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.STP. + * + * 3 : Pin is connected to Peripheral signal SDMMC.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO9. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO9_s +{ + uint32_t sel : 2; /* sdmmc_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO9_s ALT_SYSMGR_PINMUX_FLSHIO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_OFST 0x74 + +/* + * Register : sdmmc_d2 Mux Selection Register - FLASHIO10 + * + * This register is used to control the peripherals connected to sdmmc_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d2 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 46. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.DIR. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO10. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO10_s +{ + uint32_t sel : 2; /* sdmmc_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO10_s ALT_SYSMGR_PINMUX_FLSHIO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_OFST 0x78 + +/* + * Register : sdmmc_d3 Mux Selection Register - FLASHIO11 + * + * This register is used to control the peripherals connected to sdmmc_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | sdmmc_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : sdmmc_d3 Mux Selection Field - sel + * + * Select peripheral signals connected sdmmc_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 47. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal USB0.NXT. + * + * 3 : Pin is connected to Peripheral signal SDMMC.D3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO11. + */ +struct ALT_SYSMGR_PINMUX_FLSHIO11_s +{ + uint32_t sel : 2; /* sdmmc_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO11_s ALT_SYSMGR_PINMUX_FLSHIO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_OFST 0x7c + +/* + * Register : trace_clk Mux Selection Register - GENERALIO0 + * + * This register is used to control the peripherals connected to trace_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | trace_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_clk Mux Selection Field - sel + * + * Select peripheral signals connected trace_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 48. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal TRACE.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO0. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO0_s +{ + uint32_t sel : 2; /* trace_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO0_s ALT_SYSMGR_PINMUX_GENERALIO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_OFST 0x80 + +/* + * Register : trace_d0 Mux Selection Register - GENERALIO1 + * + * This register is used to control the peripherals connected to trace_d0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d0 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d0. + * + * 0 : Pin is connected to GPIO/LoanIO number 49. + * + * 1 : Pin is connected to Peripheral signal UART0.RX. + * + * 2 : Pin is connected to Peripheral signal SPIS0.CLK. + * + * 3 : Pin is connected to Peripheral signal TRACE.D0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO1. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO1_s +{ + uint32_t sel : 2; /* trace_d0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO1_s ALT_SYSMGR_PINMUX_GENERALIO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_OFST 0x84 + +/* + * Register : trace_d1 Mux Selection Register - GENERALIO2 + * + * This register is used to control the peripherals connected to trace_d1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d1 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d1. + * + * 0 : Pin is connected to GPIO/LoanIO number 50. + * + * 1 : Pin is connected to Peripheral signal UART0.TX. + * + * 2 : Pin is connected to Peripheral signal SPIS0.MOSI. + * + * 3 : Pin is connected to Peripheral signal TRACE.D1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO2. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO2_s +{ + uint32_t sel : 2; /* trace_d1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO2_s ALT_SYSMGR_PINMUX_GENERALIO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_OFST 0x88 + +/* + * Register : trace_d2 Mux Selection Register - GENERALIO3 + * + * This register is used to control the peripherals connected to trace_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d2 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 51. + * + * 1 : Pin is connected to Peripheral signal I2C1.SDA. + * + * 2 : Pin is connected to Peripheral signal SPIS0.MISO. + * + * 3 : Pin is connected to Peripheral signal TRACE.D2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO3. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO3_s +{ + uint32_t sel : 2; /* trace_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO3_s ALT_SYSMGR_PINMUX_GENERALIO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_OFST 0x8c + +/* + * Register : trace_d3 Mux Selection Register - GENERALIO4 + * + * This register is used to control the peripherals connected to trace_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d3 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 52. + * + * 1 : Pin is connected to Peripheral signal I2C1.SCL. + * + * 2 : Pin is connected to Peripheral signal SPIS0.SS0. + * + * 3 : Pin is connected to Peripheral signal TRACE.D3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO4. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO4_s +{ + uint32_t sel : 2; /* trace_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO4_s ALT_SYSMGR_PINMUX_GENERALIO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_OFST 0x90 + +/* + * Register : trace_d4 Mux Selection Register - GENERALIO5 + * + * This register is used to control the peripherals connected to trace_d4 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d4 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d4 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d4. + * + * 0 : Pin is connected to GPIO/LoanIO number 53. + * + * 1 : Pin is connected to Peripheral signal CAN1.RX. + * + * 2 : Pin is connected to Peripheral signal SPIS1.CLK. + * + * 3 : Pin is connected to Peripheral signal TRACE.D4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO5. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO5_s +{ + uint32_t sel : 2; /* trace_d4 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO5_s ALT_SYSMGR_PINMUX_GENERALIO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_OFST 0x94 + +/* + * Register : trace_d5 Mux Selection Register - GENERALIO6 + * + * This register is used to control the peripherals connected to trace_d5 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d5 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d5 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d5. + * + * 0 : Pin is connected to GPIO/LoanIO number 54. + * + * 1 : Pin is connected to Peripheral signal CAN1.TX. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MOSI. + * + * 3 : Pin is connected to Peripheral signal TRACE.D5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO6. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO6_s +{ + uint32_t sel : 2; /* trace_d5 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO6_s ALT_SYSMGR_PINMUX_GENERALIO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_OFST 0x98 + +/* + * Register : trace_d6 Mux Selection Register - GENERALIO7 + * + * This register is used to control the peripherals connected to trace_d6 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d6 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d6 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d6. + * + * 0 : Pin is connected to GPIO/LoanIO number 55. + * + * 1 : Pin is connected to Peripheral signal I2C0.SDA. + * + * 2 : Pin is connected to Peripheral signal SPIS1.SS0. + * + * 3 : Pin is connected to Peripheral signal TRACE.D6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO7. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO7_s +{ + uint32_t sel : 2; /* trace_d6 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO7_s ALT_SYSMGR_PINMUX_GENERALIO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_OFST 0x9c + +/* + * Register : trace_d7 Mux Selection Register - GENERALIO8 + * + * This register is used to control the peripherals connected to trace_d7 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | trace_d7 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : trace_d7 Mux Selection Field - sel + * + * Select peripheral signals connected trace_d7. + * + * 0 : Pin is connected to GPIO/LoanIO number 56. + * + * 1 : Pin is connected to Peripheral signal I2C0.SCL. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MISO. + * + * 3 : Pin is connected to Peripheral signal TRACE.D7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO8. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO8_s +{ + uint32_t sel : 2; /* trace_d7 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO8_s ALT_SYSMGR_PINMUX_GENERALIO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_OFST 0xa0 + +/* + * Register : spim0_clk Mux Selection Register - GENERALIO9 + * + * This register is used to control the peripherals connected to spim0_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spim0_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_clk Mux Selection Field - sel + * + * Select peripheral signals connected spim0_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 57. + * + * 1 : Pin is connected to Peripheral signal UART0.CTS. + * + * 2 : Pin is connected to Peripheral signal I2C1.SDA. + * + * 3 : Pin is connected to Peripheral signal SPIM0.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO9. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO9_s +{ + uint32_t sel : 2; /* spim0_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO9_s ALT_SYSMGR_PINMUX_GENERALIO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_OFST 0xa4 + +/* + * Register : spim0_mosi Mux Selection Register - GENERALIO10 + * + * This register is used to control the peripherals connected to spim0_mosi + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spim0_mosi Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_mosi Mux Selection Field - sel + * + * Select peripheral signals connected spim0_mosi. + * + * 0 : Pin is connected to GPIO/LoanIO number 58. + * + * 1 : Pin is connected to Peripheral signal UART0.RTS. + * + * 2 : Pin is connected to Peripheral signal I2C1.SCL. + * + * 3 : Pin is connected to Peripheral signal SPIM0.MOSI. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO10. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO10_s +{ + uint32_t sel : 2; /* spim0_mosi Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO10_s ALT_SYSMGR_PINMUX_GENERALIO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_OFST 0xa8 + +/* + * Register : spim0_miso Mux Selection Register - GENERALIO11 + * + * This register is used to control the peripherals connected to spim0_miso + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spim0_miso Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_miso Mux Selection Field - sel + * + * Select peripheral signals connected spim0_miso. + * + * 0 : Pin is connected to GPIO/LoanIO number 59. + * + * 1 : Pin is connected to Peripheral signal UART1.CTS. + * + * 2 : Pin is connected to Peripheral signal CAN1.RX. + * + * 3 : Pin is connected to Peripheral signal SPIM0.MISO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO11. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO11_s +{ + uint32_t sel : 2; /* spim0_miso Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO11_s ALT_SYSMGR_PINMUX_GENERALIO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_OFST 0xac + +/* + * Register : spim0_ss0 Mux Selection Register - GENERALIO12 + * + * This register is used to control the peripherals connected to spim0_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spim0_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected spim0_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 60. + * + * 1 : Pin is connected to Peripheral signal UART1.RTS. + * + * 2 : Pin is connected to Peripheral signal CAN1.TX. + * + * 3 : Pin is connected to Peripheral signal SPIM0.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO12. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO12_s +{ + uint32_t sel : 2; /* spim0_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO12_s ALT_SYSMGR_PINMUX_GENERALIO12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_OFST 0xb0 + +/* + * Register : uart0_rx Mux Selection Register - GENERALIO13 + * + * This register is used to control the peripherals connected to uart0_rx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart0_rx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart0_rx Mux Selection Field - sel + * + * Select peripheral signals connected uart0_rx. + * + * 0 : Pin is connected to GPIO/LoanIO number 61. + * + * 1 : Pin is connected to Peripheral signal SPIM0.SS1. + * + * 2 : Pin is connected to Peripheral signal CAN0.RX. + * + * 3 : Pin is connected to Peripheral signal UART0.RX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO13. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO13_s +{ + uint32_t sel : 2; /* uart0_rx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO13_s ALT_SYSMGR_PINMUX_GENERALIO13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_OFST 0xb4 + +/* + * Register : uart0_tx Mux Selection Register - GENERALIO14 + * + * This register is used to control the peripherals connected to uart0_tx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart0_tx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart0_tx Mux Selection Field - sel + * + * Select peripheral signals connected uart0_tx. + * + * 0 : Pin is connected to GPIO/LoanIO number 62. + * + * 1 : Pin is connected to Peripheral signal SPIM1.SS1. + * + * 2 : Pin is connected to Peripheral signal CAN0.TX. + * + * 3 : Pin is connected to Peripheral signal UART0.TX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO14. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO14_s +{ + uint32_t sel : 2; /* uart0_tx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO14_s ALT_SYSMGR_PINMUX_GENERALIO14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_OFST 0xb8 + +/* + * Register : i2c0_sda Mux Selection Register - GENERALIO15 + * + * This register is used to control the peripherals connected to i2c0_sda + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c0_sda Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c0_sda Mux Selection Field - sel + * + * Select peripheral signals connected i2c0_sda. + * + * 0 : Pin is connected to GPIO/LoanIO number 63. + * + * 1 : Pin is connected to Peripheral signal SPIM1.CLK. + * + * 2 : Pin is connected to Peripheral signal UART1.RX. + * + * 3 : Pin is connected to Peripheral signal I2C0.SDA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO15. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO15_s +{ + uint32_t sel : 2; /* i2c0_sda Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO15_s ALT_SYSMGR_PINMUX_GENERALIO15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_OFST 0xbc + +/* + * Register : i2c0_scl Mux Selection Register - GENERALIO16 + * + * This register is used to control the peripherals connected to i2c0_scl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c0_scl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c0_scl Mux Selection Field - sel + * + * Select peripheral signals connected i2c0_scl. + * + * 0 : Pin is connected to GPIO/LoanIO number 64. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MOSI. + * + * 2 : Pin is connected to Peripheral signal UART1.TX. + * + * 3 : Pin is connected to Peripheral signal I2C0.SCL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO16. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO16_s +{ + uint32_t sel : 2; /* i2c0_scl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO16_s ALT_SYSMGR_PINMUX_GENERALIO16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_OFST 0xc0 + +/* + * Register : can0_rx Mux Selection Register - GENERALIO17 + * + * This register is used to control the peripherals connected to can0_rx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | can0_rx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : can0_rx Mux Selection Field - sel + * + * Select peripheral signals connected can0_rx. + * + * 0 : Pin is connected to GPIO/LoanIO number 65. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MISO. + * + * 2 : Pin is connected to Peripheral signal UART0.RX. + * + * 3 : Pin is connected to Peripheral signal CAN0.RX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO17. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO17_s +{ + uint32_t sel : 2; /* can0_rx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO17_s ALT_SYSMGR_PINMUX_GENERALIO17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_OFST 0xc4 + +/* + * Register : can0_tx Mux Selection Register - GENERALIO18 + * + * This register is used to control the peripherals connected to can0_tx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | can0_tx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : can0_tx Mux Selection Field - sel + * + * Select peripheral signals connected can0_tx. + * + * 0 : Pin is connected to GPIO/LoanIO number 66. + * + * 1 : Pin is connected to Peripheral signal SPIM1.SS0. + * + * 2 : Pin is connected to Peripheral signal UART0.TX. + * + * 3 : Pin is connected to Peripheral signal CAN0.TX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO18. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO18_s +{ + uint32_t sel : 2; /* can0_tx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO18_s ALT_SYSMGR_PINMUX_GENERALIO18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_OFST 0xc8 + +/* + * Register : spis1_clk Mux Selection Register - GENERALIO19 + * + * This register is used to control the peripherals connected to spis1_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis1_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_clk Mux Selection Field - sel + * + * Select peripheral signals connected spis1_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 67. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.CLK. + * + * 3 : Pin is connected to Peripheral signal SPIS1.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO19. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO19_s +{ + uint32_t sel : 2; /* spis1_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO19_s ALT_SYSMGR_PINMUX_GENERALIO19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_OFST 0xcc + +/* + * Register : spis1_mosi Mux Selection Register - GENERALIO20 + * + * This register is used to control the peripherals connected to spis1_mosi + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis1_mosi Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_mosi Mux Selection Field - sel + * + * Select peripheral signals connected spis1_mosi. + * + * 0 : Pin is connected to GPIO/LoanIO number 68. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.MOSI. + * + * 3 : Pin is connected to Peripheral signal SPIS1.MOSI. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO20_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO20. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO20_s +{ + uint32_t sel : 2; /* spis1_mosi Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO20. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO20_s ALT_SYSMGR_PINMUX_GENERALIO20_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO20 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_OFST 0xd0 + +/* + * Register : spis1_miso Mux Selection Register - GENERALIO21 + * + * This register is used to control the peripherals connected to spis1_miso + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis1_miso Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_miso Mux Selection Field - sel + * + * Select peripheral signals connected spis1_miso. + * + * 0 : Pin is connected to GPIO/LoanIO number 69. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.MISO. + * + * 3 : Pin is connected to Peripheral signal SPIS1.MISO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO21_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO21. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO21_s +{ + uint32_t sel : 2; /* spis1_miso Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO21. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO21_s ALT_SYSMGR_PINMUX_GENERALIO21_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO21 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_OFST 0xd4 + +/* + * Register : spis1_ss0 Mux Selection Register - GENERALIO22 + * + * This register is used to control the peripherals connected to spis1_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis1_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis1_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected spis1_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 70. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.SS0. + * + * 3 : Pin is connected to Peripheral signal SPIS1.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO22_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO22. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO22_s +{ + uint32_t sel : 2; /* spis1_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO22. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO22_s ALT_SYSMGR_PINMUX_GENERALIO22_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO22 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_OFST 0xd8 + +/* + * Register : uart1_rx Mux Selection Register - GENERALIO23 + * + * This register is used to control the peripherals connected to uart1_rx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart1_rx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart1_rx Mux Selection Field - sel + * + * Select peripheral signals connected uart1_rx. + * + * 0 : Pin is connected to GPIO/LoanIO number 62. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM1.SS1. + * + * 3 : Pin is connected to Peripheral signal UART1.RX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO23_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO23. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO23_s +{ + uint32_t sel : 2; /* uart1_rx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO23. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO23_s ALT_SYSMGR_PINMUX_GENERALIO23_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO23 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_OFST 0xdc + +/* + * Register : uart1_tx Mux Selection Register - GENERALIO24 + * + * This register is used to control the peripherals connected to uart1_tx + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | uart1_tx Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : uart1_tx Mux Selection Field - sel + * + * Select peripheral signals connected uart1_tx. + * + * 0 : Pin is connected to GPIO/LoanIO number 63. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.CLK. + * + * 3 : Pin is connected to Peripheral signal UART1.TX. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO24_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO24. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO24_s +{ + uint32_t sel : 2; /* uart1_tx Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO24. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO24_s ALT_SYSMGR_PINMUX_GENERALIO24_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO24 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_OFST 0xe0 + +/* + * Register : i2c1_sda Mux Selection Register - GENERALIO25 + * + * This register is used to control the peripherals connected to i2c1_sda + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c1_sda Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c1_sda Mux Selection Field - sel + * + * Select peripheral signals connected i2c1_sda. + * + * 0 : Pin is connected to GPIO/LoanIO number 64. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MOSI. + * + * 3 : Pin is connected to Peripheral signal I2C1.SDA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO25_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO25. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO25_s +{ + uint32_t sel : 2; /* i2c1_sda Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO25. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO25_s ALT_SYSMGR_PINMUX_GENERALIO25_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO25 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_OFST 0xe4 + +/* + * Register : i2c1_scl Mux Selection Register - GENERALIO26 + * + * This register is used to control the peripherals connected to i2c1_scl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | i2c1_scl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : i2c1_scl Mux Selection Field - sel + * + * Select peripheral signals connected i2c1_scl. + * + * 0 : Pin is connected to GPIO/LoanIO number 65. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MISO. + * + * 3 : Pin is connected to Peripheral signal I2C1.SCL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO26_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO26. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO26_s +{ + uint32_t sel : 2; /* i2c1_scl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO26. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO26_s ALT_SYSMGR_PINMUX_GENERALIO26_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO26 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_OFST 0xe8 + +/* + * Register : spim0_ss0_alt Mux Selection Register - GENERALIO27 + * + * This register is used to control the peripherals connected to spim0_ss0_alt + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [1:0] | RW | 0x0 | spim0_ss0_alt Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spim0_ss0_alt Mux Selection Field - sel + * + * Select peripheral signals connected spim0_ss0_alt. + * + * 0 : Pin is connected to GPIO/LoanIO number 66. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.SS0. + * + * 3 : Pin is connected to Peripheral signal not applicable. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO27_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO27. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO27_s +{ + uint32_t sel : 2; /* spim0_ss0_alt Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO27. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO27_s ALT_SYSMGR_PINMUX_GENERALIO27_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO27 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_OFST 0xec + +/* + * Register : spis0_clk Mux Selection Register - GENERALIO28 + * + * This register is used to control the peripherals connected to spis0_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis0_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_clk Mux Selection Field - sel + * + * Select peripheral signals connected spis0_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 67. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal SPIM0.SS1. + * + * 3 : Pin is connected to Peripheral signal SPIS0.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO28_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO28. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO28_s +{ + uint32_t sel : 2; /* spis0_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO28. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO28_s ALT_SYSMGR_PINMUX_GENERALIO28_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO28 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_OFST 0xf0 + +/* + * Register : spis0_mosi Mux Selection Register - GENERALIO29 + * + * This register is used to control the peripherals connected to spis0_mosi + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis0_mosi Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_mosi Mux Selection Field - sel + * + * Select peripheral signals connected spis0_mosi. + * + * 0 : Pin is connected to GPIO/LoanIO number 68. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal SPIS0.MOSI. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO29_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO29. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO29_s +{ + uint32_t sel : 2; /* spis0_mosi Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO29. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO29_s ALT_SYSMGR_PINMUX_GENERALIO29_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO29 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_OFST 0xf4 + +/* + * Register : spis0_miso Mux Selection Register - GENERALIO30 + * + * This register is used to control the peripherals connected to spis0_miso + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | spis0_miso Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_miso Mux Selection Field - sel + * + * Select peripheral signals connected spis0_miso. + * + * 0 : Pin is connected to GPIO/LoanIO number 69. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal SPIS0.MISO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO30_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO30. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO30_s +{ + uint32_t sel : 2; /* spis0_miso Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO30. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO30_s ALT_SYSMGR_PINMUX_GENERALIO30_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO30 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_OFST 0xf8 + +/* + * Register : spis0_ss0 Mux Selection Register - GENERALIO31 + * + * This register is used to control the peripherals connected to spis0_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | spis0_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : spis0_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected spis0_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 70. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal SPIS0.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO31_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO31. + */ +struct ALT_SYSMGR_PINMUX_GENERALIO31_s +{ + uint32_t sel : 2; /* spis0_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO31. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO31_s ALT_SYSMGR_PINMUX_GENERALIO31_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO31 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_OFST 0xfc + +/* + * Register : nand_ale Mux Selection Register - MIXED1IO0 + * + * This register is used to control the peripherals connected to nand_ale + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_ale Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_ale Mux Selection Field - sel + * + * Select peripheral signals connected nand_ale. + * + * 0 : Pin is connected to GPIO/LoanIO number 14. + * + * 1 : Pin is connected to Peripheral signal QSPI.SS3. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TX_CLK. + * + * 3 : Pin is connected to Peripheral signal NAND.ale. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO0_s +{ + uint32_t sel : 2; /* nand_ale Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO0_s ALT_SYSMGR_PINMUX_MIXED1IO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_OFST 0x100 + +/* + * Register : nand_ce Mux Selection Register - MIXED1IO1 + * + * This register is used to control the peripherals connected to nand_ce + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_ce Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_ce Mux Selection Field - sel + * + * Select peripheral signals connected nand_ce. + * + * 0 : Pin is connected to GPIO/LoanIO number 15. + * + * 1 : Pin is connected to Peripheral signal USB1.D0. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD0. + * + * 3 : Pin is connected to Peripheral signal NAND.ce. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO1_s +{ + uint32_t sel : 2; /* nand_ce Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO1_s ALT_SYSMGR_PINMUX_MIXED1IO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_OFST 0x104 + +/* + * Register : nand_cle Mux Selection Register - MIXED1IO2 + * + * This register is used to control the peripherals connected to nand_cle + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_cle Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_cle Mux Selection Field - sel + * + * Select peripheral signals connected nand_cle. + * + * 0 : Pin is connected to GPIO/LoanIO number 16. + * + * 1 : Pin is connected to Peripheral signal USB1.D1. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD1. + * + * 3 : Pin is connected to Peripheral signal NAND.cle. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO2_s +{ + uint32_t sel : 2; /* nand_cle Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO2_s ALT_SYSMGR_PINMUX_MIXED1IO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_OFST 0x108 + +/* + * Register : nand_re Mux Selection Register - MIXED1IO3 + * + * This register is used to control the peripherals connected to nand_re + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_re Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_re Mux Selection Field - sel + * + * Select peripheral signals connected nand_re. + * + * 0 : Pin is connected to GPIO/LoanIO number 17. + * + * 1 : Pin is connected to Peripheral signal USB1.D2. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD2. + * + * 3 : Pin is connected to Peripheral signal NAND.re. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO3_s +{ + uint32_t sel : 2; /* nand_re Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO3_s ALT_SYSMGR_PINMUX_MIXED1IO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_OFST 0x10c + +/* + * Register : nand_rb Mux Selection Register - MIXED1IO4 + * + * This register is used to control the peripherals connected to nand_rb + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_rb Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_rb Mux Selection Field - sel + * + * Select peripheral signals connected nand_rb. + * + * 0 : Pin is connected to GPIO/LoanIO number 18. + * + * 1 : Pin is connected to Peripheral signal USB1.D3. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TXD3. + * + * 3 : Pin is connected to Peripheral signal NAND.rb. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO4_s +{ + uint32_t sel : 2; /* nand_rb Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO4_s ALT_SYSMGR_PINMUX_MIXED1IO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_OFST 0x110 + +/* + * Register : nand_dq0 Mux Selection Register - MIXED1IO5 + * + * This register is used to control the peripherals connected to nand_dq0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq0 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq0. + * + * 0 : Pin is connected to GPIO/LoanIO number 19. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD0. + * + * 3 : Pin is connected to Peripheral signal NAND.dq0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO5_s +{ + uint32_t sel : 2; /* nand_dq0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO5_s ALT_SYSMGR_PINMUX_MIXED1IO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_OFST 0x114 + +/* + * Register : nand_dq1 Mux Selection Register - MIXED1IO6 + * + * This register is used to control the peripherals connected to nand_dq1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq1 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq1. + * + * 0 : Pin is connected to GPIO/LoanIO number 20. + * + * 1 : Pin is connected to Peripheral signal I2C3.SDA. + * + * 2 : Pin is connected to Peripheral signal RGMII1.MDIO. + * + * 3 : Pin is connected to Peripheral signal NAND.dq1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO6_s +{ + uint32_t sel : 2; /* nand_dq1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO6_s ALT_SYSMGR_PINMUX_MIXED1IO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_OFST 0x118 + +/* + * Register : nand_dq2 Mux Selection Register - MIXED1IO7 + * + * This register is used to control the peripherals connected to nand_dq2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq2 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq2. + * + * 0 : Pin is connected to GPIO/LoanIO number 21. + * + * 1 : Pin is connected to Peripheral signal I2C3.SCL. + * + * 2 : Pin is connected to Peripheral signal RGMII1.MDC. + * + * 3 : Pin is connected to Peripheral signal NAND.dq2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO7_s +{ + uint32_t sel : 2; /* nand_dq2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO7_s ALT_SYSMGR_PINMUX_MIXED1IO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_OFST 0x11c + +/* + * Register : nand_dq3 Mux Selection Register - MIXED1IO8 + * + * This register is used to control the peripherals connected to nand_dq3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq3 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq3. + * + * 0 : Pin is connected to GPIO/LoanIO number 22. + * + * 1 : Pin is connected to Peripheral signal USB1.D4. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RX_CTL. + * + * 3 : Pin is connected to Peripheral signal NAND.dq3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO8_s +{ + uint32_t sel : 2; /* nand_dq3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO8_s ALT_SYSMGR_PINMUX_MIXED1IO8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_OFST 0x120 + +/* + * Register : nand_dq4 Mux Selection Register - MIXED1IO9 + * + * This register is used to control the peripherals connected to nand_dq4 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq4 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq4 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq4. + * + * 0 : Pin is connected to GPIO/LoanIO number 23. + * + * 1 : Pin is connected to Peripheral signal USB1.D5. + * + * 2 : Pin is connected to Peripheral signal RGMII1.TX_CTL. + * + * 3 : Pin is connected to Peripheral signal NAND.dq4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO9_s +{ + uint32_t sel : 2; /* nand_dq4 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO9_s ALT_SYSMGR_PINMUX_MIXED1IO9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_OFST 0x124 + +/* + * Register : nand_dq5 Mux Selection Register - MIXED1IO10 + * + * This register is used to control the peripherals connected to nand_dq5 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq5 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq5 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq5. + * + * 0 : Pin is connected to GPIO/LoanIO number 24. + * + * 1 : Pin is connected to Peripheral signal USB1.D6. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RX_CLK. + * + * 3 : Pin is connected to Peripheral signal NAND.dq5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO10_s +{ + uint32_t sel : 2; /* nand_dq5 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO10_s ALT_SYSMGR_PINMUX_MIXED1IO10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_OFST 0x128 + +/* + * Register : nand_dq6 Mux Selection Register - MIXED1IO11 + * + * This register is used to control the peripherals connected to nand_dq6 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq6 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq6 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq6. + * + * 0 : Pin is connected to GPIO/LoanIO number 25. + * + * 1 : Pin is connected to Peripheral signal USB1.D7. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD1. + * + * 3 : Pin is connected to Peripheral signal NAND.dq6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO11_s +{ + uint32_t sel : 2; /* nand_dq6 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO11_s ALT_SYSMGR_PINMUX_MIXED1IO11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_OFST 0x12c + +/* + * Register : nand_dq7 Mux Selection Register - MIXED1IO12 + * + * This register is used to control the peripherals connected to nand_dq7 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | nand_dq7 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_dq7 Mux Selection Field - sel + * + * Select peripheral signals connected nand_dq7. + * + * 0 : Pin is connected to GPIO/LoanIO number 26. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD2. + * + * 3 : Pin is connected to Peripheral signal NAND.dq7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO12_s +{ + uint32_t sel : 2; /* nand_dq7 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO12_s ALT_SYSMGR_PINMUX_MIXED1IO12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_OFST 0x130 + +/* + * Register : nand_wp Mux Selection Register - MIXED1IO13 + * + * This register is used to control the peripherals connected to nand_wp + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_wp Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_wp Mux Selection Field - sel + * + * Select peripheral signals connected nand_wp. + * + * 0 : Pin is connected to GPIO/LoanIO number 27. + * + * 1 : Pin is connected to Peripheral signal QSPI.SS2. + * + * 2 : Pin is connected to Peripheral signal RGMII1.RXD3. + * + * 3 : Pin is connected to Peripheral signal NAND.wp. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO13_s +{ + uint32_t sel : 2; /* nand_wp Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO13_s ALT_SYSMGR_PINMUX_MIXED1IO13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_OFST 0x134 + +/* + * Register : nand_we Mux Selection Register - MIXED1IO14 + * + * This register is used to control the peripherals connected to nand_we + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [1:0] | RW | 0x0 | nand_we Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : nand_we Mux Selection Field - sel + * + * Select peripheral signals connected nand_we. + * + * 0 : Pin is connected to GPIO/LoanIO number 28. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal QSPI.SS1. + * + * 3 : Pin is connected to Peripheral signal NAND.we. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO14_s +{ + uint32_t sel : 2; /* nand_we Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO14_s ALT_SYSMGR_PINMUX_MIXED1IO14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_OFST 0x138 + +/* + * Register : qspi_io0 Mux Selection Register - MIXED1IO15 + * + * This register is used to control the peripherals connected to qspi_io0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io0 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io0. + * + * 0 : Pin is connected to GPIO/LoanIO number 29. + * + * 1 : Pin is connected to Peripheral signal USB1.CLK. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO15_s +{ + uint32_t sel : 2; /* qspi_io0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO15_s ALT_SYSMGR_PINMUX_MIXED1IO15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_OFST 0x13c + +/* + * Register : qspi_io1 Mux Selection Register - MIXED1IO16 + * + * This register is used to control the peripherals connected to qspi_io1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io1 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io1. + * + * 0 : Pin is connected to GPIO/LoanIO number 30. + * + * 1 : Pin is connected to Peripheral signal USB1.STP. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO16_s +{ + uint32_t sel : 2; /* qspi_io1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO16_s ALT_SYSMGR_PINMUX_MIXED1IO16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_OFST 0x140 + +/* + * Register : qspi_io2 Mux Selection Register - MIXED1IO17 + * + * This register is used to control the peripherals connected to qspi_io2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io2 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io2. + * + * 0 : Pin is connected to GPIO/LoanIO number 31. + * + * 1 : Pin is connected to Peripheral signal USB1.DIR. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO17_s +{ + uint32_t sel : 2; /* qspi_io2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO17_s ALT_SYSMGR_PINMUX_MIXED1IO17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_OFST 0x144 + +/* + * Register : qspi_io3 Mux Selection Register - MIXED1IO18 + * + * This register is used to control the peripherals connected to qspi_io3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_io3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_io3 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_io3. + * + * 0 : Pin is connected to GPIO/LoanIO number 32. + * + * 1 : Pin is connected to Peripheral signal USB1.NXT. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.IO3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO18_s +{ + uint32_t sel : 2; /* qspi_io3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO18_s ALT_SYSMGR_PINMUX_MIXED1IO18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_OFST 0x148 + +/* + * Register : qspi_ss0 Mux Selection Register - MIXED1IO19 + * + * This register is used to control the peripherals connected to qspi_ss0 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_ss0 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_ss0 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_ss0. + * + * 0 : Pin is connected to GPIO/LoanIO number 33. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.SS0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO19_s +{ + uint32_t sel : 2; /* qspi_ss0 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO19_s ALT_SYSMGR_PINMUX_MIXED1IO19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_OFST 0x14c + +/* + * Register : qpsi_clk Mux Selection Register - MIXED1IO20 + * + * This register is used to control the peripherals connected to qpsi_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qpsi_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qpsi_clk Mux Selection Field - sel + * + * Select peripheral signals connected qpsi_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 34. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO20_s +{ + uint32_t sel : 2; /* qpsi_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO20_s ALT_SYSMGR_PINMUX_MIXED1IO20_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO20 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_OFST 0x150 + +/* + * Register : qspi_ss1 Mux Selection Register - MIXED1IO21 + * + * This register is used to control the peripherals connected to qspi_ss1 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | qspi_ss1 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : qspi_ss1 Mux Selection Field - sel + * + * Select peripheral signals connected qspi_ss1. + * + * 0 : Pin is connected to GPIO/LoanIO number 35. + * + * 1 : Pin is connected to Peripheral signal not applicable. + * + * 2 : Pin is connected to Peripheral signal not applicable. + * + * 3 : Pin is connected to Peripheral signal QSPI.SS1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21. + */ +struct ALT_SYSMGR_PINMUX_MIXED1IO21_s +{ + uint32_t sel : 2; /* qspi_ss1 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO21_s ALT_SYSMGR_PINMUX_MIXED1IO21_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO21 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_OFST 0x154 + +/* + * Register : emac1_mdio Mux Selection Register - MIXED2IO0 + * + * This register is used to control the peripherals connected to emac1_mdio + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [1:0] | RW | 0x0 | emac1_mdio Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_mdio Mux Selection Field - sel + * + * Select peripheral signals connected emac1_mdio. + * + * 0 : Pin is connected to GPIO/LoanIO number 54. + * + * 1 : Pin is connected to Peripheral signal SPIS0.CLK. + * + * 2 : Pin is connected to Peripheral signal SPIM0.CLK. + * + * 3 : Pin is connected to Peripheral signal RGMII1.MDIO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO0_s +{ + uint32_t sel : 2; /* emac1_mdio Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO0_s ALT_SYSMGR_PINMUX_MIXED2IO0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_OFST 0x158 + +/* + * Register : emac1_mdc Mux Selection Register - MIXED2IO1 + * + * This register is used to control the peripherals connected to emac1_mdc + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [1:0] | RW | 0x0 | emac1_mdc Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_mdc Mux Selection Field - sel + * + * Select peripheral signals connected emac1_mdc. + * + * 0 : Pin is connected to GPIO/LoanIO number 55. + * + * 1 : Pin is connected to Peripheral signal SPIS0.MOSI. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MOSI. + * + * 3 : Pin is connected to Peripheral signal RGMII1.MDC. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO1_s +{ + uint32_t sel : 2; /* emac1_mdc Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO1_s ALT_SYSMGR_PINMUX_MIXED2IO1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_OFST 0x15c + +/* + * Register : emac1_tx_d2 Mux Selection Register - MIXED2IO2 + * + * This register is used to control the peripherals connected to emac1_tx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 56. + * + * 1 : Pin is connected to Peripheral signal SPIS0.MISO. + * + * 2 : Pin is connected to Peripheral signal SPIM0.MISO. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO2_s +{ + uint32_t sel : 2; /* emac1_tx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO2_s ALT_SYSMGR_PINMUX_MIXED2IO2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_OFST 0x160 + +/* + * Register : emac1_tx_d3 Mux Selection Register - MIXED2IO3 + * + * This register is used to control the peripherals connected to emac1_tx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_tx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_tx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_tx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 57. + * + * 1 : Pin is connected to Peripheral signal SPIS0.SS0. + * + * 2 : Pin is connected to Peripheral signal SPIM0.SS0. + * + * 3 : Pin is connected to Peripheral signal RGMII1.TXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO3_s +{ + uint32_t sel : 2; /* emac1_tx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO3_s ALT_SYSMGR_PINMUX_MIXED2IO3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_OFST 0x164 + +/* + * Register : emac1_rx_clk Mux Selection Register - MIXED2IO4 + * + * This register is used to control the peripherals connected to emac1_rx_clk + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_clk Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_clk Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_clk. + * + * 0 : Pin is connected to GPIO/LoanIO number 58. + * + * 1 : Pin is connected to Peripheral signal SPIM1.CLK. + * + * 2 : Pin is connected to Peripheral signal SPIS1.CLK. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RX_CLK. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO4_s +{ + uint32_t sel : 2; /* emac1_rx_clk Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO4_s ALT_SYSMGR_PINMUX_MIXED2IO4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_OFST 0x168 + +/* + * Register : emac1_rx_ctl Mux Selection Register - MIXED2IO5 + * + * This register is used to control the peripherals connected to emac1_rx_ctl + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_ctl Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_ctl Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_ctl. + * + * 0 : Pin is connected to GPIO/LoanIO number 59. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MOSI. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MOSI. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RX_CTL. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO5_s +{ + uint32_t sel : 2; /* emac1_rx_ctl Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO5_s ALT_SYSMGR_PINMUX_MIXED2IO5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_OFST 0x16c + +/* + * Register : emac1_rx_d2 Mux Selection Register - MIXED2IO6 + * + * This register is used to control the peripherals connected to emac1_rx_d2 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d2 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d2 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d2. + * + * 0 : Pin is connected to GPIO/LoanIO number 60. + * + * 1 : Pin is connected to Peripheral signal SPIM1.MISO. + * + * 2 : Pin is connected to Peripheral signal SPIS1.MISO. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO6_s +{ + uint32_t sel : 2; /* emac1_rx_d2 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO6_s ALT_SYSMGR_PINMUX_MIXED2IO6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_OFST 0x170 + +/* + * Register : emac1_rx_d3 Mux Selection Register - MIXED2IO7 + * + * This register is used to control the peripherals connected to emac1_rx_d3 + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [1:0] | RW | 0x0 | emac1_rx_d3 Mux Selection Field + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : emac1_rx_d3 Mux Selection Field - sel + * + * Select peripheral signals connected emac1_rx_d3. + * + * 0 : Pin is connected to GPIO/LoanIO number 61. + * + * 1 : Pin is connected to Peripheral signal SPIM1.SS0. + * + * 2 : Pin is connected to Peripheral signal SPIS1.SS0. + * + * 3 : Pin is connected to Peripheral signal RGMII1.RXD3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_MSB 1 +/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_WIDTH 2 +/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7. + */ +struct ALT_SYSMGR_PINMUX_MIXED2IO7_s +{ + uint32_t sel : 2; /* emac1_rx_d3 Mux Selection Field */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO7_s ALT_SYSMGR_PINMUX_MIXED2IO7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_OFST 0x174 + +/* + * Register : GPIO/LoanIO 48 Input Mux Selection Register - GPLINMUX48 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 48. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO48Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 48. + * + * 0 : Source for GPIO/LoanIO 48 is GENERALIO0. + * + * 1 : Source for GPIO/LoanIO 48 is EMACIO14. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX48_s +{ + uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX48_s ALT_SYSMGR_PINMUX_GPLINMUX48_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX48 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_OFST 0x178 + +/* + * Register : GPIO/LoanIO 49 Input Mux Selection Register - GPLINMUX49 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 49. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO49Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 49. + * + * 0 : Source for GPIO/LoanIO 49 is GENERALIO1. + * + * 1 : Source for GPIO/LoanIO 49 is EMACIO15. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX49_s +{ + uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX49_s ALT_SYSMGR_PINMUX_GPLINMUX49_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX49 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_OFST 0x17c + +/* + * Register : GPIO/LoanIO 50 Input Mux Selection Register - GPLINMUX50 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 50. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO50Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 50. + * + * 0 : Source for GPIO/LoanIO 50 is GENERALIO2. + * + * 1 : Source for GPIO/LoanIO 50 is EMACIO16. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX50_s +{ + uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX50_s ALT_SYSMGR_PINMUX_GPLINMUX50_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX50 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_OFST 0x180 + +/* + * Register : GPIO/LoanIO 51 Input Mux Selection Register - GPLINMUX51 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 51. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO51Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 51. + * + * 0 : Source for GPIO/LoanIO 51 is GENERALIO3. + * + * 1 : Source for GPIO/LoanIO 51 is EMACIO17. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX51_s +{ + uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX51_s ALT_SYSMGR_PINMUX_GPLINMUX51_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX51 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_OFST 0x184 + +/* + * Register : GPIO/LoanIO 52 Input Mux Selection Register - GPLINMUX52 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 52. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO52Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 52. + * + * 0 : Source for GPIO/LoanIO 52 is GENERALIO4. + * + * 1 : Source for GPIO/LoanIO 52 is EMACIO18. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX52_s +{ + uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX52_s ALT_SYSMGR_PINMUX_GPLINMUX52_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX52 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_OFST 0x188 + +/* + * Register : GPIO/LoanIO 53 Input Mux Selection Register - GPLINMUX53 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 53. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO53Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 53. + * + * 0 : Source for GPIO/LoanIO 53 is GENERALIO5. + * + * 1 : Source for GPIO/LoanIO 53 is EMACIO19. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX53_s +{ + uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX53_s ALT_SYSMGR_PINMUX_GPLINMUX53_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX53 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_OFST 0x18c + +/* + * Register : GPIO/LoanIO 54 Input Mux Selection Register - GPLINMUX54 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 54. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO54Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 54. + * + * 0 : Source for GPIO/LoanIO 54 is GENERALIO6. + * + * 1 : Source for GPIO/LoanIO 54 is MIXED2IO0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX54_s +{ + uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX54_s ALT_SYSMGR_PINMUX_GPLINMUX54_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX54 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_OFST 0x190 + +/* + * Register : GPIO/LoanIO 55 Input Mux Selection Register - GPLINMUX55 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 55. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO55Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 55. + * + * 0 : Source for GPIO/LoanIO 55 is GENERALIO7. + * + * 1 : Source for GPIO/LoanIO 55 is MIXED2IO1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX55_s +{ + uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX55_s ALT_SYSMGR_PINMUX_GPLINMUX55_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX55 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_OFST 0x194 + +/* + * Register : GPIO/LoanIO 56 Input Mux Selection Register - GPLINMUX56 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 56. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO56Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 56. + * + * 0 : Source for GPIO/LoanIO 56 is GENERALIO8. + * + * 1 : Source for GPIO/LoanIO 56 is MIXED2IO2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX56_s +{ + uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX56_s ALT_SYSMGR_PINMUX_GPLINMUX56_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX56 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_OFST 0x198 + +/* + * Register : GPIO/LoanIO 57 Input Mux Selection Register - GPLINMUX57 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 57. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO57Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 57. + * + * 0 : Source for GPIO/LoanIO 57 is GENERALIO9. + * + * 1 : Source for GPIO/LoanIO 57 is MIXED2IO3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX57_s +{ + uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX57_s ALT_SYSMGR_PINMUX_GPLINMUX57_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX57 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_OFST 0x19c + +/* + * Register : GPIO/LoanIO 58 Input Mux Selection Register - GPLINMUX58 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 58. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO58Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 58. + * + * 0 : Source for GPIO/LoanIO 58 is GENERALIO10. + * + * 1 : Source for GPIO/LoanIO 58 is MIXED2IO4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX58_s +{ + uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX58_s ALT_SYSMGR_PINMUX_GPLINMUX58_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX58 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_OFST 0x1a0 + +/* + * Register : GPIO/LoanIO 59 Input Mux Selection Register - GPLINMUX59 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 59. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO59Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 59. + * + * 0 : Source for GPIO/LoanIO 59 is GENERALIO11. + * + * 1 : Source for GPIO/LoanIO 59 is MIXED2IO5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX59_s +{ + uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX59_s ALT_SYSMGR_PINMUX_GPLINMUX59_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX59 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_OFST 0x1a4 + +/* + * Register : GPIO/LoanIO 60 Input Mux Selection Register - GPLINMUX60 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 60. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO60Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 60. + * + * 0 : Source for GPIO/LoanIO 60 is GENERALIO12. + * + * 1 : Source for GPIO/LoanIO 60 is MIXED2IO6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX60_s +{ + uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX60_s ALT_SYSMGR_PINMUX_GPLINMUX60_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX60 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_OFST 0x1a8 + +/* + * Register : GPIO/LoanIO 61 Input Mux Selection Register - GPLINMUX61 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 61. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO61Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 61. + * + * 0 : Source for GPIO/LoanIO 61 is GENERALIO13. + * + * 1 : Source for GPIO/LoanIO 61 is MIXED2IO7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX61_s +{ + uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX61_s ALT_SYSMGR_PINMUX_GPLINMUX61_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX61 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_OFST 0x1ac + +/* + * Register : GPIO/LoanIO 62 Input Mux Selection Register - GPLINMUX62 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 62. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO62Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 62. + * + * 0 : Source for GPIO/LoanIO 62 is GENERALIO14. + * + * 1 : Source for GPIO/LoanIO 62 is GENERALIO23. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX62_s +{ + uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX62_s ALT_SYSMGR_PINMUX_GPLINMUX62_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX62 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_OFST 0x1b0 + +/* + * Register : GPIO/LoanIO 63 Input Mux Selection Register - GPLINMUX63 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 63. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO63Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 63. + * + * 0 : Source for GPIO/LoanIO 63 is GENERALIO15. + * + * 1 : Source for GPIO/LoanIO 63 is GENERALIO24. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX63_s +{ + uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX63_s ALT_SYSMGR_PINMUX_GPLINMUX63_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX63 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_OFST 0x1b4 + +/* + * Register : GPIO/LoanIO 64 Input Mux Selection Register - GPLINMUX64 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 64. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO64Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 64. + * + * 0 : Source for GPIO/LoanIO 64 is GENERALIO16. + * + * 1 : Source for GPIO/LoanIO 64 is GENERALIO25. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX64_s +{ + uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX64_s ALT_SYSMGR_PINMUX_GPLINMUX64_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX64 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_OFST 0x1b8 + +/* + * Register : GPIO/LoanIO 65 Input Mux Selection Register - GPLINMUX65 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 65. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO65Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 65. + * + * 0 : Source for GPIO/LoanIO 65 is GENERALIO17. + * + * 1 : Source for GPIO/LoanIO 65 is GENERALIO26. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX65_s +{ + uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX65_s ALT_SYSMGR_PINMUX_GPLINMUX65_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX65 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_OFST 0x1bc + +/* + * Register : GPIO/LoanIO 66 Input Mux Selection Register - GPLINMUX66 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 66. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO66Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 66. + * + * 0 : Source for GPIO/LoanIO 66 is GENERALIO18. + * + * 1 : Source for GPIO/LoanIO 66 is GENERALIO27. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX66_s +{ + uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX66_s ALT_SYSMGR_PINMUX_GPLINMUX66_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX66 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_OFST 0x1c0 + +/* + * Register : GPIO/LoanIO 67 Input Mux Selection Register - GPLINMUX67 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 67. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO67Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 67. + * + * 0 : Source for GPIO/LoanIO 67 is GENERALIO19. + * + * 1 : Source for GPIO/LoanIO 67 is GENERALIO28. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX67_s +{ + uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX67_s ALT_SYSMGR_PINMUX_GPLINMUX67_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX67 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_OFST 0x1c4 + +/* + * Register : GPIO/LoanIO 68 Input Mux Selection Register - GPLINMUX68 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 68. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO68Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 68. + * + * 0 : Source for GPIO/LoanIO 68 is GENERALIO20. + * + * 1 : Source for GPIO/LoanIO 68 is GENERALIO29. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX68_s +{ + uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX68_s ALT_SYSMGR_PINMUX_GPLINMUX68_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX68 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_OFST 0x1c8 + +/* + * Register : GPIO/LoanIO 69 Input Mux Selection Register - GPLINMUX69 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 69. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO69Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 69. + * + * 0 : Source for GPIO/LoanIO 69 is GENERALIO21. + * + * 1 : Source for GPIO/LoanIO 69 is GENERALIO30. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX69_s +{ + uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX69_s ALT_SYSMGR_PINMUX_GPLINMUX69_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX69 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_OFST 0x1cc + +/* + * Register : GPIO/LoanIO 70 Input Mux Selection Register - GPLINMUX70 + * + * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects + * the input signal for GPIO/LoanIO 70. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO70Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 70. + * + * 0 : Source for GPIO/LoanIO 70 is GENERALIO22. + * + * 1 : Source for GPIO/LoanIO 70 is GENERALIO31. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70. + */ +struct ALT_SYSMGR_PINMUX_GPLINMUX70_s +{ + uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX70_s ALT_SYSMGR_PINMUX_GPLINMUX70_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX70 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_OFST 0x1d0 + +/* + * Register : GPIO/LoanIO 0 Output/Output Enable Mux Selection Register - GPLMUX0 + * + * Selection between GPIO and LoanIO output and output enable for GPIO0 and + * LoanIO0. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO0Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO0Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 0. + * + * 0 : LoanIO 0 controls GPIO/LOANIO[0] output and output enable signals. + * + * 1 : GPIO 0 controls GPIO/LOANI[0] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX0_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX0. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX0_s +{ + uint32_t sel : 1; /* GPIO/Loan IO0Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX0. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX0_s ALT_SYSMGR_PINMUX_GPLMUX0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX0 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_OFST 0x1d4 + +/* + * Register : GPIO/LoanIO 1 Output/Output Enable Mux Selection Register - GPLMUX1 + * + * Selection between GPIO and LoanIO output and output enable for GPIO1 and + * LoanIO1. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO1Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO1Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 1. + * + * 0 : LoanIO 1 controls GPIO/LOANIO[1] output and output enable signals. + * + * 1 : GPIO 1 controls GPIO/LOANI[1] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX1_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX1. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX1_s +{ + uint32_t sel : 1; /* GPIO/Loan IO1Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX1. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX1_s ALT_SYSMGR_PINMUX_GPLMUX1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX1 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_OFST 0x1d8 + +/* + * Register : GPIO/LoanIO 2 Output/Output Enable Mux Selection Register - GPLMUX2 + * + * Selection between GPIO and LoanIO output and output enable for GPIO2 and + * LoanIO2. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO2Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO2Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 2. + * + * 0 : LoanIO 2 controls GPIO/LOANIO[2] output and output enable signals. + * + * 1 : GPIO 2 controls GPIO/LOANI[2] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX2_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX2. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX2_s +{ + uint32_t sel : 1; /* GPIO/Loan IO2Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX2. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX2_s ALT_SYSMGR_PINMUX_GPLMUX2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX2 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_OFST 0x1dc + +/* + * Register : GPIO/LoanIO 3 Output/Output Enable Mux Selection Register - GPLMUX3 + * + * Selection between GPIO and LoanIO output and output enable for GPIO3 and + * LoanIO3. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO3Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO3Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 3. + * + * 0 : LoanIO 3 controls GPIO/LOANIO[3] output and output enable signals. + * + * 1 : GPIO 3 controls GPIO/LOANI[3] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX3_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX3. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX3_s +{ + uint32_t sel : 1; /* GPIO/Loan IO3Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX3. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX3_s ALT_SYSMGR_PINMUX_GPLMUX3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX3 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_OFST 0x1e0 + +/* + * Register : GPIO/LoanIO 4 Output/Output Enable Mux Selection Register - GPLMUX4 + * + * Selection between GPIO and LoanIO output and output enable for GPIO4 and + * LoanIO4. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO4Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO4Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 4. + * + * 0 : LoanIO 4 controls GPIO/LOANIO[4] output and output enable signals. + * + * 1 : GPIO 4 controls GPIO/LOANI[4] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX4_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX4. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX4_s +{ + uint32_t sel : 1; /* GPIO/Loan IO4Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX4. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX4_s ALT_SYSMGR_PINMUX_GPLMUX4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX4 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_OFST 0x1e4 + +/* + * Register : GPIO/LoanIO 5 Output/Output Enable Mux Selection Register - GPLMUX5 + * + * Selection between GPIO and LoanIO output and output enable for GPIO5 and + * LoanIO5. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO5Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO5Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 5. + * + * 0 : LoanIO 5 controls GPIO/LOANIO[5] output and output enable signals. + * + * 1 : GPIO 5 controls GPIO/LOANI[5] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX5_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX5. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX5_s +{ + uint32_t sel : 1; /* GPIO/Loan IO5Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX5. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX5_s ALT_SYSMGR_PINMUX_GPLMUX5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX5 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_OFST 0x1e8 + +/* + * Register : GPIO/LoanIO 6 Output/Output Enable Mux Selection Register - GPLMUX6 + * + * Selection between GPIO and LoanIO output and output enable for GPIO6 and + * LoanIO6. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO6Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO6Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 6. + * + * 0 : LoanIO 6 controls GPIO/LOANIO[6] output and output enable signals. + * + * 1 : GPIO 6 controls GPIO/LOANI[6] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX6_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX6. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX6_s +{ + uint32_t sel : 1; /* GPIO/Loan IO6Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX6. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX6_s ALT_SYSMGR_PINMUX_GPLMUX6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX6 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_OFST 0x1ec + +/* + * Register : GPIO/LoanIO 7 Output/Output Enable Mux Selection Register - GPLMUX7 + * + * Selection between GPIO and LoanIO output and output enable for GPIO7 and + * LoanIO7. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO7Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO7Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 7. + * + * 0 : LoanIO 7 controls GPIO/LOANIO[7] output and output enable signals. + * + * 1 : GPIO 7 controls GPIO/LOANI[7] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX7_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX7. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX7_s +{ + uint32_t sel : 1; /* GPIO/Loan IO7Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX7. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX7_s ALT_SYSMGR_PINMUX_GPLMUX7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX7 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_OFST 0x1f0 + +/* + * Register : GPIO/LoanIO 8 Output/Output Enable Mux Selection Register - GPLMUX8 + * + * Selection between GPIO and LoanIO output and output enable for GPIO8 and + * LoanIO8. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO8Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO8Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 8. + * + * 0 : LoanIO 8 controls GPIO/LOANIO[8] output and output enable signals. + * + * 1 : GPIO 8 controls GPIO/LOANI[8] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX8_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX8. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX8_s +{ + uint32_t sel : 1; /* GPIO/Loan IO8Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX8. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX8_s ALT_SYSMGR_PINMUX_GPLMUX8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX8 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_OFST 0x1f4 + +/* + * Register : GPIO/LoanIO 9 Output/Output Enable Mux Selection Register - GPLMUX9 + * + * Selection between GPIO and LoanIO output and output enable for GPIO9 and + * LoanIO9. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO9Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO9Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 9. + * + * 0 : LoanIO 9 controls GPIO/LOANIO[9] output and output enable signals. + * + * 1 : GPIO 9 controls GPIO/LOANI[9] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX9_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX9. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX9_s +{ + uint32_t sel : 1; /* GPIO/Loan IO9Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX9. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX9_s ALT_SYSMGR_PINMUX_GPLMUX9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX9 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_OFST 0x1f8 + +/* + * Register : GPIO/LoanIO 10 Output/Output Enable Mux Selection Register - GPLMUX10 + * + * Selection between GPIO and LoanIO output and output enable for GPIO10 and + * LoanIO10. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO10Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO10Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 10. + * + * 0 : LoanIO 10 controls GPIO/LOANIO[10] output and output enable signals. + * + * 1 : GPIO 10 controls GPIO/LOANI[10] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX10_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX10. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX10_s +{ + uint32_t sel : 1; /* GPIO/Loan IO10Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX10. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX10_s ALT_SYSMGR_PINMUX_GPLMUX10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX10 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_OFST 0x1fc + +/* + * Register : GPIO/LoanIO 11 Output/Output Enable Mux Selection Register - GPLMUX11 + * + * Selection between GPIO and LoanIO output and output enable for GPIO11 and + * LoanIO11. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO11Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO11Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 11. + * + * 0 : LoanIO 11 controls GPIO/LOANIO[11] output and output enable signals. + * + * 1 : GPIO 11 controls GPIO/LOANI[11] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX11_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX11. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX11_s +{ + uint32_t sel : 1; /* GPIO/Loan IO11Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX11. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX11_s ALT_SYSMGR_PINMUX_GPLMUX11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX11 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_OFST 0x200 + +/* + * Register : GPIO/LoanIO 12 Output/Output Enable Mux Selection Register - GPLMUX12 + * + * Selection between GPIO and LoanIO output and output enable for GPIO12 and + * LoanIO12. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO12Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO12Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 12. + * + * 0 : LoanIO 12 controls GPIO/LOANIO[12] output and output enable signals. + * + * 1 : GPIO 12 controls GPIO/LOANI[12] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX12_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX12. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX12_s +{ + uint32_t sel : 1; /* GPIO/Loan IO12Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX12. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX12_s ALT_SYSMGR_PINMUX_GPLMUX12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX12 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_OFST 0x204 + +/* + * Register : GPIO/LoanIO 13 Output/Output Enable Mux Selection Register - GPLMUX13 + * + * Selection between GPIO and LoanIO output and output enable for GPIO13 and + * LoanIO13. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO13Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO13Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 13. + * + * 0 : LoanIO 13 controls GPIO/LOANIO[13] output and output enable signals. + * + * 1 : GPIO 13 controls GPIO/LOANI[13] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX13_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX13. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX13_s +{ + uint32_t sel : 1; /* GPIO/Loan IO13Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX13. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX13_s ALT_SYSMGR_PINMUX_GPLMUX13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX13 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_OFST 0x208 + +/* + * Register : GPIO/LoanIO 14 Output/Output Enable Mux Selection Register - GPLMUX14 + * + * Selection between GPIO and LoanIO output and output enable for GPIO14 and + * LoanIO14. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO14Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO14Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 14. + * + * 0 : LoanIO 14 controls GPIO/LOANIO[14] output and output enable signals. + * + * 1 : GPIO 14 controls GPIO/LOANI[14] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX14_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX14. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX14_s +{ + uint32_t sel : 1; /* GPIO/Loan IO14Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX14. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX14_s ALT_SYSMGR_PINMUX_GPLMUX14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX14 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_OFST 0x20c + +/* + * Register : GPIO/LoanIO 15 Output/Output Enable Mux Selection Register - GPLMUX15 + * + * Selection between GPIO and LoanIO output and output enable for GPIO15 and + * LoanIO15. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO15Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO15Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 15. + * + * 0 : LoanIO 15 controls GPIO/LOANIO[15] output and output enable signals. + * + * 1 : GPIO 15 controls GPIO/LOANI[15] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX15_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX15. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX15_s +{ + uint32_t sel : 1; /* GPIO/Loan IO15Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX15. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX15_s ALT_SYSMGR_PINMUX_GPLMUX15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX15 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_OFST 0x210 + +/* + * Register : GPIO/LoanIO 16 Output/Output Enable Mux Selection Register - GPLMUX16 + * + * Selection between GPIO and LoanIO output and output enable for GPIO16 and + * LoanIO16. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO16Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO16Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 16. + * + * 0 : LoanIO 16 controls GPIO/LOANIO[16] output and output enable signals. + * + * 1 : GPIO 16 controls GPIO/LOANI[16] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX16_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX16. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX16_s +{ + uint32_t sel : 1; /* GPIO/Loan IO16Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX16. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX16_s ALT_SYSMGR_PINMUX_GPLMUX16_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX16 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_OFST 0x214 + +/* + * Register : GPIO/LoanIO 17 Output/Output Enable Mux Selection Register - GPLMUX17 + * + * Selection between GPIO and LoanIO output and output enable for GPIO17 and + * LoanIO17. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO17Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO17Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 17. + * + * 0 : LoanIO 17 controls GPIO/LOANIO[17] output and output enable signals. + * + * 1 : GPIO 17 controls GPIO/LOANI[17] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX17_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX17. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX17_s +{ + uint32_t sel : 1; /* GPIO/Loan IO17Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX17. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX17_s ALT_SYSMGR_PINMUX_GPLMUX17_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX17 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_OFST 0x218 + +/* + * Register : GPIO/LoanIO 18 Output/Output Enable Mux Selection Register - GPLMUX18 + * + * Selection between GPIO and LoanIO output and output enable for GPIO18 and + * LoanIO18. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO18Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO18Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 18. + * + * 0 : LoanIO 18 controls GPIO/LOANIO[18] output and output enable signals. + * + * 1 : GPIO 18 controls GPIO/LOANI[18] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX18_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX18. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX18_s +{ + uint32_t sel : 1; /* GPIO/Loan IO18Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX18. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX18_s ALT_SYSMGR_PINMUX_GPLMUX18_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX18 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_OFST 0x21c + +/* + * Register : GPIO/LoanIO 19 Output/Output Enable Mux Selection Register - GPLMUX19 + * + * Selection between GPIO and LoanIO output and output enable for GPIO19 and + * LoanIO19. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO19Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO19Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 19. + * + * 0 : LoanIO 19 controls GPIO/LOANIO[19] output and output enable signals. + * + * 1 : GPIO 19 controls GPIO/LOANI[19] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX19_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX19. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX19_s +{ + uint32_t sel : 1; /* GPIO/Loan IO19Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX19. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX19_s ALT_SYSMGR_PINMUX_GPLMUX19_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX19 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_OFST 0x220 + +/* + * Register : GPIO/LoanIO 20 Output/Output Enable Mux Selection Register - GPLMUX20 + * + * Selection between GPIO and LoanIO output and output enable for GPIO20 and + * LoanIO20. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO20Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO20Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 20. + * + * 0 : LoanIO 20 controls GPIO/LOANIO[20] output and output enable signals. + * + * 1 : GPIO 20 controls GPIO/LOANI[20] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX20_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX20. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX20_s +{ + uint32_t sel : 1; /* GPIO/Loan IO20Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX20. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX20_s ALT_SYSMGR_PINMUX_GPLMUX20_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX20 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_OFST 0x224 + +/* + * Register : GPIO/LoanIO 21 Output/Output Enable Mux Selection Register - GPLMUX21 + * + * Selection between GPIO and LoanIO output and output enable for GPIO21 and + * LoanIO21. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO21Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO21Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 21. + * + * 0 : LoanIO 21 controls GPIO/LOANIO[21] output and output enable signals. + * + * 1 : GPIO 21 controls GPIO/LOANI[21] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX21_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX21. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX21_s +{ + uint32_t sel : 1; /* GPIO/Loan IO21Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX21. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX21_s ALT_SYSMGR_PINMUX_GPLMUX21_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX21 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_OFST 0x228 + +/* + * Register : GPIO/LoanIO 22 Output/Output Enable Mux Selection Register - GPLMUX22 + * + * Selection between GPIO and LoanIO output and output enable for GPIO22 and + * LoanIO22. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO22Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO22Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 22. + * + * 0 : LoanIO 22 controls GPIO/LOANIO[22] output and output enable signals. + * + * 1 : GPIO 22 controls GPIO/LOANI[22] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX22_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX22. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX22_s +{ + uint32_t sel : 1; /* GPIO/Loan IO22Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX22. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX22_s ALT_SYSMGR_PINMUX_GPLMUX22_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX22 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_OFST 0x22c + +/* + * Register : GPIO/LoanIO 23 Output/Output Enable Mux Selection Register - GPLMUX23 + * + * Selection between GPIO and LoanIO output and output enable for GPIO23 and + * LoanIO23. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO23Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO23Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 23. + * + * 0 : LoanIO 23 controls GPIO/LOANIO[23] output and output enable signals. + * + * 1 : GPIO 23 controls GPIO/LOANI[23] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX23_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX23. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX23_s +{ + uint32_t sel : 1; /* GPIO/Loan IO23Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX23. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX23_s ALT_SYSMGR_PINMUX_GPLMUX23_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX23 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_OFST 0x230 + +/* + * Register : GPIO/LoanIO 24 Output/Output Enable Mux Selection Register - GPLMUX24 + * + * Selection between GPIO and LoanIO output and output enable for GPIO24 and + * LoanIO24. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO24Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO24Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 24. + * + * 0 : LoanIO 24 controls GPIO/LOANIO[24] output and output enable signals. + * + * 1 : GPIO 24 controls GPIO/LOANI[24] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX24_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX24. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX24_s +{ + uint32_t sel : 1; /* GPIO/Loan IO24Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX24. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX24_s ALT_SYSMGR_PINMUX_GPLMUX24_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX24 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_OFST 0x234 + +/* + * Register : GPIO/LoanIO 25 Output/Output Enable Mux Selection Register - GPLMUX25 + * + * Selection between GPIO and LoanIO output and output enable for GPIO25 and + * LoanIO25. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO25Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO25Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 25. + * + * 0 : LoanIO 25 controls GPIO/LOANIO[25] output and output enable signals. + * + * 1 : GPIO 25 controls GPIO/LOANI[25] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX25_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX25. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX25_s +{ + uint32_t sel : 1; /* GPIO/Loan IO25Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX25. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX25_s ALT_SYSMGR_PINMUX_GPLMUX25_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX25 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_OFST 0x238 + +/* + * Register : GPIO/LoanIO 26 Output/Output Enable Mux Selection Register - GPLMUX26 + * + * Selection between GPIO and LoanIO output and output enable for GPIO26 and + * LoanIO26. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO26Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO26Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 26. + * + * 0 : LoanIO 26 controls GPIO/LOANIO[26] output and output enable signals. + * + * 1 : GPIO 26 controls GPIO/LOANI[26] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX26_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX26. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX26_s +{ + uint32_t sel : 1; /* GPIO/Loan IO26Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX26. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX26_s ALT_SYSMGR_PINMUX_GPLMUX26_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX26 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_OFST 0x23c + +/* + * Register : GPIO/LoanIO 27 Output/Output Enable Mux Selection Register - GPLMUX27 + * + * Selection between GPIO and LoanIO output and output enable for GPIO27 and + * LoanIO27. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO27Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO27Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 27. + * + * 0 : LoanIO 27 controls GPIO/LOANIO[27] output and output enable signals. + * + * 1 : GPIO 27 controls GPIO/LOANI[27] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX27_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX27. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX27_s +{ + uint32_t sel : 1; /* GPIO/Loan IO27Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX27. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX27_s ALT_SYSMGR_PINMUX_GPLMUX27_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX27 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_OFST 0x240 + +/* + * Register : GPIO/LoanIO 28 Output/Output Enable Mux Selection Register - GPLMUX28 + * + * Selection between GPIO and LoanIO output and output enable for GPIO28 and + * LoanIO28. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO28Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO28Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 28. + * + * 0 : LoanIO 28 controls GPIO/LOANIO[28] output and output enable signals. + * + * 1 : GPIO 28 controls GPIO/LOANI[28] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX28_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX28. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX28_s +{ + uint32_t sel : 1; /* GPIO/Loan IO28Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX28. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX28_s ALT_SYSMGR_PINMUX_GPLMUX28_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX28 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_OFST 0x244 + +/* + * Register : GPIO/LoanIO 29 Output/Output Enable Mux Selection Register - GPLMUX29 + * + * Selection between GPIO and LoanIO output and output enable for GPIO29 and + * LoanIO29. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO29Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO29Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 29. + * + * 0 : LoanIO 29 controls GPIO/LOANIO[29] output and output enable signals. + * + * 1 : GPIO 29 controls GPIO/LOANI[29] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX29_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX29. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX29_s +{ + uint32_t sel : 1; /* GPIO/Loan IO29Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX29. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX29_s ALT_SYSMGR_PINMUX_GPLMUX29_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX29 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_OFST 0x248 + +/* + * Register : GPIO/LoanIO 30 Output/Output Enable Mux Selection Register - GPLMUX30 + * + * Selection between GPIO and LoanIO output and output enable for GPIO30 and + * LoanIO30. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO30Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO30Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 30. + * + * 0 : LoanIO 30 controls GPIO/LOANIO[30] output and output enable signals. + * + * 1 : GPIO 30 controls GPIO/LOANI[30] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX30_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX30. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX30_s +{ + uint32_t sel : 1; /* GPIO/Loan IO30Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX30. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX30_s ALT_SYSMGR_PINMUX_GPLMUX30_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX30 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_OFST 0x24c + +/* + * Register : GPIO/LoanIO 31 Output/Output Enable Mux Selection Register - GPLMUX31 + * + * Selection between GPIO and LoanIO output and output enable for GPIO31 and + * LoanIO31. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO31Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO31Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 31. + * + * 0 : LoanIO 31 controls GPIO/LOANIO[31] output and output enable signals. + * + * 1 : GPIO 31 controls GPIO/LOANI[31] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX31_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX31. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX31_s +{ + uint32_t sel : 1; /* GPIO/Loan IO31Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX31. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX31_s ALT_SYSMGR_PINMUX_GPLMUX31_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX31 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_OFST 0x250 + +/* + * Register : GPIO/LoanIO 32 Output/Output Enable Mux Selection Register - GPLMUX32 + * + * Selection between GPIO and LoanIO output and output enable for GPIO32 and + * LoanIO32. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO32Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO32Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 32. + * + * 0 : LoanIO 32 controls GPIO/LOANIO[32] output and output enable signals. + * + * 1 : GPIO 32 controls GPIO/LOANI[32] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX32_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX32. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX32_s +{ + uint32_t sel : 1; /* GPIO/Loan IO32Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX32. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX32_s ALT_SYSMGR_PINMUX_GPLMUX32_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX32 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_OFST 0x254 + +/* + * Register : GPIO/LoanIO 33 Output/Output Enable Mux Selection Register - GPLMUX33 + * + * Selection between GPIO and LoanIO output and output enable for GPIO33 and + * LoanIO33. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO33Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO33Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 33. + * + * 0 : LoanIO 33 controls GPIO/LOANIO[33] output and output enable signals. + * + * 1 : GPIO 33 controls GPIO/LOANI[33] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX33_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX33. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX33_s +{ + uint32_t sel : 1; /* GPIO/Loan IO33Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX33. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX33_s ALT_SYSMGR_PINMUX_GPLMUX33_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX33 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_OFST 0x258 + +/* + * Register : GPIO/LoanIO 34 Output/Output Enable Mux Selection Register - GPLMUX34 + * + * Selection between GPIO and LoanIO output and output enable for GPIO34 and + * LoanIO34. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO34Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO34Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 34. + * + * 0 : LoanIO 34 controls GPIO/LOANIO[34] output and output enable signals. + * + * 1 : GPIO 34 controls GPIO/LOANI[34] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX34_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX34. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX34_s +{ + uint32_t sel : 1; /* GPIO/Loan IO34Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX34. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX34_s ALT_SYSMGR_PINMUX_GPLMUX34_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX34 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_OFST 0x25c + +/* + * Register : GPIO/LoanIO 35 Output/Output Enable Mux Selection Register - GPLMUX35 + * + * Selection between GPIO and LoanIO output and output enable for GPIO35 and + * LoanIO35. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO35Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO35Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 35. + * + * 0 : LoanIO 35 controls GPIO/LOANIO[35] output and output enable signals. + * + * 1 : GPIO 35 controls GPIO/LOANI[35] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX35_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX35. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX35_s +{ + uint32_t sel : 1; /* GPIO/Loan IO35Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX35. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX35_s ALT_SYSMGR_PINMUX_GPLMUX35_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX35 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_OFST 0x260 + +/* + * Register : GPIO/LoanIO 36 Output/Output Enable Mux Selection Register - GPLMUX36 + * + * Selection between GPIO and LoanIO output and output enable for GPIO36 and + * LoanIO36. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO36Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO36Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 36. + * + * 0 : LoanIO 36 controls GPIO/LOANIO[36] output and output enable signals. + * + * 1 : GPIO 36 controls GPIO/LOANI[36] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX36_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX36. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX36_s +{ + uint32_t sel : 1; /* GPIO/Loan IO36Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX36. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX36_s ALT_SYSMGR_PINMUX_GPLMUX36_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX36 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_OFST 0x264 + +/* + * Register : GPIO/LoanIO 37 Output/Output Enable Mux Selection Register - GPLMUX37 + * + * Selection between GPIO and LoanIO output and output enable for GPIO37 and + * LoanIO37. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO37Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO37Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 37. + * + * 0 : LoanIO 37 controls GPIO/LOANIO[37] output and output enable signals. + * + * 1 : GPIO 37 controls GPIO/LOANI[37] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX37_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX37. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX37_s +{ + uint32_t sel : 1; /* GPIO/Loan IO37Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX37. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX37_s ALT_SYSMGR_PINMUX_GPLMUX37_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX37 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_OFST 0x268 + +/* + * Register : GPIO/LoanIO 38 Output/Output Enable Mux Selection Register - GPLMUX38 + * + * Selection between GPIO and LoanIO output and output enable for GPIO38 and + * LoanIO38. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO38Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO38Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 38. + * + * 0 : LoanIO 38 controls GPIO/LOANIO[38] output and output enable signals. + * + * 1 : GPIO 38 controls GPIO/LOANI[38] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX38_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX38. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX38_s +{ + uint32_t sel : 1; /* GPIO/Loan IO38Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX38. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX38_s ALT_SYSMGR_PINMUX_GPLMUX38_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX38 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_OFST 0x26c + +/* + * Register : GPIO/LoanIO 39 Output/Output Enable Mux Selection Register - GPLMUX39 + * + * Selection between GPIO and LoanIO output and output enable for GPIO39 and + * LoanIO39. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO39Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO39Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 39. + * + * 0 : LoanIO 39 controls GPIO/LOANIO[39] output and output enable signals. + * + * 1 : GPIO 39 controls GPIO/LOANI[39] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX39_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX39. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX39_s +{ + uint32_t sel : 1; /* GPIO/Loan IO39Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX39. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX39_s ALT_SYSMGR_PINMUX_GPLMUX39_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX39 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_OFST 0x270 + +/* + * Register : GPIO/LoanIO 40 Output/Output Enable Mux Selection Register - GPLMUX40 + * + * Selection between GPIO and LoanIO output and output enable for GPIO40 and + * LoanIO40. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO40Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO40Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 40. + * + * 0 : LoanIO 40 controls GPIO/LOANIO[40] output and output enable signals. + * + * 1 : GPIO 40 controls GPIO/LOANI[40] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX40_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX40. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX40_s +{ + uint32_t sel : 1; /* GPIO/Loan IO40Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX40. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX40_s ALT_SYSMGR_PINMUX_GPLMUX40_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX40 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_OFST 0x274 + +/* + * Register : GPIO/LoanIO 41 Output/Output Enable Mux Selection Register - GPLMUX41 + * + * Selection between GPIO and LoanIO output and output enable for GPIO41 and + * LoanIO41. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO41Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO41Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 41. + * + * 0 : LoanIO 41 controls GPIO/LOANIO[41] output and output enable signals. + * + * 1 : GPIO 41 controls GPIO/LOANI[41] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX41_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX41. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX41_s +{ + uint32_t sel : 1; /* GPIO/Loan IO41Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX41. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX41_s ALT_SYSMGR_PINMUX_GPLMUX41_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX41 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_OFST 0x278 + +/* + * Register : GPIO/LoanIO 42 Output/Output Enable Mux Selection Register - GPLMUX42 + * + * Selection between GPIO and LoanIO output and output enable for GPIO42 and + * LoanIO42. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO42Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO42Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 42. + * + * 0 : LoanIO 42 controls GPIO/LOANIO[42] output and output enable signals. + * + * 1 : GPIO 42 controls GPIO/LOANI[42] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX42_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX42. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX42_s +{ + uint32_t sel : 1; /* GPIO/Loan IO42Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX42. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX42_s ALT_SYSMGR_PINMUX_GPLMUX42_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX42 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_OFST 0x27c + +/* + * Register : GPIO/LoanIO 43 Output/Output Enable Mux Selection Register - GPLMUX43 + * + * Selection between GPIO and LoanIO output and output enable for GPIO43 and + * LoanIO43. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO43Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO43Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 43. + * + * 0 : LoanIO 43 controls GPIO/LOANIO[43] output and output enable signals. + * + * 1 : GPIO 43 controls GPIO/LOANI[43] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX43_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX43. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX43_s +{ + uint32_t sel : 1; /* GPIO/Loan IO43Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX43. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX43_s ALT_SYSMGR_PINMUX_GPLMUX43_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX43 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_OFST 0x280 + +/* + * Register : GPIO/LoanIO 44 Output/Output Enable Mux Selection Register - GPLMUX44 + * + * Selection between GPIO and LoanIO output and output enable for GPIO44 and + * LoanIO44. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO44Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO44Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 44. + * + * 0 : LoanIO 44 controls GPIO/LOANIO[44] output and output enable signals. + * + * 1 : GPIO 44 controls GPIO/LOANI[44] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX44_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX44. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX44_s +{ + uint32_t sel : 1; /* GPIO/Loan IO44Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX44. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX44_s ALT_SYSMGR_PINMUX_GPLMUX44_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX44 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_OFST 0x284 + +/* + * Register : GPIO/LoanIO 45 Output/Output Enable Mux Selection Register - GPLMUX45 + * + * Selection between GPIO and LoanIO output and output enable for GPIO45 and + * LoanIO45. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO45Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO45Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 45. + * + * 0 : LoanIO 45 controls GPIO/LOANIO[45] output and output enable signals. + * + * 1 : GPIO 45 controls GPIO/LOANI[45] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX45_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX45. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX45_s +{ + uint32_t sel : 1; /* GPIO/Loan IO45Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX45. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX45_s ALT_SYSMGR_PINMUX_GPLMUX45_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX45 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_OFST 0x288 + +/* + * Register : GPIO/LoanIO 46 Output/Output Enable Mux Selection Register - GPLMUX46 + * + * Selection between GPIO and LoanIO output and output enable for GPIO46 and + * LoanIO46. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO46Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO46Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 46. + * + * 0 : LoanIO 46 controls GPIO/LOANIO[46] output and output enable signals. + * + * 1 : GPIO 46 controls GPIO/LOANI[46] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX46_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX46. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX46_s +{ + uint32_t sel : 1; /* GPIO/Loan IO46Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX46. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX46_s ALT_SYSMGR_PINMUX_GPLMUX46_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX46 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_OFST 0x28c + +/* + * Register : GPIO/LoanIO 47 Output/Output Enable Mux Selection Register - GPLMUX47 + * + * Selection between GPIO and LoanIO output and output enable for GPIO47 and + * LoanIO47. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO47Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO47Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 47. + * + * 0 : LoanIO 47 controls GPIO/LOANIO[47] output and output enable signals. + * + * 1 : GPIO 47 controls GPIO/LOANI[47] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX47_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX47. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX47_s +{ + uint32_t sel : 1; /* GPIO/Loan IO47Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX47. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX47_s ALT_SYSMGR_PINMUX_GPLMUX47_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX47 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_OFST 0x290 + +/* + * Register : GPIO/LoanIO 48 Output/Output Enable Mux Selection Register - GPLMUX48 + * + * Selection between GPIO and LoanIO output and output enable for GPIO48 and + * LoanIO48. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO48Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 48. + * + * 0 : LoanIO 48 controls GPIO/LOANIO[48] output and output enable signals. + * + * 1 : GPIO 48 controls GPIO/LOANI[48] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX48_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX48. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX48_s +{ + uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX48. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX48_s ALT_SYSMGR_PINMUX_GPLMUX48_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX48 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_OFST 0x294 + +/* + * Register : GPIO/LoanIO 49 Output/Output Enable Mux Selection Register - GPLMUX49 + * + * Selection between GPIO and LoanIO output and output enable for GPIO49 and + * LoanIO49. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO49Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 49. + * + * 0 : LoanIO 49 controls GPIO/LOANIO[49] output and output enable signals. + * + * 1 : GPIO 49 controls GPIO/LOANI[49] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX49_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX49. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX49_s +{ + uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX49. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX49_s ALT_SYSMGR_PINMUX_GPLMUX49_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX49 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_OFST 0x298 + +/* + * Register : GPIO/LoanIO 50 Output/Output Enable Mux Selection Register - GPLMUX50 + * + * Selection between GPIO and LoanIO output and output enable for GPIO50 and + * LoanIO50. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO50Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 50. + * + * 0 : LoanIO 50 controls GPIO/LOANIO[50] output and output enable signals. + * + * 1 : GPIO 50 controls GPIO/LOANI[50] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX50_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX50. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX50_s +{ + uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX50. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX50_s ALT_SYSMGR_PINMUX_GPLMUX50_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX50 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_OFST 0x29c + +/* + * Register : GPIO/LoanIO 51 Output/Output Enable Mux Selection Register - GPLMUX51 + * + * Selection between GPIO and LoanIO output and output enable for GPIO51 and + * LoanIO51. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO51Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 51. + * + * 0 : LoanIO 51 controls GPIO/LOANIO[51] output and output enable signals. + * + * 1 : GPIO 51 controls GPIO/LOANI[51] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX51_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX51. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX51_s +{ + uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX51. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX51_s ALT_SYSMGR_PINMUX_GPLMUX51_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX51 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_OFST 0x2a0 + +/* + * Register : GPIO/LoanIO 52 Output/Output Enable Mux Selection Register - GPLMUX52 + * + * Selection between GPIO and LoanIO output and output enable for GPIO52 and + * LoanIO52. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO52Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 52. + * + * 0 : LoanIO 52 controls GPIO/LOANIO[52] output and output enable signals. + * + * 1 : GPIO 52 controls GPIO/LOANI[52] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX52_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX52. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX52_s +{ + uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX52. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX52_s ALT_SYSMGR_PINMUX_GPLMUX52_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX52 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_OFST 0x2a4 + +/* + * Register : GPIO/LoanIO 53 Output/Output Enable Mux Selection Register - GPLMUX53 + * + * Selection between GPIO and LoanIO output and output enable for GPIO53 and + * LoanIO53. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO53Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 53. + * + * 0 : LoanIO 53 controls GPIO/LOANIO[53] output and output enable signals. + * + * 1 : GPIO 53 controls GPIO/LOANI[53] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX53_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX53. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX53_s +{ + uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX53. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX53_s ALT_SYSMGR_PINMUX_GPLMUX53_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX53 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_OFST 0x2a8 + +/* + * Register : GPIO/LoanIO 54 Output/Output Enable Mux Selection Register - GPLMUX54 + * + * Selection between GPIO and LoanIO output and output enable for GPIO54 and + * LoanIO54. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO54Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 54. + * + * 0 : LoanIO 54 controls GPIO/LOANIO[54] output and output enable signals. + * + * 1 : GPIO 54 controls GPIO/LOANI[54] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX54_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX54. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX54_s +{ + uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX54. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX54_s ALT_SYSMGR_PINMUX_GPLMUX54_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX54 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_OFST 0x2ac + +/* + * Register : GPIO/LoanIO 55 Output/Output Enable Mux Selection Register - GPLMUX55 + * + * Selection between GPIO and LoanIO output and output enable for GPIO55 and + * LoanIO55. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO55Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 55. + * + * 0 : LoanIO 55 controls GPIO/LOANIO[55] output and output enable signals. + * + * 1 : GPIO 55 controls GPIO/LOANI[55] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX55_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX55. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX55_s +{ + uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX55. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX55_s ALT_SYSMGR_PINMUX_GPLMUX55_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX55 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_OFST 0x2b0 + +/* + * Register : GPIO/LoanIO 56 Output/Output Enable Mux Selection Register - GPLMUX56 + * + * Selection between GPIO and LoanIO output and output enable for GPIO56 and + * LoanIO56. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO56Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 56. + * + * 0 : LoanIO 56 controls GPIO/LOANIO[56] output and output enable signals. + * + * 1 : GPIO 56 controls GPIO/LOANI[56] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX56_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX56. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX56_s +{ + uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX56. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX56_s ALT_SYSMGR_PINMUX_GPLMUX56_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX56 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_OFST 0x2b4 + +/* + * Register : GPIO/LoanIO 57 Output/Output Enable Mux Selection Register - GPLMUX57 + * + * Selection between GPIO and LoanIO output and output enable for GPIO57 and + * LoanIO57. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO57Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 57. + * + * 0 : LoanIO 57 controls GPIO/LOANIO[57] output and output enable signals. + * + * 1 : GPIO 57 controls GPIO/LOANI[57] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX57_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX57. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX57_s +{ + uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX57. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX57_s ALT_SYSMGR_PINMUX_GPLMUX57_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX57 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_OFST 0x2b8 + +/* + * Register : GPIO/LoanIO 58 Output/Output Enable Mux Selection Register - GPLMUX58 + * + * Selection between GPIO and LoanIO output and output enable for GPIO58 and + * LoanIO58. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO58Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 58. + * + * 0 : LoanIO 58 controls GPIO/LOANIO[58] output and output enable signals. + * + * 1 : GPIO 58 controls GPIO/LOANI[58] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX58_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX58. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX58_s +{ + uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX58. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX58_s ALT_SYSMGR_PINMUX_GPLMUX58_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX58 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_OFST 0x2bc + +/* + * Register : GPIO/LoanIO 59 Output/Output Enable Mux Selection Register - GPLMUX59 + * + * Selection between GPIO and LoanIO output and output enable for GPIO59 and + * LoanIO59. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO59Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 59. + * + * 0 : LoanIO 59 controls GPIO/LOANIO[59] output and output enable signals. + * + * 1 : GPIO 59 controls GPIO/LOANI[59] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX59_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX59. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX59_s +{ + uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX59. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX59_s ALT_SYSMGR_PINMUX_GPLMUX59_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX59 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_OFST 0x2c0 + +/* + * Register : GPIO/LoanIO 60 Output/Output Enable Mux Selection Register - GPLMUX60 + * + * Selection between GPIO and LoanIO output and output enable for GPIO60 and + * LoanIO60. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO60Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 60. + * + * 0 : LoanIO 60 controls GPIO/LOANIO[60] output and output enable signals. + * + * 1 : GPIO 60 controls GPIO/LOANI[60] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX60_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX60. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX60_s +{ + uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX60. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX60_s ALT_SYSMGR_PINMUX_GPLMUX60_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX60 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_OFST 0x2c4 + +/* + * Register : GPIO/LoanIO 61 Output/Output Enable Mux Selection Register - GPLMUX61 + * + * Selection between GPIO and LoanIO output and output enable for GPIO61 and + * LoanIO61. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO61Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 61. + * + * 0 : LoanIO 61 controls GPIO/LOANIO[61] output and output enable signals. + * + * 1 : GPIO 61 controls GPIO/LOANI[61] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX61_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX61. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX61_s +{ + uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX61. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX61_s ALT_SYSMGR_PINMUX_GPLMUX61_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX61 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_OFST 0x2c8 + +/* + * Register : GPIO/LoanIO 62 Output/Output Enable Mux Selection Register - GPLMUX62 + * + * Selection between GPIO and LoanIO output and output enable for GPIO62 and + * LoanIO62. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO62Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 62. + * + * 0 : LoanIO 62 controls GPIO/LOANIO[62] output and output enable signals. + * + * 1 : GPIO 62 controls GPIO/LOANI[62] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX62_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX62. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX62_s +{ + uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX62. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX62_s ALT_SYSMGR_PINMUX_GPLMUX62_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX62 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_OFST 0x2cc + +/* + * Register : GPIO/LoanIO 63 Output/Output Enable Mux Selection Register - GPLMUX63 + * + * Selection between GPIO and LoanIO output and output enable for GPIO63 and + * LoanIO63. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO63Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 63. + * + * 0 : LoanIO 63 controls GPIO/LOANIO[63] output and output enable signals. + * + * 1 : GPIO 63 controls GPIO/LOANI[63] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX63_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX63. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX63_s +{ + uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX63. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX63_s ALT_SYSMGR_PINMUX_GPLMUX63_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX63 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_OFST 0x2d0 + +/* + * Register : GPIO/LoanIO 64 Output/Output Enable Mux Selection Register - GPLMUX64 + * + * Selection between GPIO and LoanIO output and output enable for GPIO64 and + * LoanIO64. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO64Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 64. + * + * 0 : LoanIO 64 controls GPIO/LOANIO[64] output and output enable signals. + * + * 1 : GPIO 64 controls GPIO/LOANI[64] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX64_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX64. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX64_s +{ + uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX64. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX64_s ALT_SYSMGR_PINMUX_GPLMUX64_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX64 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_OFST 0x2d4 + +/* + * Register : GPIO/LoanIO 65 Output/Output Enable Mux Selection Register - GPLMUX65 + * + * Selection between GPIO and LoanIO output and output enable for GPIO65 and + * LoanIO65. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO65Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 65. + * + * 0 : LoanIO 65 controls GPIO/LOANIO[65] output and output enable signals. + * + * 1 : GPIO 65 controls GPIO/LOANI[65] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX65_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX65. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX65_s +{ + uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX65. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX65_s ALT_SYSMGR_PINMUX_GPLMUX65_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX65 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_OFST 0x2d8 + +/* + * Register : GPIO/LoanIO 66 Output/Output Enable Mux Selection Register - GPLMUX66 + * + * Selection between GPIO and LoanIO output and output enable for GPIO66 and + * LoanIO66. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO66Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 66. + * + * 0 : LoanIO 66 controls GPIO/LOANIO[66] output and output enable signals. + * + * 1 : GPIO 66 controls GPIO/LOANI[66] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX66_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX66. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX66_s +{ + uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX66. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX66_s ALT_SYSMGR_PINMUX_GPLMUX66_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX66 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_OFST 0x2dc + +/* + * Register : GPIO/LoanIO 67 Output/Output Enable Mux Selection Register - GPLMUX67 + * + * Selection between GPIO and LoanIO output and output enable for GPIO67 and + * LoanIO67. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO67Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 67. + * + * 0 : LoanIO 67 controls GPIO/LOANIO[67] output and output enable signals. + * + * 1 : GPIO 67 controls GPIO/LOANI[67] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX67_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX67. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX67_s +{ + uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX67. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX67_s ALT_SYSMGR_PINMUX_GPLMUX67_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX67 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_OFST 0x2e0 + +/* + * Register : GPIO/LoanIO 68 Output/Output Enable Mux Selection Register - GPLMUX68 + * + * Selection between GPIO and LoanIO output and output enable for GPIO68 and + * LoanIO68. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO68Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 68. + * + * 0 : LoanIO 68 controls GPIO/LOANIO[68] output and output enable signals. + * + * 1 : GPIO 68 controls GPIO/LOANI[68] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX68_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX68. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX68_s +{ + uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX68. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX68_s ALT_SYSMGR_PINMUX_GPLMUX68_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX68 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_OFST 0x2e4 + +/* + * Register : GPIO/LoanIO 69 Output/Output Enable Mux Selection Register - GPLMUX69 + * + * Selection between GPIO and LoanIO output and output enable for GPIO69 and + * LoanIO69. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO69Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 69. + * + * 0 : LoanIO 69 controls GPIO/LOANIO[69] output and output enable signals. + * + * 1 : GPIO 69 controls GPIO/LOANI[69] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX69_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX69. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX69_s +{ + uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX69. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX69_s ALT_SYSMGR_PINMUX_GPLMUX69_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX69 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_OFST 0x2e8 + +/* + * Register : GPIO/LoanIO 70 Output/Output Enable Mux Selection Register - GPLMUX70 + * + * Selection between GPIO and LoanIO output and output enable for GPIO70 and + * LoanIO70. These signals drive the Pin Mux. The Pin Mux must be configured to use + * GPIO/LoanIO in addition to these settings + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------------- + * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : GPIO/Loan IO70Input Mux Selection Field - sel + * + * Select source for GPIO/LoanIO 70. + * + * 0 : LoanIO 70 controls GPIO/LOANIO[70] output and output enable signals. + * + * 1 : GPIO 70 controls GPIO/LOANI[70] output and output enable signals. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX70_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX70. + */ +struct ALT_SYSMGR_PINMUX_GPLMUX70_s +{ + uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX70. */ +typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX70_s ALT_SYSMGR_PINMUX_GPLMUX70_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX70 register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_OFST 0x2ec + +/* + * Register : Select source for NAND signals (HPS Pins or FPGA Interface) - NANDUSEFPGA + * + * Selection between HPS Pins and FPGA Interface for NAND signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for NAND signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for NAND signals - sel + * + * Select connection for NAND. + * + * 0 : NAND uses HPS Pins. + * + * 1 : NAND uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA. + */ +struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s +{ + uint32_t sel : 1; /* Selection for NAND signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s ALT_SYSMGR_PINMUX_NANDUSEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_NANDUSEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST 0x2f0 + +/* + * Register : Select source for RGMII1 signals (HPS Pins or FPGA Interface) - RGMII1USEFPGA + * + * Selection between HPS Pins and FPGA Interface for RGMII1 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | RW | 0x0 | Selection for RGMII1 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for RGMII1 signals - sel + * + * Select connection for RGMII1. + * + * 0 : RGMII1 uses HPS Pins. + * + * 1 : RGMII1 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s +{ + uint32_t sel : 1; /* Selection for RGMII1 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST 0x2f8 + +/* + * Register : Select source for I2C0 signals (HPS Pins or FPGA Interface) - I2C0USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C0 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C0 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C0 signals - sel + * + * Select connection for I2C0. + * + * 0 : I2C0 uses HPS Pins. + * + * 1 : I2C0 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C0 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s ALT_SYSMGR_PINMUX_I2C0USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C0USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST 0x304 + +/* + * Register : Select source for RGMII0 signals (HPS Pins or FPGA Interface) - RGMII0USEFPGA + * + * Selection between HPS Pins and FPGA Interface for RGMII0 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [0] | RW | 0x0 | Selection for RGMII0 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for RGMII0 signals - sel + * + * Select connection for RGMII0. + * + * 0 : RGMII0 uses HPS Pins. + * + * 1 : RGMII0 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s +{ + uint32_t sel : 1; /* Selection for RGMII0 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST 0x314 + +/* + * Register : Select source for I2C3 signals (HPS Pins or FPGA Interface) - I2C3USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C3 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C3 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C3 signals - sel + * + * Select connection for I2C3. + * + * 0 : I2C3 uses HPS Pins. + * + * 1 : I2C3 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C3 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s ALT_SYSMGR_PINMUX_I2C3USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C3USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST 0x324 + +/* + * Register : Select source for I2C2 signals (HPS Pins or FPGA Interface) - I2C2USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C2 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C2 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C2 signals - sel + * + * Select connection for I2C2. + * + * 0 : I2C2 uses HPS Pins. + * + * 1 : I2C2 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C2 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s ALT_SYSMGR_PINMUX_I2C2USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C2USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST 0x328 + +/* + * Register : Select source for I2C1 signals (HPS Pins or FPGA Interface) - I2C1USEFPGA + * + * Selection between HPS Pins and FPGA Interface for I2C1 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------------- + * [0] | RW | 0x0 | Selection for I2C1 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for I2C1 signals - sel + * + * Select connection for I2C1. + * + * 0 : I2C1 uses HPS Pins. + * + * 1 : I2C1 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s +{ + uint32_t sel : 1; /* Selection for I2C1 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s ALT_SYSMGR_PINMUX_I2C1USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_I2C1USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST 0x32c + +/* + * Register : Select source for SPIM1 signals (HPS Pins or FPGA Interface) - SPIM1USEFPGA + * + * Selection between HPS Pins and FPGA Interface for SPIM1 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | Selection for SPIM1 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for SPIM1 signals - sel + * + * Select connection for SPIM1. + * + * 0 : SPIM1 uses HPS Pins. + * + * 1 : SPIM1 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s +{ + uint32_t sel : 1; /* Selection for SPIM1 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST 0x330 + +/* + * Register : Select source for SPIM0 signals (HPS Pins or FPGA Interface) - SPIM0USEFPGA + * + * Selection between HPS Pins and FPGA Interface for SPIM0 signals. + * + * Only reset by a cold reset (ignores warm reset). + * + * NOTE: These registers should not be modified after IO configuration.There is no + * support for dynamically changing the Pin Mux selections. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | RW | 0x0 | Selection for SPIM0 signals + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Selection for SPIM0 signals - sel + * + * Select connection for SPIM0. + * + * 0 : SPIM0 uses HPS Pins. + * + * 1 : SPIM0 uses the FPGA Inteface. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_MSB 0 +/* The width in bits of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_WIDTH 1 +/* The mask used to set the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_RESET 0x0 +/* Extracts the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL field value from a register. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value suitable for setting the register. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA. + */ +struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s +{ + uint32_t sel : 1; /* Selection for SPIM0 signals */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA. */ +typedef volatile struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA register from the beginning of the component. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST 0x338 + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR_PINMUX. + */ +struct ALT_SYSMGR_PINMUX_s +{ + volatile ALT_SYSMGR_PINMUX_EMACIO0_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */ + volatile ALT_SYSMGR_PINMUX_EMACIO1_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */ + volatile ALT_SYSMGR_PINMUX_EMACIO2_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */ + volatile ALT_SYSMGR_PINMUX_EMACIO3_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */ + volatile ALT_SYSMGR_PINMUX_EMACIO4_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */ + volatile ALT_SYSMGR_PINMUX_EMACIO5_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */ + volatile ALT_SYSMGR_PINMUX_EMACIO6_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */ + volatile ALT_SYSMGR_PINMUX_EMACIO7_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */ + volatile ALT_SYSMGR_PINMUX_EMACIO8_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */ + volatile ALT_SYSMGR_PINMUX_EMACIO9_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */ + volatile ALT_SYSMGR_PINMUX_EMACIO10_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */ + volatile ALT_SYSMGR_PINMUX_EMACIO11_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */ + volatile ALT_SYSMGR_PINMUX_EMACIO12_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */ + volatile ALT_SYSMGR_PINMUX_EMACIO13_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */ + volatile ALT_SYSMGR_PINMUX_EMACIO14_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */ + volatile ALT_SYSMGR_PINMUX_EMACIO15_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */ + volatile ALT_SYSMGR_PINMUX_EMACIO16_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */ + volatile ALT_SYSMGR_PINMUX_EMACIO17_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */ + volatile ALT_SYSMGR_PINMUX_EMACIO18_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */ + volatile ALT_SYSMGR_PINMUX_EMACIO19_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO0_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO1_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO2_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO3_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO4_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO5_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO6_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO7_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO8_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO9_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO10_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */ + volatile ALT_SYSMGR_PINMUX_FLSHIO11_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO0_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO1_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO2_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO3_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO4_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO5_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO6_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO7_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO8_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO9_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO10_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO11_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO12_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO13_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO14_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO15_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO16_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO17_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO18_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO19_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO20_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO21_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO22_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO23_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO24_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO25_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO26_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO27_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO28_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO29_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO30_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */ + volatile ALT_SYSMGR_PINMUX_GENERALIO31_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO0_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO1_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO2_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO3_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO4_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO5_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO6_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO7_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO8_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO9_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO10_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO11_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO12_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO13_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO14_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO15_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO16_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO17_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO18_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO19_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO20_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */ + volatile ALT_SYSMGR_PINMUX_MIXED1IO21_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO0_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO1_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO2_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO3_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO4_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO5_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO6_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */ + volatile ALT_SYSMGR_PINMUX_MIXED2IO7_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX48_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX49_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX50_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX51_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX52_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX53_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX54_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX55_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX56_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX57_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX58_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX59_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX60_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX61_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX62_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX63_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX64_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX65_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX66_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX67_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX68_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX69_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */ + volatile ALT_SYSMGR_PINMUX_GPLINMUX70_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX0_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX1_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX2_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX3_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX4_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX5_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX6_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX7_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX8_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX9_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX10_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX11_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX12_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX13_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX14_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX15_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX16_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX17_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX18_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX19_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX20_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX21_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX22_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX23_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX24_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX25_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX26_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX27_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX28_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX29_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX30_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX31_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX33_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX34_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX35_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX36_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX37_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX38_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX39_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX40_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX41_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX42_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX43_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX44_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX45_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX46_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX47_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX48_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX49_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX50_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX51_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX52_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX53_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX54_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX55_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX56_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX57_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX58_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX59_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX60_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX61_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX62_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX63_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX64_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX65_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX66_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX67_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX68_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX69_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */ + volatile ALT_SYSMGR_PINMUX_GPLMUX70_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */ + volatile ALT_SYSMGR_PINMUX_NANDUSEFPGA_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */ + volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */ + volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_I2C0USEFPGA_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */ + volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */ + volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_I2C3USEFPGA_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */ + volatile ALT_SYSMGR_PINMUX_I2C2USEFPGA_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */ + volatile ALT_SYSMGR_PINMUX_I2C1USEFPGA_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */ + volatile ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */ + volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */ + volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR_PINMUX. */ +typedef volatile struct ALT_SYSMGR_PINMUX_s ALT_SYSMGR_PINMUX_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */ +struct ALT_SYSMGR_PINMUX_raw_s +{ + volatile uint32_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */ + volatile uint32_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */ + volatile uint32_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */ + volatile uint32_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */ + volatile uint32_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */ + volatile uint32_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */ + volatile uint32_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */ + volatile uint32_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */ + volatile uint32_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */ + volatile uint32_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */ + volatile uint32_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */ + volatile uint32_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */ + volatile uint32_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */ + volatile uint32_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */ + volatile uint32_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */ + volatile uint32_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */ + volatile uint32_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */ + volatile uint32_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */ + volatile uint32_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */ + volatile uint32_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */ + volatile uint32_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */ + volatile uint32_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */ + volatile uint32_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */ + volatile uint32_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */ + volatile uint32_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */ + volatile uint32_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */ + volatile uint32_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */ + volatile uint32_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */ + volatile uint32_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */ + volatile uint32_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */ + volatile uint32_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */ + volatile uint32_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */ + volatile uint32_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */ + volatile uint32_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */ + volatile uint32_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */ + volatile uint32_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */ + volatile uint32_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */ + volatile uint32_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */ + volatile uint32_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */ + volatile uint32_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */ + volatile uint32_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */ + volatile uint32_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */ + volatile uint32_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */ + volatile uint32_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */ + volatile uint32_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */ + volatile uint32_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */ + volatile uint32_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */ + volatile uint32_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */ + volatile uint32_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */ + volatile uint32_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */ + volatile uint32_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */ + volatile uint32_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */ + volatile uint32_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */ + volatile uint32_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */ + volatile uint32_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */ + volatile uint32_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */ + volatile uint32_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */ + volatile uint32_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */ + volatile uint32_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */ + volatile uint32_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */ + volatile uint32_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */ + volatile uint32_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */ + volatile uint32_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */ + volatile uint32_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */ + volatile uint32_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */ + volatile uint32_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */ + volatile uint32_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */ + volatile uint32_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */ + volatile uint32_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */ + volatile uint32_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */ + volatile uint32_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */ + volatile uint32_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */ + volatile uint32_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */ + volatile uint32_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */ + volatile uint32_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */ + volatile uint32_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */ + volatile uint32_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */ + volatile uint32_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */ + volatile uint32_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */ + volatile uint32_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */ + volatile uint32_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */ + volatile uint32_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */ + volatile uint32_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */ + volatile uint32_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */ + volatile uint32_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */ + volatile uint32_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */ + volatile uint32_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */ + volatile uint32_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */ + volatile uint32_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */ + volatile uint32_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */ + volatile uint32_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */ + volatile uint32_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */ + volatile uint32_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */ + volatile uint32_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */ + volatile uint32_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */ + volatile uint32_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */ + volatile uint32_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */ + volatile uint32_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */ + volatile uint32_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */ + volatile uint32_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */ + volatile uint32_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */ + volatile uint32_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */ + volatile uint32_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */ + volatile uint32_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */ + volatile uint32_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */ + volatile uint32_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */ + volatile uint32_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */ + volatile uint32_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */ + volatile uint32_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */ + volatile uint32_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */ + volatile uint32_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */ + volatile uint32_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */ + volatile uint32_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */ + volatile uint32_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */ + volatile uint32_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */ + volatile uint32_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */ + volatile uint32_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */ + volatile uint32_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */ + volatile uint32_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */ + volatile uint32_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */ + volatile uint32_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */ + volatile uint32_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */ + volatile uint32_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */ + volatile uint32_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */ + volatile uint32_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */ + volatile uint32_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */ + volatile uint32_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */ + volatile uint32_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */ + volatile uint32_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */ + volatile uint32_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */ + volatile uint32_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */ + volatile uint32_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */ + volatile uint32_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */ + volatile uint32_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */ + volatile uint32_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */ + volatile uint32_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */ + volatile uint32_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */ + volatile uint32_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */ + volatile uint32_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */ + volatile uint32_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */ + volatile uint32_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */ + volatile uint32_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */ + volatile uint32_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */ + volatile uint32_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */ + volatile uint32_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */ + volatile uint32_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */ + volatile uint32_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */ + volatile uint32_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */ + volatile uint32_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */ + volatile uint32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */ + volatile uint32_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */ + volatile uint32_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */ + volatile uint32_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */ + volatile uint32_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */ + volatile uint32_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */ + volatile uint32_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */ + volatile uint32_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */ + volatile uint32_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */ + volatile uint32_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */ + volatile uint32_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */ + volatile uint32_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */ + volatile uint32_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */ + volatile uint32_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */ + volatile uint32_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */ + volatile uint32_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */ + volatile uint32_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */ + volatile uint32_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */ + volatile uint32_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */ + volatile uint32_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */ + volatile uint32_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */ + volatile uint32_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */ + volatile uint32_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */ + volatile uint32_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */ + volatile uint32_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */ + volatile uint32_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */ + volatile uint32_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */ + volatile uint32_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */ + volatile uint32_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */ + volatile uint32_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */ + volatile uint32_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */ + volatile uint32_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */ + volatile uint32_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */ + volatile uint32_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */ + volatile uint32_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */ + volatile uint32_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */ + volatile uint32_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */ + volatile uint32_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */ + volatile uint32_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */ + volatile uint32_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */ + volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */ + volatile uint32_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */ + volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */ + volatile uint32_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */ + volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */ + volatile uint32_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */ + volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */ + volatile uint32_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */ + volatile uint32_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */ + volatile uint32_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */ + volatile uint32_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */ + volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */ + volatile uint32_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */ + volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */ +typedef volatile struct ALT_SYSMGR_PINMUX_raw_s ALT_SYSMGR_PINMUX_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_SYSMGR. + */ +struct ALT_SYSMGR_s +{ + volatile ALT_SYSMGR_SILICONID1_t siliconid1; /* ALT_SYSMGR_SILICONID1 */ + volatile ALT_SYSMGR_SILICONID2_t siliconid2; /* ALT_SYSMGR_SILICONID2 */ + volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_WDDBG_t wddbg; /* ALT_SYSMGR_WDDBG */ + volatile ALT_SYSMGR_BOOT_t bootinfo; /* ALT_SYSMGR_BOOT */ + volatile ALT_SYSMGR_HPSINFO_t hpsinfo; /* ALT_SYSMGR_HPSINFO */ + volatile ALT_SYSMGR_PARITYINJ_t parityinj; /* ALT_SYSMGR_PARITYINJ */ + volatile ALT_SYSMGR_FPGAINTF_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */ + volatile ALT_SYSMGR_SCANMGR_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_FRZCTL_t frzctrl; /* ALT_SYSMGR_FRZCTL */ + volatile ALT_SYSMGR_EMAC_t emacgrp; /* ALT_SYSMGR_EMAC */ + volatile ALT_SYSMGR_DMA_t dmagrp; /* ALT_SYSMGR_DMA */ + volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ISW_t iswgrp; /* ALT_SYSMGR_ISW */ + volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_t romcodegrp; /* ALT_SYSMGR_ROMCODE */ + volatile ALT_SYSMGR_ROMHW_t romhwgrp; /* ALT_SYSMGR_ROMHW */ + volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */ + volatile ALT_SYSMGR_SDMMC_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */ + volatile ALT_SYSMGR_NAND_t nandgrp; /* ALT_SYSMGR_NAND */ + volatile ALT_SYSMGR_USB_t usbgrp; /* ALT_SYSMGR_USB */ + volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ECC_t eccgrp; /* ALT_SYSMGR_ECC */ + volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */ + volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_SYSMGR. */ +typedef volatile struct ALT_SYSMGR_s ALT_SYSMGR_t; +/* The struct declaration for the raw register contents of register group ALT_SYSMGR. */ +struct ALT_SYSMGR_raw_s +{ + volatile uint32_t siliconid1; /* ALT_SYSMGR_SILICONID1 */ + volatile uint32_t siliconid2; /* ALT_SYSMGR_SILICONID2 */ + volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ + volatile uint32_t wddbg; /* ALT_SYSMGR_WDDBG */ + volatile uint32_t bootinfo; /* ALT_SYSMGR_BOOT */ + volatile uint32_t hpsinfo; /* ALT_SYSMGR_HPSINFO */ + volatile uint32_t parityinj; /* ALT_SYSMGR_PARITYINJ */ + volatile ALT_SYSMGR_FPGAINTF_raw_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */ + volatile ALT_SYSMGR_SCANMGR_raw_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */ + volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_FRZCTL_raw_t frzctrl; /* ALT_SYSMGR_FRZCTL */ + volatile ALT_SYSMGR_EMAC_raw_t emacgrp; /* ALT_SYSMGR_EMAC */ + volatile ALT_SYSMGR_DMA_raw_t dmagrp; /* ALT_SYSMGR_DMA */ + volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ISW_raw_t iswgrp; /* ALT_SYSMGR_ISW */ + volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ROMCODE_raw_t romcodegrp; /* ALT_SYSMGR_ROMCODE */ + volatile ALT_SYSMGR_ROMHW_raw_t romhwgrp; /* ALT_SYSMGR_ROMHW */ + volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */ + volatile ALT_SYSMGR_SDMMC_raw_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */ + volatile ALT_SYSMGR_NAND_raw_t nandgrp; /* ALT_SYSMGR_NAND */ + volatile ALT_SYSMGR_USB_raw_t usbgrp; /* ALT_SYSMGR_USB */ + volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_ECC_raw_t eccgrp; /* ALT_SYSMGR_ECC */ + volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */ + volatile ALT_SYSMGR_PINMUX_raw_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */ + volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_SYSMGR. */ +typedef volatile struct ALT_SYSMGR_raw_s ALT_SYSMGR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_SYSMGR_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_tmr.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_tmr.h new file mode 100644 index 000000000..ccc9744a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_tmr.h @@ -0,0 +1,864 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_TMR */ + +#ifndef __ALTERA_ALT_TMR_H__ +#define __ALTERA_ALT_TMR_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : Timer Module - ALT_TMR + * Timer Module + * + * Registers in the timer module. The timer IP core supports multiple timers but it + * is configured for just one timer. The term Timer1 refers to this one timer in + * the IP core and not the module instance. + * + */ +/* + * Register : Timer1 Load Count Register - timer1loadcount + * + * Used to load counter value into Timer1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [31:0] | RW | 0x0 | Timer1LoadCount + * + */ +/* + * Field : Timer1LoadCount - timer1loadcount + * + * Value to be loaded into Timer1. This is the value from which counting commences. + * Any value written to this register is loaded into the associated timer. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */ +#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */ +#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_MSB 31 +/* The width in bits of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */ +#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_WIDTH 32 +/* The mask used to set the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value. */ +#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_SET_MSK 0xffffffff +/* The mask used to clear the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value. */ +#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_CLR_MSK 0x00000000 +/* The reset value of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */ +#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_RESET 0x0 +/* Extracts the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT field value from a register. */ +#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value suitable for setting the register. */ +#define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_TMR_TMR1LDCOUNT. + */ +struct ALT_TMR_TMR1LDCOUNT_s +{ + uint32_t timer1loadcount : 32; /* Timer1LoadCount */ +}; + +/* The typedef declaration for register ALT_TMR_TMR1LDCOUNT. */ +typedef volatile struct ALT_TMR_TMR1LDCOUNT_s ALT_TMR_TMR1LDCOUNT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_TMR_TMR1LDCOUNT register from the beginning of the component. */ +#define ALT_TMR_TMR1LDCOUNT_OFST 0x0 +/* The address of the ALT_TMR_TMR1LDCOUNT register. */ +#define ALT_TMR_TMR1LDCOUNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1LDCOUNT_OFST)) + +/* + * Register : Timer1 Current Value Register - timer1currentval + * + * Provides current value of Timer1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [31:0] | R | 0x0 | Timer1 Current Value + * + */ +/* + * Field : Timer1 Current Value - timer1currentval + * + * Current value of Timer1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */ +#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */ +#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_MSB 31 +/* The width in bits of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */ +#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_WIDTH 32 +/* The mask used to set the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value. */ +#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_SET_MSK 0xffffffff +/* The mask used to clear the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value. */ +#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_CLR_MSK 0x00000000 +/* The reset value of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */ +#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_RESET 0x0 +/* Extracts the ALT_TMR_TMR1CURVAL_TMR1CURVAL field value from a register. */ +#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value suitable for setting the register. */ +#define ALT_TMR_TMR1CURVAL_TMR1CURVAL_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_TMR_TMR1CURVAL. + */ +struct ALT_TMR_TMR1CURVAL_s +{ + const uint32_t timer1currentval : 32; /* Timer1 Current Value */ +}; + +/* The typedef declaration for register ALT_TMR_TMR1CURVAL. */ +typedef volatile struct ALT_TMR_TMR1CURVAL_s ALT_TMR_TMR1CURVAL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_TMR_TMR1CURVAL register from the beginning of the component. */ +#define ALT_TMR_TMR1CURVAL_OFST 0x4 +/* The address of the ALT_TMR_TMR1CURVAL register. */ +#define ALT_TMR_TMR1CURVAL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1CURVAL_OFST)) + +/* + * Register : Timer1 Control Register - timer1controlreg + * + * This register controls enabling, operating mode (free-running or user-defined- + * count), and interrupt mask of Timer1. You can program this register to enable or + * disable Timer1 and to control its mode of operation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [0] | RW | 0x0 | Timer1 Enable + * [1] | RW | 0x0 | Timer1 Mode + * [2] | RW | 0x0 | Timer1 Interrupt Mask + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timer1 Enable - timer1_enable + * + * Timer1 enable/disable bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------- + * ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD | 0x0 | Timer1 Disabled + * ALT_TMR_TMR1CTLREG_TMR1_EN_E_END | 0x1 | Timer1 Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_EN + * + * Timer1 Disabled + */ +#define ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_EN + * + * Timer1 Enabled + */ +#define ALT_TMR_TMR1CTLREG_TMR1_EN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_EN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_EN_MSB 0 +/* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_EN_WIDTH 1 +/* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_EN register field value. */ +#define ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_EN register field value. */ +#define ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_EN_RESET 0x0 +/* Extracts the ALT_TMR_TMR1CTLREG_TMR1_EN field value from a register. */ +#define ALT_TMR_TMR1CTLREG_TMR1_EN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_TMR_TMR1CTLREG_TMR1_EN register field value suitable for setting the register. */ +#define ALT_TMR_TMR1CTLREG_TMR1_EN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Timer1 Mode - timer1_mode + * + * Sets operating mode. + * + * NOTE: You must set the timer1loadcount register to all ones before enabling the + * timer in free-running mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------ + * ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN | 0x0 | Free-running mode + * ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF | 0x1 | User-defined count mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_MOD + * + * Free-running mode + */ +#define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN 0x0 +/* + * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_MOD + * + * User-defined count mode + */ +#define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_MOD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_MOD_MSB 1 +/* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_MOD_WIDTH 1 +/* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_MOD register field value. */ +#define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_MOD register field value. */ +#define ALT_TMR_TMR1CTLREG_TMR1_MOD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_MOD_RESET 0x0 +/* Extracts the ALT_TMR_TMR1CTLREG_TMR1_MOD field value from a register. */ +#define ALT_TMR_TMR1CTLREG_TMR1_MOD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_TMR_TMR1CTLREG_TMR1_MOD register field value suitable for setting the register. */ +#define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Timer1 Interrupt Mask - timer1_interrupt_mask + * + * Timer1 interrupt mask + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED | 0x0 | interrupt not masked (enabled) + * ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED | 0x1 | interrupt masked (disabled) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_INT_MSK + * + * interrupt not masked (enabled) + */ +#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED 0x0 +/* + * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_INT_MSK + * + * interrupt masked (disabled) + */ +#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_MSB 2 +/* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_WIDTH 1 +/* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value. */ +#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value. */ +#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */ +#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_RESET 0x0 +/* Extracts the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK field value from a register. */ +#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value suitable for setting the register. */ +#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_TMR_TMR1CTLREG. + */ +struct ALT_TMR_TMR1CTLREG_s +{ + uint32_t timer1_enable : 1; /* Timer1 Enable */ + uint32_t timer1_mode : 1; /* Timer1 Mode */ + uint32_t timer1_interrupt_mask : 1; /* Timer1 Interrupt Mask */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_TMR_TMR1CTLREG. */ +typedef volatile struct ALT_TMR_TMR1CTLREG_s ALT_TMR_TMR1CTLREG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_TMR_TMR1CTLREG register from the beginning of the component. */ +#define ALT_TMR_TMR1CTLREG_OFST 0x8 +/* The address of the ALT_TMR_TMR1CTLREG register. */ +#define ALT_TMR_TMR1CTLREG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1CTLREG_OFST)) + +/* + * Register : Timer1 End-of-Interrupt Register - timer1eoi + * + * Clears Timer1 interrupt when read. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | R | 0x0 | Timer1 End of Interrupt + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timer1 End of Interrupt - timer1eoi + * + * Reading from this register clears the interrupt from Timer1 and returns 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1EOI_TMR1EOI register field. */ +#define ALT_TMR_TMR1EOI_TMR1EOI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1EOI_TMR1EOI register field. */ +#define ALT_TMR_TMR1EOI_TMR1EOI_MSB 0 +/* The width in bits of the ALT_TMR_TMR1EOI_TMR1EOI register field. */ +#define ALT_TMR_TMR1EOI_TMR1EOI_WIDTH 1 +/* The mask used to set the ALT_TMR_TMR1EOI_TMR1EOI register field value. */ +#define ALT_TMR_TMR1EOI_TMR1EOI_SET_MSK 0x00000001 +/* The mask used to clear the ALT_TMR_TMR1EOI_TMR1EOI register field value. */ +#define ALT_TMR_TMR1EOI_TMR1EOI_CLR_MSK 0xfffffffe +/* The reset value of the ALT_TMR_TMR1EOI_TMR1EOI register field. */ +#define ALT_TMR_TMR1EOI_TMR1EOI_RESET 0x0 +/* Extracts the ALT_TMR_TMR1EOI_TMR1EOI field value from a register. */ +#define ALT_TMR_TMR1EOI_TMR1EOI_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_TMR_TMR1EOI_TMR1EOI register field value suitable for setting the register. */ +#define ALT_TMR_TMR1EOI_TMR1EOI_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_TMR_TMR1EOI. + */ +struct ALT_TMR_TMR1EOI_s +{ + const uint32_t timer1eoi : 1; /* Timer1 End of Interrupt */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_TMR_TMR1EOI. */ +typedef volatile struct ALT_TMR_TMR1EOI_s ALT_TMR_TMR1EOI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_TMR_TMR1EOI register from the beginning of the component. */ +#define ALT_TMR_TMR1EOI_OFST 0xc +/* The address of the ALT_TMR_TMR1EOI register. */ +#define ALT_TMR_TMR1EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1EOI_OFST)) + +/* + * Register : Timer1 Interrupt Status Register - timer1intstat + * + * Provides the interrupt status of Timer1 after masking. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | R | 0x0 | Timer1 Interrupt Status + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timer1 Interrupt Status - timer1intstat + * + * Provides the interrupt status for Timer1. The status reported is after the + * interrupt mask has been applied. Reading from this register does not clear any + * active interrupts. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------- + * ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_INACT | 0x0 | Timer1 interrupt is not active + * ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_ACT | 0x1 | Timer1 interrupt is active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_TMR_TMR1INTSTAT_TMR1INTSTAT + * + * Timer1 interrupt is not active + */ +#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_TMR_TMR1INTSTAT_TMR1INTSTAT + * + * Timer1 interrupt is active + */ +#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */ +#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */ +#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_MSB 0 +/* The width in bits of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */ +#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_WIDTH 1 +/* The mask used to set the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value. */ +#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value. */ +#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */ +#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_RESET 0x0 +/* Extracts the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT field value from a register. */ +#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value suitable for setting the register. */ +#define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_TMR_TMR1INTSTAT. + */ +struct ALT_TMR_TMR1INTSTAT_s +{ + const uint32_t timer1intstat : 1; /* Timer1 Interrupt Status */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_TMR_TMR1INTSTAT. */ +typedef volatile struct ALT_TMR_TMR1INTSTAT_s ALT_TMR_TMR1INTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_TMR_TMR1INTSTAT register from the beginning of the component. */ +#define ALT_TMR_TMR1INTSTAT_OFST 0x10 +/* The address of the ALT_TMR_TMR1INTSTAT register. */ +#define ALT_TMR_TMR1INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1INTSTAT_OFST)) + +/* + * Register : Timers Interrupt Status Register - timersintstat + * + * Provides the interrupt status for all timers after masking. Because there is + * only Timer1 in this module instance, this status is the same as timer1intstat. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | R | 0x0 | Timers Interrupt Status + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timers Interrupt Status - timersintstat + * + * Provides the interrupt status for Timer1. Because there is only Timer1 in this + * module instance, this status is the same as timer1intstat. The status reported + * is after the interrupt mask has been applied. Reading from this register does + * not clear any active interrupts. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------- + * ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_INACT | 0x0 | timer_intr is not active + * ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_ACT | 0x1 | timer_intr is active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_TMR_TMRSINTSTAT_TMRSINTSTAT + * + * timer_intr is not active + */ +#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_TMR_TMRSINTSTAT_TMRSINTSTAT + * + * timer_intr is active + */ +#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */ +#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */ +#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_MSB 0 +/* The width in bits of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */ +#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_WIDTH 1 +/* The mask used to set the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value. */ +#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value. */ +#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */ +#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_RESET 0x0 +/* Extracts the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT field value from a register. */ +#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value suitable for setting the register. */ +#define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_TMR_TMRSINTSTAT. + */ +struct ALT_TMR_TMRSINTSTAT_s +{ + const uint32_t timersintstat : 1; /* Timers Interrupt Status */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_TMR_TMRSINTSTAT. */ +typedef volatile struct ALT_TMR_TMRSINTSTAT_s ALT_TMR_TMRSINTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_TMR_TMRSINTSTAT register from the beginning of the component. */ +#define ALT_TMR_TMRSINTSTAT_OFST 0xa0 +/* The address of the ALT_TMR_TMRSINTSTAT register. */ +#define ALT_TMR_TMRSINTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSINTSTAT_OFST)) + +/* + * Register : Timers End-of-Interrupt Register - timerseoi + * + * Clears Timer1 interrupt when read. Because there is only Timer1 in this module + * instance, reading this register has the same effect as reading timer1eoi. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [0] | R | 0x0 | Timers End-of-Interrupt + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timers End-of-Interrupt - timerseoi + * + * Reading from this register clears the interrupt all timers and returns 0. + * Because there is only Timer1 in this module instance, reading this register has + * the same effect as reading timer1eoi. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSEOI_TMRSEOI register field. */ +#define ALT_TMR_TMRSEOI_TMRSEOI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSEOI_TMRSEOI register field. */ +#define ALT_TMR_TMRSEOI_TMRSEOI_MSB 0 +/* The width in bits of the ALT_TMR_TMRSEOI_TMRSEOI register field. */ +#define ALT_TMR_TMRSEOI_TMRSEOI_WIDTH 1 +/* The mask used to set the ALT_TMR_TMRSEOI_TMRSEOI register field value. */ +#define ALT_TMR_TMRSEOI_TMRSEOI_SET_MSK 0x00000001 +/* The mask used to clear the ALT_TMR_TMRSEOI_TMRSEOI register field value. */ +#define ALT_TMR_TMRSEOI_TMRSEOI_CLR_MSK 0xfffffffe +/* The reset value of the ALT_TMR_TMRSEOI_TMRSEOI register field. */ +#define ALT_TMR_TMRSEOI_TMRSEOI_RESET 0x0 +/* Extracts the ALT_TMR_TMRSEOI_TMRSEOI field value from a register. */ +#define ALT_TMR_TMRSEOI_TMRSEOI_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_TMR_TMRSEOI_TMRSEOI register field value suitable for setting the register. */ +#define ALT_TMR_TMRSEOI_TMRSEOI_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_TMR_TMRSEOI. + */ +struct ALT_TMR_TMRSEOI_s +{ + const uint32_t timerseoi : 1; /* Timers End-of-Interrupt */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_TMR_TMRSEOI. */ +typedef volatile struct ALT_TMR_TMRSEOI_s ALT_TMR_TMRSEOI_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_TMR_TMRSEOI register from the beginning of the component. */ +#define ALT_TMR_TMRSEOI_OFST 0xa4 +/* The address of the ALT_TMR_TMRSEOI register. */ +#define ALT_TMR_TMRSEOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSEOI_OFST)) + +/* + * Register : Timers Raw Interrupt Status Register - timersrawintstat + * + * Provides the interrupt status for all timers before masking. Note that there is + * only Timer1 in this module instance. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------- + * [0] | R | 0x0 | Timers Raw Interrupt Status + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Timers Raw Interrupt Status - timersrawintstat + * + * Provides the interrupt status for Timer1. Because there is only Timer1 in this + * module instance, this status is the same as timer1intstat. The status reported + * is before the interrupt mask has been applied. Reading from this register does + * not clear any active interrupts. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------- + * ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_INACT | 0x0 | Timer1 interrupt is not active + * ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_ACT | 0x1 | Timer1 interrupt is active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT + * + * Timer1 interrupt is not active + */ +#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT + * + * Timer1 interrupt is active + */ +#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */ +#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */ +#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_MSB 0 +/* The width in bits of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */ +#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_WIDTH 1 +/* The mask used to set the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value. */ +#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_SET_MSK 0x00000001 +/* The mask used to clear the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value. */ +#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_CLR_MSK 0xfffffffe +/* The reset value of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */ +#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_RESET 0x0 +/* Extracts the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT field value from a register. */ +#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value suitable for setting the register. */ +#define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_TMR_TMRSRAWINTSTAT. + */ +struct ALT_TMR_TMRSRAWINTSTAT_s +{ + const uint32_t timersrawintstat : 1; /* Timers Raw Interrupt Status */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_TMR_TMRSRAWINTSTAT. */ +typedef volatile struct ALT_TMR_TMRSRAWINTSTAT_s ALT_TMR_TMRSRAWINTSTAT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_TMR_TMRSRAWINTSTAT register from the beginning of the component. */ +#define ALT_TMR_TMRSRAWINTSTAT_OFST 0xa8 +/* The address of the ALT_TMR_TMRSRAWINTSTAT register. */ +#define ALT_TMR_TMRSRAWINTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSRAWINTSTAT_OFST)) + +/* + * Register : Timers Component Version Register - timerscompversion + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------------------- + * [31:0] | R | 0x3230352a | Timers Component Version + * + */ +/* + * Field : Timers Component Version - timerscompversion + * + * Current revision number of the timers component. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */ +#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */ +#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_MSB 31 +/* The width in bits of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */ +#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_WIDTH 32 +/* The mask used to set the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value. */ +#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_SET_MSK 0xffffffff +/* The mask used to clear the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value. */ +#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_CLR_MSK 0x00000000 +/* The reset value of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */ +#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_RESET 0x3230352a +/* Extracts the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER field value from a register. */ +#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value suitable for setting the register. */ +#define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_TMR_TMRSCOMPVER. + */ +struct ALT_TMR_TMRSCOMPVER_s +{ + const uint32_t timerscompversion : 32; /* Timers Component Version */ +}; + +/* The typedef declaration for register ALT_TMR_TMRSCOMPVER. */ +typedef volatile struct ALT_TMR_TMRSCOMPVER_s ALT_TMR_TMRSCOMPVER_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_TMR_TMRSCOMPVER register from the beginning of the component. */ +#define ALT_TMR_TMRSCOMPVER_OFST 0xac +/* The address of the ALT_TMR_TMRSCOMPVER register. */ +#define ALT_TMR_TMRSCOMPVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSCOMPVER_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_TMR. + */ +struct ALT_TMR_s +{ + volatile ALT_TMR_TMR1LDCOUNT_t timer1loadcount; /* ALT_TMR_TMR1LDCOUNT */ + volatile ALT_TMR_TMR1CURVAL_t timer1currentval; /* ALT_TMR_TMR1CURVAL */ + volatile ALT_TMR_TMR1CTLREG_t timer1controlreg; /* ALT_TMR_TMR1CTLREG */ + volatile ALT_TMR_TMR1EOI_t timer1eoi; /* ALT_TMR_TMR1EOI */ + volatile ALT_TMR_TMR1INTSTAT_t timer1intstat; /* ALT_TMR_TMR1INTSTAT */ + volatile uint32_t _pad_0x14_0x9f[35]; /* *UNDEFINED* */ + volatile ALT_TMR_TMRSINTSTAT_t timersintstat; /* ALT_TMR_TMRSINTSTAT */ + volatile ALT_TMR_TMRSEOI_t timerseoi; /* ALT_TMR_TMRSEOI */ + volatile ALT_TMR_TMRSRAWINTSTAT_t timersrawintstat; /* ALT_TMR_TMRSRAWINTSTAT */ + volatile ALT_TMR_TMRSCOMPVER_t timerscompversion; /* ALT_TMR_TMRSCOMPVER */ + volatile uint32_t _pad_0xb0_0x100[20]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_TMR. */ +typedef volatile struct ALT_TMR_s ALT_TMR_t; +/* The struct declaration for the raw register contents of register group ALT_TMR. */ +struct ALT_TMR_raw_s +{ + volatile uint32_t timer1loadcount; /* ALT_TMR_TMR1LDCOUNT */ + volatile uint32_t timer1currentval; /* ALT_TMR_TMR1CURVAL */ + volatile uint32_t timer1controlreg; /* ALT_TMR_TMR1CTLREG */ + volatile uint32_t timer1eoi; /* ALT_TMR_TMR1EOI */ + volatile uint32_t timer1intstat; /* ALT_TMR_TMR1INTSTAT */ + volatile uint32_t _pad_0x14_0x9f[35]; /* *UNDEFINED* */ + volatile uint32_t timersintstat; /* ALT_TMR_TMRSINTSTAT */ + volatile uint32_t timerseoi; /* ALT_TMR_TMRSEOI */ + volatile uint32_t timersrawintstat; /* ALT_TMR_TMRSRAWINTSTAT */ + volatile uint32_t timerscompversion; /* ALT_TMR_TMRSCOMPVER */ + volatile uint32_t _pad_0xb0_0x100[20]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_TMR. */ +typedef volatile struct ALT_TMR_raw_s ALT_TMR_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_TMR_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_uart.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_uart.h new file mode 100644 index 000000000..322553e31 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_uart.h @@ -0,0 +1,5158 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_UART */ + +#ifndef __ALTERA_ALT_UART_H__ +#define __ALTERA_ALT_UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : UART Module - ALT_UART + * UART Module + * + * Registers in the UART module + * + */ +/* + * Register : Rx Buffer, Tx Holding, and Divisor Latch Low - rbr_thr_dll + * + * This is a multi-function register. This register holds receives and transmit + * data and controls the least-signficant 8 bits of the baud rate divisor. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [7:0] | RW | 0x0 | Value + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Value - value + * + * Receive Buffer Register: + * + * This register contains the data byte received on the serial input port + * (uart_rxd). The data in this register is valid only if the Data Ready ( bit [0] + * in the Line Status Register(LSR)) is set to 1. If FIFOs are disabled(bit[0] of + * Register FCR is set to 0) the data in the RBR must be read before the next data + * arrives, otherwise it will be overwritten, resulting in an overrun error. If + * FIFOs are enabled(bit [0] of Register FCR is set to 1) this register accesses + * the head of the receive FIFO. If the receive FIFO is full, and this register is + * not read before the next data character arrives, then the data already in the + * FIFO will be preserved but any incoming data will be lost. An overrun error will + * also occur. + * + * Transmit Holding Register: + * + * This register contains data to be transmitted on the serial output port. Data + * should only be written to the THR when the THR Empty bit [5] of the LSR Register + * is set to 1. If FIFOs are disabled (bit [0] of Register FCR) is set to 0 and + * THRE is set to 1, writing a single character to the THR clears the THRE. Any + * additional writes to the THR before the THRE is set again causes the THR data to + * be overwritten. If FIFO's are enabled bit [0] of Register FCR is set to 1 and + * THRE is set up to 128 characters of data may be written to the THR before the + * FIFO is full. Any attempt to write data when the FIFO is full results in the + * write data being lost. + * + * Divisor Latch Low: + * + * This register makes up the lower 8-bits of a 16-bit, Read/write, Divisor Latch + * register that contains the baud rate divisor for the UART. This register may + * only be accessed when the DLAB bit [7] of the LCR Register is set to 1. The + * output baud rate is equal to the serial clock l4_sp_clk frequency divided by + * sixteen times the value of the baud rate divisor, as follows: + * + * baud rate = (serial clock freq) / (16 * divisor) + * + * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud + * clock is disabled and no serial communications will occur. Also, once the DLL is + * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before + * transmitting or receiving data. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_MSB 7 +/* The width in bits of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8 +/* The mask used to set the ALT_UART_RBR_THR_DLL_VALUE register field value. */ +#define ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_RBR_THR_DLL_VALUE register field value. */ +#define ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_RBR_THR_DLL_VALUE register field. */ +#define ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0 +/* Extracts the ALT_UART_RBR_THR_DLL_VALUE field value from a register. */ +#define ALT_UART_RBR_THR_DLL_VALUE_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_RBR_THR_DLL_VALUE register field value suitable for setting the register. */ +#define ALT_UART_RBR_THR_DLL_VALUE_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_RBR_THR_DLL. + */ +struct ALT_UART_RBR_THR_DLL_s +{ + uint32_t value : 8; /* Value */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_RBR_THR_DLL. */ +typedef volatile struct ALT_UART_RBR_THR_DLL_s ALT_UART_RBR_THR_DLL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_RBR_THR_DLL register from the beginning of the component. */ +#define ALT_UART_RBR_THR_DLL_OFST 0x0 +/* The address of the ALT_UART_RBR_THR_DLL register. */ +#define ALT_UART_RBR_THR_DLL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_THR_DLL_OFST)) + +/* + * Register : Interrupt Enable and Divisor Latch High - ier_dlh + * + * This is a multi-function register. This register enables/disables receive and + * transmit interrupts and also controls the most-significant 8-bits of the baud + * rate divisor. + * + * Divisor Latch High Register: + * + * This register is accessed when the DLAB bit [7] of the LCR Register is set to + * 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output + * baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen + * times the value of the baud rate divisor, as follows: + * + * baud rate = (serial clock freq) / (16 * divisor): + * + * Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud + * clock is disabled and no serial communications will occur. Also, once the DLL is + * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before + * transmitting or receiving data. + * + * Interrupt Enable Register: + * + * This register may only be accessed when the DLAB bit [7] of the LCR Register is + * set to 0.Allows control of the Interrupt Enables for transmit and receive + * functions. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------------------- + * [0] | RW | 0x0 | DLH[0] and Receive Data Interrupt Enable + * [1] | RW | 0x0 | DLH[1] and Transmit Data Interrupt Control + * [2] | RW | 0x0 | DLH[2] and Enable Receiver Line Status + * [3] | RW | 0x0 | DLH[3] and Enable Modem Status Interrupt + * [4] | RW | 0x0 | DLH[4] + * [5] | RW | 0x0 | DLH[5] + * [6] | RW | 0x0 | DLH[6] + * [7] | RW | 0x0 | DLH[7] and PTIME THRE Interrupt Mode Enable + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DLH[0] and Receive Data Interrupt Enable - erbfi_dlh0 + * + * Divisor Latch High Register: + * + * Bit 0 of DLH value. + * + * Interrupt Enable Register: + * + * Used to enable/disable the generation of the Receive Data Available Interrupt + * and the Character Timeout Interrupt(if FIFO's enabled). These are the second + * highest priority interrupts. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------ + * ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD | 0x0 | Interrupt Disable + * ALT_UART_IER_DLH_ERBFI_DLH0_E_END | 0x1 | Interrupt Enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0 + * + * Interrupt Disable + */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0 + * + * Interrupt Enable + */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_MSB 0 +/* The width in bits of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_ERBFI_DLH0 field value from a register. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_IER_DLH_ERBFI_DLH0 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_ERBFI_DLH0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : DLH[1] and Transmit Data Interrupt Control - etbei_dlhl + * + * Divisor Latch High Register: + * + * Bit 1 of DLH value. + * + * Interrupt Enable Register: + * + * Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable + * the generation of Transmitter Holding Register Empty Interrupt. This is the + * third highest priority interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD | 0x0 | Tx disable + * ALT_UART_IER_DLH_ETBEI_DLHL_E_END | 0x1 | Tx enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL + * + * Tx disable + */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL + * + * Tx enable + */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_MSB 1 +/* The width in bits of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_ETBEI_DLHL field value from a register. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_IER_DLH_ETBEI_DLHL register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_ETBEI_DLHL_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : DLH[2] and Enable Receiver Line Status - elsi_dhl2 + * + * Divisor Latch High Register: + * + * Bit 2 of DLH value. + * + * Interrupt Enable Register: + * + * This is used to enable/disable the generation of Receiver Line Status Interrupt. + * This is the highest priority interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------- + * ALT_UART_IER_DLH_ELSI_DHL2_E_DISD | 0x0 | Disable interrupt line stat + * ALT_UART_IER_DLH_ELSI_DHL2_E_END | 0x1 | Enable interrupt line stat + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2 + * + * Disable interrupt line stat + */ +#define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2 + * + * Enable interrupt line stat + */ +#define ALT_UART_IER_DLH_ELSI_DHL2_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_MSB 2 +/* The width in bits of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_ELSI_DHL2 field value from a register. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_IER_DLH_ELSI_DHL2 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_ELSI_DHL2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DLH[3] and Enable Modem Status Interrupt - edssi_dhl3 + * + * Divisor Latch High Register: + * + * Bit 3 of DLH value. + * + * Interrupt Enable Register: + * + * This is used to enable/disable the generation of Modem Status Interrupts. This + * is the fourth highest priority interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------- + * ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD | 0x0 | disable modem status interrupt + * ALT_UART_IER_DLH_EDSSI_DHL3_E_END | 0x1 | enable modem status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3 + * + * disable modem status interrupt + */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3 + * + * enable modem status interrupt + */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_MSB 3 +/* The width in bits of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_EDSSI_DHL3 field value from a register. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_IER_DLH_EDSSI_DHL3 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_EDSSI_DHL3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : DLH[4] - dlh4 + * + * Bit 4 of DLH value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_MSB 4 +/* The width in bits of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_DLH4 register field value. */ +#define ALT_UART_IER_DLH_DLH4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_IER_DLH_DLH4 register field value. */ +#define ALT_UART_IER_DLH_DLH4_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_IER_DLH_DLH4 register field. */ +#define ALT_UART_IER_DLH_DLH4_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_DLH4 field value from a register. */ +#define ALT_UART_IER_DLH_DLH4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_IER_DLH_DLH4 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_DLH4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : DLH[5] - dlh5 + * + * Bit 5 of DLH value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_MSB 5 +/* The width in bits of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_DLH5 register field value. */ +#define ALT_UART_IER_DLH_DLH5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_IER_DLH_DLH5 register field value. */ +#define ALT_UART_IER_DLH_DLH5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_IER_DLH_DLH5 register field. */ +#define ALT_UART_IER_DLH_DLH5_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_DLH5 field value from a register. */ +#define ALT_UART_IER_DLH_DLH5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_IER_DLH_DLH5 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_DLH5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : DLH[6] - dlh6 + * + * Bit 6 of DLH value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_MSB 6 +/* The width in bits of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_DLH6 register field value. */ +#define ALT_UART_IER_DLH_DLH6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_IER_DLH_DLH6 register field value. */ +#define ALT_UART_IER_DLH_DLH6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_IER_DLH_DLH6 register field. */ +#define ALT_UART_IER_DLH_DLH6_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_DLH6 field value from a register. */ +#define ALT_UART_IER_DLH_DLH6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_IER_DLH_DLH6 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_DLH6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : DLH[7] and PTIME THRE Interrupt Mode Enable - ptime_dlh7 + * + * Divisor Latch High Register: + * + * Bit 7 of DLH value. + * + * Interrupt Enable Register: + * + * This is used to enable/disable the generation of THRE Interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------ + * ALT_UART_IER_DLH_PTIME_DLH7_E_DISD | 0x0 | disable tx-hold-reg-empty interrupt + * ALT_UART_IER_DLH_PTIME_DLH7_E_END | 0x1 | enable tx-hold-reg-empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7 + * + * disable tx-hold-reg-empty interrupt + */ +#define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7 + * + * enable tx-hold-reg-empty interrupt + */ +#define ALT_UART_IER_DLH_PTIME_DLH7_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_MSB 7 +/* The width in bits of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH 1 +/* The mask used to set the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_RESET 0x0 +/* Extracts the ALT_UART_IER_DLH_PTIME_DLH7 field value from a register. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_IER_DLH_PTIME_DLH7 register field value suitable for setting the register. */ +#define ALT_UART_IER_DLH_PTIME_DLH7_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_IER_DLH. + */ +struct ALT_UART_IER_DLH_s +{ + uint32_t erbfi_dlh0 : 1; /* DLH[0] and Receive Data Interrupt Enable */ + uint32_t etbei_dlhl : 1; /* DLH[1] and Transmit Data Interrupt Control */ + uint32_t elsi_dhl2 : 1; /* DLH[2] and Enable Receiver Line Status */ + uint32_t edssi_dhl3 : 1; /* DLH[3] and Enable Modem Status Interrupt */ + uint32_t dlh4 : 1; /* DLH[4] */ + uint32_t dlh5 : 1; /* DLH[5] */ + uint32_t dlh6 : 1; /* DLH[6] */ + uint32_t ptime_dlh7 : 1; /* DLH[7] and PTIME THRE Interrupt Mode Enable */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_IER_DLH. */ +typedef volatile struct ALT_UART_IER_DLH_s ALT_UART_IER_DLH_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_IER_DLH register from the beginning of the component. */ +#define ALT_UART_IER_DLH_OFST 0x4 +/* The address of the ALT_UART_IER_DLH register. */ +#define ALT_UART_IER_DLH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_DLH_OFST)) + +/* + * Register : Interrupt Identity Register (when read) - iir + * + * Returns interrupt identification and FIFO enable/disable when read. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [3:0] | R | 0x1 | Interrupt ID + * [5:4] | ??? | 0x0 | *UNDEFINED* + * [7:6] | R | 0x0 | FIFO Enabled + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Interrupt ID - id + * + * This indicates the highest priority pending interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------- + * ALT_UART_IIR_ID_E_MODMSTAT | 0x0 | Modem status + * ALT_UART_IIR_ID_E_NOINTRPENDING | 0x1 | No Interrupt pending + * ALT_UART_IIR_ID_E_THREMPTY | 0x2 | THR empty + * ALT_UART_IIR_ID_E_RXDATAVAILABLE | 0x4 | Receive data available + * ALT_UART_IIR_ID_E_RXLINESTAT | 0x6 | Receive line status + * ALT_UART_IIR_ID_E_CHARTMO | 0xc | Character timeout + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Modem status + */ +#define ALT_UART_IIR_ID_E_MODMSTAT 0x0 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * No Interrupt pending + */ +#define ALT_UART_IIR_ID_E_NOINTRPENDING 0x1 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * THR empty + */ +#define ALT_UART_IIR_ID_E_THREMPTY 0x2 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Receive data available + */ +#define ALT_UART_IIR_ID_E_RXDATAVAILABLE 0x4 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Receive line status + */ +#define ALT_UART_IIR_ID_E_RXLINESTAT 0x6 +/* + * Enumerated value for register field ALT_UART_IIR_ID + * + * Character timeout + */ +#define ALT_UART_IIR_ID_E_CHARTMO 0xc + +/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_MSB 3 +/* The width in bits of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_WIDTH 4 +/* The mask used to set the ALT_UART_IIR_ID register field value. */ +#define ALT_UART_IIR_ID_SET_MSK 0x0000000f +/* The mask used to clear the ALT_UART_IIR_ID register field value. */ +#define ALT_UART_IIR_ID_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_UART_IIR_ID register field. */ +#define ALT_UART_IIR_ID_RESET 0x1 +/* Extracts the ALT_UART_IIR_ID field value from a register. */ +#define ALT_UART_IIR_ID_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_UART_IIR_ID register field value suitable for setting the register. */ +#define ALT_UART_IIR_ID_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : FIFO Enabled - fifoen + * + * This is used to indicate whether the FIFO's are enabled or disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:-------------- + * ALT_UART_IIR_FIFOEN_E_DISD | 0x0 | FIFO disabled + * ALT_UART_IIR_FIFOEN_E_END | 0x3 | FIFO enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_IIR_FIFOEN + * + * FIFO disabled + */ +#define ALT_UART_IIR_FIFOEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_IIR_FIFOEN + * + * FIFO enabled + */ +#define ALT_UART_IIR_FIFOEN_E_END 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_MSB 7 +/* The width in bits of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_WIDTH 2 +/* The mask used to set the ALT_UART_IIR_FIFOEN register field value. */ +#define ALT_UART_IIR_FIFOEN_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_UART_IIR_FIFOEN register field value. */ +#define ALT_UART_IIR_FIFOEN_CLR_MSK 0xffffff3f +/* The reset value of the ALT_UART_IIR_FIFOEN register field. */ +#define ALT_UART_IIR_FIFOEN_RESET 0x0 +/* Extracts the ALT_UART_IIR_FIFOEN field value from a register. */ +#define ALT_UART_IIR_FIFOEN_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_UART_IIR_FIFOEN register field value suitable for setting the register. */ +#define ALT_UART_IIR_FIFOEN_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_IIR. + */ +struct ALT_UART_IIR_s +{ + const uint32_t id : 4; /* Interrupt ID */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t fifoen : 2; /* FIFO Enabled */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_IIR. */ +typedef volatile struct ALT_UART_IIR_s ALT_UART_IIR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_IIR register from the beginning of the component. */ +#define ALT_UART_IIR_OFST 0x8 +/* The address of the ALT_UART_IIR register. */ +#define ALT_UART_IIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IIR_OFST)) + +/* + * Register : FIFO Control (when written) - fcr + * + * Controls FIFO Operations when written. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:----------------------- + * [0] | W | Unknown | FIFO Enable + * [1] | W | Unknown | Rx FIFO Reset + * [2] | W | Unknown | Tx FIFO Reset + * [3] | W | Unknown | DMA Mode + * [5:4] | W | Unknown | Tx Empty Trigger Level + * [7:6] | W | Unknown | Rx Trigger Level + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FIFO Enable - fifoe + * + * Enables/disables the transmit (Tx) and receive (Rx ) FIFO's. Whenever the value + * of this bit is changed both the Tx and Rx controller portion of FIFO's will be + * reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:--------------- + * ALT_UART_FCR_FIFOE_E_DISD | 0x0 | FIFOs disabled + * ALT_UART_FCR_FIFOE_E_END | 0x1 | FIFOs enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_FIFOE + * + * FIFOs disabled + */ +#define ALT_UART_FCR_FIFOE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_FIFOE + * + * FIFOs enabled + */ +#define ALT_UART_FCR_FIFOE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field. */ +#define ALT_UART_FCR_FIFOE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field. */ +#define ALT_UART_FCR_FIFOE_MSB 0 +/* The width in bits of the ALT_UART_FCR_FIFOE register field. */ +#define ALT_UART_FCR_FIFOE_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_FIFOE register field value. */ +#define ALT_UART_FCR_FIFOE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_FCR_FIFOE register field value. */ +#define ALT_UART_FCR_FIFOE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_FCR_FIFOE register field is UNKNOWN. */ +#define ALT_UART_FCR_FIFOE_RESET 0x0 +/* Extracts the ALT_UART_FCR_FIFOE field value from a register. */ +#define ALT_UART_FCR_FIFOE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register. */ +#define ALT_UART_FCR_FIFOE_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Rx FIFO Reset - rfifor + * + * Resets the control portion of the receive FIFO and treats the FIFO as empty. + * This will also de-assert the DMA Rxrequest and single signals. Note that this + * bit is self-clearing' and it is not necessary to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------- + * ALT_UART_FCR_RFIFOR_E_NORST | 0x0 | No Reset of Rx FIFO Control + * ALT_UART_FCR_RFIFOR_E_RST | 0x1 | Resets of Rx FIFO Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_RFIFOR + * + * No Reset of Rx FIFO Control + */ +#define ALT_UART_FCR_RFIFOR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_RFIFOR + * + * Resets of Rx FIFO Control + */ +#define ALT_UART_FCR_RFIFOR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field. */ +#define ALT_UART_FCR_RFIFOR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field. */ +#define ALT_UART_FCR_RFIFOR_MSB 1 +/* The width in bits of the ALT_UART_FCR_RFIFOR register field. */ +#define ALT_UART_FCR_RFIFOR_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_RFIFOR register field value. */ +#define ALT_UART_FCR_RFIFOR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_FCR_RFIFOR register field value. */ +#define ALT_UART_FCR_RFIFOR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_FCR_RFIFOR register field is UNKNOWN. */ +#define ALT_UART_FCR_RFIFOR_RESET 0x0 +/* Extracts the ALT_UART_FCR_RFIFOR field value from a register. */ +#define ALT_UART_FCR_RFIFOR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register. */ +#define ALT_UART_FCR_RFIFOR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Tx FIFO Reset - xfifor + * + * Resets the control portion of the transmit FIFO and treats the FIFO as empty. + * This will also de-assert the DMA Tx request and single signals when additional + * DMA handshaking is used. + * + * Note that this bit is 'self-clearing' and it is not necessary to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:---------------------------- + * ALT_UART_FCR_XFIFOR_E_NORST | 0x0 | No Reset of Tx FIFO Control + * ALT_UART_FCR_XFIFOR_E_RST | 0x1 | Resets Tx FIFO Control + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_XFIFOR + * + * No Reset of Tx FIFO Control + */ +#define ALT_UART_FCR_XFIFOR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_XFIFOR + * + * Resets Tx FIFO Control + */ +#define ALT_UART_FCR_XFIFOR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field. */ +#define ALT_UART_FCR_XFIFOR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field. */ +#define ALT_UART_FCR_XFIFOR_MSB 2 +/* The width in bits of the ALT_UART_FCR_XFIFOR register field. */ +#define ALT_UART_FCR_XFIFOR_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_XFIFOR register field value. */ +#define ALT_UART_FCR_XFIFOR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_FCR_XFIFOR register field value. */ +#define ALT_UART_FCR_XFIFOR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_FCR_XFIFOR register field is UNKNOWN. */ +#define ALT_UART_FCR_XFIFOR_RESET 0x0 +/* Extracts the ALT_UART_FCR_XFIFOR field value from a register. */ +#define ALT_UART_FCR_XFIFOR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register. */ +#define ALT_UART_FCR_XFIFOR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : DMA Mode - dmam + * + * This determines the DMA signalling mode used for the uart_dma_tx_req_n and + * uart_dma_rx_req_n output signals when additional DMA handshaking signals are not + * selected. DMA mode 0 supports single DMA data transfers at a time. In mode 0, + * the uart_dma_tx_req_n signal goes active low under the following conditions: + * + * * When the Transmitter Holding Register is empty in non-FIFO mode. + * + * * When the transmitter FIFO is empty in FIFO mode with Programmable THRE + * interrupt mode disabled. + * + * * When the transmitter FIFO is at or below the programmed threshold with + * Programmable THRE interrupt mode enabled. + * + * It goes inactive under the following conditions + * + * * When a single character has been written into the Transmitter Holding + * Register or transmitter FIFO with Programmable THRE interrupt mode disabled. + * + * * When the transmitter FIFO is above the threshold with Programmable THRE + * interrupt mode enabled. + * + * DMA mode 1 supports multi-DMA data transfers, where multiple transfers are made + * continuously until the receiver FIFO has been emptied or the transmit FIFO has + * been filled. In mode 1 the uart_dma_tx_req_n signal is asserted under the + * following conditions: + * + * * When the transmitter FIFO is empty with Programmable THRE interrupt mode + * disabled. + * + * * When the transmitter FIFO is at or below the programmed threshold with + * Programmable THRE interrupt mode enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:--------------------------- + * ALT_UART_FCR_DMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode + * ALT_UART_FCR_DMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_DMAM + * + * Single DMA Transfer Mode + */ +#define ALT_UART_FCR_DMAM_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_DMAM + * + * Multiple DMA Transfer Mode + */ +#define ALT_UART_FCR_DMAM_E_MULT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field. */ +#define ALT_UART_FCR_DMAM_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field. */ +#define ALT_UART_FCR_DMAM_MSB 3 +/* The width in bits of the ALT_UART_FCR_DMAM register field. */ +#define ALT_UART_FCR_DMAM_WIDTH 1 +/* The mask used to set the ALT_UART_FCR_DMAM register field value. */ +#define ALT_UART_FCR_DMAM_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_FCR_DMAM register field value. */ +#define ALT_UART_FCR_DMAM_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_FCR_DMAM register field is UNKNOWN. */ +#define ALT_UART_FCR_DMAM_RESET 0x0 +/* Extracts the ALT_UART_FCR_DMAM field value from a register. */ +#define ALT_UART_FCR_DMAM_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register. */ +#define ALT_UART_FCR_DMAM_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Tx Empty Trigger Level - tet + * + * This is used to select the empty threshold level at which the THRE Interrupts + * will be generated when the mode is active. It also determines when the uart DMA + * transmit request signal uart_dma_tx_req_n will be asserted when in certain modes + * of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:----------------------- + * ALT_UART_FCR_TET_E_FIFOEMPTY | 0x0 | FIFO empty + * ALT_UART_FCR_TET_E_TWOCHARS | 0x1 | Two characters in FIFO + * ALT_UART_FCR_TET_E_QUARTERFULL | 0x2 | FIFO 1/4 full + * ALT_UART_FCR_TET_E_HALFFULL | 0x3 | FIFO 1/2 full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * FIFO empty + */ +#define ALT_UART_FCR_TET_E_FIFOEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * Two characters in FIFO + */ +#define ALT_UART_FCR_TET_E_TWOCHARS 0x1 +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * FIFO 1/4 full + */ +#define ALT_UART_FCR_TET_E_QUARTERFULL 0x2 +/* + * Enumerated value for register field ALT_UART_FCR_TET + * + * FIFO 1/2 full + */ +#define ALT_UART_FCR_TET_E_HALFFULL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field. */ +#define ALT_UART_FCR_TET_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field. */ +#define ALT_UART_FCR_TET_MSB 5 +/* The width in bits of the ALT_UART_FCR_TET register field. */ +#define ALT_UART_FCR_TET_WIDTH 2 +/* The mask used to set the ALT_UART_FCR_TET register field value. */ +#define ALT_UART_FCR_TET_SET_MSK 0x00000030 +/* The mask used to clear the ALT_UART_FCR_TET register field value. */ +#define ALT_UART_FCR_TET_CLR_MSK 0xffffffcf +/* The reset value of the ALT_UART_FCR_TET register field is UNKNOWN. */ +#define ALT_UART_FCR_TET_RESET 0x0 +/* Extracts the ALT_UART_FCR_TET field value from a register. */ +#define ALT_UART_FCR_TET_GET(value) (((value) & 0x00000030) >> 4) +/* Produces a ALT_UART_FCR_TET register field value suitable for setting the register. */ +#define ALT_UART_FCR_TET_SET(value) (((value) << 4) & 0x00000030) + +/* + * Field : Rx Trigger Level - rt + * + * This register is configured to implement FIFOs. Bits[7:6], Rx Trigger (or RT): + * This is used to select the trigger level in the receiver FIFO at which the + * Received Data Available Interrupt will be generated. In auto flow control mode + * it is used to determine when the uart_rts_n signal will be de-asserted. It also + * determines when the uart_dma_rx_req_n signal will be asserted when in certain + * modes of operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------------- + * ALT_UART_FCR_RT_E_ONECHAR | 0x0 | one character in fifo + * ALT_UART_FCR_RT_E_QUARTERFULL | 0x1 | FIFO 1/4 full + * ALT_UART_FCR_RT_E_HALFFULL | 0x2 | FIFO 1/2 full + * ALT_UART_FCR_RT_E_FULLLESS2 | 0x3 | FIFO 2 less than full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * one character in fifo + */ +#define ALT_UART_FCR_RT_E_ONECHAR 0x0 +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * FIFO 1/4 full + */ +#define ALT_UART_FCR_RT_E_QUARTERFULL 0x1 +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * FIFO 1/2 full + */ +#define ALT_UART_FCR_RT_E_HALFFULL 0x2 +/* + * Enumerated value for register field ALT_UART_FCR_RT + * + * FIFO 2 less than full + */ +#define ALT_UART_FCR_RT_E_FULLLESS2 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field. */ +#define ALT_UART_FCR_RT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field. */ +#define ALT_UART_FCR_RT_MSB 7 +/* The width in bits of the ALT_UART_FCR_RT register field. */ +#define ALT_UART_FCR_RT_WIDTH 2 +/* The mask used to set the ALT_UART_FCR_RT register field value. */ +#define ALT_UART_FCR_RT_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_UART_FCR_RT register field value. */ +#define ALT_UART_FCR_RT_CLR_MSK 0xffffff3f +/* The reset value of the ALT_UART_FCR_RT register field is UNKNOWN. */ +#define ALT_UART_FCR_RT_RESET 0x0 +/* Extracts the ALT_UART_FCR_RT field value from a register. */ +#define ALT_UART_FCR_RT_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_UART_FCR_RT register field value suitable for setting the register. */ +#define ALT_UART_FCR_RT_SET(value) (((value) << 6) & 0x000000c0) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_FCR. + */ +struct ALT_UART_FCR_s +{ + uint32_t fifoe : 1; /* FIFO Enable */ + uint32_t rfifor : 1; /* Rx FIFO Reset */ + uint32_t xfifor : 1; /* Tx FIFO Reset */ + uint32_t dmam : 1; /* DMA Mode */ + uint32_t tet : 2; /* Tx Empty Trigger Level */ + uint32_t rt : 2; /* Rx Trigger Level */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_FCR. */ +typedef volatile struct ALT_UART_FCR_s ALT_UART_FCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_FCR register from the beginning of the component. */ +#define ALT_UART_FCR_OFST 0x8 +/* The address of the ALT_UART_FCR register. */ +#define ALT_UART_FCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST)) + +/* + * Register : Line Control Register (When Written) - lcr + * + * Formats serial data. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [1:0] | RW | 0x0 | Data Length Select + * [2] | RW | 0x0 | Stop Bits + * [3] | RW | 0x0 | Parity Enable + * [4] | RW | 0x0 | Even Parity Select + * [5] | ??? | 0x0 | *UNDEFINED* + * [6] | RW | 0x0 | Break Control Bit + * [7] | RW | 0x0 | Divisor Latch Access Bit + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Length Select - dls + * + * Data Length Select.Selects the number of data bits per character that the + * peripheral will transmit and receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:------------ + * ALT_UART_LCR_DLS_E_LEN5 | 0x0 | 5 bits + * ALT_UART_LCR_DLS_E_LEN6 | 0x1 | 6 bits + * ALT_UART_LCR_DLS_E_LEN7 | 0x2 | 7 bits + * ALT_UART_LCR_DLS_E_LEN8 | 0x3 | 8 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 5 bits + */ +#define ALT_UART_LCR_DLS_E_LEN5 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 6 bits + */ +#define ALT_UART_LCR_DLS_E_LEN6 0x1 +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 7 bits + */ +#define ALT_UART_LCR_DLS_E_LEN7 0x2 +/* + * Enumerated value for register field ALT_UART_LCR_DLS + * + * 8 bits + */ +#define ALT_UART_LCR_DLS_E_LEN8 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_MSB 1 +/* The width in bits of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_WIDTH 2 +/* The mask used to set the ALT_UART_LCR_DLS register field value. */ +#define ALT_UART_LCR_DLS_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_LCR_DLS register field value. */ +#define ALT_UART_LCR_DLS_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_LCR_DLS register field. */ +#define ALT_UART_LCR_DLS_RESET 0x0 +/* Extracts the ALT_UART_LCR_DLS field value from a register. */ +#define ALT_UART_LCR_DLS_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_LCR_DLS register field value suitable for setting the register. */ +#define ALT_UART_LCR_DLS_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Stop Bits - stop + * + * Number of stop bits. Used to select the number of stop bits per character that + * the peripheral will transmit and receive.Note that regardless of the number of + * stop bits selected the receiver will only check the first stop bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------ + * ALT_UART_LCR_STOP_E_ONESTOP | 0x0 | one stop bit + * ALT_UART_LCR_STOP_E_ONEPOINT5STOP | 0x1 | 1.5 stop bits when DLS (LCR[1:0]) is zero + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_STOP + * + * one stop bit + */ +#define ALT_UART_LCR_STOP_E_ONESTOP 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_STOP + * + * 1.5 stop bits when DLS (LCR[1:0]) is zero + */ +#define ALT_UART_LCR_STOP_E_ONEPOINT5STOP 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_MSB 2 +/* The width in bits of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_STOP register field value. */ +#define ALT_UART_LCR_STOP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_LCR_STOP register field value. */ +#define ALT_UART_LCR_STOP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_LCR_STOP register field. */ +#define ALT_UART_LCR_STOP_RESET 0x0 +/* Extracts the ALT_UART_LCR_STOP field value from a register. */ +#define ALT_UART_LCR_STOP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_LCR_STOP register field value suitable for setting the register. */ +#define ALT_UART_LCR_STOP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Parity Enable - pen + * + * This bit is used to enable and disable parity generation and detection in a + * transmitted and received data character. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:---------------- + * ALT_UART_LCR_PEN_E_DISD | 0x0 | parity disabled + * ALT_UART_LCR_PEN_E_END | 0x1 | parity enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_PEN + * + * parity disabled + */ +#define ALT_UART_LCR_PEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_PEN + * + * parity enabled + */ +#define ALT_UART_LCR_PEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_MSB 3 +/* The width in bits of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_PEN register field value. */ +#define ALT_UART_LCR_PEN_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_LCR_PEN register field value. */ +#define ALT_UART_LCR_PEN_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_LCR_PEN register field. */ +#define ALT_UART_LCR_PEN_RESET 0x0 +/* Extracts the ALT_UART_LCR_PEN field value from a register. */ +#define ALT_UART_LCR_PEN_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_LCR_PEN register field value suitable for setting the register. */ +#define ALT_UART_LCR_PEN_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Even Parity Select - eps + * + * This is used to select between even and odd parity, when parity is enabled (PEN + * set to one). If set to one, an even number of logic '1's is transmitted or + * checked. If set to zero, an odd number of logic '1's is transmitted or checked. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:------------ + * ALT_UART_LCR_EPS_E_ODDPAR | 0x0 | odd parity + * ALT_UART_LCR_EPS_E_EVENPAR | 0x1 | even parity + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LCR_EPS + * + * odd parity + */ +#define ALT_UART_LCR_EPS_E_ODDPAR 0x0 +/* + * Enumerated value for register field ALT_UART_LCR_EPS + * + * even parity + */ +#define ALT_UART_LCR_EPS_E_EVENPAR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_MSB 4 +/* The width in bits of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_EPS register field value. */ +#define ALT_UART_LCR_EPS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_LCR_EPS register field value. */ +#define ALT_UART_LCR_EPS_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_LCR_EPS register field. */ +#define ALT_UART_LCR_EPS_RESET 0x0 +/* Extracts the ALT_UART_LCR_EPS field value from a register. */ +#define ALT_UART_LCR_EPS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_LCR_EPS register field value suitable for setting the register. */ +#define ALT_UART_LCR_EPS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Break Control Bit - break + * + * This is used to cause a break condition to be transmitted to the receiving + * device. If set to one the serial output is forced to the spacing (logic 0) + * state. When not in Loopback Mode, as determined by MCR[4], the sout line is + * forced low until the Break bit is cleared. When in Loopback Mode, the break + * condition is internally looped back to the receiver and the sir_out_n line is + * forced low. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_MSB 6 +/* The width in bits of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_BREAK register field value. */ +#define ALT_UART_LCR_BREAK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_LCR_BREAK register field value. */ +#define ALT_UART_LCR_BREAK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_LCR_BREAK register field. */ +#define ALT_UART_LCR_BREAK_RESET 0x0 +/* Extracts the ALT_UART_LCR_BREAK field value from a register. */ +#define ALT_UART_LCR_BREAK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_LCR_BREAK register field value suitable for setting the register. */ +#define ALT_UART_LCR_BREAK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Divisor Latch Access Bit - dlab + * + * Used to enable reading and writing of the Divisor Latch register (DLL and DLH) + * to set the baud rate of the UART. This bit must be cleared after initial baud + * rate setup in order to access other registers. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_MSB 7 +/* The width in bits of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_WIDTH 1 +/* The mask used to set the ALT_UART_LCR_DLAB register field value. */ +#define ALT_UART_LCR_DLAB_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_LCR_DLAB register field value. */ +#define ALT_UART_LCR_DLAB_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_LCR_DLAB register field. */ +#define ALT_UART_LCR_DLAB_RESET 0x0 +/* Extracts the ALT_UART_LCR_DLAB field value from a register. */ +#define ALT_UART_LCR_DLAB_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_LCR_DLAB register field value suitable for setting the register. */ +#define ALT_UART_LCR_DLAB_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_LCR. + */ +struct ALT_UART_LCR_s +{ + uint32_t dls : 2; /* Data Length Select */ + uint32_t stop : 1; /* Stop Bits */ + uint32_t pen : 1; /* Parity Enable */ + uint32_t eps : 1; /* Even Parity Select */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t break_ : 1; /* Break Control Bit */ + uint32_t dlab : 1; /* Divisor Latch Access Bit */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_LCR. */ +typedef volatile struct ALT_UART_LCR_s ALT_UART_LCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_LCR register from the beginning of the component. */ +#define ALT_UART_LCR_OFST 0xc +/* The address of the ALT_UART_LCR register. */ +#define ALT_UART_LCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LCR_OFST)) + +/* + * Register : Modem Control Register - mcr + * + * Reports various operations of the modem signals + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x0 | Data Terminal Ready + * [1] | RW | 0x0 | Request to Send + * [2] | RW | 0x0 | Out1 + * [3] | RW | 0x0 | out2 + * [4] | RW | 0x0 | LoopBack Bit + * [5] | RW | 0x0 | Auto Flow Control Enable + * [31:6] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Terminal Ready - dtr + * + * This is used to directly control the Data Terminal Ready output. The value + * written to this location is inverted and driven out on uart_dtr_n, that is: The + * Data Terminal Ready output is used to inform the modem or data set that the UART + * is ready to establish communications. + * + * Note that Loopback mode bit [4] of MCR is set to one, the uart_dtr_n output is + * held inactive high while the value of this location is internally looped back + * to an input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:--------------------------------- + * ALT_UART_MCR_DTR_E_LOGIC1 | 0x0 | uart_dtr_n de-asserted (logic 1) + * ALT_UART_MCR_DTR_E_LOGIC0 | 0x1 | uart_dtr_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_DTR + * + * uart_dtr_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_DTR_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_DTR + * + * uart_dtr_n asserted (logic 0) + */ +#define ALT_UART_MCR_DTR_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_MSB 0 +/* The width in bits of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_DTR register field value. */ +#define ALT_UART_MCR_DTR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_MCR_DTR register field value. */ +#define ALT_UART_MCR_DTR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_MCR_DTR register field. */ +#define ALT_UART_MCR_DTR_RESET 0x0 +/* Extracts the ALT_UART_MCR_DTR field value from a register. */ +#define ALT_UART_MCR_DTR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_MCR_DTR register field value suitable for setting the register. */ +#define ALT_UART_MCR_DTR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Request to Send - rts + * + * This is used to directly control the Request to Send (uart_rts_n) output. The + * Request to Send (uart_rts_n) output is used to inform the modem or data set that + * the UART is ready to exchange data. When Auto RTS Flow Control is not enabled + * (MCR[5] set to zero), the uart_rts_n signal is set low by programming MCR[1] + * (RTS) to a high. If Auto Flow Control is active (MCR[5] set to one) and FIFO's + * enable (FCR[0] set to one), the uart_rts_n output is controlled in the same way, + * but is also gated with the receiver FIFO threshold trigger (uart_rts_n is + * inactive high when above the threshold). The uart_rts_n signal will be de- + * asserted when MCR[1] is set low. + * + * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held + * inactive high while the value of this location is internally looped back to an + * input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:--------------------------------- + * ALT_UART_MCR_RTS_E_LOGIC1 | 0x0 | uart_rts_n de-asserted (logic 1) + * ALT_UART_MCR_RTS_E_LOGIC0 | 0x1 | uart_rts_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_RTS + * + * uart_rts_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_RTS_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_RTS + * + * uart_rts_n asserted (logic 0) + */ +#define ALT_UART_MCR_RTS_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_MSB 1 +/* The width in bits of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_RTS register field value. */ +#define ALT_UART_MCR_RTS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_MCR_RTS register field value. */ +#define ALT_UART_MCR_RTS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_MCR_RTS register field. */ +#define ALT_UART_MCR_RTS_RESET 0x0 +/* Extracts the ALT_UART_MCR_RTS field value from a register. */ +#define ALT_UART_MCR_RTS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_MCR_RTS register field value suitable for setting the register. */ +#define ALT_UART_MCR_RTS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Out1 - out1 + * + * The value written to this location is inverted and driven out on uart_out1_n + * pin. + * + * Note that in Loopback mode (MCR[4] set to one), the uart_out1_n output is held + * inactive high while the value of this location is internally looped back to an + * input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:---------------------------------- + * ALT_UART_MCR_OUT1_E_LOGIC1 | 0x0 | uart_out1_n de-asserted (logic 1) + * ALT_UART_MCR_OUT1_E_LOGIC0 | 0x1 | uart_out1_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_OUT1 + * + * uart_out1_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_OUT1_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_OUT1 + * + * uart_out1_n asserted (logic 0) + */ +#define ALT_UART_MCR_OUT1_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_MSB 2 +/* The width in bits of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_OUT1 register field value. */ +#define ALT_UART_MCR_OUT1_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_MCR_OUT1 register field value. */ +#define ALT_UART_MCR_OUT1_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_MCR_OUT1 register field. */ +#define ALT_UART_MCR_OUT1_RESET 0x0 +/* Extracts the ALT_UART_MCR_OUT1 field value from a register. */ +#define ALT_UART_MCR_OUT1_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register. */ +#define ALT_UART_MCR_OUT1_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : out2 - out2 + * + * This is used to directly control the user-designated uart_out2_n output. The + * value written to this location is inverted and driven out on uart_out2_n + * + * Note: In Loopback mode bit 4 of the modem control register (MCR) is set to one, + * the uart_out2_n output is held inactive high while the value of this location is + * internally looped back to an input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:---------------------------------- + * ALT_UART_MCR_OUT2_E_LOGIC1 | 0x0 | uart_out2_n de-asserted (logic 1) + * ALT_UART_MCR_OUT2_E_LOGIC0 | 0x1 | uart_out2_n asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_OUT2 + * + * uart_out2_n de-asserted (logic 1) + */ +#define ALT_UART_MCR_OUT2_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_OUT2 + * + * uart_out2_n asserted (logic 0) + */ +#define ALT_UART_MCR_OUT2_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_MSB 3 +/* The width in bits of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_OUT2 register field value. */ +#define ALT_UART_MCR_OUT2_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_MCR_OUT2 register field value. */ +#define ALT_UART_MCR_OUT2_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_MCR_OUT2 register field. */ +#define ALT_UART_MCR_OUT2_RESET 0x0 +/* Extracts the ALT_UART_MCR_OUT2 field value from a register. */ +#define ALT_UART_MCR_OUT2_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register. */ +#define ALT_UART_MCR_OUT2_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : LoopBack Bit - loopback + * + * This is used to put the UART into a diagnostic mode for test purposes. If UART + * mode is NOT active, bit [6] of the modem control register MCR is set to zero, + * data on the sout line is held high, while serial data output is looped back to + * the sin line, internally. In this mode all the interrupts are fully functional. + * Also, in loopback mode, the modem control inputs (uart_dsr_n, uart_cts_n, + * uart_ri_n, uart_dcd_n) are disconnected and the modem control outputs + * (uart_dtr_n, uart_rts_n, uart_out1_n, uart_out2_n) are loopedback to the inputs, + * internally. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_MSB 4 +/* The width in bits of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_LOOPBACK register field value. */ +#define ALT_UART_MCR_LOOPBACK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_MCR_LOOPBACK register field value. */ +#define ALT_UART_MCR_LOOPBACK_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_MCR_LOOPBACK register field. */ +#define ALT_UART_MCR_LOOPBACK_RESET 0x0 +/* Extracts the ALT_UART_MCR_LOOPBACK field value from a register. */ +#define ALT_UART_MCR_LOOPBACK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register. */ +#define ALT_UART_MCR_LOOPBACK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Auto Flow Control Enable - afce + * + * When FIFOs are enabled, the Auto Flow Control enable bits are active. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:-------------------------------- + * ALT_UART_MCR_AFCE_E_DISD | 0x0 | Auto Flow Control Mode disabled + * ALT_UART_MCR_AFCE_E_END | 0x1 | Auto Flow Control Mode enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MCR_AFCE + * + * Auto Flow Control Mode disabled + */ +#define ALT_UART_MCR_AFCE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_MCR_AFCE + * + * Auto Flow Control Mode enabled + */ +#define ALT_UART_MCR_AFCE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_MSB 5 +/* The width in bits of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_WIDTH 1 +/* The mask used to set the ALT_UART_MCR_AFCE register field value. */ +#define ALT_UART_MCR_AFCE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_MCR_AFCE register field value. */ +#define ALT_UART_MCR_AFCE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_MCR_AFCE register field. */ +#define ALT_UART_MCR_AFCE_RESET 0x0 +/* Extracts the ALT_UART_MCR_AFCE field value from a register. */ +#define ALT_UART_MCR_AFCE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register. */ +#define ALT_UART_MCR_AFCE_SET(value) (((value) << 5) & 0x00000020) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_MCR. + */ +struct ALT_UART_MCR_s +{ + uint32_t dtr : 1; /* Data Terminal Ready */ + uint32_t rts : 1; /* Request to Send */ + uint32_t out1 : 1; /* Out1 */ + uint32_t out2 : 1; /* out2 */ + uint32_t loopback : 1; /* LoopBack Bit */ + uint32_t afce : 1; /* Auto Flow Control Enable */ + uint32_t : 26; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_MCR. */ +typedef volatile struct ALT_UART_MCR_s ALT_UART_MCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_MCR register from the beginning of the component. */ +#define ALT_UART_MCR_OFST 0x10 +/* The address of the ALT_UART_MCR register. */ +#define ALT_UART_MCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST)) + +/* + * Register : Line Status Register - lsr + * + * Reports status of transmit and receive. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------------ + * [0] | R | 0x0 | Data Ready bit + * [1] | R | 0x0 | Overrun error + * [2] | R | 0x0 | Parity Error + * [3] | R | 0x0 | Framing Error + * [4] | R | 0x0 | Break Interrupt + * [5] | R | 0x1 | Transmit Holding Register Empty bit + * [6] | R | 0x1 | Transmitter Empty bit + * [7] | R | 0x0 | Receiver FIFO Error bit + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Data Ready bit - dr + * + * This is used to indicate that the receiver contains at least one character in + * the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the + * non-FIFO mode, or when the receiver FIFO is empty, in the FIFO mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------- + * ALT_UART_LSR_DR_E_NODATARDY | 0x0 | no data ready + * ALT_UART_LSR_DR_E_DATARDY | 0x1 | data ready + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_DR + * + * no data ready + */ +#define ALT_UART_LSR_DR_E_NODATARDY 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_DR + * + * data ready + */ +#define ALT_UART_LSR_DR_E_DATARDY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_MSB 0 +/* The width in bits of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_DR register field value. */ +#define ALT_UART_LSR_DR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_LSR_DR register field value. */ +#define ALT_UART_LSR_DR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_LSR_DR register field. */ +#define ALT_UART_LSR_DR_RESET 0x0 +/* Extracts the ALT_UART_LSR_DR field value from a register. */ +#define ALT_UART_LSR_DR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_LSR_DR register field value suitable for setting the register. */ +#define ALT_UART_LSR_DR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Overrun error - oe + * + * This is used to indicate the occurrence of an overrun error. This occurs if a + * new data character was received before the previous data was read. In the non- + * FIFO mode, the OE bit is set when a new character arrives in the receiver before + * the previous character was read from the RBR. When this happens, the data in the + * RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is + * full and new character arrives at the receiver. The data in the FIFO is retained + * and the data in the receive shift register is lost.Reading the LSR clears the OE + * bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------- + * ALT_UART_LSR_OE_E_NOOVERRUN | 0x0 | no overrun error + * ALT_UART_LSR_OE_E_OVERRUN | 0x1 | overrun error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_OE + * + * no overrun error + */ +#define ALT_UART_LSR_OE_E_NOOVERRUN 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_OE + * + * overrun error + */ +#define ALT_UART_LSR_OE_E_OVERRUN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_MSB 1 +/* The width in bits of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_OE register field value. */ +#define ALT_UART_LSR_OE_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_LSR_OE register field value. */ +#define ALT_UART_LSR_OE_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_LSR_OE register field. */ +#define ALT_UART_LSR_OE_RESET 0x0 +/* Extracts the ALT_UART_LSR_OE field value from a register. */ +#define ALT_UART_LSR_OE_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_LSR_OE register field value suitable for setting the register. */ +#define ALT_UART_LSR_OE_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Parity Error - pe + * + * This is used to indicate the occurrence of a parity error in the receiver if the + * Parity Enable (PEN) bit (LCR[3]) is set. Since the parity error is associated + * with a character received, it is revealed when the character with the parity + * error arrives at the top of the FIFO. It should be noted that the Parity Error + * (PE) bit (LSR[2]) will be set if a break interrupt has occurred, as indicated by + * Break Interrupt (BI) bit (LSR[4]). Reading the LSR clears the PE bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:---------------- + * ALT_UART_LSR_PE_E_NOPARITYERR | 0x0 | no parity error + * ALT_UART_LSR_PE_E_PARITYERR | 0x1 | no parity error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_PE + * + * no parity error + */ +#define ALT_UART_LSR_PE_E_NOPARITYERR 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_PE + * + * no parity error + */ +#define ALT_UART_LSR_PE_E_PARITYERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_MSB 2 +/* The width in bits of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_PE register field value. */ +#define ALT_UART_LSR_PE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_LSR_PE register field value. */ +#define ALT_UART_LSR_PE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_LSR_PE register field. */ +#define ALT_UART_LSR_PE_RESET 0x0 +/* Extracts the ALT_UART_LSR_PE field value from a register. */ +#define ALT_UART_LSR_PE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_LSR_PE register field value suitable for setting the register. */ +#define ALT_UART_LSR_PE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Framing Error - fe + * + * This is used to indicate the occurrence of a framing error in the receiver. A + * framing error occurs when the receiver does not detect a valid STOP bit in the + * received data. In the FIFO mode, since the framing error is associated with a + * character received, it is revealed when the character with the framing error is + * at the top of the FIFO. When a framing error occurs the UART will try to + * resynchronize. It does this by assuming that the error was due to the start bit + * of the next character and then continues receiving the other bit i.e. data, + * and/or parity and stop. It should be noted that the Framing Error (FE) + * bit(LSR[3]) will be set if a break interrupt has occurred, as indicated by a + * Break Interrupt BIT bit (LSR[4]). Reading the LSR clears the FE bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------- + * ALT_UART_LSR_FE_E_NOFRMERR | 0x0 | no framing error + * ALT_UART_LSR_FE_E_FRMERR | 0x1 | framing error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_FE + * + * no framing error + */ +#define ALT_UART_LSR_FE_E_NOFRMERR 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_FE + * + * framing error + */ +#define ALT_UART_LSR_FE_E_FRMERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_MSB 3 +/* The width in bits of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_FE register field value. */ +#define ALT_UART_LSR_FE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_LSR_FE register field value. */ +#define ALT_UART_LSR_FE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_LSR_FE register field. */ +#define ALT_UART_LSR_FE_RESET 0x0 +/* Extracts the ALT_UART_LSR_FE field value from a register. */ +#define ALT_UART_LSR_FE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_LSR_FE register field value suitable for setting the register. */ +#define ALT_UART_LSR_FE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Break Interrupt - bi + * + * This is used to indicate the detection of a break sequence on the serial input + * data. Set whenever the serial input, sin, is held in a logic 0 state for longer + * than the sum of start time + data bits + parity + stop bits. A break condition + * on serial input causes one and only one character, consisting of all zeros, to + * be received by the UART. The character associated with the break condition is + * carried through the FIFO and is revealed when the character is at the top of the + * FIFO. Reading the LSR clears the BI bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_MSB 4 +/* The width in bits of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_BI register field value. */ +#define ALT_UART_LSR_BI_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_LSR_BI register field value. */ +#define ALT_UART_LSR_BI_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_LSR_BI register field. */ +#define ALT_UART_LSR_BI_RESET 0x0 +/* Extracts the ALT_UART_LSR_BI field value from a register. */ +#define ALT_UART_LSR_BI_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_LSR_BI register field value suitable for setting the register. */ +#define ALT_UART_LSR_BI_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Transmit Holding Register Empty bit - thre + * + * If THRE mode is disabled (IER[7] set to zero) this bit indicates that the THR or + * Tx FIFO is empty. This bit is set whenever data is transferred from the THR or + * Tx FIFO to the transmitter shift register and no new data has been written to + * the THR or Tx FIFO. This also causes a THRE Interrupt to occur, if the THRE + * Interrupt is enabled. If both THRE and FIFOs are enabled, both (IER[7] set to + * one and FCR[0] set to one respectively), the functionality will indicate the + * transmitter FIFO is full, and no longer controls THRE interrupts, which are then + * controlled by the FCR[5:4] thresholdsetting. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_MSB 5 +/* The width in bits of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_THRE register field value. */ +#define ALT_UART_LSR_THRE_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_LSR_THRE register field value. */ +#define ALT_UART_LSR_THRE_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_LSR_THRE register field. */ +#define ALT_UART_LSR_THRE_RESET 0x1 +/* Extracts the ALT_UART_LSR_THRE field value from a register. */ +#define ALT_UART_LSR_THRE_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_LSR_THRE register field value suitable for setting the register. */ +#define ALT_UART_LSR_THRE_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Transmitter Empty bit - temt + * + * If in FIFO mode and FIFO's enabled (FCR[0] set to one), this bit is set whenever + * the Transmitter Shift Register and the FIFO are both empty. If FIFO's are + * disabled, this bit is set whenever the Transmitter Holding Register and the + * Transmitter Shift Register are both empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:----------------------- + * ALT_UART_LSR_TEMT_E_NOTEMPTY | 0x0 | Transmit Empty not set + * ALT_UART_LSR_TEMT_E_EMPTY | 0x1 | Transmit Empty set + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_TEMT + * + * Transmit Empty not set + */ +#define ALT_UART_LSR_TEMT_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_TEMT + * + * Transmit Empty set + */ +#define ALT_UART_LSR_TEMT_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_MSB 6 +/* The width in bits of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_TEMT register field value. */ +#define ALT_UART_LSR_TEMT_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_LSR_TEMT register field value. */ +#define ALT_UART_LSR_TEMT_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_LSR_TEMT register field. */ +#define ALT_UART_LSR_TEMT_RESET 0x1 +/* Extracts the ALT_UART_LSR_TEMT field value from a register. */ +#define ALT_UART_LSR_TEMT_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_LSR_TEMT register field value suitable for setting the register. */ +#define ALT_UART_LSR_TEMT_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Receiver FIFO Error bit - rfe + * + * This bit is only relevant when FIFO's are enabled (FCR[0] set to one). This is + * used to indicate if there is at least one parity error, framing error, or break + * indication in the FIFO. This bit is cleared when the LSR is read and the + * character with the error is at the top of the receiver FIFO and there are no + * subsequent errors in the FIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:-------------------- + * ALT_UART_LSR_RFE_E_NOERR | 0x0 | no error in Rx FIFO + * ALT_UART_LSR_RFE_E_ERR | 0x1 | error in Rx FIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_LSR_RFE + * + * no error in Rx FIFO + */ +#define ALT_UART_LSR_RFE_E_NOERR 0x0 +/* + * Enumerated value for register field ALT_UART_LSR_RFE + * + * error in Rx FIFO + */ +#define ALT_UART_LSR_RFE_E_ERR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_MSB 7 +/* The width in bits of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_WIDTH 1 +/* The mask used to set the ALT_UART_LSR_RFE register field value. */ +#define ALT_UART_LSR_RFE_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_LSR_RFE register field value. */ +#define ALT_UART_LSR_RFE_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_LSR_RFE register field. */ +#define ALT_UART_LSR_RFE_RESET 0x0 +/* Extracts the ALT_UART_LSR_RFE field value from a register. */ +#define ALT_UART_LSR_RFE_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_LSR_RFE register field value suitable for setting the register. */ +#define ALT_UART_LSR_RFE_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_LSR. + */ +struct ALT_UART_LSR_s +{ + const uint32_t dr : 1; /* Data Ready bit */ + const uint32_t oe : 1; /* Overrun error */ + const uint32_t pe : 1; /* Parity Error */ + const uint32_t fe : 1; /* Framing Error */ + const uint32_t bi : 1; /* Break Interrupt */ + const uint32_t thre : 1; /* Transmit Holding Register Empty bit */ + const uint32_t temt : 1; /* Transmitter Empty bit */ + const uint32_t rfe : 1; /* Receiver FIFO Error bit */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_LSR. */ +typedef volatile struct ALT_UART_LSR_s ALT_UART_LSR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_LSR register from the beginning of the component. */ +#define ALT_UART_LSR_OFST 0x14 +/* The address of the ALT_UART_LSR register. */ +#define ALT_UART_LSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LSR_OFST)) + +/* + * Register : Modem Status Register - msr + * + * It should be noted that whenever bits 0, 1, 2 or 3 are set to logic one, to + * indicate a change on the modem control inputs, a modem status interrupt will be + * generated if enabled via the IER regardless of when the change occurred. Since + * the delta bits (bits 0, 1, 3) can get set after a reset if their respective + * modem signals are active (see individual bits for details), a read of the MSR + * after reset can be performed to prevent unwanted interrupts. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------------- + * [0] | R | 0x0 | Delta Clear to Send + * [1] | R | 0x0 | Delta Data Set Ready + * [2] | R | 0x0 | Trailing Edge of Ring Indicator + * [3] | R | 0x0 | Delta Data Carrier Detect + * [4] | R | 0x0 | Clear to Send + * [5] | R | 0x0 | Data Set Ready + * [6] | R | 0x0 | Ring Indicator + * [7] | R | 0x0 | Data Carrier Detect + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Delta Clear to Send - dcts + * + * This is used to indicate that the modem control line uart_cts_n has changed + * since the last time the MSR was read. That is: Reading the MSR clears the DCTS + * bit. In Loopback Mode bit [4] of MCR set to one, DCTS reflects changes on bit + * [1] RTS of register MCR. + * + * Note: If the DCTS bit is not set and the uart_cts_n signal is asserted (low) and + * a reset occurs (software or otherwise), then the DCTS bit will get set when the + * reset is removed if the uart_cts_n signal remains asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------------------------------------- + * ALT_UART_MSR_DCTS_E_NOCHG | 0x0 | no change on uart_cts_n since last read of MSR + * ALT_UART_MSR_DCTS_E_CHG | 0x1 | change on uart_cts_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DCTS + * + * no change on uart_cts_n since last read of MSR + */ +#define ALT_UART_MSR_DCTS_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DCTS + * + * change on uart_cts_n since last read of MSR + */ +#define ALT_UART_MSR_DCTS_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_MSB 0 +/* The width in bits of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DCTS register field value. */ +#define ALT_UART_MSR_DCTS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_MSR_DCTS register field value. */ +#define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_MSR_DCTS register field. */ +#define ALT_UART_MSR_DCTS_RESET 0x0 +/* Extracts the ALT_UART_MSR_DCTS field value from a register. */ +#define ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register. */ +#define ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Delta Data Set Ready - ddsr + * + * This is used to indicate that the modem control line uart_dsr_n has changed + * since the last time the MSR was read. Reading the MSR clears the DDSR bit.In + * Loopback Mode (MCR[4] set to one), DDSR reflects changes on bit [0] DTR of + * register MCR . + * + * Note, if the DDSR bit is not set and the uart_dsr_n signal is asserted (low) and + * a reset occurs (software or otherwise), then the DDSR bit will get set when the + * reset is removed if the uart_dsr_n signal remains asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------------------------------------- + * ALT_UART_MSR_DDSR_E_NOCHG | 0x0 | no change on uart_dsr_n since last read of MSR + * ALT_UART_MSR_DDSR_E_CHG | 0x1 | change on uart_dsr_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DDSR + * + * no change on uart_dsr_n since last read of MSR + */ +#define ALT_UART_MSR_DDSR_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DDSR + * + * change on uart_dsr_n since last read of MSR + */ +#define ALT_UART_MSR_DDSR_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_MSB 1 +/* The width in bits of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DDSR register field value. */ +#define ALT_UART_MSR_DDSR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_MSR_DDSR register field value. */ +#define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_MSR_DDSR register field. */ +#define ALT_UART_MSR_DDSR_RESET 0x0 +/* Extracts the ALT_UART_MSR_DDSR field value from a register. */ +#define ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register. */ +#define ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Trailing Edge of Ring Indicator - teri + * + * This is used to indicate that a change on the input uart_ri_n (from an active + * low, to an inactive high state) has occurred since the last time the MSR was + * read. Reading the MSR clears the TERI bit. In Loopback Mode bit [4] of register + * MCR is set to one, TERI reflects when bit [2] of register MCR has changed state + * from a high to a low. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------------------------------------- + * ALT_UART_MSR_TERI_E_NOCHG | 0x0 | no change on uart_ri_n since last read of MSR + * ALT_UART_MSR_TERI_E_CHG | 0x1 | change on uart_ri_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_TERI + * + * no change on uart_ri_n since last read of MSR + */ +#define ALT_UART_MSR_TERI_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_TERI + * + * change on uart_ri_n since last read of MSR + */ +#define ALT_UART_MSR_TERI_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_MSB 2 +/* The width in bits of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_TERI register field value. */ +#define ALT_UART_MSR_TERI_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_MSR_TERI register field value. */ +#define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_MSR_TERI register field. */ +#define ALT_UART_MSR_TERI_RESET 0x0 +/* Extracts the ALT_UART_MSR_TERI field value from a register. */ +#define ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_MSR_TERI register field value suitable for setting the register. */ +#define ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Delta Data Carrier Detect - ddcd + * + * This is used to indicate that the modem control line dcd_n has changed since the + * last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback + * Mode bit [4] of register MCR is set to one, DDCD reflects changes bit [3] + * uart_out2 of register MCR. + * + * Note: If the DDCD bit is not set and the uart_dcd_n signal is asserted (low) and + * a reset occurs (software or otherwise), then the DDCD bit will get set when the + * reset is removed if the uart_dcd_n signal remains asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------------------------------------- + * ALT_UART_MSR_DDCD_E_NOCHG | 0x0 | no change on uart_dcd_n since last read of MSR + * ALT_UART_MSR_DDCD_E_CHG | 0x1 | change on uart_dcd_n since last read of MSR + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DDCD + * + * no change on uart_dcd_n since last read of MSR + */ +#define ALT_UART_MSR_DDCD_E_NOCHG 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DDCD + * + * change on uart_dcd_n since last read of MSR + */ +#define ALT_UART_MSR_DDCD_E_CHG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_MSB 3 +/* The width in bits of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DDCD register field value. */ +#define ALT_UART_MSR_DDCD_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_MSR_DDCD register field value. */ +#define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_MSR_DDCD register field. */ +#define ALT_UART_MSR_DDCD_RESET 0x0 +/* Extracts the ALT_UART_MSR_DDCD field value from a register. */ +#define ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register. */ +#define ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Clear to Send - cts + * + * This is used to indicate the current state of the modem control line uart_cts_n. + * That is, this bit is the complement uart_cts_n. When the Clear to Send input + * (uart_cts_n) is asserted it is an indication that the modem or data set is ready + * to exchange data with the uart. In Loopback Mode bit [4] of register MCR is set + * to one, CTS is the same as bit [1] RTS of register MCR. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------ + * ALT_UART_MSR_CTS_E_LOGIC1 | 0x0 | uart_cts_n input is de-asserted (logic 1) + * ALT_UART_MSR_CTS_E_LOGIC0 | 0x1 | uart_cts_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_CTS + * + * uart_cts_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_CTS_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_CTS + * + * uart_cts_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_CTS_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_MSB 4 +/* The width in bits of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_CTS register field value. */ +#define ALT_UART_MSR_CTS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_MSR_CTS register field value. */ +#define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_MSR_CTS register field. */ +#define ALT_UART_MSR_CTS_RESET 0x0 +/* Extracts the ALT_UART_MSR_CTS field value from a register. */ +#define ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_MSR_CTS register field value suitable for setting the register. */ +#define ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Data Set Ready - dsr + * + * This is used to indicate the current state of the modem control line uart_dsr_n. + * That is this bit is the complement f uart_dsr_n. When the Data Set Ready input + * (uart_dsr_n) is asserted it is an indication that the modem or data set is ready + * to establish communications with the uart. In Loopback Mode bit [4] of register + * MCR is set to one, DSR is the same as bit [0] (DTR) of register MCR. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------ + * ALT_UART_MSR_DSR_E_LOGIC1 | 0x0 | uart_dsr_n input is de-asserted (logic 1) + * ALT_UART_MSR_DSR_E_LOGIC0 | 0x1 | uart_dsr_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DSR + * + * uart_dsr_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_DSR_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DSR + * + * uart_dsr_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_DSR_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_MSB 5 +/* The width in bits of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DSR register field value. */ +#define ALT_UART_MSR_DSR_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_MSR_DSR register field value. */ +#define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_MSR_DSR register field. */ +#define ALT_UART_MSR_DSR_RESET 0x0 +/* Extracts the ALT_UART_MSR_DSR field value from a register. */ +#define ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_MSR_DSR register field value suitable for setting the register. */ +#define ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Ring Indicator - ri + * + * This bit is used to indicate the current state of the modem control line + * uart_ri_n. That is this bit is the complement uart_ri_n. When the Ring Indicator + * input (uart_ri_n) is asserted it is an indication that a telephone ringing + * signal has been received by the modem or data set. In Loopback Mode bit [4] of + * register MCR set to one, RI is the same as bit [2] uart_out1_n of register MCR. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------------------------------- + * ALT_UART_MSR_RI_E_LOGIC1 | 0x0 | uart_ri_n input is de-asserted (logic 1) + * ALT_UART_MSR_RI_E_LOGIC0 | 0x1 | uart_ri_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_RI + * + * uart_ri_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_RI_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_RI + * + * uart_ri_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_RI_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_MSB 6 +/* The width in bits of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_RI register field value. */ +#define ALT_UART_MSR_RI_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_MSR_RI register field value. */ +#define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_MSR_RI register field. */ +#define ALT_UART_MSR_RI_RESET 0x0 +/* Extracts the ALT_UART_MSR_RI field value from a register. */ +#define ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_MSR_RI register field value suitable for setting the register. */ +#define ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Data Carrier Detect - dcd + * + * This is used to indicate the current state of the modem control line uart_dcd_n. + * That is this bit is the complement uart_dcd_n. When the Data Carrier Detect + * input (uart_dcd_n) is asserted it is an indication that the carrier has been + * detected by the modem or data set. In Loopback Mode (MCR[4] set to one), DCD is + * the same as MCR[3] (uart_out2). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:------------------------------------------ + * ALT_UART_MSR_DCD_E_LOGIC1 | 0x0 | uart_dcd_n input is de-asserted (logic 1) + * ALT_UART_MSR_DCD_E_LOGIC0 | 0x1 | uart_dcd_n input is asserted (logic 0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_MSR_DCD + * + * uart_dcd_n input is de-asserted (logic 1) + */ +#define ALT_UART_MSR_DCD_E_LOGIC1 0x0 +/* + * Enumerated value for register field ALT_UART_MSR_DCD + * + * uart_dcd_n input is asserted (logic 0) + */ +#define ALT_UART_MSR_DCD_E_LOGIC0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_MSB 7 +/* The width in bits of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_WIDTH 1 +/* The mask used to set the ALT_UART_MSR_DCD register field value. */ +#define ALT_UART_MSR_DCD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_MSR_DCD register field value. */ +#define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_MSR_DCD register field. */ +#define ALT_UART_MSR_DCD_RESET 0x0 +/* Extracts the ALT_UART_MSR_DCD field value from a register. */ +#define ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_MSR_DCD register field value suitable for setting the register. */ +#define ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_MSR. + */ +struct ALT_UART_MSR_s +{ + const uint32_t dcts : 1; /* Delta Clear to Send */ + const uint32_t ddsr : 1; /* Delta Data Set Ready */ + const uint32_t teri : 1; /* Trailing Edge of Ring Indicator */ + const uint32_t ddcd : 1; /* Delta Data Carrier Detect */ + const uint32_t cts : 1; /* Clear to Send */ + const uint32_t dsr : 1; /* Data Set Ready */ + const uint32_t ri : 1; /* Ring Indicator */ + const uint32_t dcd : 1; /* Data Carrier Detect */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_MSR. */ +typedef volatile struct ALT_UART_MSR_s ALT_UART_MSR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_MSR register from the beginning of the component. */ +#define ALT_UART_MSR_OFST 0x18 +/* The address of the ALT_UART_MSR register. */ +#define ALT_UART_MSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST)) + +/* + * Register : Scratchpad Register - scr + * + * Scratchpad Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [7:0] | RW | 0x0 | Scratchpad Register + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Scratchpad Register - scr + * + * This register is for programmers to use as a temporary storage space. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_MSB 7 +/* The width in bits of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_WIDTH 8 +/* The mask used to set the ALT_UART_SCR_SCR register field value. */ +#define ALT_UART_SCR_SCR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_SCR_SCR register field value. */ +#define ALT_UART_SCR_SCR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_SCR_SCR register field. */ +#define ALT_UART_SCR_SCR_RESET 0x0 +/* Extracts the ALT_UART_SCR_SCR field value from a register. */ +#define ALT_UART_SCR_SCR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_SCR_SCR register field value suitable for setting the register. */ +#define ALT_UART_SCR_SCR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SCR. + */ +struct ALT_UART_SCR_s +{ + uint32_t scr : 8; /* Scratchpad Register */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SCR. */ +typedef volatile struct ALT_UART_SCR_s ALT_UART_SCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SCR register from the beginning of the component. */ +#define ALT_UART_SCR_OFST 0x1c +/* The address of the ALT_UART_SCR register. */ +#define ALT_UART_SCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SCR_OFST)) + +/* + * Register : Shadow Receive Buffer Register - srbr + * + * Used to accomadate burst accesses from the master. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------- + * [7:0] | RW | 0x0 | Shadow Receive Buffer + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Receive Buffer - srbr + * + * This is a shadow register for the RBR and has been allocated one 32-bit location + * so as to accommodate burst accesses from the master.This register contains the + * data byte received on the serial input port (sin). The data in this register is + * valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. + * If FIFOs are disabled, bit [0] of register FCR set to zero, the data in the RBR + * must be read before the next data arrives, otherwise it will be overwritten, + * resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this + * register accesses the head of the receive FIFO. If the receive FIFO is full and + * this register is not read before the next data character arrives, then the data + * already in the FIFO will be preserved but any incoming data will be lost. An + * overrun error will also occur. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_MSB 7 +/* The width in bits of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_WIDTH 8 +/* The mask used to set the ALT_UART_SRBR_SRBR register field value. */ +#define ALT_UART_SRBR_SRBR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_SRBR_SRBR register field value. */ +#define ALT_UART_SRBR_SRBR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_SRBR_SRBR register field. */ +#define ALT_UART_SRBR_SRBR_RESET 0x0 +/* Extracts the ALT_UART_SRBR_SRBR field value from a register. */ +#define ALT_UART_SRBR_SRBR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_SRBR_SRBR register field value suitable for setting the register. */ +#define ALT_UART_SRBR_SRBR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRBR. + */ +struct ALT_UART_SRBR_s +{ + uint32_t srbr : 8; /* Shadow Receive Buffer */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRBR. */ +typedef volatile struct ALT_UART_SRBR_s ALT_UART_SRBR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRBR register from the beginning of the component. */ +#define ALT_UART_SRBR_OFST 0x30 +/* The address of the ALT_UART_SRBR register. */ +#define ALT_UART_SRBR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_OFST)) + +/* + * Register : Shadow Transmit Buffer Register - sthr + * + * Used to accomadate burst accesses from the master. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [7:0] | RW | 0x0 | Shadow Transmit Buffer + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Transmit Buffer - sthr + * + * This is a shadow register for the THR and has been allocated sixteen 32-bit + * locations so as to accommodate burst accesses from the master. This register + * contains data to be transmitted on the serial output port (sout). Data should + * only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If + * FIFO's are disabled bit [0] of register FCR set to zero and THRE is set, writing + * a single character to the THR clears the THRE. Any additional writes to the THR + * before the THRE is set again causes the THR data to be overwritten. If FIFO's + * are enabled bit [0] of register FCR set to one and THRE is set, 128 characters + * of data may be written to the THR before the FIFO is full. The UART FIFO depth + * is configured for 128 characters. Any attempt to write data when the FIFO is + * full results in the write data being lost. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_MSB 7 +/* The width in bits of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_WIDTH 8 +/* The mask used to set the ALT_UART_STHR_STHR register field value. */ +#define ALT_UART_STHR_STHR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_STHR_STHR register field value. */ +#define ALT_UART_STHR_STHR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_STHR_STHR register field. */ +#define ALT_UART_STHR_STHR_RESET 0x0 +/* Extracts the ALT_UART_STHR_STHR field value from a register. */ +#define ALT_UART_STHR_STHR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_STHR_STHR register field value suitable for setting the register. */ +#define ALT_UART_STHR_STHR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_STHR. + */ +struct ALT_UART_STHR_s +{ + uint32_t sthr : 8; /* Shadow Transmit Buffer */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_STHR. */ +typedef volatile struct ALT_UART_STHR_s ALT_UART_STHR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_STHR register from the beginning of the component. */ +#define ALT_UART_STHR_OFST 0x34 +/* The address of the ALT_UART_STHR register. */ +#define ALT_UART_STHR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STHR_OFST)) + +/* + * Register : FIFO Access Register - far + * + * This register is used in FIFO access testing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | RW | 0x0 | FIFO ACCESS Bit + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : FIFO ACCESS Bit - srbr_sthr + * + * This register is used to enable a FIFO access mode for testing, so that the + * receive FIFO can be written by the master and the transmit FIFO can be read by + * the master when FIFO's are enabled. When FIFO's are not enabled it allows the + * RBR to be written by the master and the THR to be read by the master + * + * Note: That when the FIFO access mode is enabled/disabled, the control portion of + * the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:-------------------------- + * ALT_UART_FAR_SRBR_STHR_E_DISD | 0x0 | FIFO access mode disabled + * ALT_UART_FAR_SRBR_STHR_E_END | 0x1 | FIFO access mode enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_FAR_SRBR_STHR + * + * FIFO access mode disabled + */ +#define ALT_UART_FAR_SRBR_STHR_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_FAR_SRBR_STHR + * + * FIFO access mode enabled + */ +#define ALT_UART_FAR_SRBR_STHR_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_MSB 0 +/* The width in bits of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_WIDTH 1 +/* The mask used to set the ALT_UART_FAR_SRBR_STHR register field value. */ +#define ALT_UART_FAR_SRBR_STHR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_FAR_SRBR_STHR register field value. */ +#define ALT_UART_FAR_SRBR_STHR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_FAR_SRBR_STHR register field. */ +#define ALT_UART_FAR_SRBR_STHR_RESET 0x0 +/* Extracts the ALT_UART_FAR_SRBR_STHR field value from a register. */ +#define ALT_UART_FAR_SRBR_STHR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_FAR_SRBR_STHR register field value suitable for setting the register. */ +#define ALT_UART_FAR_SRBR_STHR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_FAR. + */ +struct ALT_UART_FAR_s +{ + uint32_t srbr_sthr : 1; /* FIFO ACCESS Bit */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_FAR. */ +typedef volatile struct ALT_UART_FAR_s ALT_UART_FAR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_FAR register from the beginning of the component. */ +#define ALT_UART_FAR_OFST 0x70 +/* The address of the ALT_UART_FAR register. */ +#define ALT_UART_FAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FAR_OFST)) + +/* + * Register : Transmit FIFO Read Register - tfr + * + * Used in FIFO Access test mode. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [7:0] | R | 0x0 | Transmit FIFO Read + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Read - tfr + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, reading this register gives the data at the top + * of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the + * next data value that is currently at the top of the FIFO. When FIFO's are not + * enabled, reading this register gives the data in the THR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_MSB 7 +/* The width in bits of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_WIDTH 8 +/* The mask used to set the ALT_UART_TFR_TFR register field value. */ +#define ALT_UART_TFR_TFR_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_TFR_TFR register field value. */ +#define ALT_UART_TFR_TFR_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_TFR_TFR register field. */ +#define ALT_UART_TFR_TFR_RESET 0x0 +/* Extracts the ALT_UART_TFR_TFR field value from a register. */ +#define ALT_UART_TFR_TFR_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_TFR_TFR register field value suitable for setting the register. */ +#define ALT_UART_TFR_TFR_SET(value) (((value) << 0) & 0x000000ff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_TFR. + */ +struct ALT_UART_TFR_s +{ + const uint32_t tfr : 8; /* Transmit FIFO Read */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_TFR. */ +typedef volatile struct ALT_UART_TFR_s ALT_UART_TFR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_TFR register from the beginning of the component. */ +#define ALT_UART_TFR_OFST 0x74 +/* The address of the ALT_UART_TFR register. */ +#define ALT_UART_TFR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFR_OFST)) + +/* + * Register : Receive FIFO Write - RFW + * + * Used only with FIFO access test mode. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [7:0] | W | 0x0 | Receive FIFO Write Field + * [8] | W | 0x0 | Receive FIFO Parity Error + * [9] | W | 0x0 | Receive FIFO Framing Error + * [31:10] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Write Field - rfwd + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, the data that is written to the RFWD is pushed + * into the receive FIFO. Each consecutive write pushes the new data to the next + * write location in the receive FIFO. When FIFO's are not enabled, the data that + * is written to the RFWD is pushed into the RBR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_MSB 7 +/* The width in bits of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_WIDTH 8 +/* The mask used to set the ALT_UART_RFW_RFWD register field value. */ +#define ALT_UART_RFW_RFWD_SET_MSK 0x000000ff +/* The mask used to clear the ALT_UART_RFW_RFWD register field value. */ +#define ALT_UART_RFW_RFWD_CLR_MSK 0xffffff00 +/* The reset value of the ALT_UART_RFW_RFWD register field. */ +#define ALT_UART_RFW_RFWD_RESET 0x0 +/* Extracts the ALT_UART_RFW_RFWD field value from a register. */ +#define ALT_UART_RFW_RFWD_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_UART_RFW_RFWD register field value suitable for setting the register. */ +#define ALT_UART_RFW_RFWD_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : Receive FIFO Parity Error - rfpe + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, this bit is used to write parity error detection + * information to the receive FIFO. When FIFO's are not enabled, this bit is used + * to write parity error detection information to the RBR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_MSB 8 +/* The width in bits of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_WIDTH 1 +/* The mask used to set the ALT_UART_RFW_RFPE register field value. */ +#define ALT_UART_RFW_RFPE_SET_MSK 0x00000100 +/* The mask used to clear the ALT_UART_RFW_RFPE register field value. */ +#define ALT_UART_RFW_RFPE_CLR_MSK 0xfffffeff +/* The reset value of the ALT_UART_RFW_RFPE register field. */ +#define ALT_UART_RFW_RFPE_RESET 0x0 +/* Extracts the ALT_UART_RFW_RFPE field value from a register. */ +#define ALT_UART_RFW_RFPE_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_UART_RFW_RFPE register field value suitable for setting the register. */ +#define ALT_UART_RFW_RFPE_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Receive FIFO Framing Error - RFFE + * + * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to + * one). When FIFO's are enabled, this bit is used to write framing error detection + * information to the receive FIFO. When FIFO's are not enabled, this bit is used + * to write framing error detection information to the RBR. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_MSB 9 +/* The width in bits of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_WIDTH 1 +/* The mask used to set the ALT_UART_RFW_RFFE register field value. */ +#define ALT_UART_RFW_RFFE_SET_MSK 0x00000200 +/* The mask used to clear the ALT_UART_RFW_RFFE register field value. */ +#define ALT_UART_RFW_RFFE_CLR_MSK 0xfffffdff +/* The reset value of the ALT_UART_RFW_RFFE register field. */ +#define ALT_UART_RFW_RFFE_RESET 0x0 +/* Extracts the ALT_UART_RFW_RFFE field value from a register. */ +#define ALT_UART_RFW_RFFE_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_UART_RFW_RFFE register field value suitable for setting the register. */ +#define ALT_UART_RFW_RFFE_SET(value) (((value) << 9) & 0x00000200) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_RFW. + */ +struct ALT_UART_RFW_s +{ + uint32_t rfwd : 8; /* Receive FIFO Write Field */ + uint32_t rfpe : 1; /* Receive FIFO Parity Error */ + uint32_t RFFE : 1; /* Receive FIFO Framing Error */ + uint32_t : 22; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_RFW. */ +typedef volatile struct ALT_UART_RFW_s ALT_UART_RFW_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_RFW register from the beginning of the component. */ +#define ALT_UART_RFW_OFST 0x78 +/* The address of the ALT_UART_RFW register. */ +#define ALT_UART_RFW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFW_OFST)) + +/* + * Register : UART Status Register - usr + * + * Status of FIFO Operations. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | R | 0x1 | Transmit FIFO Not Full + * [2] | R | 0x1 | Transmit FIFO Empty + * [3] | R | 0x0 | Receive FIFO Not Empty + * [4] | R | 0x0 | Receive FIFO Full + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Not Full - tfnf + * + * This Bit is used to indicate that the transmit FIFO in not full. This bit is + * cleared when the Tx FIFO is full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:-------------------------- + * ALT_UART_USR_TFNF_E_FULL | 0x0 | Transmit FIFO is full + * ALT_UART_USR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_TFNF + * + * Transmit FIFO is full + */ +#define ALT_UART_USR_TFNF_E_FULL 0x0 +/* + * Enumerated value for register field ALT_UART_USR_TFNF + * + * Transmit FIFO is not full + */ +#define ALT_UART_USR_TFNF_E_NOTFULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_MSB 1 +/* The width in bits of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_WIDTH 1 +/* The mask used to set the ALT_UART_USR_TFNF register field value. */ +#define ALT_UART_USR_TFNF_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_USR_TFNF register field value. */ +#define ALT_UART_USR_TFNF_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_USR_TFNF register field. */ +#define ALT_UART_USR_TFNF_RESET 0x1 +/* Extracts the ALT_UART_USR_TFNF field value from a register. */ +#define ALT_UART_USR_TFNF_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_USR_TFNF register field value suitable for setting the register. */ +#define ALT_UART_USR_TFNF_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Transmit FIFO Empty - tfe + * + * This is used to indicate that the transmit FIFO is completely empty. This bit is + * cleared when the Tx FIFO is no longer empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:--------------------------- + * ALT_UART_USR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty + * ALT_UART_USR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_TFE + * + * Transmit FIFO is not empty + */ +#define ALT_UART_USR_TFE_E_NOTEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_USR_TFE + * + * Transmit FIFO is empty + */ +#define ALT_UART_USR_TFE_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_MSB 2 +/* The width in bits of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_WIDTH 1 +/* The mask used to set the ALT_UART_USR_TFE register field value. */ +#define ALT_UART_USR_TFE_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_USR_TFE register field value. */ +#define ALT_UART_USR_TFE_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_USR_TFE register field. */ +#define ALT_UART_USR_TFE_RESET 0x1 +/* Extracts the ALT_UART_USR_TFE field value from a register. */ +#define ALT_UART_USR_TFE_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_USR_TFE register field value suitable for setting the register. */ +#define ALT_UART_USR_TFE_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Receive FIFO Not Empty - rfne + * + * This Bit is used to indicate that the receive FIFO contains one or more entries. + * This bit is cleared when the Rx FIFO is empty. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------------- + * ALT_UART_USR_RFNE_E_EMPTY | 0x0 | Receiive FIFO is empty + * ALT_UART_USR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_RFNE + * + * Receiive FIFO is empty + */ +#define ALT_UART_USR_RFNE_E_EMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_USR_RFNE + * + * Receive FIFO is not empty + */ +#define ALT_UART_USR_RFNE_E_NOTEMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_MSB 3 +/* The width in bits of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_WIDTH 1 +/* The mask used to set the ALT_UART_USR_RFNE register field value. */ +#define ALT_UART_USR_RFNE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_UART_USR_RFNE register field value. */ +#define ALT_UART_USR_RFNE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_UART_USR_RFNE register field. */ +#define ALT_UART_USR_RFNE_RESET 0x0 +/* Extracts the ALT_UART_USR_RFNE field value from a register. */ +#define ALT_UART_USR_RFNE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_UART_USR_RFNE register field value suitable for setting the register. */ +#define ALT_UART_USR_RFNE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Full - rff + * + * This Bit is used to indicate that the receive FIFO is completely full. This bit + * is cleared when the Rx FIFO is no longer full. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------|:------|:----------------------- + * ALT_UART_USR_RFF_E_NOTFULL | 0x0 | Receiive FIFO not full + * ALT_UART_USR_RFF_E_FULL | 0x1 | Transmit FIFO is full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_USR_RFF + * + * Receiive FIFO not full + */ +#define ALT_UART_USR_RFF_E_NOTFULL 0x0 +/* + * Enumerated value for register field ALT_UART_USR_RFF + * + * Transmit FIFO is full + */ +#define ALT_UART_USR_RFF_E_FULL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_MSB 4 +/* The width in bits of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_WIDTH 1 +/* The mask used to set the ALT_UART_USR_RFF register field value. */ +#define ALT_UART_USR_RFF_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_USR_RFF register field value. */ +#define ALT_UART_USR_RFF_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_USR_RFF register field. */ +#define ALT_UART_USR_RFF_RESET 0x0 +/* Extracts the ALT_UART_USR_RFF field value from a register. */ +#define ALT_UART_USR_RFF_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_USR_RFF register field value suitable for setting the register. */ +#define ALT_UART_USR_RFF_SET(value) (((value) << 4) & 0x00000010) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_USR. + */ +struct ALT_UART_USR_s +{ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t tfnf : 1; /* Transmit FIFO Not Full */ + const uint32_t tfe : 1; /* Transmit FIFO Empty */ + const uint32_t rfne : 1; /* Receive FIFO Not Empty */ + const uint32_t rff : 1; /* Receive FIFO Full */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_USR. */ +typedef volatile struct ALT_UART_USR_s ALT_UART_USR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_USR register from the beginning of the component. */ +#define ALT_UART_USR_OFST 0x7c +/* The address of the ALT_UART_USR register. */ +#define ALT_UART_USR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_USR_OFST)) + +/* + * Register : Transmit FIFO Level - tfl + * + * This register is used to specify the number of data entries in the Tx FIFO. + * Status Bits in USR register monitor the FIFO state. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------- + * [4:0] | R | 0x0 | Transmit FIFO Level + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transmit FIFO Level - tfl + * + * This indicates the number of data entries in the transmit FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_MSB 4 +/* The width in bits of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_WIDTH 5 +/* The mask used to set the ALT_UART_TFL_TFL register field value. */ +#define ALT_UART_TFL_TFL_SET_MSK 0x0000001f +/* The mask used to clear the ALT_UART_TFL_TFL register field value. */ +#define ALT_UART_TFL_TFL_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_UART_TFL_TFL register field. */ +#define ALT_UART_TFL_TFL_RESET 0x0 +/* Extracts the ALT_UART_TFL_TFL field value from a register. */ +#define ALT_UART_TFL_TFL_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_UART_TFL_TFL register field value suitable for setting the register. */ +#define ALT_UART_TFL_TFL_SET(value) (((value) << 0) & 0x0000001f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_TFL. + */ +struct ALT_UART_TFL_s +{ + const uint32_t tfl : 5; /* Transmit FIFO Level */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_TFL. */ +typedef volatile struct ALT_UART_TFL_s ALT_UART_TFL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_TFL register from the beginning of the component. */ +#define ALT_UART_TFL_OFST 0x80 +/* The address of the ALT_UART_TFL register. */ +#define ALT_UART_TFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFL_OFST)) + +/* + * Register : Receive FIFO Level Write - rfl + * + * This register is used to specify the number of data entries in the Tx FIFO. + * Status Bits in USR register monitor the FIFO state. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------------------- + * [4:0] | R | 0x0 | Receive FIFO Level Status + * [31:5] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Receive FIFO Level Status - rfl + * + * This indicates the number of data entries in the receive FIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_MSB 4 +/* The width in bits of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_WIDTH 5 +/* The mask used to set the ALT_UART_RFL_RFL register field value. */ +#define ALT_UART_RFL_RFL_SET_MSK 0x0000001f +/* The mask used to clear the ALT_UART_RFL_RFL register field value. */ +#define ALT_UART_RFL_RFL_CLR_MSK 0xffffffe0 +/* The reset value of the ALT_UART_RFL_RFL register field. */ +#define ALT_UART_RFL_RFL_RESET 0x0 +/* Extracts the ALT_UART_RFL_RFL field value from a register. */ +#define ALT_UART_RFL_RFL_GET(value) (((value) & 0x0000001f) >> 0) +/* Produces a ALT_UART_RFL_RFL register field value suitable for setting the register. */ +#define ALT_UART_RFL_RFL_SET(value) (((value) << 0) & 0x0000001f) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_RFL. + */ +struct ALT_UART_RFL_s +{ + const uint32_t rfl : 5; /* Receive FIFO Level Status */ + uint32_t : 27; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_RFL. */ +typedef volatile struct ALT_UART_RFL_s ALT_UART_RFL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_RFL register from the beginning of the component. */ +#define ALT_UART_RFL_OFST 0x84 +/* The address of the ALT_UART_RFL register. */ +#define ALT_UART_RFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFL_OFST)) + +/* + * Register : Software Reset Register - srr + * + * Provides Software Resets for Tx/Rx FIFO's and the uart. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:-------------- + * [0] | W | 0x0 | UART Reset + * [1] | W | 0x0 | Rx FIFO Reset + * [2] | W | 0x0 | Tx FIFO Reset + * [31:3] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : UART Reset - ur + * + * This asynchronously resets the UART and synchronously removes the reset + * assertion. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:-------------- + * ALT_UART_SRR_UR_E_NORST | 0x0 | No reset Uart + * ALT_UART_SRR_UR_E_RST | 0x1 | Reset Uart + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRR_UR + * + * No reset Uart + */ +#define ALT_UART_SRR_UR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_SRR_UR + * + * Reset Uart + */ +#define ALT_UART_SRR_UR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_MSB 0 +/* The width in bits of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_WIDTH 1 +/* The mask used to set the ALT_UART_SRR_UR register field value. */ +#define ALT_UART_SRR_UR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SRR_UR register field value. */ +#define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SRR_UR register field. */ +#define ALT_UART_SRR_UR_RESET 0x0 +/* Extracts the ALT_UART_SRR_UR field value from a register. */ +#define ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SRR_UR register field value suitable for setting the register. */ +#define ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Rx FIFO Reset - rfr + * + * This is a shadow register for the Rx FIFO Reset bit (FCR[1]). This can be used + * to remove the burden on software having to store previously written FCR values + * (which are pretty static) just to reset the receive FIFO. This resets the + * control portion of the receive FIFO and treats the FIFO as empty. This will also + * de-assert the DMA Rx request and single signals. Note that this bit is 'self- + * clearing' and it is not necessary to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_UART_SRR_RFR_E_NORST | 0x0 | No reset Rx FIFO + * ALT_UART_SRR_RFR_E_RST | 0x1 | Reset Rx FIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRR_RFR + * + * No reset Rx FIFO + */ +#define ALT_UART_SRR_RFR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_SRR_RFR + * + * Reset Rx FIFO + */ +#define ALT_UART_SRR_RFR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_MSB 1 +/* The width in bits of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_WIDTH 1 +/* The mask used to set the ALT_UART_SRR_RFR register field value. */ +#define ALT_UART_SRR_RFR_SET_MSK 0x00000002 +/* The mask used to clear the ALT_UART_SRR_RFR register field value. */ +#define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd +/* The reset value of the ALT_UART_SRR_RFR register field. */ +#define ALT_UART_SRR_RFR_RESET 0x0 +/* Extracts the ALT_UART_SRR_RFR field value from a register. */ +#define ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_UART_SRR_RFR register field value suitable for setting the register. */ +#define ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Tx FIFO Reset - xfr + * + * This is a shadow register forthe Tx FIFO Reset bit (FCR[2]). This can be used + * to remove the burden on software having to store previously written FCR values + * (which are pretty static) just to reset the transmit FIFO.This resets the + * control portion of the transmit FIFO and treats the FIFO as empty. This will + * also de-assert the DMA Tx request and single signals. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------|:------|:----------------- + * ALT_UART_SRR_XFR_E_NORST | 0x0 | No reset Tx FIFO + * ALT_UART_SRR_XFR_E_RST | 0x1 | Reset Tx FIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRR_XFR + * + * No reset Tx FIFO + */ +#define ALT_UART_SRR_XFR_E_NORST 0x0 +/* + * Enumerated value for register field ALT_UART_SRR_XFR + * + * Reset Tx FIFO + */ +#define ALT_UART_SRR_XFR_E_RST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_MSB 2 +/* The width in bits of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_WIDTH 1 +/* The mask used to set the ALT_UART_SRR_XFR register field value. */ +#define ALT_UART_SRR_XFR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_UART_SRR_XFR register field value. */ +#define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_UART_SRR_XFR register field. */ +#define ALT_UART_SRR_XFR_RESET 0x0 +/* Extracts the ALT_UART_SRR_XFR field value from a register. */ +#define ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_UART_SRR_XFR register field value suitable for setting the register. */ +#define ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRR. + */ +struct ALT_UART_SRR_s +{ + uint32_t ur : 1; /* UART Reset */ + uint32_t rfr : 1; /* Rx FIFO Reset */ + uint32_t xfr : 1; /* Tx FIFO Reset */ + uint32_t : 29; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRR. */ +typedef volatile struct ALT_UART_SRR_s ALT_UART_SRR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRR register from the beginning of the component. */ +#define ALT_UART_SRR_OFST 0x88 +/* The address of the ALT_UART_SRR register. */ +#define ALT_UART_SRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST)) + +/* + * Register : Shadow Request to Send - srts + * + * This is a shadow register for the RTS status (MCR[1]), this can be used to + * remove the burden of having to performing a read modify write on the MCR. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------- + * [0] | RW | 0x0 | Shadow Request to Send + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Request to Send - srts + * + * This is used to directly control the Request to Send (uart_rts_n) output. The + * Request to Send (uart_rts_n) output is used to inform the modem or data set that + * the UART is read to exchange data. The uart_rts_n signal is set low by + * programming MCR[1] (RTS) to a high. In Auto Flow Control, (MCR[5] set to one) + * and FIFO's are enabled (FCR[0] set to one), the uart_rts_n output is controlled + * in the same way, but is also gated with the receiver FIFO threshold trigger + * (uart_rts_n is inactive high when above the threshold). + * + * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held + * inactive high while the value of this location is internally looped back to an + * input. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------ + * ALT_UART_SRTS_SRTS_E_LOGIC0 | 0x1 | uart_rts_n logic0 + * ALT_UART_SRTS_SRTS_E_LOGIC1 | 0x0 | uart_rts_n logic1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRTS_SRTS + * + * uart_rts_n logic0 + */ +#define ALT_UART_SRTS_SRTS_E_LOGIC0 0x1 +/* + * Enumerated value for register field ALT_UART_SRTS_SRTS + * + * uart_rts_n logic1 + */ +#define ALT_UART_SRTS_SRTS_E_LOGIC1 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_MSB 0 +/* The width in bits of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_WIDTH 1 +/* The mask used to set the ALT_UART_SRTS_SRTS register field value. */ +#define ALT_UART_SRTS_SRTS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SRTS_SRTS register field value. */ +#define ALT_UART_SRTS_SRTS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SRTS_SRTS register field. */ +#define ALT_UART_SRTS_SRTS_RESET 0x0 +/* Extracts the ALT_UART_SRTS_SRTS field value from a register. */ +#define ALT_UART_SRTS_SRTS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SRTS_SRTS register field value suitable for setting the register. */ +#define ALT_UART_SRTS_SRTS_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRTS. + */ +struct ALT_UART_SRTS_s +{ + uint32_t srts : 1; /* Shadow Request to Send */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRTS. */ +typedef volatile struct ALT_UART_SRTS_s ALT_UART_SRTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRTS register from the beginning of the component. */ +#define ALT_UART_SRTS_OFST 0x8c +/* The address of the ALT_UART_SRTS register. */ +#define ALT_UART_SRTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRTS_OFST)) + +/* + * Register : Shadow Break Control Register - sbcr + * + * This is a shadow register for the Break bit [6] of the register LCR. This can be + * used to remove the burden of having to performing a read modify write on the + * LCR. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:--------------------- + * [0] | RW | 0x0 | Shadow Break Control + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Break Control - sbcr + * + * This is used to cause a break condition to be transmitted to the receiving + * device. If set to one the serial output is forced to the spacing (logic 0) + * state. When not in Loopback Mode, as determined by MCR[4], the uart_txd line is + * forced low until the Break bit is cleared. When in Loopback Mode, the break + * condition is internally looped back to the receiver. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:---------------------------- + * ALT_UART_SBCR_SBCR_E_DISD | 0x0 | no break + * ALT_UART_SBCR_SBCR_E_END | 0x1 | break serial output spacing + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SBCR_SBCR + * + * no break + */ +#define ALT_UART_SBCR_SBCR_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_SBCR_SBCR + * + * break serial output spacing + */ +#define ALT_UART_SBCR_SBCR_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_MSB 0 +/* The width in bits of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_WIDTH 1 +/* The mask used to set the ALT_UART_SBCR_SBCR register field value. */ +#define ALT_UART_SBCR_SBCR_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SBCR_SBCR register field value. */ +#define ALT_UART_SBCR_SBCR_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SBCR_SBCR register field. */ +#define ALT_UART_SBCR_SBCR_RESET 0x0 +/* Extracts the ALT_UART_SBCR_SBCR field value from a register. */ +#define ALT_UART_SBCR_SBCR_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SBCR_SBCR register field value suitable for setting the register. */ +#define ALT_UART_SBCR_SBCR_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SBCR. + */ +struct ALT_UART_SBCR_s +{ + uint32_t sbcr : 1; /* Shadow Break Control */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SBCR. */ +typedef volatile struct ALT_UART_SBCR_s ALT_UART_SBCR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SBCR register from the beginning of the component. */ +#define ALT_UART_SBCR_OFST 0x90 +/* The address of the ALT_UART_SBCR register. */ +#define ALT_UART_SBCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SBCR_OFST)) + +/* + * Register : Shadow DMA Mode - sdmam + * + * This is a shadow register for the DMA mode bit (FCR[3]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------- + * [0] | RW | 0x0 | Shadow DMA Mode + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow DMA Mode - sdmam + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the DMA + * Mode bit gets updated. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------|:------|:--------------------------- + * ALT_UART_SDMAM_SDMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode + * ALT_UART_SDMAM_SDMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SDMAM_SDMAM + * + * Single DMA Transfer Mode + */ +#define ALT_UART_SDMAM_SDMAM_E_SINGLE 0x0 +/* + * Enumerated value for register field ALT_UART_SDMAM_SDMAM + * + * Multiple DMA Transfer Mode + */ +#define ALT_UART_SDMAM_SDMAM_E_MULT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_MSB 0 +/* The width in bits of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_WIDTH 1 +/* The mask used to set the ALT_UART_SDMAM_SDMAM register field value. */ +#define ALT_UART_SDMAM_SDMAM_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SDMAM_SDMAM register field value. */ +#define ALT_UART_SDMAM_SDMAM_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SDMAM_SDMAM register field. */ +#define ALT_UART_SDMAM_SDMAM_RESET 0x0 +/* Extracts the ALT_UART_SDMAM_SDMAM field value from a register. */ +#define ALT_UART_SDMAM_SDMAM_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SDMAM_SDMAM register field value suitable for setting the register. */ +#define ALT_UART_SDMAM_SDMAM_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SDMAM. + */ +struct ALT_UART_SDMAM_s +{ + uint32_t sdmam : 1; /* Shadow DMA Mode */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SDMAM. */ +typedef volatile struct ALT_UART_SDMAM_s ALT_UART_SDMAM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SDMAM register from the beginning of the component. */ +#define ALT_UART_SDMAM_OFST 0x94 +/* The address of the ALT_UART_SDMAM register. */ +#define ALT_UART_SDMAM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SDMAM_OFST)) + +/* + * Register : Shadow FIFO Enable - sfe + * + * This is a shadow register for the FIFO enable bit [0] of register FCR. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [0] | RW | 0x0 | Shadow FIFO Enable + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow FIFO Enable - sfe + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the FIFO + * enable bit gets updated. This enables/disables the transmit (Tx) and receive (Rx + * ) FIFO's. If this bit is set to zero (disabled) after being enabled then both + * the Tx and Rx controller portion of FIFO's will be reset. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:-------------- + * ALT_UART_SFE_SFE_E_DISD | 0x0 | Disable Rx/Tx + * ALT_UART_SFE_SFE_E_END | 0x1 | Enable Rx/Tx + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SFE_SFE + * + * Disable Rx/Tx + */ +#define ALT_UART_SFE_SFE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_SFE_SFE + * + * Enable Rx/Tx + */ +#define ALT_UART_SFE_SFE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_MSB 0 +/* The width in bits of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_WIDTH 1 +/* The mask used to set the ALT_UART_SFE_SFE register field value. */ +#define ALT_UART_SFE_SFE_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_SFE_SFE register field value. */ +#define ALT_UART_SFE_SFE_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_SFE_SFE register field. */ +#define ALT_UART_SFE_SFE_RESET 0x0 +/* Extracts the ALT_UART_SFE_SFE field value from a register. */ +#define ALT_UART_SFE_SFE_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_SFE_SFE register field value suitable for setting the register. */ +#define ALT_UART_SFE_SFE_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SFE. + */ +struct ALT_UART_SFE_s +{ + uint32_t sfe : 1; /* Shadow FIFO Enable */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SFE. */ +typedef volatile struct ALT_UART_SFE_s ALT_UART_SFE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SFE register from the beginning of the component. */ +#define ALT_UART_SFE_OFST 0x98 +/* The address of the ALT_UART_SFE register. */ +#define ALT_UART_SFE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SFE_OFST)) + +/* + * Register : Shadow Rx Trigger - srt + * + * This is a shadow register for the Rx trigger bits (FCR[7:6]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------ + * [1:0] | RW | 0x0 | Shadow Rx Trigger Bits + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Rx Trigger Bits - srt + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the Rx + * trigger bit gets updated. This is used to select the trigger level in the + * receiver FIFO at which the Received Data Available Interrupt will be generated. + * It also determines when the uart_dma_rx_req_n signal will be asserted when DMA + * Mode (FCR[3]) is set to one. The enum below shows trigger levels that are + * supported. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------- + * ALT_UART_SRT_SRT_E_ONECHAR | 0x0 | one character in fifo + * ALT_UART_SRT_SRT_E_QUARTERFULL | 0x1 | FIFO 1/4 full + * ALT_UART_SRT_SRT_E_HALFFULL | 0x2 | FIFO 1/2 full + * ALT_UART_SRT_SRT_E_FULLLESS2 | 0x3 | FIFO 2 less than full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * one character in fifo + */ +#define ALT_UART_SRT_SRT_E_ONECHAR 0x0 +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * FIFO 1/4 full + */ +#define ALT_UART_SRT_SRT_E_QUARTERFULL 0x1 +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * FIFO 1/2 full + */ +#define ALT_UART_SRT_SRT_E_HALFFULL 0x2 +/* + * Enumerated value for register field ALT_UART_SRT_SRT + * + * FIFO 2 less than full + */ +#define ALT_UART_SRT_SRT_E_FULLLESS2 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_MSB 1 +/* The width in bits of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_WIDTH 2 +/* The mask used to set the ALT_UART_SRT_SRT register field value. */ +#define ALT_UART_SRT_SRT_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_SRT_SRT register field value. */ +#define ALT_UART_SRT_SRT_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_SRT_SRT register field. */ +#define ALT_UART_SRT_SRT_RESET 0x0 +/* Extracts the ALT_UART_SRT_SRT field value from a register. */ +#define ALT_UART_SRT_SRT_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_SRT_SRT register field value suitable for setting the register. */ +#define ALT_UART_SRT_SRT_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_SRT. + */ +struct ALT_UART_SRT_s +{ + uint32_t srt : 2; /* Shadow Rx Trigger Bits */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_SRT. */ +typedef volatile struct ALT_UART_SRT_s ALT_UART_SRT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_SRT register from the beginning of the component. */ +#define ALT_UART_SRT_OFST 0x9c +/* The address of the ALT_UART_SRT register. */ +#define ALT_UART_SRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRT_OFST)) + +/* + * Register : Shadow Tx Empty Trigger - stet + * + * This is a shadow register for the Tx empty trigger bits (FCR[5:4]). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------- + * [1:0] | RW | 0x0 | Shadow Tx Empty Trigger Bits + * [31:2] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Shadow Tx Empty Trigger Bits - stet + * + * This can be used to remove the burden of having to store the previously written + * value to the FCR in memory and having to mask this value so that only the Tx + * empty trigger bit gets updated. This is used to select the empty threshold level + * at which the THRE Interrupts will be generated when the mode is active. These + * threshold levels are also described in. The enum trigger levels are supported. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------- + * ALT_UART_STET_STET_E_FIFOEMPTY | 0x0 | FIFO empty + * ALT_UART_STET_STET_E_TWOCHARS | 0x1 | Two characters in FIFO + * ALT_UART_STET_STET_E_QUARTERFULL | 0x2 | FIFO quarter full + * ALT_UART_STET_STET_E_HALFFULL | 0x3 | FIFO half full + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * FIFO empty + */ +#define ALT_UART_STET_STET_E_FIFOEMPTY 0x0 +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * Two characters in FIFO + */ +#define ALT_UART_STET_STET_E_TWOCHARS 0x1 +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * FIFO quarter full + */ +#define ALT_UART_STET_STET_E_QUARTERFULL 0x2 +/* + * Enumerated value for register field ALT_UART_STET_STET + * + * FIFO half full + */ +#define ALT_UART_STET_STET_E_HALFFULL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_MSB 1 +/* The width in bits of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_WIDTH 2 +/* The mask used to set the ALT_UART_STET_STET register field value. */ +#define ALT_UART_STET_STET_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_STET_STET register field value. */ +#define ALT_UART_STET_STET_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_STET_STET register field. */ +#define ALT_UART_STET_STET_RESET 0x0 +/* Extracts the ALT_UART_STET_STET field value from a register. */ +#define ALT_UART_STET_STET_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_STET_STET register field value suitable for setting the register. */ +#define ALT_UART_STET_STET_SET(value) (((value) << 0) & 0x00000003) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_STET. + */ +struct ALT_UART_STET_s +{ + uint32_t stet : 2; /* Shadow Tx Empty Trigger Bits */ + uint32_t : 30; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_STET. */ +typedef volatile struct ALT_UART_STET_s ALT_UART_STET_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_STET register from the beginning of the component. */ +#define ALT_UART_STET_OFST 0xa0 +/* The address of the ALT_UART_STET register. */ +#define ALT_UART_STET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STET_OFST)) + +/* + * Register : Halt Tx - htx + * + * Used to halt transmission for testing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------- + * [0] | RW | 0x0 | Halt Tx Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Halt Tx Bits - htx + * + * This register is use to halt transmissions for testing, so that the transmit + * FIFO can be filled by the master when FIFO's are enabled. + * + * Note, if FIFO's are not enabled, the setting of the halt Tx register will have + * no effect on operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------|:------|:----------------- + * ALT_UART_HTX_HTX_E_DISD | 0x0 | Halt Tx disabled + * ALT_UART_HTX_HTX_E_END | 0x1 | Halt Tx enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_HTX_HTX + * + * Halt Tx disabled + */ +#define ALT_UART_HTX_HTX_E_DISD 0x0 +/* + * Enumerated value for register field ALT_UART_HTX_HTX + * + * Halt Tx enabled + */ +#define ALT_UART_HTX_HTX_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_MSB 0 +/* The width in bits of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_WIDTH 1 +/* The mask used to set the ALT_UART_HTX_HTX register field value. */ +#define ALT_UART_HTX_HTX_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_HTX_HTX register field value. */ +#define ALT_UART_HTX_HTX_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_HTX_HTX register field. */ +#define ALT_UART_HTX_HTX_RESET 0x0 +/* Extracts the ALT_UART_HTX_HTX field value from a register. */ +#define ALT_UART_HTX_HTX_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_HTX_HTX register field value suitable for setting the register. */ +#define ALT_UART_HTX_HTX_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_HTX. + */ +struct ALT_UART_HTX_s +{ + uint32_t htx : 1; /* Halt Tx Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_HTX. */ +typedef volatile struct ALT_UART_HTX_s ALT_UART_HTX_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_HTX register from the beginning of the component. */ +#define ALT_UART_HTX_OFST 0xa4 +/* The address of the ALT_UART_HTX register. */ +#define ALT_UART_HTX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_HTX_OFST)) + +/* + * Register : DMA Software Acknowledge - dmasa + * + * DMA Operation Control + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------ + * [0] | W | 0x0 | DMA Software Acknowledge Bits + * [31:1] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : DMA Software Acknowledge Bits - dmasa + * + * This register is used to perform DMA software acknowledge if a transfer needs to + * be terminated due to an error condition. For example, if the DMA disables the + * channel, then the uart should clear its request. This will cause the Tx request, + * Tx single, Rx request and Rx single signals to de-assert. Note that this bit is + * 'self-clearing' and it is not necessary to clear this bit. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_MSB 0 +/* The width in bits of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_WIDTH 1 +/* The mask used to set the ALT_UART_DMASA_DMASA register field value. */ +#define ALT_UART_DMASA_DMASA_SET_MSK 0x00000001 +/* The mask used to clear the ALT_UART_DMASA_DMASA register field value. */ +#define ALT_UART_DMASA_DMASA_CLR_MSK 0xfffffffe +/* The reset value of the ALT_UART_DMASA_DMASA register field. */ +#define ALT_UART_DMASA_DMASA_RESET 0x0 +/* Extracts the ALT_UART_DMASA_DMASA field value from a register. */ +#define ALT_UART_DMASA_DMASA_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_UART_DMASA_DMASA register field value suitable for setting the register. */ +#define ALT_UART_DMASA_DMASA_SET(value) (((value) << 0) & 0x00000001) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_DMASA. + */ +struct ALT_UART_DMASA_s +{ + uint32_t dmasa : 1; /* DMA Software Acknowledge Bits */ + uint32_t : 31; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_DMASA. */ +typedef volatile struct ALT_UART_DMASA_s ALT_UART_DMASA_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_DMASA register from the beginning of the component. */ +#define ALT_UART_DMASA_OFST 0xa8 +/* The address of the ALT_UART_DMASA register. */ +#define ALT_UART_DMASA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_DMASA_OFST)) + +/* + * Register : Component Parameter Register - cpr + * + * Describes various fixed hardware setups states. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [1:0] | R | 0x2 | APB DATA WIDTH + * [3:2] | ??? | 0x0 | *UNDEFINED* + * [4] | R | 0x1 | Auto Flow Control + * [5] | R | 0x1 | THRE MODE + * [6] | R | 0x0 | SIR MODE Unsupported + * [7] | R | 0x0 | SIR LP MODE Unsupported + * [8] | R | 0x1 | ADDITIONAL FEATURES Supported + * [9] | R | 0x1 | FIFO ACCESS Supported + * [10] | R | 0x1 | FIFO STAT Supported + * [11] | R | 0x1 | SHADOW Supported + * [12] | R | 0x1 | Configuartion ID Register Present + * [13] | R | 0x1 | DMA EXTRA Supported + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [23:16] | R | 0x37 | FIFO Depth + * [31:24] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : APB DATA WIDTH - apbdatawidth + * + * Fixed to support an ABP data bus width of 32-bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------- + * ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH + * + * APB Data Width = 32-bits + */ +#define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_MSB 1 +/* The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value. */ +#define ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003 +/* The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value. */ +#define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc +/* The reset value of the ALT_UART_CPR_APBDATAWIDTH register field. */ +#define ALT_UART_CPR_APBDATAWIDTH_RESET 0x2 +/* Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register. */ +#define ALT_UART_CPR_APBDATAWIDTH_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register. */ +#define ALT_UART_CPR_APBDATAWIDTH_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Auto Flow Control - afce_mode + * + * Allows auto flow control. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------ + * ALT_UART_CPR_AFCE_MOD_E_END | 0x1 | Auto Flow + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_AFCE_MOD + * + * Auto Flow + */ +#define ALT_UART_CPR_AFCE_MOD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_MSB 4 +/* The width in bits of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_AFCE_MOD register field value. */ +#define ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010 +/* The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value. */ +#define ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef +/* The reset value of the ALT_UART_CPR_AFCE_MOD register field. */ +#define ALT_UART_CPR_AFCE_MOD_RESET 0x1 +/* Extracts the ALT_UART_CPR_AFCE_MOD field value from a register. */ +#define ALT_UART_CPR_AFCE_MOD_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_AFCE_MOD_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : THRE MODE - thre_mode + * + * Programmable Transmitter Hold Register Empty interrupt + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:------------------------------------------ + * ALT_UART_CPR_THRE_MOD_E_END | 0x1 | Programmable Tx Hold Reg. Empty interrupt + * : | | present + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_THRE_MOD + * + * Programmable Tx Hold Reg. Empty interrupt present + */ +#define ALT_UART_CPR_THRE_MOD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_MSB 5 +/* The width in bits of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_THRE_MOD register field value. */ +#define ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_UART_CPR_THRE_MOD register field value. */ +#define ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_UART_CPR_THRE_MOD register field. */ +#define ALT_UART_CPR_THRE_MOD_RESET 0x1 +/* Extracts the ALT_UART_CPR_THRE_MOD field value from a register. */ +#define ALT_UART_CPR_THRE_MOD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_THRE_MOD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : SIR MODE Unsupported - sir_mode + * + * Sir mode not used in this application. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------|:------|:----------------------- + * ALT_UART_CPR_SIR_MOD_E_DISD | 0x0 | Sir Mode Not Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_SIR_MOD + * + * Sir Mode Not Supported + */ +#define ALT_UART_CPR_SIR_MOD_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_MSB 6 +/* The width in bits of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_SIR_MOD register field value. */ +#define ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040 +/* The mask used to clear the ALT_UART_CPR_SIR_MOD register field value. */ +#define ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf +/* The reset value of the ALT_UART_CPR_SIR_MOD register field. */ +#define ALT_UART_CPR_SIR_MOD_RESET 0x0 +/* Extracts the ALT_UART_CPR_SIR_MOD field value from a register. */ +#define ALT_UART_CPR_SIR_MOD_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_SIR_MOD_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : SIR LP MODE Unsupported - sir_lp_mode + * + * LP Sir Mode not used in this application. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:-------------------------- + * ALT_UART_CPR_SIR_LP_MOD_E_DISD | 0x0 | LP Sir Mode Not Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD + * + * LP Sir Mode Not Supported + */ +#define ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_MSB 7 +/* The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value. */ +#define ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080 +/* The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value. */ +#define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f +/* The reset value of the ALT_UART_CPR_SIR_LP_MOD register field. */ +#define ALT_UART_CPR_SIR_LP_MOD_RESET 0x0 +/* Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register. */ +#define ALT_UART_CPR_SIR_LP_MOD_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_SIR_LP_MOD_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : ADDITIONAL FEATURES Supported - additional_feat + * + * Configures the uart to include fifo status register, shadow registers and + * encoded parameter register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------ + * ALT_UART_CPR_ADDITIONAL_FEAT_E_END | 0x1 | Additional Features Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT + * + * Additional Features Supported + */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8 +/* The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100 +/* The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff +/* The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1 +/* Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register. */ +#define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : FIFO ACCESS Supported - fifo_access + * + * Configures the peripheral to have a programmable FIFO access mode. This is used + * for test purposes, to allow the receiver FIFO to be written and the transmit + * FIFO to be read when FIFOs are implemented and enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------- + * ALT_UART_CPR_FIFO_ACCESS_E_END | 0x1 | FIFO Access Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS + * + * FIFO Access Supported + */ +#define ALT_UART_CPR_FIFO_ACCESS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_MSB 9 +/* The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value. */ +#define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200 +/* The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value. */ +#define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff +/* The reset value of the ALT_UART_CPR_FIFO_ACCESS register field. */ +#define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1 +/* Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register. */ +#define ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register. */ +#define ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : FIFO STAT Supported - fifo_stat + * + * Configures the peripheral to have three additional FIFO status registers. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------- + * ALT_UART_CPR_FIFO_STAT_E_END | 0x1 | FIFO Stat Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_FIFO_STAT + * + * FIFO Stat Supported + */ +#define ALT_UART_CPR_FIFO_STAT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_MSB 10 +/* The width in bits of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_FIFO_STAT register field value. */ +#define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400 +/* The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value. */ +#define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff +/* The reset value of the ALT_UART_CPR_FIFO_STAT register field. */ +#define ALT_UART_CPR_FIFO_STAT_RESET 0x1 +/* Extracts the ALT_UART_CPR_FIFO_STAT field value from a register. */ +#define ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register. */ +#define ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : SHADOW Supported - shadow + * + * Configures the peripheral to have seven additional registers that shadow some of + * the existing register bits that are regularly modified by software. These can be + * used to reduce the software overhead that is introduced by having to perform + * read-modify writes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------|:------|:----------------- + * ALT_UART_CPR_SHADOW_E_END | 0x1 | Shadow Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_SHADOW + * + * Shadow Supported + */ +#define ALT_UART_CPR_SHADOW_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_MSB 11 +/* The width in bits of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_SHADOW register field value. */ +#define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800 +/* The mask used to clear the ALT_UART_CPR_SHADOW register field value. */ +#define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_UART_CPR_SHADOW register field. */ +#define ALT_UART_CPR_SHADOW_RESET 0x1 +/* Extracts the ALT_UART_CPR_SHADOW field value from a register. */ +#define ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register. */ +#define ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Configuartion ID Register Present - uart_add_encoded_param + * + * Configures the peripheral to have a configuration identification register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END | 0x1 | ID register present + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM + * + * ID register present + */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12 +/* The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000 +/* The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff +/* The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1 +/* Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register. */ +#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : DMA EXTRA Supported - dma_extra + * + * Configures the peripheral to have four additional DMA signals on the interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------|:------|:-------------------- + * ALT_UART_CPR_DMA_EXTRA_E_END | 0x1 | DMA Extra Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_DMA_EXTRA + * + * DMA Extra Supported + */ +#define ALT_UART_CPR_DMA_EXTRA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_MSB 13 +/* The width in bits of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_WIDTH 1 +/* The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value. */ +#define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000 +/* The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value. */ +#define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff +/* The reset value of the ALT_UART_CPR_DMA_EXTRA register field. */ +#define ALT_UART_CPR_DMA_EXTRA_RESET 0x1 +/* Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register. */ +#define ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register. */ +#define ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : FIFO Depth - fifo_mode + * + * Receiver and Transmitter FIFO depth in bytes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES | 0x80 | FIFO Depth 128 bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_UART_CPR_FIFO_MOD + * + * FIFO Depth 128 bytes + */ +#define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80 + +/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_MSB 23 +/* The width in bits of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_WIDTH 8 +/* The mask used to set the ALT_UART_CPR_FIFO_MOD register field value. */ +#define ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value. */ +#define ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff +/* The reset value of the ALT_UART_CPR_FIFO_MOD register field. */ +#define ALT_UART_CPR_FIFO_MOD_RESET 0x37 +/* Extracts the ALT_UART_CPR_FIFO_MOD field value from a register. */ +#define ALT_UART_CPR_FIFO_MOD_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register. */ +#define ALT_UART_CPR_FIFO_MOD_SET(value) (((value) << 16) & 0x00ff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_CPR. + */ +struct ALT_UART_CPR_s +{ + const uint32_t apbdatawidth : 2; /* APB DATA WIDTH */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t afce_mode : 1; /* Auto Flow Control */ + const uint32_t thre_mode : 1; /* THRE MODE */ + const uint32_t sir_mode : 1; /* SIR MODE Unsupported */ + const uint32_t sir_lp_mode : 1; /* SIR LP MODE Unsupported */ + const uint32_t additional_feat : 1; /* ADDITIONAL FEATURES Supported */ + const uint32_t fifo_access : 1; /* FIFO ACCESS Supported */ + const uint32_t fifo_stat : 1; /* FIFO STAT Supported */ + const uint32_t shadow : 1; /* SHADOW Supported */ + const uint32_t uart_add_encoded_param : 1; /* Configuartion ID Register Present */ + const uint32_t dma_extra : 1; /* DMA EXTRA Supported */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t fifo_mode : 8; /* FIFO Depth */ + uint32_t : 8; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_UART_CPR. */ +typedef volatile struct ALT_UART_CPR_s ALT_UART_CPR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_CPR register from the beginning of the component. */ +#define ALT_UART_CPR_OFST 0xf4 +/* The address of the ALT_UART_CPR register. */ +#define ALT_UART_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST)) + +/* + * Register : Component Version - ucv + * + * Used only with Additional Features + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------- + * [31:0] | R | 0x3331312a | ASCII version + * + */ +/* + * Field : ASCII version - uart_component_version + * + * ASCII value for each number in the version, followed by *For example 32_30_31_2A + * represents the version 2.01a + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_MSB 31 +/* The width in bits of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_WIDTH 32 +/* The mask used to set the ALT_UART_UCV_UART_COMPONENT_VER register field value. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_SET_MSK 0xffffffff +/* The mask used to clear the ALT_UART_UCV_UART_COMPONENT_VER register field value. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_CLR_MSK 0x00000000 +/* The reset value of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_RESET 0x3331312a +/* Extracts the ALT_UART_UCV_UART_COMPONENT_VER field value from a register. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_UART_UCV_UART_COMPONENT_VER register field value suitable for setting the register. */ +#define ALT_UART_UCV_UART_COMPONENT_VER_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_UCV. + */ +struct ALT_UART_UCV_s +{ + const uint32_t uart_component_version : 32; /* ASCII version */ +}; + +/* The typedef declaration for register ALT_UART_UCV. */ +typedef volatile struct ALT_UART_UCV_s ALT_UART_UCV_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_UCV register from the beginning of the component. */ +#define ALT_UART_UCV_OFST 0xf8 +/* The address of the ALT_UART_UCV register. */ +#define ALT_UART_UCV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_UCV_OFST)) + +/* + * Register : Component Type Register - ctr + * + * Describes a hex value associated with the component. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:-------------- + * [31:0] | R | 0x44570110 | Peripheral ID + * + */ +/* + * Field : Peripheral ID - peripheral_id + * + * This register contains the peripherals identification code. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_MSB 31 +/* The width in bits of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_WIDTH 32 +/* The mask used to set the ALT_UART_CTR_PERIPHERAL_ID register field value. */ +#define ALT_UART_CTR_PERIPHERAL_ID_SET_MSK 0xffffffff +/* The mask used to clear the ALT_UART_CTR_PERIPHERAL_ID register field value. */ +#define ALT_UART_CTR_PERIPHERAL_ID_CLR_MSK 0x00000000 +/* The reset value of the ALT_UART_CTR_PERIPHERAL_ID register field. */ +#define ALT_UART_CTR_PERIPHERAL_ID_RESET 0x44570110 +/* Extracts the ALT_UART_CTR_PERIPHERAL_ID field value from a register. */ +#define ALT_UART_CTR_PERIPHERAL_ID_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_UART_CTR_PERIPHERAL_ID register field value suitable for setting the register. */ +#define ALT_UART_CTR_PERIPHERAL_ID_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_UART_CTR. + */ +struct ALT_UART_CTR_s +{ + const uint32_t peripheral_id : 32; /* Peripheral ID */ +}; + +/* The typedef declaration for register ALT_UART_CTR. */ +typedef volatile struct ALT_UART_CTR_s ALT_UART_CTR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_UART_CTR register from the beginning of the component. */ +#define ALT_UART_CTR_OFST 0xfc +/* The address of the ALT_UART_CTR register. */ +#define ALT_UART_CTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CTR_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_UART. + */ +struct ALT_UART_s +{ + volatile ALT_UART_RBR_THR_DLL_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */ + volatile ALT_UART_IER_DLH_t ier_dlh; /* ALT_UART_IER_DLH */ + /* Union for registers colocated at base address offset #0x. */ + union + { + volatile ALT_UART_IIR_t iir; /* ALT_UART_IIR */ + volatile ALT_UART_FCR_t fcr; /* ALT_UART_FCR */ + } _u_0x8; + volatile ALT_UART_LCR_t lcr; /* ALT_UART_LCR */ + volatile ALT_UART_MCR_t mcr; /* ALT_UART_MCR */ + volatile ALT_UART_LSR_t lsr; /* ALT_UART_LSR */ + volatile ALT_UART_MSR_t msr; /* ALT_UART_MSR */ + volatile ALT_UART_SCR_t scr; /* ALT_UART_SCR */ + volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */ + volatile ALT_UART_SRBR_t srbr; /* ALT_UART_SRBR */ + volatile ALT_UART_STHR_t sthr; /* ALT_UART_STHR */ + volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */ + volatile ALT_UART_FAR_t far; /* ALT_UART_FAR */ + volatile ALT_UART_TFR_t tfr; /* ALT_UART_TFR */ + volatile ALT_UART_RFW_t RFW; /* ALT_UART_RFW */ + volatile ALT_UART_USR_t usr; /* ALT_UART_USR */ + volatile ALT_UART_TFL_t tfl; /* ALT_UART_TFL */ + volatile ALT_UART_RFL_t rfl; /* ALT_UART_RFL */ + volatile ALT_UART_SRR_t srr; /* ALT_UART_SRR */ + volatile ALT_UART_SRTS_t srts; /* ALT_UART_SRTS */ + volatile ALT_UART_SBCR_t sbcr; /* ALT_UART_SBCR */ + volatile ALT_UART_SDMAM_t sdmam; /* ALT_UART_SDMAM */ + volatile ALT_UART_SFE_t sfe; /* ALT_UART_SFE */ + volatile ALT_UART_SRT_t srt; /* ALT_UART_SRT */ + volatile ALT_UART_STET_t stet; /* ALT_UART_STET */ + volatile ALT_UART_HTX_t htx; /* ALT_UART_HTX */ + volatile ALT_UART_DMASA_t dmasa; /* ALT_UART_DMASA */ + volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */ + volatile ALT_UART_CPR_t cpr; /* ALT_UART_CPR */ + volatile ALT_UART_UCV_t ucv; /* ALT_UART_UCV */ + volatile ALT_UART_CTR_t ctr; /* ALT_UART_CTR */ +}; + +/* The typedef declaration for register group ALT_UART. */ +typedef volatile struct ALT_UART_s ALT_UART_t; +/* The struct declaration for the raw register contents of register group ALT_UART. */ +struct ALT_UART_raw_s +{ + volatile uint32_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */ + volatile uint32_t ier_dlh; /* ALT_UART_IER_DLH */ + /* Union for registers colocated at base address offset #0x. */ + union + { + volatile uint32_t iir; /* ALT_UART_IIR */ + volatile uint32_t fcr; /* ALT_UART_FCR */ + } _u_0x8; + volatile uint32_t lcr; /* ALT_UART_LCR */ + volatile uint32_t mcr; /* ALT_UART_MCR */ + volatile uint32_t lsr; /* ALT_UART_LSR */ + volatile uint32_t msr; /* ALT_UART_MSR */ + volatile uint32_t scr; /* ALT_UART_SCR */ + volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */ + volatile uint32_t srbr; /* ALT_UART_SRBR */ + volatile uint32_t sthr; /* ALT_UART_STHR */ + volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */ + volatile uint32_t far; /* ALT_UART_FAR */ + volatile uint32_t tfr; /* ALT_UART_TFR */ + volatile uint32_t RFW; /* ALT_UART_RFW */ + volatile uint32_t usr; /* ALT_UART_USR */ + volatile uint32_t tfl; /* ALT_UART_TFL */ + volatile uint32_t rfl; /* ALT_UART_RFL */ + volatile uint32_t srr; /* ALT_UART_SRR */ + volatile uint32_t srts; /* ALT_UART_SRTS */ + volatile uint32_t sbcr; /* ALT_UART_SBCR */ + volatile uint32_t sdmam; /* ALT_UART_SDMAM */ + volatile uint32_t sfe; /* ALT_UART_SFE */ + volatile uint32_t srt; /* ALT_UART_SRT */ + volatile uint32_t stet; /* ALT_UART_STET */ + volatile uint32_t htx; /* ALT_UART_HTX */ + volatile uint32_t dmasa; /* ALT_UART_DMASA */ + volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */ + volatile uint32_t cpr; /* ALT_UART_CPR */ + volatile uint32_t ucv; /* ALT_UART_UCV */ + volatile uint32_t ctr; /* ALT_UART_CTR */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_UART. */ +typedef volatile struct ALT_UART_raw_s ALT_UART_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_UART_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_usb.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_usb.h new file mode 100644 index 000000000..dd688b78e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_usb.h @@ -0,0 +1,114043 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - ALT_USB */ + +#ifndef __ALTERA_ALT_USB_H__ +#define __ALTERA_ALT_USB_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Component : USB OTG Controller Module Registers - ALT_USB + * USB OTG Controller Module Registers + * + * Registers in the USB OTG Controller Module. + * + * Only the Core Global, Power and Clock Gating, Data FIFO Access, and Host Port + * registers can be accessedin both Host and Device modes. When the USB OTG + * Controller is operating in one mode, either Device or Host, the application must + * not access registers from the other mode. If an illegal access occurs, a Mode + * Mismatch interrupt is generated and reflected in the Core Interrupt register + * (GINTSTS.ModeMis). + * + * When the core switches from one mode to another, the registers in the new mode + * must be reprogrammed as they would be after a power-on reset. + * + * The register address map is fixed and does not depend on the module + * configuration (for example, how many endpoints are implemented). Host and Device + * mode registers occupy different addresses. + * + */ +/* + * Register Group : Global Registers - ALT_USB_GLOB + * Global Registers + * + * These registers are available in both Host and Device modes, and do not need to + * be reprogrammed when switching between these modes. + * + */ +/* + * Register : OTG Control and Status Register - gotgctl + * + * The OTG Control and Status register controls the behavior and reflects the + * status of the OTG function. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | R | 0x0 | Session Request Success + * [1] | RW | 0x0 | Session Request + * [2] | RW | 0x0 | VBUS Valid Override Enable + * [3] | RW | 0x0 | VBUS Valid Override Value + * [4] | RW | 0x0 | A-Peripheral Session Valid Override Enable + * [5] | RW | 0x0 | A-Peripheral Session Valid OverrideValue + * [6] | RW | 0x0 | B-Peripheral Session Valid Override Enable + * [7] | RW | 0x0 | B-Peripheral Session Valid OverrideValue + * [8] | R | 0x0 | Host Negotiation Success + * [9] | RW | 0x0 | HNP Request + * [10] | RW | 0x0 | Host Set HNP Enable + * [11] | RW | 0x0 | Device HNP Enabled + * [15:12] | ??? | 0x0 | *UNDEFINED* + * [16] | R | 0x1 | Connector ID Status + * [17] | R | 0x0 | Long Short Debounce Time + * [18] | R | 0x0 | A-Session Valid + * [19] | R | 0x0 | B-Session Valid + * [20] | RW | 0x0 | OTG Version + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Session Request Success - sesreqscs + * + * This bit is set when a session request initiation is successful. This bit is + * valid only For Device Only configuration when OTG_MODE == 3 or OTG_MODE == 4. + * Applies for device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_FAIL | 0x0 | Session request failure + * ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_SUCCESS | 0x1 | Session request success + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQSCS + * + * Session request failure + */ +#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_FAIL 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQSCS + * + * Session request success + */ +#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_SUCCESS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_MSB 0 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_SESREQSCS field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Session Request - sesreq + * + * The application sets this bit to initiate a session request on the USB. The + * application can clear this bit by writing a 0 when the Host Negotiation Success + * Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is + * SET. The core clears this bit when the HstNegSucStsChng bit is cleared. If you + * use the USB 1.1 Full-Speed Serial Transceiver interface to initiate the session + * request, the application must wait until the VBUS discharges to 0.2 V, after the + * B-Session Valid bit in this register (GOTGCTL.BSesVld) is cleared. This + * discharge time varies between different PHYs and can be obtained from the PHY + * vendor. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------- + * ALT_USB_GLOB_GOTGCTL_SESREQ_E_NOREQUEST | 0x0 | No session request + * ALT_USB_GLOB_GOTGCTL_SESREQ_E_REQUEST | 0x1 | Session request + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQ + * + * No session request + */ +#define ALT_USB_GLOB_GOTGCTL_SESREQ_E_NOREQUEST 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQ + * + * Session request + */ +#define ALT_USB_GLOB_GOTGCTL_SESREQ_E_REQUEST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQ_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQ_MSB 1 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQ_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_SESREQ register field value. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQ_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_SESREQ register field value. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQ_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQ_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_SESREQ field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQ_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_GLOB_GOTGCTL_SESREQ register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_SESREQ_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : VBUS Valid Override Enable - vbvalidoven + * + * This bit is used to enable/disable the software to override the vbus-valid + * signal using the GOTGCTL.vbvalidOvVal.. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------------------ + * ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_DISD | 0x0 | Override is disabled and bvalid signal from the + * : | | respective PHY selected is used internally by + * : | | the force + * ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_END | 0x1 | The vbus-valid signal received from the PHY is + * : | | overridden with GOTGCTL.vbvalidOvVal + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN + * + * Override is disabled and bvalid signal from the respective PHY selected is used + * internally by the force + */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN + * + * The vbus-valid signal received from the PHY is overridden with + * GOTGCTL.vbvalidOvVal + */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_MSB 2 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : VBUS Valid Override Value - vbvalidovval + * + * This bit is used to set Override value for vbus valid signal when + * GOTGCTL.VbvalidOvEn is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------------------------- + * ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET0 | 0x0 | vbusvalid value when GOTGCTL.VbvalidOvEn = 1 + * ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET1 | 0x1 | vbusvalid value when GOTGCTL.VbvalidOvEn is 1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL + * + * vbusvalid value when GOTGCTL.VbvalidOvEn = 1 + */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET0 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL + * + * vbusvalid value when GOTGCTL.VbvalidOvEn is 1 + */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET1 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_MSB 3 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : A-Peripheral Session Valid Override Enable - avalidoven + * + * This bit is used to enable/disable the software to override the Avalid signal + * using the GOTGCTL.AvalidOvVal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_DISD | 0x0 | Override is disabled and Avalid signal from the + * : | | respective PHY is used internally by the core. + * ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_END | 0x1 | Internally Avalid received from the PHY is + * : | | overridden with GOTGCTL.AvalidOvVa + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVEN + * + * Override is disabled and Avalid signal from the respective PHY is used + * internally by the core. + */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVEN + * + * Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVa + */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_MSB 4 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : A-Peripheral Session Valid OverrideValue - avalidovval + * + * This bit is used to set Override value for Avalid signal when GOTGCTL.BvalidOvEn + * is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------------ + * ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE0 | 0x0 | Avalid value is 1'b0 when GOTGCTL.BvalidOvEn =1 + * ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE1 | 0x1 | Avalid value is 1'b1 when GOTGCTL.BvalidOvEn =1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL + * + * Avalid value is 1'b0 when GOTGCTL.BvalidOvEn =1 + */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE0 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL + * + * Avalid value is 1'b1 when GOTGCTL.BvalidOvEn =1 + */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE1 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_MSB 5 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : B-Peripheral Session Valid Override Enable - bvalidoven + * + * This bit is used to enable/disable the software to override the Bvalid signal + * using the GOTGCTL.BvalidOvVal. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_DISD | 0x0 | Override is disabled and bvalid signal from the + * : | | respective PHY selected is used internally by + * : | | the core + * ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_END | 0x1 | Internally Bvalid received from the PHY is + * : | | overridden with GOTGCTL.BvalidOvVal + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVEN + * + * Override is disabled and bvalid signal from the respective PHY selected is used + * internally by the core + */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVEN + * + * Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal + */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_MSB 6 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : B-Peripheral Session Valid OverrideValue - bvalidovval + * + * This bit is used to set Override value for Bvalid signalwhen GOTGCTL.BvalidOvEn + * is set. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------------------------- + * ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE0 | 0x0 | Bvalid value when GOTGCTL.AvalidOvEn =1 + * ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE1 | 0x1 | Bvalid value when GOTGCTL.AvalidOvEn =1 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL + * + * Bvalid value when GOTGCTL.AvalidOvEn =1 + */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE0 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL + * + * Bvalid value when GOTGCTL.AvalidOvEn =1 + */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE1 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_MSB 7 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Host Negotiation Success - hstnegscs + * + * Mode: Device only. Host Negotiation Success (HstNegScs) The core sets this bit + * when host negotiation is successful. The core clears this bit when the HNP + * Request (HNPReq) bit in this register is SET. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------- + * ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_FAIL | 0x0 | Host negotiation failure + * ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_SUCCESS | 0x1 | Host negotiation success + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTNEGSCS + * + * Host negotiation failure + */ +#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_FAIL 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTNEGSCS + * + * Host negotiation success + */ +#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_SUCCESS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */ +#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */ +#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_MSB 8 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */ +#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value. */ +#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value. */ +#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */ +#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : HNP Request - hnpreq + * + * Mode: Device only. The application sets this bit to initiate an HNP request to + * the connected USB host. The application can clear this bit by writing a 0 when + * the Host Negotiation Success Status Change bit in the OTG Interrupt register + * (GOTGINT.HstNegSucStsChng) is SET.The core clears this bit when the + * HstNegSucStsChng bit iscleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------- + * ALT_USB_GLOB_GOTGCTL_HNPREQ_E_DISD | 0x0 | No HNP request + * ALT_USB_GLOB_GOTGCTL_HNPREQ_E_END | 0x1 | HNP request + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HNPREQ + * + * No HNP request + */ +#define ALT_USB_GLOB_GOTGCTL_HNPREQ_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HNPREQ + * + * HNP request + */ +#define ALT_USB_GLOB_GOTGCTL_HNPREQ_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */ +#define ALT_USB_GLOB_GOTGCTL_HNPREQ_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */ +#define ALT_USB_GLOB_GOTGCTL_HNPREQ_MSB 9 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */ +#define ALT_USB_GLOB_GOTGCTL_HNPREQ_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_HNPREQ register field value. */ +#define ALT_USB_GLOB_GOTGCTL_HNPREQ_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HNPREQ register field value. */ +#define ALT_USB_GLOB_GOTGCTL_HNPREQ_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */ +#define ALT_USB_GLOB_GOTGCTL_HNPREQ_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_HNPREQ field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_HNPREQ_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_GLOB_GOTGCTL_HNPREQ register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_HNPREQ_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Host Set HNP Enable - hstsethnpen + * + * Mode: Host only. The application sets this bit when it has successfully enabled + * HNP (using the SetFeature.SetHNPEnable command) on the connected device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------- + * ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_DISD | 0x0 | Host Set HNP is not enabled + * ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_END | 0x1 | Host Set HNP is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN + * + * Host Set HNP is not enabled + */ +#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN + * + * Host Set HNP is enabled + */ +#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_MSB 10 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value. */ +#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value. */ +#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Device HNP Enabled - devhnpen + * + * Mode: Device only. The application sets this bit when it successfully receives a + * SetFeature.SetHNPEnable command from the connected USB host. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------------------------- + * ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_DISD | 0x0 | HNP is not enabled in the application + * ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_END | 0x1 | HNP Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DEVHNPEN + * + * HNP is not enabled in the application + */ +#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DEVHNPEN + * + * HNP Enabled + */ +#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_MSB 11 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value. */ +#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value. */ +#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */ +#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_DEVHNPEN field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Connector ID Status - conidsts + * + * Mode: Host and Device. Indicates the connector ID status on a connect event.This + * bit is valid only for Host and Device mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------- + * ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODA | 0x0 | The DWC_otg core is in A-Device mode + * ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODB | 0x1 | The otg core is in B-Device mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_CONIDSTS + * + * The DWC_otg core is in A-Device mode + */ +#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODA 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_CONIDSTS + * + * The otg core is in B-Device mode + */ +#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODB 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */ +#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */ +#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_MSB 16 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */ +#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value. */ +#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value. */ +#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */ +#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GOTGCTL_CONIDSTS field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Long Short Debounce Time - dbnctime + * + * Mode: Host only. Indicates the debounce time of a detected connection. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_LONG | 0x0 | Long debounce time, used FOR physical + * : | | connections (100 ms + 2.5 s) + * ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_SHORT | 0x1 | Short debounce time, used FOR soft connections + * : | | (2.5 s + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DBNCTIME + * + * Long debounce time, used FOR physical connections (100 ms + 2.5 s) + */ +#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_LONG 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DBNCTIME + * + * Short debounce time, used FOR soft connections (2.5 s + */ +#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_SHORT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */ +#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */ +#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_MSB 17 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */ +#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value. */ +#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value. */ +#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */ +#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_DBNCTIME field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : A-Session Valid - asesvld + * + * Mode: Host only. Indicates the Host mode transceiver status. If you do not + * enabled OTG features (such as SRP and HNP), the read reset value will be 1.The + * vbus assigns the values internally for non-SRP or non-HNP configurations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------- + * ALT_USB_GLOB_GOTGCTL_ASESVLD_E_VALID | 0x0 | A-session is not valid + * ALT_USB_GLOB_GOTGCTL_ASESVLD_E_NOTVALID | 0x1 | A-session is valid + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_ASESVLD + * + * A-session is not valid + */ +#define ALT_USB_GLOB_GOTGCTL_ASESVLD_E_VALID 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_ASESVLD + * + * A-session is valid + */ +#define ALT_USB_GLOB_GOTGCTL_ASESVLD_E_NOTVALID 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */ +#define ALT_USB_GLOB_GOTGCTL_ASESVLD_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */ +#define ALT_USB_GLOB_GOTGCTL_ASESVLD_MSB 18 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */ +#define ALT_USB_GLOB_GOTGCTL_ASESVLD_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_ASESVLD register field value. */ +#define ALT_USB_GLOB_GOTGCTL_ASESVLD_SET_MSK 0x00040000 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_ASESVLD register field value. */ +#define ALT_USB_GLOB_GOTGCTL_ASESVLD_CLR_MSK 0xfffbffff +/* The reset value of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */ +#define ALT_USB_GLOB_GOTGCTL_ASESVLD_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_ASESVLD field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_ASESVLD_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_USB_GLOB_GOTGCTL_ASESVLD register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_ASESVLD_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : B-Session Valid - bsesvld + * + * Mode: Device only. Indicates the Device mode transceiver status. In OTG mode, + * you can use this bit to determine IF the device is connected or disconnected. If + * you do not enable OTG features (such as SRP and HNP), the read reset value will + * be 1. The vbus assigns the values internally for non-SRP or non-HNP + * configurations. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------- + * ALT_USB_GLOB_GOTGCTL_BSESVLD_E_NOTVALID | 0x0 | B-session is not valid + * ALT_USB_GLOB_GOTGCTL_BSESVLD_E_VALID | 0x1 | B-session is valid + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BSESVLD + * + * B-session is not valid + */ +#define ALT_USB_GLOB_GOTGCTL_BSESVLD_E_NOTVALID 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BSESVLD + * + * B-session is valid + */ +#define ALT_USB_GLOB_GOTGCTL_BSESVLD_E_VALID 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */ +#define ALT_USB_GLOB_GOTGCTL_BSESVLD_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */ +#define ALT_USB_GLOB_GOTGCTL_BSESVLD_MSB 19 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */ +#define ALT_USB_GLOB_GOTGCTL_BSESVLD_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_BSESVLD register field value. */ +#define ALT_USB_GLOB_GOTGCTL_BSESVLD_SET_MSK 0x00080000 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BSESVLD register field value. */ +#define ALT_USB_GLOB_GOTGCTL_BSESVLD_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */ +#define ALT_USB_GLOB_GOTGCTL_BSESVLD_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_BSESVLD field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_BSESVLD_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_USB_GLOB_GOTGCTL_BSESVLD register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_BSESVLD_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : OTG Version - otgver + * + * Indicates the OTG revision. In OTG Version 1.3. the core supports Data line + * pulsing and VBus pulsing for SRP. In OTG Version 2.0 the core supports only Data + * line pulsing for SRP. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------ + * ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER13 | 0x0 | OTG Version 1.3. In this version the core + * : | | supports Data line + * ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER20 | 0x1 | OTG Version 2.0. In this version the core + * : | | supports only Data line pulsing for SRP + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_OTGVER + * + * OTG Version 1.3. In this version the core supports Data line + */ +#define ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER13 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_OTGVER + * + * OTG Version 2.0. In this version the core supports only Data line pulsing for + * SRP + */ +#define ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER20 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */ +#define ALT_USB_GLOB_GOTGCTL_OTGVER_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */ +#define ALT_USB_GLOB_GOTGCTL_OTGVER_MSB 20 +/* The width in bits of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */ +#define ALT_USB_GLOB_GOTGCTL_OTGVER_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGCTL_OTGVER register field value. */ +#define ALT_USB_GLOB_GOTGCTL_OTGVER_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_OTGVER register field value. */ +#define ALT_USB_GLOB_GOTGCTL_OTGVER_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */ +#define ALT_USB_GLOB_GOTGCTL_OTGVER_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGCTL_OTGVER field value from a register. */ +#define ALT_USB_GLOB_GOTGCTL_OTGVER_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_GLOB_GOTGCTL_OTGVER register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGCTL_OTGVER_SET(value) (((value) << 20) & 0x00100000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GOTGCTL. + */ +struct ALT_USB_GLOB_GOTGCTL_s +{ + const uint32_t sesreqscs : 1; /* Session Request Success */ + uint32_t sesreq : 1; /* Session Request */ + uint32_t vbvalidoven : 1; /* VBUS Valid Override Enable */ + uint32_t vbvalidovval : 1; /* VBUS Valid Override Value */ + uint32_t avalidoven : 1; /* A-Peripheral Session Valid Override Enable */ + uint32_t avalidovval : 1; /* A-Peripheral Session Valid OverrideValue */ + uint32_t bvalidoven : 1; /* B-Peripheral Session Valid Override Enable */ + uint32_t bvalidovval : 1; /* B-Peripheral Session Valid OverrideValue */ + const uint32_t hstnegscs : 1; /* Host Negotiation Success */ + uint32_t hnpreq : 1; /* HNP Request */ + uint32_t hstsethnpen : 1; /* Host Set HNP Enable */ + uint32_t devhnpen : 1; /* Device HNP Enabled */ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t conidsts : 1; /* Connector ID Status */ + const uint32_t dbnctime : 1; /* Long Short Debounce Time */ + const uint32_t asesvld : 1; /* A-Session Valid */ + const uint32_t bsesvld : 1; /* B-Session Valid */ + uint32_t otgver : 1; /* OTG Version */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GOTGCTL. */ +typedef volatile struct ALT_USB_GLOB_GOTGCTL_s ALT_USB_GLOB_GOTGCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GOTGCTL register from the beginning of the component. */ +#define ALT_USB_GLOB_GOTGCTL_OFST 0x0 +/* The address of the ALT_USB_GLOB_GOTGCTL register. */ +#define ALT_USB_GLOB_GOTGCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GOTGCTL_OFST)) + +/* + * Register : OTG Interrupt Register - gotgint + * + * The application reads this register whenever there is an OTG interrupt and + * clears the bits in this register to clear the OTG interrupt. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [1:0] | ??? | 0x0 | *UNDEFINED* + * [2] | R | 0x0 | Session End Detected + * [7:3] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | Session Request Success Status Change + * [9] | R | 0x0 | Host Negotiation Success Status Change + * [16:10] | ??? | 0x0 | *UNDEFINED* + * [17] | R | 0x0 | Host Negotiation Detected + * [18] | R | 0x0 | A-Device Timeout Change + * [19] | R | 0x0 | Debounce Done + * [31:20] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Session End Detected - sesenddet + * + * Mode:Host and Device.This bit can be set only by the core and the application + * should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------------------------------- + * ALT_USB_GLOB_GOTGINT_SESENDDET_E_INACT | 0x0 | Non Active State + * ALT_USB_GLOB_GOTGINT_SESENDDET_E_ACT | 0x1 | Set when utmisrp_bvalid signal is deasserted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESENDDET + * + * Non Active State + */ +#define ALT_USB_GLOB_GOTGINT_SESENDDET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESENDDET + * + * Set when utmisrp_bvalid signal is deasserted + */ +#define ALT_USB_GLOB_GOTGINT_SESENDDET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */ +#define ALT_USB_GLOB_GOTGINT_SESENDDET_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */ +#define ALT_USB_GLOB_GOTGINT_SESENDDET_MSB 2 +/* The width in bits of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */ +#define ALT_USB_GLOB_GOTGINT_SESENDDET_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGINT_SESENDDET register field value. */ +#define ALT_USB_GLOB_GOTGINT_SESENDDET_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_GLOB_GOTGINT_SESENDDET register field value. */ +#define ALT_USB_GLOB_GOTGINT_SESENDDET_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */ +#define ALT_USB_GLOB_GOTGINT_SESENDDET_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGINT_SESENDDET field value from a register. */ +#define ALT_USB_GLOB_GOTGINT_SESENDDET_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_GLOB_GOTGINT_SESENDDET register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGINT_SESENDDET_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Session Request Success Status Change - sesreqsucstschng + * + * Mode: Host and Device. The core sets this bit on the success or failure of a + * session request. The application must read the Session Request Success bit in + * the OTG Control and Status register (GOTGCTL.SesReqScs) to check for success or + * failure. This bit can be set only by the core and the application should write 1 + * to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:----------------------- + * ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_INACT | 0x0 | No change + * ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_ACT | 0x1 | Session Request Status + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG + * + * No change + */ +#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG + * + * Session Request Status + */ +#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */ +#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */ +#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_MSB 8 +/* The width in bits of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */ +#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value. */ +#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value. */ +#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */ +#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG field value from a register. */ +#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Host Negotiation Success Status Change - hstnegsucstschng + * + * Mode: Host and Device. The core sets this bit on the success or failure of a USB + * host negotiation request. The application must read the Host Negotiation Success + * bit of the OTG Control and Status register (GOTGCTL.HstNegScs) to check for + * success or failure. This bit can be set only by the core and the application + * should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------- + * ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_INACT | 0x0 | No Change + * ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_ACT | 0x1 | Host Negotiation Status Change + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG + * + * No Change + */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG + * + * Host Negotiation Status Change + */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_MSB 9 +/* The width in bits of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG field value from a register. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Host Negotiation Detected - hstnegdet + * + * Mode:Host and Device. The core sets this bit when it detects a host negotiation + * request on the USB. This bit can be set only by the core and the application + * should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------- + * ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_INACT | 0x0 | No Change + * ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_ACT | 0x1 | Host Negotiation Detected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGDET + * + * No Change + */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGDET + * + * Host Negotiation Detected + */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_MSB 17 +/* The width in bits of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGINT_HSTNEGDET field value from a register. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : A-Device Timeout Change - adevtoutchg + * + * Mode:Host and Device. The core sets this bit to indicate that the A-device has + * timed out WHILE waiting FOR the B-device to connect. This bit can be set only by + * the core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------- + * ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_INACT | 0x0 | No Change + * ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_ACT | 0x1 | A-Device Timeout + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG + * + * No Change + */ +#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG + * + * A-Device Timeout + */ +#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */ +#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */ +#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_MSB 18 +/* The width in bits of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */ +#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value. */ +#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_SET_MSK 0x00040000 +/* The mask used to clear the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value. */ +#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_CLR_MSK 0xfffbffff +/* The reset value of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */ +#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG field value from a register. */ +#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Debounce Done - dbncedone + * + * Mode: Host only. The core sets this bit when the debounce is completed after the + * device connect. The application can start driving USB reset after seeing this + * interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is SET + * in the Core USB Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, + * respectively). This bit can be set only by the core and the application should + * write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------- + * ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_INACT | 0x0 | No Change + * ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_ACT | 0x1 | Debounce completed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_DBNCEDONE + * + * No Change + */ +#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GOTGINT_DBNCEDONE + * + * Debounce completed + */ +#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */ +#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */ +#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_MSB 19 +/* The width in bits of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */ +#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value. */ +#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_SET_MSK 0x00080000 +/* The mask used to clear the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value. */ +#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */ +#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GOTGINT_DBNCEDONE field value from a register. */ +#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_SET(value) (((value) << 19) & 0x00080000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GOTGINT. + */ +struct ALT_USB_GLOB_GOTGINT_s +{ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t sesenddet : 1; /* Session End Detected */ + uint32_t : 5; /* *UNDEFINED* */ + const uint32_t sesreqsucstschng : 1; /* Session Request Success Status Change */ + const uint32_t hstnegsucstschng : 1; /* Host Negotiation Success Status Change */ + uint32_t : 7; /* *UNDEFINED* */ + const uint32_t hstnegdet : 1; /* Host Negotiation Detected */ + const uint32_t adevtoutchg : 1; /* A-Device Timeout Change */ + const uint32_t dbncedone : 1; /* Debounce Done */ + uint32_t : 12; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GOTGINT. */ +typedef volatile struct ALT_USB_GLOB_GOTGINT_s ALT_USB_GLOB_GOTGINT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GOTGINT register from the beginning of the component. */ +#define ALT_USB_GLOB_GOTGINT_OFST 0x4 +/* The address of the ALT_USB_GLOB_GOTGINT register. */ +#define ALT_USB_GLOB_GOTGINT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GOTGINT_OFST)) + +/* + * Register : AHB Configuration Register - gahbcfg + * + * This register can be used to configure the core after power-on or a change in + * mode. This register mainly contains AHB system-related configuration parameters. + * Do not change this register after the initial programming. The application must + * program this register before starting any transactions on either the AHB or the + * USB. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Global Interrupt Mask + * [4:1] | RW | 0x0 | Burst Length Type + * [5] | RW | 0x0 | DMA Enable + * [6] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | Non-Periodic TxFIFO Empty Level + * [8] | RW | 0x0 | Periodic TxFIFO Empty Leve + * [20:9] | ??? | 0x0 | *UNDEFINED* + * [21] | RW | 0x0 | Remote Memory Support + * [22] | RW | 0x0 | Notify All Dma Write Transactions + * [31:23] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Global Interrupt Mask - glblintrmsk + * + * Mode: Host and device. The application uses this bit to mask or unmask the + * interrupt line assertion to itself. Irrespective of this bits setting, the + * interrupt status registers are updated by the core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------------ + * ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_MSK | 0x0 | Mask the interrupt assertion to the application + * ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_NOMSK | 0x1 | Unmask the interrupt assertion to the + * : | | application. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK + * + * Mask the interrupt assertion to the application + */ +#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK + * + * Unmask the interrupt assertion to the application. + */ +#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */ +#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */ +#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_MSB 0 +/* The width in bits of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */ +#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value. */ +#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value. */ +#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */ +#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK field value from a register. */ +#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Burst Length Type - hbstlen + * + * Mode:Host and device. This field is used in Internal DMA modes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:------------------- + * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD1ORSINGLE | 0x0 | 1 word or single + * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD4ORINCR | 0x1 | 4 word or incr + * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD8 | 0x2 | 8 word + * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD16ORINCR4 | 0x3 | 16 word or incr4 + * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD32 | 0x4 | 32 word + * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD64ORINCR8 | 0x5 | 64 word or incr8 + * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD128 | 0x6 | 128 word + * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD256ORINCR16 | 0x7 | 256 word or incr16 + * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORDX | 0x8 | Others reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN + * + * 1 word or single + */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD1ORSINGLE 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN + * + * 4 word or incr + */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD4ORINCR 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN + * + * 8 word + */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD8 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN + * + * 16 word or incr4 + */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD16ORINCR4 0x3 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN + * + * 32 word + */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD32 0x4 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN + * + * 64 word or incr8 + */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD64ORINCR8 0x5 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN + * + * 128 word + */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD128 0x6 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN + * + * 256 word or incr16 + */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD256ORINCR16 0x7 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN + * + * Others reserved + */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORDX 0x8 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_MSB 4 +/* The width in bits of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value. */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_SET_MSK 0x0000001e +/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value. */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_CLR_MSK 0xffffffe1 +/* The reset value of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GAHBCFG_HBSTLEN field value from a register. */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_GET(value) (((value) & 0x0000001e) >> 1) +/* Produces a ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_SET(value) (((value) << 1) & 0x0000001e) + +/* + * Field : DMA Enable - dmaen + * + * Mode:Host and device. Enables switching from DMA mode to slave mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_GLOB_GAHBCFG_DMAEN_E_SLVMOD | 0x0 | Core operates in Slave mode + * ALT_USB_GLOB_GAHBCFG_DMAEN_E_DMAMOD | 0x1 | Core operates in a DMA mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_DMAEN + * + * Core operates in Slave mode + */ +#define ALT_USB_GLOB_GAHBCFG_DMAEN_E_SLVMOD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_DMAEN + * + * Core operates in a DMA mode + */ +#define ALT_USB_GLOB_GAHBCFG_DMAEN_E_DMAMOD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */ +#define ALT_USB_GLOB_GAHBCFG_DMAEN_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */ +#define ALT_USB_GLOB_GAHBCFG_DMAEN_MSB 5 +/* The width in bits of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */ +#define ALT_USB_GLOB_GAHBCFG_DMAEN_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GAHBCFG_DMAEN register field value. */ +#define ALT_USB_GLOB_GAHBCFG_DMAEN_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_DMAEN register field value. */ +#define ALT_USB_GLOB_GAHBCFG_DMAEN_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */ +#define ALT_USB_GLOB_GAHBCFG_DMAEN_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GAHBCFG_DMAEN field value from a register. */ +#define ALT_USB_GLOB_GAHBCFG_DMAEN_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_GLOB_GAHBCFG_DMAEN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GAHBCFG_DMAEN_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Non-Periodic TxFIFO Empty Level - nptxfemplvl + * + * Mode:Host and device. This bit is used only in Slave mode. In host mode and with + * Shared FIFO with device mode, this bit indicates when the Non-Periodic TxFIFO + * Empty Interrupt bit in the Core Interrupt register (GINTSTS.NPTxFEmp) is + * triggered. With dedicated FIFO in device mode, this bit indicates when IN + * endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is triggered. Host mode + * and with Shared FIFO with device mode: + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------------- + * ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_HALFEMPTY | 0x0 | DIEPINTn.TxFEmp interrupt indicates that the IN + * : | | Endpoint TxFIFO is half empty or DIEPINTn.TxFEmp + * : | | interrupt indicates that the IN Endpoint TxFIFO + * : | | is half empty + * ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_EMPTY | 0x1 | GINTSTS.NPTxFEmp interrupt indicates that the + * : | | Non-Periodic TxFIFO is completely empty or + * : | | DIEPINTn.TxFEmp interrupt indicates that the IN + * : | | Endpoint TxFIFO is completely empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL + * + * DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty or + * DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty + */ +#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_HALFEMPTY 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL + * + * GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely + * empty or DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is + * completely empty + */ +#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */ +#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */ +#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_MSB 7 +/* The width in bits of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */ +#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value. */ +#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value. */ +#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */ +#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL field value from a register. */ +#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Periodic TxFIFO Empty Leve - ptxfemplvl + * + * Mode:Host only. Indicates when the Periodic TxFIFO Empty Interrupt bit in the + * Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This bit is used only in + * Slave mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------------- + * ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_HALFEMPTY | 0x0 | GINTSTS.PTxFEmp interrupt indicates that the + * : | | Periodic TxFIFO is half empty + * ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_EMPTY | 0x1 | GINTSTS.PTxFEmp interrupt indicates that the + * : | | Periodic TxFIFO is completely empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL + * + * GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty + */ +#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_HALFEMPTY 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL + * + * GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty + */ +#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_EMPTY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */ +#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */ +#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_MSB 8 +/* The width in bits of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */ +#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value. */ +#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value. */ +#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */ +#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL field value from a register. */ +#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Remote Memory Support - remmemsupp + * + * This bit is programmed to enable/disable the functionality to wait for the + * system DMA Done Signal for the DMA Write Transfers. + * + * * The int_dma_req output signal is asserted when HSOTG DMA starts write transfer + * to the external memory. When the core is done with the Transfers it asserts + * int_dma_done signal to flag the completion of DMA writes from HSOTG. The core + * then waits for sys_dma_done signal from the system to proceed further and + * complete the Data Transfer corresponding to a particular Channel/Endpoint. + * + * * The int_dma_req and int_dma_done signals are not asserted and the core + * proceeds with the assertion of the XferComp interrupt as soon as wait for the + * system DMA Done Signal for the DMA Write Transfers the DMA write transfer is + * done at the HSOTG Core Boundary and it doesn't wait for the sys_dma_done + * signal to complete the DATA + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------------------------- + * ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_DISD | 0x0 | Disable wait for system DMA Done Signal + * ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_END | 0x1 | Enable wait for the system DMA Done Signal for + * : | | the DMA Write Transfers + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_REMMEMSUPP + * + * Disable wait for system DMA Done Signal + */ +#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_REMMEMSUPP + * + * Enable wait for the system DMA Done Signal for the DMA Write Transfers + */ +#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */ +#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */ +#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_MSB 21 +/* The width in bits of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */ +#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value. */ +#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value. */ +#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */ +#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP field value from a register. */ +#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Notify All Dma Write Transactions - notialldmawrit + * + * This bit is programmed to enable the System DMA Done functionality for all the + * DMA write Transactions corresponding to the Channel/Endpoint. This bit is valid + * only when GAHBCFG.RemMemSupp is set to 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------------|:------|:------------------------------------------------- + * ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_ALLTRANS | 0x1 | HSOTG core asserts int_dma_req for all the DMA + * : | | write transactions on the AHB interface along + * : | | with int_dma_done, chep_last_transact and + * : | | chep_number signal informations. The core waits + * : | | for sys_dma_done signal for all the DMA write + * : | | transactions in order to complete the transfer + * : | | of a particular Channel/Endpoint + * ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_LASTTRANS | 0x0 | HSOTG core asserts int_dma_req signal only for + * : | | the last transaction of DMA write transfer + * : | | corresponding to a particular Channel/Endpoint. + * : | | Similarly, the core waits for sys_dma_done + * : | | signal only for that transaction of DMA write to + * : | | complete the transfer of a particular + * : | | Channel/Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT + * + * HSOTG core asserts int_dma_req for all the DMA write transactions on the AHB + * interface along with int_dma_done, chep_last_transact and chep_number signal + * informations. The core waits for sys_dma_done signal for all the DMA write + * transactions in order to complete the transfer of a particular Channel/Endpoint + */ +#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_ALLTRANS 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT + * + * HSOTG core asserts int_dma_req signal only for the last transaction of DMA write + * transfer corresponding to a particular Channel/Endpoint. Similarly, the core + * waits for sys_dma_done signal only for that transaction of DMA write to complete + * the transfer of a particular Channel/Endpoint + */ +#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_LASTTRANS 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */ +#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */ +#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_MSB 22 +/* The width in bits of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */ +#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value. */ +#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_SET_MSK 0x00400000 +/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value. */ +#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_CLR_MSK 0xffbfffff +/* The reset value of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */ +#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT field value from a register. */ +#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_SET(value) (((value) << 22) & 0x00400000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GAHBCFG. + */ +struct ALT_USB_GLOB_GAHBCFG_s +{ + uint32_t glblintrmsk : 1; /* Global Interrupt Mask */ + uint32_t hbstlen : 4; /* Burst Length Type */ + uint32_t dmaen : 1; /* DMA Enable */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t nptxfemplvl : 1; /* Non-Periodic TxFIFO Empty Level */ + uint32_t ptxfemplvl : 1; /* Periodic TxFIFO Empty Leve */ + uint32_t : 12; /* *UNDEFINED* */ + uint32_t remmemsupp : 1; /* Remote Memory Support */ + uint32_t notialldmawrit : 1; /* Notify All Dma Write Transactions */ + uint32_t : 9; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GAHBCFG. */ +typedef volatile struct ALT_USB_GLOB_GAHBCFG_s ALT_USB_GLOB_GAHBCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GAHBCFG register from the beginning of the component. */ +#define ALT_USB_GLOB_GAHBCFG_OFST 0x8 +/* The address of the ALT_USB_GLOB_GAHBCFG register. */ +#define ALT_USB_GLOB_GAHBCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GAHBCFG_OFST)) + +/* + * Register : USB Configuration Registe - gusbcfg + * + * This register can be used to configure the core after power-on or a changing to + * Host mode or Device mode. It contains USB and USB-PHY related configuration + * parameters. The application must program this register before starting any + * transactions on either the AHB or the USB. Do not make changes to this register + * after the initial programming. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------- + * [2:0] | RW | 0x0 | HS FS Timeout Calibration + * [3] | R | 0x0 | PHY Interfac + * [4] | R | 0x1 | ULPI Select + * [5] | R | 0x0 | Full-Speed Serial Interface Select + * [6] | R | 0x0 | USB 2.0 High-Speed PHY + * [7] | RW | 0x0 | ULPI DDR Select + * [8] | RW | 0x0 | SRP-Capable + * [9] | RW | 0x0 | HNP-Capable + * [13:10] | RW | 0x5 | USB Turnaround Time + * [17:14] | ??? | 0x0 | *UNDEFINED* + * [18] | RW | 0x0 | ULPI Auto Resume + * [19] | RW | 0x0 | ULPI Clock SuspendM + * [20] | RW | 0x0 | ULPI External VBUS Drive + * [21] | RW | 0x0 | ULPI External VBUS Indicato + * [22] | RW | 0x0 | TermSel DLine Pulsing Selection + * [23] | RW | 0x0 | Indicator Complement + * [24] | RW | 0x0 | Indicator Pass Throug + * [25] | RW | 0x0 | ULPI Interface Protect Disable + * [27:26] | ??? | 0x0 | *UNDEFINED* + * [28] | RW | 0x0 | Tx End Delay + * [29] | RW | 0x0 | Force Host Mode. + * [30] | RW | 0x0 | Force Device Mode + * [31] | W | 0x0 | Corrupt Tx packet + * + */ +/* + * Field : HS FS Timeout Calibration - toutcal + * + * Mode:Host and Device. The number of PHY clocks that the application programs in + * this field is added to the high-speed/full-speed interpacket timeout duration in + * the core to account for any additional delays introduced by the PHY. This can be + * required, because the delay introduced by the PHY in generating the linestate + * condition can vary from one PHY to another. The USB standard timeout value for + * high-speed operation is 736 to 816 (inclusive) bit times. The USB standard + * timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The + * application must program this field based on the speed of enumeration. The + * number of bit times added per PHY clock are: High-speed operation: + * + * * One 30-MHz PHY clock = 16 bit times + * + * * One 60-MHz PHY clock = 8 bit times + * + * Full-speed operation: + * + * * One 30-MHz PHY clock = 0.4 bit times + * + * * One 60-MHz PHY clock = 0.2 bit times + * + * * One 48-MHz PHY clock = 0.25 bit times + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */ +#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */ +#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_MSB 2 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */ +#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_WIDTH 3 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value. */ +#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_SET_MSK 0x00000007 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value. */ +#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */ +#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_TOUTCAL field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : PHY Interfac - phyif + * + * Mode:Host and Device. This application uses a ULPI interface only. Hence only + * 8-bit setting is relevant. This setting should not matter since UTMI is not + * enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------- + * ALT_USB_GLOB_GUSBCFG_PHYIF_E_BITS8 | 0x0 | PHY 8bit Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_PHYIF + * + * PHY 8bit Mode + */ +#define ALT_USB_GLOB_GUSBCFG_PHYIF_E_BITS8 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */ +#define ALT_USB_GLOB_GUSBCFG_PHYIF_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */ +#define ALT_USB_GLOB_GUSBCFG_PHYIF_MSB 3 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */ +#define ALT_USB_GLOB_GUSBCFG_PHYIF_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_PHYIF register field value. */ +#define ALT_USB_GLOB_GUSBCFG_PHYIF_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_PHYIF register field value. */ +#define ALT_USB_GLOB_GUSBCFG_PHYIF_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */ +#define ALT_USB_GLOB_GUSBCFG_PHYIF_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_PHYIF field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_PHYIF_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_GLOB_GUSBCFG_PHYIF register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_PHYIF_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : ULPI Select - ulpi_utmi_sel + * + * Mode:Host and Device. The application uses ULPI Only in 8bit mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_E_ULPI | 0x0 | ULPI PHY + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL + * + * ULPI PHY + */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_E_ULPI 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_MSB 4 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Full-Speed Serial Interface Select - fsintf + * + * Mode:Host and Device. The application can Set this bit to select between the 3- + * and 6-pin interfaces, and access is Read and Write. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------- + * ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS6PIN | 0x0 | 6-pin unidirectional full-speed serial interface + * ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS3PIN | 0x1 | 3-pin bidirectional full-speed serial interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FSINTF + * + * 6-pin unidirectional full-speed serial interface + */ +#define ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS6PIN 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FSINTF + * + * 3-pin bidirectional full-speed serial interface + */ +#define ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS3PIN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */ +#define ALT_USB_GLOB_GUSBCFG_FSINTF_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */ +#define ALT_USB_GLOB_GUSBCFG_FSINTF_MSB 5 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */ +#define ALT_USB_GLOB_GUSBCFG_FSINTF_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_FSINTF register field value. */ +#define ALT_USB_GLOB_GUSBCFG_FSINTF_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FSINTF register field value. */ +#define ALT_USB_GLOB_GUSBCFG_FSINTF_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */ +#define ALT_USB_GLOB_GUSBCFG_FSINTF_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_FSINTF field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_FSINTF_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_GLOB_GUSBCFG_FSINTF register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_FSINTF_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : USB 2.0 High-Speed PHY - physel + * + * Mode:Host and Device. The application uses USB 2.0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------ + * ALT_USB_GLOB_GUSBCFG_PHYSEL_E_USB20 | 0x0 | USB 2.0 high-speed ULPI + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_PHYSEL + * + * USB 2.0 high-speed ULPI + */ +#define ALT_USB_GLOB_GUSBCFG_PHYSEL_E_USB20 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_PHYSEL_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_PHYSEL_MSB 6 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_PHYSEL_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_PHYSEL register field value. */ +#define ALT_USB_GLOB_GUSBCFG_PHYSEL_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_PHYSEL register field value. */ +#define ALT_USB_GLOB_GUSBCFG_PHYSEL_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_PHYSEL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_PHYSEL field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_PHYSEL_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_GLOB_GUSBCFG_PHYSEL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_PHYSEL_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : ULPI DDR Select - ddrsel + * + * Mode:Host and Device. The application uses this bit to select a Single Data Rate + * (SDR) or Double Data Rate (DDR) or ULPI interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------------------- + * ALT_USB_GLOB_GUSBCFG_DDRSEL_E_SDR | 0x0 | Single Data Rate ULPI Interfacewith 8-bit-wide + * : | | data bus + * ALT_USB_GLOB_GUSBCFG_DDRSEL_E_DDR | 0x1 | Double Data Rate ULPI Interface, with 4-bit-wide + * : | | data bus + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_DDRSEL + * + * Single Data Rate ULPI Interfacewith 8-bit-wide data bus + */ +#define ALT_USB_GLOB_GUSBCFG_DDRSEL_E_SDR 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_DDRSEL + * + * Double Data Rate ULPI Interface, with 4-bit-wide data bus + */ +#define ALT_USB_GLOB_GUSBCFG_DDRSEL_E_DDR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_DDRSEL_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_DDRSEL_MSB 7 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_DDRSEL_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_DDRSEL register field value. */ +#define ALT_USB_GLOB_GUSBCFG_DDRSEL_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_DDRSEL register field value. */ +#define ALT_USB_GLOB_GUSBCFG_DDRSEL_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */ +#define ALT_USB_GLOB_GUSBCFG_DDRSEL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_DDRSEL field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_DDRSEL_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_GLOB_GUSBCFG_DDRSEL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_DDRSEL_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : SRP-Capable - srpcap + * + * Mode:Host and Device. The application uses this bit to control the otg core SRP + * capabilities. If the core operates as a non-SRP-capable B-device, it cannot + * request the connected A-device (host) to activate VBUS and start a session. This + * bit is writable only If an SRP mode was specified for Mode of Operation in + * coreConsultant (parameter OTG_MODE). Otherwise, reads Return 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------ + * ALT_USB_GLOB_GUSBCFG_SRPCAP_E_DISD | 0x0 | SRP capability is not enabled + * ALT_USB_GLOB_GUSBCFG_SRPCAP_E_END | 0x1 | SRP capability is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_SRPCAP + * + * SRP capability is not enabled + */ +#define ALT_USB_GLOB_GUSBCFG_SRPCAP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_SRPCAP + * + * SRP capability is enabled + */ +#define ALT_USB_GLOB_GUSBCFG_SRPCAP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */ +#define ALT_USB_GLOB_GUSBCFG_SRPCAP_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */ +#define ALT_USB_GLOB_GUSBCFG_SRPCAP_MSB 8 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */ +#define ALT_USB_GLOB_GUSBCFG_SRPCAP_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_SRPCAP register field value. */ +#define ALT_USB_GLOB_GUSBCFG_SRPCAP_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_SRPCAP register field value. */ +#define ALT_USB_GLOB_GUSBCFG_SRPCAP_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */ +#define ALT_USB_GLOB_GUSBCFG_SRPCAP_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_SRPCAP field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_SRPCAP_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_GLOB_GUSBCFG_SRPCAP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_SRPCAP_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : HNP-Capable - hnpcap + * + * Mode:Host and Device. The application uses this bit to control the otg core's + * HNP capabilities. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------- + * ALT_USB_GLOB_GUSBCFG_HNPCAP_E_DISD | 0x0 | HNP capability is not enabled. + * ALT_USB_GLOB_GUSBCFG_HNPCAP_E_END | 0x1 | HNP capability is enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_HNPCAP + * + * HNP capability is not enabled. + */ +#define ALT_USB_GLOB_GUSBCFG_HNPCAP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_HNPCAP + * + * HNP capability is enabled + */ +#define ALT_USB_GLOB_GUSBCFG_HNPCAP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */ +#define ALT_USB_GLOB_GUSBCFG_HNPCAP_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */ +#define ALT_USB_GLOB_GUSBCFG_HNPCAP_MSB 9 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */ +#define ALT_USB_GLOB_GUSBCFG_HNPCAP_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_HNPCAP register field value. */ +#define ALT_USB_GLOB_GUSBCFG_HNPCAP_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_HNPCAP register field value. */ +#define ALT_USB_GLOB_GUSBCFG_HNPCAP_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */ +#define ALT_USB_GLOB_GUSBCFG_HNPCAP_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_HNPCAP field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_HNPCAP_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_GLOB_GUSBCFG_HNPCAP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_HNPCAP_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : USB Turnaround Time - usbtrdtim + * + * Mode: Device only. Sets the turnaround time in PHY clocks. Specifies the + * response time for a MAC request to the Packet FIFO Controller (PFC) to fetch + * data from the DFIFO (SPRAM). + * + * The value is calculated for the minimum AHB frequency of 30 MHz. USB turnaround + * time is critical for certification where long cables and 5-Hubs are used, so If + * you need the AHB to run at less than 30 MHz, and If USB turnaround time is not + * critical, these bits can be programmed to a larger value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------ + * ALT_USB_GLOB_GUSBCFG_USBTRDTIM_E_TURNTIME | 0x9 | MAC interface is 8-bit UTMI+. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_USBTRDTIM + * + * MAC interface is 8-bit UTMI+. + */ +#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_E_TURNTIME 0x9 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */ +#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */ +#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_MSB 13 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */ +#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value. */ +#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_SET_MSK 0x00003c00 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value. */ +#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_CLR_MSK 0xffffc3ff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */ +#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_RESET 0x5 +/* Extracts the ALT_USB_GLOB_GUSBCFG_USBTRDTIM field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_GET(value) (((value) & 0x00003c00) >> 10) +/* Produces a ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_SET(value) (((value) << 10) & 0x00003c00) + +/* + * Field : ULPI Auto Resume - ulpiautores + * + * Mode:Host and Device. This bit sets the AutoResume bit in the Interface Control + * register on the ULPI PHY. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_DISD | 0x0 | PHY does not use AutoResume feature + * ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_END | 0x1 | PHY uses AutoResume feature + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIAUTORES + * + * PHY does not use AutoResume feature + */ +#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIAUTORES + * + * PHY uses AutoResume feature + */ +#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_MSB 18 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_SET_MSK 0x00040000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_CLR_MSK 0xfffbffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : ULPI Clock SuspendM - ulpiclksusm + * + * Mode:Host and Device. This bit sets the ClockSuspendM bit in the Interface + * Control register on the ULPI PHY. This bit applies only in serial or carkit + * modes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:---------------------------------------------- + * ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_PWDCLK | 0x0 | PHY powers down internal clock during suspend + * ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_NONPWDCLK | 0x1 | PHY does not power down internal clock + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM + * + * PHY powers down internal clock during suspend + */ +#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_PWDCLK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM + * + * PHY does not power down internal clock + */ +#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_NONPWDCLK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_MSB 19 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_SET_MSK 0x00080000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : ULPI External VBUS Drive - ulpiextvbusdrv + * + * Mode:Host only. This bit selects between internal or external supply to drive 5V + * on VBUS, in ULPI PHY. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------------------------------------- + * ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_INTERN | 0x0 | PHY drives VBUS using internal charge pump + * ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_EXTERN | 0x1 | PHY drives VBUS using external supply + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV + * + * PHY drives VBUS using internal charge pump + */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_INTERN 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV + * + * PHY drives VBUS using external supply + */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_EXTERN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_MSB 20 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : ULPI External VBUS Indicato - ulpiextvbusindicator + * + * Mode:Host only. This bit indicates to the ULPI PHY to use an external VBUS + * overcurrent indicator. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:---------------------------------------- + * ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_INTERN | 0x0 | PHY uses internal VBUS valid comparator + * ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_EXTERN | 0x1 | PHY uses external VBUS valid comparator + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR + * + * PHY uses internal VBUS valid comparator + */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_INTERN 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR + * + * PHY uses external VBUS valid comparator + */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_EXTERN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_MSB 21 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TermSel DLine Pulsing Selection - termseldlpulse + * + * Mode:Device only. This bit selects utmi_termselect to drive data line pulse + * during SRP. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------- + * ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TXVALID | 0x0 | Data line pulsing using utmi_txvalid + * ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TERMSEL | 0x1 | Data line pulsing using utmi_termsel + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE + * + * Data line pulsing using utmi_txvalid + */ +#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TXVALID 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE + * + * Data line pulsing using utmi_termsel + */ +#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TERMSEL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */ +#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */ +#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_MSB 22 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */ +#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value. */ +#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_SET_MSK 0x00400000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value. */ +#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_CLR_MSK 0xffbfffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */ +#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : Indicator Complement - complement + * + * Mode:Host only. Controls the PHY to invert the ExternalVbusIndicator + * inputsignal, generating the ComplementOutput. Please refer to the ULPI Spec for + * more detail. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_NONINVERT | 0x0 | PHY does not invert ExternalVbusIndicator signal + * ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_INVERT | 0x1 | PHY does invert ExternalVbusIndicator signal + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_COMPLEMENT + * + * PHY does not invert ExternalVbusIndicator signal + */ +#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_NONINVERT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_COMPLEMENT + * + * PHY does invert ExternalVbusIndicator signal + */ +#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_INVERT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */ +#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */ +#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_MSB 23 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */ +#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value. */ +#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_SET_MSK 0x00800000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value. */ +#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_CLR_MSK 0xff7fffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */ +#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_COMPLEMENT field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Indicator Pass Throug - indicator + * + * Mode:Host only. Controls wether the Complement Output is qualified with the + * Internal Vbus Valid comparator before being used in the Vbus State in the RX + * CMD. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:------------------------------------------------ + * ALT_USB_GLOB_GUSBCFG_INDICATOR_E_QUALIFIED | 0x0 | Complement Output signal is qualified with the + * : | | Internal VbusValid comparator + * ALT_USB_GLOB_GUSBCFG_INDICATOR_E_NONQUALIFIED | 0x1 | Complement Output signal is not qualified with + * : | | the Internal VbusValid comparator + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_INDICATOR + * + * Complement Output signal is qualified with the Internal VbusValid comparator + */ +#define ALT_USB_GLOB_GUSBCFG_INDICATOR_E_QUALIFIED 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_INDICATOR + * + * Complement Output signal is not qualified with the Internal VbusValid + * comparator + */ +#define ALT_USB_GLOB_GUSBCFG_INDICATOR_E_NONQUALIFIED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */ +#define ALT_USB_GLOB_GUSBCFG_INDICATOR_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */ +#define ALT_USB_GLOB_GUSBCFG_INDICATOR_MSB 24 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */ +#define ALT_USB_GLOB_GUSBCFG_INDICATOR_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_INDICATOR register field value. */ +#define ALT_USB_GLOB_GUSBCFG_INDICATOR_SET_MSK 0x01000000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_INDICATOR register field value. */ +#define ALT_USB_GLOB_GUSBCFG_INDICATOR_CLR_MSK 0xfeffffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */ +#define ALT_USB_GLOB_GUSBCFG_INDICATOR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_INDICATOR field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_INDICATOR_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_USB_GLOB_GUSBCFG_INDICATOR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_INDICATOR_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : ULPI Interface Protect Disable - ulpi + * + * Mode:Host only. Controls circuitry built into the PHY for protecting the ULPI + * interface when the link tri-states STP and data. Any pull-ups or pull-downs + * employed by this feature can be disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:--------------------------------------- + * ALT_USB_GLOB_GUSBCFG_ULPI_E_END | 0x0 | Enables the interface protect circuit + * ALT_USB_GLOB_GUSBCFG_ULPI_E_DISD | 0x1 | Disables the interface protect circuit + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI + * + * Enables the interface protect circuit + */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_E_END 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI + * + * Disables the interface protect circuit + */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_E_DISD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_MSB 25 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPI register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_SET_MSK 0x02000000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPI register field value. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_CLR_MSK 0xfdffffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPI field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_USB_GLOB_GUSBCFG_ULPI register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_ULPI_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Tx End Delay - txenddelay + * + * Mode: Device only. Set to non UTMI+. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------ + * ALT_USB_GLOB_GUSBCFG_TXENDDELAY_E_DISD | 0x0 | Normal Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TXENDDELAY + * + * Normal Mode + */ +#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */ +#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */ +#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_MSB 28 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */ +#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value. */ +#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value. */ +#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */ +#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_TXENDDELAY field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Force Host Mode. - forcehstmode + * + * Mode:Host and device. Writing a 1 to this bit forces the core to host mode After + * setting the force bit, the application must wait at least 25 ms before the + * change to take effect. When the simulation is in scale down mode, waiting for + * 500 micro-sec is sufficient. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------- + * ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_DISD | 0x0 | Normal Mode + * ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_END | 0x1 | Force Host Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD + * + * Normal Mode + */ +#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD + * + * Force Host Mode + */ +#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_MSB 29 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Force Device Mode - forcedevmode + * + * Mode:Host and device. Writing a 1 to this bit forces the core to device mode. + * After setting the force bit, the application must wait at least 25 ms before the + * change to take effect. When the simulation is in scale down mode, waiting for + * 500 micro-sec is sufficient. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------ + * ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_DISD | 0x0 | Normal Mode + * ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_END | 0x1 | Force Device Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD + * + * Normal Mode + */ +#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD + * + * Force Device Mode + */ +#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_MSB 30 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Corrupt Tx packet - corrupttxpkt + * + * Mode: Host and device. This bit is for debug purposes only. Never Set this bit + * to 1. The application should always write 0 to this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_NODBG | 0x0 | Normal Mode + * ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_DBG | 0x1 | Debug Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT + * + * Normal Mode + */ +#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_NODBG 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT + * + * Debug Mode + */ +#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_DBG 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */ +#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */ +#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */ +#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value. */ +#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value. */ +#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */ +#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT field value from a register. */ +#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GUSBCFG. + */ +struct ALT_USB_GLOB_GUSBCFG_s +{ + uint32_t toutcal : 3; /* HS FS Timeout Calibration */ + const uint32_t phyif : 1; /* PHY Interfac */ + const uint32_t ulpi_utmi_sel : 1; /* ULPI Select */ + const uint32_t fsintf : 1; /* Full-Speed Serial Interface Select */ + const uint32_t physel : 1; /* USB 2.0 High-Speed PHY */ + uint32_t ddrsel : 1; /* ULPI DDR Select */ + uint32_t srpcap : 1; /* SRP-Capable */ + uint32_t hnpcap : 1; /* HNP-Capable */ + uint32_t usbtrdtim : 4; /* USB Turnaround Time */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t ulpiautores : 1; /* ULPI Auto Resume */ + uint32_t ulpiclksusm : 1; /* ULPI Clock SuspendM */ + uint32_t ulpiextvbusdrv : 1; /* ULPI External VBUS Drive */ + uint32_t ulpiextvbusindicator : 1; /* ULPI External VBUS Indicato */ + uint32_t termseldlpulse : 1; /* TermSel DLine Pulsing Selection */ + uint32_t complement : 1; /* Indicator Complement */ + uint32_t indicator : 1; /* Indicator Pass Throug */ + uint32_t ulpi : 1; /* ULPI Interface Protect Disable */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t txenddelay : 1; /* Tx End Delay */ + uint32_t forcehstmode : 1; /* Force Host Mode. */ + uint32_t forcedevmode : 1; /* Force Device Mode */ + uint32_t corrupttxpkt : 1; /* Corrupt Tx packet */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GUSBCFG. */ +typedef volatile struct ALT_USB_GLOB_GUSBCFG_s ALT_USB_GLOB_GUSBCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GUSBCFG register from the beginning of the component. */ +#define ALT_USB_GLOB_GUSBCFG_OFST 0xc +/* The address of the ALT_USB_GLOB_GUSBCFG register. */ +#define ALT_USB_GLOB_GUSBCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GUSBCFG_OFST)) + +/* + * Register : Reset Register - grstctl + * + * The application uses this register to reset various hardware features inside the + * core + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [0] | R | 0x0 | Core Soft Reset + * [1] | ??? | 0x0 | *UNDEFINED* + * [2] | R | 0x0 | Host Frame Counter Reset + * [3] | ??? | 0x0 | *UNDEFINED* + * [4] | R | 0x0 | RxFIFO Flush + * [5] | R | 0x0 | TxFIFO Flush + * [10:6] | RW | 0x0 | TxFIFO Number + * [29:11] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | DMA Request Signal + * [31] | R | 0x1 | AHB Master Idle + * + */ +/* + * Field : Core Soft Reset - csftrst + * + * Mode:Host and Device. Resets the hclk and phy_clock domains as follows:Clears + * the interrupts and all the CSR registers except the following register bits: + * + * * PCGCCTL.RstPdwnModule + * + * * PCGCCTL.GateHclk + * + * * PCGCCTL.PwrClmp + * + * * PCGCCTL.StopPPhyLPwrClkSelclk + * + * * GUSBCFG.PhyLPwrClkSel + * + * * GUSBCFG.DDRSel + * + * * GUSBCFG.PHYSel + * + * * GUSBCFG.FSIntf + * + * * GUSBCFG.ULPI_UTMI_Sel + * + * * GUSBCFG.PHYIf + * + * * HCFG.FSLSPclkSel + * + * * DCFG.DevSpd + * + * * GGPIO + * + * * GPWRDN + * + * * GADPCTL + * + * All module state machines (except the AHB Slave Unit) are reset to the IDLE + * state, and all the transmit FIFOs and the receive FIFO are flushed. Any + * transactions on the AHB Master are terminated as soonas possible, after + * gracefully completing the last data phase of an AHB transfer. Any transactions + * on the USB are terminated immediately. When Hibernation or ADP feature is + * enabled, the PMU module is not reset by the Core Soft Reset.The application can + * write to this bit any time it wants to reset the core. This is a self-clearing + * bit and the core clears this bit after all the necessary logic is reset in the + * core, which can take several clocks, depending on the current state of the core. + * Once this bit is cleared software must wait at least 3 PHY clocks before doing + * any access to the PHY domain (synchronization delay). Software must also must + * check that bit 31 of this register is 1 (AHB Master is IDLE) before starting any + * operation.Typically software reset is used during software development and also + * when you dynamically change the PHY selection bits in the USB configuration + * registers listed above. When you change the PHY, the corresponding clock for the + * PHY is selected and used in the PHY domain. Once a new clock is selected, the + * PHY domain has to be reset for proper operation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------- + * ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT | 0x0 | No reset + * ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT | 0x1 | Resets hclk and phy_clock domains + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_CSFTRST + * + * No reset + */ +#define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_CSFTRST + * + * Resets hclk and phy_clock domains + */ +#define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */ +#define ALT_USB_GLOB_GRSTCTL_CSFTRST_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */ +#define ALT_USB_GLOB_GRSTCTL_CSFTRST_MSB 0 +/* The width in bits of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */ +#define ALT_USB_GLOB_GRSTCTL_CSFTRST_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GRSTCTL_CSFTRST register field value. */ +#define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_CSFTRST register field value. */ +#define ALT_USB_GLOB_GRSTCTL_CSFTRST_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */ +#define ALT_USB_GLOB_GRSTCTL_CSFTRST_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRSTCTL_CSFTRST field value from a register. */ +#define ALT_USB_GLOB_GRSTCTL_CSFTRST_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_GLOB_GRSTCTL_CSFTRST register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Host Frame Counter Reset - frmcntrrst + * + * Mode:Host only. The application writes this bit to reset the (micro)frame number + * counter inside the core. When the (micro)frame counter is reset, the subsequent + * SOF sent out by the core has a (micro)frame number of 0. When application writes + * 1 to the bit, it might not be able to read back the value as it will get cleared + * by the core in a few clock cycles. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------- + * ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT | 0x0 | No reset + * ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT | 0x1 | Host Frame Counter Reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_FRMCNTRRST + * + * No reset + */ +#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_FRMCNTRRST + * + * Host Frame Counter Reset + */ +#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */ +#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */ +#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_MSB 2 +/* The width in bits of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */ +#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value. */ +#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value. */ +#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */ +#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST field value from a register. */ +#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : RxFIFO Flush - rxfflsh + * + * Mode:Host and Device. The application can flush the entire RxFIFO using this + * bit, but must first ensure that the core is not in the middle of a transaction. + * The application must only write to this bit after checking that the core is + * neither reading from the RxFIFO nor writing to the RxFIFO. The application must + * wait until the bit is cleared before performing any other operations. This bit + * requires 8 clocks (slowest of PHY or AHB clock) to clear. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------- + * ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT | 0x0 | no flush the entire RxFIFO + * ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT | 0x1 | flush the entire RxFIFO + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_RXFFLSH + * + * no flush the entire RxFIFO + */ +#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_RXFFLSH + * + * flush the entire RxFIFO + */ +#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */ +#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */ +#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_MSB 4 +/* The width in bits of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */ +#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value. */ +#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value. */ +#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */ +#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRSTCTL_RXFFLSH field value from a register. */ +#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : TxFIFO Flush - txfflsh + * + * Mode:Host and Device. This bit selectively flushes a single or all transmit + * FIFOs, but cannot do so If the core is in the midst of a transaction. The + * application must write this bit only after checking that the core is neither + * writing to the TxFIFO nor reading from the TxFIFO. Verify using these registers: + * ReadNAK Effective Interrupt ensures the core is notreading from the FIFO + * WriteGRSTCTL.AHBIdle ensures the core is not writinganything to the FIFO. + * Flushing is normally recommended when FIFOs are reconfigured or when switching + * between Shared FIFO and Dedicated Transmit FIFO operation. FIFO flushing is also + * recommended during device endpoint disable. The application must wait until the + * core clears this bit before performing any operations. This bit takes eight + * clocks to clear, using the slower clock of phy_clk or hclk. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------------------------- + * ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT | 0x0 | No Flush + * ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT | 0x1 | selectively flushes a single or all transmit + * : | | FIFOs + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFFLSH + * + * No Flush + */ +#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFFLSH + * + * selectively flushes a single or all transmit FIFOs + */ +#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */ +#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */ +#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_MSB 5 +/* The width in bits of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */ +#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value. */ +#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value. */ +#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */ +#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRSTCTL_TXFFLSH field value from a register. */ +#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : TxFIFO Number - txfnum + * + * Mode:Host and Device. This is the FIFO number that must be flushed using the + * TxFIFO Flush bit. This field must not be changed until the core clears the + * TxFIFO Flush bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0 | 0x0 | - Non-periodic TxFIFO flush in Host mode - Non- + * : | | periodic TxFIFO flush in device mode when in + * : | | shared FIFO operation + * ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1 | 0x1 | - Periodic TxFIFO flush in Host mode - Periodic + * : | | TxFIFO 1 flush in Device mode when in sharedFIFO + * : | | operation + * ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2 | 0x2 | - Periodic TxFIFO 2 flush in Device mode when in + * : | | sharedFIFO operation- TXFIFO 2 flush in device + * : | | mode when in dedicated FIFO mode + * ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15 | 0xf | - Periodic TxFIFO 15 flush in Device mode when + * : | | in shared FIFO operation - TXFIFO 15 flush in + * : | | device mode when in dedicated FIFO mode + * ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16 | 0x10 | Flush all the transmit FIFOs in device or host + * : | | mode. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM + * + * * Non-periodic TxFIFO flush in Host mode + * + * * Non-periodic TxFIFO flush in device mode when in shared FIFO operation + */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM + * + * * Periodic TxFIFO flush in Host mode + * + * * Periodic TxFIFO 1 flush in Device mode when in sharedFIFO operation + */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM + * + * * Periodic TxFIFO 2 flush in Device mode when in sharedFIFO operation- TXFIFO 2 + * flush in device mode when in dedicated FIFO mode + */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM + * + * * Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation + * + * * TXFIFO 15 flush in device mode when in dedicated FIFO mode + */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15 0xf +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM + * + * Flush all the transmit FIFOs in device or host mode. + */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16 0x10 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_MSB 10 +/* The width in bits of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_WIDTH 5 +/* The mask used to set the ALT_USB_GLOB_GRSTCTL_TXFNUM register field value. */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET_MSK 0x000007c0 +/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_TXFNUM register field value. */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_CLR_MSK 0xfffff83f +/* The reset value of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRSTCTL_TXFNUM field value from a register. */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_GET(value) (((value) & 0x000007c0) >> 6) +/* Produces a ALT_USB_GLOB_GRSTCTL_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET(value) (((value) << 6) & 0x000007c0) + +/* + * Field : DMA Request Signal - dmareq + * + * Mode:Host and Device. Indicates that the DMA request is in progress. Used for + * debug. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------------- + * ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT | 0x0 | No DMA request + * ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT | 0x1 | DMA request is in progress + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_DMAREQ + * + * No DMA request + */ +#define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_DMAREQ + * + * DMA request is in progress + */ +#define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */ +#define ALT_USB_GLOB_GRSTCTL_DMAREQ_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */ +#define ALT_USB_GLOB_GRSTCTL_DMAREQ_MSB 30 +/* The width in bits of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */ +#define ALT_USB_GLOB_GRSTCTL_DMAREQ_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GRSTCTL_DMAREQ register field value. */ +#define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_DMAREQ register field value. */ +#define ALT_USB_GLOB_GRSTCTL_DMAREQ_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */ +#define ALT_USB_GLOB_GRSTCTL_DMAREQ_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRSTCTL_DMAREQ field value from a register. */ +#define ALT_USB_GLOB_GRSTCTL_DMAREQ_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_GLOB_GRSTCTL_DMAREQ register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : AHB Master Idle - ahbidle + * + * Mode:Host and Device. Indicates that the AHB Master State Machine is in the IDLE + * condition. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------- + * ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT | 0x0 | Not Idle + * ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT | 0x1 | AHB Master Idle + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_AHBIDLE + * + * Not Idle + */ +#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_AHBIDLE + * + * AHB Master Idle + */ +#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */ +#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */ +#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */ +#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value. */ +#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value. */ +#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */ +#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GRSTCTL_AHBIDLE field value from a register. */ +#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GRSTCTL. + */ +struct ALT_USB_GLOB_GRSTCTL_s +{ + const uint32_t csftrst : 1; /* Core Soft Reset */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t frmcntrrst : 1; /* Host Frame Counter Reset */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t rxfflsh : 1; /* RxFIFO Flush */ + const uint32_t txfflsh : 1; /* TxFIFO Flush */ + uint32_t txfnum : 5; /* TxFIFO Number */ + uint32_t : 19; /* *UNDEFINED* */ + const uint32_t dmareq : 1; /* DMA Request Signal */ + const uint32_t ahbidle : 1; /* AHB Master Idle */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GRSTCTL. */ +typedef volatile struct ALT_USB_GLOB_GRSTCTL_s ALT_USB_GLOB_GRSTCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GRSTCTL register from the beginning of the component. */ +#define ALT_USB_GLOB_GRSTCTL_OFST 0x10 +/* The address of the ALT_USB_GLOB_GRSTCTL register. */ +#define ALT_USB_GLOB_GRSTCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRSTCTL_OFST)) + +/* + * Register : Interrupt Register - gintsts + * + * This register interrupts the application for system-level events in the current + * mode (Device mode or Host mode). Some of the bits in this register are valid + * only in Host mode, while others are valid in Device mode only. This register + * also indicates the current mode. To clear the interrupt status bits of type + * R_SS_WC, the application must write 1 into the bit. The FIFO status interrupts + * are read only; once software reads from or writes to the FIFO while servicing + * these interrupts, FIFO interrupt conditions are cleared automatically. The + * application must clear the GINTSTS register at initialization before unmasking + * the interrupt bit to avoid any interrupts generated prior to initialization. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------------- + * [0] | R | 0x0 | Current Mode of Operation + * [1] | R | 0x0 | Mode Mismatch Interrupt + * [2] | R | 0x0 | OTG Interrupt + * [3] | R | 0x0 | Start of Frame + * [4] | R | 0x0 | RxFIFO Non-Empty + * [5] | ??? | 0x0 | *UNDEFINED* + * [6] | R | 0x0 | Global IN Non-periodic NAK Effective + * [7] | R | 0x0 | Global OUT NAK Effective + * [9:8] | ??? | 0x0 | *UNDEFINED* + * [10] | R | 0x0 | Early Suspend + * [11] | R | 0x0 | USB Suspend + * [12] | R | 0x0 | USB Reset + * [13] | R | 0x0 | Enumeration Done + * [14] | R | 0x0 | Isochronous OUT Packet Dropped Interrupt + * [16:15] | ??? | 0x0 | *UNDEFINED* + * [17] | R | 0x0 | Endpoint Mismatch Interrupt + * [18] | R | 0x0 | IN Endpoints Interrupt + * [19] | R | 0x0 | OUT Endpoints Interrupt + * [20] | R | 0x0 | Incomplete Isochronous IN Transfer + * [21] | R | 0x0 | Incomplete Periodic Transfer + * [22] | R | 0x0 | Data Fetch Suspended + * [23] | R | 0x0 | Reset detected Interrupt + * [24] | R | 0x0 | Host Port Interrupt + * [25] | R | 0x0 | Host Channels Interrupt + * [26] | R | 0x1 | Periodic TxFIFO Empty + * [27] | ??? | 0x0 | *UNDEFINED* + * [28] | R | 0x1 | Connector ID Status Change + * [29] | R | 0x0 | Disconnect Detected Interrupt + * [30] | R | 0x0 | Session Request New Session Detected Interrupt + * [31] | R | 0x0 | Resume Remote Wakeup Detected Interrupt + * + */ +/* + * Field : Current Mode of Operation - curmod + * + * Mode: Host and Device. Indicates the current mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_GLOB_GINTSTS_CURMOD_E_DEVICE | 0x0 | Device mode + * ALT_USB_GLOB_GINTSTS_CURMOD_E_HOST | 0x1 | Host mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CURMOD + * + * Device mode + */ +#define ALT_USB_GLOB_GINTSTS_CURMOD_E_DEVICE 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CURMOD + * + * Host mode + */ +#define ALT_USB_GLOB_GINTSTS_CURMOD_E_HOST 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */ +#define ALT_USB_GLOB_GINTSTS_CURMOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */ +#define ALT_USB_GLOB_GINTSTS_CURMOD_MSB 0 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */ +#define ALT_USB_GLOB_GINTSTS_CURMOD_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_CURMOD register field value. */ +#define ALT_USB_GLOB_GINTSTS_CURMOD_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_CURMOD register field value. */ +#define ALT_USB_GLOB_GINTSTS_CURMOD_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */ +#define ALT_USB_GLOB_GINTSTS_CURMOD_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_CURMOD field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_CURMOD_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_GLOB_GINTSTS_CURMOD register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_CURMOD_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Mode Mismatch Interrupt - modemis + * + * Mode: Host and Device. The core sets this bit when the application is trying to + * access: + * + * * A Host mode register, when the core is operating in Device mode. -A Device + * mode register, when the core is operating in Host mode. + * + * The register access is completed on the AHB with an OKAYresponse, but is ignored + * by the core internally and does not affect the operation of the core. This bit + * can be set only by the core and the application should write 1 to clearit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------------- + * ALT_USB_GLOB_GINTSTS_MODMIS_E_INACT | 0x0 | No Mode Mismatch Interrupt + * ALT_USB_GLOB_GINTSTS_MODMIS_E_ACT | 0x1 | Mode Mismatch Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_MODMIS + * + * No Mode Mismatch Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_MODMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_MODMIS + * + * Mode Mismatch Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_MODMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */ +#define ALT_USB_GLOB_GINTSTS_MODMIS_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */ +#define ALT_USB_GLOB_GINTSTS_MODMIS_MSB 1 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */ +#define ALT_USB_GLOB_GINTSTS_MODMIS_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_MODMIS register field value. */ +#define ALT_USB_GLOB_GINTSTS_MODMIS_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_MODMIS register field value. */ +#define ALT_USB_GLOB_GINTSTS_MODMIS_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */ +#define ALT_USB_GLOB_GINTSTS_MODMIS_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_MODMIS field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_MODMIS_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_GLOB_GINTSTS_MODMIS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_MODMIS_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : OTG Interrupt - otgint + * + * Mode: Host and Device. The core sets this bit to indicate an OTG protocol event. + * The application must read the OTG Interrupt Status (GOTGINT) register to + * determine the exact event that caused this interrupt. The application must clear + * the appropriate status bit in the GOTGINT register to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------- + * ALT_USB_GLOB_GINTSTS_OTGINT_E_INACT | 0x0 | No Interrupt + * ALT_USB_GLOB_GINTSTS_OTGINT_E_ACT | 0x1 | OTG Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OTGINT + * + * No Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_OTGINT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OTGINT + * + * OTG Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_OTGINT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */ +#define ALT_USB_GLOB_GINTSTS_OTGINT_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */ +#define ALT_USB_GLOB_GINTSTS_OTGINT_MSB 2 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */ +#define ALT_USB_GLOB_GINTSTS_OTGINT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_OTGINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_OTGINT_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_OTGINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_OTGINT_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */ +#define ALT_USB_GLOB_GINTSTS_OTGINT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_OTGINT field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_OTGINT_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_GLOB_GINTSTS_OTGINT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_OTGINT_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Start of Frame - sof + * + * Mode: Host and Device. In Host mode, the core sets this bit to indicate that an + * SOF (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB. The + * application must write a 1 to this bit to clear the interrupt. In Device mode, + * the core sets this bit to indicate that an SOF token has been received on the + * USB. The application can read the Device Status register to get the current + * (micro)Frame number. This interrupt is seen only when the core is operating at + * either HS or FS. This bit can be set only by the core and the application should + * write 1 to clear it. This register may return 1 if read immediately after power + * on reset. If the register bit reads 1 immediately after power on reset it does + * not indicate that an SOF has been sent (in case of host mode) or SOF has been + * received (in case of device mode). The read value of this interrupt is valid + * only after a valid connection between host and device is established. If the bit + * is set after power on reset the application can clear the bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------- + * ALT_USB_GLOB_GINTSTS_SOF_E_INTACT | 0x0 | No sof + * ALT_USB_GLOB_GINTSTS_SOF_E_ACT | 0x1 | Start of Frame + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SOF + * + * No sof + */ +#define ALT_USB_GLOB_GINTSTS_SOF_E_INTACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SOF + * + * Start of Frame + */ +#define ALT_USB_GLOB_GINTSTS_SOF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_SOF register field. */ +#define ALT_USB_GLOB_GINTSTS_SOF_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_SOF register field. */ +#define ALT_USB_GLOB_GINTSTS_SOF_MSB 3 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_SOF register field. */ +#define ALT_USB_GLOB_GINTSTS_SOF_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_SOF register field value. */ +#define ALT_USB_GLOB_GINTSTS_SOF_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_SOF register field value. */ +#define ALT_USB_GLOB_GINTSTS_SOF_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_GLOB_GINTSTS_SOF register field. */ +#define ALT_USB_GLOB_GINTSTS_SOF_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_SOF field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_SOF_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_GLOB_GINTSTS_SOF register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_SOF_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : RxFIFO Non-Empty - rxflvl + * + * Mode: Host and Device. Indicates that there is at least one packet pending to be + * read from the RxFIFO. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_GLOB_GINTSTS_RXFLVL_E_INACT | 0x0 | Not Active + * ALT_USB_GLOB_GINTSTS_RXFLVL_E_ACT | 0x1 | Rx Fifo Non Empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RXFLVL + * + * Not Active + */ +#define ALT_USB_GLOB_GINTSTS_RXFLVL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RXFLVL + * + * Rx Fifo Non Empty + */ +#define ALT_USB_GLOB_GINTSTS_RXFLVL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */ +#define ALT_USB_GLOB_GINTSTS_RXFLVL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */ +#define ALT_USB_GLOB_GINTSTS_RXFLVL_MSB 4 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */ +#define ALT_USB_GLOB_GINTSTS_RXFLVL_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_RXFLVL register field value. */ +#define ALT_USB_GLOB_GINTSTS_RXFLVL_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_RXFLVL register field value. */ +#define ALT_USB_GLOB_GINTSTS_RXFLVL_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */ +#define ALT_USB_GLOB_GINTSTS_RXFLVL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_RXFLVL field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_RXFLVL_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_GLOB_GINTSTS_RXFLVL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_RXFLVL_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Global IN Non-periodic NAK Effective - ginnakeff + * + * Mode: Device only. Indicates that the Set Global Non-periodic IN NAK bit in the + * Device Control register (DCTL.SGNPInNak), Set by the application, has taken + * effect in the core. That is, the core has sampled the Global IN NAK bit Set by + * the application. This bit can be cleared by clearing the Clear Global Non- + * periodic IN NAK bit in the Device Control register (DCTL.CGNPInNak). This + * interrupt does not necessarily mean that a NAK handshake is sent out on the USB. + * The STALL bit takes precedence over the NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------------- + * ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_ACT | 0x1 | Set Global Non-periodic IN NAK bi + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GINNAKEFF + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GINNAKEFF + * + * Set Global Non-periodic IN NAK bi + */ +#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */ +#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */ +#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */ +#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value. */ +#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value. */ +#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */ +#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_GINNAKEFF field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Global OUT NAK Effective - goutnakeff + * + * Mode: Device only. Indicates that the Set Global OUT NAK bit in the Device + * Control register (DCTL.SGOUTNak), Set by the application, has taken effect in + * the core. This bit can be cleared by writing the Clear Global OUT NAK bit in the + * Device Control register (DCTL.CGOUTNak). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------- + * ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_INACT | 0x0 | No Active + * ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_ACT | 0x1 | Global OUT NAK Effective + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GOUTNAKEFF + * + * No Active + */ +#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GOUTNAKEFF + * + * Global OUT NAK Effective + */ +#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */ +#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */ +#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_MSB 7 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */ +#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value. */ +#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value. */ +#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */ +#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Early Suspend - erlysusp + * + * Mode: Device only. The core sets this bit to indicate that an Idle state has + * been detected on the USB for 3 ms. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_INACT | 0x0 | No Idle + * ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_ACT | 0x1 | Idle state detecetd + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ERLYSUSP + * + * No Idle + */ +#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ERLYSUSP + * + * Idle state detecetd + */ +#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_MSB 10 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value. */ +#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value. */ +#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_ERLYSUSP field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : USB Suspend - usbsusp + * + * Mode: Device only. The core sets this bit to indicate that a suspend was + * detected on the USB. The core enters the Suspended state when there is no + * activity on the phy_line_state_i signal for an extended period of time. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_GLOB_GINTSTS_USBSUSP_E_INACT | 0x0 | Not Active + * ALT_USB_GLOB_GINTSTS_USBSUSP_E_ACT | 0x1 | USB Suspend + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBSUSP + * + * Not Active + */ +#define ALT_USB_GLOB_GINTSTS_USBSUSP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBSUSP + * + * USB Suspend + */ +#define ALT_USB_GLOB_GINTSTS_USBSUSP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_USBSUSP_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_USBSUSP_MSB 11 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_USBSUSP_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_USBSUSP register field value. */ +#define ALT_USB_GLOB_GINTSTS_USBSUSP_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_USBSUSP register field value. */ +#define ALT_USB_GLOB_GINTSTS_USBSUSP_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_USBSUSP_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_USBSUSP field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_USBSUSP_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_GLOB_GINTSTS_USBSUSP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_USBSUSP_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : USB Reset - usbrst + * + * Mode: Device only. The core sets this bit to indicate that a reset is detected + * on the USB. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_GLOB_GINTSTS_USBRST_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_USBRST_E_ACT | 0x1 | USB Reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBRST + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_USBRST_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBRST + * + * USB Reset + */ +#define ALT_USB_GLOB_GINTSTS_USBRST_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_USBRST register field. */ +#define ALT_USB_GLOB_GINTSTS_USBRST_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_USBRST register field. */ +#define ALT_USB_GLOB_GINTSTS_USBRST_MSB 12 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_USBRST register field. */ +#define ALT_USB_GLOB_GINTSTS_USBRST_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_USBRST register field value. */ +#define ALT_USB_GLOB_GINTSTS_USBRST_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_USBRST register field value. */ +#define ALT_USB_GLOB_GINTSTS_USBRST_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_GLOB_GINTSTS_USBRST register field. */ +#define ALT_USB_GLOB_GINTSTS_USBRST_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_USBRST field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_USBRST_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_GLOB_GINTSTS_USBRST register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_USBRST_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Enumeration Done - enumdone + * + * Mode: Device only. The core sets this bit to indicate that speed enumeration is + * complete. The application must read the Device Status register to obtain the + * enumerated speed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------- + * ALT_USB_GLOB_GINTSTS_ENUMDONE_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_ENUMDONE_E_ACT | 0x1 | Enumeration Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ENUMDONE + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_ENUMDONE_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ENUMDONE + * + * Enumeration Done + */ +#define ALT_USB_GLOB_GINTSTS_ENUMDONE_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */ +#define ALT_USB_GLOB_GINTSTS_ENUMDONE_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */ +#define ALT_USB_GLOB_GINTSTS_ENUMDONE_MSB 13 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */ +#define ALT_USB_GLOB_GINTSTS_ENUMDONE_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_ENUMDONE register field value. */ +#define ALT_USB_GLOB_GINTSTS_ENUMDONE_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_ENUMDONE register field value. */ +#define ALT_USB_GLOB_GINTSTS_ENUMDONE_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */ +#define ALT_USB_GLOB_GINTSTS_ENUMDONE_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_ENUMDONE field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_ENUMDONE_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_GLOB_GINTSTS_ENUMDONE register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_ENUMDONE_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Isochronous OUT Packet Dropped Interrupt - isooutdrop + * + * Mode: Device only. The core sets this bit when it fails to write an isochronous + * OUT packet into the RxFIFO because the RxFIFO does not have enough space to + * accommodate a maximum packet size packet for the isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------------- + * ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_ACT | 0x1 | Isochronous OUT Packet Dropped Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ISOOUTDROP + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ISOOUTDROP + * + * Isochronous OUT Packet Dropped Interrup + */ +#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */ +#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */ +#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_MSB 14 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */ +#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value. */ +#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value. */ +#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */ +#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_ISOOUTDROP field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : Endpoint Mismatch Interrupt - epmis + * + * Mode: Device only. This interrupt is valid only in shared FIFO operation. + * Indicates that an IN token has been received for a non-periodic endpoint, but + * the data for another endpoint is present in the top of the Non-periodic Transmit + * FIFO and the IN endpoint mismatch count programmed by the application has + * expired. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------------------- + * ALT_USB_GLOB_GINTSTS_EPMIS_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_EPMIS_E_ACT | 0x1 | Endpoint Mismatch Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_EPMIS + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_EPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_EPMIS + * + * Endpoint Mismatch Interrup + */ +#define ALT_USB_GLOB_GINTSTS_EPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */ +#define ALT_USB_GLOB_GINTSTS_EPMIS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */ +#define ALT_USB_GLOB_GINTSTS_EPMIS_MSB 17 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */ +#define ALT_USB_GLOB_GINTSTS_EPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_EPMIS register field value. */ +#define ALT_USB_GLOB_GINTSTS_EPMIS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_EPMIS register field value. */ +#define ALT_USB_GLOB_GINTSTS_EPMIS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */ +#define ALT_USB_GLOB_GINTSTS_EPMIS_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_EPMIS field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_EPMIS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_GLOB_GINTSTS_EPMIS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_EPMIS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : IN Endpoints Interrupt - iepint + * + * Mode: Device only. The core sets this bit to indicate that an interrupt is + * pending on one of the IN endpoints of the core (in Device mode). The application + * must read the Device All Endpoints Interrupt (DAINT) register to determine the + * exact number of the IN endpoint on Device IN Endpoint-n Interrupt (DIEPINTn) + * register to determine the exact cause of the interrupt. The application must + * clear the appropriate status bit in the corresponding DIEPINTn register to clear + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------- + * ALT_USB_GLOB_GINTSTS_IEPINT_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_IEPINT_E_ACT | 0x1 | IN Endpoints Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_IEPINT + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_IEPINT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_IEPINT + * + * IN Endpoints Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_IEPINT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_IEPINT_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_IEPINT_MSB 18 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_IEPINT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_IEPINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_IEPINT_SET_MSK 0x00040000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_IEPINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_IEPINT_CLR_MSK 0xfffbffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_IEPINT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_IEPINT field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_IEPINT_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_USB_GLOB_GINTSTS_IEPINT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_IEPINT_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : OUT Endpoints Interrupt - oepint + * + * Mode: Device only. The core sets this bit to indicate that an interrupt is + * pending on one of the OUT endpoints of the core (in Device mode). The + * application must read the Device All Endpoints Interrupt (DAINT) register to + * determine the exact number of the OUT endpoint on which the interrupt occurred, + * and Then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) + * register to determine the exact cause of the interrupt. The application must + * clear the appropriate status bit in the corresponding DOEPINTn register to clear + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------ + * ALT_USB_GLOB_GINTSTS_OEPINT_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_OEPINT_E_ACT | 0x1 | OUT Endpoints Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OEPINT + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_OEPINT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OEPINT + * + * OUT Endpoints Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_OEPINT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_OEPINT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_OEPINT_MSB 19 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_OEPINT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_OEPINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_OEPINT_SET_MSK 0x00080000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_OEPINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_OEPINT_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_OEPINT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_OEPINT field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_OEPINT_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_USB_GLOB_GINTSTS_OEPINT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_OEPINT_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Incomplete Isochronous IN Transfer - incompisoin + * + * Mode: Device only. The core sets this interrupt to indicate that there is at + * least isochronous IN endpoint on which the transfer is not completed in the + * current microframe. This interrupt is asserted along with the End of Periodic + * Frame Interrupt (EOPF) bit in this register. This interrupt is not asserted in + * Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------------- + * ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_ACT | 0x1 | Incomplete Isochronous IN Transfer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPISOIN + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPISOIN + * + * Incomplete Isochronous IN Transfer + */ +#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_MSB 20 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_INCOMPISOIN field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Incomplete Periodic Transfer - incomplp + * + * Mode: Device only. In Host mode, the core sets this interrupt bit when there are + * incomplete periodic transactions still pending which arescheduled for the + * current microframe. Incomplete Isochronous OUT Transfer (incompISOOUT) The + * Device mode, the core sets this interrupt to indicate that there is at least one + * isochronous OUT endpoint on which the transfer is not completed in the current + * microframe. This interrupt is asserted along with the End of Periodic Frame + * Interrupt (EOPF) bit in this register. This bit can be set only by the core and + * the application should write 1 to clear it + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_GLOB_GINTSTS_INCOMPLP_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_INCOMPLP_E_ACT | 0x1 | Incomplete Periodic Transfer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPLP + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_INCOMPLP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPLP + * + * Incomplete Periodic Transfer + */ +#define ALT_USB_GLOB_GINTSTS_INCOMPLP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPLP_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPLP_MSB 21 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPLP_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_INCOMPLP register field value. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPLP_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_INCOMPLP register field value. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPLP_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPLP_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_INCOMPLP field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPLP_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_GLOB_GINTSTS_INCOMPLP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_INCOMPLP_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Data Fetch Suspended - fetsusp + * + * Mode: Device only. This interrupt is valid only in DMA mode. This interrupt + * indicates that the core has stopped fetching data for IN endpoints due to the + * unavailability of TxFIFO space or Request Queue space. This interrupt is used by + * the application for an endpoint mismatch algorithm. for example, after detecting + * an endpoint mismatch, the application: + * + * * Sets a Global non-periodic IN NAK handshake + * + * * Disables In endpoints + * + * * Flushes the FIFO + * + * * Determines the token sequence from the IN Token Sequence + * + * Learning Queue + * + * * Re-enables the endpoints + * + * * Clears the Global non-periodic IN NAK handshake + * + * If the Global non-periodic IN NAK is cleared, the core has not yet fetched data + * for the IN endpoint, and the IN token is received: the core generates an IN + * token received when FIFO empty interrupt. The OTG Then sends the host a NAK + * response. To avoid this scenario, the application can check the GINTSTS.FetSusp + * interrupt, which ensures that the FIFO is full before clearing a Global NAK + * handshake. Alternatively, the application can mask the "IN token received when + * FIFO empty" interrupt when clearing a Global IN NAKhandshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_USB_GLOB_GINTSTS_FETSUSP_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_FETSUSP_E_ACT | 0x1 | Data Fetch Suspended + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_FETSUSP + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_FETSUSP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_FETSUSP + * + * Data Fetch Suspended + */ +#define ALT_USB_GLOB_GINTSTS_FETSUSP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_FETSUSP_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_FETSUSP_MSB 22 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_FETSUSP_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_FETSUSP register field value. */ +#define ALT_USB_GLOB_GINTSTS_FETSUSP_SET_MSK 0x00400000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_FETSUSP register field value. */ +#define ALT_USB_GLOB_GINTSTS_FETSUSP_CLR_MSK 0xffbfffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */ +#define ALT_USB_GLOB_GINTSTS_FETSUSP_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_FETSUSP field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_FETSUSP_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_USB_GLOB_GINTSTS_FETSUSP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_FETSUSP_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : Reset detected Interrupt - resetdet + * + * Mode: Device only. In Device mode, this interrupt is asserted when a reset is + * detected on the USB in partial power-down mode when the device is in Suspend. In + * Host mode, this interrupt is not asserted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------ + * ALT_USB_GLOB_GINTSTS_RSTDET_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_RSTDET_E_ACT | 0x1 | Reset detected Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RSTDET + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_RSTDET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RSTDET + * + * Reset detected Interrup + */ +#define ALT_USB_GLOB_GINTSTS_RSTDET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */ +#define ALT_USB_GLOB_GINTSTS_RSTDET_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */ +#define ALT_USB_GLOB_GINTSTS_RSTDET_MSB 23 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */ +#define ALT_USB_GLOB_GINTSTS_RSTDET_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_RSTDET register field value. */ +#define ALT_USB_GLOB_GINTSTS_RSTDET_SET_MSK 0x00800000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_RSTDET register field value. */ +#define ALT_USB_GLOB_GINTSTS_RSTDET_CLR_MSK 0xff7fffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */ +#define ALT_USB_GLOB_GINTSTS_RSTDET_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_RSTDET field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_RSTDET_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_USB_GLOB_GINTSTS_RSTDET register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_RSTDET_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Host Port Interrupt - prtint + * + * Mode:Host only. The core sets this bit to indicate a change in port status of + * one of the otg core ports in Host mode. The application must read the Host Port + * Control and Status (HPRT) register to determine the exact event that caused this + * interrupt. The application must clear the appropriate status bit in the Host PC + * Control and Status register to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_GLOB_GINTSTS_PRTINT_E_INACT | 0x0 | + * ALT_USB_GLOB_GINTSTS_PRTINT_E_ACT | 0x1 | Host Port Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PRTINT + * + */ +#define ALT_USB_GLOB_GINTSTS_PRTINT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PRTINT + * + * Host Port Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_PRTINT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */ +#define ALT_USB_GLOB_GINTSTS_PRTINT_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */ +#define ALT_USB_GLOB_GINTSTS_PRTINT_MSB 24 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */ +#define ALT_USB_GLOB_GINTSTS_PRTINT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_PRTINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_PRTINT_SET_MSK 0x01000000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_PRTINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_PRTINT_CLR_MSK 0xfeffffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */ +#define ALT_USB_GLOB_GINTSTS_PRTINT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_PRTINT field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_PRTINT_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_USB_GLOB_GINTSTS_PRTINT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_PRTINT_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Host Channels Interrupt - hchint + * + * Mode:Host only. The core sets this bit to indicate that an interrupt is pending + * on one of the channels of the core (in Host mode). The application must read the + * Host All Channels Interrupt (HAINT) register to determine the exact number of + * the channel on which the interrupt occurred, and Then read the corresponding + * Host Channel-n Interrupt (HCINTn) register to determine the exact cause of the + * interrupt. The application must clear the appropriate status bit in the HCINTn + * register to clear this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------ + * ALT_USB_GLOB_GINTSTS_HCHINT_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_HCHINT_E_ACT | 0x1 | Host Channels Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_HCHINT + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_HCHINT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_HCHINT + * + * Host Channels Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_HCHINT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */ +#define ALT_USB_GLOB_GINTSTS_HCHINT_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */ +#define ALT_USB_GLOB_GINTSTS_HCHINT_MSB 25 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */ +#define ALT_USB_GLOB_GINTSTS_HCHINT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_HCHINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_HCHINT_SET_MSK 0x02000000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_HCHINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_HCHINT_CLR_MSK 0xfdffffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */ +#define ALT_USB_GLOB_GINTSTS_HCHINT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_HCHINT field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_HCHINT_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_USB_GLOB_GINTSTS_HCHINT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_HCHINT_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Periodic TxFIFO Empty - ptxfemp + * + * Mode:Host only. This interrupt is asserted when the Periodic Transmit FIFO is + * either half or completely empty and there is space for at least one entry to be + * written in the Periodic Request Queue. The half or completely empty status is + * determined by the Periodic TxFIFO Empty Level bit in the Core AHB Configuration + * register (GAHBCFG.PTxFEmpLvl). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------- + * ALT_USB_GLOB_GINTSTS_PTXFEMP_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_PTXFEMP_E_ACT | 0x1 | Periodic TxFIFO Empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PTXFEMP + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_PTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PTXFEMP + * + * Periodic TxFIFO Empty + */ +#define ALT_USB_GLOB_GINTSTS_PTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */ +#define ALT_USB_GLOB_GINTSTS_PTXFEMP_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */ +#define ALT_USB_GLOB_GINTSTS_PTXFEMP_MSB 26 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */ +#define ALT_USB_GLOB_GINTSTS_PTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_PTXFEMP register field value. */ +#define ALT_USB_GLOB_GINTSTS_PTXFEMP_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_PTXFEMP register field value. */ +#define ALT_USB_GLOB_GINTSTS_PTXFEMP_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */ +#define ALT_USB_GLOB_GINTSTS_PTXFEMP_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GINTSTS_PTXFEMP field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_PTXFEMP_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_GLOB_GINTSTS_PTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_PTXFEMP_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Connector ID Status Change - ConIDStsChng + * + * Mode:Host and Device. The core sets this bit when there is a change in connector + * ID status. This bit can be set only by the core and the application should write + * 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------- + * ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_INACT | 0x0 | Not Active + * ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_ACT | 0x1 | Connector ID Status Change + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG + * + * Not Active + */ +#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG + * + * Connector ID Status Change + */ +#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */ +#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */ +#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_MSB 28 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */ +#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value. */ +#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value. */ +#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */ +#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Disconnect Detected Interrupt - disconnint + * + * Mode:Host only. Asserted when a device disconnect is detected. This bit can be + * set only by the core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------ + * ALT_USB_GLOB_GINTSTS_DISCONNINT_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_DISCONNINT_E_ACT | 0x1 | Disconnect Detected Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_DISCONNINT + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_DISCONNINT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_DISCONNINT + * + * Disconnect Detected Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_DISCONNINT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */ +#define ALT_USB_GLOB_GINTSTS_DISCONNINT_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */ +#define ALT_USB_GLOB_GINTSTS_DISCONNINT_MSB 29 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */ +#define ALT_USB_GLOB_GINTSTS_DISCONNINT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_DISCONNINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_DISCONNINT_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_DISCONNINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_DISCONNINT_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */ +#define ALT_USB_GLOB_GINTSTS_DISCONNINT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_DISCONNINT field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_DISCONNINT_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_GLOB_GINTSTS_DISCONNINT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_DISCONNINT_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Session Request New Session Detected Interrupt - sessreqint + * + * Mode:Host and Device. In Host mode, this interrupt is asserted when a session + * request is detected from the device. In Host mode, this interrupt is asserted + * when a session request is detected from the device. In Device mode, this + * interrupt is asserted when the utmisrp_bvalid signal goes high. This bit can be + * set only by the core and the application should write 1 to clear. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------------------------- + * ALT_USB_GLOB_GINTSTS_SESSREQINT_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_SESSREQINT_E_ACT | 0x1 | Session Request New Session Detected Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SESSREQINT + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_SESSREQINT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SESSREQINT + * + * Session Request New Session Detected Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_SESSREQINT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */ +#define ALT_USB_GLOB_GINTSTS_SESSREQINT_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */ +#define ALT_USB_GLOB_GINTSTS_SESSREQINT_MSB 30 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */ +#define ALT_USB_GLOB_GINTSTS_SESSREQINT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_SESSREQINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_SESSREQINT_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_SESSREQINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_SESSREQINT_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */ +#define ALT_USB_GLOB_GINTSTS_SESSREQINT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_SESSREQINT field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_SESSREQINT_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_GLOB_GINTSTS_SESSREQINT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_SESSREQINT_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Resume Remote Wakeup Detected Interrupt - wkupint + * + * Mode:Host and Device. Wakeup Interrupt during Suspend(L2) or LPM(L1) state. + * -During Suspend(L2): + * + * * Device Mode - This interrupt is asserted only when Host Initiated Resume is + * detected on USB. + * + * * Host Mode - This interrupt is asserted only when Device Initiated Remote + * Wakeup is detected on USB + * + * * During LPM(L1):- - Device Mode - This interrupt is asserted for either Host + * Initiated Resume or Device Initiated Remote Wakeup on USB. + * + * * Host Mode - This interrupt is asserted for either Host Initiated Resume or + * Device Initiated Remote Wakeup on USB. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------- + * ALT_USB_GLOB_GINTSTS_WKUPINT_E_INACT | 0x0 | Not active + * ALT_USB_GLOB_GINTSTS_WKUPINT_E_ACT | 0x1 | Resume Remote Wakeup Detected Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_WKUPINT + * + * Not active + */ +#define ALT_USB_GLOB_GINTSTS_WKUPINT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTSTS_WKUPINT + * + * Resume Remote Wakeup Detected Interrupt + */ +#define ALT_USB_GLOB_GINTSTS_WKUPINT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_WKUPINT_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_WKUPINT_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_WKUPINT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTSTS_WKUPINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_WKUPINT_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_GLOB_GINTSTS_WKUPINT register field value. */ +#define ALT_USB_GLOB_GINTSTS_WKUPINT_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */ +#define ALT_USB_GLOB_GINTSTS_WKUPINT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTSTS_WKUPINT field value from a register. */ +#define ALT_USB_GLOB_GINTSTS_WKUPINT_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_GLOB_GINTSTS_WKUPINT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTSTS_WKUPINT_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GINTSTS. + */ +struct ALT_USB_GLOB_GINTSTS_s +{ + const uint32_t curmod : 1; /* Current Mode of Operation */ + const uint32_t modemis : 1; /* Mode Mismatch Interrupt */ + const uint32_t otgint : 1; /* OTG Interrupt */ + const uint32_t sof : 1; /* Start of Frame */ + const uint32_t rxflvl : 1; /* RxFIFO Non-Empty */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t ginnakeff : 1; /* Global IN Non-periodic NAK Effective */ + const uint32_t goutnakeff : 1; /* Global OUT NAK Effective */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t erlysusp : 1; /* Early Suspend */ + const uint32_t usbsusp : 1; /* USB Suspend */ + const uint32_t usbrst : 1; /* USB Reset */ + const uint32_t enumdone : 1; /* Enumeration Done */ + const uint32_t isooutdrop : 1; /* Isochronous OUT Packet Dropped Interrupt */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t epmis : 1; /* Endpoint Mismatch Interrupt */ + const uint32_t iepint : 1; /* IN Endpoints Interrupt */ + const uint32_t oepint : 1; /* OUT Endpoints Interrupt */ + const uint32_t incompisoin : 1; /* Incomplete Isochronous IN Transfer */ + const uint32_t incomplp : 1; /* Incomplete Periodic Transfer */ + const uint32_t fetsusp : 1; /* Data Fetch Suspended */ + const uint32_t resetdet : 1; /* Reset detected Interrupt */ + const uint32_t prtint : 1; /* Host Port Interrupt */ + const uint32_t hchint : 1; /* Host Channels Interrupt */ + const uint32_t ptxfemp : 1; /* Periodic TxFIFO Empty */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t ConIDStsChng : 1; /* Connector ID Status Change */ + const uint32_t disconnint : 1; /* Disconnect Detected Interrupt */ + const uint32_t sessreqint : 1; /* Session Request New Session Detected Interrupt */ + const uint32_t wkupint : 1; /* Resume Remote Wakeup Detected Interrupt */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GINTSTS. */ +typedef volatile struct ALT_USB_GLOB_GINTSTS_s ALT_USB_GLOB_GINTSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GINTSTS register from the beginning of the component. */ +#define ALT_USB_GLOB_GINTSTS_OFST 0x14 +/* The address of the ALT_USB_GLOB_GINTSTS register. */ +#define ALT_USB_GLOB_GINTSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GINTSTS_OFST)) + +/* + * Register : Interrupt Mask Register - gintmsk + * + * This register works with the Interrupt Register (GINTSTS) to interrupt the + * application. When an interrupt bit is masked, the interrupt associated with that + * bit is not generated. However, the GINTSTS register bit corresponding to that + * interrupt is still set. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :------|:-------|:------|:--------------------------------------------------- + * [0] | ??? | 0x0 | *UNDEFINED* + * [1] | RW | 0x0 | Mode Mismatch Interrupt Mask + * [2] | RW | 0x0 | OTG Interrupt Mask + * [3] | RW | 0x0 | Start of (micro)Frame Mask + * [4] | RW | 0x0 | Receive FIFO Non-Empty Mask + * [5] | ??? | 0x0 | *UNDEFINED* + * [6] | RW | 0x0 | Global Non-periodic IN NAK Effective Mask + * [7] | RW | 0x0 | Global OUT NAK Effective Mask + * [9:8] | ??? | 0x0 | *UNDEFINED* + * [10] | RW | 0x0 | Early Suspend Mask + * [11] | RW | 0x0 | USB Suspend Mask + * [12] | RW | 0x0 | USB Reset Mask + * [13] | RW | 0x0 | Enumeration Done Mask + * [14] | RW | 0x0 | Isochronous OUT Packet Dropped Interrupt Mask + * [15] | RW | 0x0 | End of Periodic Frame Interrupt Mask + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Endpoint Mismatch Interrupt Mask + * [18] | RW | 0x0 | IN Endpoints Interrupt Mask + * [19] | RW | 0x0 | OUT Endpoints Interrupt Mask + * [20] | RW | 0x0 | Incomplete Isochronous IN Transfer Mask + * [21] | RW | 0x0 | Incomplete Periodic Transfer Mask + * [22] | RW | 0x0 | Data Fetch Suspended Mask + * [23] | RW | 0x0 | Reset detected Interrupt Mask + * [24] | RW | 0x0 | Host Port Interrupt Mask + * [25] | RW | 0x0 | Host Channels Interrupt Mask + * [26] | RW | 0x0 | Periodic TxFIFO Empty Mask + * [27] | ??? | 0x0 | *UNDEFINED* + * [28] | RW | 0x0 | Connector ID Status Change Mask + * [29] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_DISCONNINTMSK + * [30] | RW | 0x0 | Session Request New Session Detected Interrupt Mas + * [31] | RW | 0x0 | Resume Remote Wakeup Detected Interrupt Mask + * + */ +/* + * Field : Mode Mismatch Interrupt Mask - modemismsk + * + * Mode: Host and Device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------- + * ALT_USB_GLOB_GINTMSK_MODMISMSK_E_MSK | 0x0 | Mode Mismatch Interrupt Mask + * ALT_USB_GLOB_GINTMSK_MODMISMSK_E_NOMSK | 0x1 | No Mask Mode Mismatch Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_MODMISMSK + * + * Mode Mismatch Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_MODMISMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_MODMISMSK + * + * No Mask Mode Mismatch Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_MODMISMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_MODMISMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_MODMISMSK_MSB 1 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_MODMISMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_MODMISMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_MODMISMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_MODMISMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_MODMISMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_MODMISMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_MODMISMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_MODMISMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_GLOB_GINTMSK_MODMISMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_MODMISMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : OTG Interrupt Mask - otgintmsk + * + * Mode: Host and Device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------- + * ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_MSK | 0x0 | OTG Interrupt Mask + * ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_NOMSK | 0x1 | No mask OTG Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OTGINTMSK + * + * OTG Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OTGINTMSK + * + * No mask OTG Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_MSB 2 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_OTGINTMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Start of (micro)Frame Mask - sofmsk + * + * Mode: Host and Device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------- + * ALT_USB_GLOB_GINTMSK_SOFMSK_E_MSK | 0x0 | Start of Frame Mask + * ALT_USB_GLOB_GINTMSK_SOFMSK_E_NOMSK | 0x1 | No Mask Start of Frame + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SOFMSK + * + * Start of Frame Mask + */ +#define ALT_USB_GLOB_GINTMSK_SOFMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SOFMSK + * + * No Mask Start of Frame + */ +#define ALT_USB_GLOB_GINTMSK_SOFMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_SOFMSK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_SOFMSK_MSB 3 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_SOFMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_SOFMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_SOFMSK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_SOFMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_SOFMSK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_SOFMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_SOFMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_SOFMSK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_GLOB_GINTMSK_SOFMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_SOFMSK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Receive FIFO Non-Empty Mask - rxflvlmsk + * + * Mode: Host and Device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------- + * ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_MSK | 0x0 | Receive FIFO Non-Empty Mask + * ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_NOMSK | 0x1 | No maks Receive FIFO Non-Empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RXFLVLMSK + * + * Receive FIFO Non-Empty Mask + */ +#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RXFLVLMSK + * + * No maks Receive FIFO Non-Empty + */ +#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_MSB 4 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_RXFLVLMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Global Non-periodic IN NAK Effective Mask - ginnakeffmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------------------------- + * ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_MSK | 0x0 | Global Non-periodic IN NAK Effective Mask + * ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_NOMSK | 0x1 | No mask Global Non-periodic IN NAK Effective + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK + * + * Global Non-periodic IN NAK Effective Mask + */ +#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK + * + * No mask Global Non-periodic IN NAK Effective + */ +#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_MSB 6 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Global OUT NAK Effective Mask - goutnakeffmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------- + * ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_MSK | 0x0 | Global OUT NAK Effective Mask + * ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_NOMAKS | 0x1 | No mask Global OUT NAK Effective + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK + * + * Global OUT NAK Effective Mask + */ +#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK + * + * No mask Global OUT NAK Effective + */ +#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_NOMAKS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_MSB 7 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Early Suspend Mask - erlysuspmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------- + * ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_MSK | 0x0 | Early Suspend Mask + * ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_NOMSK | 0x1 | No mask Early Suspend Mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK + * + * Early Suspend Mask + */ +#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK + * + * No mask Early Suspend Mask + */ +#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_MSB 10 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : USB Suspend Mask - usbsuspmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_MSK | 0x0 | USB Suspend Mask + * ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_NOMSK | 0x1 | No mask USB Suspend + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBSUSPMSK + * + * USB Suspend Mask + */ +#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBSUSPMSK + * + * No mask USB Suspend + */ +#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_MSB 11 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_USBSUSPMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : USB Reset Mask - usbrstmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------ + * ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_MSK | 0x0 | USB Reset Mask + * ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_NOMSK | 0x1 | No mask USB Reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBRSTMSK + * + * USB Reset Mask + */ +#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBRSTMSK + * + * No mask USB Reset + */ +#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_MSB 12 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_USBRSTMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Enumeration Done Mask - enumdonemsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------- + * ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_MSK | 0x0 | Enumeration Done Mask + * ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_NOMSK | 0x1 | No mask Enumeration Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ENUMDONEMSK + * + * Enumeration Done Mask + */ +#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ENUMDONEMSK + * + * No mask Enumeration Done + */ +#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_MSB 13 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Isochronous OUT Packet Dropped Interrupt Mask - isooutdropmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------------------------- + * ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_MSK | 0x0 | Isochronous OUT Packet Dropped Interrupt Mask + * ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_NOMSK | 0x1 | No mask Isochronous OUT Packet Dropped Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK + * + * Isochronous OUT Packet Dropped Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK + * + * No mask Isochronous OUT Packet Dropped Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_MSB 14 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : End of Periodic Frame Interrupt Mask - eopfmsk + * + * Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------- + * ALT_USB_GLOB_GINTMSK_EOPFMSK_E_MSK | 0x0 | End of Periodic Frame Interrupt Mask + * ALT_USB_GLOB_GINTMSK_EOPFMSK_E_NOMSK | 0x1 | No mask End of Periodic Frame Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EOPFMSK + * + * End of Periodic Frame Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_EOPFMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EOPFMSK + * + * No mask End of Periodic Frame Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_EOPFMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_EOPFMSK_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_EOPFMSK_MSB 15 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_EOPFMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_EOPFMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_EOPFMSK_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_EOPFMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_EOPFMSK_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_EOPFMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_EOPFMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_EOPFMSK_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_GLOB_GINTMSK_EOPFMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_EOPFMSK_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Mismatch Interrupt Mask - epmismsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------ + * ALT_USB_GLOB_GINTMSK_EPMISMSK_E_MSK | 0x0 | Endpoint Mismatch Interrupt Mask + * ALT_USB_GLOB_GINTMSK_EPMISMSK_E_NOMSK | 0x1 | No mask Endpoint Mismatch Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EPMISMSK + * + * Endpoint Mismatch Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_EPMISMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EPMISMSK + * + * No mask Endpoint Mismatch Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_EPMISMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_EPMISMSK_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_EPMISMSK_MSB 17 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_EPMISMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_EPMISMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_EPMISMSK_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_EPMISMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_EPMISMSK_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_EPMISMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_EPMISMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_EPMISMSK_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_GLOB_GINTMSK_EPMISMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_EPMISMSK_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : IN Endpoints Interrupt Mask - iepintmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------- + * ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_MSK | 0x0 | IN Endpoints Interrupt Mask + * ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_NOMAKS | 0x1 | No mask IN Endpoints Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_IEPINTMSK + * + * IN Endpoints Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_IEPINTMSK + * + * No mask IN Endpoints Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_NOMAKS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_MSB 18 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_SET_MSK 0x00040000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_CLR_MSK 0xfffbffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_IEPINTMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : OUT Endpoints Interrupt Mask - oepintmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------- + * ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_MSK | 0x0 | OUT Endpoints Interrupt Mask + * ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_NOMSK | 0x1 | No mask OUT Endpoints Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OEPINTMSK + * + * OUT Endpoints Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OEPINTMSK + * + * No mask OUT Endpoints Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_MSB 19 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_SET_MSK 0x00080000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_OEPINTMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Incomplete Isochronous IN Transfer Mask - incompisoinmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------- + * ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_MSK | 0x0 | Incomplete Isochronous IN Transfer Mask + * ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_NOMSK | 0x1 | No mask Incomplete Isochronous IN Transfer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK + * + * Incomplete Isochronous IN Transfer Mask + */ +#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK + * + * No mask Incomplete Isochronous IN Transfer + */ +#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_MSB 20 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Incomplete Periodic Transfer Mask - incomplpmsk + * + * Mode: Host only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------- + * ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_MSK | 0x0 | Incomplete Periodic Transfer Mask + * ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_NOMSK | 0x1 | No mask Incomplete Periodic Transfer + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPLPMSK + * + * Incomplete Periodic Transfer Mask + */ +#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPLPMSK + * + * No mask Incomplete Periodic Transfer + */ +#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_MSB 21 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Data Fetch Suspended Mask - fetsuspmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_MSK | 0x0 | Data Fetch Suspended Mask + * ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_NOMSK | 0x1 | No mask Data Fetch Suspended + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_FETSUSPMSK + * + * Data Fetch Suspended Mask + */ +#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_FETSUSPMSK + * + * No mask Data Fetch Suspended + */ +#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_MSB 22 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_SET_MSK 0x00400000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_CLR_MSK 0xffbfffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_FETSUSPMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : Reset detected Interrupt Mask - resetdetmsk + * + * Mode: Device only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------------------- + * ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_MSK | 0x0 | Reset detected Interrupt Mask + * ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_NOMSK | 0x1 | No mask Reset detected Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RSTDETMSK + * + * Reset detected Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RSTDETMSK + * + * No mask Reset detected Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_MSB 23 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_SET_MSK 0x00800000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_CLR_MSK 0xff7fffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_RSTDETMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Host Port Interrupt Mask - prtintmsk + * + * Mode: Host only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_MSK | 0x0 | Host Port Interrupt Mask + * ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_NOMSK | 0x1 | No mask Host Port Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PRTINTMSK + * + * Host Port Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PRTINTMSK + * + * No mask Host Port Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_MSB 24 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_SET_MSK 0x01000000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_CLR_MSK 0xfeffffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_PRTINTMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Host Channels Interrupt Mask - hchintmsk + * + * Mode: Host only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------------- + * ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_MSK | 0x0 | Host Channels Interrupt Mask + * ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_NOMSK | 0x1 | No mask Host Channels Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_HCHINTMSK + * + * Host Channels Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_HCHINTMSK + * + * No mask Host Channels Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_MSB 25 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_SET_MSK 0x02000000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_CLR_MSK 0xfdffffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_HCHINTMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Periodic TxFIFO Empty Mask - ptxfempmsk + * + * Mode: Host only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------ + * ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_MSK | 0x0 | Periodic TxFIFO Empty Mask + * ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_NOMSK | 0x1 | No mask Periodic TxFIFO Empty + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PTXFEMPMSK + * + * Periodic TxFIFO Empty Mask + */ +#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PTXFEMPMSK + * + * No mask Periodic TxFIFO Empty + */ +#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_MSB 26 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Connector ID Status Change Mask - conidstschngmsk + * + * Mode: Host and Device. This bit can be set only by the core and the application + * should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:----------------------------------- + * ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_MSK | 0x0 | Connector ID Status Change Mask + * ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_NOMSK | 0x1 | No mask Connector ID Status Change + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK + * + * Connector ID Status Change Mask + */ +#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK + * + * No mask Connector ID Status Change + */ +#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_MSB 28 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : disconnintmsk + * + * Mode: Host and Device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------------- + * ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_MSK | 0x0 | Disconnect Detected Interrupt Mask + * ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_NOMSK | 0x1 | No mask Disconnect Detected Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_DISCONNINTMSK + * + * Disconnect Detected Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_DISCONNINTMSK + * + * No mask Disconnect Detected Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_MSB 29 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Session Request New Session Detected Interrupt Mas - sessreqintmsk + * + * Mode: Host and Device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------------------------------------- + * ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_MSK | 0x0 | Session Request New Session Detected Interrupt + * : | | Mask + * ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_NOMSK | 0x1 | No mask Session RequestNew Session Detected + * : | | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SESSREQINTMSK + * + * Session Request New Session Detected Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SESSREQINTMSK + * + * No mask Session RequestNew Session Detected Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_MSB 30 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Resume Remote Wakeup Detected Interrupt Mask - wkupintmsk + * + * Mode: Host and Device. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------------------------- + * ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_MSK | 0x0 | Resume Remote Wakeup Detected Interrupt Mask + * ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_NOMSK | 0x1 | No maskResume Remote Wakeup Detected Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_WKUPINTMSK + * + * Resume Remote Wakeup Detected Interrupt Mask + */ +#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GINTMSK_WKUPINTMSK + * + * No maskResume Remote Wakeup Detected Interrupt + */ +#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value. */ +#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */ +#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GINTMSK_WKUPINTMSK field value from a register. */ +#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GINTMSK. + */ +struct ALT_USB_GLOB_GINTMSK_s +{ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t modemismsk : 1; /* Mode Mismatch Interrupt Mask */ + uint32_t otgintmsk : 1; /* OTG Interrupt Mask */ + uint32_t sofmsk : 1; /* Start of (micro)Frame Mask */ + uint32_t rxflvlmsk : 1; /* Receive FIFO Non-Empty Mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t ginnakeffmsk : 1; /* Global Non-periodic IN NAK Effective Mask */ + uint32_t goutnakeffmsk : 1; /* Global OUT NAK Effective Mask */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t erlysuspmsk : 1; /* Early Suspend Mask */ + uint32_t usbsuspmsk : 1; /* USB Suspend Mask */ + uint32_t usbrstmsk : 1; /* USB Reset Mask */ + uint32_t enumdonemsk : 1; /* Enumeration Done Mask */ + uint32_t isooutdropmsk : 1; /* Isochronous OUT Packet Dropped Interrupt Mask */ + uint32_t eopfmsk : 1; /* End of Periodic Frame Interrupt Mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t epmismsk : 1; /* Endpoint Mismatch Interrupt Mask */ + uint32_t iepintmsk : 1; /* IN Endpoints Interrupt Mask */ + uint32_t oepintmsk : 1; /* OUT Endpoints Interrupt Mask */ + uint32_t incompisoinmsk : 1; /* Incomplete Isochronous IN Transfer Mask */ + uint32_t incomplpmsk : 1; /* Incomplete Periodic Transfer Mask */ + uint32_t fetsuspmsk : 1; /* Data Fetch Suspended Mask */ + uint32_t resetdetmsk : 1; /* Reset detected Interrupt Mask */ + uint32_t prtintmsk : 1; /* Host Port Interrupt Mask */ + uint32_t hchintmsk : 1; /* Host Channels Interrupt Mask */ + uint32_t ptxfempmsk : 1; /* Periodic TxFIFO Empty Mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t conidstschngmsk : 1; /* Connector ID Status Change Mask */ + uint32_t disconnintmsk : 1; /* ALT_USB_GLOB_GINTMSK_DISCONNINTMSK */ + uint32_t sessreqintmsk : 1; /* Session Request New Session Detected Interrupt Mas */ + uint32_t wkupintmsk : 1; /* Resume Remote Wakeup Detected Interrupt Mask */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GINTMSK. */ +typedef volatile struct ALT_USB_GLOB_GINTMSK_s ALT_USB_GLOB_GINTMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GINTMSK register from the beginning of the component. */ +#define ALT_USB_GLOB_GINTMSK_OFST 0x18 +/* The address of the ALT_USB_GLOB_GINTMSK register. */ +#define ALT_USB_GLOB_GINTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GINTMSK_OFST)) + +/* + * Register : Receive Status Debug Read Register - grxstsr + * + * A read to the Receive Status Read and Pop register additionally pops the: top + * data entry out of the RxFIFO. The receive status contents must be interpreted + * differently in Host and Device modes. The core ignores the receive status + * pop/read when the receive FIFO is empty and returns a value of 0. The + * application must only pop the Receive Status FIFO when the Receive FIFO Non- + * Empty bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted. Use of + * these fields vary based on whether the HS OTG core is functioning as a host or a + * device. Do not read this register's reset value before configuring the core + * because the read value is "X" in the simulation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------- + * [3:0] | R | 0x0 | Channel Number + * [14:4] | R | 0x0 | Byte Count + * [16:15] | R | 0x0 | Data PID + * [20:17] | R | 0x0 | Packet Status + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Channel Number - chnum + * + * Indicates the endpoint number to which the current received packet belongs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */ +#define ALT_USB_GLOB_GRXSTSR_CHNUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */ +#define ALT_USB_GLOB_GRXSTSR_CHNUM_MSB 3 +/* The width in bits of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */ +#define ALT_USB_GLOB_GRXSTSR_CHNUM_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GRXSTSR_CHNUM register field value. */ +#define ALT_USB_GLOB_GRXSTSR_CHNUM_SET_MSK 0x0000000f +/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_CHNUM register field value. */ +#define ALT_USB_GLOB_GRXSTSR_CHNUM_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */ +#define ALT_USB_GLOB_GRXSTSR_CHNUM_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRXSTSR_CHNUM field value from a register. */ +#define ALT_USB_GLOB_GRXSTSR_CHNUM_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_USB_GLOB_GRXSTSR_CHNUM register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRXSTSR_CHNUM_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Byte Count - bcnt + * + * Indicates the byte count of the received data packet. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */ +#define ALT_USB_GLOB_GRXSTSR_BCNT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */ +#define ALT_USB_GLOB_GRXSTSR_BCNT_MSB 14 +/* The width in bits of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */ +#define ALT_USB_GLOB_GRXSTSR_BCNT_WIDTH 11 +/* The mask used to set the ALT_USB_GLOB_GRXSTSR_BCNT register field value. */ +#define ALT_USB_GLOB_GRXSTSR_BCNT_SET_MSK 0x00007ff0 +/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_BCNT register field value. */ +#define ALT_USB_GLOB_GRXSTSR_BCNT_CLR_MSK 0xffff800f +/* The reset value of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */ +#define ALT_USB_GLOB_GRXSTSR_BCNT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRXSTSR_BCNT field value from a register. */ +#define ALT_USB_GLOB_GRXSTSR_BCNT_GET(value) (((value) & 0x00007ff0) >> 4) +/* Produces a ALT_USB_GLOB_GRXSTSR_BCNT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRXSTSR_BCNT_SET(value) (((value) << 4) & 0x00007ff0) + +/* + * Field : Data PID - dpid + * + * Indicates the Data PID of the received packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_GLOB_GRXSTSR_DPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_GLOB_GRXSTSR_DPID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_GLOB_GRXSTSR_DPID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_GLOB_GRXSTSR_DPID_E_MDATA | 0x3 | MDATA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID + * + * DATA0 + */ +#define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID + * + * DATA1 + */ +#define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID + * + * DATA2 + */ +#define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID + * + * MDATA + */ +#define ALT_USB_GLOB_GRXSTSR_DPID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_DPID register field. */ +#define ALT_USB_GLOB_GRXSTSR_DPID_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_DPID register field. */ +#define ALT_USB_GLOB_GRXSTSR_DPID_MSB 16 +/* The width in bits of the ALT_USB_GLOB_GRXSTSR_DPID register field. */ +#define ALT_USB_GLOB_GRXSTSR_DPID_WIDTH 2 +/* The mask used to set the ALT_USB_GLOB_GRXSTSR_DPID register field value. */ +#define ALT_USB_GLOB_GRXSTSR_DPID_SET_MSK 0x00018000 +/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_DPID register field value. */ +#define ALT_USB_GLOB_GRXSTSR_DPID_CLR_MSK 0xfffe7fff +/* The reset value of the ALT_USB_GLOB_GRXSTSR_DPID register field. */ +#define ALT_USB_GLOB_GRXSTSR_DPID_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRXSTSR_DPID field value from a register. */ +#define ALT_USB_GLOB_GRXSTSR_DPID_GET(value) (((value) & 0x00018000) >> 15) +/* Produces a ALT_USB_GLOB_GRXSTSR_DPID register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRXSTSR_DPID_SET(value) (((value) << 15) & 0x00018000) + +/* + * Field : Packet Status - pktsts + * + * Mode: Host only. Others: Reserved. Indicates the status of the received packet + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:--------------------------------------------- + * ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INDPRX | 0x2 | IN data packet received + * ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INTRCOM | 0x3 | IN transfer completed (triggers an interrupt + * ALT_USB_GLOB_GRXSTSR_PKTSTS_E_DTTOG | 0x5 | Data toggle error (triggers an interrupt) + * ALT_USB_GLOB_GRXSTSR_PKTSTS_E_CHHALT | 0x7 | Channel halted (triggers an interrupt) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS + * + * IN data packet received + */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INDPRX 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS + * + * IN transfer completed (triggers an interrupt + */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INTRCOM 0x3 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS + * + * Data toggle error (triggers an interrupt) + */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_DTTOG 0x5 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS + * + * Channel halted (triggers an interrupt) + */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_CHHALT 0x7 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_MSB 20 +/* The width in bits of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GRXSTSR_PKTSTS register field value. */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_SET_MSK 0x001e0000 +/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_PKTSTS register field value. */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_CLR_MSK 0xffe1ffff +/* The reset value of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRXSTSR_PKTSTS field value from a register. */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_GET(value) (((value) & 0x001e0000) >> 17) +/* Produces a ALT_USB_GLOB_GRXSTSR_PKTSTS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRXSTSR_PKTSTS_SET(value) (((value) << 17) & 0x001e0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GRXSTSR. + */ +struct ALT_USB_GLOB_GRXSTSR_s +{ + const uint32_t chnum : 4; /* Channel Number */ + const uint32_t bcnt : 11; /* Byte Count */ + const uint32_t dpid : 2; /* Data PID */ + const uint32_t pktsts : 4; /* Packet Status */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GRXSTSR. */ +typedef volatile struct ALT_USB_GLOB_GRXSTSR_s ALT_USB_GLOB_GRXSTSR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GRXSTSR register from the beginning of the component. */ +#define ALT_USB_GLOB_GRXSTSR_OFST 0x1c +/* The address of the ALT_USB_GLOB_GRXSTSR register. */ +#define ALT_USB_GLOB_GRXSTSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXSTSR_OFST)) + +/* + * Register : Receive Status Read Pop Register - grxstsp + * + * A read to the Receive Status Read and Pop register additionally pops the: top + * data entry out of the RxFIFO. The receive status contents must be interpreted + * differently in Host and Device modes. The core ignores the receive status + * pop/read when the receive FIFO is empty and returns a value of 0. The + * application must only pop the Receive Status FIFO when the Receive FIFO Non- + * Empty bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted. Use of + * these fields vary based on whether the HS OTG core is functioning as a host or a + * device. Do not read this register'ss reset value before configuring the core + * because the read value is "X" in the simulation. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------- + * [3:0] | R | 0x0 | Channel Number + * [14:4] | R | 0x0 | Byte Count + * [16:15] | R | 0x0 | Data PID + * [20:17] | R | 0x0 | Packet Status + * [24:21] | R | 0x0 | Frame Number + * [31:25] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Channel Number - chnum + * + * Mode: Host only. Indicates the channel number to which the current received + * packet belongs. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */ +#define ALT_USB_GLOB_GRXSTSP_CHNUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */ +#define ALT_USB_GLOB_GRXSTSP_CHNUM_MSB 3 +/* The width in bits of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */ +#define ALT_USB_GLOB_GRXSTSP_CHNUM_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GRXSTSP_CHNUM register field value. */ +#define ALT_USB_GLOB_GRXSTSP_CHNUM_SET_MSK 0x0000000f +/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_CHNUM register field value. */ +#define ALT_USB_GLOB_GRXSTSP_CHNUM_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */ +#define ALT_USB_GLOB_GRXSTSP_CHNUM_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRXSTSP_CHNUM field value from a register. */ +#define ALT_USB_GLOB_GRXSTSP_CHNUM_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_USB_GLOB_GRXSTSP_CHNUM register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRXSTSP_CHNUM_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Byte Count - bcnt + * + * Mode: Host only. Indicates the byte count of the received IN data packet. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */ +#define ALT_USB_GLOB_GRXSTSP_BCNT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */ +#define ALT_USB_GLOB_GRXSTSP_BCNT_MSB 14 +/* The width in bits of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */ +#define ALT_USB_GLOB_GRXSTSP_BCNT_WIDTH 11 +/* The mask used to set the ALT_USB_GLOB_GRXSTSP_BCNT register field value. */ +#define ALT_USB_GLOB_GRXSTSP_BCNT_SET_MSK 0x00007ff0 +/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_BCNT register field value. */ +#define ALT_USB_GLOB_GRXSTSP_BCNT_CLR_MSK 0xffff800f +/* The reset value of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */ +#define ALT_USB_GLOB_GRXSTSP_BCNT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRXSTSP_BCNT field value from a register. */ +#define ALT_USB_GLOB_GRXSTSP_BCNT_GET(value) (((value) & 0x00007ff0) >> 4) +/* Produces a ALT_USB_GLOB_GRXSTSP_BCNT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRXSTSP_BCNT_SET(value) (((value) << 4) & 0x00007ff0) + +/* + * Field : Data PID - dpid + * + * Indicates the Data PID of the received OUT data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_GLOB_GRXSTSP_DPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_GLOB_GRXSTSP_DPID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_GLOB_GRXSTSP_DPID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_GLOB_GRXSTSP_DPID_E_MDATA | 0x3 | MDATA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID + * + * DATA0 + */ +#define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID + * + * DATA1 + */ +#define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID + * + * DATA2 + */ +#define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID + * + * MDATA + */ +#define ALT_USB_GLOB_GRXSTSP_DPID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_DPID register field. */ +#define ALT_USB_GLOB_GRXSTSP_DPID_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_DPID register field. */ +#define ALT_USB_GLOB_GRXSTSP_DPID_MSB 16 +/* The width in bits of the ALT_USB_GLOB_GRXSTSP_DPID register field. */ +#define ALT_USB_GLOB_GRXSTSP_DPID_WIDTH 2 +/* The mask used to set the ALT_USB_GLOB_GRXSTSP_DPID register field value. */ +#define ALT_USB_GLOB_GRXSTSP_DPID_SET_MSK 0x00018000 +/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_DPID register field value. */ +#define ALT_USB_GLOB_GRXSTSP_DPID_CLR_MSK 0xfffe7fff +/* The reset value of the ALT_USB_GLOB_GRXSTSP_DPID register field. */ +#define ALT_USB_GLOB_GRXSTSP_DPID_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRXSTSP_DPID field value from a register. */ +#define ALT_USB_GLOB_GRXSTSP_DPID_GET(value) (((value) & 0x00018000) >> 15) +/* Produces a ALT_USB_GLOB_GRXSTSP_DPID register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRXSTSP_DPID_SET(value) (((value) << 15) & 0x00018000) + +/* + * Field : Packet Status - pktsts + * + * Mode: Host only. Others: Reserved. Indicates the status of the received packet + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA0 | 0x0 | DATA0 + * ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA1 | 0x2 | DATA1 + * ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA2 | 0x1 | DATA2 + * ALT_USB_GLOB_GRXSTSP_PKTSTS_E_MDATA | 0x3 | MDATA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS + * + * DATA0 + */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS + * + * DATA1 + */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS + * + * DATA2 + */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS + * + * MDATA + */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_MSB 20 +/* The width in bits of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GRXSTSP_PKTSTS register field value. */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_SET_MSK 0x001e0000 +/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_PKTSTS register field value. */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_CLR_MSK 0xffe1ffff +/* The reset value of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRXSTSP_PKTSTS field value from a register. */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_GET(value) (((value) & 0x001e0000) >> 17) +/* Produces a ALT_USB_GLOB_GRXSTSP_PKTSTS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRXSTSP_PKTSTS_SET(value) (((value) << 17) & 0x001e0000) + +/* + * Field : Frame Number - fn + * + * Mode: Device only. This is the least significant 4 bits of the (micro)Frame + * number in which the packet is received on the USB. This field is supported only + * when isochronous OUT endpoints are supported. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_FN register field. */ +#define ALT_USB_GLOB_GRXSTSP_FN_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_FN register field. */ +#define ALT_USB_GLOB_GRXSTSP_FN_MSB 24 +/* The width in bits of the ALT_USB_GLOB_GRXSTSP_FN register field. */ +#define ALT_USB_GLOB_GRXSTSP_FN_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GRXSTSP_FN register field value. */ +#define ALT_USB_GLOB_GRXSTSP_FN_SET_MSK 0x01e00000 +/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_FN register field value. */ +#define ALT_USB_GLOB_GRXSTSP_FN_CLR_MSK 0xfe1fffff +/* The reset value of the ALT_USB_GLOB_GRXSTSP_FN register field. */ +#define ALT_USB_GLOB_GRXSTSP_FN_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GRXSTSP_FN field value from a register. */ +#define ALT_USB_GLOB_GRXSTSP_FN_GET(value) (((value) & 0x01e00000) >> 21) +/* Produces a ALT_USB_GLOB_GRXSTSP_FN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRXSTSP_FN_SET(value) (((value) << 21) & 0x01e00000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GRXSTSP. + */ +struct ALT_USB_GLOB_GRXSTSP_s +{ + const uint32_t chnum : 4; /* Channel Number */ + const uint32_t bcnt : 11; /* Byte Count */ + const uint32_t dpid : 2; /* Data PID */ + const uint32_t pktsts : 4; /* Packet Status */ + const uint32_t fn : 4; /* Frame Number */ + uint32_t : 7; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GRXSTSP. */ +typedef volatile struct ALT_USB_GLOB_GRXSTSP_s ALT_USB_GLOB_GRXSTSP_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GRXSTSP register from the beginning of the component. */ +#define ALT_USB_GLOB_GRXSTSP_OFST 0x20 +/* The address of the ALT_USB_GLOB_GRXSTSP register. */ +#define ALT_USB_GLOB_GRXSTSP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXSTSP_OFST)) + +/* + * Register : Receive FIFO Size Register - grxfsiz + * + * The application can program the RAM size that must be allocated to the RxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------- + * [13:0] | RW | 0x2000 | RxFIFO Depth + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : RxFIFO Depth - rxfdep + * + * This value is in terms of 32-bit words. Minimum value is 16 Maximum value is + * 32,768 The power-on reset value of this register is specified as the Largest Rx + * Data FIFO Dept 8192. Using the Dynamic FIFO Sizing, you can write a new value in + * this field. Programmed values must not exceed 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */ +#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */ +#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_MSB 13 +/* The width in bits of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */ +#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value. */ +#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_SET_MSK 0x00003fff +/* The mask used to clear the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value. */ +#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_CLR_MSK 0xffffc000 +/* The reset value of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */ +#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_GRXFSIZ_RXFDEP field value from a register. */ +#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_GET(value) (((value) & 0x00003fff) >> 0) +/* Produces a ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_SET(value) (((value) << 0) & 0x00003fff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GRXFSIZ. + */ +struct ALT_USB_GLOB_GRXFSIZ_s +{ + uint32_t rxfdep : 14; /* RxFIFO Depth */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GRXFSIZ. */ +typedef volatile struct ALT_USB_GLOB_GRXFSIZ_s ALT_USB_GLOB_GRXFSIZ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GRXFSIZ register from the beginning of the component. */ +#define ALT_USB_GLOB_GRXFSIZ_OFST 0x24 +/* The address of the ALT_USB_GLOB_GRXFSIZ register. */ +#define ALT_USB_GLOB_GRXFSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXFSIZ_OFST)) + +/* + * Register : Non-periodic Transmit FIFO Size Register - gnptxfsiz + * + * The application can program the RAM size and the memory start address for the + * Non-periodic TxFIFO. The fields of this register change, depending on host or + * device mode. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:---------------------------------------- + * [13:0] | RW | 0x2000 | Non-periodic Transmit RAM Start Address + * [15:14] | ??? | 0x0 | *UNDEFINED* + * [29:16] | RW | 0x2000 | Non-periodic TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Non-periodic Transmit RAM Start Address - nptxfstaddr + * + * Mode: Host only. for host mode, this field is always valid.This field contains + * the memory start address for Non-periodic Transmit FIFO RAM. This field is set + * from 16-8192 32 bit words. The application can write a new value in this field. + * Programmed values must not exceed 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_MSB 13 +/* The width in bits of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_SET_MSK 0x00003fff +/* The mask used to clear the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_CLR_MSK 0xffffc000 +/* The reset value of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_GET(value) (((value) & 0x00003fff) >> 0) +/* Produces a ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_SET(value) (((value) << 0) & 0x00003fff) + +/* + * Field : Non-periodic TxFIFO Depth - nptxfdep + * + * Mode: Host only. for host mode, this field is always valid. The application can + * write a new value in this field. Programmed values must not exceed 8192 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP field value from a register. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GNPTXFSIZ. + */ +struct ALT_USB_GLOB_GNPTXFSIZ_s +{ + uint32_t nptxfstaddr : 14; /* Non-periodic Transmit RAM Start Address */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t nptxfdep : 14; /* Non-periodic TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GNPTXFSIZ. */ +typedef volatile struct ALT_USB_GLOB_GNPTXFSIZ_s ALT_USB_GLOB_GNPTXFSIZ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GNPTXFSIZ register from the beginning of the component. */ +#define ALT_USB_GLOB_GNPTXFSIZ_OFST 0x28 +/* The address of the ALT_USB_GLOB_GNPTXFSIZ register. */ +#define ALT_USB_GLOB_GNPTXFSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GNPTXFSIZ_OFST)) + +/* + * Register : Non-periodic Transmit FIFO Queue Status Register - gnptxsts + * + * In Device mode, this register is valid only in Shared FIFO operation. It + * contains the free space information for the Non-periodic TxFIFO and the + * Nonperiodic Transmit RequestQueue + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------------- + * [15:0] | R | 0x400 | Non-periodic TxFIFO Space Avail + * [23:16] | R | 0x8 | Non-periodic Transmit Request Queue Space Available + * [30:24] | R | 0x0 | Top of the Non-periodic Transmit Request Queue + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Non-periodic TxFIFO Space Avail - nptxfspcavail + * + * Indicates the amount of free space available in the Non-periodic TxFIFO.Values + * are in terms of 32-bit words. 16h0: Non-periodic TxFIFO is full 16h1: 1 word + * available 16h2: 2 words available 16hn: n words available (where 0 n 32,768) + * 16h8000: 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_RESET 0x400 +/* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Non-periodic Transmit Request Queue Space Available - nptxqspcavail + * + * Indicates the amount of free space available in the Non-periodic Transmit + * Request Queue. This queue holds both IN and OUT requests in Host mode. Device + * mode has only IN requests. -Others: Reserved + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------------------- + * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_FULL | 0x0 | Non-periodic Transmit Request Queue is full + * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE1 | 0x1 | 1 location available + * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE2 | 0x2 | 2 locations available + * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE3 | 0x3 | 3 locations available + * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE4 | 0x4 | 4 locations available + * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE5 | 0x5 | 5 locations available + * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE6 | 0x6 | 6 locations available + * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE7 | 0x7 | 7 locations available + * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE8 | 0x8 | 8 locations available + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL + * + * Non-periodic Transmit Request Queue is full + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_FULL 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL + * + * 1 location available + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE1 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL + * + * 2 locations available + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE2 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL + * + * 3 locations available + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE3 0x3 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL + * + * 4 locations available + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE4 0x4 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL + * + * 5 locations available + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE5 0x5 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL + * + * 6 locations available + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE6 0x6 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL + * + * 7 locations available + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE7 0x7 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL + * + * 8 locations available + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE8 0x8 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_MSB 23 +/* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_WIDTH 8 +/* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_CLR_MSK 0xff00ffff +/* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_RESET 0x8 +/* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL field value from a register. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Top of the Non-periodic Transmit Request Queue - nptxqtop + * + * Entry in the Non-periodic Tx Request Queue that is currently being processed by + * the MAC. + * + * * Bits [30:27]: Channel/endpoint number + * + * * Bits [26:25]: + * + * * Bit [24]: Terminate (last Entry for selected channel endpoint) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------------------- + * ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_INOUTTK | 0x0 | IN/OUT token + * ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_ZEROTX | 0x1 | Zero-length transmit packet (device IN/host OUT) + * ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_PINGCSPLIT | 0x2 | PING/CSPLIT token + * ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_CHNHALT | 0x3 | Channel halt command + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP + * + * IN/OUT token + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_INOUTTK 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP + * + * Zero-length transmit packet (device IN/host OUT) + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_ZEROTX 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP + * + * PING/CSPLIT token + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_PINGCSPLIT 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP + * + * Channel halt command + */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_CHNHALT 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_MSB 30 +/* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_WIDTH 7 +/* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_SET_MSK 0x7f000000 +/* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_CLR_MSK 0x80ffffff +/* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP field value from a register. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_GET(value) (((value) & 0x7f000000) >> 24) +/* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_SET(value) (((value) << 24) & 0x7f000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GNPTXSTS. + */ +struct ALT_USB_GLOB_GNPTXSTS_s +{ + const uint32_t nptxfspcavail : 16; /* Non-periodic TxFIFO Space Avail */ + const uint32_t nptxqspcavail : 8; /* Non-periodic Transmit Request Queue Space Available */ + const uint32_t nptxqtop : 7; /* Top of the Non-periodic Transmit Request Queue */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GNPTXSTS. */ +typedef volatile struct ALT_USB_GLOB_GNPTXSTS_s ALT_USB_GLOB_GNPTXSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GNPTXSTS register from the beginning of the component. */ +#define ALT_USB_GLOB_GNPTXSTS_OFST 0x2c +/* The address of the ALT_USB_GLOB_GNPTXSTS register. */ +#define ALT_USB_GLOB_GNPTXSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GNPTXSTS_OFST)) + +/* + * Register : PHY Vendor Control Register - gpvndctl + * + * The application can use this register to access PHY registers. for a ULPI PHY, + * the core uses the ULPI interface for PHY register access. The application sets + * Vendor Control register for PHY register access and times the PHY register + * access. The application polls the VStatus Done bit in this register for the + * completion of the PHY register access + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [7:0] | RW | 0x0 | Register Data + * [15:8] | RW | 0x0 | UTMI+ Vendor Control Register Address + * [21:16] | RW | 0x0 | Register Address + * [22] | RW | 0x0 | Register Write + * [24:23] | ??? | 0x0 | *UNDEFINED* + * [25] | R | 0x0 | New Register Request + * [26] | R | 0x0 | VStatus Busy + * [27] | R | 0x0 | VStatus Done + * [30:28] | ??? | 0x0 | *UNDEFINED* + * [31] | R | 0x0 | Disable ULPI Drivers + * + */ +/* + * Field : Register Data - regdata + * + * Contains the write data for register write. Read data for register read, valid + * when VStatus Done is Set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGDATA_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGDATA_MSB 7 +/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGDATA_WIDTH 8 +/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGDATA register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_REGDATA_SET_MSK 0x000000ff +/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGDATA register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_REGDATA_CLR_MSK 0xffffff00 +/* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGDATA_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GPVNDCTL_REGDATA field value from a register. */ +#define ALT_USB_GLOB_GPVNDCTL_REGDATA_GET(value) (((value) & 0x000000ff) >> 0) +/* Produces a ALT_USB_GLOB_GPVNDCTL_REGDATA register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GPVNDCTL_REGDATA_SET(value) (((value) << 0) & 0x000000ff) + +/* + * Field : UTMI+ Vendor Control Register Address - vctrl + * + * The 4-bit register address a vendor defined 4-bit parallel output bus. ULPI + * Extended Register Address and the 6-bit PHY extended register address. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VCTL_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VCTL_MSB 15 +/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VCTL_WIDTH 8 +/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VCTL register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_VCTL_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VCTL register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_VCTL_CLR_MSK 0xffff00ff +/* The reset value of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VCTL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GPVNDCTL_VCTL field value from a register. */ +#define ALT_USB_GLOB_GPVNDCTL_VCTL_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_USB_GLOB_GPVNDCTL_VCTL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GPVNDCTL_VCTL_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Register Address - regaddr + * + * The 6-bit PHY register address for immediate PHY Register Set access. Set to + * 0x2F for Extended PHY Register Set access. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGADDR_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGADDR_MSB 21 +/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGADDR_WIDTH 6 +/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGADDR register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_REGADDR_SET_MSK 0x003f0000 +/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGADDR register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_REGADDR_CLR_MSK 0xffc0ffff +/* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGADDR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GPVNDCTL_REGADDR field value from a register. */ +#define ALT_USB_GLOB_GPVNDCTL_REGADDR_GET(value) (((value) & 0x003f0000) >> 16) +/* Produces a ALT_USB_GLOB_GPVNDCTL_REGADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GPVNDCTL_REGADDR_SET(value) (((value) << 16) & 0x003f0000) + +/* + * Field : Register Write - regwr + * + * Set this bit for register writes, and clear it for register reads. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:--------------- + * ALT_USB_GLOB_GPVNDCTL_REGWR_E_RD | 0x0 | Register Write + * ALT_USB_GLOB_GPVNDCTL_REGWR_E_WR | 0x1 | Register Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_REGWR + * + * Register Write + */ +#define ALT_USB_GLOB_GPVNDCTL_REGWR_E_RD 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_REGWR + * + * Register Write + */ +#define ALT_USB_GLOB_GPVNDCTL_REGWR_E_WR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGWR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGWR_MSB 22 +/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGWR_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGWR register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_REGWR_SET_MSK 0x00400000 +/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGWR register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_REGWR_CLR_MSK 0xffbfffff +/* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_REGWR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GPVNDCTL_REGWR field value from a register. */ +#define ALT_USB_GLOB_GPVNDCTL_REGWR_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_USB_GLOB_GPVNDCTL_REGWR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GPVNDCTL_REGWR_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : New Register Request - newregreq + * + * The application sets this bit for a new vendor controlaccess. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------------------- + * ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_INACT | 0x0 | New Register Request not active + * ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_ACT | 0x1 | New Register Request active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_NEWREGREQ + * + * New Register Request not active + */ +#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_NEWREGREQ + * + * New Register Request active + */ +#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */ +#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */ +#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_MSB 25 +/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */ +#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_SET_MSK 0x02000000 +/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_CLR_MSK 0xfdffffff +/* The reset value of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */ +#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ field value from a register. */ +#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : VStatus Busy - vstsbsy + * + * The core sets this bit when the vendor control access is in progress and clears + * this bit when done. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------- + * ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_INACT | 0x0 | VStatus Busy inactive + * ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_ACT | 0x1 | VStatus Busy active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSBSY + * + * VStatus Busy inactive + */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSBSY + * + * VStatus Busy active + */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_MSB 26 +/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GPVNDCTL_VSTSBSY field value from a register. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : VStatus Done - vstsdone + * + * The core sets this bit when the vendor control access isdone. This bit is + * cleared by the core when the application sets the New Register Request bit (bit + * 25). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------- + * ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_INACT | 0x0 | VStatus Done inactive + * ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_ACT | 0x1 | VStatus Done active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSDONE + * + * VStatus Done inactive + */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSDONE + * + * VStatus Done active + */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_MSB 27 +/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GPVNDCTL_VSTSDONE field value from a register. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Disable ULPI Drivers - disulpidrvr + * + * The application sets this bit when it has finished processing the ULPI Carkit + * Interrupt (GINTSTS.ULPICKINT). When Set, the otg core disables drivers for + * output signals and masks input signal for the ULPI interface. otg clears this + * bit before enabling the ULPI interface. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------- + * ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_END | 0x0 | ULPI ouput signals + * ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_DISD | 0x1 | Disable ULPI ouput signals + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR + * + * ULPI ouput signals + */ +#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_END 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR + * + * Disable ULPI ouput signals + */ +#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_DISD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value. */ +#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */ +#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR field value from a register. */ +#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GPVNDCTL. + */ +struct ALT_USB_GLOB_GPVNDCTL_s +{ + uint32_t regdata : 8; /* Register Data */ + uint32_t vctrl : 8; /* UTMI+ Vendor Control Register Address */ + uint32_t regaddr : 6; /* Register Address */ + uint32_t regwr : 1; /* Register Write */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t newregreq : 1; /* New Register Request */ + const uint32_t vstsbsy : 1; /* VStatus Busy */ + const uint32_t vstsdone : 1; /* VStatus Done */ + uint32_t : 3; /* *UNDEFINED* */ + const uint32_t disulpidrvr : 1; /* Disable ULPI Drivers */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GPVNDCTL. */ +typedef volatile struct ALT_USB_GLOB_GPVNDCTL_s ALT_USB_GLOB_GPVNDCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GPVNDCTL register from the beginning of the component. */ +#define ALT_USB_GLOB_GPVNDCTL_OFST 0x34 +/* The address of the ALT_USB_GLOB_GPVNDCTL register. */ +#define ALT_USB_GLOB_GPVNDCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GPVNDCTL_OFST)) + +/* + * Register : General Purpose Input Output Register - ggpio + * + * The application can use this register for general purpose input/output ports or + * for debugging. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [15:0] | R | 0x0 | General Purpose Input + * [31:16] | RW | 0x0 | General Purpose Output + * + */ +/* + * Field : General Purpose Input - gpi + * + * This field's read value reflects the gp_i[15:0] core input value. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GGPIO_GPI register field. */ +#define ALT_USB_GLOB_GGPIO_GPI_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GGPIO_GPI register field. */ +#define ALT_USB_GLOB_GGPIO_GPI_MSB 15 +/* The width in bits of the ALT_USB_GLOB_GGPIO_GPI register field. */ +#define ALT_USB_GLOB_GGPIO_GPI_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_GGPIO_GPI register field value. */ +#define ALT_USB_GLOB_GGPIO_GPI_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_GGPIO_GPI register field value. */ +#define ALT_USB_GLOB_GGPIO_GPI_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_GGPIO_GPI register field. */ +#define ALT_USB_GLOB_GGPIO_GPI_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GGPIO_GPI field value from a register. */ +#define ALT_USB_GLOB_GGPIO_GPI_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_GGPIO_GPI register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GGPIO_GPI_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : General Purpose Output - gpo + * + * This field is driven as an output from the core, gp_o[15:0]. The application can + * program this field to determine the corresponding value on the gp_o[15:0] + * output. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GGPIO_GPO register field. */ +#define ALT_USB_GLOB_GGPIO_GPO_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GGPIO_GPO register field. */ +#define ALT_USB_GLOB_GGPIO_GPO_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GGPIO_GPO register field. */ +#define ALT_USB_GLOB_GGPIO_GPO_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_GGPIO_GPO register field value. */ +#define ALT_USB_GLOB_GGPIO_GPO_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_USB_GLOB_GGPIO_GPO register field value. */ +#define ALT_USB_GLOB_GGPIO_GPO_CLR_MSK 0x0000ffff +/* The reset value of the ALT_USB_GLOB_GGPIO_GPO register field. */ +#define ALT_USB_GLOB_GGPIO_GPO_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GGPIO_GPO field value from a register. */ +#define ALT_USB_GLOB_GGPIO_GPO_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_USB_GLOB_GGPIO_GPO register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GGPIO_GPO_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GGPIO. + */ +struct ALT_USB_GLOB_GGPIO_s +{ + const uint32_t gpi : 16; /* General Purpose Input */ + uint32_t gpo : 16; /* General Purpose Output */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GGPIO. */ +typedef volatile struct ALT_USB_GLOB_GGPIO_s ALT_USB_GLOB_GGPIO_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GGPIO register from the beginning of the component. */ +#define ALT_USB_GLOB_GGPIO_OFST 0x38 +/* The address of the ALT_USB_GLOB_GGPIO register. */ +#define ALT_USB_GLOB_GGPIO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GGPIO_OFST)) + +/* + * Register : User ID Register - guid + * + * This is a read/write register containing the User ID. This register can be used + * in the following ways: + * + * * To store the version or revision of your system + * + * * To store hardware configurations that are outside the otg core + * + * As a scratch register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------ + * [31:0] | RW | 0x12345678 | User ID + * + */ +/* + * Field : User ID - guid + * + * Application-programmable ID field. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUID_GUID register field. */ +#define ALT_USB_GLOB_GUID_GUID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUID_GUID register field. */ +#define ALT_USB_GLOB_GUID_GUID_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GUID_GUID register field. */ +#define ALT_USB_GLOB_GUID_GUID_WIDTH 32 +/* The mask used to set the ALT_USB_GLOB_GUID_GUID register field value. */ +#define ALT_USB_GLOB_GUID_GUID_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_GLOB_GUID_GUID register field value. */ +#define ALT_USB_GLOB_GUID_GUID_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_GLOB_GUID_GUID register field. */ +#define ALT_USB_GLOB_GUID_GUID_RESET 0x12345678 +/* Extracts the ALT_USB_GLOB_GUID_GUID field value from a register. */ +#define ALT_USB_GLOB_GUID_GUID_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_GLOB_GUID_GUID register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GUID_GUID_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GUID. + */ +struct ALT_USB_GLOB_GUID_s +{ + uint32_t guid : 32; /* User ID */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GUID. */ +typedef volatile struct ALT_USB_GLOB_GUID_s ALT_USB_GLOB_GUID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GUID register from the beginning of the component. */ +#define ALT_USB_GLOB_GUID_OFST 0x3c +/* The address of the ALT_USB_GLOB_GUID register. */ +#define ALT_USB_GLOB_GUID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GUID_OFST)) + +/* + * Register : Synopsys ID Register - gsnpsid + * + * This read-only register contains the release number of the core being used. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:-----------|:------------ + * [31:0] | R | 0x4f54293a | Synopsys ID + * + */ +/* + * Field : Synopsys ID - gsnpsid + * + * Release number of the otg core being used is currently OTG 2.93a + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */ +#define ALT_USB_GLOB_GSNPSID_GSNPSID_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */ +#define ALT_USB_GLOB_GSNPSID_GSNPSID_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */ +#define ALT_USB_GLOB_GSNPSID_GSNPSID_WIDTH 32 +/* The mask used to set the ALT_USB_GLOB_GSNPSID_GSNPSID register field value. */ +#define ALT_USB_GLOB_GSNPSID_GSNPSID_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_GLOB_GSNPSID_GSNPSID register field value. */ +#define ALT_USB_GLOB_GSNPSID_GSNPSID_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */ +#define ALT_USB_GLOB_GSNPSID_GSNPSID_RESET 0x4f54293a +/* Extracts the ALT_USB_GLOB_GSNPSID_GSNPSID field value from a register. */ +#define ALT_USB_GLOB_GSNPSID_GSNPSID_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_GLOB_GSNPSID_GSNPSID register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GSNPSID_GSNPSID_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GSNPSID. + */ +struct ALT_USB_GLOB_GSNPSID_s +{ + const uint32_t gsnpsid : 32; /* Synopsys ID */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GSNPSID. */ +typedef volatile struct ALT_USB_GLOB_GSNPSID_s ALT_USB_GLOB_GSNPSID_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GSNPSID register from the beginning of the component. */ +#define ALT_USB_GLOB_GSNPSID_OFST 0x40 +/* The address of the ALT_USB_GLOB_GSNPSID register. */ +#define ALT_USB_GLOB_GSNPSID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GSNPSID_OFST)) + +/* + * Register : User HW Config1 Register - ghwcfg1 + * + * This register contains the logical endpoint direction(s). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------- + * [31:0] | R | 0x0 | Endpoint Direction + * + */ +/* + * Field : Endpoint Direction - ghwcfg1 + * + * This 32-bit field uses two bits per endpoint to determine the endpoint + * direction. + * + * Endpoint + * + * * Bits [31:30]: Endpoint 15 direction + * + * * Bits [29:28]: Endpoint 14 direction + * + * ... + * + * * Bits [3:2]: Endpoint 1 direction + * + * * Bits[1:0]: Endpoint 0 direction (always BIDIR) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------- + * ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_BDIR | 0x0 | BIDIR (IN and OUT) endpoint + * ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_INENDPT | 0x1 | IN endpoint + * ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_OUTENDPT | 0x2 | OUT endpoint + * ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_RSVD | 0x3 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1 + * + * BIDIR (IN and OUT) endpoint + */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_BDIR 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1 + * + * IN endpoint + */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_INENDPT 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1 + * + * OUT endpoint + */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_OUTENDPT 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1 + * + * Reserved + */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_RSVD 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_WIDTH 32 +/* The mask used to set the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value. */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value. */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG1_GHWCFG1 field value from a register. */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GHWCFG1. + */ +struct ALT_USB_GLOB_GHWCFG1_s +{ + const uint32_t ghwcfg1 : 32; /* Endpoint Direction */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GHWCFG1. */ +typedef volatile struct ALT_USB_GLOB_GHWCFG1_s ALT_USB_GLOB_GHWCFG1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GHWCFG1 register from the beginning of the component. */ +#define ALT_USB_GLOB_GHWCFG1_OFST 0x44 +/* The address of the ALT_USB_GLOB_GHWCFG1 register. */ +#define ALT_USB_GLOB_GHWCFG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG1_OFST)) + +/* + * Register : User HW Config2 Register - ghwcfg2 + * + * This register contains configuration options. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------------------- + * [2:0] | R | 0x0 | Mode of Operation + * [4:3] | R | 0x2 | Architecture + * [5] | R | 0x0 | Point-to-Point + * [7:6] | R | 0x2 | High Speed PHY Interface Type + * [9:8] | R | 0x0 | Full Speed PHY Interface Type + * [13:10] | R | 0xf | Number of Device Endpoints + * [17:14] | R | 0xf | Number of Host Channels + * [18] | R | 0x1 | Periodic OUT Channels Supported in Host Mode + * [19] | R | 0x1 | Dynamic FIFO Sizing Enabled + * [20] | R | 0x0 | Multi Processor Interrupt Enabled + * [21] | ??? | 0x0 | *UNDEFINED* + * [23:22] | R | 0x2 | Non Periodic Request Queue Depth + * [25:24] | R | 0x0 | Host Mode Periodic Request Queue Depth + * [30:26] | R | 0x8 | Device Mode IN Token Sequence Learning Queue Depth + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Mode of Operation - otgmode + * + * HNP- and SRP-Capable OTG (Device and Host). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_HNPSRP | 0x0 | HNP- and SRP-Capable OTG (Host & Device + * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPOTG | 0x1 | SRP-Capable OTG (Host & Device) + * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NHNPNSRP | 0x2 | Non-HNP and Non-SRP Capable OTG (Host & Device) + * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPD | 0x3 | SRP-Capable Device + * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGD | 0x4 | Non-OTG Device + * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPH | 0x5 | SRP-Capable Host + * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGH | 0x6 | Non-OTG Host + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD + * + * HNP- and SRP-Capable OTG (Host & Device + */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_HNPSRP 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD + * + * SRP-Capable OTG (Host & Device) + */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPOTG 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD + * + * Non-HNP and Non-SRP Capable OTG (Host & Device) + */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NHNPNSRP 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD + * + * SRP-Capable Device + */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPD 0x3 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD + * + * Non-OTG Device + */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGD 0x4 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD + * + * SRP-Capable Host + */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPH 0x5 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD + * + * Non-OTG Host + */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGH 0x6 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_MSB 2 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_WIDTH 3 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_OTGMOD register field value. */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_SET_MSK 0x00000007 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_OTGMOD register field value. */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_CLR_MSK 0xfffffff8 +/* The reset value of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG2_OTGMOD field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_GET(value) (((value) & 0x00000007) >> 0) +/* Produces a ALT_USB_GLOB_GHWCFG2_OTGMOD register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_OTGMOD_SET(value) (((value) << 0) & 0x00000007) + +/* + * Field : Architecture - otgarch + * + * DMA Architecture. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------- + * ALT_USB_GLOB_GHWCFG2_OTGARCH_E_DMAMOD | 0x2 | Internal DMA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGARCH + * + * Internal DMA + */ +#define ALT_USB_GLOB_GHWCFG2_OTGARCH_E_DMAMOD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */ +#define ALT_USB_GLOB_GHWCFG2_OTGARCH_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */ +#define ALT_USB_GLOB_GHWCFG2_OTGARCH_MSB 4 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */ +#define ALT_USB_GLOB_GHWCFG2_OTGARCH_WIDTH 2 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_OTGARCH register field value. */ +#define ALT_USB_GLOB_GHWCFG2_OTGARCH_SET_MSK 0x00000018 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_OTGARCH register field value. */ +#define ALT_USB_GLOB_GHWCFG2_OTGARCH_CLR_MSK 0xffffffe7 +/* The reset value of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */ +#define ALT_USB_GLOB_GHWCFG2_OTGARCH_RESET 0x2 +/* Extracts the ALT_USB_GLOB_GHWCFG2_OTGARCH field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_OTGARCH_GET(value) (((value) & 0x00000018) >> 3) +/* Produces a ALT_USB_GLOB_GHWCFG2_OTGARCH register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_OTGARCH_SET(value) (((value) << 3) & 0x00000018) + +/* + * Field : Point-to-Point - singpnt + * + * Single Point Only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------ + * ALT_USB_GLOB_GHWCFG2_SINGPNT_E_SINGLEPOINT | 0x1 | Single-point applicatio + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_SINGPNT + * + * Single-point applicatio + */ +#define ALT_USB_GLOB_GHWCFG2_SINGPNT_E_SINGLEPOINT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */ +#define ALT_USB_GLOB_GHWCFG2_SINGPNT_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */ +#define ALT_USB_GLOB_GHWCFG2_SINGPNT_MSB 5 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */ +#define ALT_USB_GLOB_GHWCFG2_SINGPNT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_SINGPNT register field value. */ +#define ALT_USB_GLOB_GHWCFG2_SINGPNT_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_SINGPNT register field value. */ +#define ALT_USB_GLOB_GHWCFG2_SINGPNT_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */ +#define ALT_USB_GLOB_GHWCFG2_SINGPNT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG2_SINGPNT field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_SINGPNT_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_GLOB_GHWCFG2_SINGPNT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_SINGPNT_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : High Speed PHY Interface Type - hsphytype + * + * Specifies the High Speed PHY in use. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------- + * ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_NOHS | 0x0 | High-Speed interface not supported + * ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_ULPI | 0x2 | ULPI + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_HSPHYTYPE + * + * High-Speed interface not supported + */ +#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_NOHS 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_HSPHYTYPE + * + * ULPI + */ +#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_ULPI 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_MSB 7 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value. */ +#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_SET_MSK 0x000000c0 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value. */ +#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_CLR_MSK 0xffffff3f +/* The reset value of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_RESET 0x2 +/* Extracts the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_GET(value) (((value) & 0x000000c0) >> 6) +/* Produces a ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_SET(value) (((value) << 6) & 0x000000c0) + +/* + * Field : Full Speed PHY Interface Type - fsphytype + * + * Specifies the Full Speed PHY in use. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_E_FULLSPEED | 0x2 | ULPI Type + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_FSPHYTYPE + * + * ULPI Type + */ +#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_E_FULLSPEED 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_MSB 9 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value. */ +#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_SET_MSK 0x00000300 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value. */ +#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_CLR_MSK 0xfffffcff +/* The reset value of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_GET(value) (((value) & 0x00000300) >> 8) +/* Produces a ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_SET(value) (((value) << 8) & 0x00000300) + +/* + * Field : Number of Device Endpoints - numdeveps + * + * The number of endpoints is 1 to 15 in Device mode in addition to control + * endpoint 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------- + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 0 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 1 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 2 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 3 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 4 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 5 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 6 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 7 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 8 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 9 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 10 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 11 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 12 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 13 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 14 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS + * + * End point 15 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_MSB 13 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value. */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_SET_MSK 0x00003c00 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value. */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_CLR_MSK 0xffffc3ff +/* The reset value of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_RESET 0xf +/* Extracts the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_GET(value) (((value) & 0x00003c00) >> 10) +/* Produces a ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_SET(value) (((value) << 10) & 0x00003c00) + +/* + * Field : Number of Host Channels - numhstchnl + * + * Indicates the number of host channels supported by the core in Host mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------- + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH0 | 0x0 | Host Channel 1 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH1 | 0x1 | Host Channel 2 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH2 | 0x2 | Host Channel 3 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH3 | 0x3 | Host Channel 4 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH4 | 0x4 | Host Channel 5 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH5 | 0x5 | Host Channel 6 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH6 | 0x6 | Host Channel 7 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH7 | 0x7 | Host Channel 8 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH8 | 0x8 | Host Channel 9 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH9 | 0x9 | Host Channel 10 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH10 | 0xa | Host Channel 11 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH11 | 0xb | Host Channel 12 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH12 | 0xc | Host Channel 13 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH13 | 0xd | Host Channel 14 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH14 | 0xe | Host Channel 15 + * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH15 | 0xf | Host Channel 16 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 1 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH0 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 2 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH1 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 3 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH2 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 4 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH3 0x3 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 5 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH4 0x4 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 6 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH5 0x5 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 7 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH6 0x6 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 8 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH7 0x7 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 9 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH8 0x8 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 10 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH9 0x9 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 11 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH10 0xa +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 12 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH11 0xb +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 13 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH12 0xc +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 14 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH13 0xd +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 15 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH14 0xe +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL + * + * Host Channel 16 + */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_MSB 17 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value. */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_SET_MSK 0x0003c000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value. */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_CLR_MSK 0xfffc3fff +/* The reset value of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_RESET 0xf +/* Extracts the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_GET(value) (((value) & 0x0003c000) >> 14) +/* Produces a ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_SET(value) (((value) << 14) & 0x0003c000) + +/* + * Field : Periodic OUT Channels Supported in Host Mode - periosupport + * + * Feature supported. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_E_END | 0x1 | Periodic OUT Channels Supported in Host Mode + * : | | Supported + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT + * + * Periodic OUT Channels Supported in Host Mode Supported + */ +#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_MSB 18 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value. */ +#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_SET_MSK 0x00040000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value. */ +#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_CLR_MSK 0xfffbffff +/* The reset value of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : Dynamic FIFO Sizing Enabled - dynfifosizing + * + * Feature supported. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_E_END | 0x1 | Dynamic FIFO Sizing Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING + * + * Dynamic FIFO Sizing Enabled + */ +#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */ +#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */ +#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_MSB 19 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */ +#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value. */ +#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_SET_MSK 0x00080000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value. */ +#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */ +#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : Multi Processor Interrupt Enabled - multiprocintrpt + * + * Not implemented. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------------- + * ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_E_DISD | 0x0 | No Multi Processor Interrupt Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT + * + * No Multi Processor Interrupt Enabled + */ +#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */ +#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */ +#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_MSB 20 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */ +#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value. */ +#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value. */ +#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */ +#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Non Periodic Request Queue Depth - nptxqdepth + * + * Specifies the Non-periodic Request Queue depth, the maximum number of packets + * that can reside in the Non-periodic TxFIFO. + * + * In Device mode, the queue is used only in Shared FIFO Mode (Enable Dedicated + * Transmit FIFO for device IN Endpoints? =No). In this mode, there is one entry in + * the Non-periodic Request Queue for each packet in the Non-periodic TxFIFO. + * + * In Host mode, this queue holds one entry corresponding to each IN or OUT + * nonperiodic request. This queue is seven bits wide. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------ + * ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_TWO | 0x0 | Que size 2 + * ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_FOUR | 0x1 | Que size 4 + * ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_EIGHT | 0x2 | Que size 8 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH + * + * Que size 2 + */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_TWO 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH + * + * Que size 4 + */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_FOUR 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH + * + * Que size 8 + */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_EIGHT 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_MSB 23 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_WIDTH 2 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value. */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_SET_MSK 0x00c00000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value. */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_CLR_MSK 0xff3fffff +/* The reset value of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_RESET 0x2 +/* Extracts the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_GET(value) (((value) & 0x00c00000) >> 22) +/* Produces a ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_SET(value) (((value) << 22) & 0x00c00000) + +/* + * Field : Host Mode Periodic Request Queue Depth - ptxqdepth + * + * Specifies the Host mode Periodic Request Queue depth.That is, the maximum number + * of packets that can reside in the Host Periodic TxFIFO. This queue holds one + * entry corresponding to each IN or OUT periodic request. This queue is 9 bits + * wide. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------- + * ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE2 | 0x0 | Que Depth 2 + * ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE4 | 0x1 | Que Depth 4 + * ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE8 | 0x2 | Que Depth 8 + * ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE16 | 0x3 | Que Depth 16 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH + * + * Que Depth 2 + */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE2 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH + * + * Que Depth 4 + */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE4 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH + * + * Que Depth 8 + */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE8 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH + * + * Que Depth 16 + */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE16 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_MSB 25 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_WIDTH 2 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value. */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_SET_MSK 0x03000000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value. */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_CLR_MSK 0xfcffffff +/* The reset value of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_GET(value) (((value) & 0x03000000) >> 24) +/* Produces a ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_SET(value) (((value) << 24) & 0x03000000) + +/* + * Field : Device Mode IN Token Sequence Learning Queue Depth - tknqdepth + * + * Range: 0 to 30. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_MSB 30 +/* The width in bits of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_WIDTH 5 +/* The mask used to set the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value. */ +#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_SET_MSK 0x7c000000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value. */ +#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_CLR_MSK 0x83ffffff +/* The reset value of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_RESET 0x8 +/* Extracts the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH field value from a register. */ +#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_GET(value) (((value) & 0x7c000000) >> 26) +/* Produces a ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_SET(value) (((value) << 26) & 0x7c000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GHWCFG2. + */ +struct ALT_USB_GLOB_GHWCFG2_s +{ + const uint32_t otgmode : 3; /* Mode of Operation */ + const uint32_t otgarch : 2; /* Architecture */ + const uint32_t singpnt : 1; /* Point-to-Point */ + const uint32_t hsphytype : 2; /* High Speed PHY Interface Type */ + const uint32_t fsphytype : 2; /* Full Speed PHY Interface Type */ + const uint32_t numdeveps : 4; /* Number of Device Endpoints */ + const uint32_t numhstchnl : 4; /* Number of Host Channels */ + const uint32_t periosupport : 1; /* Periodic OUT Channels Supported in Host Mode */ + const uint32_t dynfifosizing : 1; /* Dynamic FIFO Sizing Enabled */ + const uint32_t multiprocintrpt : 1; /* Multi Processor Interrupt Enabled */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t nptxqdepth : 2; /* Non Periodic Request Queue Depth */ + const uint32_t ptxqdepth : 2; /* Host Mode Periodic Request Queue Depth */ + const uint32_t tknqdepth : 5; /* Device Mode IN Token Sequence Learning Queue Depth */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GHWCFG2. */ +typedef volatile struct ALT_USB_GLOB_GHWCFG2_s ALT_USB_GLOB_GHWCFG2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GHWCFG2 register from the beginning of the component. */ +#define ALT_USB_GLOB_GHWCFG2_OFST 0x48 +/* The address of the ALT_USB_GLOB_GHWCFG2 register. */ +#define ALT_USB_GLOB_GHWCFG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG2_OFST)) + +/* + * Register : User HW Config3 Register - ghwcfg3 + * + * This register contains the configuration options. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [3:0] | R | 0x8 | Width of Transfer Size Counters + * [6:4] | R | 0x6 | Width of Packet Size Counters + * [7] | R | 0x1 | OTG Function Enabled + * [8] | R | 0x0 | I2C Selection + * [9] | R | 0x1 | Vendor Control Interface Suppor + * [10] | R | 0x0 | Optional Features Removed + * [11] | R | 0x0 | Reset Style for Clocked always Blocks in RTL + * [12] | R | 0x0 | OTG ADP Support + * [13] | R | 0x0 | OTG ENABLE HSIC + * [14] | R | 0x0 | OTG BC SUPPORT + * [15] | R | 0x0 | OTG ENABLE LPM + * [31:16] | R | 0x1f80 | DFIFO Depth + * + */ +/* + * Field : Width of Transfer Size Counters - xfersizewidth + * + * Width variable from 11 to 19 bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:--------------------------------------- + * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH11 | 0x0 | Width of Transfer Size Counter 11 bits + * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH12 | 0x1 | Width of Transfer Size Counter 12 bits + * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH13 | 0x2 | Width of Transfer Size Counter 13 bits + * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH14 | 0x3 | Width of Transfer Size Counter 14 bits + * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH15 | 0x4 | Width of Transfer Size Counter 15 bits + * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH16 | 0x5 | Width of Transfer Size Counter 16 bits + * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH17 | 0x6 | Width of Transfer Size Counter 17 bits + * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH18 | 0x7 | Width of Transfer Size Counter 18 bits + * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH19 | 0x8 | Width of Transfer Size Counter 19 bits + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH + * + * Width of Transfer Size Counter 11 bits + */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH11 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH + * + * Width of Transfer Size Counter 12 bits + */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH12 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH + * + * Width of Transfer Size Counter 13 bits + */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH13 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH + * + * Width of Transfer Size Counter 14 bits + */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH14 0x3 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH + * + * Width of Transfer Size Counter 15 bits + */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH15 0x4 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH + * + * Width of Transfer Size Counter 16 bits + */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH16 0x5 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH + * + * Width of Transfer Size Counter 17 bits + */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH17 0x6 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH + * + * Width of Transfer Size Counter 18 bits + */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH18 0x7 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH + * + * Width of Transfer Size Counter 19 bits + */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH19 0x8 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_MSB 3 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value. */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_SET_MSK 0x0000000f +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value. */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_RESET 0x8 +/* Extracts the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Width of Packet Size Counters - pktsizewidth + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------- + * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS4 | 0x0 | Width of Packet Size Counter 4 + * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS5 | 0x1 | Width of Packet Size Counter 5 + * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS6 | 0x2 | Width of Packet Size Counter 6 + * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS7 | 0x3 | Width of Packet Size Counter 7 + * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS8 | 0x4 | Width of Packet Size Counter 8 + * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS9 | 0x5 | Width of Packet Size Counter 9 + * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS10 | 0x6 | Width of Packet Size Counter 10 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH + * + * Width of Packet Size Counter 4 + */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS4 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH + * + * Width of Packet Size Counter 5 + */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS5 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH + * + * Width of Packet Size Counter 6 + */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS6 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH + * + * Width of Packet Size Counter 7 + */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS7 0x3 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH + * + * Width of Packet Size Counter 8 + */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS8 0x4 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH + * + * Width of Packet Size Counter 9 + */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS9 0x5 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH + * + * Width of Packet Size Counter 10 + */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS10 0x6 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_MSB 6 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_WIDTH 3 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value. */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_SET_MSK 0x00000070 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value. */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_CLR_MSK 0xffffff8f +/* The reset value of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_RESET 0x6 +/* Extracts the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_GET(value) (((value) & 0x00000070) >> 4) +/* Produces a ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_SET(value) (((value) << 4) & 0x00000070) + +/* + * Field : OTG Function Enabled - otgen + * + * HNP and SRP Capable OTG (Device and Host) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------ + * ALT_USB_GLOB_GHWCFG3_OTGEN_E_END | 0x1 | OTG Capable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_OTGEN + * + * OTG Capable + */ +#define ALT_USB_GLOB_GHWCFG3_OTGEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */ +#define ALT_USB_GLOB_GHWCFG3_OTGEN_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */ +#define ALT_USB_GLOB_GHWCFG3_OTGEN_MSB 7 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */ +#define ALT_USB_GLOB_GHWCFG3_OTGEN_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_OTGEN register field value. */ +#define ALT_USB_GLOB_GHWCFG3_OTGEN_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_OTGEN register field value. */ +#define ALT_USB_GLOB_GHWCFG3_OTGEN_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */ +#define ALT_USB_GLOB_GHWCFG3_OTGEN_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GHWCFG3_OTGEN field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_OTGEN_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_GLOB_GHWCFG3_OTGEN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_OTGEN_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : I2C Selection - i2cintsel + * + * I2C Interface not used. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_GLOB_GHWCFG3_I2CINTSEL_E_DISD | 0x0 | I2C Interface + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_I2CINTSEL + * + * I2C Interface + */ +#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */ +#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */ +#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_MSB 8 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */ +#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value. */ +#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value. */ +#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */ +#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG3_I2CINTSEL field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Vendor Control Interface Suppor - vndctlsupt + * + * ULPI PHY internal registers can be accessed by software using register + * reads/writes to otg + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------- + * ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_E_END | 0x1 | Vendor Control Interface is not available on the + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT + * + * Vendor Control Interface is not available on the + */ +#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */ +#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */ +#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_MSB 9 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */ +#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value. */ +#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value. */ +#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */ +#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Optional Features Removed - optfeature + * + * User ID register, GPIO interface ports, and SOF toggle and counter ports were + * removed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_GLOB_GHWCFG3_OPTFEATURE_E_DISD | 0x0 | No Optional features + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_OPTFEATURE + * + * No Optional features + */ +#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */ +#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */ +#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_MSB 10 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */ +#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value. */ +#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value. */ +#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */ +#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG3_OPTFEATURE field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Reset Style for Clocked always Blocks in RTL - rsttype + * + * Defines what reset type is used in the core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------------------------------- + * ALT_USB_GLOB_GHWCFG3_RSTTYPE_E_END | 0x0 | Asynchronous reset is used in the core + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_RSTTYPE + * + * Asynchronous reset is used in the core + */ +#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_E_END 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_MSB 11 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value. */ +#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value. */ +#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */ +#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG3_RSTTYPE field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : OTG ADP Support - adpsupport + * + * ADP logic support. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------- + * ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_E_END | 0x1 | ADP logic is present along with HSOTG controller + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_ADPSUPPORT + * + * ADP logic is present along with HSOTG controller + */ +#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_MSB 12 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value. */ +#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value. */ +#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : OTG ENABLE HSIC - hsicmode + * + * Supports HSIC and Non-HSIC Modes. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_GLOB_GHWCFG3_HSICMOD_E_DISD | 0x0 | Non-HSIC-capable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_HSICMOD + * + * Non-HSIC-capable + */ +#define ALT_USB_GLOB_GHWCFG3_HSICMOD_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */ +#define ALT_USB_GLOB_GHWCFG3_HSICMOD_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */ +#define ALT_USB_GLOB_GHWCFG3_HSICMOD_MSB 13 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */ +#define ALT_USB_GLOB_GHWCFG3_HSICMOD_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_HSICMOD register field value. */ +#define ALT_USB_GLOB_GHWCFG3_HSICMOD_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_HSICMOD register field value. */ +#define ALT_USB_GLOB_GHWCFG3_HSICMOD_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */ +#define ALT_USB_GLOB_GHWCFG3_HSICMOD_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG3_HSICMOD field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_HSICMOD_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_GLOB_GHWCFG3_HSICMOD register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_HSICMOD_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : OTG BC SUPPORT - bcsupport + * + * Battery Charger Support. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:--------------------------- + * ALT_USB_GLOB_GHWCFG3_BCSUPPORT_E_DISD | 0x0 | No Battery Charger Support + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_BCSUPPORT + * + * No Battery Charger Support + */ +#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_MSB 14 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value. */ +#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value. */ +#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */ +#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG3_BCSUPPORT field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : OTG ENABLE LPM - lpmmode + * + * LPM Mode Enabled/Disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_GLOB_GHWCFG3_LPMMOD_E_DISD | 0x0 | LPM disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_LPMMOD + * + * LPM disabled + */ +#define ALT_USB_GLOB_GHWCFG3_LPMMOD_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */ +#define ALT_USB_GLOB_GHWCFG3_LPMMOD_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */ +#define ALT_USB_GLOB_GHWCFG3_LPMMOD_MSB 15 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */ +#define ALT_USB_GLOB_GHWCFG3_LPMMOD_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_LPMMOD register field value. */ +#define ALT_USB_GLOB_GHWCFG3_LPMMOD_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_LPMMOD register field value. */ +#define ALT_USB_GLOB_GHWCFG3_LPMMOD_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */ +#define ALT_USB_GLOB_GHWCFG3_LPMMOD_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG3_LPMMOD field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_LPMMOD_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_GLOB_GHWCFG3_LPMMOD register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_LPMMOD_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : DFIFO Depth - dfifodepth + * + * DFIFO Depth. This value is in terms of 35-bit words. + * + * Minimum value is 32 + * + * Maximum value is 8192 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value. */ +#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value. */ +#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_CLR_MSK 0x0000ffff +/* The reset value of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */ +#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_RESET 0x1f80 +/* Extracts the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH field value from a register. */ +#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GHWCFG3. + */ +struct ALT_USB_GLOB_GHWCFG3_s +{ + const uint32_t xfersizewidth : 4; /* Width of Transfer Size Counters */ + const uint32_t pktsizewidth : 3; /* Width of Packet Size Counters */ + const uint32_t otgen : 1; /* OTG Function Enabled */ + const uint32_t i2cintsel : 1; /* I2C Selection */ + const uint32_t vndctlsupt : 1; /* Vendor Control Interface Suppor */ + const uint32_t optfeature : 1; /* Optional Features Removed */ + const uint32_t rsttype : 1; /* Reset Style for Clocked always Blocks in RTL */ + const uint32_t adpsupport : 1; /* OTG ADP Support */ + const uint32_t hsicmode : 1; /* OTG ENABLE HSIC */ + const uint32_t bcsupport : 1; /* OTG BC SUPPORT */ + const uint32_t lpmmode : 1; /* OTG ENABLE LPM */ + const uint32_t dfifodepth : 16; /* DFIFO Depth */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GHWCFG3. */ +typedef volatile struct ALT_USB_GLOB_GHWCFG3_s ALT_USB_GLOB_GHWCFG3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GHWCFG3 register from the beginning of the component. */ +#define ALT_USB_GLOB_GHWCFG3_OFST 0x4c +/* The address of the ALT_USB_GLOB_GHWCFG3 register. */ +#define ALT_USB_GLOB_GHWCFG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG3_OFST)) + +/* + * Register : User HW Config4 Register - ghwcfg4 + * + * This register contains the configuration options. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------------------------------ + * [3:0] | R | 0x0 | Number of Device Mode Periodic IN Endpoints + * [4] | R | 0x0 | Enable Partial Power Down + * [5] | R | 0x1 | Minimum AHB Frequency Less Than 60 MHz + * [6] | R | 0x0 | Enable Hibernation + * [13:7] | ??? | 0x0 | *UNDEFINED* + * [15:14] | R | 0x0 | UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width + * [19:16] | R | 0xf | Number of Device Mode Control Endpoints in Addition to Endpoint 0 + * [20] | R | 0x0 | Iddig Filter Enable + * [21] | R | 0x0 | Vbus Valid Filter Enabled + * [22] | R | 0x0 | a_valid Filter + * [23] | R | 0x0 | b_valid Filter + * [24] | R | 0x0 | Session End Filter + * [25] | R | 0x1 | Enable Dedicated Transmit FIFO for device IN Endpoints + * [29:26] | R | 0xf | Number of Device Mode IN Endpoints Including Control + * [30] | R | 0x1 | Scatter Gather DMA configuration + * [31] | R | 0x1 | Scatter Gather DMA + * + */ +/* + * Field : Number of Device Mode Periodic IN Endpoints - numdevperioeps + * + * The maximum number of device IN operations is 16 active at any time including + * endpoint 0, which is always present. This parameter determines the number of + * device mode Tx FIFOs to be instantiated. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_MSB 3 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value. */ +#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_SET_MSK 0x0000000f +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value. */ +#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_CLR_MSK 0xfffffff0 +/* The reset value of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_GET(value) (((value) & 0x0000000f) >> 0) +/* Produces a ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_SET(value) (((value) << 0) & 0x0000000f) + +/* + * Field : Enable Partial Power Down - partialpwrdn + * + * Specifies whether to enable power optimization. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_E_DISD | 0x0 | Partial Power Down disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN + * + * Partial Power Down disabled + */ +#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */ +#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */ +#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_MSB 4 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */ +#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value. */ +#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value. */ +#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */ +#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Minimum AHB Frequency Less Than 60 MHz - ahbfreq + * + * When the AHB frequency is less than 60 MHz, 4-deep clock-domain crossing sink + * and source buffers are instantiated between the MAC and the Packet FIFO + * Controller (PFC); otherwise, two-deep buffers are sufficient. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------------- + * ALT_USB_GLOB_GHWCFG4_AHBFREQ_E_END | 0x1 | Minimum AHB Frequency Less Than 60 MH + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_AHBFREQ + * + * Minimum AHB Frequency Less Than 60 MH + */ +#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */ +#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */ +#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_MSB 5 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */ +#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value. */ +#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value. */ +#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */ +#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GHWCFG4_AHBFREQ field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Enable Hibernation - hibernation + * + * Enables power saving mode hibernation. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_GLOB_GHWCFG4_HIBERNATION_E_DISD | 0x0 | Hibernation feature disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_HIBERNATION + * + * Hibernation feature disabled + */ +#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */ +#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */ +#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_MSB 6 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */ +#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value. */ +#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value. */ +#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */ +#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG4_HIBERNATION field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width - phydatawidth + * + * Uses a ULPI interface only. Hence only 8-bit setting is relevant. This setting + * should not matter since UTMI is not enabled. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_MSB 15 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_WIDTH 2 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value. */ +#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value. */ +#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */ +#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Number of Device Mode Control Endpoints in Addition to Endpoint 0 - numctleps + * + * Specifies the number of Device mode control endpoints in addition to control + * endpoint 0, which is always present. Range: 0-15. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------- + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 0 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 1 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 2 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 3 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 4 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 5 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 6 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 7 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 8 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 9 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 10 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 11 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 12 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 13 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 14 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS + * + * End point 15 + */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_MSB 19 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value. */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_SET_MSK 0x000f0000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value. */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_CLR_MSK 0xfff0ffff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_RESET 0xf +/* Extracts the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_GET(value) (((value) & 0x000f0000) >> 16) +/* Produces a ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_SET(value) (((value) << 16) & 0x000f0000) + +/* + * Field : Iddig Filter Enable - iddgfltr + * + * Specifies whether to add a filter on the iddig input from the PHY. This is not + * relevant since we only support ULPI and there is no iddig pin exposed to I/O + * pads. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------- + * ALT_USB_GLOB_GHWCFG4_IDDGFLTR_E_DISD | 0x0 | Iddig Filter Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_IDDGFLTR + * + * Iddig Filter Disabled + */ +#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_MSB 20 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value. */ +#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value. */ +#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG4_IDDGFLTR field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : Vbus Valid Filter Enabled - vbusvalidfltr + * + * Vbus Valid Filter Enabled (VBusValidFltr) 0: No filter 1: Filter(coreConsultant + * parameter: OTG_EN_VBUSVALID_FILTER) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------- + * ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_E_DISD | 0x0 | Vbus Valid Filter Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR + * + * Vbus Valid Filter Disabled + */ +#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_MSB 21 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value. */ +#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value. */ +#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : a_valid Filter - avalidfltr + * + * Specifies whether to add a filter on the b_valid input from the PHY. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------ + * ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_E_DISD | 0x0 | No filter + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_AVALIDFLTR + * + * No filter + */ +#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_MSB 22 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value. */ +#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_SET_MSK 0x00400000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value. */ +#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_CLR_MSK 0xffbfffff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : b_valid Filter - bvalidfltr + * + * Specifies whether to add a filter on the b_valid input from the PHY. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------ + * ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_E_DISD | 0x0 | No Filter + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_BVALIDFLTR + * + * No Filter + */ +#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_MSB 23 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value. */ +#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_SET_MSK 0x00800000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value. */ +#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_CLR_MSK 0xff7fffff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Session End Filter - sessendfltr + * + * Specifies whether to add a filter on the session_end input from the PHY. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------ + * ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_E_DISD | 0x0 | No filter + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_SESSENDFLTR + * + * No filter + */ +#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_E_DISD 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_MSB 24 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value. */ +#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_SET_MSK 0x01000000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value. */ +#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_CLR_MSK 0xfeffffff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */ +#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Enable Dedicated Transmit FIFO for device IN Endpoints - dedfifomode + * + * Specifies whether Dedicated Transmit FIFOs should be enabled in device mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------ + * ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_E_END | 0x1 | Dedicated Transmit FIFO Operation enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD + * + * Dedicated Transmit FIFO Operation enabled + */ +#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */ +#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */ +#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_MSB 25 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */ +#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value. */ +#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_SET_MSK 0x02000000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value. */ +#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_CLR_MSK 0xfdffffff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */ +#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : Number of Device Mode IN Endpoints Including Control - ineps + * + * Number of Device Mode IN Endpoints Including Control. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------- + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT1 | 0x0 | In Endpoint 1 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT2 | 0x1 | In Endpoint 2 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT3 | 0x2 | In Endpoint 3 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT4 | 0x3 | In Endpoint 4 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT5 | 0x4 | In Endpoint 5 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT6 | 0x5 | In Endpoint 6 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT7 | 0x6 | In Endpoint 7 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT8 | 0x7 | In Endpoint 8 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT9 | 0x8 | In Endpoint 9 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT10 | 0x9 | In Endpoint 10 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT11 | 0xa | In Endpoint 11 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT12 | 0xb | In Endpoint 12 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT13 | 0xc | In Endpoint 13 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT14 | 0xd | In Endpoint 14 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT15 | 0xe | In Endpoint 15 + * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT16 | 0xf | In Endpoint 16 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 1 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT1 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 2 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT2 0x1 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 3 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT3 0x2 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 4 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT4 0x3 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 5 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT5 0x4 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 6 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT6 0x5 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 7 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT7 0x6 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 8 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT8 0x7 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 9 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT9 0x8 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 10 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT10 0x9 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 11 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT11 0xa +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 12 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT12 0xb +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 13 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT13 0xc +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 14 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT14 0xd +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 15 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT15 0xe +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS + * + * In Endpoint 16 + */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT16 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_MSB 29 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_WIDTH 4 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_INEPS register field value. */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_SET_MSK 0x3c000000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_INEPS register field value. */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_CLR_MSK 0xc3ffffff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_RESET 0xf +/* Extracts the ALT_USB_GLOB_GHWCFG4_INEPS field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_GET(value) (((value) & 0x3c000000) >> 26) +/* Produces a ALT_USB_GLOB_GHWCFG4_INEPS register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_INEPS_SET(value) (((value) << 26) & 0x3c000000) + +/* + * Field : Scatter Gather DMA configuration - dma_configuration + * + * Selects bewteen scatter and nonscatter configuration + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------- + * ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_NONSCATTER | 0x0 | Non-Scatter/Gather DMA configuration + * ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_SCATTER | 0x1 | Scatter/Gather DMA configuration + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA_CFG + * + * Non-Scatter/Gather DMA configuration + */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_NONSCATTER 0x0 +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA_CFG + * + * Scatter/Gather DMA configuration + */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_SCATTER 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_MSB 30 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GHWCFG4_DMA_CFG field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Scatter Gather DMA - dma + * + * Enable descriptor based scatter/gather DMA. When enabled, DMA operations will + * be serviced with descriptor based scatter/gather DMA + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:---------------------- + * ALT_USB_GLOB_GHWCFG4_DMA_E_END | 0x1 | Dynamic configuration + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA + * + * Dynamic configuration + */ +#define ALT_USB_GLOB_GHWCFG4_DMA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DMA register field. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DMA register field. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GHWCFG4_DMA register field. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_WIDTH 1 +/* The mask used to set the ALT_USB_GLOB_GHWCFG4_DMA register field value. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DMA register field value. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_GLOB_GHWCFG4_DMA register field. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_RESET 0x1 +/* Extracts the ALT_USB_GLOB_GHWCFG4_DMA field value from a register. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_GLOB_GHWCFG4_DMA register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GHWCFG4_DMA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GHWCFG4. + */ +struct ALT_USB_GLOB_GHWCFG4_s +{ + const uint32_t numdevperioeps : 4; /* Number of Device Mode Periodic IN Endpoints */ + const uint32_t partialpwrdn : 1; /* Enable Partial Power Down */ + const uint32_t ahbfreq : 1; /* Minimum AHB Frequency Less Than 60 MHz */ + const uint32_t hibernation : 1; /* Enable Hibernation */ + uint32_t : 7; /* *UNDEFINED* */ + const uint32_t phydatawidth : 2; /* UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width */ + const uint32_t numctleps : 4; /* Number of Device Mode Control Endpoints in Addition to Endpoint 0 */ + const uint32_t iddgfltr : 1; /* Iddig Filter Enable */ + const uint32_t vbusvalidfltr : 1; /* Vbus Valid Filter Enabled */ + const uint32_t avalidfltr : 1; /* a_valid Filter */ + const uint32_t bvalidfltr : 1; /* b_valid Filter */ + const uint32_t sessendfltr : 1; /* Session End Filter */ + const uint32_t dedfifomode : 1; /* Enable Dedicated Transmit FIFO for device IN Endpoints */ + const uint32_t ineps : 4; /* Number of Device Mode IN Endpoints Including Control */ + const uint32_t dma_configuration : 1; /* Scatter Gather DMA configuration */ + const uint32_t dma : 1; /* Scatter Gather DMA */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GHWCFG4. */ +typedef volatile struct ALT_USB_GLOB_GHWCFG4_s ALT_USB_GLOB_GHWCFG4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GHWCFG4 register from the beginning of the component. */ +#define ALT_USB_GLOB_GHWCFG4_OFST 0x50 +/* The address of the ALT_USB_GLOB_GHWCFG4 register. */ +#define ALT_USB_GLOB_GHWCFG4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG4_OFST)) + +/* + * Register : DFIFO Software Config Register - gdfifocfg + * + * Specifies whether Dedicated Transmit FIFOs should be enabled in device mode. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------- + * [15:0] | RW | 0x2000 | DFIFO Software Config + * [31:16] | RW | 0x1f80 | End Point Info Basr Addr + * + */ +/* + * Field : DFIFO Software Config - gdfifocfg + * + * This field is for dynamic programming of the DFIFO Size. This value takes effect + * only when the application programs a non zero value to this register. The otg + * core does not have any corrective logic if the FIFO sizes are programmed + * incorrectly. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */ +#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */ +#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_MSB 15 +/* The width in bits of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */ +#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value. */ +#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value. */ +#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */ +#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG field value from a register. */ +#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : End Point Info Basr Addr - epinfobaseaddr + * + * This field provides the start address of the EP info controller. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */ +#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */ +#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_MSB 31 +/* The width in bits of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */ +#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value. */ +#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value. */ +#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_CLR_MSK 0x0000ffff +/* The reset value of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */ +#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_RESET 0x1f80 +/* Extracts the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR field value from a register. */ +#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_GDFIFOCFG. + */ +struct ALT_USB_GLOB_GDFIFOCFG_s +{ + uint32_t gdfifocfg : 16; /* DFIFO Software Config */ + uint32_t epinfobaseaddr : 16; /* End Point Info Basr Addr */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_GDFIFOCFG. */ +typedef volatile struct ALT_USB_GLOB_GDFIFOCFG_s ALT_USB_GLOB_GDFIFOCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_GDFIFOCFG register from the beginning of the component. */ +#define ALT_USB_GLOB_GDFIFOCFG_OFST 0x5c +/* The address of the ALT_USB_GLOB_GDFIFOCFG register. */ +#define ALT_USB_GLOB_GDFIFOCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GDFIFOCFG_OFST)) + +/* + * Register : Host Periodic Transmit FIFO Size Register - hptxfsiz + * + * This register holds the size and the memory start address of the Periodic TxFIFO + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:----------------------------------- + * [14:0] | RW | 0x4000 | Host Periodic TxFIFO Start Address + * [15] | ??? | 0x0 | *UNDEFINED* + * [29:16] | RW | 0x2000 | Host Periodic TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Host Periodic TxFIFO Start Address - ptxfstaddr + * + * The power-on reset value of this register is the sum of the Largest Rx Data FIFO + * Depth and Largest Non-periodic Tx Data FIFO. Programmed values must not exceed + * the power-on value + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_MSB 14 +/* The width in bits of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_WIDTH 15 +/* The mask used to set the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_SET_MSK 0x00007fff +/* The mask used to clear the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_CLR_MSK 0xffff8000 +/* The reset value of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_RESET 0x4000 +/* Extracts the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0) +/* Produces a ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff) + +/* + * Field : Host Periodic TxFIFO Depth - ptxfsize + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 1024 + * + * The power-on reset value of this register is specified as the 1024. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_MSB 29 +/* The width in bits of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE field value from a register. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value suitable for setting the register. */ +#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_HPTXFSIZ. + */ +struct ALT_USB_GLOB_HPTXFSIZ_s +{ + uint32_t ptxfstaddr : 15; /* Host Periodic TxFIFO Start Address */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t ptxfsize : 14; /* Host Periodic TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_HPTXFSIZ. */ +typedef volatile struct ALT_USB_GLOB_HPTXFSIZ_s ALT_USB_GLOB_HPTXFSIZ_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_HPTXFSIZ register from the beginning of the component. */ +#define ALT_USB_GLOB_HPTXFSIZ_OFST 0x100 +/* The address of the ALT_USB_GLOB_HPTXFSIZ register. */ +#define ALT_USB_GLOB_HPTXFSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_HPTXFSIZ_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 1 - dieptxf1 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [14:0] | RW | 0x4000 | IN Endpoint FIFOn Transmit RAM Start Address + * [15] | ??? | 0x0 | *UNDEFINED* + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 1. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_MSB 14 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_WIDTH 15 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_SET_MSK 0x00007fff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_CLR_MSK 0xffff8000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_RESET 0x4000 +/* Extracts the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF1. + */ +struct ALT_USB_GLOB_DIEPTXF1_s +{ + uint32_t inepntxfstaddr : 15; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF1. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF1_s ALT_USB_GLOB_DIEPTXF1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF1 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF1_OFST 0x104 +/* The address of the ALT_USB_GLOB_DIEPTXF1 register. */ +#define ALT_USB_GLOB_DIEPTXF1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF1_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 2 - dieptxf2 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for instantiated IN endpoint FIFO. For IN endpoint FIFO 0 + * use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [14:0] | RW | 0x6000 | IN Endpoint FIFOn Transmit RAM Start Address + * [15] | ??? | 0x0 | *UNDEFINED* + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 2. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_MSB 14 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_WIDTH 15 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_SET_MSK 0x00007fff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_CLR_MSK 0xffff8000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_RESET 0x6000 +/* Extracts the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF2. + */ +struct ALT_USB_GLOB_DIEPTXF2_s +{ + uint32_t inepntxfstaddr : 15; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF2. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF2_s ALT_USB_GLOB_DIEPTXF2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF2 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF2_OFST 0x108 +/* The address of the ALT_USB_GLOB_DIEPTXF2 register. */ +#define ALT_USB_GLOB_DIEPTXF2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF2_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 3 - dieptxf3 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for instantiated IN endpoint FIFO. For IN endpoint FIFO 0 + * use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0x8000 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 3. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_RESET 0x8000 +/* Extracts the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words.Minimum value is 16Maximum value is 8192 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF3. + */ +struct ALT_USB_GLOB_DIEPTXF3_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF3. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF3_s ALT_USB_GLOB_DIEPTXF3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF3 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF3_OFST 0x10c +/* The address of the ALT_USB_GLOB_DIEPTXF3 register. */ +#define ALT_USB_GLOB_DIEPTXF3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF3_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 4 - dieptxf4 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0xa000 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 4. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_RESET 0xa000 +/* Extracts the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF4. + */ +struct ALT_USB_GLOB_DIEPTXF4_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF4. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF4_s ALT_USB_GLOB_DIEPTXF4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF4 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF4_OFST 0x110 +/* The address of the ALT_USB_GLOB_DIEPTXF4 register. */ +#define ALT_USB_GLOB_DIEPTXF4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF4_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 5 - dieptxf5 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0xc000 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 5. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_RESET 0xc000 +/* Extracts the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF5. + */ +struct ALT_USB_GLOB_DIEPTXF5_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF5. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF5_s ALT_USB_GLOB_DIEPTXF5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF5 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF5_OFST 0x114 +/* The address of the ALT_USB_GLOB_DIEPTXF5 register. */ +#define ALT_USB_GLOB_DIEPTXF5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF5_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 6 - dieptxf6 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0xe000 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 6. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_RESET 0xe000 +/* Extracts the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF6. + */ +struct ALT_USB_GLOB_DIEPTXF6_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF6. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF6_s ALT_USB_GLOB_DIEPTXF6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF6 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF6_OFST 0x118 +/* The address of the ALT_USB_GLOB_DIEPTXF6 register. */ +#define ALT_USB_GLOB_DIEPTXF6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF6_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 7 - dieptxf7 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0x0 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 7. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF7. + */ +struct ALT_USB_GLOB_DIEPTXF7_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF7. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF7_s ALT_USB_GLOB_DIEPTXF7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF7 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF7_OFST 0x11c +/* The address of the ALT_USB_GLOB_DIEPTXF7 register. */ +#define ALT_USB_GLOB_DIEPTXF7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF7_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 8 - dieptxf8 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0x2000 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 8. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF8. + */ +struct ALT_USB_GLOB_DIEPTXF8_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF8. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF8_s ALT_USB_GLOB_DIEPTXF8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF8 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF8_OFST 0x120 +/* The address of the ALT_USB_GLOB_DIEPTXF8 register. */ +#define ALT_USB_GLOB_DIEPTXF8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF8_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 9 - dieptxf9 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:-------------------------------------------- + * [15:0] | RW | 0x4000 | IN Endpoint FIFOn Transmit RAM Start Addres + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Addres - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 9. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_RESET 0x4000 +/* Extracts the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF9. + */ +struct ALT_USB_GLOB_DIEPTXF9_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Addres */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF9. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF9_s ALT_USB_GLOB_DIEPTXF9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF9 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF9_OFST 0x124 +/* The address of the ALT_USB_GLOB_DIEPTXF9 register. */ +#define ALT_USB_GLOB_DIEPTXF9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF9_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 10 - dieptxf10 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0x6000 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 10. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_RESET 0x6000 +/* Extracts the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF10. + */ +struct ALT_USB_GLOB_DIEPTXF10_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF10. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF10_s ALT_USB_GLOB_DIEPTXF10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF10 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF10_OFST 0x128 +/* The address of the ALT_USB_GLOB_DIEPTXF10 register. */ +#define ALT_USB_GLOB_DIEPTXF10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF10_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 11 - dieptxf11 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0x8000 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 11. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_RESET 0x8000 +/* Extracts the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF11. + */ +struct ALT_USB_GLOB_DIEPTXF11_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF11. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF11_s ALT_USB_GLOB_DIEPTXF11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF11 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF11_OFST 0x12c +/* The address of the ALT_USB_GLOB_DIEPTXF11 register. */ +#define ALT_USB_GLOB_DIEPTXF11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF11_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 12 - dieptxf12 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0xa000 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 12. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_RESET 0xa000 +/* Extracts the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF12. + */ +struct ALT_USB_GLOB_DIEPTXF12_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF12. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF12_s ALT_USB_GLOB_DIEPTXF12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF12 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF12_OFST 0x130 +/* The address of the ALT_USB_GLOB_DIEPTXF12 register. */ +#define ALT_USB_GLOB_DIEPTXF12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF12_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 13 - dieptxf13 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0xc000 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 13. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_RESET 0xc000 +/* Extracts the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF13. + */ +struct ALT_USB_GLOB_DIEPTXF13_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF13. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF13_s ALT_USB_GLOB_DIEPTXF13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF13 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF13_OFST 0x134 +/* The address of the ALT_USB_GLOB_DIEPTXF13 register. */ +#define ALT_USB_GLOB_DIEPTXF13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF13_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 14 - dieptxf14 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0xe000 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 14. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_RESET 0xe000 +/* Extracts the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF14. + */ +struct ALT_USB_GLOB_DIEPTXF14_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF14. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF14_s ALT_USB_GLOB_DIEPTXF14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF14 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF14_OFST 0x138 +/* The address of the ALT_USB_GLOB_DIEPTXF14 register. */ +#define ALT_USB_GLOB_DIEPTXF14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF14_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Size Register 15 - dieptxf15 + * + * This register holds the size and memory start address of IN endpoint TxFIFOs + * implemented in Device mode. Each FIFO holds the data for one IN endpoint. This + * register is repeated for each instantiated IN endpoint FIFO. For IN endpoint + * FIFO 0 use GNPTXFSIZ register for programming the size and memory start address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------------------------- + * [15:0] | RW | 0x0 | IN Endpoint FIFOn Transmit RAM Start Address + * [29:16] | RW | 0x2000 | IN Endpoint TxFIFO Depth + * [31:30] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint FIFOn Transmit RAM Start Address - inepntxfstaddr + * + * This field contains the memory start address for IN endpoint Transmit FIFO 15. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_MSB 15 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_WIDTH 16 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_RESET 0x0 +/* Extracts the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : IN Endpoint TxFIFO Depth - inepntxfdep + * + * This value is in terms of 32-bit words. + * + * Minimum value is 16 + * + * Maximum value is 8192. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_MSB 29 +/* The width in bits of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_WIDTH 14 +/* The mask used to set the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_SET_MSK 0x3fff0000 +/* The mask used to clear the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_CLR_MSK 0xc000ffff +/* The reset value of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_RESET 0x2000 +/* Extracts the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP field value from a register. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16) +/* Produces a ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value suitable for setting the register. */ +#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_GLOB_DIEPTXF15. + */ +struct ALT_USB_GLOB_DIEPTXF15_s +{ + uint32_t inepntxfstaddr : 16; /* IN Endpoint FIFOn Transmit RAM Start Address */ + uint32_t inepntxfdep : 14; /* IN Endpoint TxFIFO Depth */ + uint32_t : 2; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF15. */ +typedef volatile struct ALT_USB_GLOB_DIEPTXF15_s ALT_USB_GLOB_DIEPTXF15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_GLOB_DIEPTXF15 register from the beginning of the component. */ +#define ALT_USB_GLOB_DIEPTXF15_OFST 0x13c +/* The address of the ALT_USB_GLOB_DIEPTXF15 register. */ +#define ALT_USB_GLOB_DIEPTXF15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF15_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_USB_GLOB. + */ +struct ALT_USB_GLOB_s +{ + volatile ALT_USB_GLOB_GOTGCTL_t gotgctl; /* ALT_USB_GLOB_GOTGCTL */ + volatile ALT_USB_GLOB_GOTGINT_t gotgint; /* ALT_USB_GLOB_GOTGINT */ + volatile ALT_USB_GLOB_GAHBCFG_t gahbcfg; /* ALT_USB_GLOB_GAHBCFG */ + volatile ALT_USB_GLOB_GUSBCFG_t gusbcfg; /* ALT_USB_GLOB_GUSBCFG */ + volatile ALT_USB_GLOB_GRSTCTL_t grstctl; /* ALT_USB_GLOB_GRSTCTL */ + volatile ALT_USB_GLOB_GINTSTS_t gintsts; /* ALT_USB_GLOB_GINTSTS */ + volatile ALT_USB_GLOB_GINTMSK_t gintmsk; /* ALT_USB_GLOB_GINTMSK */ + volatile ALT_USB_GLOB_GRXSTSR_t grxstsr; /* ALT_USB_GLOB_GRXSTSR */ + volatile ALT_USB_GLOB_GRXSTSP_t grxstsp; /* ALT_USB_GLOB_GRXSTSP */ + volatile ALT_USB_GLOB_GRXFSIZ_t grxfsiz; /* ALT_USB_GLOB_GRXFSIZ */ + volatile ALT_USB_GLOB_GNPTXFSIZ_t gnptxfsiz; /* ALT_USB_GLOB_GNPTXFSIZ */ + volatile ALT_USB_GLOB_GNPTXSTS_t gnptxsts; /* ALT_USB_GLOB_GNPTXSTS */ + volatile uint32_t _pad_0x30_0x33; /* *UNDEFINED* */ + volatile ALT_USB_GLOB_GPVNDCTL_t gpvndctl; /* ALT_USB_GLOB_GPVNDCTL */ + volatile ALT_USB_GLOB_GGPIO_t ggpio; /* ALT_USB_GLOB_GGPIO */ + volatile ALT_USB_GLOB_GUID_t guid; /* ALT_USB_GLOB_GUID */ + volatile ALT_USB_GLOB_GSNPSID_t gsnpsid; /* ALT_USB_GLOB_GSNPSID */ + volatile ALT_USB_GLOB_GHWCFG1_t ghwcfg1; /* ALT_USB_GLOB_GHWCFG1 */ + volatile ALT_USB_GLOB_GHWCFG2_t ghwcfg2; /* ALT_USB_GLOB_GHWCFG2 */ + volatile ALT_USB_GLOB_GHWCFG3_t ghwcfg3; /* ALT_USB_GLOB_GHWCFG3 */ + volatile ALT_USB_GLOB_GHWCFG4_t ghwcfg4; /* ALT_USB_GLOB_GHWCFG4 */ + volatile uint32_t _pad_0x54_0x5b[2]; /* *UNDEFINED* */ + volatile ALT_USB_GLOB_GDFIFOCFG_t gdfifocfg; /* ALT_USB_GLOB_GDFIFOCFG */ + volatile uint32_t _pad_0x60_0xff[40]; /* *UNDEFINED* */ + volatile ALT_USB_GLOB_HPTXFSIZ_t hptxfsiz; /* ALT_USB_GLOB_HPTXFSIZ */ + volatile ALT_USB_GLOB_DIEPTXF1_t dieptxf1; /* ALT_USB_GLOB_DIEPTXF1 */ + volatile ALT_USB_GLOB_DIEPTXF2_t dieptxf2; /* ALT_USB_GLOB_DIEPTXF2 */ + volatile ALT_USB_GLOB_DIEPTXF3_t dieptxf3; /* ALT_USB_GLOB_DIEPTXF3 */ + volatile ALT_USB_GLOB_DIEPTXF4_t dieptxf4; /* ALT_USB_GLOB_DIEPTXF4 */ + volatile ALT_USB_GLOB_DIEPTXF5_t dieptxf5; /* ALT_USB_GLOB_DIEPTXF5 */ + volatile ALT_USB_GLOB_DIEPTXF6_t dieptxf6; /* ALT_USB_GLOB_DIEPTXF6 */ + volatile ALT_USB_GLOB_DIEPTXF7_t dieptxf7; /* ALT_USB_GLOB_DIEPTXF7 */ + volatile ALT_USB_GLOB_DIEPTXF8_t dieptxf8; /* ALT_USB_GLOB_DIEPTXF8 */ + volatile ALT_USB_GLOB_DIEPTXF9_t dieptxf9; /* ALT_USB_GLOB_DIEPTXF9 */ + volatile ALT_USB_GLOB_DIEPTXF10_t dieptxf10; /* ALT_USB_GLOB_DIEPTXF10 */ + volatile ALT_USB_GLOB_DIEPTXF11_t dieptxf11; /* ALT_USB_GLOB_DIEPTXF11 */ + volatile ALT_USB_GLOB_DIEPTXF12_t dieptxf12; /* ALT_USB_GLOB_DIEPTXF12 */ + volatile ALT_USB_GLOB_DIEPTXF13_t dieptxf13; /* ALT_USB_GLOB_DIEPTXF13 */ + volatile ALT_USB_GLOB_DIEPTXF14_t dieptxf14; /* ALT_USB_GLOB_DIEPTXF14 */ + volatile ALT_USB_GLOB_DIEPTXF15_t dieptxf15; /* ALT_USB_GLOB_DIEPTXF15 */ +}; + +/* The typedef declaration for register group ALT_USB_GLOB. */ +typedef volatile struct ALT_USB_GLOB_s ALT_USB_GLOB_t; +/* The struct declaration for the raw register contents of register group ALT_USB_GLOB. */ +struct ALT_USB_GLOB_raw_s +{ + volatile uint32_t gotgctl; /* ALT_USB_GLOB_GOTGCTL */ + volatile uint32_t gotgint; /* ALT_USB_GLOB_GOTGINT */ + volatile uint32_t gahbcfg; /* ALT_USB_GLOB_GAHBCFG */ + volatile uint32_t gusbcfg; /* ALT_USB_GLOB_GUSBCFG */ + volatile uint32_t grstctl; /* ALT_USB_GLOB_GRSTCTL */ + volatile uint32_t gintsts; /* ALT_USB_GLOB_GINTSTS */ + volatile uint32_t gintmsk; /* ALT_USB_GLOB_GINTMSK */ + volatile uint32_t grxstsr; /* ALT_USB_GLOB_GRXSTSR */ + volatile uint32_t grxstsp; /* ALT_USB_GLOB_GRXSTSP */ + volatile uint32_t grxfsiz; /* ALT_USB_GLOB_GRXFSIZ */ + volatile uint32_t gnptxfsiz; /* ALT_USB_GLOB_GNPTXFSIZ */ + volatile uint32_t gnptxsts; /* ALT_USB_GLOB_GNPTXSTS */ + volatile uint32_t _pad_0x30_0x33; /* *UNDEFINED* */ + volatile uint32_t gpvndctl; /* ALT_USB_GLOB_GPVNDCTL */ + volatile uint32_t ggpio; /* ALT_USB_GLOB_GGPIO */ + volatile uint32_t guid; /* ALT_USB_GLOB_GUID */ + volatile uint32_t gsnpsid; /* ALT_USB_GLOB_GSNPSID */ + volatile uint32_t ghwcfg1; /* ALT_USB_GLOB_GHWCFG1 */ + volatile uint32_t ghwcfg2; /* ALT_USB_GLOB_GHWCFG2 */ + volatile uint32_t ghwcfg3; /* ALT_USB_GLOB_GHWCFG3 */ + volatile uint32_t ghwcfg4; /* ALT_USB_GLOB_GHWCFG4 */ + volatile uint32_t _pad_0x54_0x5b[2]; /* *UNDEFINED* */ + volatile uint32_t gdfifocfg; /* ALT_USB_GLOB_GDFIFOCFG */ + volatile uint32_t _pad_0x60_0xff[40]; /* *UNDEFINED* */ + volatile uint32_t hptxfsiz; /* ALT_USB_GLOB_HPTXFSIZ */ + volatile uint32_t dieptxf1; /* ALT_USB_GLOB_DIEPTXF1 */ + volatile uint32_t dieptxf2; /* ALT_USB_GLOB_DIEPTXF2 */ + volatile uint32_t dieptxf3; /* ALT_USB_GLOB_DIEPTXF3 */ + volatile uint32_t dieptxf4; /* ALT_USB_GLOB_DIEPTXF4 */ + volatile uint32_t dieptxf5; /* ALT_USB_GLOB_DIEPTXF5 */ + volatile uint32_t dieptxf6; /* ALT_USB_GLOB_DIEPTXF6 */ + volatile uint32_t dieptxf7; /* ALT_USB_GLOB_DIEPTXF7 */ + volatile uint32_t dieptxf8; /* ALT_USB_GLOB_DIEPTXF8 */ + volatile uint32_t dieptxf9; /* ALT_USB_GLOB_DIEPTXF9 */ + volatile uint32_t dieptxf10; /* ALT_USB_GLOB_DIEPTXF10 */ + volatile uint32_t dieptxf11; /* ALT_USB_GLOB_DIEPTXF11 */ + volatile uint32_t dieptxf12; /* ALT_USB_GLOB_DIEPTXF12 */ + volatile uint32_t dieptxf13; /* ALT_USB_GLOB_DIEPTXF13 */ + volatile uint32_t dieptxf14; /* ALT_USB_GLOB_DIEPTXF14 */ + volatile uint32_t dieptxf15; /* ALT_USB_GLOB_DIEPTXF15 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_USB_GLOB. */ +typedef volatile struct ALT_USB_GLOB_raw_s ALT_USB_GLOB_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Host Mode Registers - ALT_USB_HOST + * Host Mode Registers + * + * These registers must be programmed every time the USB OTG Controller changes to + * Host mode. + * + */ +/* + * Register : Host Configuration Register - hcfg + * + * Host Mode control. This register must be programmed every time the core changes + * to Host mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [1:0] | RW | 0x0 | FS LS PHY Clock Select + * [2] | RW | 0x0 | FS- and LS-Only Suppor + * [6:3] | ??? | 0x0 | *UNDEFINED* + * [7] | RW | 0x0 | Enable 32 KHz Suspend mode + * [15:8] | RW | 0x2 | Resume Validation Period + * [22:16] | ??? | 0x0 | *UNDEFINED* + * [23] | RW | 0x0 | Enable Scatter Gather DMA in Host mode + * [25:24] | RW | 0x0 | Frame List Entries + * [26] | RW | 0x0 | Enable Periodic Scheduling + * [30:27] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Mode Change Ready Timer Enable + * + */ +/* + * Field : FS LS PHY Clock Select - fslspclksel + * + * When the core is in FS Host mode. The internal PHY clock is running at 30/60 MHZ + * for ULPI PHY Interfaces. The internal PHY clock is running at 48MHZ for 1.1 FS + * transceiver Interface When the core is in LS Host mode, the internal PHY clock + * is running at 30/60 MHZ for ULPI PHY Interfaces. The internal PHY clock is + * running at 6 MHZ and the external clock is running at 48MHZ. When you select a 6 + * MHz clock during LS Mode, you must do a soft reset for 1.1 FS transceiver + * Interface. * When Core in FS mode, the internal and external clocks have the + * same frequency. + * + * * When Core in LS mode, + * + * - If fslspclksel is 30/60 Mhz internal and external clocks have the same + * frequency. + * + * - If fslspclksel is 6Mhz the internal clock is divided by eight of external + * 48 MHz clock (utmifs_clk). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------------------------- + * ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK3060 | 0x0 | PHY clock is running at 30/60 MHz + * ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK48 | 0x1 | PHY clock is running at 48 MHz + * ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK6 | 0x2 | PHY clock is running at 6 MHz + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL + * + * PHY clock is running at 30/60 MHz + */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK3060 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL + * + * PHY clock is running at 48 MHz + */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK48 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL + * + * PHY clock is running at 6 MHz + */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK6 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value. */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_SET_MSK 0x00000003 +/* The mask used to clear the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value. */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_CLR_MSK 0xfffffffc +/* The reset value of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCFG_FSLSPCLKSEL field value from a register. */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : FS- and LS-Only Suppor - fslssupp + * + * The application uses this bit to control the core's enumeration speed. Using + * this bit, the application can make the core enumerate as a FS host, even If the + * connected device supports HS traffic. Do not make changes to this field after + * initial programming. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCFG_FSLSSUPP_E_HSFSLS | 0x0 | HS/FS/LS, based on the maximum speed supported + * : | | by the connected device + * ALT_USB_HOST_HCFG_FSLSSUPP_E_FSLS | 0x1 | FS/LS-only, even if the connected device can + * : | | support HS + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSSUPP + * + * HS/FS/LS, based on the maximum speed supported by the connected device + */ +#define ALT_USB_HOST_HCFG_FSLSSUPP_E_HSFSLS 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSSUPP + * + * FS/LS-only, even if the connected device can support HS + */ +#define ALT_USB_HOST_HCFG_FSLSSUPP_E_FSLS 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */ +#define ALT_USB_HOST_HCFG_FSLSSUPP_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */ +#define ALT_USB_HOST_HCFG_FSLSSUPP_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */ +#define ALT_USB_HOST_HCFG_FSLSSUPP_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCFG_FSLSSUPP register field value. */ +#define ALT_USB_HOST_HCFG_FSLSSUPP_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCFG_FSLSSUPP register field value. */ +#define ALT_USB_HOST_HCFG_FSLSSUPP_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */ +#define ALT_USB_HOST_HCFG_FSLSSUPP_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCFG_FSLSSUPP field value from a register. */ +#define ALT_USB_HOST_HCFG_FSLSSUPP_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCFG_FSLSSUPP register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCFG_FSLSSUPP_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Enable 32 KHz Suspend mode - ena32khzs + * + * This bit can only be set if the USB 1.1 Full-Speed Serial Transceiver Interface + * has been selected. If USB 1.1 Full-Speed Serial Transceiver Interface has not + * been selected, this bit must be zero. When the USB 1.1 Full-Speed Serial + * Transceiver Interface is chosen and this bit is set, the core expects the 48-MHz + * PHY clock to be switched to 32 KHz during a suspend. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCFG_ENA32KHZS_E_DISD | 0x0 | USB 1.1 Full-Speed Not Selected + * ALT_USB_HOST_HCFG_ENA32KHZS_E_END | 0x1 | USB 1.1 Full-Speed Serial Transceiver Interface + * : | | selected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_ENA32KHZS + * + * USB 1.1 Full-Speed Not Selected + */ +#define ALT_USB_HOST_HCFG_ENA32KHZS_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_ENA32KHZS + * + * USB 1.1 Full-Speed Serial Transceiver Interface selected + */ +#define ALT_USB_HOST_HCFG_ENA32KHZS_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */ +#define ALT_USB_HOST_HCFG_ENA32KHZS_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */ +#define ALT_USB_HOST_HCFG_ENA32KHZS_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */ +#define ALT_USB_HOST_HCFG_ENA32KHZS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCFG_ENA32KHZS register field value. */ +#define ALT_USB_HOST_HCFG_ENA32KHZS_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCFG_ENA32KHZS register field value. */ +#define ALT_USB_HOST_HCFG_ENA32KHZS_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */ +#define ALT_USB_HOST_HCFG_ENA32KHZS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCFG_ENA32KHZS field value from a register. */ +#define ALT_USB_HOST_HCFG_ENA32KHZS_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCFG_ENA32KHZS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCFG_ENA32KHZS_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Resume Validation Period - resvalid + * + * This field is effective only when HCFG.Ena32KHzS is set. It will control the + * resume period when the core resumes from suspend. The core counts for ResValid + * number of clock cycles to detect a valid resume when this is set. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_RESVALID register field. */ +#define ALT_USB_HOST_HCFG_RESVALID_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_RESVALID register field. */ +#define ALT_USB_HOST_HCFG_RESVALID_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCFG_RESVALID register field. */ +#define ALT_USB_HOST_HCFG_RESVALID_WIDTH 8 +/* The mask used to set the ALT_USB_HOST_HCFG_RESVALID register field value. */ +#define ALT_USB_HOST_HCFG_RESVALID_SET_MSK 0x0000ff00 +/* The mask used to clear the ALT_USB_HOST_HCFG_RESVALID register field value. */ +#define ALT_USB_HOST_HCFG_RESVALID_CLR_MSK 0xffff00ff +/* The reset value of the ALT_USB_HOST_HCFG_RESVALID register field. */ +#define ALT_USB_HOST_HCFG_RESVALID_RESET 0x2 +/* Extracts the ALT_USB_HOST_HCFG_RESVALID field value from a register. */ +#define ALT_USB_HOST_HCFG_RESVALID_GET(value) (((value) & 0x0000ff00) >> 8) +/* Produces a ALT_USB_HOST_HCFG_RESVALID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCFG_RESVALID_SET(value) (((value) << 8) & 0x0000ff00) + +/* + * Field : Enable Scatter Gather DMA in Host mode - descdma + * + * The application can set this bit during initialization to enable the + * Scatter/Gather DMA operation. This bit must be modified only once after a reset. + * The following combinations are available for programming: + * + * GAHBCFG.DMAEn=0,HCFG.DescDMA=0 => Slave mode GAHBCFG.DMAEn=0,HCFG.DescDMA=1 => + * InvalidGAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA mode + * GAHBCFG.DMAEn=1,HCFG.DescDMA=1 => Scatter/Gather DMA mode + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCFG_DESCDMA_E_DISD | 0x0 | No Scatter/Gather DMA + * ALT_USB_HOST_HCFG_DESCDMA_E_END | 0x1 | Scatter/Gather DMA selected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_DESCDMA + * + * No Scatter/Gather DMA + */ +#define ALT_USB_HOST_HCFG_DESCDMA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_DESCDMA + * + * Scatter/Gather DMA selected + */ +#define ALT_USB_HOST_HCFG_DESCDMA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_DESCDMA register field. */ +#define ALT_USB_HOST_HCFG_DESCDMA_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_DESCDMA register field. */ +#define ALT_USB_HOST_HCFG_DESCDMA_MSB 23 +/* The width in bits of the ALT_USB_HOST_HCFG_DESCDMA register field. */ +#define ALT_USB_HOST_HCFG_DESCDMA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCFG_DESCDMA register field value. */ +#define ALT_USB_HOST_HCFG_DESCDMA_SET_MSK 0x00800000 +/* The mask used to clear the ALT_USB_HOST_HCFG_DESCDMA register field value. */ +#define ALT_USB_HOST_HCFG_DESCDMA_CLR_MSK 0xff7fffff +/* The reset value of the ALT_USB_HOST_HCFG_DESCDMA register field. */ +#define ALT_USB_HOST_HCFG_DESCDMA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCFG_DESCDMA field value from a register. */ +#define ALT_USB_HOST_HCFG_DESCDMA_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_USB_HOST_HCFG_DESCDMA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCFG_DESCDMA_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Frame List Entries - frlisten + * + * The value in the register specifies the number of entries in the Frame list. + * This field is valid only in Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_HOST_HCFG_FRLISTEN_E_RSVD | 0x0 | Reserved + * ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY8 | 0x1 | 8 Entries + * ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY16 | 0x2 | 16 Entries + * ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY32 | 0x3 | 32 Entries + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN + * + * Reserved + */ +#define ALT_USB_HOST_HCFG_FRLISTEN_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN + * + * 8 Entries + */ +#define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY8 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN + * + * 16 Entries + */ +#define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY16 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN + * + * 32 Entries + */ +#define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY32 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FRLISTEN register field. */ +#define ALT_USB_HOST_HCFG_FRLISTEN_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FRLISTEN register field. */ +#define ALT_USB_HOST_HCFG_FRLISTEN_MSB 25 +/* The width in bits of the ALT_USB_HOST_HCFG_FRLISTEN register field. */ +#define ALT_USB_HOST_HCFG_FRLISTEN_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCFG_FRLISTEN register field value. */ +#define ALT_USB_HOST_HCFG_FRLISTEN_SET_MSK 0x03000000 +/* The mask used to clear the ALT_USB_HOST_HCFG_FRLISTEN register field value. */ +#define ALT_USB_HOST_HCFG_FRLISTEN_CLR_MSK 0xfcffffff +/* The reset value of the ALT_USB_HOST_HCFG_FRLISTEN register field. */ +#define ALT_USB_HOST_HCFG_FRLISTEN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCFG_FRLISTEN field value from a register. */ +#define ALT_USB_HOST_HCFG_FRLISTEN_GET(value) (((value) & 0x03000000) >> 24) +/* Produces a ALT_USB_HOST_HCFG_FRLISTEN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCFG_FRLISTEN_SET(value) (((value) << 24) & 0x03000000) + +/* + * Field : Enable Periodic Scheduling - perschedena + * + * Applicable in Scatter/Gather DMA mode only. Enables periodic scheduling within + * the core. Initially, the bit is reset. The core will not process any periodic + * channels. As soon as this bit is set, the core will get ready to start + * scheduling periodic channels. In non Scatter/Gather DMA mode, this bit is + * reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------------------------------- + * ALT_USB_HOST_HCFG_PERSCHEDENA_E_DISD | 0x0 | Disables periodic scheduling within the core + * ALT_USB_HOST_HCFG_PERSCHEDENA_E_END | 0x1 | Enables periodic scheduling within the core + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_PERSCHEDENA + * + * Disables periodic scheduling within the core + */ +#define ALT_USB_HOST_HCFG_PERSCHEDENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_PERSCHEDENA + * + * Enables periodic scheduling within the core + */ +#define ALT_USB_HOST_HCFG_PERSCHEDENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */ +#define ALT_USB_HOST_HCFG_PERSCHEDENA_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */ +#define ALT_USB_HOST_HCFG_PERSCHEDENA_MSB 26 +/* The width in bits of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */ +#define ALT_USB_HOST_HCFG_PERSCHEDENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCFG_PERSCHEDENA register field value. */ +#define ALT_USB_HOST_HCFG_PERSCHEDENA_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_HOST_HCFG_PERSCHEDENA register field value. */ +#define ALT_USB_HOST_HCFG_PERSCHEDENA_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */ +#define ALT_USB_HOST_HCFG_PERSCHEDENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCFG_PERSCHEDENA field value from a register. */ +#define ALT_USB_HOST_HCFG_PERSCHEDENA_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_HOST_HCFG_PERSCHEDENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCFG_PERSCHEDENA_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Mode Change Ready Timer Enable - modechtimen + * + * This bit is used to enable or disable the host core to wait for 200 PHY clock + * cycles at the end of Resume to change the opmode signal to the PHY to 00 after + * Suspend or LPM. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCFG_MODCHTIMEN_E_END | 0x0 | The Host core waits for either 200 PHY clock + * : | | cycles or a linestate of SE0 at the end of + * : | | resume to change the opmode from 0x2 to 0x0 + * ALT_USB_HOST_HCFG_MODCHTIMEN_E_DISD | 0x1 | The Host core waits only for a linestate of SE0 + * : | | at the end of resume to change the opmode from + * : | | 0x2 to 0x0 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_MODCHTIMEN + * + * The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the + * end of resume to change the opmode from 0x2 to 0x0 + */ +#define ALT_USB_HOST_HCFG_MODCHTIMEN_E_END 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCFG_MODCHTIMEN + * + * The Host core waits only for a linestate of SE0 at the end of resume to change + * the opmode from 0x2 to 0x0 + */ +#define ALT_USB_HOST_HCFG_MODCHTIMEN_E_DISD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */ +#define ALT_USB_HOST_HCFG_MODCHTIMEN_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */ +#define ALT_USB_HOST_HCFG_MODCHTIMEN_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */ +#define ALT_USB_HOST_HCFG_MODCHTIMEN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCFG_MODCHTIMEN register field value. */ +#define ALT_USB_HOST_HCFG_MODCHTIMEN_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCFG_MODCHTIMEN register field value. */ +#define ALT_USB_HOST_HCFG_MODCHTIMEN_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */ +#define ALT_USB_HOST_HCFG_MODCHTIMEN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCFG_MODCHTIMEN field value from a register. */ +#define ALT_USB_HOST_HCFG_MODCHTIMEN_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCFG_MODCHTIMEN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCFG_MODCHTIMEN_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCFG. + */ +struct ALT_USB_HOST_HCFG_s +{ + uint32_t fslspclksel : 2; /* FS LS PHY Clock Select */ + uint32_t fslssupp : 1; /* FS- and LS-Only Suppor */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t ena32khzs : 1; /* Enable 32 KHz Suspend mode */ + uint32_t resvalid : 8; /* Resume Validation Period */ + uint32_t : 7; /* *UNDEFINED* */ + uint32_t descdma : 1; /* Enable Scatter Gather DMA in Host mode */ + uint32_t frlisten : 2; /* Frame List Entries */ + uint32_t perschedena : 1; /* Enable Periodic Scheduling */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t modechtimen : 1; /* Mode Change Ready Timer Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCFG. */ +typedef volatile struct ALT_USB_HOST_HCFG_s ALT_USB_HOST_HCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCFG register from the beginning of the component. */ +#define ALT_USB_HOST_HCFG_OFST 0x0 +/* The address of the ALT_USB_HOST_HCFG register. */ +#define ALT_USB_HOST_HCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCFG_OFST)) + +/* + * Register : Host Frame Interval Register - hfir + * + * This register stores the frame interval information for the current speed to + * which the otg core has enumerated + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------- + * [15:0] | RW | 0xea60 | Frame IntervaL + * [16] | RW | 0x0 | Reload Control + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Frame IntervaL - frint + * + * The value that the application programs to this field specifies the interval + * between two consecutive SOFs (FS) or micro- SOFs (HS) or Keep-Alive tokens (HS). + * This field contains the number of PHY clocks that constitute the required frame + * interval. The Default value Set in this field for a FS operation when the PHY + * clock frequency is 60 MHz. The application can write a value to this register + * only after the Port Enable bit of the Host Port Control and Status register + * (HPRT.PrtEnaPort) has been Set. If no value is programmed, the core calculates + * the value based on the PHY clock specified in the FS/LS PHY Clock Select field + * of the Host Configuration register (HCFG.FSLSPclkSel). Do not change the value + * of this field after the initial configuration. + * + * 125 s * (PHY clock frequency for HS) + * + * 1 ms * (PHY clock frequency for FS/LS) + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFIR_FRINT register field. */ +#define ALT_USB_HOST_HFIR_FRINT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFIR_FRINT register field. */ +#define ALT_USB_HOST_HFIR_FRINT_MSB 15 +/* The width in bits of the ALT_USB_HOST_HFIR_FRINT register field. */ +#define ALT_USB_HOST_HFIR_FRINT_WIDTH 16 +/* The mask used to set the ALT_USB_HOST_HFIR_FRINT register field value. */ +#define ALT_USB_HOST_HFIR_FRINT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_HOST_HFIR_FRINT register field value. */ +#define ALT_USB_HOST_HFIR_FRINT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_HOST_HFIR_FRINT register field. */ +#define ALT_USB_HOST_HFIR_FRINT_RESET 0xea60 +/* Extracts the ALT_USB_HOST_HFIR_FRINT field value from a register. */ +#define ALT_USB_HOST_HFIR_FRINT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_HOST_HFIR_FRINT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HFIR_FRINT_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Reload Control - hfirrldctrl + * + * This bit allows dynamic reloading of the HFIR register during run time. 0x0 : + * The HFIR cannot be reloaded dynamically0x1: the HFIR can be dynamically reloaded + * during runtime. This bit needs to be programmed during initial configuration and + * its value should not be changed during runtime. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------------------------------- + * ALT_USB_HOST_HFIR_HFIRRLDCTL_E_DISD | 0x0 | The HFIR cannot be reloaded dynamically + * ALT_USB_HOST_HFIR_HFIRRLDCTL_E_END | 0x1 | The HFIR can be dynamically reloaded during + * : | | runtime + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HFIR_HFIRRLDCTL + * + * The HFIR cannot be reloaded dynamically + */ +#define ALT_USB_HOST_HFIR_HFIRRLDCTL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HFIR_HFIRRLDCTL + * + * The HFIR can be dynamically reloaded during runtime + */ +#define ALT_USB_HOST_HFIR_HFIRRLDCTL_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */ +#define ALT_USB_HOST_HFIR_HFIRRLDCTL_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */ +#define ALT_USB_HOST_HFIR_HFIRRLDCTL_MSB 16 +/* The width in bits of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */ +#define ALT_USB_HOST_HFIR_HFIRRLDCTL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HFIR_HFIRRLDCTL register field value. */ +#define ALT_USB_HOST_HFIR_HFIRRLDCTL_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HFIR_HFIRRLDCTL register field value. */ +#define ALT_USB_HOST_HFIR_HFIRRLDCTL_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */ +#define ALT_USB_HOST_HFIR_HFIRRLDCTL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HFIR_HFIRRLDCTL field value from a register. */ +#define ALT_USB_HOST_HFIR_HFIRRLDCTL_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HFIR_HFIRRLDCTL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HFIR_HFIRRLDCTL_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HFIR. + */ +struct ALT_USB_HOST_HFIR_s +{ + uint32_t frint : 16; /* Frame IntervaL */ + uint32_t hfirrldctrl : 1; /* Reload Control */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HFIR. */ +typedef volatile struct ALT_USB_HOST_HFIR_s ALT_USB_HOST_HFIR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HFIR register from the beginning of the component. */ +#define ALT_USB_HOST_HFIR_OFST 0x4 +/* The address of the ALT_USB_HOST_HFIR register. */ +#define ALT_USB_HOST_HFIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFIR_OFST)) + +/* + * Register : Host Frame Number Frame Time Remaining Register - hfnum + * + * This register contains the free space information for the Periodic TxFIFO and + * the Periodic Transmit Request Queue + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------- + * [15:0] | R | 0x3fff | Frame Number + * [31:16] | R | 0x0 | Frame Time Remaining + * + */ +/* + * Field : Frame Number - frnum + * + * This field increments when a new SOF is transmitted on the USB, and is reset to + * 0 when it reaches 0x3FFF. Reads Return the Frame number value. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:---------------------- + * ALT_USB_HOST_HFNUM_FRNUM_E_INACT | 0x0 | No SOF is transmitted + * ALT_USB_HOST_HFNUM_FRNUM_E_ACT | 0x1 | SOF is transmitted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HFNUM_FRNUM + * + * No SOF is transmitted + */ +#define ALT_USB_HOST_HFNUM_FRNUM_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HFNUM_FRNUM + * + * SOF is transmitted + */ +#define ALT_USB_HOST_HFNUM_FRNUM_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFNUM_FRNUM register field. */ +#define ALT_USB_HOST_HFNUM_FRNUM_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFNUM_FRNUM register field. */ +#define ALT_USB_HOST_HFNUM_FRNUM_MSB 15 +/* The width in bits of the ALT_USB_HOST_HFNUM_FRNUM register field. */ +#define ALT_USB_HOST_HFNUM_FRNUM_WIDTH 16 +/* The mask used to set the ALT_USB_HOST_HFNUM_FRNUM register field value. */ +#define ALT_USB_HOST_HFNUM_FRNUM_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_HOST_HFNUM_FRNUM register field value. */ +#define ALT_USB_HOST_HFNUM_FRNUM_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_HOST_HFNUM_FRNUM register field. */ +#define ALT_USB_HOST_HFNUM_FRNUM_RESET 0x3fff +/* Extracts the ALT_USB_HOST_HFNUM_FRNUM field value from a register. */ +#define ALT_USB_HOST_HFNUM_FRNUM_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_HOST_HFNUM_FRNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HFNUM_FRNUM_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Frame Time Remaining - frrem + * + * Indicates the amount of time remaining in the current microframe (HS) or Frame + * (FS/LS), in terms of PHY clocks. This field decrements on each PHY clock. When + * it reaches zero, this field is reloaded with the value in the Frame Interval + * register and a new SOF is transmitted on the USB. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFNUM_FRREM register field. */ +#define ALT_USB_HOST_HFNUM_FRREM_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFNUM_FRREM register field. */ +#define ALT_USB_HOST_HFNUM_FRREM_MSB 31 +/* The width in bits of the ALT_USB_HOST_HFNUM_FRREM register field. */ +#define ALT_USB_HOST_HFNUM_FRREM_WIDTH 16 +/* The mask used to set the ALT_USB_HOST_HFNUM_FRREM register field value. */ +#define ALT_USB_HOST_HFNUM_FRREM_SET_MSK 0xffff0000 +/* The mask used to clear the ALT_USB_HOST_HFNUM_FRREM register field value. */ +#define ALT_USB_HOST_HFNUM_FRREM_CLR_MSK 0x0000ffff +/* The reset value of the ALT_USB_HOST_HFNUM_FRREM register field. */ +#define ALT_USB_HOST_HFNUM_FRREM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HFNUM_FRREM field value from a register. */ +#define ALT_USB_HOST_HFNUM_FRREM_GET(value) (((value) & 0xffff0000) >> 16) +/* Produces a ALT_USB_HOST_HFNUM_FRREM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HFNUM_FRREM_SET(value) (((value) << 16) & 0xffff0000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HFNUM. + */ +struct ALT_USB_HOST_HFNUM_s +{ + const uint32_t frnum : 16; /* Frame Number */ + const uint32_t frrem : 16; /* Frame Time Remaining */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HFNUM. */ +typedef volatile struct ALT_USB_HOST_HFNUM_s ALT_USB_HOST_HFNUM_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HFNUM register from the beginning of the component. */ +#define ALT_USB_HOST_HFNUM_OFST 0x8 +/* The address of the ALT_USB_HOST_HFNUM register. */ +#define ALT_USB_HOST_HFNUM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFNUM_OFST)) + +/* + * Register : Host Periodic Transmit FIFO Queue Status Register - hptxsts + * + * This register contains the free space information for the Periodic TxFIFO and + * the Periodic Transmit Request Queue. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------------------------ + * [15:0] | R | 0x2000 | Periodic Transmit Data FIFO Space Available + * [23:16] | R | 0x10 | Periodic Transmit Request Queue Space Available + * [24] | R | 0x0 | Terminate + * [26:25] | R | 0x0 | Type + * [30:27] | R | 0x0 | Channel Endpoint Number + * [31] | R | 0x0 | Odd Even Micro Frame + * + */ +/* + * Field : Periodic Transmit Data FIFO Space Available - ptxfspcavail + * + * Indicates the number of free locations available to be written to in the + * Periodic TxFIFO. Values are in terms of 32-bit words + * + * 16h0: Periodic TxFIFO is full + * + * 16h1: 1 word available + * + * 16h2: 2 words available + * + * 16hn: n words available where n is 0 to 8192 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */ +#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */ +#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */ +#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value. */ +#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value. */ +#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */ +#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL field value from a register. */ +#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +/* + * Field : Periodic Transmit Request Queue Space Available - ptxqspcavail + * + * Indicates the number of free locations available to be written in the Periodic + * Transmit Request Queue. This queue holds both IN and OUT requests. Others: + * Reserved + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FULL | 0x0 | Periodic Transmit Request Queue is full + * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE1 | 0x1 | 1 location available + * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE2 | 0x2 | 2 location available + * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE3 | 0x3 | 3 location available + * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE4 | 0x4 | 4 location available + * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE5 | 0x5 | 5 location available + * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE6 | 0x6 | 6 location available + * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE7 | 0x7 | 7 location available + * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE8 | 0x8 | 8 location available + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL + * + * Periodic Transmit Request Queue is full + */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FULL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL + * + * 1 location available + */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL + * + * 2 location available + */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL + * + * 3 location available + */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL + * + * 4 location available + */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL + * + * 5 location available + */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL + * + * 6 location available + */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL + * + * 7 location available + */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL + * + * 8 location available + */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE8 0x8 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_MSB 23 +/* The width in bits of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_WIDTH 8 +/* The mask used to set the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value. */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_SET_MSK 0x00ff0000 +/* The mask used to clear the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value. */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_CLR_MSK 0xff00ffff +/* The reset value of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_RESET 0x10 +/* Extracts the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL field value from a register. */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_GET(value) (((value) & 0x00ff0000) >> 16) +/* Produces a ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_SET(value) (((value) << 16) & 0x00ff0000) + +/* + * Field : Terminate - term + * + * Terminate last entry for selected channel/endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------------- + * ALT_USB_HOST_HPTXSTS_TERM_E_INACT | 0x0 | No termination + * ALT_USB_HOST_HPTXSTS_TERM_E_ACT | 0x1 | Terminate last entry for selected + * : | | channel/endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TERM + * + * No termination + */ +#define ALT_USB_HOST_HPTXSTS_TERM_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TERM + * + * Terminate last entry for selected channel/endpoint + */ +#define ALT_USB_HOST_HPTXSTS_TERM_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_TERM register field. */ +#define ALT_USB_HOST_HPTXSTS_TERM_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_TERM register field. */ +#define ALT_USB_HOST_HPTXSTS_TERM_MSB 24 +/* The width in bits of the ALT_USB_HOST_HPTXSTS_TERM register field. */ +#define ALT_USB_HOST_HPTXSTS_TERM_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPTXSTS_TERM register field value. */ +#define ALT_USB_HOST_HPTXSTS_TERM_SET_MSK 0x01000000 +/* The mask used to clear the ALT_USB_HOST_HPTXSTS_TERM register field value. */ +#define ALT_USB_HOST_HPTXSTS_TERM_CLR_MSK 0xfeffffff +/* The reset value of the ALT_USB_HOST_HPTXSTS_TERM register field. */ +#define ALT_USB_HOST_HPTXSTS_TERM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPTXSTS_TERM field value from a register. */ +#define ALT_USB_HOST_HPTXSTS_TERM_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_USB_HOST_HPTXSTS_TERM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPTXSTS_TERM_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : Type - type + * + * This indicates the Entry in the Periodic Tx Request Queue that is currently + * being processes by the MAC. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------ + * ALT_USB_HOST_HPTXSTS_TYPE_E_INOUT | 0x0 | IN/OUT type + * ALT_USB_HOST_HPTXSTS_TYPE_E_ZEROLNGTH | 0x1 | Zero-length packet type + * ALT_USB_HOST_HPTXSTS_TYPE_E_CSPLIT | 0x2 | CSPLIT type + * ALT_USB_HOST_HPTXSTS_TYPE_E_DIS | 0x3 | Disable channel command + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE + * + * IN/OUT type + */ +#define ALT_USB_HOST_HPTXSTS_TYPE_E_INOUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE + * + * Zero-length packet type + */ +#define ALT_USB_HOST_HPTXSTS_TYPE_E_ZEROLNGTH 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE + * + * CSPLIT type + */ +#define ALT_USB_HOST_HPTXSTS_TYPE_E_CSPLIT 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE + * + * Disable channel command + */ +#define ALT_USB_HOST_HPTXSTS_TYPE_E_DIS 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_TYPE register field. */ +#define ALT_USB_HOST_HPTXSTS_TYPE_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_TYPE register field. */ +#define ALT_USB_HOST_HPTXSTS_TYPE_MSB 26 +/* The width in bits of the ALT_USB_HOST_HPTXSTS_TYPE register field. */ +#define ALT_USB_HOST_HPTXSTS_TYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HPTXSTS_TYPE register field value. */ +#define ALT_USB_HOST_HPTXSTS_TYPE_SET_MSK 0x06000000 +/* The mask used to clear the ALT_USB_HOST_HPTXSTS_TYPE register field value. */ +#define ALT_USB_HOST_HPTXSTS_TYPE_CLR_MSK 0xf9ffffff +/* The reset value of the ALT_USB_HOST_HPTXSTS_TYPE register field. */ +#define ALT_USB_HOST_HPTXSTS_TYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPTXSTS_TYPE field value from a register. */ +#define ALT_USB_HOST_HPTXSTS_TYPE_GET(value) (((value) & 0x06000000) >> 25) +/* Produces a ALT_USB_HOST_HPTXSTS_TYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPTXSTS_TYPE_SET(value) (((value) << 25) & 0x06000000) + +/* + * Field : Channel Endpoint Number - chanendpt + * + * This indicates the channel endpoint number that is currently being processes by + * the MAC. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:-------------- + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT0 | 0x0 | End point 1 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT1 | 0x1 | End point 2 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT2 | 0x2 | End point 3 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT3 | 0x3 | End point 4 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT4 | 0x4 | End point 5 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT5 | 0x5 | End point 6 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT6 | 0x6 | End point 7 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT7 | 0x7 | End point 8 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT8 | 0x8 | End point 9 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT9 | 0x9 | End point 10 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT10 | 0xa | End point 11 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT11 | 0xb | End point 12 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT12 | 0xc | End point 13 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT13 | 0xd | End point 14 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT14 | 0xe | End point 15 + * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT15 | 0xf | End point 16 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 1 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 2 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 3 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 4 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 5 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 6 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 7 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 8 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 9 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 10 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 11 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 12 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 13 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 14 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 15 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT + * + * End point 16 + */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_MSB 30 +/* The width in bits of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HPTXSTS_CHANENDPT register field value. */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_SET_MSK 0x78000000 +/* The mask used to clear the ALT_USB_HOST_HPTXSTS_CHANENDPT register field value. */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_CLR_MSK 0x87ffffff +/* The reset value of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPTXSTS_CHANENDPT field value from a register. */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_GET(value) (((value) & 0x78000000) >> 27) +/* Produces a ALT_USB_HOST_HPTXSTS_CHANENDPT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPTXSTS_CHANENDPT_SET(value) (((value) << 27) & 0x78000000) + +/* + * Field : Odd Even Micro Frame - oddevnmframe + * + * This indicates the odd/even micro frame that is currently being processes by the + * MAC. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------------- + * ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_EVEN | 0x0 | Send in even (micro)Frame + * ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_ODD | 0x1 | Send in odd (micro)Frame + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_ODDEVNMFRM + * + * Send in even (micro)Frame + */ +#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_EVEN 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPTXSTS_ODDEVNMFRM + * + * Send in odd (micro)Frame + */ +#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_ODD 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */ +#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */ +#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_MSB 31 +/* The width in bits of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */ +#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value. */ +#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value. */ +#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */ +#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM field value from a register. */ +#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HPTXSTS. + */ +struct ALT_USB_HOST_HPTXSTS_s +{ + const uint32_t ptxfspcavail : 16; /* Periodic Transmit Data FIFO Space Available */ + const uint32_t ptxqspcavail : 8; /* Periodic Transmit Request Queue Space Available */ + const uint32_t term : 1; /* Terminate */ + const uint32_t type : 2; /* Type */ + const uint32_t chanendpt : 4; /* Channel Endpoint Number */ + const uint32_t oddevnmframe : 1; /* Odd Even Micro Frame */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HPTXSTS. */ +typedef volatile struct ALT_USB_HOST_HPTXSTS_s ALT_USB_HOST_HPTXSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HPTXSTS register from the beginning of the component. */ +#define ALT_USB_HOST_HPTXSTS_OFST 0x10 +/* The address of the ALT_USB_HOST_HPTXSTS register. */ +#define ALT_USB_HOST_HPTXSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HPTXSTS_OFST)) + +/* + * Register : Host All Channels Interrupt Register - haint + * + * When a significant event occurs on a channel, the Host All Channels Interrupt + * register interrupts the application using the Host Channels Interrupt bit of the + * Core Interrupt register (GINTSTS.HChInt). There is one interrupt bit per + * channel, up to a maximum of 16 bits. Bits in this register are set and cleared + * when the application sets and clears bits in the corresponding Host Channel-n + * Interrupt register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [15:0] | R | 0x0 | Channel Interrupts + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Channel Interrupts - haint + * + * One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HAINT_HAINT register field. */ +#define ALT_USB_HOST_HAINT_HAINT_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HAINT_HAINT register field. */ +#define ALT_USB_HOST_HAINT_HAINT_MSB 15 +/* The width in bits of the ALT_USB_HOST_HAINT_HAINT register field. */ +#define ALT_USB_HOST_HAINT_HAINT_WIDTH 16 +/* The mask used to set the ALT_USB_HOST_HAINT_HAINT register field value. */ +#define ALT_USB_HOST_HAINT_HAINT_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_HOST_HAINT_HAINT register field value. */ +#define ALT_USB_HOST_HAINT_HAINT_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_HOST_HAINT_HAINT register field. */ +#define ALT_USB_HOST_HAINT_HAINT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HAINT_HAINT field value from a register. */ +#define ALT_USB_HOST_HAINT_HAINT_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_HOST_HAINT_HAINT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HAINT_HAINT_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HAINT. + */ +struct ALT_USB_HOST_HAINT_s +{ + const uint32_t haint : 16; /* Channel Interrupts */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HAINT. */ +typedef volatile struct ALT_USB_HOST_HAINT_s ALT_USB_HOST_HAINT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HAINT register from the beginning of the component. */ +#define ALT_USB_HOST_HAINT_OFST 0x14 +/* The address of the ALT_USB_HOST_HAINT register. */ +#define ALT_USB_HOST_HAINT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HAINT_OFST)) + +/* + * Register : Host All Channels Interrupt Mask Register - haintmsk + * + * The Host All Channel Interrupt Mask register works with the Host All Channel + * Interrupt register to interrupt the application when an event occurs on a + * channel. There is one interrupt mask bit per channel, up to a maximum of 16 + * bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------- + * [15:0] | RW | 0x0 | Channel Interrupt Mask + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Channel Interrupt Mask - haintmsk + * + * One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------- + * ALT_USB_HOST_HAINTMSK_HAINTMSK_E_MSK | 0x0 | Mask interrupt + * ALT_USB_HOST_HAINTMSK_HAINTMSK_E_NOMSK | 0x1 | Unmask interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HAINTMSK_HAINTMSK + * + * Mask interrupt + */ +#define ALT_USB_HOST_HAINTMSK_HAINTMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HAINTMSK_HAINTMSK + * + * Unmask interrupt + */ +#define ALT_USB_HOST_HAINTMSK_HAINTMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */ +#define ALT_USB_HOST_HAINTMSK_HAINTMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */ +#define ALT_USB_HOST_HAINTMSK_HAINTMSK_MSB 15 +/* The width in bits of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */ +#define ALT_USB_HOST_HAINTMSK_HAINTMSK_WIDTH 16 +/* The mask used to set the ALT_USB_HOST_HAINTMSK_HAINTMSK register field value. */ +#define ALT_USB_HOST_HAINTMSK_HAINTMSK_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_HOST_HAINTMSK_HAINTMSK register field value. */ +#define ALT_USB_HOST_HAINTMSK_HAINTMSK_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */ +#define ALT_USB_HOST_HAINTMSK_HAINTMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HAINTMSK_HAINTMSK field value from a register. */ +#define ALT_USB_HOST_HAINTMSK_HAINTMSK_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_HOST_HAINTMSK_HAINTMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HAINTMSK_HAINTMSK_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HAINTMSK. + */ +struct ALT_USB_HOST_HAINTMSK_s +{ + uint32_t haintmsk : 16; /* Channel Interrupt Mask */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HAINTMSK. */ +typedef volatile struct ALT_USB_HOST_HAINTMSK_s ALT_USB_HOST_HAINTMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HAINTMSK register from the beginning of the component. */ +#define ALT_USB_HOST_HAINTMSK_OFST 0x18 +/* The address of the ALT_USB_HOST_HAINTMSK register. */ +#define ALT_USB_HOST_HAINTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HAINTMSK_OFST)) + +/* + * Register : Host Frame List Base Address Register - hflbaddr + * + * This Register is valid only for Host mode Scatter-Gather DMA. Starting address + * of the Frame list. This register is used only for Isochronous and Interrupt + * Channels. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------------- + * [31:0] | RW | 0x0 | ALT_USB_HOST_HFLBADDR_HFLBADDR + * + */ +/* + * Field : hflbaddr + * + * This Register is valid only for Host mode Scatter-Gather DMA mode. Starting + * address of the Frame list. This register is used only for Isochronous and + * Interrupt Channels. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */ +#define ALT_USB_HOST_HFLBADDR_HFLBADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */ +#define ALT_USB_HOST_HFLBADDR_HFLBADDR_MSB 31 +/* The width in bits of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */ +#define ALT_USB_HOST_HFLBADDR_HFLBADDR_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HFLBADDR_HFLBADDR register field value. */ +#define ALT_USB_HOST_HFLBADDR_HFLBADDR_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HFLBADDR_HFLBADDR register field value. */ +#define ALT_USB_HOST_HFLBADDR_HFLBADDR_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */ +#define ALT_USB_HOST_HFLBADDR_HFLBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HFLBADDR_HFLBADDR field value from a register. */ +#define ALT_USB_HOST_HFLBADDR_HFLBADDR_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HFLBADDR_HFLBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HFLBADDR_HFLBADDR_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HFLBADDR. + */ +struct ALT_USB_HOST_HFLBADDR_s +{ + uint32_t hflbaddr : 32; /* ALT_USB_HOST_HFLBADDR_HFLBADDR */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HFLBADDR. */ +typedef volatile struct ALT_USB_HOST_HFLBADDR_s ALT_USB_HOST_HFLBADDR_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HFLBADDR register from the beginning of the component. */ +#define ALT_USB_HOST_HFLBADDR_OFST 0x1c +/* The address of the ALT_USB_HOST_HFLBADDR register. */ +#define ALT_USB_HOST_HFLBADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFLBADDR_OFST)) + +/* + * Register : Host Port Control and Status Register - hprt + * + * This register is available only in Host mode. Currently, the OTG Host supports + * only one port. A single register holds USB port-related information such as USB + * reset, enable, suspend, resume, connect status, and test mode for each port.The + * R_SS_WC bits in this register can trigger an interrupt to the application + * through the Host Port Interrupt bit of the Core Interrupt register + * (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register + * and clear the bit that caused the interrupt. for the R_SS_WC bits, the + * application must write a 1 to the bit to clear the interrupt + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------- + * [0] | R | 0x0 | Port Connect Status + * [1] | R | 0x0 | Port Connect Detected + * [2] | R | 0x0 | Port Enabl + * [3] | R | 0x0 | Port Enable Disable Change + * [4] | R | 0x0 | Port Overcurrent Active + * [5] | R | 0x0 | Port Overcurrent Change + * [6] | RW | 0x0 | Port Resume + * [7] | R | 0x0 | Port Suspend + * [8] | RW | 0x0 | Port Reset + * [9] | ??? | 0x0 | *UNDEFINED* + * [11:10] | R | 0x0 | Port Line Status + * [12] | RW | 0x0 | Port Power + * [16:13] | RW | 0x0 | Port Test Control + * [18:17] | R | 0x0 | Port Speed + * [31:19] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Port Connect Status - prtconnsts + * + * Defines whether port is attached. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:---------------------------------- + * ALT_USB_HOST_HPRT_PRTCONNSTS_E_NOTATTACHED | 0x0 | No device is attached to the port + * ALT_USB_HOST_HPRT_PRTCONNSTS_E_ATTACHED | 0x1 | A device is attached to the port + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNSTS + * + * No device is attached to the port + */ +#define ALT_USB_HOST_HPRT_PRTCONNSTS_E_NOTATTACHED 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNSTS + * + * A device is attached to the port + */ +#define ALT_USB_HOST_HPRT_PRTCONNSTS_E_ATTACHED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */ +#define ALT_USB_HOST_HPRT_PRTCONNSTS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */ +#define ALT_USB_HOST_HPRT_PRTCONNSTS_MSB 0 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */ +#define ALT_USB_HOST_HPRT_PRTCONNSTS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTCONNSTS register field value. */ +#define ALT_USB_HOST_HPRT_PRTCONNSTS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTCONNSTS register field value. */ +#define ALT_USB_HOST_HPRT_PRTCONNSTS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */ +#define ALT_USB_HOST_HPRT_PRTCONNSTS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTCONNSTS field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTCONNSTS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HPRT_PRTCONNSTS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTCONNSTS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Port Connect Detected - PrtConnDet + * + * The core sets this bit when a device connection is detected to trigger an + * interrupt to the application using the Host Port Interrupt bit of the Core + * Interrupt register (GINTSTS.PrtInt). This bit can be set only by the core and + * the application should write 1 to clear it.The application must write a 1 to + * this bit to clear the interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------ + * ALT_USB_HOST_HPRT_PRTCONNDET_E_ACT | 0x0 | Device connection detected + * ALT_USB_HOST_HPRT_PRTCONNDET_E_INACT | 0x1 | No device connection detected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNDET + * + * Device connection detected + */ +#define ALT_USB_HOST_HPRT_PRTCONNDET_E_ACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNDET + * + * No device connection detected + */ +#define ALT_USB_HOST_HPRT_PRTCONNDET_E_INACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */ +#define ALT_USB_HOST_HPRT_PRTCONNDET_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */ +#define ALT_USB_HOST_HPRT_PRTCONNDET_MSB 1 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */ +#define ALT_USB_HOST_HPRT_PRTCONNDET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTCONNDET register field value. */ +#define ALT_USB_HOST_HPRT_PRTCONNDET_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTCONNDET register field value. */ +#define ALT_USB_HOST_HPRT_PRTCONNDET_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */ +#define ALT_USB_HOST_HPRT_PRTCONNDET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTCONNDET field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTCONNDET_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HPRT_PRTCONNDET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTCONNDET_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Port Enabl - prtena + * + * A port is enabled only by the core after a reset sequence, and is disabled by an + * overcurrent condition, a disconnect condition, or by the application clearing + * this bit. The application cannot Set this bit by a register write. It can only + * clear it to disable the port by writing 1. This bit does not trigger any + * interrupt to the application. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:-------------- + * ALT_USB_HOST_HPRT_PRTENA_E_DISD | 0x0 | Port disabled + * ALT_USB_HOST_HPRT_PRTENA_E_END | 0x1 | Port enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENA + * + * Port disabled + */ +#define ALT_USB_HOST_HPRT_PRTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENA + * + * Port enabled + */ +#define ALT_USB_HOST_HPRT_PRTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTENA register field. */ +#define ALT_USB_HOST_HPRT_PRTENA_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTENA register field. */ +#define ALT_USB_HOST_HPRT_PRTENA_MSB 2 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTENA register field. */ +#define ALT_USB_HOST_HPRT_PRTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTENA register field value. */ +#define ALT_USB_HOST_HPRT_PRTENA_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTENA register field value. */ +#define ALT_USB_HOST_HPRT_PRTENA_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HPRT_PRTENA register field. */ +#define ALT_USB_HOST_HPRT_PRTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTENA field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTENA_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HPRT_PRTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTENA_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Port Enable Disable Change - prtenchng + * + * The core sets this bit when the status of the Port Enable bit [2] of this + * register changes. This bit can be set only by the core and the application + * should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HPRT_PRTENCHNG_E_INACT | 0x0 | Port Enable bit 2 no change + * ALT_USB_HOST_HPRT_PRTENCHNG_E_ACT | 0x1 | Port Enable bit 2 changed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENCHNG + * + * Port Enable bit 2 no change + */ +#define ALT_USB_HOST_HPRT_PRTENCHNG_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENCHNG + * + * Port Enable bit 2 changed + */ +#define ALT_USB_HOST_HPRT_PRTENCHNG_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */ +#define ALT_USB_HOST_HPRT_PRTENCHNG_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */ +#define ALT_USB_HOST_HPRT_PRTENCHNG_MSB 3 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */ +#define ALT_USB_HOST_HPRT_PRTENCHNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTENCHNG register field value. */ +#define ALT_USB_HOST_HPRT_PRTENCHNG_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTENCHNG register field value. */ +#define ALT_USB_HOST_HPRT_PRTENCHNG_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */ +#define ALT_USB_HOST_HPRT_PRTENCHNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTENCHNG field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTENCHNG_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HPRT_PRTENCHNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTENCHNG_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Port Overcurrent Active - prtovrcurract + * + * Indicates the overcurrent condition of the port. 0x0: No overcurrent condition + * 0x1: Overcurrent condition + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------- + * ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_INACT | 0x0 | No overcurrent condition + * ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_ACT | 0x1 | Overcurrent condition + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRACT + * + * No overcurrent condition + */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRACT + * + * Overcurrent condition + */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_MSB 4 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTOVRCURRACT field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Port Overcurrent Change - prtovrcurrchng + * + * The core sets this bit when the status of the PortOvercurrent Active bit (bit 4) + * in this register changes.This bit can be set only by the core and the + * application should write 1 to clear it + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------- + * ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_INACT | 0x0 | Status of port overcurrent no change + * ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_ACT | 0x1 | Status of port overcurrent changed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRCHNG + * + * Status of port overcurrent no change + */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRCHNG + * + * Status of port overcurrent changed + */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_MSB 5 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Port Resume - prtres + * + * The application sets this bit to drive resume signaling on the port. The core + * continues to drive the resume signal until the application clears this bit. If + * the core detects a USB remote wakeup sequence, as indicated by the Port + * Resume/Remote Wakeup Detected Interrupt bit of the Core Interrupt register + * (GINTSTS.WkUpInt), the core starts driving resume signaling without application + * intervention and clears this bit when it detects a disconnect condition. The + * read value of this bit indicates whether the core is currently drivingresume + * signaling. When LPM is enabled and the core is in the L1 (Sleep) state, setting + * this bit results in the following behavior: + * + * The core continues to drive the resume signal until a pre-determined time + * specified in the GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote + * wakeup sequence, as indicated by the Port L1 Resume/Remote L1 Wakeup Detected + * Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt), the core + * starts driving resume signaling without application intervention and clears this + * bit at the end of the resume. The read value of this bit indicates whether the + * core is currently driving resume signaling. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HPRT_PRTRES_E_NORESUME | 0x0 | No resume driven + * ALT_USB_HOST_HPRT_PRTRES_E_RESUME | 0x1 | Resume driven + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRES + * + * No resume driven + */ +#define ALT_USB_HOST_HPRT_PRTRES_E_NORESUME 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRES + * + * Resume driven + */ +#define ALT_USB_HOST_HPRT_PRTRES_E_RESUME 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTRES register field. */ +#define ALT_USB_HOST_HPRT_PRTRES_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTRES register field. */ +#define ALT_USB_HOST_HPRT_PRTRES_MSB 6 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTRES register field. */ +#define ALT_USB_HOST_HPRT_PRTRES_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTRES register field value. */ +#define ALT_USB_HOST_HPRT_PRTRES_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTRES register field value. */ +#define ALT_USB_HOST_HPRT_PRTRES_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HPRT_PRTRES register field. */ +#define ALT_USB_HOST_HPRT_PRTRES_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTRES field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTRES_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HPRT_PRTRES register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTRES_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Port Suspend - prtsusp + * + * The application sets this bit to put this port in Suspend mode. The core only + * stops sending SOFs when this is Set. To stop the PHY clock, the application must + * Set the Port Clock Stop bit, which asserts the suspend input pin of the PHY. The + * read value of this bit reflects the current suspend status of the port. This bit + * is cleared by the core after a remote wakeup signal is detected or the + * application sets the Port Reset bit or Port Resume bit in this register or the + * Resume/Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit + * in the Core Interrupt register (GINTSTS.WkUpInt or GINTSTS.DisconnInt, + * respectively). This bit is cleared by the core even if there is no device + * connected to the Host. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------- + * ALT_USB_HOST_HPRT_PRTSUSP_E_INACT | 0x0 | Port not in Suspend mode + * ALT_USB_HOST_HPRT_PRTSUSP_E_ACT | 0x1 | Port in Suspend mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSUSP + * + * Port not in Suspend mode + */ +#define ALT_USB_HOST_HPRT_PRTSUSP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSUSP + * + * Port in Suspend mode + */ +#define ALT_USB_HOST_HPRT_PRTSUSP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTSUSP register field. */ +#define ALT_USB_HOST_HPRT_PRTSUSP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTSUSP register field. */ +#define ALT_USB_HOST_HPRT_PRTSUSP_MSB 7 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTSUSP register field. */ +#define ALT_USB_HOST_HPRT_PRTSUSP_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTSUSP register field value. */ +#define ALT_USB_HOST_HPRT_PRTSUSP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTSUSP register field value. */ +#define ALT_USB_HOST_HPRT_PRTSUSP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HPRT_PRTSUSP register field. */ +#define ALT_USB_HOST_HPRT_PRTSUSP_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTSUSP field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTSUSP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HPRT_PRTSUSP register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTSUSP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Port Reset - prtrst + * + * When the application sets this bit, a reset sequence is started on this port. + * The application must time the reset period and clear this bit after the reset + * sequence is complete. The application must leave this bit Set for at least a + * minimum duration mentioned below to start a reset on the port. The application + * can leave it Set for another 10 ms in addition to the required minimum duration, + * before clearing the bit, even though there is no maximum limit set by theUSB + * standard. This bit is cleared by the core even if there is no device connected + * to the Host. + * + * High speed: 50 ms + * + * Full speed/Low speed: 10 ms + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------ + * ALT_USB_HOST_HPRT_PRTRST_E_DISD | 0x0 | Port not in reset + * ALT_USB_HOST_HPRT_PRTRST_E_END | 0x1 | Port in reset + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRST + * + * Port not in reset + */ +#define ALT_USB_HOST_HPRT_PRTRST_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRST + * + * Port in reset + */ +#define ALT_USB_HOST_HPRT_PRTRST_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTRST register field. */ +#define ALT_USB_HOST_HPRT_PRTRST_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTRST register field. */ +#define ALT_USB_HOST_HPRT_PRTRST_MSB 8 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTRST register field. */ +#define ALT_USB_HOST_HPRT_PRTRST_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTRST register field value. */ +#define ALT_USB_HOST_HPRT_PRTRST_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTRST register field value. */ +#define ALT_USB_HOST_HPRT_PRTRST_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HPRT_PRTRST register field. */ +#define ALT_USB_HOST_HPRT_PRTRST_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTRST field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTRST_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HPRT_PRTRST register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTRST_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Port Line Status - prtlnsts + * + * Indicates the current logic level USB data lines. Bit [10]: Logic level of D+ + * Bit [11]: Logic level of D- + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HPRT_PRTLNSTS_E_PLUSD | 0x1 | Logic level of D+ + * ALT_USB_HOST_HPRT_PRTLNSTS_E_MINUSD | 0x2 | Logic level of D- + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTLNSTS + * + * Logic level of D+ + */ +#define ALT_USB_HOST_HPRT_PRTLNSTS_E_PLUSD 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTLNSTS + * + * Logic level of D- + */ +#define ALT_USB_HOST_HPRT_PRTLNSTS_E_MINUSD 0x2 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */ +#define ALT_USB_HOST_HPRT_PRTLNSTS_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */ +#define ALT_USB_HOST_HPRT_PRTLNSTS_MSB 11 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */ +#define ALT_USB_HOST_HPRT_PRTLNSTS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTLNSTS register field value. */ +#define ALT_USB_HOST_HPRT_PRTLNSTS_SET_MSK 0x00000c00 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTLNSTS register field value. */ +#define ALT_USB_HOST_HPRT_PRTLNSTS_CLR_MSK 0xfffff3ff +/* The reset value of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */ +#define ALT_USB_HOST_HPRT_PRTLNSTS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTLNSTS field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTLNSTS_GET(value) (((value) & 0x00000c00) >> 10) +/* Produces a ALT_USB_HOST_HPRT_PRTLNSTS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTLNSTS_SET(value) (((value) << 10) & 0x00000c00) + +/* + * Field : Port Power - prtpwr + * + * The application uses this field to control power to this port, and the core can + * clear this bit on an over current condition. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------ + * ALT_USB_HOST_HPRT_PRTPWR_E_OFF | 0x0 | Power off + * ALT_USB_HOST_HPRT_PRTPWR_E_ON | 0x1 | Power on + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTPWR + * + * Power off + */ +#define ALT_USB_HOST_HPRT_PRTPWR_E_OFF 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTPWR + * + * Power on + */ +#define ALT_USB_HOST_HPRT_PRTPWR_E_ON 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTPWR register field. */ +#define ALT_USB_HOST_HPRT_PRTPWR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTPWR register field. */ +#define ALT_USB_HOST_HPRT_PRTPWR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTPWR register field. */ +#define ALT_USB_HOST_HPRT_PRTPWR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTPWR register field value. */ +#define ALT_USB_HOST_HPRT_PRTPWR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTPWR register field value. */ +#define ALT_USB_HOST_HPRT_PRTPWR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HPRT_PRTPWR register field. */ +#define ALT_USB_HOST_HPRT_PRTPWR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTPWR field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTPWR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HPRT_PRTPWR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTPWR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Port Test Control - prttstctl + * + * The application writes a nonzero value to this field to put the port into a Test + * mode, and the corresponding pattern is signaled on the port. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------- + * ALT_USB_HOST_HPRT_PRTTSTCTL_E_DISD | 0x0 | Test mode disabled + * ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTJ | 0x1 | Test_J mode + * ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTK | 0x2 | Test_K mode + * ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTSN | 0x3 | Test_SE0_NAK mode + * ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTPM | 0x4 | Test_Packet mode + * ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTFENB | 0x5 | Test_force_Enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL + * + * Test mode disabled + */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL + * + * Test_J mode + */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTJ 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL + * + * Test_K mode + */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL + * + * Test_SE0_NAK mode + */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTSN 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL + * + * Test_Packet mode + */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTPM 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL + * + * Test_force_Enable + */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTFENB 0x5 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_MSB 16 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTTSTCTL register field value. */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_SET_MSK 0x0001e000 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTTSTCTL register field value. */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_CLR_MSK 0xfffe1fff +/* The reset value of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTTSTCTL field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_GET(value) (((value) & 0x0001e000) >> 13) +/* Produces a ALT_USB_HOST_HPRT_PRTTSTCTL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTTSTCTL_SET(value) (((value) << 13) & 0x0001e000) + +/* + * Field : Port Speed - prtspd + * + * Indicates the speed of the device attached to this port. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_HOST_HPRT_PRTSPD_E_HIGHSPD | 0x0 | High speed + * ALT_USB_HOST_HPRT_PRTSPD_E_FULLSPD | 0x1 | Full speed + * ALT_USB_HOST_HPRT_PRTSPD_E_LOWSPD | 0x2 | Low speed + * ALT_USB_HOST_HPRT_PRTSPD_E_RSVD | 0x3 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD + * + * High speed + */ +#define ALT_USB_HOST_HPRT_PRTSPD_E_HIGHSPD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD + * + * Full speed + */ +#define ALT_USB_HOST_HPRT_PRTSPD_E_FULLSPD 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD + * + * Low speed + */ +#define ALT_USB_HOST_HPRT_PRTSPD_E_LOWSPD 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD + * + * Reserved + */ +#define ALT_USB_HOST_HPRT_PRTSPD_E_RSVD 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTSPD register field. */ +#define ALT_USB_HOST_HPRT_PRTSPD_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTSPD register field. */ +#define ALT_USB_HOST_HPRT_PRTSPD_MSB 18 +/* The width in bits of the ALT_USB_HOST_HPRT_PRTSPD register field. */ +#define ALT_USB_HOST_HPRT_PRTSPD_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HPRT_PRTSPD register field value. */ +#define ALT_USB_HOST_HPRT_PRTSPD_SET_MSK 0x00060000 +/* The mask used to clear the ALT_USB_HOST_HPRT_PRTSPD register field value. */ +#define ALT_USB_HOST_HPRT_PRTSPD_CLR_MSK 0xfff9ffff +/* The reset value of the ALT_USB_HOST_HPRT_PRTSPD register field. */ +#define ALT_USB_HOST_HPRT_PRTSPD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HPRT_PRTSPD field value from a register. */ +#define ALT_USB_HOST_HPRT_PRTSPD_GET(value) (((value) & 0x00060000) >> 17) +/* Produces a ALT_USB_HOST_HPRT_PRTSPD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HPRT_PRTSPD_SET(value) (((value) << 17) & 0x00060000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HPRT. + */ +struct ALT_USB_HOST_HPRT_s +{ + const uint32_t prtconnsts : 1; /* Port Connect Status */ + const uint32_t PrtConnDet : 1; /* Port Connect Detected */ + const uint32_t prtena : 1; /* Port Enabl */ + const uint32_t prtenchng : 1; /* Port Enable Disable Change */ + const uint32_t prtovrcurract : 1; /* Port Overcurrent Active */ + const uint32_t prtovrcurrchng : 1; /* Port Overcurrent Change */ + uint32_t prtres : 1; /* Port Resume */ + const uint32_t prtsusp : 1; /* Port Suspend */ + uint32_t prtrst : 1; /* Port Reset */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t prtlnsts : 2; /* Port Line Status */ + uint32_t prtpwr : 1; /* Port Power */ + uint32_t prttstctl : 4; /* Port Test Control */ + const uint32_t prtspd : 2; /* Port Speed */ + uint32_t : 13; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HPRT. */ +typedef volatile struct ALT_USB_HOST_HPRT_s ALT_USB_HOST_HPRT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HPRT register from the beginning of the component. */ +#define ALT_USB_HOST_HPRT_OFST 0x40 +/* The address of the ALT_USB_HOST_HPRT register. */ +#define ALT_USB_HOST_HPRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HPRT_OFST)) + +/* + * Register : Host Channel 0 Characteristics Register - hcchar0 + * + * Channel_number: 0. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count Error Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_MPS register field. */ +#define ALT_USB_HOST_HCCHAR0_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_MPS register field. */ +#define ALT_USB_HOST_HCCHAR0_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR0_MPS register field. */ +#define ALT_USB_HOST_HCCHAR0_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR0_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR0_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR0_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR0_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR0_MPS register field. */ +#define ALT_USB_HOST_HCCHAR0_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR0_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR0_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR0_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR0_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR0_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR0_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR0_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR0_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR0_EPDIR_E_OUTDIR | 0x0 | OUT + * ALT_USB_HOST_HCCHAR0_EPDIR_E_INDIR | 0x1 | IN + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPDIR + * + * OUT + */ +#define ALT_USB_HOST_HCCHAR0_EPDIR_E_OUTDIR 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPDIR + * + * IN + */ +#define ALT_USB_HOST_HCCHAR0_EPDIR_E_INDIR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR0_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR0_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR0_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR0_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR0_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR0_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR0_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR0_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR0_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR0_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR0_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is Set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCCHAR0_LSPDDEV_E_NONLOWSPEED | 0x0 | Communicating with non lowspeed + * ALT_USB_HOST_HCCHAR0_LSPDDEV_E_LOWSPEED | 0x1 | Communicating with lowspeed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_LSPDDEV + * + * Communicating with non lowspeed + */ +#define ALT_USB_HOST_HCCHAR0_LSPDDEV_E_NONLOWSPEED 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_LSPDDEV + * + * Communicating with lowspeed + */ +#define ALT_USB_HOST_HCCHAR0_LSPDDEV_E_LOWSPEED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR0_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR0_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR0_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR0_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR0_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR0_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR0_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR0_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR0_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR0_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR0_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR0_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR0_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR0_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR0_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR0_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR0_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR0_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR0_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count Error Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1'b1), this field indicates + * the number of immediate retries to be performed for a periodic split + * transactions on transaction errors. This field must be Set to at least 2'b01. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR0_EC_E_RSVD | 0x0 | Reserved This field yields undefined results + * ALT_USB_HOST_HCCHAR0_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR0_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR0_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC + * + * Reserved This field yields undefined results + */ +#define ALT_USB_HOST_HCCHAR0_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR0_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR0_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR0_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EC register field. */ +#define ALT_USB_HOST_HCCHAR0_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EC register field. */ +#define ALT_USB_HOST_HCCHAR0_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR0_EC register field. */ +#define ALT_USB_HOST_HCCHAR0_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR0_EC register field value. */ +#define ALT_USB_HOST_HCCHAR0_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EC register field value. */ +#define ALT_USB_HOST_HCCHAR0_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR0_EC register field. */ +#define ALT_USB_HOST_HCCHAR0_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR0_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR0_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR0_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR0_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR0_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR0_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR0_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR0_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR0_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR0_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR0_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR0_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR0_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR0_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR0_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR0_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCCHAR0_CHDIS_E_INACT | 0x0 | No activity + * ALT_USB_HOST_HCCHAR0_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving data + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHDIS + * + * No activity + */ +#define ALT_USB_HOST_HCCHAR0_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHDIS + * + * Stop transmitting/receiving data + */ +#define ALT_USB_HOST_HCCHAR0_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR0_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR0_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR0_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR0_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR0_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR0_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR0_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR0_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR0_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR0_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR0_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR0_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled. This field is set by the application and + * cleared by the OTG host. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR0_CHENA_E_NOTRDY | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR0_CHENA_E_RDY | 0x1 | Indicates that the descriptor structure and data + * : | | buffer with data is setup and this channel can + * : | | access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR0_CHENA_E_NOTRDY 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHENA + * + * Indicates that the descriptor structure and data buffer with data is setup and + * this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR0_CHENA_E_RDY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR0_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR0_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR0_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR0_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR0_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR0_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR0_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR0_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR0_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR0_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR0_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR0_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR0_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR0_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR0. + */ +struct ALT_USB_HOST_HCCHAR0_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count Error Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR0. */ +typedef volatile struct ALT_USB_HOST_HCCHAR0_s ALT_USB_HOST_HCCHAR0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR0 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR0_OFST 0x100 +/* The address of the ALT_USB_HOST_HCCHAR0 register. */ +#define ALT_USB_HOST_HCCHAR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR0_OFST)) + +/* + * Register : Host Channel 0 Split Control Register - hcsplt0 + * + * Channel_number 0 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT0_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT0_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT0_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT0_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT0_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT0_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT0_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT0_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT0_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT0_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT0_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT0_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT0_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT0_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT0_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT0_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT0_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT0_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT0_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT0_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT0_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT0_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT0_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT0_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT0_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT0_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT0_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT0_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT0_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT0_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT0_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT0_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT0_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT0_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT0_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT0_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT0_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT0_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT0_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT0_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT0_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT0_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT0_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT0_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT0_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT0_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT0_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT0_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT0_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT0_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT0_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT0_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT0_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT0_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT0_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT0_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT0_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT0_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT0_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT0_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT0_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT0_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT0_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT0_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT0_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT0_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT0_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT0_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT0_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT0. + */ +struct ALT_USB_HOST_HCSPLT0_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT0. */ +typedef volatile struct ALT_USB_HOST_HCSPLT0_s ALT_USB_HOST_HCSPLT0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT0 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT0_OFST 0x104 +/* The address of the ALT_USB_HOST_HCSPLT0 register. */ +#define ALT_USB_HOST_HCSPLT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT0_OFST)) + +/* + * Register : Host Channel 0 Interrupt Register - hcint0 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT0_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT0_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT0_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT0_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT0_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT0_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT0_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT0_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT0_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT0_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT0_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT0_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT0_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT0_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT0_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT0_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT0_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT0_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT0_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT0_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT0_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT0_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT0_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT0_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT0_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT0_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT0_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT0_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT0_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT0_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT0_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_AHBERR register field. */ +#define ALT_USB_HOST_HCINT0_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_AHBERR register field. */ +#define ALT_USB_HOST_HCINT0_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT0_AHBERR register field. */ +#define ALT_USB_HOST_HCINT0_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT0_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT0_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT0_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT0_AHBERR register field. */ +#define ALT_USB_HOST_HCINT0_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT0_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT0_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT0_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT0_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT0_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_STALL register field. */ +#define ALT_USB_HOST_HCINT0_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_STALL register field. */ +#define ALT_USB_HOST_HCINT0_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT0_STALL register field. */ +#define ALT_USB_HOST_HCINT0_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_STALL register field value. */ +#define ALT_USB_HOST_HCINT0_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT0_STALL register field value. */ +#define ALT_USB_HOST_HCINT0_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT0_STALL register field. */ +#define ALT_USB_HOST_HCINT0_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT0_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT0_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT0_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT0_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT0_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT0_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_NAK register field. */ +#define ALT_USB_HOST_HCINT0_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_NAK register field. */ +#define ALT_USB_HOST_HCINT0_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT0_NAK register field. */ +#define ALT_USB_HOST_HCINT0_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_NAK register field value. */ +#define ALT_USB_HOST_HCINT0_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT0_NAK register field value. */ +#define ALT_USB_HOST_HCINT0_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT0_NAK register field. */ +#define ALT_USB_HOST_HCINT0_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT0_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT0_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT0_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT0_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT0_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT0_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_ACK register field. */ +#define ALT_USB_HOST_HCINT0_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_ACK register field. */ +#define ALT_USB_HOST_HCINT0_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT0_ACK register field. */ +#define ALT_USB_HOST_HCINT0_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_ACK register field value. */ +#define ALT_USB_HOST_HCINT0_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT0_ACK register field value. */ +#define ALT_USB_HOST_HCINT0_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT0_ACK register field. */ +#define ALT_USB_HOST_HCINT0_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT0_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT0_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT0_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT0_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT0_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT0_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_NYET register field. */ +#define ALT_USB_HOST_HCINT0_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_NYET register field. */ +#define ALT_USB_HOST_HCINT0_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT0_NYET register field. */ +#define ALT_USB_HOST_HCINT0_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_NYET register field value. */ +#define ALT_USB_HOST_HCINT0_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT0_NYET register field value. */ +#define ALT_USB_HOST_HCINT0_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT0_NYET register field. */ +#define ALT_USB_HOST_HCINT0_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT0_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT0_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT0_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT0_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT0_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT0_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XACTERR register field. */ +#define ALT_USB_HOST_HCINT0_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XACTERR register field. */ +#define ALT_USB_HOST_HCINT0_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT0_XACTERR register field. */ +#define ALT_USB_HOST_HCINT0_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT0_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT0_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT0_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT0_XACTERR register field. */ +#define ALT_USB_HOST_HCINT0_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT0_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT0_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT0_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT0_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT0_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT0_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_BBLERR register field. */ +#define ALT_USB_HOST_HCINT0_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_BBLERR register field. */ +#define ALT_USB_HOST_HCINT0_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT0_BBLERR register field. */ +#define ALT_USB_HOST_HCINT0_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT0_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT0_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT0_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT0_BBLERR register field. */ +#define ALT_USB_HOST_HCINT0_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT0_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT0_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT0_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT0_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT0_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT0_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT0_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT0_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT0_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT0_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT0_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT0_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT0_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT0_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT0_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT0_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT0_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT0_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT0_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT0_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT0_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT0_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT0_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT0_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT0_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT0_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT0_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT0_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT0_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT0_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT0_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT0_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT0_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT0_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT0_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT0_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT0_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT0_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT0_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT0_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT0_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT0_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT0_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT0. + */ +struct ALT_USB_HOST_HCINT0_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT0. */ +typedef volatile struct ALT_USB_HOST_HCINT0_s ALT_USB_HOST_HCINT0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT0 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT0_OFST 0x108 +/* The address of the ALT_USB_HOST_HCINT0 register. */ +#define ALT_USB_HOST_HCINT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT0_OFST)) + +/* + * Register : Host Channel 0 Interrupt Mask Register - hcintmsk0 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK0_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK0. + */ +struct ALT_USB_HOST_HCINTMSK0_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK0. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK0_s ALT_USB_HOST_HCINTMSK0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK0 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK0_OFST 0x10c +/* The address of the ALT_USB_HOST_HCINTMSK0 register. */ +#define ALT_USB_HOST_HCINTMSK0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK0_OFST)) + +/* + * Register : Host Channel 0 Transfer Size Register - hctsiz0 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * For an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ0_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ0_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ0_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ0_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ0_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ0_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ0_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ0_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ0_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ0_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ0_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ0_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ0_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ0_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ0_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ0_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ0_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ0_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ0_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_PID register field. */ +#define ALT_USB_HOST_HCTSIZ0_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_PID register field. */ +#define ALT_USB_HOST_HCTSIZ0_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ0_PID register field. */ +#define ALT_USB_HOST_HCTSIZ0_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ0_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ0_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ0_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ0_PID register field. */ +#define ALT_USB_HOST_HCTSIZ0_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ0_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ0_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ0_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ0_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ0_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ0_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ0_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ0_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ0_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ0_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ0_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ0_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ0_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ0_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ0_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ0_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ0_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ0_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ0_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ0. + */ +struct ALT_USB_HOST_HCTSIZ0_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ0. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ0_s ALT_USB_HOST_HCTSIZ0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ0 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ0_OFST 0x110 +/* The address of the ALT_USB_HOST_HCTSIZ0 register. */ +#define ALT_USB_HOST_HCTSIZ0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ0_OFST)) + +/* + * Register : Host Channel 0 DMA Address Register - hcdma0 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma0 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC nTD N nTD + * N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * + * 0 - 1 descriptor. + * + * 63 - 64 descriptors. + * + * This field indicates the current descriptor processed in the list. This field is + * updated both by application and the core. for example, if the application + * enables the channel after programming CTD=5, then the core will start processing + * the 6th descriptor. The address is obtained by adding a value of (8bytes*5=) + * 40(decimal) to DMAAddr. Isochronous: CTD for isochronous is based on the + * current frame/microframe value. Need to be set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */ +#define ALT_USB_HOST_HCDMA0_HCDMA0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */ +#define ALT_USB_HOST_HCDMA0_HCDMA0_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */ +#define ALT_USB_HOST_HCDMA0_HCDMA0_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA0_HCDMA0 register field value. */ +#define ALT_USB_HOST_HCDMA0_HCDMA0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA0_HCDMA0 register field value. */ +#define ALT_USB_HOST_HCDMA0_HCDMA0_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */ +#define ALT_USB_HOST_HCDMA0_HCDMA0_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA0_HCDMA0 field value from a register. */ +#define ALT_USB_HOST_HCDMA0_HCDMA0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA0_HCDMA0 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA0_HCDMA0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA0. + */ +struct ALT_USB_HOST_HCDMA0_s +{ + uint32_t hcdma0 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA0. */ +typedef volatile struct ALT_USB_HOST_HCDMA0_s ALT_USB_HOST_HCDMA0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA0 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA0_OFST 0x114 +/* The address of the ALT_USB_HOST_HCDMA0 register. */ +#define ALT_USB_HOST_HCDMA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA0_OFST)) + +/* + * Register : Host Channel 0 DMA Buffer Address Register - hcdmab0 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 0 DMA Buffer Address + * + */ +/* + * Field : Host Channel 0 DMA Buffer Address - hcdmab0 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */ +#define ALT_USB_HOST_HCDMAB0_HCDMAB0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */ +#define ALT_USB_HOST_HCDMAB0_HCDMAB0_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */ +#define ALT_USB_HOST_HCDMAB0_HCDMAB0_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value. */ +#define ALT_USB_HOST_HCDMAB0_HCDMAB0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value. */ +#define ALT_USB_HOST_HCDMAB0_HCDMAB0_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */ +#define ALT_USB_HOST_HCDMAB0_HCDMAB0_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB0_HCDMAB0 field value from a register. */ +#define ALT_USB_HOST_HCDMAB0_HCDMAB0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB0_HCDMAB0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB0. + */ +struct ALT_USB_HOST_HCDMAB0_s +{ + uint32_t hcdmab0 : 32; /* Host Channel 0 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB0. */ +typedef volatile struct ALT_USB_HOST_HCDMAB0_s ALT_USB_HOST_HCDMAB0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB0 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB0_OFST 0x118 +/* The address of the ALT_USB_HOST_HCDMAB0 register. */ +#define ALT_USB_HOST_HCDMAB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB0_OFST)) + +/* + * Register : Host Channel 1 Characteristics Register - hcchar1 + * + * Host Channel 1 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_MPS register field. */ +#define ALT_USB_HOST_HCCHAR1_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_MPS register field. */ +#define ALT_USB_HOST_HCCHAR1_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR1_MPS register field. */ +#define ALT_USB_HOST_HCCHAR1_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR1_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR1_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR1_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR1_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR1_MPS register field. */ +#define ALT_USB_HOST_HCCHAR1_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR1_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR1_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR1_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR1_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR1_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR1_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR1_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR1_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR1_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR1_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR1_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR1_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR1_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR1_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR1_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR1_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR1_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR1_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR1_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR1_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR1_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR1_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR1_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR1_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR1_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR1_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR1_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR1_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR1_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR1_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR1_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR1_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR1_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR1_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR1_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR1_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR1_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR1_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR1_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR1_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR1_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR1_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR1_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR1_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR1_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR1_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR1_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR1_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR1_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR1_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR1_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR1_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR1_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR1_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EC register field. */ +#define ALT_USB_HOST_HCCHAR1_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EC register field. */ +#define ALT_USB_HOST_HCCHAR1_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR1_EC register field. */ +#define ALT_USB_HOST_HCCHAR1_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR1_EC register field value. */ +#define ALT_USB_HOST_HCCHAR1_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EC register field value. */ +#define ALT_USB_HOST_HCCHAR1_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR1_EC register field. */ +#define ALT_USB_HOST_HCCHAR1_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR1_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR1_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR1_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR1_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR1_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR1_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR1_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR1_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR1_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR1_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR1_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR1_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR1_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR1_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR1_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR1_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR1_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR1_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR1_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR1_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR1_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR1_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR1_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR1_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR1_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR1_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR1_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR1_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR1_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR1_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR1_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR1_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR1_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR1_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR1_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR1_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR1_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR1_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR1_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR1_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR1_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR1_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR1_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR1_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR1_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR1_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR1_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR1_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR1_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR1_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR1. + */ +struct ALT_USB_HOST_HCCHAR1_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR1. */ +typedef volatile struct ALT_USB_HOST_HCCHAR1_s ALT_USB_HOST_HCCHAR1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR1 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR1_OFST 0x120 +/* The address of the ALT_USB_HOST_HCCHAR1 register. */ +#define ALT_USB_HOST_HCCHAR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR1_OFST)) + +/* + * Register : Host Channel 1 Split Control Register - hcsplt1 + * + * Channel_number 1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT1_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT1_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT1_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT1_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT1_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT1_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT1_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT1_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT1_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT1_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT1_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT1_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT1_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT1_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT1_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT1_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT1_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT1_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT1_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT1_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT1_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT1_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT1_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT1_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT1_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT1_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT1_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT1_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT1_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT1_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT1_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT1_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT1_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT1_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT1_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT1_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT1_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT1_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT1_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT1_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT1_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT1_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT1_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT1_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT1_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT1_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT1_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT1_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT1_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT1_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT1_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT1_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT1_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT1_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT1_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT1_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT1_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT1_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT1_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT1_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT1_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT1_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT1_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT1_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT1_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT1_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT1_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT1_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT1_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT1. + */ +struct ALT_USB_HOST_HCSPLT1_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT1. */ +typedef volatile struct ALT_USB_HOST_HCSPLT1_s ALT_USB_HOST_HCSPLT1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT1 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT1_OFST 0x124 +/* The address of the ALT_USB_HOST_HCSPLT1 register. */ +#define ALT_USB_HOST_HCSPLT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT1_OFST)) + +/* + * Register : Host Channel 1 Interrupt Register - hcint1 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT1_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT1_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT1_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT1_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT1_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT1_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT1_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT1_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT1_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT1_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT1_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT1_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT1_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT1_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT1_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT1_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT1_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT1_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT1_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT1_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT1_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT1_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT1_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT1_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT1_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT1_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT1_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT1_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT1_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT1_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT1_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_AHBERR register field. */ +#define ALT_USB_HOST_HCINT1_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_AHBERR register field. */ +#define ALT_USB_HOST_HCINT1_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT1_AHBERR register field. */ +#define ALT_USB_HOST_HCINT1_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT1_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT1_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT1_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT1_AHBERR register field. */ +#define ALT_USB_HOST_HCINT1_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT1_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT1_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT1_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT1_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT1_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_STALL register field. */ +#define ALT_USB_HOST_HCINT1_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_STALL register field. */ +#define ALT_USB_HOST_HCINT1_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT1_STALL register field. */ +#define ALT_USB_HOST_HCINT1_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_STALL register field value. */ +#define ALT_USB_HOST_HCINT1_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT1_STALL register field value. */ +#define ALT_USB_HOST_HCINT1_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT1_STALL register field. */ +#define ALT_USB_HOST_HCINT1_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT1_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT1_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT1_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT1_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT1_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT1_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_NAK register field. */ +#define ALT_USB_HOST_HCINT1_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_NAK register field. */ +#define ALT_USB_HOST_HCINT1_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT1_NAK register field. */ +#define ALT_USB_HOST_HCINT1_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_NAK register field value. */ +#define ALT_USB_HOST_HCINT1_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT1_NAK register field value. */ +#define ALT_USB_HOST_HCINT1_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT1_NAK register field. */ +#define ALT_USB_HOST_HCINT1_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT1_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT1_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT1_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT1_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT1_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT1_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_ACK register field. */ +#define ALT_USB_HOST_HCINT1_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_ACK register field. */ +#define ALT_USB_HOST_HCINT1_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT1_ACK register field. */ +#define ALT_USB_HOST_HCINT1_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_ACK register field value. */ +#define ALT_USB_HOST_HCINT1_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT1_ACK register field value. */ +#define ALT_USB_HOST_HCINT1_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT1_ACK register field. */ +#define ALT_USB_HOST_HCINT1_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT1_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT1_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT1_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT1_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT1_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT1_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_NYET register field. */ +#define ALT_USB_HOST_HCINT1_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_NYET register field. */ +#define ALT_USB_HOST_HCINT1_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT1_NYET register field. */ +#define ALT_USB_HOST_HCINT1_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_NYET register field value. */ +#define ALT_USB_HOST_HCINT1_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT1_NYET register field value. */ +#define ALT_USB_HOST_HCINT1_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT1_NYET register field. */ +#define ALT_USB_HOST_HCINT1_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT1_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT1_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT1_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT1_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT1_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT1_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XACTERR register field. */ +#define ALT_USB_HOST_HCINT1_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XACTERR register field. */ +#define ALT_USB_HOST_HCINT1_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT1_XACTERR register field. */ +#define ALT_USB_HOST_HCINT1_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT1_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT1_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT1_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT1_XACTERR register field. */ +#define ALT_USB_HOST_HCINT1_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT1_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT1_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT1_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT1_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT1_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT1_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_BBLERR register field. */ +#define ALT_USB_HOST_HCINT1_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_BBLERR register field. */ +#define ALT_USB_HOST_HCINT1_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT1_BBLERR register field. */ +#define ALT_USB_HOST_HCINT1_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT1_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT1_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT1_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT1_BBLERR register field. */ +#define ALT_USB_HOST_HCINT1_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT1_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT1_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT1_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT1_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT1_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT1_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT1_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT1_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT1_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT1_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT1_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT1_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT1_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT1_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT1_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT1_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT1_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT1_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT1_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT1_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT1_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT1_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT1_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT1_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT1_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT1_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT1_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT1_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT1_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT1_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT1_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT1_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT1_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT1_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT1_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT1_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT1_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT1_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT1_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT1_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT1_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT1_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT1_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT1. + */ +struct ALT_USB_HOST_HCINT1_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT1. */ +typedef volatile struct ALT_USB_HOST_HCINT1_s ALT_USB_HOST_HCINT1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT1 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT1_OFST 0x128 +/* The address of the ALT_USB_HOST_HCINT1 register. */ +#define ALT_USB_HOST_HCINT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT1_OFST)) + +/* + * Register : Host Channel 1 Interrupt Mask Register - hcintmsk1 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK1_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK1. + */ +struct ALT_USB_HOST_HCINTMSK1_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK1. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK1_s ALT_USB_HOST_HCINTMSK1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK1 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK1_OFST 0x12c +/* The address of the ALT_USB_HOST_HCINTMSK1 register. */ +#define ALT_USB_HOST_HCINTMSK1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK1_OFST)) + +/* + * Register : Host Channel 1 Transfer Size Register - hctsiz1 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ1_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ1_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ1_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ1_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ1_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ1_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ1_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ1_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ1_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ1_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ1_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ1_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ1_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ1_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ1_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ1_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ1_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ1_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_PID register field. */ +#define ALT_USB_HOST_HCTSIZ1_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_PID register field. */ +#define ALT_USB_HOST_HCTSIZ1_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ1_PID register field. */ +#define ALT_USB_HOST_HCTSIZ1_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ1_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ1_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ1_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ1_PID register field. */ +#define ALT_USB_HOST_HCTSIZ1_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ1_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ1_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ1_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ1_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ1_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ1_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ1_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ1_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ1_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ1_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ1_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ1_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ1_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ1_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ1_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ1_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ1_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ1_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ1_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ1. + */ +struct ALT_USB_HOST_HCTSIZ1_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ1. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ1_s ALT_USB_HOST_HCTSIZ1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ1 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ1_OFST 0x130 +/* The address of the ALT_USB_HOST_HCTSIZ1 register. */ +#define ALT_USB_HOST_HCTSIZ1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ1_OFST)) + +/* + * Register : Host Channel 1 DMA Address Register - hcdma1 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma1 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */ +#define ALT_USB_HOST_HCDMA1_HCDMA1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */ +#define ALT_USB_HOST_HCDMA1_HCDMA1_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */ +#define ALT_USB_HOST_HCDMA1_HCDMA1_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA1_HCDMA1 register field value. */ +#define ALT_USB_HOST_HCDMA1_HCDMA1_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA1_HCDMA1 register field value. */ +#define ALT_USB_HOST_HCDMA1_HCDMA1_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */ +#define ALT_USB_HOST_HCDMA1_HCDMA1_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA1_HCDMA1 field value from a register. */ +#define ALT_USB_HOST_HCDMA1_HCDMA1_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA1_HCDMA1 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA1_HCDMA1_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA1. + */ +struct ALT_USB_HOST_HCDMA1_s +{ + uint32_t hcdma1 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA1. */ +typedef volatile struct ALT_USB_HOST_HCDMA1_s ALT_USB_HOST_HCDMA1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA1 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA1_OFST 0x134 +/* The address of the ALT_USB_HOST_HCDMA1 register. */ +#define ALT_USB_HOST_HCDMA1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA1_OFST)) + +/* + * Register : Host Channel 1 DMA Buffer Address Register - hcdmab1 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 1 DMA Buffer Address + * + */ +/* + * Field : Host Channel 1 DMA Buffer Address - hcdmab1 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */ +#define ALT_USB_HOST_HCDMAB1_HCDMAB1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */ +#define ALT_USB_HOST_HCDMAB1_HCDMAB1_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */ +#define ALT_USB_HOST_HCDMAB1_HCDMAB1_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value. */ +#define ALT_USB_HOST_HCDMAB1_HCDMAB1_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value. */ +#define ALT_USB_HOST_HCDMAB1_HCDMAB1_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */ +#define ALT_USB_HOST_HCDMAB1_HCDMAB1_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB1_HCDMAB1 field value from a register. */ +#define ALT_USB_HOST_HCDMAB1_HCDMAB1_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB1_HCDMAB1_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB1. + */ +struct ALT_USB_HOST_HCDMAB1_s +{ + uint32_t hcdmab1 : 32; /* Host Channel 1 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB1. */ +typedef volatile struct ALT_USB_HOST_HCDMAB1_s ALT_USB_HOST_HCDMAB1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB1 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB1_OFST 0x138 +/* The address of the ALT_USB_HOST_HCDMAB1 register. */ +#define ALT_USB_HOST_HCDMAB1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB1_OFST)) + +/* + * Register : Host Channel 2 Characteristics Register - hcchar2 + * + * Host Channel 2 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_MPS register field. */ +#define ALT_USB_HOST_HCCHAR2_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_MPS register field. */ +#define ALT_USB_HOST_HCCHAR2_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR2_MPS register field. */ +#define ALT_USB_HOST_HCCHAR2_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR2_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR2_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR2_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR2_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR2_MPS register field. */ +#define ALT_USB_HOST_HCCHAR2_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR2_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR2_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR2_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR2_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR2_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR2_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR2_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR2_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR2_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR2_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR2_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR2_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR2_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR2_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR2_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR2_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR2_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR2_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR2_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR2_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR2_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR2_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR2_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR2_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR2_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR2_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR2_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR2_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR2_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR2_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR2_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR2_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR2_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR2_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR2_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR2_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR2_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR2_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR2_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR2_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR2_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR2_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR2_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR2_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR2_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR2_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR2_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR2_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR2_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR2_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR2_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR2_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR2_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR2_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EC register field. */ +#define ALT_USB_HOST_HCCHAR2_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EC register field. */ +#define ALT_USB_HOST_HCCHAR2_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR2_EC register field. */ +#define ALT_USB_HOST_HCCHAR2_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR2_EC register field value. */ +#define ALT_USB_HOST_HCCHAR2_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EC register field value. */ +#define ALT_USB_HOST_HCCHAR2_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR2_EC register field. */ +#define ALT_USB_HOST_HCCHAR2_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR2_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR2_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR2_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR2_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR2_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR2_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR2_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR2_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR2_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR2_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR2_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR2_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR2_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR2_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR2_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR2_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR2_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR2_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR2_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR2_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR2_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR2_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR2_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR2_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR2_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR2_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR2_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR2_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR2_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR2_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR2_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR2_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR2_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR2_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR2_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR2_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR2_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR2_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR2_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR2_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR2_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR2_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR2_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR2_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR2_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR2_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR2_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR2_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR2_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR2_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR2. + */ +struct ALT_USB_HOST_HCCHAR2_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR2. */ +typedef volatile struct ALT_USB_HOST_HCCHAR2_s ALT_USB_HOST_HCCHAR2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR2 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR2_OFST 0x140 +/* The address of the ALT_USB_HOST_HCCHAR2 register. */ +#define ALT_USB_HOST_HCCHAR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR2_OFST)) + +/* + * Register : Host Channel 2 Split Control Register - hcsplt2 + * + * Channel_number 2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT2_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT2_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT2_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT2_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT2_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT2_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT2_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT2_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT2_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT2_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT2_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT2_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT2_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT2_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT2_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT2_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT2_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT2_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT2_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT2_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT2_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT2_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT2_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT2_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT2_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT2_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT2_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT2_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT2_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT2_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT2_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT2_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT2_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT2_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT2_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT2_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT2_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT2_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT2_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT2_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT2_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT2_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT2_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT2_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT2_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT2_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT2_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT2_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT2_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT2_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT2_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT2_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT2_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT2_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT2_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT2_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT2_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT2_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT2_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT2_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT2_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT2_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT2_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT2_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT2_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT2_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT2_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT2_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT2_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT2. + */ +struct ALT_USB_HOST_HCSPLT2_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT2. */ +typedef volatile struct ALT_USB_HOST_HCSPLT2_s ALT_USB_HOST_HCSPLT2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT2 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT2_OFST 0x144 +/* The address of the ALT_USB_HOST_HCSPLT2 register. */ +#define ALT_USB_HOST_HCSPLT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT2_OFST)) + +/* + * Register : Host Channel 2 Interrupt Register - hcint2 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT2_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT2_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT2_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT2_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT2_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT2_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT2_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT2_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT2_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT2_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT2_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT2_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT2_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT2_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT2_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT2_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT2_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT2_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT2_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT2_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT2_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT2_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT2_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT2_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT2_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT2_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT2_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT2_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT2_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT2_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT2_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_AHBERR register field. */ +#define ALT_USB_HOST_HCINT2_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_AHBERR register field. */ +#define ALT_USB_HOST_HCINT2_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT2_AHBERR register field. */ +#define ALT_USB_HOST_HCINT2_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT2_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT2_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT2_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT2_AHBERR register field. */ +#define ALT_USB_HOST_HCINT2_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT2_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT2_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT2_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT2_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT2_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_STALL register field. */ +#define ALT_USB_HOST_HCINT2_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_STALL register field. */ +#define ALT_USB_HOST_HCINT2_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT2_STALL register field. */ +#define ALT_USB_HOST_HCINT2_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_STALL register field value. */ +#define ALT_USB_HOST_HCINT2_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT2_STALL register field value. */ +#define ALT_USB_HOST_HCINT2_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT2_STALL register field. */ +#define ALT_USB_HOST_HCINT2_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT2_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT2_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT2_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT2_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT2_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT2_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_NAK register field. */ +#define ALT_USB_HOST_HCINT2_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_NAK register field. */ +#define ALT_USB_HOST_HCINT2_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT2_NAK register field. */ +#define ALT_USB_HOST_HCINT2_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_NAK register field value. */ +#define ALT_USB_HOST_HCINT2_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT2_NAK register field value. */ +#define ALT_USB_HOST_HCINT2_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT2_NAK register field. */ +#define ALT_USB_HOST_HCINT2_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT2_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT2_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT2_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT2_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT2_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT2_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_ACK register field. */ +#define ALT_USB_HOST_HCINT2_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_ACK register field. */ +#define ALT_USB_HOST_HCINT2_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT2_ACK register field. */ +#define ALT_USB_HOST_HCINT2_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_ACK register field value. */ +#define ALT_USB_HOST_HCINT2_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT2_ACK register field value. */ +#define ALT_USB_HOST_HCINT2_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT2_ACK register field. */ +#define ALT_USB_HOST_HCINT2_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT2_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT2_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT2_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT2_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT2_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT2_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_NYET register field. */ +#define ALT_USB_HOST_HCINT2_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_NYET register field. */ +#define ALT_USB_HOST_HCINT2_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT2_NYET register field. */ +#define ALT_USB_HOST_HCINT2_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_NYET register field value. */ +#define ALT_USB_HOST_HCINT2_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT2_NYET register field value. */ +#define ALT_USB_HOST_HCINT2_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT2_NYET register field. */ +#define ALT_USB_HOST_HCINT2_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT2_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT2_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT2_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT2_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT2_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT2_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XACTERR register field. */ +#define ALT_USB_HOST_HCINT2_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XACTERR register field. */ +#define ALT_USB_HOST_HCINT2_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT2_XACTERR register field. */ +#define ALT_USB_HOST_HCINT2_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT2_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT2_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT2_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT2_XACTERR register field. */ +#define ALT_USB_HOST_HCINT2_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT2_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT2_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT2_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT2_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT2_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT2_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_BBLERR register field. */ +#define ALT_USB_HOST_HCINT2_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_BBLERR register field. */ +#define ALT_USB_HOST_HCINT2_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT2_BBLERR register field. */ +#define ALT_USB_HOST_HCINT2_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT2_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT2_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT2_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT2_BBLERR register field. */ +#define ALT_USB_HOST_HCINT2_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT2_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT2_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT2_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT2_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT2_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT2_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT2_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT2_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT2_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT2_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT2_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT2_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT2_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT2_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT2_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT2_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT2_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT2_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT2_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT2_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT2_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT2_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT2_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT2_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT2_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT2_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT2_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT2_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT2_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT2_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT2_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT2_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT2_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT2_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT2_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT2_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT2_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT2_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT2_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT2_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT2_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT2_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT2_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT2. + */ +struct ALT_USB_HOST_HCINT2_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT2. */ +typedef volatile struct ALT_USB_HOST_HCINT2_s ALT_USB_HOST_HCINT2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT2 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT2_OFST 0x148 +/* The address of the ALT_USB_HOST_HCINT2 register. */ +#define ALT_USB_HOST_HCINT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT2_OFST)) + +/* + * Register : Host Channel 2 Interrupt Mask Register - hcintmsk2 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK2_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK2. + */ +struct ALT_USB_HOST_HCINTMSK2_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK2. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK2_s ALT_USB_HOST_HCINTMSK2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK2 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK2_OFST 0x14c +/* The address of the ALT_USB_HOST_HCINTMSK2 register. */ +#define ALT_USB_HOST_HCINTMSK2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK2_OFST)) + +/* + * Register : Host Channel 2 Transfer Size Register - hctsiz2 + * + * Buffer DMA Mode. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ2_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ2_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ2_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ2_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ2_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ2_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ2_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ2_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ2_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ2_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ2_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ2_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ2_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ2_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ2_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ2_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ2_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ2_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_PID register field. */ +#define ALT_USB_HOST_HCTSIZ2_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_PID register field. */ +#define ALT_USB_HOST_HCTSIZ2_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ2_PID register field. */ +#define ALT_USB_HOST_HCTSIZ2_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ2_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ2_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ2_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ2_PID register field. */ +#define ALT_USB_HOST_HCTSIZ2_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ2_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ2_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ2_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ2_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ2_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ2_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ2_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ2_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ2_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ2_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ2_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ2_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ2_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ2_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ2_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ2_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ2_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ2_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ2_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ2. + */ +struct ALT_USB_HOST_HCTSIZ2_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ2. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ2_s ALT_USB_HOST_HCTSIZ2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ2 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ2_OFST 0x150 +/* The address of the ALT_USB_HOST_HCTSIZ2 register. */ +#define ALT_USB_HOST_HCTSIZ2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ2_OFST)) + +/* + * Register : Host Channel 2 DMA Address Register - hcdma2 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma2 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */ +#define ALT_USB_HOST_HCDMA2_HCDMA2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */ +#define ALT_USB_HOST_HCDMA2_HCDMA2_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */ +#define ALT_USB_HOST_HCDMA2_HCDMA2_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA2_HCDMA2 register field value. */ +#define ALT_USB_HOST_HCDMA2_HCDMA2_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA2_HCDMA2 register field value. */ +#define ALT_USB_HOST_HCDMA2_HCDMA2_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */ +#define ALT_USB_HOST_HCDMA2_HCDMA2_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA2_HCDMA2 field value from a register. */ +#define ALT_USB_HOST_HCDMA2_HCDMA2_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA2_HCDMA2 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA2_HCDMA2_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA2. + */ +struct ALT_USB_HOST_HCDMA2_s +{ + uint32_t hcdma2 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA2. */ +typedef volatile struct ALT_USB_HOST_HCDMA2_s ALT_USB_HOST_HCDMA2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA2 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA2_OFST 0x154 +/* The address of the ALT_USB_HOST_HCDMA2 register. */ +#define ALT_USB_HOST_HCDMA2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA2_OFST)) + +/* + * Register : Host Channel 2 DMA Buffer Address Register - hcdmab2 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 2 DMA Buffer Address + * + */ +/* + * Field : Host Channel 2 DMA Buffer Address - hcdmab2 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */ +#define ALT_USB_HOST_HCDMAB2_HCDMAB2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */ +#define ALT_USB_HOST_HCDMAB2_HCDMAB2_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */ +#define ALT_USB_HOST_HCDMAB2_HCDMAB2_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value. */ +#define ALT_USB_HOST_HCDMAB2_HCDMAB2_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value. */ +#define ALT_USB_HOST_HCDMAB2_HCDMAB2_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */ +#define ALT_USB_HOST_HCDMAB2_HCDMAB2_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB2_HCDMAB2 field value from a register. */ +#define ALT_USB_HOST_HCDMAB2_HCDMAB2_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB2_HCDMAB2_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB2. + */ +struct ALT_USB_HOST_HCDMAB2_s +{ + uint32_t hcdmab2 : 32; /* Host Channel 2 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB2. */ +typedef volatile struct ALT_USB_HOST_HCDMAB2_s ALT_USB_HOST_HCDMAB2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB2 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB2_OFST 0x158 +/* The address of the ALT_USB_HOST_HCDMAB2 register. */ +#define ALT_USB_HOST_HCDMAB2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB2_OFST)) + +/* + * Register : Host Channel 3 Characteristics Register - hcchar3 + * + * Channel_number: 3. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count Error Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_MPS register field. */ +#define ALT_USB_HOST_HCCHAR3_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_MPS register field. */ +#define ALT_USB_HOST_HCCHAR3_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR3_MPS register field. */ +#define ALT_USB_HOST_HCCHAR3_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR3_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR3_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR3_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR3_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR3_MPS register field. */ +#define ALT_USB_HOST_HCCHAR3_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR3_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR3_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR3_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR3_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR3_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR3_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR3_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR3_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR3_EPDIR_E_OUTDIR | 0x0 | OUT + * ALT_USB_HOST_HCCHAR3_EPDIR_E_INDIR | 0x1 | IN + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPDIR + * + * OUT + */ +#define ALT_USB_HOST_HCCHAR3_EPDIR_E_OUTDIR 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPDIR + * + * IN + */ +#define ALT_USB_HOST_HCCHAR3_EPDIR_E_INDIR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR3_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR3_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR3_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR3_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR3_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR3_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR3_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR3_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR3_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR3_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR3_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is Set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCCHAR3_LSPDDEV_E_NONLOWSPEED | 0x0 | Communicating with non lowspeed + * ALT_USB_HOST_HCCHAR3_LSPDDEV_E_LOWSPEED | 0x1 | Communicating with lowspeed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_LSPDDEV + * + * Communicating with non lowspeed + */ +#define ALT_USB_HOST_HCCHAR3_LSPDDEV_E_NONLOWSPEED 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_LSPDDEV + * + * Communicating with lowspeed + */ +#define ALT_USB_HOST_HCCHAR3_LSPDDEV_E_LOWSPEED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR3_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR3_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR3_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR3_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR3_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR3_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR3_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR3_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR3_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR3_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR3_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR3_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR3_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR3_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR3_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR3_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR3_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR3_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR3_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count Error Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be Set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR3_EC_E_RSVD | 0x0 | Reserved This field yields undefined results + * ALT_USB_HOST_HCCHAR3_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR3_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR3_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC + * + * Reserved This field yields undefined results + */ +#define ALT_USB_HOST_HCCHAR3_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR3_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR3_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR3_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EC register field. */ +#define ALT_USB_HOST_HCCHAR3_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EC register field. */ +#define ALT_USB_HOST_HCCHAR3_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR3_EC register field. */ +#define ALT_USB_HOST_HCCHAR3_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR3_EC register field value. */ +#define ALT_USB_HOST_HCCHAR3_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EC register field value. */ +#define ALT_USB_HOST_HCCHAR3_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR3_EC register field. */ +#define ALT_USB_HOST_HCCHAR3_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR3_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR3_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR3_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR3_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR3_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR3_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR3_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR3_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR3_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR3_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR3_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR3_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR3_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR3_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR3_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR3_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCCHAR3_CHDIS_E_INACT | 0x0 | No activity + * ALT_USB_HOST_HCCHAR3_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving data + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHDIS + * + * No activity + */ +#define ALT_USB_HOST_HCCHAR3_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHDIS + * + * Stop transmitting/receiving data + */ +#define ALT_USB_HOST_HCCHAR3_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR3_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR3_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR3_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR3_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR3_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR3_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR3_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR3_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR3_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR3_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR3_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR3_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled. This field is set by the application and + * cleared by the OTG host. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR3_CHENA_E_NOTRDY | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR3_CHENA_E_RDY | 0x1 | Indicates that the descriptor structure and data + * : | | buffer with data is setup and this channel can + * : | | access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR3_CHENA_E_NOTRDY 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHENA + * + * Indicates that the descriptor structure and data buffer with data is setup and + * this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR3_CHENA_E_RDY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR3_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR3_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR3_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR3_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR3_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR3_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR3_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR3_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR3_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR3_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR3_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR3_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR3_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR3_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR3. + */ +struct ALT_USB_HOST_HCCHAR3_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count Error Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR3. */ +typedef volatile struct ALT_USB_HOST_HCCHAR3_s ALT_USB_HOST_HCCHAR3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR3 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR3_OFST 0x160 +/* The address of the ALT_USB_HOST_HCCHAR3 register. */ +#define ALT_USB_HOST_HCCHAR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR3_OFST)) + +/* + * Register : Host Channel 3 Split Control Register - hcsplt3 + * + * Channel_number 3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT3_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT3_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT3_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT3_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT3_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT3_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT3_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT3_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT3_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT3_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT3_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT3_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT3_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT3_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT3_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT3_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT3_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT3_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT3_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT3_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT3_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT3_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT3_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT3_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT3_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT3_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT3_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT3_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT3_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT3_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT3_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT3_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT3_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT3_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT3_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT3_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT3_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT3_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT3_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT3_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT3_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT3_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT3_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT3_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT3_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT3_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT3_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT3_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT3_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT3_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT3_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT3_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT3_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT3_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT3_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT3_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT3_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT3_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT3_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT3_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT3_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT3_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT3_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT3_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT3_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT3_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT3_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT3_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT3_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT3. + */ +struct ALT_USB_HOST_HCSPLT3_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT3. */ +typedef volatile struct ALT_USB_HOST_HCSPLT3_s ALT_USB_HOST_HCSPLT3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT3 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT3_OFST 0x164 +/* The address of the ALT_USB_HOST_HCSPLT3 register. */ +#define ALT_USB_HOST_HCSPLT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT3_OFST)) + +/* + * Register : Host Channel 3 Interrupt Register - hcint3 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT3_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT3_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT3_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT3_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT3_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT3_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT3_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT3_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT3_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT3_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT3_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT3_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT3_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT3_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT3_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT3_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT3_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT3_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT3_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT3_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT3_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT3_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT3_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT3_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT3_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT3_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT3_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT3_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT3_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT3_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT3_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_AHBERR register field. */ +#define ALT_USB_HOST_HCINT3_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_AHBERR register field. */ +#define ALT_USB_HOST_HCINT3_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT3_AHBERR register field. */ +#define ALT_USB_HOST_HCINT3_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT3_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT3_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT3_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT3_AHBERR register field. */ +#define ALT_USB_HOST_HCINT3_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT3_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT3_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT3_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT3_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT3_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_STALL register field. */ +#define ALT_USB_HOST_HCINT3_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_STALL register field. */ +#define ALT_USB_HOST_HCINT3_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT3_STALL register field. */ +#define ALT_USB_HOST_HCINT3_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_STALL register field value. */ +#define ALT_USB_HOST_HCINT3_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT3_STALL register field value. */ +#define ALT_USB_HOST_HCINT3_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT3_STALL register field. */ +#define ALT_USB_HOST_HCINT3_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT3_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT3_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT3_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT3_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT3_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT3_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_NAK register field. */ +#define ALT_USB_HOST_HCINT3_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_NAK register field. */ +#define ALT_USB_HOST_HCINT3_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT3_NAK register field. */ +#define ALT_USB_HOST_HCINT3_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_NAK register field value. */ +#define ALT_USB_HOST_HCINT3_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT3_NAK register field value. */ +#define ALT_USB_HOST_HCINT3_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT3_NAK register field. */ +#define ALT_USB_HOST_HCINT3_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT3_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT3_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT3_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT3_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT3_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT3_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_ACK register field. */ +#define ALT_USB_HOST_HCINT3_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_ACK register field. */ +#define ALT_USB_HOST_HCINT3_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT3_ACK register field. */ +#define ALT_USB_HOST_HCINT3_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_ACK register field value. */ +#define ALT_USB_HOST_HCINT3_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT3_ACK register field value. */ +#define ALT_USB_HOST_HCINT3_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT3_ACK register field. */ +#define ALT_USB_HOST_HCINT3_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT3_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT3_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT3_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT3_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT3_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT3_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_NYET register field. */ +#define ALT_USB_HOST_HCINT3_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_NYET register field. */ +#define ALT_USB_HOST_HCINT3_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT3_NYET register field. */ +#define ALT_USB_HOST_HCINT3_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_NYET register field value. */ +#define ALT_USB_HOST_HCINT3_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT3_NYET register field value. */ +#define ALT_USB_HOST_HCINT3_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT3_NYET register field. */ +#define ALT_USB_HOST_HCINT3_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT3_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT3_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT3_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT3_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT3_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT3_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XACTERR register field. */ +#define ALT_USB_HOST_HCINT3_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XACTERR register field. */ +#define ALT_USB_HOST_HCINT3_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT3_XACTERR register field. */ +#define ALT_USB_HOST_HCINT3_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT3_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT3_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT3_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT3_XACTERR register field. */ +#define ALT_USB_HOST_HCINT3_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT3_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT3_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT3_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT3_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT3_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT3_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_BBLERR register field. */ +#define ALT_USB_HOST_HCINT3_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_BBLERR register field. */ +#define ALT_USB_HOST_HCINT3_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT3_BBLERR register field. */ +#define ALT_USB_HOST_HCINT3_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT3_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT3_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT3_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT3_BBLERR register field. */ +#define ALT_USB_HOST_HCINT3_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT3_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT3_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT3_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT3_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT3_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT3_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT3_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT3_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT3_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT3_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT3_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT3_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT3_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT3_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT3_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT3_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT3_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT3_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT3_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT3_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT3_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT3_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT3_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT3_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT3_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT3_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT3_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT3_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT3_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT3_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT3_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT3_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT3_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT3_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT3_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT3_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT3_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT3_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT3_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT3_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT3_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT3_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT3_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT3. + */ +struct ALT_USB_HOST_HCINT3_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT3. */ +typedef volatile struct ALT_USB_HOST_HCINT3_s ALT_USB_HOST_HCINT3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT3 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT3_OFST 0x168 +/* The address of the ALT_USB_HOST_HCINT3 register. */ +#define ALT_USB_HOST_HCINT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT3_OFST)) + +/* + * Register : Host Channel 3 Interrupt Mask Registe - hcintmsk3 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK3_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK3. + */ +struct ALT_USB_HOST_HCINTMSK3_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK3. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK3_s ALT_USB_HOST_HCINTMSK3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK3 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK3_OFST 0x16c +/* The address of the ALT_USB_HOST_HCINTMSK3 register. */ +#define ALT_USB_HOST_HCINTMSK3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK3_OFST)) + +/* + * Register : Host Channel 3 Transfer Size Registe - hctsiz3 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ3_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ3_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ3_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ3_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ3_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ3_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ3_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ3_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ3_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ3_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ3_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ3_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ3_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ3_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ3_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ3_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ3_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ3_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_PID register field. */ +#define ALT_USB_HOST_HCTSIZ3_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_PID register field. */ +#define ALT_USB_HOST_HCTSIZ3_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ3_PID register field. */ +#define ALT_USB_HOST_HCTSIZ3_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ3_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ3_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ3_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ3_PID register field. */ +#define ALT_USB_HOST_HCTSIZ3_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ3_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ3_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ3_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ3_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ3_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ3_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ3_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ3_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ3_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ3_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ3_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ3_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ3_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ3_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ3_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ3_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ3_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ3_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ3_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ3. + */ +struct ALT_USB_HOST_HCTSIZ3_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ3. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ3_s ALT_USB_HOST_HCTSIZ3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ3 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ3_OFST 0x170 +/* The address of the ALT_USB_HOST_HCTSIZ3 register. */ +#define ALT_USB_HOST_HCTSIZ3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ3_OFST)) + +/* + * Register : Host Channel 3 DMA Address Register - hcdma3 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma3 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */ +#define ALT_USB_HOST_HCDMA3_HCDMA3_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */ +#define ALT_USB_HOST_HCDMA3_HCDMA3_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */ +#define ALT_USB_HOST_HCDMA3_HCDMA3_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA3_HCDMA3 register field value. */ +#define ALT_USB_HOST_HCDMA3_HCDMA3_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA3_HCDMA3 register field value. */ +#define ALT_USB_HOST_HCDMA3_HCDMA3_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */ +#define ALT_USB_HOST_HCDMA3_HCDMA3_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA3_HCDMA3 field value from a register. */ +#define ALT_USB_HOST_HCDMA3_HCDMA3_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA3_HCDMA3 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA3_HCDMA3_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA3. + */ +struct ALT_USB_HOST_HCDMA3_s +{ + uint32_t hcdma3 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA3. */ +typedef volatile struct ALT_USB_HOST_HCDMA3_s ALT_USB_HOST_HCDMA3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA3 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA3_OFST 0x174 +/* The address of the ALT_USB_HOST_HCDMA3 register. */ +#define ALT_USB_HOST_HCDMA3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA3_OFST)) + +/* + * Register : Host Channel 3 DMA Buffer Address Register - hcdmab3 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 3 DMA Buffer Address + * + */ +/* + * Field : Host Channel 3 DMA Buffer Address - hcdmab3 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */ +#define ALT_USB_HOST_HCDMAB3_HCDMAB3_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */ +#define ALT_USB_HOST_HCDMAB3_HCDMAB3_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */ +#define ALT_USB_HOST_HCDMAB3_HCDMAB3_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value. */ +#define ALT_USB_HOST_HCDMAB3_HCDMAB3_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value. */ +#define ALT_USB_HOST_HCDMAB3_HCDMAB3_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */ +#define ALT_USB_HOST_HCDMAB3_HCDMAB3_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB3_HCDMAB3 field value from a register. */ +#define ALT_USB_HOST_HCDMAB3_HCDMAB3_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB3_HCDMAB3_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB3. + */ +struct ALT_USB_HOST_HCDMAB3_s +{ + uint32_t hcdmab3 : 32; /* Host Channel 3 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB3. */ +typedef volatile struct ALT_USB_HOST_HCDMAB3_s ALT_USB_HOST_HCDMAB3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB3 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB3_OFST 0x178 +/* The address of the ALT_USB_HOST_HCDMAB3 register. */ +#define ALT_USB_HOST_HCDMAB3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB3_OFST)) + +/* + * Register : Host Channel 4 Characteristics Register - hcchar4 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 0 DMA Buffer Address + * + */ +/* + * Field : Host Channel 0 DMA Buffer Address - hcdmab4 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */ +#define ALT_USB_HOST_HCCHAR4_HCDMAB4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */ +#define ALT_USB_HOST_HCCHAR4_HCDMAB4_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */ +#define ALT_USB_HOST_HCCHAR4_HCDMAB4_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value. */ +#define ALT_USB_HOST_HCCHAR4_HCDMAB4_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value. */ +#define ALT_USB_HOST_HCCHAR4_HCDMAB4_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */ +#define ALT_USB_HOST_HCCHAR4_HCDMAB4_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR4_HCDMAB4 field value from a register. */ +#define ALT_USB_HOST_HCCHAR4_HCDMAB4_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR4_HCDMAB4_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR4. + */ +struct ALT_USB_HOST_HCCHAR4_s +{ + uint32_t hcdmab4 : 32; /* Host Channel 0 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR4. */ +typedef volatile struct ALT_USB_HOST_HCCHAR4_s ALT_USB_HOST_HCCHAR4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR4 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR4_OFST 0x180 +/* The address of the ALT_USB_HOST_HCCHAR4 register. */ +#define ALT_USB_HOST_HCCHAR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR4_OFST)) + +/* + * Register : Host Channel 4 Split Control Register - hcsplt4 + * + * Channel_number 4 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT4_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT4_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT4_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT4_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT4_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT4_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT4_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT4_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT4_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT4_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT4_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT4_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT4_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT4_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT4_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT4_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT4_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT4_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT4_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT4_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT4_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT4_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT4_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT4_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT4_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT4_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT4_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT4_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT4_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT4_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT4_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT4_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT4_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT4_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT4_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT4_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT4_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT4_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT4_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT4_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT4_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT4_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT4_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT4_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT4_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT4_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT4_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT4_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT4_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT4_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT4_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT4_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT4_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT4_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT4_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT4_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT4_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT4_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT4_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT4_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT4_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT4_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT4_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT4_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT4_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT4_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT4_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT4_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT4_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT4. + */ +struct ALT_USB_HOST_HCSPLT4_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT4. */ +typedef volatile struct ALT_USB_HOST_HCSPLT4_s ALT_USB_HOST_HCSPLT4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT4 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT4_OFST 0x184 +/* The address of the ALT_USB_HOST_HCSPLT4 register. */ +#define ALT_USB_HOST_HCSPLT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT4_OFST)) + +/* + * Register : Host Channel 4 Interrupt Register - hcint4 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT4_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT4_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT4_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT4_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT4_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT4_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT4_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT4_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT4_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT4_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT4_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT4_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT4_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT4_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT4_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT4_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT4_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT4_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT4_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT4_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT4_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT4_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT4_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT4_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT4_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT4_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT4_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT4_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT4_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT4_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT4_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_AHBERR register field. */ +#define ALT_USB_HOST_HCINT4_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_AHBERR register field. */ +#define ALT_USB_HOST_HCINT4_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT4_AHBERR register field. */ +#define ALT_USB_HOST_HCINT4_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT4_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT4_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT4_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT4_AHBERR register field. */ +#define ALT_USB_HOST_HCINT4_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT4_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT4_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT4_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT4_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT4_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_STALL register field. */ +#define ALT_USB_HOST_HCINT4_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_STALL register field. */ +#define ALT_USB_HOST_HCINT4_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT4_STALL register field. */ +#define ALT_USB_HOST_HCINT4_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_STALL register field value. */ +#define ALT_USB_HOST_HCINT4_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT4_STALL register field value. */ +#define ALT_USB_HOST_HCINT4_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT4_STALL register field. */ +#define ALT_USB_HOST_HCINT4_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT4_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT4_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT4_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT4_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT4_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT4_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_NAK register field. */ +#define ALT_USB_HOST_HCINT4_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_NAK register field. */ +#define ALT_USB_HOST_HCINT4_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT4_NAK register field. */ +#define ALT_USB_HOST_HCINT4_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_NAK register field value. */ +#define ALT_USB_HOST_HCINT4_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT4_NAK register field value. */ +#define ALT_USB_HOST_HCINT4_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT4_NAK register field. */ +#define ALT_USB_HOST_HCINT4_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT4_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT4_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT4_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT4_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT4_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT4_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_ACK register field. */ +#define ALT_USB_HOST_HCINT4_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_ACK register field. */ +#define ALT_USB_HOST_HCINT4_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT4_ACK register field. */ +#define ALT_USB_HOST_HCINT4_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_ACK register field value. */ +#define ALT_USB_HOST_HCINT4_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT4_ACK register field value. */ +#define ALT_USB_HOST_HCINT4_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT4_ACK register field. */ +#define ALT_USB_HOST_HCINT4_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT4_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT4_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT4_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT4_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT4_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT4_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_NYET register field. */ +#define ALT_USB_HOST_HCINT4_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_NYET register field. */ +#define ALT_USB_HOST_HCINT4_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT4_NYET register field. */ +#define ALT_USB_HOST_HCINT4_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_NYET register field value. */ +#define ALT_USB_HOST_HCINT4_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT4_NYET register field value. */ +#define ALT_USB_HOST_HCINT4_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT4_NYET register field. */ +#define ALT_USB_HOST_HCINT4_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT4_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT4_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT4_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT4_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT4_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT4_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XACTERR register field. */ +#define ALT_USB_HOST_HCINT4_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XACTERR register field. */ +#define ALT_USB_HOST_HCINT4_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT4_XACTERR register field. */ +#define ALT_USB_HOST_HCINT4_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT4_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT4_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT4_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT4_XACTERR register field. */ +#define ALT_USB_HOST_HCINT4_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT4_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT4_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT4_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT4_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT4_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT4_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_BBLERR register field. */ +#define ALT_USB_HOST_HCINT4_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_BBLERR register field. */ +#define ALT_USB_HOST_HCINT4_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT4_BBLERR register field. */ +#define ALT_USB_HOST_HCINT4_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT4_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT4_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT4_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT4_BBLERR register field. */ +#define ALT_USB_HOST_HCINT4_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT4_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT4_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT4_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT4_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT4_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT4_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT4_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT4_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT4_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT4_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT4_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT4_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT4_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT4_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT4_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT4_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT4_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT4_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT4_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT4_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT4_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT4_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT4_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT4_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT4_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT4_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT4_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT4_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT4_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT4_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT4_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT4_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT4_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT4_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT4_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT4_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT4_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT4_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT4_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT4_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT4_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT4_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT4_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT4. + */ +struct ALT_USB_HOST_HCINT4_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT4. */ +typedef volatile struct ALT_USB_HOST_HCINT4_s ALT_USB_HOST_HCINT4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT4 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT4_OFST 0x188 +/* The address of the ALT_USB_HOST_HCINT4 register. */ +#define ALT_USB_HOST_HCINT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT4_OFST)) + +/* + * Register : Host Channel 4 Interrupt Mask Register - hcintmsk4 + * + * This register reflects the mask for Channel 4 interrupt status bits. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK4_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK4. + */ +struct ALT_USB_HOST_HCINTMSK4_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK4. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK4_s ALT_USB_HOST_HCINTMSK4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK4 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK4_OFST 0x18c +/* The address of the ALT_USB_HOST_HCINTMSK4 register. */ +#define ALT_USB_HOST_HCINTMSK4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK4_OFST)) + +/* + * Register : Host Channel 4 Transfer Size Register - hctsiz4 + * + * Buffer DMA Mode Channel 4 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ4_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ4_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ4_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ4_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ4_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ4_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ4_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ4_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ4_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ4_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ4_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ4_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ4_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ4_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ4_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ4_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ4_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ4_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_PID register field. */ +#define ALT_USB_HOST_HCTSIZ4_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_PID register field. */ +#define ALT_USB_HOST_HCTSIZ4_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ4_PID register field. */ +#define ALT_USB_HOST_HCTSIZ4_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ4_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ4_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ4_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ4_PID register field. */ +#define ALT_USB_HOST_HCTSIZ4_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ4_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ4_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ4_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ4_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ4_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ4_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ4_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ4_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ4_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ4_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ4_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ4_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ4_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ4_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ4_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ4_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ4_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ4_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ4_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ4. + */ +struct ALT_USB_HOST_HCTSIZ4_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ4. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ4_s ALT_USB_HOST_HCTSIZ4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ4 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ4_OFST 0x190 +/* The address of the ALT_USB_HOST_HCTSIZ4 register. */ +#define ALT_USB_HOST_HCTSIZ4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ4_OFST)) + +/* + * Register : Host Channel 4 DMA Address Register - hcdma4 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma4 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */ +#define ALT_USB_HOST_HCDMA4_HCDMA4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */ +#define ALT_USB_HOST_HCDMA4_HCDMA4_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */ +#define ALT_USB_HOST_HCDMA4_HCDMA4_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA4_HCDMA4 register field value. */ +#define ALT_USB_HOST_HCDMA4_HCDMA4_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA4_HCDMA4 register field value. */ +#define ALT_USB_HOST_HCDMA4_HCDMA4_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */ +#define ALT_USB_HOST_HCDMA4_HCDMA4_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA4_HCDMA4 field value from a register. */ +#define ALT_USB_HOST_HCDMA4_HCDMA4_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA4_HCDMA4 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA4_HCDMA4_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA4. + */ +struct ALT_USB_HOST_HCDMA4_s +{ + uint32_t hcdma4 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA4. */ +typedef volatile struct ALT_USB_HOST_HCDMA4_s ALT_USB_HOST_HCDMA4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA4 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA4_OFST 0x194 +/* The address of the ALT_USB_HOST_HCDMA4 register. */ +#define ALT_USB_HOST_HCDMA4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA4_OFST)) + +/* + * Register : Host Channel 4 DMA Buffer Address Register - hcdmab4 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field is + * reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 0 DMA Buffer Address + * + */ +/* + * Field : Host Channel 0 DMA Buffer Address - hcdmab4 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */ +#define ALT_USB_HOST_HCDMAB4_HCDMAB4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */ +#define ALT_USB_HOST_HCDMAB4_HCDMAB4_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */ +#define ALT_USB_HOST_HCDMAB4_HCDMAB4_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value. */ +#define ALT_USB_HOST_HCDMAB4_HCDMAB4_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value. */ +#define ALT_USB_HOST_HCDMAB4_HCDMAB4_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */ +#define ALT_USB_HOST_HCDMAB4_HCDMAB4_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB4_HCDMAB4 field value from a register. */ +#define ALT_USB_HOST_HCDMAB4_HCDMAB4_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB4_HCDMAB4_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB4. + */ +struct ALT_USB_HOST_HCDMAB4_s +{ + uint32_t hcdmab4 : 32; /* Host Channel 0 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB4. */ +typedef volatile struct ALT_USB_HOST_HCDMAB4_s ALT_USB_HOST_HCDMAB4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB4 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB4_OFST 0x198 +/* The address of the ALT_USB_HOST_HCDMAB4 register. */ +#define ALT_USB_HOST_HCDMAB4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB4_OFST)) + +/* + * Register : Host Channel 5 Characteristics Register - hcchar5 + * + * Channel_number: 5. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------ + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count Error Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_MPS register field. */ +#define ALT_USB_HOST_HCCHAR5_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_MPS register field. */ +#define ALT_USB_HOST_HCCHAR5_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR5_MPS register field. */ +#define ALT_USB_HOST_HCCHAR5_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR5_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR5_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR5_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR5_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR5_MPS register field. */ +#define ALT_USB_HOST_HCCHAR5_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR5_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR5_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR5_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR5_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR5_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR5_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR5_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR5_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR5_EPDIR_E_OUTDIR | 0x0 | OUT + * ALT_USB_HOST_HCCHAR5_EPDIR_E_INDIR | 0x1 | IN + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPDIR + * + * OUT + */ +#define ALT_USB_HOST_HCCHAR5_EPDIR_E_OUTDIR 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPDIR + * + * IN + */ +#define ALT_USB_HOST_HCCHAR5_EPDIR_E_INDIR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR5_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR5_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR5_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR5_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR5_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR5_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR5_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR5_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR5_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR5_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR5_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is Set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCCHAR5_LSPDDEV_E_NONLOWSPEED | 0x0 | Communicating with non lowspeed + * ALT_USB_HOST_HCCHAR5_LSPDDEV_E_LOWSPEED | 0x1 | Communicating with lowspeed + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_LSPDDEV + * + * Communicating with non lowspeed + */ +#define ALT_USB_HOST_HCCHAR5_LSPDDEV_E_NONLOWSPEED 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_LSPDDEV + * + * Communicating with lowspeed + */ +#define ALT_USB_HOST_HCCHAR5_LSPDDEV_E_LOWSPEED 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR5_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR5_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR5_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR5_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR5_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR5_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR5_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR5_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR5_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR5_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR5_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR5_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR5_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR5_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR5_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR5_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR5_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR5_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR5_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count Error Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. 0x0: Reserved This field yields undefined results. 0x1: + * transaction 0x2: 2 transactions to be issued for this endpoint permicroframe + * 0x3: 3 transactions to be issued for this endpoint permicroframeWhen + * HCSPLTn.SpltEna is Set (1), this field indicates thenumber of immediate retries + * to be performed for a periodic splittransactions on transaction errors. This + * field must be Set to atleast 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR5_EC_E_RSVD | 0x0 | Reserved This field yields undefined results + * ALT_USB_HOST_HCCHAR5_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR5_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR5_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC + * + * Reserved This field yields undefined results + */ +#define ALT_USB_HOST_HCCHAR5_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR5_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR5_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR5_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EC register field. */ +#define ALT_USB_HOST_HCCHAR5_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EC register field. */ +#define ALT_USB_HOST_HCCHAR5_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR5_EC register field. */ +#define ALT_USB_HOST_HCCHAR5_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR5_EC register field value. */ +#define ALT_USB_HOST_HCCHAR5_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EC register field value. */ +#define ALT_USB_HOST_HCCHAR5_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR5_EC register field. */ +#define ALT_USB_HOST_HCCHAR5_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR5_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR5_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR5_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR5_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR5_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR5_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR5_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR5_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR5_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR5_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR5_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR5_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR5_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR5_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR5_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR5_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCCHAR5_CHDIS_E_INACT | 0x0 | No activity + * ALT_USB_HOST_HCCHAR5_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving data + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHDIS + * + * No activity + */ +#define ALT_USB_HOST_HCCHAR5_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHDIS + * + * Stop transmitting/receiving data + */ +#define ALT_USB_HOST_HCCHAR5_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR5_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR5_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR5_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR5_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR5_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR5_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR5_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR5_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR5_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR5_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR5_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR5_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled. This field is set by the application and + * cleared by the OTG host. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR5_CHENA_E_NOTRDY | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR5_CHENA_E_RDY | 0x1 | Indicates that the descriptor structure and data + * : | | buffer with data is setup and this channel can + * : | | access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR5_CHENA_E_NOTRDY 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHENA + * + * Indicates that the descriptor structure and data buffer with data is setup and + * this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR5_CHENA_E_RDY 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR5_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR5_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR5_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR5_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR5_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR5_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR5_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR5_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR5_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR5_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR5_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR5_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR5_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR5_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR5. + */ +struct ALT_USB_HOST_HCCHAR5_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count Error Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR5. */ +typedef volatile struct ALT_USB_HOST_HCCHAR5_s ALT_USB_HOST_HCCHAR5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR5 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR5_OFST 0x1a0 +/* The address of the ALT_USB_HOST_HCCHAR5 register. */ +#define ALT_USB_HOST_HCCHAR5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR5_OFST)) + +/* + * Register : Host Channel 5 Split Control Register - hcsplt5 + * + * Channel_number 5 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT5_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT5_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT5_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT5_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT5_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT5_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT5_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT5_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT5_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT5_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT5_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT5_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT5_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT5_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT5_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT5_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT5_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT5_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT5_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT5_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT5_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT5_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT5_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT5_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT5_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT5_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT5_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT5_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT5_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT5_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT5_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT5_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT5_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT5_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT5_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT5_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT5_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT5_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT5_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT5_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT5_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT5_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT5_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT5_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT5_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT5_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT5_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT5_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT5_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT5_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT5_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT5_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT5_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT5_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT5_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT5_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT5_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT5_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT5_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT5_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT5_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT5_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT5_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT5_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT5_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT5_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT5_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT5_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT5_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT5. + */ +struct ALT_USB_HOST_HCSPLT5_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT5. */ +typedef volatile struct ALT_USB_HOST_HCSPLT5_s ALT_USB_HOST_HCSPLT5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT5 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT5_OFST 0x1a4 +/* The address of the ALT_USB_HOST_HCSPLT5 register. */ +#define ALT_USB_HOST_HCSPLT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT5_OFST)) + +/* + * Register : Host Channel 5 Interrupt Register - hcint5 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT5_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT5_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT5_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT5_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT5_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT5_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT5_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT5_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT5_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT5_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT5_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT5_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT5_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT5_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT5_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT5_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT5_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT5_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT5_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT5_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT5_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT5_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT5_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT5_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT5_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT5_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT5_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT5_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT5_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT5_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT5_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_AHBERR register field. */ +#define ALT_USB_HOST_HCINT5_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_AHBERR register field. */ +#define ALT_USB_HOST_HCINT5_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT5_AHBERR register field. */ +#define ALT_USB_HOST_HCINT5_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT5_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT5_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT5_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT5_AHBERR register field. */ +#define ALT_USB_HOST_HCINT5_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT5_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT5_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT5_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT5_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT5_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_STALL register field. */ +#define ALT_USB_HOST_HCINT5_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_STALL register field. */ +#define ALT_USB_HOST_HCINT5_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT5_STALL register field. */ +#define ALT_USB_HOST_HCINT5_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_STALL register field value. */ +#define ALT_USB_HOST_HCINT5_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT5_STALL register field value. */ +#define ALT_USB_HOST_HCINT5_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT5_STALL register field. */ +#define ALT_USB_HOST_HCINT5_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT5_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT5_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT5_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT5_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT5_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT5_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_NAK register field. */ +#define ALT_USB_HOST_HCINT5_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_NAK register field. */ +#define ALT_USB_HOST_HCINT5_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT5_NAK register field. */ +#define ALT_USB_HOST_HCINT5_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_NAK register field value. */ +#define ALT_USB_HOST_HCINT5_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT5_NAK register field value. */ +#define ALT_USB_HOST_HCINT5_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT5_NAK register field. */ +#define ALT_USB_HOST_HCINT5_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT5_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT5_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT5_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT5_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT5_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT5_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_ACK register field. */ +#define ALT_USB_HOST_HCINT5_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_ACK register field. */ +#define ALT_USB_HOST_HCINT5_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT5_ACK register field. */ +#define ALT_USB_HOST_HCINT5_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_ACK register field value. */ +#define ALT_USB_HOST_HCINT5_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT5_ACK register field value. */ +#define ALT_USB_HOST_HCINT5_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT5_ACK register field. */ +#define ALT_USB_HOST_HCINT5_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT5_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT5_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT5_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT5_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT5_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT5_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_NYET register field. */ +#define ALT_USB_HOST_HCINT5_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_NYET register field. */ +#define ALT_USB_HOST_HCINT5_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT5_NYET register field. */ +#define ALT_USB_HOST_HCINT5_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_NYET register field value. */ +#define ALT_USB_HOST_HCINT5_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT5_NYET register field value. */ +#define ALT_USB_HOST_HCINT5_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT5_NYET register field. */ +#define ALT_USB_HOST_HCINT5_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT5_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT5_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT5_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT5_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT5_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT5_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XACTERR register field. */ +#define ALT_USB_HOST_HCINT5_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XACTERR register field. */ +#define ALT_USB_HOST_HCINT5_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT5_XACTERR register field. */ +#define ALT_USB_HOST_HCINT5_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT5_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT5_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT5_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT5_XACTERR register field. */ +#define ALT_USB_HOST_HCINT5_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT5_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT5_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT5_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT5_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT5_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT5_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_BBLERR register field. */ +#define ALT_USB_HOST_HCINT5_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_BBLERR register field. */ +#define ALT_USB_HOST_HCINT5_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT5_BBLERR register field. */ +#define ALT_USB_HOST_HCINT5_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT5_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT5_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT5_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT5_BBLERR register field. */ +#define ALT_USB_HOST_HCINT5_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT5_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT5_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT5_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT5_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT5_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT5_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT5_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT5_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT5_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT5_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT5_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT5_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT5_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT5_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT5_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT5_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT5_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT5_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT5_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT5_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT5_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT5_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT5_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT5_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT5_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT5_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT5_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT5_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT5_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT5_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT5_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT5_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT5_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT5_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT5_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT5_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT5_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT5_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT5_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT5_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT5_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT5_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT5_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT5. + */ +struct ALT_USB_HOST_HCINT5_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT5. */ +typedef volatile struct ALT_USB_HOST_HCINT5_s ALT_USB_HOST_HCINT5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT5 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT5_OFST 0x1a8 +/* The address of the ALT_USB_HOST_HCINT5 register. */ +#define ALT_USB_HOST_HCINT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT5_OFST)) + +/* + * Register : Host Channel 5 Interrupt Mask Register - hcintmsk5 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK5_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK5. + */ +struct ALT_USB_HOST_HCINTMSK5_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK5. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK5_s ALT_USB_HOST_HCINTMSK5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK5 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK5_OFST 0x1ac +/* The address of the ALT_USB_HOST_HCINTMSK5 register. */ +#define ALT_USB_HOST_HCINTMSK5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK5_OFST)) + +/* + * Register : Host Channel 5 Transfer Size Register - hctsiz5 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ5_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ5_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ5_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ5_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ5_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ5_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ5_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ5_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ5_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ5_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ5_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ5_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ5_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ5_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ5_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ5_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ5_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ5_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_PID register field. */ +#define ALT_USB_HOST_HCTSIZ5_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_PID register field. */ +#define ALT_USB_HOST_HCTSIZ5_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ5_PID register field. */ +#define ALT_USB_HOST_HCTSIZ5_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ5_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ5_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ5_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ5_PID register field. */ +#define ALT_USB_HOST_HCTSIZ5_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ5_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ5_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ5_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ5_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ5_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ5_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ5_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ5_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ5_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ5_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ5_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ5_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ5_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ5_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ5_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ5_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ5_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ5_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ5_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ5. + */ +struct ALT_USB_HOST_HCTSIZ5_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ5. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ5_s ALT_USB_HOST_HCTSIZ5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ5 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ5_OFST 0x1b0 +/* The address of the ALT_USB_HOST_HCTSIZ5 register. */ +#define ALT_USB_HOST_HCTSIZ5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ5_OFST)) + +/* + * Register : Host Channel 5 DMA Address Register - hcdma5 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma5 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */ +#define ALT_USB_HOST_HCDMA5_HCDMA5_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */ +#define ALT_USB_HOST_HCDMA5_HCDMA5_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */ +#define ALT_USB_HOST_HCDMA5_HCDMA5_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA5_HCDMA5 register field value. */ +#define ALT_USB_HOST_HCDMA5_HCDMA5_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA5_HCDMA5 register field value. */ +#define ALT_USB_HOST_HCDMA5_HCDMA5_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */ +#define ALT_USB_HOST_HCDMA5_HCDMA5_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA5_HCDMA5 field value from a register. */ +#define ALT_USB_HOST_HCDMA5_HCDMA5_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA5_HCDMA5 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA5_HCDMA5_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA5. + */ +struct ALT_USB_HOST_HCDMA5_s +{ + uint32_t hcdma5 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA5. */ +typedef volatile struct ALT_USB_HOST_HCDMA5_s ALT_USB_HOST_HCDMA5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA5 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA5_OFST 0x1b4 +/* The address of the ALT_USB_HOST_HCDMA5 register. */ +#define ALT_USB_HOST_HCDMA5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA5_OFST)) + +/* + * Register : Host Channel 5 DMA Buffer Address Register - hcdmab5 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 5 DMA Buffer Address + * + */ +/* + * Field : Host Channel 5 DMA Buffer Address - hcdmab5 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */ +#define ALT_USB_HOST_HCDMAB5_HCDMAB5_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */ +#define ALT_USB_HOST_HCDMAB5_HCDMAB5_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */ +#define ALT_USB_HOST_HCDMAB5_HCDMAB5_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value. */ +#define ALT_USB_HOST_HCDMAB5_HCDMAB5_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value. */ +#define ALT_USB_HOST_HCDMAB5_HCDMAB5_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */ +#define ALT_USB_HOST_HCDMAB5_HCDMAB5_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB5_HCDMAB5 field value from a register. */ +#define ALT_USB_HOST_HCDMAB5_HCDMAB5_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB5_HCDMAB5_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB5. + */ +struct ALT_USB_HOST_HCDMAB5_s +{ + uint32_t hcdmab5 : 32; /* Host Channel 5 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB5. */ +typedef volatile struct ALT_USB_HOST_HCDMAB5_s ALT_USB_HOST_HCDMAB5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB5 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB5_OFST 0x1b8 +/* The address of the ALT_USB_HOST_HCDMAB5 register. */ +#define ALT_USB_HOST_HCDMAB5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB5_OFST)) + +/* + * Register : Host Channel 6 Characteristics Register - hcchar6 + * + * Host Channel 6 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_MPS register field. */ +#define ALT_USB_HOST_HCCHAR6_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_MPS register field. */ +#define ALT_USB_HOST_HCCHAR6_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR6_MPS register field. */ +#define ALT_USB_HOST_HCCHAR6_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR6_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR6_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR6_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR6_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR6_MPS register field. */ +#define ALT_USB_HOST_HCCHAR6_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR6_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR6_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR6_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR6_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR6_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR6_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR6_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR6_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR6_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR6_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR6_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR6_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR6_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR6_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR6_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR6_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR6_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR6_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR6_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR6_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR6_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR6_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR6_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR6_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR6_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR6_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR6_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR6_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR6_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR6_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR6_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR6_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR6_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR6_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR6_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR6_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR6_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR6_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR6_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR6_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR6_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR6_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR6_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR6_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR6_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR6_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR6_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR6_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR6_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR6_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR6_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR6_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR6_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR6_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EC register field. */ +#define ALT_USB_HOST_HCCHAR6_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EC register field. */ +#define ALT_USB_HOST_HCCHAR6_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR6_EC register field. */ +#define ALT_USB_HOST_HCCHAR6_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR6_EC register field value. */ +#define ALT_USB_HOST_HCCHAR6_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EC register field value. */ +#define ALT_USB_HOST_HCCHAR6_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR6_EC register field. */ +#define ALT_USB_HOST_HCCHAR6_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR6_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR6_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR6_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR6_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR6_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR6_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR6_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR6_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR6_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR6_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR6_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR6_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR6_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR6_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR6_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR6_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR6_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR6_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR6_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR6_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR6_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR6_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR6_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR6_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR6_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR6_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR6_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR6_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR6_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR6_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR6_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR6_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR6_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR6_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR6_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR6_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR6_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR6_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR6_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR6_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR6_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR6_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR6_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR6_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR6_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR6_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR6_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR6_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR6_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR6_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR6. + */ +struct ALT_USB_HOST_HCCHAR6_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR6. */ +typedef volatile struct ALT_USB_HOST_HCCHAR6_s ALT_USB_HOST_HCCHAR6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR6 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR6_OFST 0x1c0 +/* The address of the ALT_USB_HOST_HCCHAR6 register. */ +#define ALT_USB_HOST_HCCHAR6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR6_OFST)) + +/* + * Register : Host Channel 6 Split Control Register - hcsplt6 + * + * Channel_number 6 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT6_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT6_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT6_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT6_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT6_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT6_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT6_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT6_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT6_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT6_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT6_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT6_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT6_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT6_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT6_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT6_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT6_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT6_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT6_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT6_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT6_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT6_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT6_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT6_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT6_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT6_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT6_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT6_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT6_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT6_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT6_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT6_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT6_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT6_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT6_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT6_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT6_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT6_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT6_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT6_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT6_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT6_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT6_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT6_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT6_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT6_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT6_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT6_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT6_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT6_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT6_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT6_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT6_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT6_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT6_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT6_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT6_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT6_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT6_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT6_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT6_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT6_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT6_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT6_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT6_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT6_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT6_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT6_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT6_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT6. + */ +struct ALT_USB_HOST_HCSPLT6_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT6. */ +typedef volatile struct ALT_USB_HOST_HCSPLT6_s ALT_USB_HOST_HCSPLT6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT6 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT6_OFST 0x1c4 +/* The address of the ALT_USB_HOST_HCSPLT6 register. */ +#define ALT_USB_HOST_HCSPLT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT6_OFST)) + +/* + * Register : Host Channel 6 Interrupt Register - hcint6 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT6_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT6_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT6_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT6_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT6_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT6_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT6_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT6_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT6_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT6_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT6_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT6_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT6_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT6_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT6_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT6_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT6_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT6_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT6_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT6_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT6_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT6_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT6_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT6_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT6_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT6_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT6_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT6_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT6_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT6_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT6_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_AHBERR register field. */ +#define ALT_USB_HOST_HCINT6_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_AHBERR register field. */ +#define ALT_USB_HOST_HCINT6_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT6_AHBERR register field. */ +#define ALT_USB_HOST_HCINT6_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT6_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT6_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT6_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT6_AHBERR register field. */ +#define ALT_USB_HOST_HCINT6_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT6_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT6_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT6_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT6_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT6_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_STALL register field. */ +#define ALT_USB_HOST_HCINT6_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_STALL register field. */ +#define ALT_USB_HOST_HCINT6_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT6_STALL register field. */ +#define ALT_USB_HOST_HCINT6_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_STALL register field value. */ +#define ALT_USB_HOST_HCINT6_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT6_STALL register field value. */ +#define ALT_USB_HOST_HCINT6_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT6_STALL register field. */ +#define ALT_USB_HOST_HCINT6_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT6_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT6_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT6_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT6_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT6_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT6_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_NAK register field. */ +#define ALT_USB_HOST_HCINT6_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_NAK register field. */ +#define ALT_USB_HOST_HCINT6_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT6_NAK register field. */ +#define ALT_USB_HOST_HCINT6_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_NAK register field value. */ +#define ALT_USB_HOST_HCINT6_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT6_NAK register field value. */ +#define ALT_USB_HOST_HCINT6_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT6_NAK register field. */ +#define ALT_USB_HOST_HCINT6_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT6_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT6_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT6_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT6_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT6_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT6_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_ACK register field. */ +#define ALT_USB_HOST_HCINT6_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_ACK register field. */ +#define ALT_USB_HOST_HCINT6_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT6_ACK register field. */ +#define ALT_USB_HOST_HCINT6_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_ACK register field value. */ +#define ALT_USB_HOST_HCINT6_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT6_ACK register field value. */ +#define ALT_USB_HOST_HCINT6_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT6_ACK register field. */ +#define ALT_USB_HOST_HCINT6_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT6_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT6_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT6_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT6_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT6_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT6_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_NYET register field. */ +#define ALT_USB_HOST_HCINT6_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_NYET register field. */ +#define ALT_USB_HOST_HCINT6_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT6_NYET register field. */ +#define ALT_USB_HOST_HCINT6_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_NYET register field value. */ +#define ALT_USB_HOST_HCINT6_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT6_NYET register field value. */ +#define ALT_USB_HOST_HCINT6_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT6_NYET register field. */ +#define ALT_USB_HOST_HCINT6_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT6_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT6_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT6_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT6_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT6_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT6_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XACTERR register field. */ +#define ALT_USB_HOST_HCINT6_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XACTERR register field. */ +#define ALT_USB_HOST_HCINT6_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT6_XACTERR register field. */ +#define ALT_USB_HOST_HCINT6_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT6_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT6_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT6_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT6_XACTERR register field. */ +#define ALT_USB_HOST_HCINT6_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT6_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT6_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT6_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT6_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT6_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT6_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_BBLERR register field. */ +#define ALT_USB_HOST_HCINT6_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_BBLERR register field. */ +#define ALT_USB_HOST_HCINT6_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT6_BBLERR register field. */ +#define ALT_USB_HOST_HCINT6_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT6_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT6_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT6_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT6_BBLERR register field. */ +#define ALT_USB_HOST_HCINT6_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT6_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT6_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT6_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT6_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT6_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT6_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT6_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT6_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT6_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT6_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT6_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT6_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT6_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT6_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT6_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT6_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT6_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT6_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT6_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT6_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT6_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT6_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT6_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT6_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT6_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT6_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT6_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT6_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT6_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT6_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT6_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT6_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT6_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT6_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT6_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT6_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT6_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT6_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT6_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT6_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT6_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT6_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT6_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT6. + */ +struct ALT_USB_HOST_HCINT6_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT6. */ +typedef volatile struct ALT_USB_HOST_HCINT6_s ALT_USB_HOST_HCINT6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT6 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT6_OFST 0x1c8 +/* The address of the ALT_USB_HOST_HCINT6 register. */ +#define ALT_USB_HOST_HCINT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT6_OFST)) + +/* + * Register : Host Channel 6 Interrupt Mask Register - hcintmsk6 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK6_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK6. + */ +struct ALT_USB_HOST_HCINTMSK6_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK6. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK6_s ALT_USB_HOST_HCINTMSK6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK6 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK6_OFST 0x1cc +/* The address of the ALT_USB_HOST_HCINTMSK6 register. */ +#define ALT_USB_HOST_HCINTMSK6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK6_OFST)) + +/* + * Register : Host Channel 6 Transfer Size Register - hctsiz6 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ6_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ6_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ6_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ6_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ6_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ6_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ6_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ6_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ6_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ6_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ6_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ6_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ6_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ6_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ6_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ6_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ6_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ6_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_PID register field. */ +#define ALT_USB_HOST_HCTSIZ6_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_PID register field. */ +#define ALT_USB_HOST_HCTSIZ6_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ6_PID register field. */ +#define ALT_USB_HOST_HCTSIZ6_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ6_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ6_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ6_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ6_PID register field. */ +#define ALT_USB_HOST_HCTSIZ6_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ6_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ6_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ6_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ6_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ6_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ6_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ6_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ6_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ6_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ6_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ6_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ6_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ6_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ6_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ6_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ6_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ6_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ6_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ6_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ6. + */ +struct ALT_USB_HOST_HCTSIZ6_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ6. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ6_s ALT_USB_HOST_HCTSIZ6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ6 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ6_OFST 0x1d0 +/* The address of the ALT_USB_HOST_HCTSIZ6 register. */ +#define ALT_USB_HOST_HCTSIZ6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ6_OFST)) + +/* + * Register : Host Channel DMA Address Registe - hcdma6 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma6 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */ +#define ALT_USB_HOST_HCDMA6_HCDMA6_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */ +#define ALT_USB_HOST_HCDMA6_HCDMA6_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */ +#define ALT_USB_HOST_HCDMA6_HCDMA6_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA6_HCDMA6 register field value. */ +#define ALT_USB_HOST_HCDMA6_HCDMA6_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA6_HCDMA6 register field value. */ +#define ALT_USB_HOST_HCDMA6_HCDMA6_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */ +#define ALT_USB_HOST_HCDMA6_HCDMA6_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA6_HCDMA6 field value from a register. */ +#define ALT_USB_HOST_HCDMA6_HCDMA6_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA6_HCDMA6 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA6_HCDMA6_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA6. + */ +struct ALT_USB_HOST_HCDMA6_s +{ + uint32_t hcdma6 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA6. */ +typedef volatile struct ALT_USB_HOST_HCDMA6_s ALT_USB_HOST_HCDMA6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA6 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA6_OFST 0x1d4 +/* The address of the ALT_USB_HOST_HCDMA6 register. */ +#define ALT_USB_HOST_HCDMA6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA6_OFST)) + +/* + * Register : Host Channel 6 DMA Buffer Address Register - hcdmab6 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 6 DMA Buffer Address + * + */ +/* + * Field : Host Channel 6 DMA Buffer Address - hcdmab6 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */ +#define ALT_USB_HOST_HCDMAB6_HCDMAB6_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */ +#define ALT_USB_HOST_HCDMAB6_HCDMAB6_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */ +#define ALT_USB_HOST_HCDMAB6_HCDMAB6_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value. */ +#define ALT_USB_HOST_HCDMAB6_HCDMAB6_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value. */ +#define ALT_USB_HOST_HCDMAB6_HCDMAB6_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */ +#define ALT_USB_HOST_HCDMAB6_HCDMAB6_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB6_HCDMAB6 field value from a register. */ +#define ALT_USB_HOST_HCDMAB6_HCDMAB6_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB6_HCDMAB6_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB6. + */ +struct ALT_USB_HOST_HCDMAB6_s +{ + uint32_t hcdmab6 : 32; /* Host Channel 6 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB6. */ +typedef volatile struct ALT_USB_HOST_HCDMAB6_s ALT_USB_HOST_HCDMAB6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB6 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB6_OFST 0x1d8 +/* The address of the ALT_USB_HOST_HCDMAB6 register. */ +#define ALT_USB_HOST_HCDMAB6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB6_OFST)) + +/* + * Register : Host Channel 7 Characteristics Register - hcchar7 + * + * Host Channel 7 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_MPS register field. */ +#define ALT_USB_HOST_HCCHAR7_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_MPS register field. */ +#define ALT_USB_HOST_HCCHAR7_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR7_MPS register field. */ +#define ALT_USB_HOST_HCCHAR7_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR7_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR7_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR7_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR7_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR7_MPS register field. */ +#define ALT_USB_HOST_HCCHAR7_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR7_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR7_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR7_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR7_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR7_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR7_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR7_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR7_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR7_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR7_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR7_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR7_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR7_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR7_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR7_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR7_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR7_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR7_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR7_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR7_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR7_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR7_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR7_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR7_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR7_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR7_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR7_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR7_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR7_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR7_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR7_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR7_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR7_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR7_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR7_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR7_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR7_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR7_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR7_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR7_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR7_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR7_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR7_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR7_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR7_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR7_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR7_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR7_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR7_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR7_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR7_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR7_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR7_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR7_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EC register field. */ +#define ALT_USB_HOST_HCCHAR7_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EC register field. */ +#define ALT_USB_HOST_HCCHAR7_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR7_EC register field. */ +#define ALT_USB_HOST_HCCHAR7_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR7_EC register field value. */ +#define ALT_USB_HOST_HCCHAR7_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EC register field value. */ +#define ALT_USB_HOST_HCCHAR7_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR7_EC register field. */ +#define ALT_USB_HOST_HCCHAR7_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR7_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR7_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR7_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR7_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR7_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR7_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR7_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR7_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR7_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR7_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR7_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR7_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR7_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR7_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR7_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR7_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR7_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR7_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR7_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR7_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR7_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR7_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR7_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR7_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR7_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR7_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR7_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR7_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR7_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR7_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR7_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR7_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR7_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR7_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR7_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR7_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR7_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR7_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR7_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR7_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR7_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR7_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR7_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR7_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR7_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR7_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR7_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR7_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR7_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR7_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR7. + */ +struct ALT_USB_HOST_HCCHAR7_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR7. */ +typedef volatile struct ALT_USB_HOST_HCCHAR7_s ALT_USB_HOST_HCCHAR7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR7 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR7_OFST 0x1e0 +/* The address of the ALT_USB_HOST_HCCHAR7 register. */ +#define ALT_USB_HOST_HCCHAR7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR7_OFST)) + +/* + * Register : Host Channel 7 Split Control Register - hcsplt7 + * + * Channel_number 7 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT7_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT7_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT7_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT7_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT7_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT7_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT7_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT7_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT7_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT7_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT7_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT7_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT7_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT7_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT7_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT7_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT7_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT7_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT7_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT7_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT7_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT7_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT7_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT7_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT7_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT7_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT7_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT7_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT7_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT7_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT7_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT7_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT7_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT7_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT7_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT7_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT7_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT7_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT7_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT7_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT7_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT7_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT7_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT7_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT7_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT7_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT7_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT7_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT7_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT7_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT7_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT7_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT7_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT7_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT7_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT7_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT7_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT7_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT7_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT7_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT7_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT7_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT7_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT7_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT7_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT7_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT7_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT7_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT7_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT7. + */ +struct ALT_USB_HOST_HCSPLT7_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT7. */ +typedef volatile struct ALT_USB_HOST_HCSPLT7_s ALT_USB_HOST_HCSPLT7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT7 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT7_OFST 0x1e4 +/* The address of the ALT_USB_HOST_HCSPLT7 register. */ +#define ALT_USB_HOST_HCSPLT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT7_OFST)) + +/* + * Register : Host Channel 7 Interrupt Register - hcint7 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT7_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT7_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT7_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT7_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT7_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT7_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT7_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT7_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT7_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT7_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT7_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT7_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT7_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT7_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT7_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT7_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT7_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT7_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT7_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT7_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT7_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT7_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT7_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT7_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT7_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT7_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT7_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT7_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT7_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT7_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT7_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_AHBERR register field. */ +#define ALT_USB_HOST_HCINT7_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_AHBERR register field. */ +#define ALT_USB_HOST_HCINT7_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT7_AHBERR register field. */ +#define ALT_USB_HOST_HCINT7_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT7_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT7_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT7_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT7_AHBERR register field. */ +#define ALT_USB_HOST_HCINT7_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT7_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT7_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT7_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT7_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT7_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_STALL register field. */ +#define ALT_USB_HOST_HCINT7_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_STALL register field. */ +#define ALT_USB_HOST_HCINT7_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT7_STALL register field. */ +#define ALT_USB_HOST_HCINT7_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_STALL register field value. */ +#define ALT_USB_HOST_HCINT7_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT7_STALL register field value. */ +#define ALT_USB_HOST_HCINT7_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT7_STALL register field. */ +#define ALT_USB_HOST_HCINT7_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT7_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT7_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT7_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT7_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT7_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT7_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_NAK register field. */ +#define ALT_USB_HOST_HCINT7_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_NAK register field. */ +#define ALT_USB_HOST_HCINT7_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT7_NAK register field. */ +#define ALT_USB_HOST_HCINT7_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_NAK register field value. */ +#define ALT_USB_HOST_HCINT7_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT7_NAK register field value. */ +#define ALT_USB_HOST_HCINT7_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT7_NAK register field. */ +#define ALT_USB_HOST_HCINT7_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT7_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT7_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT7_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT7_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT7_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT7_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_ACK register field. */ +#define ALT_USB_HOST_HCINT7_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_ACK register field. */ +#define ALT_USB_HOST_HCINT7_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT7_ACK register field. */ +#define ALT_USB_HOST_HCINT7_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_ACK register field value. */ +#define ALT_USB_HOST_HCINT7_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT7_ACK register field value. */ +#define ALT_USB_HOST_HCINT7_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT7_ACK register field. */ +#define ALT_USB_HOST_HCINT7_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT7_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT7_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT7_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT7_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT7_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT7_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_NYET register field. */ +#define ALT_USB_HOST_HCINT7_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_NYET register field. */ +#define ALT_USB_HOST_HCINT7_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT7_NYET register field. */ +#define ALT_USB_HOST_HCINT7_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_NYET register field value. */ +#define ALT_USB_HOST_HCINT7_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT7_NYET register field value. */ +#define ALT_USB_HOST_HCINT7_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT7_NYET register field. */ +#define ALT_USB_HOST_HCINT7_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT7_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT7_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT7_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT7_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT7_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT7_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XACTERR register field. */ +#define ALT_USB_HOST_HCINT7_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XACTERR register field. */ +#define ALT_USB_HOST_HCINT7_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT7_XACTERR register field. */ +#define ALT_USB_HOST_HCINT7_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT7_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT7_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT7_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT7_XACTERR register field. */ +#define ALT_USB_HOST_HCINT7_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT7_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT7_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT7_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT7_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT7_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT7_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_BBLERR register field. */ +#define ALT_USB_HOST_HCINT7_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_BBLERR register field. */ +#define ALT_USB_HOST_HCINT7_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT7_BBLERR register field. */ +#define ALT_USB_HOST_HCINT7_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT7_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT7_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT7_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT7_BBLERR register field. */ +#define ALT_USB_HOST_HCINT7_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT7_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT7_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT7_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT7_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT7_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT7_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT7_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT7_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT7_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT7_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT7_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT7_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT7_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT7_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT7_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT7_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT7_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT7_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT7_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT7_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT7_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT7_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT7_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT7_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT7_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT7_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT7_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT7_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT7_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT7_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT7_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT7_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT7_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT7_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT7_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT7_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT7_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT7_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT7_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT7_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT7_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT7_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT7_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT7. + */ +struct ALT_USB_HOST_HCINT7_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT7. */ +typedef volatile struct ALT_USB_HOST_HCINT7_s ALT_USB_HOST_HCINT7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT7 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT7_OFST 0x1e8 +/* The address of the ALT_USB_HOST_HCINT7 register. */ +#define ALT_USB_HOST_HCINT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT7_OFST)) + +/* + * Register : Host Channel 7 Interrupt Mask Register - hcintmsk7 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK7_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK7. + */ +struct ALT_USB_HOST_HCINTMSK7_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK7. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK7_s ALT_USB_HOST_HCINTMSK7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK7 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK7_OFST 0x1ec +/* The address of the ALT_USB_HOST_HCINTMSK7 register. */ +#define ALT_USB_HOST_HCINTMSK7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK7_OFST)) + +/* + * Register : Host Channel 7 Transfer Size Register - hctsiz7 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ7_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ7_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ7_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ7_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ7_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ7_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ7_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ7_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ7_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ7_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ7_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ7_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ7_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ7_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ7_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ7_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ7_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ7_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_PID register field. */ +#define ALT_USB_HOST_HCTSIZ7_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_PID register field. */ +#define ALT_USB_HOST_HCTSIZ7_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ7_PID register field. */ +#define ALT_USB_HOST_HCTSIZ7_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ7_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ7_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ7_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ7_PID register field. */ +#define ALT_USB_HOST_HCTSIZ7_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ7_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ7_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ7_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ7_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ7_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ7_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ7_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ7_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ7_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ7_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ7_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ7_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ7_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ7_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ7_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ7_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ7_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ7_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ7_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ7. + */ +struct ALT_USB_HOST_HCTSIZ7_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ7. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ7_s ALT_USB_HOST_HCTSIZ7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ7 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ7_OFST 0x1f0 +/* The address of the ALT_USB_HOST_HCTSIZ7 register. */ +#define ALT_USB_HOST_HCTSIZ7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ7_OFST)) + +/* + * Register : Host Channel 7 DMA Address Register - hcdma7 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma7 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */ +#define ALT_USB_HOST_HCDMA7_HCDMA7_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */ +#define ALT_USB_HOST_HCDMA7_HCDMA7_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */ +#define ALT_USB_HOST_HCDMA7_HCDMA7_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA7_HCDMA7 register field value. */ +#define ALT_USB_HOST_HCDMA7_HCDMA7_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA7_HCDMA7 register field value. */ +#define ALT_USB_HOST_HCDMA7_HCDMA7_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */ +#define ALT_USB_HOST_HCDMA7_HCDMA7_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA7_HCDMA7 field value from a register. */ +#define ALT_USB_HOST_HCDMA7_HCDMA7_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA7_HCDMA7 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA7_HCDMA7_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA7. + */ +struct ALT_USB_HOST_HCDMA7_s +{ + uint32_t hcdma7 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA7. */ +typedef volatile struct ALT_USB_HOST_HCDMA7_s ALT_USB_HOST_HCDMA7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA7 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA7_OFST 0x1f4 +/* The address of the ALT_USB_HOST_HCDMA7 register. */ +#define ALT_USB_HOST_HCDMA7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA7_OFST)) + +/* + * Register : Host Channel 7 DMA Buffer Address Register - hcdmab7 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 7 DMA Buffer Address + * + */ +/* + * Field : Host Channel 7 DMA Buffer Address - hcdmab7 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */ +#define ALT_USB_HOST_HCDMAB7_HCDMAB7_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */ +#define ALT_USB_HOST_HCDMAB7_HCDMAB7_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */ +#define ALT_USB_HOST_HCDMAB7_HCDMAB7_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value. */ +#define ALT_USB_HOST_HCDMAB7_HCDMAB7_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value. */ +#define ALT_USB_HOST_HCDMAB7_HCDMAB7_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */ +#define ALT_USB_HOST_HCDMAB7_HCDMAB7_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB7_HCDMAB7 field value from a register. */ +#define ALT_USB_HOST_HCDMAB7_HCDMAB7_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB7_HCDMAB7_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB7. + */ +struct ALT_USB_HOST_HCDMAB7_s +{ + uint32_t hcdmab7 : 32; /* Host Channel 7 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB7. */ +typedef volatile struct ALT_USB_HOST_HCDMAB7_s ALT_USB_HOST_HCDMAB7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB7 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB7_OFST 0x1f8 +/* The address of the ALT_USB_HOST_HCDMAB7 register. */ +#define ALT_USB_HOST_HCDMAB7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB7_OFST)) + +/* + * Register : Host Channel 8 Characteristics Register - hcchar8 + * + * Host Channel 8 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_MPS register field. */ +#define ALT_USB_HOST_HCCHAR8_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_MPS register field. */ +#define ALT_USB_HOST_HCCHAR8_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR8_MPS register field. */ +#define ALT_USB_HOST_HCCHAR8_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR8_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR8_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR8_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR8_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR8_MPS register field. */ +#define ALT_USB_HOST_HCCHAR8_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR8_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR8_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR8_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR8_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR8_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR8_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR8_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR8_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR8_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR8_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR8_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR8_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR8_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR8_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR8_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR8_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR8_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR8_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR8_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR8_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR8_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR8_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR8_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR8_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR8_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR8_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR8_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR8_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR8_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR8_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR8_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR8_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR8_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR8_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR8_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR8_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR8_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR8_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR8_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR8_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR8_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR8_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR8_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR8_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR8_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR8_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR8_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR8_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR8_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR8_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR8_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR8_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR8_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR8_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EC register field. */ +#define ALT_USB_HOST_HCCHAR8_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EC register field. */ +#define ALT_USB_HOST_HCCHAR8_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR8_EC register field. */ +#define ALT_USB_HOST_HCCHAR8_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR8_EC register field value. */ +#define ALT_USB_HOST_HCCHAR8_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EC register field value. */ +#define ALT_USB_HOST_HCCHAR8_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR8_EC register field. */ +#define ALT_USB_HOST_HCCHAR8_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR8_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR8_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR8_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR8_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR8_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR8_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR8_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR8_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR8_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR8_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR8_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR8_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR8_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR8_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR8_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR8_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR8_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR8_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR8_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR8_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR8_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR8_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR8_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR8_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR8_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR8_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR8_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR8_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR8_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR8_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR8_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR8_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR8_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR8_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR8_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR8_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR8_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR8_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR8_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR8_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR8_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR8_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR8_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR8_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR8_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR8_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR8_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR8_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR8_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR8_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR8. + */ +struct ALT_USB_HOST_HCCHAR8_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR8. */ +typedef volatile struct ALT_USB_HOST_HCCHAR8_s ALT_USB_HOST_HCCHAR8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR8 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR8_OFST 0x200 +/* The address of the ALT_USB_HOST_HCCHAR8 register. */ +#define ALT_USB_HOST_HCCHAR8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR8_OFST)) + +/* + * Register : Host Channel 8 Split Control Register - hcsplt8 + * + * Channel_number 8 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT8_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT8_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT8_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT8_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT8_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT8_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT8_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT8_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT8_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT8_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT8_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT8_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT8_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT8_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT8_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT8_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT8_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT8_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT8_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT8_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT8_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT8_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT8_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT8_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT8_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT8_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT8_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT8_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT8_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT8_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT8_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT8_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT8_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT8_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT8_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT8_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT8_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT8_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT8_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT8_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT8_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT8_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT8_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT8_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT8_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT8_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT8_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT8_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT8_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT8_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT8_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT8_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT8_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT8_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT8_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT8_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT8_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT8_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT8_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT8_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT8_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT8_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT8_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT8_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT8_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT8_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT8_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT8_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT8_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT8. + */ +struct ALT_USB_HOST_HCSPLT8_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT8. */ +typedef volatile struct ALT_USB_HOST_HCSPLT8_s ALT_USB_HOST_HCSPLT8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT8 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT8_OFST 0x204 +/* The address of the ALT_USB_HOST_HCSPLT8 register. */ +#define ALT_USB_HOST_HCSPLT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT8_OFST)) + +/* + * Register : Host Channel 8 Interrupt Register - hcint8 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT8_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT8_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT8_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT8_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT8_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT8_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT8_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT8_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT8_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT8_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT8_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT8_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT8_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT8_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT8_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT8_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT8_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT8_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT8_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT8_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT8_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT8_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT8_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT8_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT8_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT8_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT8_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT8_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT8_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT8_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT8_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_AHBERR register field. */ +#define ALT_USB_HOST_HCINT8_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_AHBERR register field. */ +#define ALT_USB_HOST_HCINT8_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT8_AHBERR register field. */ +#define ALT_USB_HOST_HCINT8_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT8_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT8_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT8_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT8_AHBERR register field. */ +#define ALT_USB_HOST_HCINT8_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT8_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT8_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT8_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT8_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT8_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_STALL register field. */ +#define ALT_USB_HOST_HCINT8_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_STALL register field. */ +#define ALT_USB_HOST_HCINT8_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT8_STALL register field. */ +#define ALT_USB_HOST_HCINT8_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_STALL register field value. */ +#define ALT_USB_HOST_HCINT8_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT8_STALL register field value. */ +#define ALT_USB_HOST_HCINT8_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT8_STALL register field. */ +#define ALT_USB_HOST_HCINT8_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT8_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT8_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT8_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT8_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT8_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT8_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_NAK register field. */ +#define ALT_USB_HOST_HCINT8_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_NAK register field. */ +#define ALT_USB_HOST_HCINT8_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT8_NAK register field. */ +#define ALT_USB_HOST_HCINT8_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_NAK register field value. */ +#define ALT_USB_HOST_HCINT8_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT8_NAK register field value. */ +#define ALT_USB_HOST_HCINT8_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT8_NAK register field. */ +#define ALT_USB_HOST_HCINT8_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT8_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT8_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT8_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT8_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT8_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT8_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_ACK register field. */ +#define ALT_USB_HOST_HCINT8_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_ACK register field. */ +#define ALT_USB_HOST_HCINT8_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT8_ACK register field. */ +#define ALT_USB_HOST_HCINT8_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_ACK register field value. */ +#define ALT_USB_HOST_HCINT8_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT8_ACK register field value. */ +#define ALT_USB_HOST_HCINT8_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT8_ACK register field. */ +#define ALT_USB_HOST_HCINT8_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT8_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT8_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT8_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT8_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT8_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT8_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_NYET register field. */ +#define ALT_USB_HOST_HCINT8_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_NYET register field. */ +#define ALT_USB_HOST_HCINT8_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT8_NYET register field. */ +#define ALT_USB_HOST_HCINT8_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_NYET register field value. */ +#define ALT_USB_HOST_HCINT8_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT8_NYET register field value. */ +#define ALT_USB_HOST_HCINT8_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT8_NYET register field. */ +#define ALT_USB_HOST_HCINT8_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT8_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT8_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT8_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT8_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT8_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT8_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XACTERR register field. */ +#define ALT_USB_HOST_HCINT8_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XACTERR register field. */ +#define ALT_USB_HOST_HCINT8_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT8_XACTERR register field. */ +#define ALT_USB_HOST_HCINT8_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT8_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT8_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT8_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT8_XACTERR register field. */ +#define ALT_USB_HOST_HCINT8_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT8_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT8_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT8_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT8_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT8_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT8_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_BBLERR register field. */ +#define ALT_USB_HOST_HCINT8_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_BBLERR register field. */ +#define ALT_USB_HOST_HCINT8_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT8_BBLERR register field. */ +#define ALT_USB_HOST_HCINT8_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT8_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT8_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT8_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT8_BBLERR register field. */ +#define ALT_USB_HOST_HCINT8_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT8_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT8_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT8_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT8_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT8_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT8_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT8_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT8_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT8_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT8_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT8_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT8_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT8_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT8_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT8_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT8_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT8_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT8_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT8_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT8_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT8_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT8_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT8_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT8_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT8_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT8_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT8_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT8_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT8_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT8_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT8_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT8_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT8_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT8_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT8_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT8_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT8_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT8_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT8_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT8_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT8_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT8_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT8_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT8. + */ +struct ALT_USB_HOST_HCINT8_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT8. */ +typedef volatile struct ALT_USB_HOST_HCINT8_s ALT_USB_HOST_HCINT8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT8 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT8_OFST 0x208 +/* The address of the ALT_USB_HOST_HCINT8 register. */ +#define ALT_USB_HOST_HCINT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT8_OFST)) + +/* + * Register : Host Channel 8 Interrupt Mask Register - hcintmsk8 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK8_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK8. + */ +struct ALT_USB_HOST_HCINTMSK8_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK8. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK8_s ALT_USB_HOST_HCINTMSK8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK8 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK8_OFST 0x20c +/* The address of the ALT_USB_HOST_HCINTMSK8 register. */ +#define ALT_USB_HOST_HCINTMSK8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK8_OFST)) + +/* + * Register : Host Channel 8 Transfer Size Register - hctsiz8 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ8_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ8_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ8_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ8_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ8_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ8_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ8_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ8_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ8_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ8_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ8_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ8_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ8_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ8_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ8_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ8_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ8_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ8_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_PID register field. */ +#define ALT_USB_HOST_HCTSIZ8_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_PID register field. */ +#define ALT_USB_HOST_HCTSIZ8_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ8_PID register field. */ +#define ALT_USB_HOST_HCTSIZ8_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ8_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ8_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ8_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ8_PID register field. */ +#define ALT_USB_HOST_HCTSIZ8_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ8_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ8_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ8_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ8_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ8_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ8_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ8_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ8_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ8_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ8_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ8_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ8_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ8_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ8_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ8_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ8_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ8_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ8_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ8_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ8. + */ +struct ALT_USB_HOST_HCTSIZ8_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ8. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ8_s ALT_USB_HOST_HCTSIZ8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ8 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ8_OFST 0x210 +/* The address of the ALT_USB_HOST_HCTSIZ8 register. */ +#define ALT_USB_HOST_HCTSIZ8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ8_OFST)) + +/* + * Register : Host Channel 8 DMA Address Register - hcdma8 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma8 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */ +#define ALT_USB_HOST_HCDMA8_HCDMA8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */ +#define ALT_USB_HOST_HCDMA8_HCDMA8_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */ +#define ALT_USB_HOST_HCDMA8_HCDMA8_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA8_HCDMA8 register field value. */ +#define ALT_USB_HOST_HCDMA8_HCDMA8_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA8_HCDMA8 register field value. */ +#define ALT_USB_HOST_HCDMA8_HCDMA8_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */ +#define ALT_USB_HOST_HCDMA8_HCDMA8_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA8_HCDMA8 field value from a register. */ +#define ALT_USB_HOST_HCDMA8_HCDMA8_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA8_HCDMA8 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA8_HCDMA8_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA8. + */ +struct ALT_USB_HOST_HCDMA8_s +{ + uint32_t hcdma8 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA8. */ +typedef volatile struct ALT_USB_HOST_HCDMA8_s ALT_USB_HOST_HCDMA8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA8 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA8_OFST 0x214 +/* The address of the ALT_USB_HOST_HCDMA8 register. */ +#define ALT_USB_HOST_HCDMA8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA8_OFST)) + +/* + * Register : Host Channel 8 DMA Buffer Address Register - hcdmab8 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 8 DMA Buffer Address + * + */ +/* + * Field : Host Channel 8 DMA Buffer Address - hcdmab8 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */ +#define ALT_USB_HOST_HCDMAB8_HCDMAB8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */ +#define ALT_USB_HOST_HCDMAB8_HCDMAB8_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */ +#define ALT_USB_HOST_HCDMAB8_HCDMAB8_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value. */ +#define ALT_USB_HOST_HCDMAB8_HCDMAB8_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value. */ +#define ALT_USB_HOST_HCDMAB8_HCDMAB8_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */ +#define ALT_USB_HOST_HCDMAB8_HCDMAB8_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB8_HCDMAB8 field value from a register. */ +#define ALT_USB_HOST_HCDMAB8_HCDMAB8_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB8_HCDMAB8_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB8. + */ +struct ALT_USB_HOST_HCDMAB8_s +{ + uint32_t hcdmab8 : 32; /* Host Channel 8 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB8. */ +typedef volatile struct ALT_USB_HOST_HCDMAB8_s ALT_USB_HOST_HCDMAB8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB8 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB8_OFST 0x218 +/* The address of the ALT_USB_HOST_HCDMAB8 register. */ +#define ALT_USB_HOST_HCDMAB8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB8_OFST)) + +/* + * Register : Host Channel 9 Characteristics Register - hcchar9 + * + * Host Channel 9 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_MPS register field. */ +#define ALT_USB_HOST_HCCHAR9_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_MPS register field. */ +#define ALT_USB_HOST_HCCHAR9_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR9_MPS register field. */ +#define ALT_USB_HOST_HCCHAR9_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR9_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR9_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR9_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR9_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR9_MPS register field. */ +#define ALT_USB_HOST_HCCHAR9_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR9_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR9_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR9_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR9_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR9_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR9_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR9_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR9_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR9_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR9_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR9_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR9_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR9_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR9_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR9_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR9_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR9_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR9_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR9_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR9_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR9_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR9_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR9_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR9_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR9_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR9_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR9_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR9_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR9_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR9_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR9_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR9_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR9_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR9_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR9_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR9_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR9_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR9_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR9_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR9_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR9_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR9_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR9_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR9_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR9_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR9_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR9_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR9_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR9_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR9_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR9_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR9_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR9_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR9_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EC register field. */ +#define ALT_USB_HOST_HCCHAR9_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EC register field. */ +#define ALT_USB_HOST_HCCHAR9_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR9_EC register field. */ +#define ALT_USB_HOST_HCCHAR9_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR9_EC register field value. */ +#define ALT_USB_HOST_HCCHAR9_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EC register field value. */ +#define ALT_USB_HOST_HCCHAR9_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR9_EC register field. */ +#define ALT_USB_HOST_HCCHAR9_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR9_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR9_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR9_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR9_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR9_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR9_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR9_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR9_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR9_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR9_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR9_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR9_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR9_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR9_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR9_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR9_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR9_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR9_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR9_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR9_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR9_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR9_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR9_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR9_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR9_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR9_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR9_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR9_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR9_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR9_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR9_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR9_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR9_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR9_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR9_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR9_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR9_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR9_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR9_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR9_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR9_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR9_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR9_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR9_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR9_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR9_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR9_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR9_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR9_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR9_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR9. + */ +struct ALT_USB_HOST_HCCHAR9_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR9. */ +typedef volatile struct ALT_USB_HOST_HCCHAR9_s ALT_USB_HOST_HCCHAR9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR9 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR9_OFST 0x220 +/* The address of the ALT_USB_HOST_HCCHAR9 register. */ +#define ALT_USB_HOST_HCCHAR9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR9_OFST)) + +/* + * Register : Host Channel 9 Split Control Register - hcsplt9 + * + * Channel_number 9 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT9_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT9_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT9_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT9_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT9_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT9_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT9_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT9_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT9_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT9_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT9_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT9_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT9_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT9_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT9_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT9_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT9_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT9_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT9_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT9_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT9_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT9_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT9_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT9_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT9_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT9_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT9_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT9_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT9_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT9_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT9_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT9_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT9_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT9_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT9_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT9_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT9_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT9_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT9_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT9_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT9_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT9_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT9_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT9_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT9_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT9_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT9_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT9_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT9_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT9_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT9_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT9_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT9_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT9_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT9_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT9_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT9_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT9_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT9_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT9_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT9_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT9_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT9_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT9_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT9_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT9_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT9_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT9_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT9_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT9. + */ +struct ALT_USB_HOST_HCSPLT9_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT9. */ +typedef volatile struct ALT_USB_HOST_HCSPLT9_s ALT_USB_HOST_HCSPLT9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT9 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT9_OFST 0x224 +/* The address of the ALT_USB_HOST_HCSPLT9 register. */ +#define ALT_USB_HOST_HCSPLT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT9_OFST)) + +/* + * Register : Host Channel 9 Interrupt Register - hcint9 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT9_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT9_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT9_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT9_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT9_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT9_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT9_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT9_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT9_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT9_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT9_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT9_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT9_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT9_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT9_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT9_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT9_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT9_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT9_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT9_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT9_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT9_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT9_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT9_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT9_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT9_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT9_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT9_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT9_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT9_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT9_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_AHBERR register field. */ +#define ALT_USB_HOST_HCINT9_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_AHBERR register field. */ +#define ALT_USB_HOST_HCINT9_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT9_AHBERR register field. */ +#define ALT_USB_HOST_HCINT9_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT9_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT9_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT9_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT9_AHBERR register field. */ +#define ALT_USB_HOST_HCINT9_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT9_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT9_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT9_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT9_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT9_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_STALL register field. */ +#define ALT_USB_HOST_HCINT9_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_STALL register field. */ +#define ALT_USB_HOST_HCINT9_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT9_STALL register field. */ +#define ALT_USB_HOST_HCINT9_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_STALL register field value. */ +#define ALT_USB_HOST_HCINT9_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT9_STALL register field value. */ +#define ALT_USB_HOST_HCINT9_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT9_STALL register field. */ +#define ALT_USB_HOST_HCINT9_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT9_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT9_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT9_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT9_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT9_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT9_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_NAK register field. */ +#define ALT_USB_HOST_HCINT9_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_NAK register field. */ +#define ALT_USB_HOST_HCINT9_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT9_NAK register field. */ +#define ALT_USB_HOST_HCINT9_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_NAK register field value. */ +#define ALT_USB_HOST_HCINT9_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT9_NAK register field value. */ +#define ALT_USB_HOST_HCINT9_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT9_NAK register field. */ +#define ALT_USB_HOST_HCINT9_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT9_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT9_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT9_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT9_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT9_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT9_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_ACK register field. */ +#define ALT_USB_HOST_HCINT9_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_ACK register field. */ +#define ALT_USB_HOST_HCINT9_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT9_ACK register field. */ +#define ALT_USB_HOST_HCINT9_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_ACK register field value. */ +#define ALT_USB_HOST_HCINT9_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT9_ACK register field value. */ +#define ALT_USB_HOST_HCINT9_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT9_ACK register field. */ +#define ALT_USB_HOST_HCINT9_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT9_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT9_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT9_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT9_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT9_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT9_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_NYET register field. */ +#define ALT_USB_HOST_HCINT9_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_NYET register field. */ +#define ALT_USB_HOST_HCINT9_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT9_NYET register field. */ +#define ALT_USB_HOST_HCINT9_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_NYET register field value. */ +#define ALT_USB_HOST_HCINT9_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT9_NYET register field value. */ +#define ALT_USB_HOST_HCINT9_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT9_NYET register field. */ +#define ALT_USB_HOST_HCINT9_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT9_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT9_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT9_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT9_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT9_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT9_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XACTERR register field. */ +#define ALT_USB_HOST_HCINT9_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XACTERR register field. */ +#define ALT_USB_HOST_HCINT9_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT9_XACTERR register field. */ +#define ALT_USB_HOST_HCINT9_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT9_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT9_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT9_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT9_XACTERR register field. */ +#define ALT_USB_HOST_HCINT9_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT9_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT9_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT9_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT9_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT9_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT9_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_BBLERR register field. */ +#define ALT_USB_HOST_HCINT9_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_BBLERR register field. */ +#define ALT_USB_HOST_HCINT9_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT9_BBLERR register field. */ +#define ALT_USB_HOST_HCINT9_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT9_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT9_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT9_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT9_BBLERR register field. */ +#define ALT_USB_HOST_HCINT9_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT9_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT9_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT9_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT9_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT9_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT9_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT9_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT9_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT9_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT9_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT9_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT9_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT9_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT9_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT9_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT9_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT9_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT9_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT9_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT9_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT9_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT9_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT9_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT9_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT9_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT9_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT9_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT9_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT9_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT9_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT9_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT9_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT9_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT9_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT9_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT9_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT9_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT9_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT9_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT9_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT9_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT9_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT9_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT9. + */ +struct ALT_USB_HOST_HCINT9_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT9. */ +typedef volatile struct ALT_USB_HOST_HCINT9_s ALT_USB_HOST_HCINT9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT9 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT9_OFST 0x228 +/* The address of the ALT_USB_HOST_HCINT9 register. */ +#define ALT_USB_HOST_HCINT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT9_OFST)) + +/* + * Register : Host Channel 9 Interrupt Mask Register - hcintmsk9 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK9_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK9. + */ +struct ALT_USB_HOST_HCINTMSK9_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK9. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK9_s ALT_USB_HOST_HCINTMSK9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK9 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK9_OFST 0x22c +/* The address of the ALT_USB_HOST_HCINTMSK9 register. */ +#define ALT_USB_HOST_HCINTMSK9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK9_OFST)) + +/* + * Register : Host Channel 9 Transfer Size Register - hctsiz9 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ9_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ9_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ9_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ9_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ9_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ9_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ9_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ9_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ9_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ9_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ9_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ9_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ9_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ9_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ9_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ9_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ9_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ9_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_PID register field. */ +#define ALT_USB_HOST_HCTSIZ9_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_PID register field. */ +#define ALT_USB_HOST_HCTSIZ9_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ9_PID register field. */ +#define ALT_USB_HOST_HCTSIZ9_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ9_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ9_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ9_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ9_PID register field. */ +#define ALT_USB_HOST_HCTSIZ9_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ9_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ9_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ9_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ9_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ9_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ9_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ9_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ9_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ9_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ9_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ9_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ9_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ9_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ9_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ9_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ9_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ9_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ9_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ9_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ9. + */ +struct ALT_USB_HOST_HCTSIZ9_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ9. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ9_s ALT_USB_HOST_HCTSIZ9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ9 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ9_OFST 0x230 +/* The address of the ALT_USB_HOST_HCTSIZ9 register. */ +#define ALT_USB_HOST_HCTSIZ9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ9_OFST)) + +/* + * Register : Host Channel DMA Address Register - hcdma9 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma9 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */ +#define ALT_USB_HOST_HCDMA9_HCDMA9_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */ +#define ALT_USB_HOST_HCDMA9_HCDMA9_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */ +#define ALT_USB_HOST_HCDMA9_HCDMA9_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA9_HCDMA9 register field value. */ +#define ALT_USB_HOST_HCDMA9_HCDMA9_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA9_HCDMA9 register field value. */ +#define ALT_USB_HOST_HCDMA9_HCDMA9_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */ +#define ALT_USB_HOST_HCDMA9_HCDMA9_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA9_HCDMA9 field value from a register. */ +#define ALT_USB_HOST_HCDMA9_HCDMA9_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA9_HCDMA9 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA9_HCDMA9_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA9. + */ +struct ALT_USB_HOST_HCDMA9_s +{ + uint32_t hcdma9 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA9. */ +typedef volatile struct ALT_USB_HOST_HCDMA9_s ALT_USB_HOST_HCDMA9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA9 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA9_OFST 0x234 +/* The address of the ALT_USB_HOST_HCDMA9 register. */ +#define ALT_USB_HOST_HCDMA9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA9_OFST)) + +/* + * Register : Host Channel 9 DMA Buffer Address Register - hcdmab9 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 0 DMA Buffer Address + * + */ +/* + * Field : Host Channel 0 DMA Buffer Address - hcdmab9 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */ +#define ALT_USB_HOST_HCDMAB9_HCDMAB9_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */ +#define ALT_USB_HOST_HCDMAB9_HCDMAB9_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */ +#define ALT_USB_HOST_HCDMAB9_HCDMAB9_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value. */ +#define ALT_USB_HOST_HCDMAB9_HCDMAB9_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value. */ +#define ALT_USB_HOST_HCDMAB9_HCDMAB9_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */ +#define ALT_USB_HOST_HCDMAB9_HCDMAB9_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB9_HCDMAB9 field value from a register. */ +#define ALT_USB_HOST_HCDMAB9_HCDMAB9_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB9_HCDMAB9_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB9. + */ +struct ALT_USB_HOST_HCDMAB9_s +{ + uint32_t hcdmab9 : 32; /* Host Channel 0 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB9. */ +typedef volatile struct ALT_USB_HOST_HCDMAB9_s ALT_USB_HOST_HCDMAB9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB9 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB9_OFST 0x238 +/* The address of the ALT_USB_HOST_HCDMAB9 register. */ +#define ALT_USB_HOST_HCDMAB9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB9_OFST)) + +/* + * Register : Host Channel 10 Characteristics Register - hcchar10 + * + * Host Channel 1 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_MPS register field. */ +#define ALT_USB_HOST_HCCHAR10_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_MPS register field. */ +#define ALT_USB_HOST_HCCHAR10_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR10_MPS register field. */ +#define ALT_USB_HOST_HCCHAR10_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR10_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR10_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR10_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR10_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR10_MPS register field. */ +#define ALT_USB_HOST_HCCHAR10_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR10_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR10_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR10_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR10_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR10_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR10_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR10_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR10_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR10_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR10_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR10_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR10_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR10_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR10_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR10_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR10_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR10_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR10_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR10_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR10_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR10_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR10_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR10_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR10_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR10_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR10_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR10_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR10_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR10_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR10_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR10_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR10_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR10_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR10_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR10_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR10_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR10_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR10_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR10_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR10_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR10_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR10_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR10_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR10_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR10_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR10_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR10_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR10_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR10_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR10_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR10_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR10_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR10_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR10_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EC register field. */ +#define ALT_USB_HOST_HCCHAR10_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EC register field. */ +#define ALT_USB_HOST_HCCHAR10_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR10_EC register field. */ +#define ALT_USB_HOST_HCCHAR10_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR10_EC register field value. */ +#define ALT_USB_HOST_HCCHAR10_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EC register field value. */ +#define ALT_USB_HOST_HCCHAR10_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR10_EC register field. */ +#define ALT_USB_HOST_HCCHAR10_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR10_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR10_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR10_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR10_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR10_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR10_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR10_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR10_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR10_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR10_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR10_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR10_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR10_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR10_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR10_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR10_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR10_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR10_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR10_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR10_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR10_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR10_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR10_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR10_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR10_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR10_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR10_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR10_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR10_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR10_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR10_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR10_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR10_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR10_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR10_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR10_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR10_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR10_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR10_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR10_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR10_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR10_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR10_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR10_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR10_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR10_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR10_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR10_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR10_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR10_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR10. + */ +struct ALT_USB_HOST_HCCHAR10_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR10. */ +typedef volatile struct ALT_USB_HOST_HCCHAR10_s ALT_USB_HOST_HCCHAR10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR10 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR10_OFST 0x240 +/* The address of the ALT_USB_HOST_HCCHAR10 register. */ +#define ALT_USB_HOST_HCCHAR10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR10_OFST)) + +/* + * Register : Host Channel 10 Split Control Register - hcsplt10 + * + * Channel_number 1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT10_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT10_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT10_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT10_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT10_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT10_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT10_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT10_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT10_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT10_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT10_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT10_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT10_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT10_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT10_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT10_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT10_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT10_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT10_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT10_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT10_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT10_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT10_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT10_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT10_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT10_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT10_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT10_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT10_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT10_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT10_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT10_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT10_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT10_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT10_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT10_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT10_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT10_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT10_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT10_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT10_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT10_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT10_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT10_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT10_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT10_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT10_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT10_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT10_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT10_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT10_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT10_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT10_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT10_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT10_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT10_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT10_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT10_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT10_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT10_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT10_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT10_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT10_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT10_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT10_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT10_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT10_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT10_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT10_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT10. + */ +struct ALT_USB_HOST_HCSPLT10_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT10. */ +typedef volatile struct ALT_USB_HOST_HCSPLT10_s ALT_USB_HOST_HCSPLT10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT10 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT10_OFST 0x244 +/* The address of the ALT_USB_HOST_HCSPLT10 register. */ +#define ALT_USB_HOST_HCSPLT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT10_OFST)) + +/* + * Register : Host Channel 10 Interrupt Register - hcint10 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT10_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT10_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT10_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT10_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT10_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT10_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT10_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT10_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT10_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT10_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT10_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT10_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT10_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT10_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT10_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT10_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT10_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT10_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT10_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT10_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT10_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT10_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT10_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT10_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT10_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT10_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT10_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT10_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT10_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT10_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT10_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_AHBERR register field. */ +#define ALT_USB_HOST_HCINT10_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_AHBERR register field. */ +#define ALT_USB_HOST_HCINT10_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT10_AHBERR register field. */ +#define ALT_USB_HOST_HCINT10_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT10_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT10_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT10_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT10_AHBERR register field. */ +#define ALT_USB_HOST_HCINT10_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT10_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT10_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT10_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT10_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT10_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_STALL register field. */ +#define ALT_USB_HOST_HCINT10_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_STALL register field. */ +#define ALT_USB_HOST_HCINT10_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT10_STALL register field. */ +#define ALT_USB_HOST_HCINT10_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_STALL register field value. */ +#define ALT_USB_HOST_HCINT10_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT10_STALL register field value. */ +#define ALT_USB_HOST_HCINT10_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT10_STALL register field. */ +#define ALT_USB_HOST_HCINT10_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT10_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT10_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT10_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT10_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT10_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT10_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_NAK register field. */ +#define ALT_USB_HOST_HCINT10_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_NAK register field. */ +#define ALT_USB_HOST_HCINT10_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT10_NAK register field. */ +#define ALT_USB_HOST_HCINT10_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_NAK register field value. */ +#define ALT_USB_HOST_HCINT10_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT10_NAK register field value. */ +#define ALT_USB_HOST_HCINT10_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT10_NAK register field. */ +#define ALT_USB_HOST_HCINT10_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT10_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT10_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT10_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT10_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT10_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT10_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_ACK register field. */ +#define ALT_USB_HOST_HCINT10_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_ACK register field. */ +#define ALT_USB_HOST_HCINT10_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT10_ACK register field. */ +#define ALT_USB_HOST_HCINT10_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_ACK register field value. */ +#define ALT_USB_HOST_HCINT10_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT10_ACK register field value. */ +#define ALT_USB_HOST_HCINT10_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT10_ACK register field. */ +#define ALT_USB_HOST_HCINT10_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT10_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT10_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT10_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT10_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT10_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT10_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_NYET register field. */ +#define ALT_USB_HOST_HCINT10_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_NYET register field. */ +#define ALT_USB_HOST_HCINT10_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT10_NYET register field. */ +#define ALT_USB_HOST_HCINT10_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_NYET register field value. */ +#define ALT_USB_HOST_HCINT10_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT10_NYET register field value. */ +#define ALT_USB_HOST_HCINT10_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT10_NYET register field. */ +#define ALT_USB_HOST_HCINT10_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT10_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT10_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT10_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT10_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT10_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT10_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XACTERR register field. */ +#define ALT_USB_HOST_HCINT10_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XACTERR register field. */ +#define ALT_USB_HOST_HCINT10_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT10_XACTERR register field. */ +#define ALT_USB_HOST_HCINT10_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT10_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT10_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT10_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT10_XACTERR register field. */ +#define ALT_USB_HOST_HCINT10_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT10_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT10_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT10_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT10_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT10_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT10_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_BBLERR register field. */ +#define ALT_USB_HOST_HCINT10_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_BBLERR register field. */ +#define ALT_USB_HOST_HCINT10_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT10_BBLERR register field. */ +#define ALT_USB_HOST_HCINT10_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT10_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT10_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT10_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT10_BBLERR register field. */ +#define ALT_USB_HOST_HCINT10_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT10_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT10_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT10_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT10_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT10_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT10_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT10_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT10_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT10_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT10_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT10_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT10_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT10_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT10_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT10_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT10_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT10_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT10_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT10_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT10_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT10_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT10_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT10_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT10_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT10_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT10_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT10_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT10_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT10_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT10_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT10_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT10_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT10_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT10_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT10_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT10_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT10_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT10_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT10_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT10_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT10_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT10_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT10_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT10. + */ +struct ALT_USB_HOST_HCINT10_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT10. */ +typedef volatile struct ALT_USB_HOST_HCINT10_s ALT_USB_HOST_HCINT10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT10 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT10_OFST 0x248 +/* The address of the ALT_USB_HOST_HCINT10 register. */ +#define ALT_USB_HOST_HCINT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT10_OFST)) + +/* + * Register : Host Channel 10 Interrupt Mask Register - hcintmsk10 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK10_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK10. + */ +struct ALT_USB_HOST_HCINTMSK10_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK10. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK10_s ALT_USB_HOST_HCINTMSK10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK10 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK10_OFST 0x24c +/* The address of the ALT_USB_HOST_HCINTMSK10 register. */ +#define ALT_USB_HOST_HCINTMSK10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK10_OFST)) + +/* + * Register : Host Channel 10 Transfer Size Register - hctsiz10 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ10_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ10_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ10_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ10_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ10_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ10_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ10_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ10_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ10_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ10_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ10_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ10_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ10_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ10_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ10_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ10_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ10_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ10_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_PID register field. */ +#define ALT_USB_HOST_HCTSIZ10_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_PID register field. */ +#define ALT_USB_HOST_HCTSIZ10_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ10_PID register field. */ +#define ALT_USB_HOST_HCTSIZ10_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ10_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ10_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ10_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ10_PID register field. */ +#define ALT_USB_HOST_HCTSIZ10_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ10_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ10_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ10_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ10_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ10_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ10_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ10_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ10_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ10_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ10_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ10_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ10_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ10_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ10_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ10_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ10_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ10_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ10_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ10_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ10. + */ +struct ALT_USB_HOST_HCTSIZ10_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ10. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ10_s ALT_USB_HOST_HCTSIZ10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ10 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ10_OFST 0x250 +/* The address of the ALT_USB_HOST_HCTSIZ10 register. */ +#define ALT_USB_HOST_HCTSIZ10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ10_OFST)) + +/* + * Register : Host Channel 10 DMA Address Register - hcdma10 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma10 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */ +#define ALT_USB_HOST_HCDMA10_HCDMA10_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */ +#define ALT_USB_HOST_HCDMA10_HCDMA10_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */ +#define ALT_USB_HOST_HCDMA10_HCDMA10_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA10_HCDMA10 register field value. */ +#define ALT_USB_HOST_HCDMA10_HCDMA10_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA10_HCDMA10 register field value. */ +#define ALT_USB_HOST_HCDMA10_HCDMA10_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */ +#define ALT_USB_HOST_HCDMA10_HCDMA10_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA10_HCDMA10 field value from a register. */ +#define ALT_USB_HOST_HCDMA10_HCDMA10_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA10_HCDMA10 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA10_HCDMA10_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA10. + */ +struct ALT_USB_HOST_HCDMA10_s +{ + uint32_t hcdma10 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA10. */ +typedef volatile struct ALT_USB_HOST_HCDMA10_s ALT_USB_HOST_HCDMA10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA10 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA10_OFST 0x254 +/* The address of the ALT_USB_HOST_HCDMA10 register. */ +#define ALT_USB_HOST_HCDMA10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA10_OFST)) + +/* + * Register : Host Channel 10 DMA Buffer Address Register - hcdmab10 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------- + * [31:0] | RW | 0x0 | Host Channel 10 DMA Buffer Address + * + */ +/* + * Field : Host Channel 10 DMA Buffer Address - hcdmab10 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */ +#define ALT_USB_HOST_HCDMAB10_HCDMAB10_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */ +#define ALT_USB_HOST_HCDMAB10_HCDMAB10_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */ +#define ALT_USB_HOST_HCDMAB10_HCDMAB10_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value. */ +#define ALT_USB_HOST_HCDMAB10_HCDMAB10_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value. */ +#define ALT_USB_HOST_HCDMAB10_HCDMAB10_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */ +#define ALT_USB_HOST_HCDMAB10_HCDMAB10_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB10_HCDMAB10 field value from a register. */ +#define ALT_USB_HOST_HCDMAB10_HCDMAB10_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB10_HCDMAB10_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB10. + */ +struct ALT_USB_HOST_HCDMAB10_s +{ + uint32_t hcdmab10 : 32; /* Host Channel 10 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB10. */ +typedef volatile struct ALT_USB_HOST_HCDMAB10_s ALT_USB_HOST_HCDMAB10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB10 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB10_OFST 0x258 +/* The address of the ALT_USB_HOST_HCDMAB10 register. */ +#define ALT_USB_HOST_HCDMAB10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB10_OFST)) + +/* + * Register : Host Channel 11 Characteristics Register - hcchar11 + * + * Host Channel 11 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_MPS register field. */ +#define ALT_USB_HOST_HCCHAR11_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_MPS register field. */ +#define ALT_USB_HOST_HCCHAR11_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR11_MPS register field. */ +#define ALT_USB_HOST_HCCHAR11_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR11_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR11_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR11_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR11_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR11_MPS register field. */ +#define ALT_USB_HOST_HCCHAR11_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR11_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR11_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR11_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR11_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR11_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR11_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR11_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR11_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR11_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR11_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR11_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR11_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR11_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR11_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR11_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR11_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR11_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR11_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR11_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR11_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR11_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR11_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR11_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR11_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR11_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR11_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR11_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR11_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR11_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR11_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR11_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR11_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR11_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR11_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR11_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR11_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR11_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR11_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR11_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR11_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR11_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR11_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR11_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR11_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR11_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR11_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR11_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR11_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR11_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR11_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR11_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR11_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR11_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR11_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EC register field. */ +#define ALT_USB_HOST_HCCHAR11_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EC register field. */ +#define ALT_USB_HOST_HCCHAR11_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR11_EC register field. */ +#define ALT_USB_HOST_HCCHAR11_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR11_EC register field value. */ +#define ALT_USB_HOST_HCCHAR11_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EC register field value. */ +#define ALT_USB_HOST_HCCHAR11_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR11_EC register field. */ +#define ALT_USB_HOST_HCCHAR11_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR11_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR11_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR11_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR11_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR11_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR11_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR11_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR11_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR11_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR11_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR11_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR11_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR11_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR11_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR11_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR11_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR11_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR11_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR11_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR11_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR11_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR11_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR11_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR11_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR11_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR11_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR11_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR11_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR11_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR11_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR11_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR11_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR11_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR11_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR11_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR11_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR11_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR11_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR11_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR11_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR11_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR11_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR11_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR11_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR11_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR11_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR11_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR11_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR11_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR11_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR11. + */ +struct ALT_USB_HOST_HCCHAR11_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR11. */ +typedef volatile struct ALT_USB_HOST_HCCHAR11_s ALT_USB_HOST_HCCHAR11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR11 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR11_OFST 0x260 +/* The address of the ALT_USB_HOST_HCCHAR11 register. */ +#define ALT_USB_HOST_HCCHAR11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR11_OFST)) + +/* + * Register : Host Channel 11 Split Control Register - HCSPLT11 + * + * Channel number 11. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT11_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT11_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT11_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT11_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT11_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT11_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT11_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT11_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT11_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT11_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT11_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT11_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT11_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT11_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT11_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT11_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT11_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT11_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT11_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT11_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT11_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT11_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT11_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT11_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT11_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT11_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT11_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT11_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT11_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT11_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT11_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT11_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT11_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT11_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT11_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT11_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT11_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT11_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT11_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT11_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT11_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT11_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT11_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT11_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT11_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT11_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT11_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT11_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT11_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT11_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT11_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT11_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT11_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT11_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT11_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT11_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT11_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT11_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT11_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT11_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT11_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT11_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT11_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT11_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT11_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT11_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT11_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT11_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT11_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT11. + */ +struct ALT_USB_HOST_HCSPLT11_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT11. */ +typedef volatile struct ALT_USB_HOST_HCSPLT11_s ALT_USB_HOST_HCSPLT11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT11 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT11_OFST 0x264 +/* The address of the ALT_USB_HOST_HCSPLT11 register. */ +#define ALT_USB_HOST_HCSPLT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT11_OFST)) + +/* + * Register : Host Channel 11 Interrupt Register - hcint11 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT11_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT11_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT11_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT11_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT11_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT11_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT11_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT11_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT11_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT11_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT11_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT11_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT11_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT11_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT11_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT11_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT11_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT11_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT11_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT11_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT11_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT11_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT11_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT11_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT11_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT11_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT11_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT11_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT11_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT11_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT11_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_AHBERR register field. */ +#define ALT_USB_HOST_HCINT11_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_AHBERR register field. */ +#define ALT_USB_HOST_HCINT11_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT11_AHBERR register field. */ +#define ALT_USB_HOST_HCINT11_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT11_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT11_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT11_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT11_AHBERR register field. */ +#define ALT_USB_HOST_HCINT11_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT11_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT11_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT11_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT11_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT11_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_STALL register field. */ +#define ALT_USB_HOST_HCINT11_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_STALL register field. */ +#define ALT_USB_HOST_HCINT11_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT11_STALL register field. */ +#define ALT_USB_HOST_HCINT11_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_STALL register field value. */ +#define ALT_USB_HOST_HCINT11_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT11_STALL register field value. */ +#define ALT_USB_HOST_HCINT11_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT11_STALL register field. */ +#define ALT_USB_HOST_HCINT11_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT11_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT11_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT11_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT11_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT11_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT11_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_NAK register field. */ +#define ALT_USB_HOST_HCINT11_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_NAK register field. */ +#define ALT_USB_HOST_HCINT11_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT11_NAK register field. */ +#define ALT_USB_HOST_HCINT11_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_NAK register field value. */ +#define ALT_USB_HOST_HCINT11_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT11_NAK register field value. */ +#define ALT_USB_HOST_HCINT11_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT11_NAK register field. */ +#define ALT_USB_HOST_HCINT11_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT11_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT11_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT11_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT11_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT11_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT11_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_ACK register field. */ +#define ALT_USB_HOST_HCINT11_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_ACK register field. */ +#define ALT_USB_HOST_HCINT11_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT11_ACK register field. */ +#define ALT_USB_HOST_HCINT11_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_ACK register field value. */ +#define ALT_USB_HOST_HCINT11_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT11_ACK register field value. */ +#define ALT_USB_HOST_HCINT11_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT11_ACK register field. */ +#define ALT_USB_HOST_HCINT11_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT11_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT11_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT11_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT11_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT11_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT11_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_NYET register field. */ +#define ALT_USB_HOST_HCINT11_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_NYET register field. */ +#define ALT_USB_HOST_HCINT11_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT11_NYET register field. */ +#define ALT_USB_HOST_HCINT11_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_NYET register field value. */ +#define ALT_USB_HOST_HCINT11_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT11_NYET register field value. */ +#define ALT_USB_HOST_HCINT11_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT11_NYET register field. */ +#define ALT_USB_HOST_HCINT11_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT11_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT11_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT11_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT11_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT11_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT11_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XACTERR register field. */ +#define ALT_USB_HOST_HCINT11_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XACTERR register field. */ +#define ALT_USB_HOST_HCINT11_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT11_XACTERR register field. */ +#define ALT_USB_HOST_HCINT11_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT11_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT11_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT11_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT11_XACTERR register field. */ +#define ALT_USB_HOST_HCINT11_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT11_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT11_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT11_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT11_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT11_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT11_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_BBLERR register field. */ +#define ALT_USB_HOST_HCINT11_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_BBLERR register field. */ +#define ALT_USB_HOST_HCINT11_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT11_BBLERR register field. */ +#define ALT_USB_HOST_HCINT11_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT11_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT11_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT11_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT11_BBLERR register field. */ +#define ALT_USB_HOST_HCINT11_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT11_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT11_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT11_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT11_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT11_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT11_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT11_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT11_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT11_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT11_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT11_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT11_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT11_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT11_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT11_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT11_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT11_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT11_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT11_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT11_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT11_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT11_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT11_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT11_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT11_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT11_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT11_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT11_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT11_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT11_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT11_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT11_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT11_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT11_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT11_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT11_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT11_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT11_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT11_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT11_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT11_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT11_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT11_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT11. + */ +struct ALT_USB_HOST_HCINT11_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT11. */ +typedef volatile struct ALT_USB_HOST_HCINT11_s ALT_USB_HOST_HCINT11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT11 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT11_OFST 0x268 +/* The address of the ALT_USB_HOST_HCINT11 register. */ +#define ALT_USB_HOST_HCINT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT11_OFST)) + +/* + * Register : Channel 11 Interrupt Mask Register - hcintmsk11 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK11_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK11. + */ +struct ALT_USB_HOST_HCINTMSK11_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK11. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK11_s ALT_USB_HOST_HCINTMSK11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK11 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK11_OFST 0x26c +/* The address of the ALT_USB_HOST_HCINTMSK11 register. */ +#define ALT_USB_HOST_HCINTMSK11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK11_OFST)) + +/* + * Register : Host Channel 11 Transfer Size Register - hctsiz11 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ11_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ11_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ11_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ11_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ11_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ11_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ11_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ11_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ11_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ11_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ11_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ11_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ11_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ11_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ11_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ11_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ11_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ11_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_PID register field. */ +#define ALT_USB_HOST_HCTSIZ11_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_PID register field. */ +#define ALT_USB_HOST_HCTSIZ11_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ11_PID register field. */ +#define ALT_USB_HOST_HCTSIZ11_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ11_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ11_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ11_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ11_PID register field. */ +#define ALT_USB_HOST_HCTSIZ11_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ11_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ11_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ11_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ11_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ11_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ11_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ11_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ11_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ11_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ11_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ11_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ11_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ11_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ11_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ11_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ11_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ11_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ11_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ11_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ11. + */ +struct ALT_USB_HOST_HCTSIZ11_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ11. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ11_s ALT_USB_HOST_HCTSIZ11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ11 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ11_OFST 0x270 +/* The address of the ALT_USB_HOST_HCTSIZ11 register. */ +#define ALT_USB_HOST_HCTSIZ11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ11_OFST)) + +/* + * Register : Host Channel 11 DMA Address Register - hcdma11 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma11 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */ +#define ALT_USB_HOST_HCDMA11_HCDMA11_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */ +#define ALT_USB_HOST_HCDMA11_HCDMA11_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */ +#define ALT_USB_HOST_HCDMA11_HCDMA11_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA11_HCDMA11 register field value. */ +#define ALT_USB_HOST_HCDMA11_HCDMA11_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA11_HCDMA11 register field value. */ +#define ALT_USB_HOST_HCDMA11_HCDMA11_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */ +#define ALT_USB_HOST_HCDMA11_HCDMA11_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA11_HCDMA11 field value from a register. */ +#define ALT_USB_HOST_HCDMA11_HCDMA11_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA11_HCDMA11 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA11_HCDMA11_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA11. + */ +struct ALT_USB_HOST_HCDMA11_s +{ + uint32_t hcdma11 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA11. */ +typedef volatile struct ALT_USB_HOST_HCDMA11_s ALT_USB_HOST_HCDMA11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA11 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA11_OFST 0x274 +/* The address of the ALT_USB_HOST_HCDMA11 register. */ +#define ALT_USB_HOST_HCDMA11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA11_OFST)) + +/* + * Register : Host Channel 11 DMA Buffer Address Register - hcdmab11 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------- + * [31:0] | RW | 0x0 | Host Channel 11 DMA Buffer Address + * + */ +/* + * Field : Host Channel 11 DMA Buffer Address - hcdmab11 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */ +#define ALT_USB_HOST_HCDMAB11_HCDMAB11_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */ +#define ALT_USB_HOST_HCDMAB11_HCDMAB11_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */ +#define ALT_USB_HOST_HCDMAB11_HCDMAB11_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value. */ +#define ALT_USB_HOST_HCDMAB11_HCDMAB11_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value. */ +#define ALT_USB_HOST_HCDMAB11_HCDMAB11_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */ +#define ALT_USB_HOST_HCDMAB11_HCDMAB11_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB11_HCDMAB11 field value from a register. */ +#define ALT_USB_HOST_HCDMAB11_HCDMAB11_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB11_HCDMAB11_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB11. + */ +struct ALT_USB_HOST_HCDMAB11_s +{ + uint32_t hcdmab11 : 32; /* Host Channel 11 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB11. */ +typedef volatile struct ALT_USB_HOST_HCDMAB11_s ALT_USB_HOST_HCDMAB11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB11 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB11_OFST 0x278 +/* The address of the ALT_USB_HOST_HCDMAB11 register. */ +#define ALT_USB_HOST_HCDMAB11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB11_OFST)) + +/* + * Register : Host Channel 12 Characteristics Register - hcchar12 + * + * Host Channel 1 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_MPS register field. */ +#define ALT_USB_HOST_HCCHAR12_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_MPS register field. */ +#define ALT_USB_HOST_HCCHAR12_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR12_MPS register field. */ +#define ALT_USB_HOST_HCCHAR12_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR12_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR12_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR12_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR12_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR12_MPS register field. */ +#define ALT_USB_HOST_HCCHAR12_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR12_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR12_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR12_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR12_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR12_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR12_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR12_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR12_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR12_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR12_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR12_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR12_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR12_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR12_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR12_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR12_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR12_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR12_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR12_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR12_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR12_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR12_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR12_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR12_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR12_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR12_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR12_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR12_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR12_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR12_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR12_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR12_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR12_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR12_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR12_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR12_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR12_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR12_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR12_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR12_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR12_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR12_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR12_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR12_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR12_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR12_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR12_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR12_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR12_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR12_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR12_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR12_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR12_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR12_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EC register field. */ +#define ALT_USB_HOST_HCCHAR12_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EC register field. */ +#define ALT_USB_HOST_HCCHAR12_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR12_EC register field. */ +#define ALT_USB_HOST_HCCHAR12_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR12_EC register field value. */ +#define ALT_USB_HOST_HCCHAR12_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EC register field value. */ +#define ALT_USB_HOST_HCCHAR12_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR12_EC register field. */ +#define ALT_USB_HOST_HCCHAR12_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR12_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR12_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR12_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR12_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR12_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR12_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR12_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR12_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR12_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR12_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR12_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR12_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR12_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR12_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR12_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR12_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR12_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR12_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR12_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR12_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR12_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR12_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR12_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR12_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR12_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR12_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR12_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR12_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR12_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR12_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR12_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR12_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR12_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR12_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR12_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR12_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR12_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR12_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR12_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR12_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR12_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR12_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR12_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR12_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR12_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR12_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR12_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR12_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR12_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR12_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR12. + */ +struct ALT_USB_HOST_HCCHAR12_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR12. */ +typedef volatile struct ALT_USB_HOST_HCCHAR12_s ALT_USB_HOST_HCCHAR12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR12 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR12_OFST 0x280 +/* The address of the ALT_USB_HOST_HCCHAR12 register. */ +#define ALT_USB_HOST_HCCHAR12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR12_OFST)) + +/* + * Register : Host Channel 12 Split Control Register - hcsplt12 + * + * Channel_number 1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT12_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT12_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT12_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT12_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT12_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT12_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT12_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT12_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT12_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT12_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT12_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT12_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT12_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT12_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT12_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT12_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT12_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT12_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT12_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT12_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT12_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT12_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT12_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT12_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT12_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT12_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT12_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT12_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT12_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT12_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT12_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT12_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT12_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT12_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT12_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT12_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT12_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT12_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT12_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT12_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT12_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT12_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT12_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT12_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT12_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT12_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT12_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT12_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT12_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT12_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT12_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT12_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT12_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT12_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT12_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT12_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT12_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT12_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT12_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT12_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT12_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT12_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT12_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT12_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT12_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT12_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT12_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT12_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT12_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT12. + */ +struct ALT_USB_HOST_HCSPLT12_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT12. */ +typedef volatile struct ALT_USB_HOST_HCSPLT12_s ALT_USB_HOST_HCSPLT12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT12 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT12_OFST 0x284 +/* The address of the ALT_USB_HOST_HCSPLT12 register. */ +#define ALT_USB_HOST_HCSPLT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT12_OFST)) + +/* + * Register : Host Channel 12 Interrupt Register - hcint12 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT12_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT12_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT12_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT12_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT12_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT12_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT12_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT12_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT12_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT12_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT12_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT12_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT12_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT12_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT12_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT12_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT12_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT12_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT12_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT12_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT12_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT12_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT12_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT12_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT12_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT12_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT12_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT12_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT12_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT12_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT12_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_AHBERR register field. */ +#define ALT_USB_HOST_HCINT12_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_AHBERR register field. */ +#define ALT_USB_HOST_HCINT12_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT12_AHBERR register field. */ +#define ALT_USB_HOST_HCINT12_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT12_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT12_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT12_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT12_AHBERR register field. */ +#define ALT_USB_HOST_HCINT12_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT12_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT12_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT12_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT12_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT12_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_STALL register field. */ +#define ALT_USB_HOST_HCINT12_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_STALL register field. */ +#define ALT_USB_HOST_HCINT12_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT12_STALL register field. */ +#define ALT_USB_HOST_HCINT12_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_STALL register field value. */ +#define ALT_USB_HOST_HCINT12_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT12_STALL register field value. */ +#define ALT_USB_HOST_HCINT12_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT12_STALL register field. */ +#define ALT_USB_HOST_HCINT12_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT12_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT12_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT12_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT12_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT12_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT12_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_NAK register field. */ +#define ALT_USB_HOST_HCINT12_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_NAK register field. */ +#define ALT_USB_HOST_HCINT12_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT12_NAK register field. */ +#define ALT_USB_HOST_HCINT12_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_NAK register field value. */ +#define ALT_USB_HOST_HCINT12_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT12_NAK register field value. */ +#define ALT_USB_HOST_HCINT12_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT12_NAK register field. */ +#define ALT_USB_HOST_HCINT12_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT12_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT12_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT12_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT12_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT12_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT12_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_ACK register field. */ +#define ALT_USB_HOST_HCINT12_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_ACK register field. */ +#define ALT_USB_HOST_HCINT12_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT12_ACK register field. */ +#define ALT_USB_HOST_HCINT12_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_ACK register field value. */ +#define ALT_USB_HOST_HCINT12_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT12_ACK register field value. */ +#define ALT_USB_HOST_HCINT12_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT12_ACK register field. */ +#define ALT_USB_HOST_HCINT12_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT12_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT12_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT12_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT12_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT12_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT12_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_NYET register field. */ +#define ALT_USB_HOST_HCINT12_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_NYET register field. */ +#define ALT_USB_HOST_HCINT12_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT12_NYET register field. */ +#define ALT_USB_HOST_HCINT12_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_NYET register field value. */ +#define ALT_USB_HOST_HCINT12_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT12_NYET register field value. */ +#define ALT_USB_HOST_HCINT12_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT12_NYET register field. */ +#define ALT_USB_HOST_HCINT12_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT12_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT12_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT12_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT12_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT12_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT12_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XACTERR register field. */ +#define ALT_USB_HOST_HCINT12_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XACTERR register field. */ +#define ALT_USB_HOST_HCINT12_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT12_XACTERR register field. */ +#define ALT_USB_HOST_HCINT12_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT12_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT12_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT12_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT12_XACTERR register field. */ +#define ALT_USB_HOST_HCINT12_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT12_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT12_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT12_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT12_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT12_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT12_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_BBLERR register field. */ +#define ALT_USB_HOST_HCINT12_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_BBLERR register field. */ +#define ALT_USB_HOST_HCINT12_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT12_BBLERR register field. */ +#define ALT_USB_HOST_HCINT12_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT12_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT12_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT12_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT12_BBLERR register field. */ +#define ALT_USB_HOST_HCINT12_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT12_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT12_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT12_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT12_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT12_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT12_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT12_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT12_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT12_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT12_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT12_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT12_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT12_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT12_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT12_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT12_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT12_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT12_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT12_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT12_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT12_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT12_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT12_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT12_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT12_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT12_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT12_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT12_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT12_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT12_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT12_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT12_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT12_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT12_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT12_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT12_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT12_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT12_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT12_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT12_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT12_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT12_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT12_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT12. + */ +struct ALT_USB_HOST_HCINT12_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT12. */ +typedef volatile struct ALT_USB_HOST_HCINT12_s ALT_USB_HOST_HCINT12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT12 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT12_OFST 0x288 +/* The address of the ALT_USB_HOST_HCINT12 register. */ +#define ALT_USB_HOST_HCINT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT12_OFST)) + +/* + * Register : Host Channel 12 Interrupt Mask Register - hcintmsk12 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK12_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK12. + */ +struct ALT_USB_HOST_HCINTMSK12_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK12. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK12_s ALT_USB_HOST_HCINTMSK12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK12 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK12_OFST 0x28c +/* The address of the ALT_USB_HOST_HCINTMSK12 register. */ +#define ALT_USB_HOST_HCINTMSK12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK12_OFST)) + +/* + * Register : Host Channel 12 Transfer Size Register - hctsiz12 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ12_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ12_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ12_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ12_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ12_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ12_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ12_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ12_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ12_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ12_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ12_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ12_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ12_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ12_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ12_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ12_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ12_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ12_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_PID register field. */ +#define ALT_USB_HOST_HCTSIZ12_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_PID register field. */ +#define ALT_USB_HOST_HCTSIZ12_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ12_PID register field. */ +#define ALT_USB_HOST_HCTSIZ12_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ12_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ12_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ12_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ12_PID register field. */ +#define ALT_USB_HOST_HCTSIZ12_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ12_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ12_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ12_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ12_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ12_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ12_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ12_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ12_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ12_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ12_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ12_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ12_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ12_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ12_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ12_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ12_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ12_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ12_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ12_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ12. + */ +struct ALT_USB_HOST_HCTSIZ12_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ12. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ12_s ALT_USB_HOST_HCTSIZ12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ12 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ12_OFST 0x290 +/* The address of the ALT_USB_HOST_HCTSIZ12 register. */ +#define ALT_USB_HOST_HCTSIZ12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ12_OFST)) + +/* + * Register : Host Channel 12 DMA Address Register - hcdma12 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma12 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */ +#define ALT_USB_HOST_HCDMA12_HCDMA12_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */ +#define ALT_USB_HOST_HCDMA12_HCDMA12_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */ +#define ALT_USB_HOST_HCDMA12_HCDMA12_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA12_HCDMA12 register field value. */ +#define ALT_USB_HOST_HCDMA12_HCDMA12_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA12_HCDMA12 register field value. */ +#define ALT_USB_HOST_HCDMA12_HCDMA12_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */ +#define ALT_USB_HOST_HCDMA12_HCDMA12_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA12_HCDMA12 field value from a register. */ +#define ALT_USB_HOST_HCDMA12_HCDMA12_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA12_HCDMA12 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA12_HCDMA12_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA12. + */ +struct ALT_USB_HOST_HCDMA12_s +{ + uint32_t hcdma12 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA12. */ +typedef volatile struct ALT_USB_HOST_HCDMA12_s ALT_USB_HOST_HCDMA12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA12 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA12_OFST 0x294 +/* The address of the ALT_USB_HOST_HCDMA12 register. */ +#define ALT_USB_HOST_HCDMA12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA12_OFST)) + +/* + * Register : Host Channel 12 DMA Buffer Address Register - hcdmab12 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This register + * is present only in Scatter/Gather DMA mode. Otherwise this field is + * reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 0 DMA Buffer Address + * + */ +/* + * Field : Host Channel 0 DMA Buffer Address - hcdmab12 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */ +#define ALT_USB_HOST_HCDMAB12_HCDMAB12_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */ +#define ALT_USB_HOST_HCDMAB12_HCDMAB12_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */ +#define ALT_USB_HOST_HCDMAB12_HCDMAB12_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value. */ +#define ALT_USB_HOST_HCDMAB12_HCDMAB12_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value. */ +#define ALT_USB_HOST_HCDMAB12_HCDMAB12_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */ +#define ALT_USB_HOST_HCDMAB12_HCDMAB12_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB12_HCDMAB12 field value from a register. */ +#define ALT_USB_HOST_HCDMAB12_HCDMAB12_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB12_HCDMAB12_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB12. + */ +struct ALT_USB_HOST_HCDMAB12_s +{ + uint32_t hcdmab12 : 32; /* Host Channel 0 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB12. */ +typedef volatile struct ALT_USB_HOST_HCDMAB12_s ALT_USB_HOST_HCDMAB12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB12 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB12_OFST 0x298 +/* The address of the ALT_USB_HOST_HCDMAB12 register. */ +#define ALT_USB_HOST_HCDMAB12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB12_OFST)) + +/* + * Register : Host Channel 13 Characteristics Register - hcchar13 + * + * Host Channel 13 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_MPS register field. */ +#define ALT_USB_HOST_HCCHAR13_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_MPS register field. */ +#define ALT_USB_HOST_HCCHAR13_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR13_MPS register field. */ +#define ALT_USB_HOST_HCCHAR13_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR13_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR13_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR13_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR13_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR13_MPS register field. */ +#define ALT_USB_HOST_HCCHAR13_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR13_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR13_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR13_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR13_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR13_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR13_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR13_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR13_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR13_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR13_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR13_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR13_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR13_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR13_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR13_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR13_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR13_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR13_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR13_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR13_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR13_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR13_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR13_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR13_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR13_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR13_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR13_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR13_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR13_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR13_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR13_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR13_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR13_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR13_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR13_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR13_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR13_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR13_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR13_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR13_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR13_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR13_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR13_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR13_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR13_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR13_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR13_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR13_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR13_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR13_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR13_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR13_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR13_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR13_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EC register field. */ +#define ALT_USB_HOST_HCCHAR13_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EC register field. */ +#define ALT_USB_HOST_HCCHAR13_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR13_EC register field. */ +#define ALT_USB_HOST_HCCHAR13_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR13_EC register field value. */ +#define ALT_USB_HOST_HCCHAR13_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EC register field value. */ +#define ALT_USB_HOST_HCCHAR13_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR13_EC register field. */ +#define ALT_USB_HOST_HCCHAR13_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR13_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR13_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR13_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR13_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR13_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR13_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR13_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR13_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR13_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR13_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR13_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR13_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR13_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR13_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR13_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR13_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR13_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR13_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR13_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR13_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR13_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR13_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR13_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR13_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR13_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR13_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR13_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR13_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR13_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR13_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR13_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR13_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR13_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR13_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR13_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR13_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR13_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR13_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR13_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR13_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR13_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR13_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR13_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR13_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR13_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR13_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR13_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR13_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR13_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR13_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR13. + */ +struct ALT_USB_HOST_HCCHAR13_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR13. */ +typedef volatile struct ALT_USB_HOST_HCCHAR13_s ALT_USB_HOST_HCCHAR13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR13 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR13_OFST 0x2a0 +/* The address of the ALT_USB_HOST_HCCHAR13 register. */ +#define ALT_USB_HOST_HCCHAR13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR13_OFST)) + +/* + * Register : Host Channel 13 Split Control Register - hcsplt13 + * + * Channel_number 13. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT13_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT13_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT13_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT13_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT13_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT13_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT13_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT13_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT13_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT13_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT13_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT13_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT13_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT13_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT13_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT13_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT13_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT13_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT13_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT13_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT13_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT13_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT13_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT13_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT13_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT13_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT13_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT13_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT13_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT13_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT13_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT13_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT13_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT13_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT13_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT13_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT13_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT13_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT13_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT13_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT13_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT13_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT13_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT13_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT13_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT13_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT13_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT13_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT13_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT13_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT13_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT13_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT13_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT13_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT13_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT13_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT13_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT13_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT13_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT13_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT13_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT13_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT13_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT13_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT13_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT13_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT13_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT13_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT13_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT13. + */ +struct ALT_USB_HOST_HCSPLT13_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT13. */ +typedef volatile struct ALT_USB_HOST_HCSPLT13_s ALT_USB_HOST_HCSPLT13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT13 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT13_OFST 0x2a4 +/* The address of the ALT_USB_HOST_HCSPLT13 register. */ +#define ALT_USB_HOST_HCSPLT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT13_OFST)) + +/* + * Register : Host Channel 13 Interrupt Register - hcint13 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT13_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT13_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT13_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT13_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT13_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT13_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT13_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT13_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT13_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT13_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT13_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT13_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT13_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT13_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT13_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT13_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT13_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT13_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT13_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT13_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT13_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT13_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT13_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT13_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT13_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT13_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT13_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT13_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT13_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT13_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT13_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_AHBERR register field. */ +#define ALT_USB_HOST_HCINT13_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_AHBERR register field. */ +#define ALT_USB_HOST_HCINT13_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT13_AHBERR register field. */ +#define ALT_USB_HOST_HCINT13_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT13_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT13_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT13_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT13_AHBERR register field. */ +#define ALT_USB_HOST_HCINT13_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT13_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT13_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT13_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT13_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT13_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_STALL register field. */ +#define ALT_USB_HOST_HCINT13_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_STALL register field. */ +#define ALT_USB_HOST_HCINT13_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT13_STALL register field. */ +#define ALT_USB_HOST_HCINT13_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_STALL register field value. */ +#define ALT_USB_HOST_HCINT13_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT13_STALL register field value. */ +#define ALT_USB_HOST_HCINT13_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT13_STALL register field. */ +#define ALT_USB_HOST_HCINT13_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT13_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT13_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT13_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT13_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT13_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT13_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_NAK register field. */ +#define ALT_USB_HOST_HCINT13_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_NAK register field. */ +#define ALT_USB_HOST_HCINT13_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT13_NAK register field. */ +#define ALT_USB_HOST_HCINT13_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_NAK register field value. */ +#define ALT_USB_HOST_HCINT13_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT13_NAK register field value. */ +#define ALT_USB_HOST_HCINT13_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT13_NAK register field. */ +#define ALT_USB_HOST_HCINT13_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT13_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT13_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT13_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT13_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT13_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT13_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_ACK register field. */ +#define ALT_USB_HOST_HCINT13_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_ACK register field. */ +#define ALT_USB_HOST_HCINT13_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT13_ACK register field. */ +#define ALT_USB_HOST_HCINT13_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_ACK register field value. */ +#define ALT_USB_HOST_HCINT13_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT13_ACK register field value. */ +#define ALT_USB_HOST_HCINT13_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT13_ACK register field. */ +#define ALT_USB_HOST_HCINT13_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT13_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT13_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT13_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT13_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT13_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT13_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_NYET register field. */ +#define ALT_USB_HOST_HCINT13_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_NYET register field. */ +#define ALT_USB_HOST_HCINT13_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT13_NYET register field. */ +#define ALT_USB_HOST_HCINT13_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_NYET register field value. */ +#define ALT_USB_HOST_HCINT13_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT13_NYET register field value. */ +#define ALT_USB_HOST_HCINT13_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT13_NYET register field. */ +#define ALT_USB_HOST_HCINT13_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT13_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT13_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT13_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT13_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT13_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT13_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XACTERR register field. */ +#define ALT_USB_HOST_HCINT13_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XACTERR register field. */ +#define ALT_USB_HOST_HCINT13_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT13_XACTERR register field. */ +#define ALT_USB_HOST_HCINT13_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT13_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT13_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT13_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT13_XACTERR register field. */ +#define ALT_USB_HOST_HCINT13_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT13_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT13_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT13_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT13_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT13_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT13_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_BBLERR register field. */ +#define ALT_USB_HOST_HCINT13_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_BBLERR register field. */ +#define ALT_USB_HOST_HCINT13_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT13_BBLERR register field. */ +#define ALT_USB_HOST_HCINT13_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT13_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT13_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT13_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT13_BBLERR register field. */ +#define ALT_USB_HOST_HCINT13_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT13_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT13_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT13_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT13_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT13_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT13_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT13_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT13_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT13_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT13_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT13_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT13_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT13_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT13_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT13_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT13_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT13_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT13_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT13_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT13_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT13_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT13_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT13_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT13_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT13_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT13_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT13_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT13_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT13_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT13_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT13_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT13_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT13_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT13_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT13_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT13_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT13_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT13_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT13_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT13_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT13_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT13_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT13_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT13. + */ +struct ALT_USB_HOST_HCINT13_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT13. */ +typedef volatile struct ALT_USB_HOST_HCINT13_s ALT_USB_HOST_HCINT13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT13 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT13_OFST 0x2a8 +/* The address of the ALT_USB_HOST_HCINT13 register. */ +#define ALT_USB_HOST_HCINT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT13_OFST)) + +/* + * Register : Host Channel 13 Interrupt Mask Registe - hcintmsk13 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK13_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK13. + */ +struct ALT_USB_HOST_HCINTMSK13_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK13. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK13_s ALT_USB_HOST_HCINTMSK13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK13 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK13_OFST 0x2ac +/* The address of the ALT_USB_HOST_HCINTMSK13 register. */ +#define ALT_USB_HOST_HCINTMSK13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK13_OFST)) + +/* + * Register : Host Channel 13 Transfer Size Register - hctsiz13 + * + * Buffer DMA Mode + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ13_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ13_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ13_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ13_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ13_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ13_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ13_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ13_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ13_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ13_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ13_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ13_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ13_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ13_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ13_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ13_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ13_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ13_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_PID register field. */ +#define ALT_USB_HOST_HCTSIZ13_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_PID register field. */ +#define ALT_USB_HOST_HCTSIZ13_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ13_PID register field. */ +#define ALT_USB_HOST_HCTSIZ13_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ13_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ13_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ13_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ13_PID register field. */ +#define ALT_USB_HOST_HCTSIZ13_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ13_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ13_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ13_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ13_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ13_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ13_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ13_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ13_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ13_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ13_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ13_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ13_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ13_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ13_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ13_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ13_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ13_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ13_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ13_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ13. + */ +struct ALT_USB_HOST_HCTSIZ13_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ13. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ13_s ALT_USB_HOST_HCTSIZ13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ13 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ13_OFST 0x2b0 +/* The address of the ALT_USB_HOST_HCTSIZ13 register. */ +#define ALT_USB_HOST_HCTSIZ13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ13_OFST)) + +/* + * Register : Host Channel 13 DMA Address Register - hcdma13 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma13 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */ +#define ALT_USB_HOST_HCDMA13_HCDMA13_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */ +#define ALT_USB_HOST_HCDMA13_HCDMA13_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */ +#define ALT_USB_HOST_HCDMA13_HCDMA13_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA13_HCDMA13 register field value. */ +#define ALT_USB_HOST_HCDMA13_HCDMA13_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA13_HCDMA13 register field value. */ +#define ALT_USB_HOST_HCDMA13_HCDMA13_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */ +#define ALT_USB_HOST_HCDMA13_HCDMA13_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA13_HCDMA13 field value from a register. */ +#define ALT_USB_HOST_HCDMA13_HCDMA13_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA13_HCDMA13 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA13_HCDMA13_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA13. + */ +struct ALT_USB_HOST_HCDMA13_s +{ + uint32_t hcdma13 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA13. */ +typedef volatile struct ALT_USB_HOST_HCDMA13_s ALT_USB_HOST_HCDMA13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA13 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA13_OFST 0x2b4 +/* The address of the ALT_USB_HOST_HCDMA13 register. */ +#define ALT_USB_HOST_HCDMA13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA13_OFST)) + +/* + * Register : Host Channel 13 DMA Buffer Address Register - hcdmab13 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------- + * [31:0] | RW | 0x0 | Host Channel 13 DMA Buffer Address + * + */ +/* + * Field : Host Channel 13 DMA Buffer Address - hcdmab13 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */ +#define ALT_USB_HOST_HCDMAB13_HCDMAB13_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */ +#define ALT_USB_HOST_HCDMAB13_HCDMAB13_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */ +#define ALT_USB_HOST_HCDMAB13_HCDMAB13_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value. */ +#define ALT_USB_HOST_HCDMAB13_HCDMAB13_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value. */ +#define ALT_USB_HOST_HCDMAB13_HCDMAB13_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */ +#define ALT_USB_HOST_HCDMAB13_HCDMAB13_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB13_HCDMAB13 field value from a register. */ +#define ALT_USB_HOST_HCDMAB13_HCDMAB13_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB13_HCDMAB13_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB13. + */ +struct ALT_USB_HOST_HCDMAB13_s +{ + uint32_t hcdmab13 : 32; /* Host Channel 13 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB13. */ +typedef volatile struct ALT_USB_HOST_HCDMAB13_s ALT_USB_HOST_HCDMAB13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB13 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB13_OFST 0x2b8 +/* The address of the ALT_USB_HOST_HCDMAB13 register. */ +#define ALT_USB_HOST_HCDMAB13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB13_OFST)) + +/* + * Register : Host Channel 14 Characteristics Register - hcchar14 + * + * Host Channel 1 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_MPS register field. */ +#define ALT_USB_HOST_HCCHAR14_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_MPS register field. */ +#define ALT_USB_HOST_HCCHAR14_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR14_MPS register field. */ +#define ALT_USB_HOST_HCCHAR14_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR14_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR14_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR14_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR14_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR14_MPS register field. */ +#define ALT_USB_HOST_HCCHAR14_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR14_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR14_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR14_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR14_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR14_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR14_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR14_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR14_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR14_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR14_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR14_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR14_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR14_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR14_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR14_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR14_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR14_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR14_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR14_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR14_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR14_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR14_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR14_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 0x3 while communicating + * to the LS Device through the FS hub. In a peer to peer setup, the HS OTG Host + * core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR14_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR14_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR14_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR14_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR14_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR14_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR14_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR14_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR14_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR14_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR14_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR14_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR14_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR14_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR14_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR14_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR14_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR14_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR14_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR14_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR14_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR14_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR14_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR14_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR14_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR14_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR14_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR14_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR14_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR14_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR14_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EC register field. */ +#define ALT_USB_HOST_HCCHAR14_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EC register field. */ +#define ALT_USB_HOST_HCCHAR14_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR14_EC register field. */ +#define ALT_USB_HOST_HCCHAR14_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR14_EC register field value. */ +#define ALT_USB_HOST_HCCHAR14_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EC register field value. */ +#define ALT_USB_HOST_HCCHAR14_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR14_EC register field. */ +#define ALT_USB_HOST_HCCHAR14_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR14_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR14_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR14_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR14_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR14_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR14_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR14_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR14_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR14_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR14_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR14_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR14_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR14_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR14_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR14_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR14_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR14_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR14_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR14_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR14_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR14_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR14_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR14_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR14_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR14_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR14_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR14_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR14_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR14_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR14_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR14_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR14_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR14_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR14_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR14_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR14_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR14_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR14_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR14_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR14_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR14_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR14_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR14_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR14_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR14_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR14_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR14_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR14_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR14_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR14_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR14. + */ +struct ALT_USB_HOST_HCCHAR14_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR14. */ +typedef volatile struct ALT_USB_HOST_HCCHAR14_s ALT_USB_HOST_HCCHAR14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR14 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR14_OFST 0x2c0 +/* The address of the ALT_USB_HOST_HCCHAR14 register. */ +#define ALT_USB_HOST_HCCHAR14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR14_OFST)) + +/* + * Register : Host Channel 14 Split Control Register - hcsplt14 + * + * Channel_number 14 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT14_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT14_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT14_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT14_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT14_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT14_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT14_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT14_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT14_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT14_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT14_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT14_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT14_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT14_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT14_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT14_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT14_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT14_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT14_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT14_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT14_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT14_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT14_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT14_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT14_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT14_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT14_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT14_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT14_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT14_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT14_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT14_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT14_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT14_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT14_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT14_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT14_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT14_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT14_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT14_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT14_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT14_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT14_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT14_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT14_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT14_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT14_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT14_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT14_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT14_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT14_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT14_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT14_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT14_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT14_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT14_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT14_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT14_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT14_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT14_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT14_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT14_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT14_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT14_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT14_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT14_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT14_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT14_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT14_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT14. + */ +struct ALT_USB_HOST_HCSPLT14_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT14. */ +typedef volatile struct ALT_USB_HOST_HCSPLT14_s ALT_USB_HOST_HCSPLT14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT14 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT14_OFST 0x2c4 +/* The address of the ALT_USB_HOST_HCSPLT14 register. */ +#define ALT_USB_HOST_HCSPLT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT14_OFST)) + +/* + * Register : Host Channel 14 Interrupt Register - hcint14 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT14_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT14_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT14_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT14_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT14_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT14_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT14_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT14_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT14_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT14_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT14_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT14_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT14_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT14_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT14_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT14_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT14_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT14_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT14_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT14_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT14_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT14_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT14_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT14_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT14_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT14_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT14_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT14_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT14_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT14_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT14_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_AHBERR register field. */ +#define ALT_USB_HOST_HCINT14_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_AHBERR register field. */ +#define ALT_USB_HOST_HCINT14_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT14_AHBERR register field. */ +#define ALT_USB_HOST_HCINT14_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT14_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT14_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT14_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT14_AHBERR register field. */ +#define ALT_USB_HOST_HCINT14_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT14_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT14_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT14_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT14_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT14_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_STALL register field. */ +#define ALT_USB_HOST_HCINT14_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_STALL register field. */ +#define ALT_USB_HOST_HCINT14_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT14_STALL register field. */ +#define ALT_USB_HOST_HCINT14_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_STALL register field value. */ +#define ALT_USB_HOST_HCINT14_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT14_STALL register field value. */ +#define ALT_USB_HOST_HCINT14_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT14_STALL register field. */ +#define ALT_USB_HOST_HCINT14_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT14_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT14_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT14_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT14_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT14_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT14_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_NAK register field. */ +#define ALT_USB_HOST_HCINT14_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_NAK register field. */ +#define ALT_USB_HOST_HCINT14_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT14_NAK register field. */ +#define ALT_USB_HOST_HCINT14_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_NAK register field value. */ +#define ALT_USB_HOST_HCINT14_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT14_NAK register field value. */ +#define ALT_USB_HOST_HCINT14_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT14_NAK register field. */ +#define ALT_USB_HOST_HCINT14_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT14_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT14_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT14_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT14_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT14_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT14_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_ACK register field. */ +#define ALT_USB_HOST_HCINT14_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_ACK register field. */ +#define ALT_USB_HOST_HCINT14_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT14_ACK register field. */ +#define ALT_USB_HOST_HCINT14_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_ACK register field value. */ +#define ALT_USB_HOST_HCINT14_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT14_ACK register field value. */ +#define ALT_USB_HOST_HCINT14_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT14_ACK register field. */ +#define ALT_USB_HOST_HCINT14_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT14_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT14_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT14_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT14_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT14_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT14_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_NYET register field. */ +#define ALT_USB_HOST_HCINT14_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_NYET register field. */ +#define ALT_USB_HOST_HCINT14_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT14_NYET register field. */ +#define ALT_USB_HOST_HCINT14_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_NYET register field value. */ +#define ALT_USB_HOST_HCINT14_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT14_NYET register field value. */ +#define ALT_USB_HOST_HCINT14_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT14_NYET register field. */ +#define ALT_USB_HOST_HCINT14_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT14_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT14_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT14_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT14_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT14_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT14_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XACTERR register field. */ +#define ALT_USB_HOST_HCINT14_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XACTERR register field. */ +#define ALT_USB_HOST_HCINT14_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT14_XACTERR register field. */ +#define ALT_USB_HOST_HCINT14_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT14_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT14_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT14_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT14_XACTERR register field. */ +#define ALT_USB_HOST_HCINT14_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT14_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT14_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT14_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT14_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT14_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT14_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_BBLERR register field. */ +#define ALT_USB_HOST_HCINT14_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_BBLERR register field. */ +#define ALT_USB_HOST_HCINT14_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT14_BBLERR register field. */ +#define ALT_USB_HOST_HCINT14_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT14_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT14_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT14_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT14_BBLERR register field. */ +#define ALT_USB_HOST_HCINT14_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT14_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT14_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT14_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT14_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT14_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT14_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT14_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT14_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT14_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT14_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT14_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT14_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT14_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT14_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT14_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT14_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT14_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT14_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT14_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT14_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT14_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT14_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT14_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT14_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT14_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT14_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT14_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT14_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT14_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT14_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT14_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT14_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT14_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT14_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT14_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT14_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT14_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT14_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT14_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT14_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT14_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT14_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT14_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT14. + */ +struct ALT_USB_HOST_HCINT14_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT14. */ +typedef volatile struct ALT_USB_HOST_HCINT14_s ALT_USB_HOST_HCINT14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT14 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT14_OFST 0x2c8 +/* The address of the ALT_USB_HOST_HCINT14 register. */ +#define ALT_USB_HOST_HCINT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT14_OFST)) + +/* + * Register : Host Channel 14 Interrupt Mask Register - hcintmsk14 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK14_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK14. + */ +struct ALT_USB_HOST_HCINTMSK14_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK14. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK14_s ALT_USB_HOST_HCINTMSK14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK14 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK14_OFST 0x2cc +/* The address of the ALT_USB_HOST_HCINTMSK14 register. */ +#define ALT_USB_HOST_HCINTMSK14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK14_OFST)) + +/* + * Register : Host Channel 14 Transfer Size Register - hctsiz14 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic). The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ14_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ14_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ14_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ14_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ14_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ14_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ14_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ14_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ14_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ14_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ14_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ14_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ14_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ14_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ14_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ14_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ14_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ14_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_PID register field. */ +#define ALT_USB_HOST_HCTSIZ14_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_PID register field. */ +#define ALT_USB_HOST_HCTSIZ14_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ14_PID register field. */ +#define ALT_USB_HOST_HCTSIZ14_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ14_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ14_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ14_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ14_PID register field. */ +#define ALT_USB_HOST_HCTSIZ14_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ14_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ14_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ14_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ14_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ14_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ14_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ14_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ14_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ14_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ14_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ14_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ14_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ14_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ14_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ14_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ14_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ14_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ14_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ14_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ14. + */ +struct ALT_USB_HOST_HCTSIZ14_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ14. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ14_s ALT_USB_HOST_HCTSIZ14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ14 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ14_OFST 0x2d0 +/* The address of the ALT_USB_HOST_HCTSIZ14 register. */ +#define ALT_USB_HOST_HCTSIZ14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ14_OFST)) + +/* + * Register : Host Channel 14 DMA Address Register - hcdma14 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma14 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */ +#define ALT_USB_HOST_HCDMA14_HCDMA14_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */ +#define ALT_USB_HOST_HCDMA14_HCDMA14_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */ +#define ALT_USB_HOST_HCDMA14_HCDMA14_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA14_HCDMA14 register field value. */ +#define ALT_USB_HOST_HCDMA14_HCDMA14_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA14_HCDMA14 register field value. */ +#define ALT_USB_HOST_HCDMA14_HCDMA14_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */ +#define ALT_USB_HOST_HCDMA14_HCDMA14_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA14_HCDMA14 field value from a register. */ +#define ALT_USB_HOST_HCDMA14_HCDMA14_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA14_HCDMA14 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA14_HCDMA14_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA14. + */ +struct ALT_USB_HOST_HCDMA14_s +{ + uint32_t hcdma14 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA14. */ +typedef volatile struct ALT_USB_HOST_HCDMA14_s ALT_USB_HOST_HCDMA14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA14 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA14_OFST 0x2d4 +/* The address of the ALT_USB_HOST_HCDMA14 register. */ +#define ALT_USB_HOST_HCDMA14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA14_OFST)) + +/* + * Register : Host Channel 14 DMA Buffer Address Register - hcdmab14 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:---------------------------------- + * [31:0] | RW | 0x0 | Host Channel 0 DMA Buffer Address + * + */ +/* + * Field : Host Channel 0 DMA Buffer Address - hcdmab14 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */ +#define ALT_USB_HOST_HCDMAB14_HCDMAB14_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */ +#define ALT_USB_HOST_HCDMAB14_HCDMAB14_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */ +#define ALT_USB_HOST_HCDMAB14_HCDMAB14_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value. */ +#define ALT_USB_HOST_HCDMAB14_HCDMAB14_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value. */ +#define ALT_USB_HOST_HCDMAB14_HCDMAB14_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */ +#define ALT_USB_HOST_HCDMAB14_HCDMAB14_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB14_HCDMAB14 field value from a register. */ +#define ALT_USB_HOST_HCDMAB14_HCDMAB14_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB14_HCDMAB14_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB14. + */ +struct ALT_USB_HOST_HCDMAB14_s +{ + uint32_t hcdmab14 : 32; /* Host Channel 0 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB14. */ +typedef volatile struct ALT_USB_HOST_HCDMAB14_s ALT_USB_HOST_HCDMAB14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB14 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB14_OFST 0x2d8 +/* The address of the ALT_USB_HOST_HCDMAB14 register. */ +#define ALT_USB_HOST_HCDMAB14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB14_OFST)) + +/* + * Register : Host Channel 15 Characteristics Register - hcchar15 + * + * Host Channel 15 Characteristics Register + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | RW | 0x0 | Endpoint Number + * [15] | RW | 0x0 | Endpoint Direction + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | RW | 0x0 | Low-Speed Device + * [19:18] | RW | 0x0 | Endpoint Type + * [21:20] | RW | 0x0 | Multi Count + * [28:22] | RW | 0x0 | Device Address + * [29] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Channel Disable + * [31] | R | 0x0 | Channel Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Indicates the maximum packet size of the associated endpoint. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_MPS register field. */ +#define ALT_USB_HOST_HCCHAR15_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_MPS register field. */ +#define ALT_USB_HOST_HCCHAR15_MPS_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCCHAR15_MPS register field. */ +#define ALT_USB_HOST_HCCHAR15_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_HOST_HCCHAR15_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR15_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_HOST_HCCHAR15_MPS register field value. */ +#define ALT_USB_HOST_HCCHAR15_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_HOST_HCCHAR15_MPS register field. */ +#define ALT_USB_HOST_HCCHAR15_MPS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR15_MPS field value from a register. */ +#define ALT_USB_HOST_HCCHAR15_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_HOST_HCCHAR15_MPS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR15_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : Endpoint Number - epnum + * + * Indicates the endpoint number on the device serving as the data source or sink. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT0 | 0x0 | End point 0 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT1 | 0x1 | End point 1 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT2 | 0x2 | End point 2 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT3 | 0x3 | End point 3 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT4 | 0x4 | End point 4 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT5 | 0x5 | End point 5 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT6 | 0x6 | End point 6 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT7 | 0x7 | End point 7 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT8 | 0x8 | End point 8 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT9 | 0x9 | End point 9 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT10 | 0xa | End point 10 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT11 | 0xb | End point 11 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT12 | 0xc | End point 12 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT13 | 0xd | End point 13 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT14 | 0xe | End point 14 + * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT15 | 0xf | End point 15 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 0 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 1 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT1 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 2 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT2 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 3 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT3 0x3 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 4 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT4 0x4 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 5 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT5 0x5 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 6 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT6 0x6 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 7 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT7 0x7 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 8 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT8 0x8 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 9 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT9 0x9 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 10 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT10 0xa +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 11 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT11 0xb +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 12 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT12 0xc +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 13 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT13 0xd +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 14 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT14 0xe +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM + * + * End point 15 + */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT15 0xf + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_MSB 14 +/* The width in bits of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_WIDTH 4 +/* The mask used to set the ALT_USB_HOST_HCCHAR15_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_SET_MSK 0x00007800 +/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPNUM register field value. */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_CLR_MSK 0xffff87ff +/* The reset value of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR15_EPNUM field value from a register. */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_GET(value) (((value) & 0x00007800) >> 11) +/* Produces a ALT_USB_HOST_HCCHAR15_EPNUM register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR15_EPNUM_SET(value) (((value) << 11) & 0x00007800) + +/* + * Field : Endpoint Direction - epdir + * + * Indicates whether the transaction is IN or OUT. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:-------------- + * ALT_USB_HOST_HCCHAR15_EPDIR_E_OUT | 0x0 | OUT Direction + * ALT_USB_HOST_HCCHAR15_EPDIR_E_IN | 0x1 | IN Direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPDIR + * + * OUT Direction + */ +#define ALT_USB_HOST_HCCHAR15_EPDIR_E_OUT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPDIR + * + * IN Direction + */ +#define ALT_USB_HOST_HCCHAR15_EPDIR_E_IN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR15_EPDIR_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR15_EPDIR_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR15_EPDIR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR15_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR15_EPDIR_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPDIR register field value. */ +#define ALT_USB_HOST_HCCHAR15_EPDIR_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */ +#define ALT_USB_HOST_HCCHAR15_EPDIR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR15_EPDIR field value from a register. */ +#define ALT_USB_HOST_HCCHAR15_EPDIR_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_HOST_HCCHAR15_EPDIR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR15_EPDIR_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Low-Speed Device - lspddev + * + * This field is set by the application to indicate that this channel is + * communicating to a low-speed device. The application must program this bit when + * a low speed device is connected to the host through an FS HUB. The HS OTG Host + * core uses this field to drive the XCVR_SELECT signal to 2'b11 while + * communicating to the LS Device through the FS hub. In a peer to peer setup, the + * HS OTG Host core ignores this bit even if it is set by the application software + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------------- + * ALT_USB_HOST_HCCHAR15_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device + * ALT_USB_HOST_HCCHAR15_LSPDDEV_E_END | 0x1 | Communicating with low speed device + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_LSPDDEV + * + * Not Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR15_LSPDDEV_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_LSPDDEV + * + * Communicating with low speed device + */ +#define ALT_USB_HOST_HCCHAR15_LSPDDEV_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR15_LSPDDEV_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR15_LSPDDEV_MSB 17 +/* The width in bits of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR15_LSPDDEV_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR15_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR15_LSPDDEV_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR15_LSPDDEV register field value. */ +#define ALT_USB_HOST_HCCHAR15_LSPDDEV_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */ +#define ALT_USB_HOST_HCCHAR15_LSPDDEV_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR15_LSPDDEV field value from a register. */ +#define ALT_USB_HOST_HCCHAR15_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_HOST_HCCHAR15_LSPDDEV register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR15_LSPDDEV_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Indicates the transfer type selected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------ + * ALT_USB_HOST_HCCHAR15_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_HOST_HCCHAR15_EPTYPE_E_ISOC | 0x1 | Isochronous + * ALT_USB_HOST_HCCHAR15_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_HOST_HCCHAR15_EPTYPE_E_INTERR | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE + * + * Control + */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE + * + * Isochronous + */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_ISOC 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE + * + * Bulk + */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE + * + * Interrupt + */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_INTERR 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR15_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPTYPE register field value. */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR15_EPTYPE field value from a register. */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_HOST_HCCHAR15_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Multi Count - ec + * + * When the Split Enable bit of the Host Channel-n Split Control register + * (HCSPLTn.SpltEna) is reset (0), this field indicates to the host the number of + * transactions that must be executed per microframe for this periodic endpoint. + * for non periodic transfers, this field is used only in DMA mode, and specifies + * the number packets to be fetched for this channel before the internal DMA engine + * changes arbitration. When HCSPLTn.SpltEna is Set (1), this field indicates the + * number of immediate retries to be performed for a periodic split transactions on + * transaction errors. This field must be set to at least 1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------------------------- + * ALT_USB_HOST_HCCHAR15_EC_E_RSVD | 0x0 | Reserved This field yields undefined result + * ALT_USB_HOST_HCCHAR15_EC_E_TRANSONE | 0x1 | 1 transaction + * ALT_USB_HOST_HCCHAR15_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint + * : | | per microframe + * ALT_USB_HOST_HCCHAR15_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint + * : | | per microframe + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC + * + * Reserved This field yields undefined result + */ +#define ALT_USB_HOST_HCCHAR15_EC_E_RSVD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC + * + * 1 transaction + */ +#define ALT_USB_HOST_HCCHAR15_EC_E_TRANSONE 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC + * + * 2 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR15_EC_E_TRANSTWO 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC + * + * 3 transactions to be issued for this endpoint per microframe + */ +#define ALT_USB_HOST_HCCHAR15_EC_E_TRANSTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EC register field. */ +#define ALT_USB_HOST_HCCHAR15_EC_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EC register field. */ +#define ALT_USB_HOST_HCCHAR15_EC_MSB 21 +/* The width in bits of the ALT_USB_HOST_HCCHAR15_EC register field. */ +#define ALT_USB_HOST_HCCHAR15_EC_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCCHAR15_EC register field value. */ +#define ALT_USB_HOST_HCCHAR15_EC_SET_MSK 0x00300000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EC register field value. */ +#define ALT_USB_HOST_HCCHAR15_EC_CLR_MSK 0xffcfffff +/* The reset value of the ALT_USB_HOST_HCCHAR15_EC register field. */ +#define ALT_USB_HOST_HCCHAR15_EC_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR15_EC field value from a register. */ +#define ALT_USB_HOST_HCCHAR15_EC_GET(value) (((value) & 0x00300000) >> 20) +/* Produces a ALT_USB_HOST_HCCHAR15_EC register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR15_EC_SET(value) (((value) << 20) & 0x00300000) + +/* + * Field : Device Address - devaddr + * + * This field selects the specific device serving as the data source or sink. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR15_DEVADDR_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR15_DEVADDR_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR15_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCCHAR15_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR15_DEVADDR_SET_MSK 0x1fc00000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR15_DEVADDR register field value. */ +#define ALT_USB_HOST_HCCHAR15_DEVADDR_CLR_MSK 0xe03fffff +/* The reset value of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */ +#define ALT_USB_HOST_HCCHAR15_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR15_DEVADDR field value from a register. */ +#define ALT_USB_HOST_HCCHAR15_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22) +/* Produces a ALT_USB_HOST_HCCHAR15_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR15_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000) + +/* + * Field : Channel Disable - chdis + * + * The application sets this bit to stop transmitting/receiving data on a channel, + * even before the transfer for that channel is complete. The application must wait + * for the Channel Disabled interrupt before treating the channel as disabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_HOST_HCCHAR15_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal + * ALT_USB_HOST_HCCHAR15_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHDIS + * + * Transmit/Recieve normal + */ +#define ALT_USB_HOST_HCCHAR15_CHDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHDIS + * + * Stop transmitting/receiving + */ +#define ALT_USB_HOST_HCCHAR15_CHDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR15_CHDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR15_CHDIS_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR15_CHDIS_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR15_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR15_CHDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR15_CHDIS register field value. */ +#define ALT_USB_HOST_HCCHAR15_CHDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */ +#define ALT_USB_HOST_HCCHAR15_CHDIS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR15_CHDIS field value from a register. */ +#define ALT_USB_HOST_HCCHAR15_CHDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_HOST_HCCHAR15_CHDIS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR15_CHDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Channel Enable - chena + * + * When Scatter/Gather mode is disabled This field is set by the application and + * cleared by the OTG host. + * + * 0: Channel disabled + * + * 1: Channel enabled + * + * When Scatter/Gather mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_HOST_HCCHAR15_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not + * : | | yet ready + * ALT_USB_HOST_HCCHAR15_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and + * : | | data buffer with data is setup and this + * : | | channel can access the descriptor + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHENA + * + * Indicates that the descriptor structure is not yet ready + */ +#define ALT_USB_HOST_HCCHAR15_CHENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHENA + * + * Indicates that the descriptor structure and data buffer with data is + * setup and this channel can access the descriptor + */ +#define ALT_USB_HOST_HCCHAR15_CHENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR15_CHENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR15_CHENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCCHAR15_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR15_CHENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCCHAR15_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR15_CHENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCCHAR15_CHENA register field value. */ +#define ALT_USB_HOST_HCCHAR15_CHENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCCHAR15_CHENA register field. */ +#define ALT_USB_HOST_HCCHAR15_CHENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCCHAR15_CHENA field value from a register. */ +#define ALT_USB_HOST_HCCHAR15_CHENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCCHAR15_CHENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCCHAR15_CHENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCCHAR15. + */ +struct ALT_USB_HOST_HCCHAR15_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t epnum : 4; /* Endpoint Number */ + uint32_t epdir : 1; /* Endpoint Direction */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t lspddev : 1; /* Low-Speed Device */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t ec : 2; /* Multi Count */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t chdis : 1; /* Channel Disable */ + const uint32_t chena : 1; /* Channel Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCCHAR15. */ +typedef volatile struct ALT_USB_HOST_HCCHAR15_s ALT_USB_HOST_HCCHAR15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCCHAR15 register from the beginning of the component. */ +#define ALT_USB_HOST_HCCHAR15_OFST 0x2e0 +/* The address of the ALT_USB_HOST_HCCHAR15 register. */ +#define ALT_USB_HOST_HCCHAR15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR15_OFST)) + +/* + * Register : Host Channel 15 Split Control Register - hcsplt15 + * + * Channel_number 15. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------- + * [6:0] | RW | 0x0 | Port Address + * [13:7] | RW | 0x0 | Hub Address + * [15:14] | RW | 0x0 | Transaction Position + * [16] | RW | 0x0 | Do Complete Split + * [30:17] | ??? | 0x0 | *UNDEFINED* + * [31] | RW | 0x0 | Split Enable + * + */ +/* + * Field : Port Address - prtaddr + * + * This field is the port number of the recipient transactiontranslator. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT15_PRTADDR_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT15_PRTADDR_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT15_PRTADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT15_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT15_PRTADDR_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_HOST_HCSPLT15_PRTADDR register field value. */ +#define ALT_USB_HOST_HCSPLT15_PRTADDR_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */ +#define ALT_USB_HOST_HCSPLT15_PRTADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT15_PRTADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT15_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_HOST_HCSPLT15_PRTADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT15_PRTADDR_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Hub Address - hubaddr + * + * This field holds the device address of the transaction translator's hub. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT15_HUBADDR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT15_HUBADDR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT15_HUBADDR_WIDTH 7 +/* The mask used to set the ALT_USB_HOST_HCSPLT15_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT15_HUBADDR_SET_MSK 0x00003f80 +/* The mask used to clear the ALT_USB_HOST_HCSPLT15_HUBADDR register field value. */ +#define ALT_USB_HOST_HCSPLT15_HUBADDR_CLR_MSK 0xffffc07f +/* The reset value of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */ +#define ALT_USB_HOST_HCSPLT15_HUBADDR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT15_HUBADDR field value from a register. */ +#define ALT_USB_HOST_HCSPLT15_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7) +/* Produces a ALT_USB_HOST_HCSPLT15_HUBADDR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT15_HUBADDR_SET(value) (((value) << 7) & 0x00003f80) + +/* + * Field : Transaction Position - xactpos + * + * This field is used to determine whether to send all, first, middle, or last + * payloads with each OUT transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------------------------ + * ALT_USB_HOST_HCSPLT15_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT15_XACTPOS_E_END | 0x1 | End. This is the last payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT15_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this + * : | | transaction (which is larger than 188 bytes) + * ALT_USB_HOST_HCSPLT15_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this + * : | | transaction (which is less than or equal to 188 + * : | | bytes) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS + * + * Mid. This is the middle payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_MIDDLE 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS + * + * End. This is the last payload of this transaction (which is larger than 188 + * bytes) + */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_END 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS + * + * Begin. This is the first data payload of this transaction (which is larger than + * 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_BEGIN 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS + * + * All. This is the entire data payload is of this transaction (which is less than + * or equal to 188 bytes) + */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_ALL 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_MSB 15 +/* The width in bits of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCSPLT15_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_SET_MSK 0x0000c000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT15_XACTPOS register field value. */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_CLR_MSK 0xffff3fff +/* The reset value of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT15_XACTPOS field value from a register. */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14) +/* Produces a ALT_USB_HOST_HCSPLT15_XACTPOS register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT15_XACTPOS_SET(value) (((value) << 14) & 0x0000c000) + +/* + * Field : Do Complete Split - compsplt + * + * The application sets this field to request the OTG host to perform a complete + * split transaction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCSPLT15_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction + * ALT_USB_HOST_HCSPLT15_COMPSPLT_E_SPLIT | 0x1 | Split transaction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT15_COMPSPLT + * + * No split transaction + */ +#define ALT_USB_HOST_HCSPLT15_COMPSPLT_E_NOSPLIT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT15_COMPSPLT + * + * Split transaction + */ +#define ALT_USB_HOST_HCSPLT15_COMPSPLT_E_SPLIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT15_COMPSPLT_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT15_COMPSPLT_MSB 16 +/* The width in bits of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT15_COMPSPLT_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT15_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT15_COMPSPLT_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT15_COMPSPLT register field value. */ +#define ALT_USB_HOST_HCSPLT15_COMPSPLT_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */ +#define ALT_USB_HOST_HCSPLT15_COMPSPLT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT15_COMPSPLT field value from a register. */ +#define ALT_USB_HOST_HCSPLT15_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_HOST_HCSPLT15_COMPSPLT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT15_COMPSPLT_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Split Enable - spltena + * + * The application sets this field to indicate that this channel is enabled to + * perform split transactions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_HOST_HCSPLT15_SPLTENA_E_DISD | 0x0 | Split not enabled + * ALT_USB_HOST_HCSPLT15_SPLTENA_E_END | 0x1 | Split enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT15_SPLTENA + * + * Split not enabled + */ +#define ALT_USB_HOST_HCSPLT15_SPLTENA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCSPLT15_SPLTENA + * + * Split enabled + */ +#define ALT_USB_HOST_HCSPLT15_SPLTENA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT15_SPLTENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT15_SPLTENA_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT15_SPLTENA_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCSPLT15_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT15_SPLTENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCSPLT15_SPLTENA register field value. */ +#define ALT_USB_HOST_HCSPLT15_SPLTENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */ +#define ALT_USB_HOST_HCSPLT15_SPLTENA_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCSPLT15_SPLTENA field value from a register. */ +#define ALT_USB_HOST_HCSPLT15_SPLTENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCSPLT15_SPLTENA register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCSPLT15_SPLTENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCSPLT15. + */ +struct ALT_USB_HOST_HCSPLT15_s +{ + uint32_t prtaddr : 7; /* Port Address */ + uint32_t hubaddr : 7; /* Hub Address */ + uint32_t xactpos : 2; /* Transaction Position */ + uint32_t compsplt : 1; /* Do Complete Split */ + uint32_t : 14; /* *UNDEFINED* */ + uint32_t spltena : 1; /* Split Enable */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCSPLT15. */ +typedef volatile struct ALT_USB_HOST_HCSPLT15_s ALT_USB_HOST_HCSPLT15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCSPLT15 register from the beginning of the component. */ +#define ALT_USB_HOST_HCSPLT15_OFST 0x2e4 +/* The address of the ALT_USB_HOST_HCSPLT15 register. */ +#define ALT_USB_HOST_HCSPLT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT15_OFST)) + +/* + * Register : Host Channel 15 Interrupt Register - hcint15 + * + * This register indicates the status of a channel with respect to USB- and AHB- + * related events. The application must read this register when the Host Channels + * Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the + * application can read this register, it must first read the Host All Channels + * Interrupt (HAINT) register to get the exact channel number for the Host + * Channel-n Interrupt register. The application must clear the appropriate bit in + * this register to clear the corresponding bits in the HAINT and GINTSTS + * registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------------- + * [0] | R | 0x0 | Transfer Completed + * [1] | R | 0x0 | Channel Halted + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | STALL Response Received Interrupt + * [4] | R | 0x0 | NAK Response Received Interrupt + * [5] | R | 0x0 | ACK Response Received Transmitted Interrupt + * [6] | R | 0x0 | NYET Response Received Interrupt + * [7] | R | 0x0 | Transaction Error + * [8] | R | 0x0 | Babble Error + * [9] | R | 0x0 | Frame Overrun + * [10] | R | 0x0 | Data Toggle Error + * [11] | R | 0x0 | BNA Interrupt + * [12] | R | 0x0 | Excessive Transaction Error + * [13] | R | 0x0 | Descriptor rollover interrupt + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed - xfercompl + * + * Transfer completed normally without any errors. This bit can be set only by the + * core and the application should write 1 to clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT15_XFERCOMPL_E_INACT | 0x0 | No transfer + * ALT_USB_HOST_HCINT15_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_XFERCOMPL + * + * No transfer + */ +#define ALT_USB_HOST_HCINT15_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_XFERCOMPL + * + * Transfer completed normally without any errors + */ +#define ALT_USB_HOST_HCINT15_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT15_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT15_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT15_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT15_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINT15_XFERCOMPL register field value. */ +#define ALT_USB_HOST_HCINT15_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */ +#define ALT_USB_HOST_HCINT15_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_XFERCOMPL field value from a register. */ +#define ALT_USB_HOST_HCINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINT15_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted - chhltd + * + * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally + * either because of any USB transaction error or in response to disable request by + * the application or because of a completed transfer. In Scatter/gather DMA mode, + * this indicates that transfer completed due to any of the following + * + * . EOL being set in descriptor + * + * . AHB error + * + * . Excessive transaction errors + * + * . Babble + * + * . Stall + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT15_CHHLTD_E_INACT | 0x0 | Channel not halted + * ALT_USB_HOST_HCINT15_CHHLTD_E_ACT | 0x1 | Channel Halted + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_CHHLTD + * + * Channel not halted + */ +#define ALT_USB_HOST_HCINT15_CHHLTD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_CHHLTD + * + * Channel Halted + */ +#define ALT_USB_HOST_HCINT15_CHHLTD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT15_CHHLTD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT15_CHHLTD_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINT15_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT15_CHHLTD_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT15_CHHLTD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINT15_CHHLTD register field value. */ +#define ALT_USB_HOST_HCINT15_CHHLTD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINT15_CHHLTD register field. */ +#define ALT_USB_HOST_HCINT15_CHHLTD_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_CHHLTD field value from a register. */ +#define ALT_USB_HOST_HCINT15_CHHLTD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINT15_CHHLTD register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_CHHLTD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * This is generated only in Internal DMA mode when there is an AHB error during + * AHB read/write. The application can read the corresponding channel's DMA address + * register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------------------- + * ALT_USB_HOST_HCINT15_AHBERR_E_INACT | 0x0 | No AHB error + * ALT_USB_HOST_HCINT15_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_AHBERR + * + * No AHB error + */ +#define ALT_USB_HOST_HCINT15_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_AHBERR + * + * AHB error during AHB read/write + */ +#define ALT_USB_HOST_HCINT15_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_AHBERR register field. */ +#define ALT_USB_HOST_HCINT15_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_AHBERR register field. */ +#define ALT_USB_HOST_HCINT15_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINT15_AHBERR register field. */ +#define ALT_USB_HOST_HCINT15_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT15_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINT15_AHBERR register field value. */ +#define ALT_USB_HOST_HCINT15_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINT15_AHBERR register field. */ +#define ALT_USB_HOST_HCINT15_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_AHBERR field value from a register. */ +#define ALT_USB_HOST_HCINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINT15_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : STALL Response Received Interrupt - stall + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------- + * ALT_USB_HOST_HCINT15_STALL_E_INACT | 0x0 | No Stall Interrupt + * ALT_USB_HOST_HCINT15_STALL_E_ACT | 0x1 | Stall Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_STALL + * + * No Stall Interrupt + */ +#define ALT_USB_HOST_HCINT15_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_STALL + * + * Stall Interrupt + */ +#define ALT_USB_HOST_HCINT15_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_STALL register field. */ +#define ALT_USB_HOST_HCINT15_STALL_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_STALL register field. */ +#define ALT_USB_HOST_HCINT15_STALL_MSB 3 +/* The width in bits of the ALT_USB_HOST_HCINT15_STALL register field. */ +#define ALT_USB_HOST_HCINT15_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_STALL register field value. */ +#define ALT_USB_HOST_HCINT15_STALL_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_HOST_HCINT15_STALL register field value. */ +#define ALT_USB_HOST_HCINT15_STALL_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_HOST_HCINT15_STALL register field. */ +#define ALT_USB_HOST_HCINT15_STALL_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_STALL field value from a register. */ +#define ALT_USB_HOST_HCINT15_STALL_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_HOST_HCINT15_STALL register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_STALL_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : NAK Response Received Interrupt - nak + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------- + * ALT_USB_HOST_HCINT15_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt + * ALT_USB_HOST_HCINT15_NAK_E_ACT | 0x1 | NAK Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_NAK + * + * No NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT15_NAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_NAK + * + * NAK Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT15_NAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_NAK register field. */ +#define ALT_USB_HOST_HCINT15_NAK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_NAK register field. */ +#define ALT_USB_HOST_HCINT15_NAK_MSB 4 +/* The width in bits of the ALT_USB_HOST_HCINT15_NAK register field. */ +#define ALT_USB_HOST_HCINT15_NAK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_NAK register field value. */ +#define ALT_USB_HOST_HCINT15_NAK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_HOST_HCINT15_NAK register field value. */ +#define ALT_USB_HOST_HCINT15_NAK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_HOST_HCINT15_NAK register field. */ +#define ALT_USB_HOST_HCINT15_NAK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_NAK field value from a register. */ +#define ALT_USB_HOST_HCINT15_NAK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_HOST_HCINT15_NAK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_NAK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : ACK Response Received Transmitted Interrupt - ack + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------------------- + * ALT_USB_HOST_HCINT15_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt + * ALT_USB_HOST_HCINT15_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_ACK + * + * No ACK Response Received Transmitted Interrupt + */ +#define ALT_USB_HOST_HCINT15_ACK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_ACK + * + * ACK Response Received Transmitted Interrup + */ +#define ALT_USB_HOST_HCINT15_ACK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_ACK register field. */ +#define ALT_USB_HOST_HCINT15_ACK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_ACK register field. */ +#define ALT_USB_HOST_HCINT15_ACK_MSB 5 +/* The width in bits of the ALT_USB_HOST_HCINT15_ACK register field. */ +#define ALT_USB_HOST_HCINT15_ACK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_ACK register field value. */ +#define ALT_USB_HOST_HCINT15_ACK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_HOST_HCINT15_ACK register field value. */ +#define ALT_USB_HOST_HCINT15_ACK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_HOST_HCINT15_ACK register field. */ +#define ALT_USB_HOST_HCINT15_ACK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_ACK field value from a register. */ +#define ALT_USB_HOST_HCINT15_ACK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_HOST_HCINT15_ACK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_ACK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : NYET Response Received Interrupt - nyet + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core.This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCINT15_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt + * ALT_USB_HOST_HCINT15_NYET_E_ACT | 0x1 | NYET Response Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_NYET + * + * No NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT15_NYET_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_NYET + * + * NYET Response Received Interrupt + */ +#define ALT_USB_HOST_HCINT15_NYET_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_NYET register field. */ +#define ALT_USB_HOST_HCINT15_NYET_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_NYET register field. */ +#define ALT_USB_HOST_HCINT15_NYET_MSB 6 +/* The width in bits of the ALT_USB_HOST_HCINT15_NYET register field. */ +#define ALT_USB_HOST_HCINT15_NYET_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_NYET register field value. */ +#define ALT_USB_HOST_HCINT15_NYET_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_HOST_HCINT15_NYET register field value. */ +#define ALT_USB_HOST_HCINT15_NYET_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_HOST_HCINT15_NYET register field. */ +#define ALT_USB_HOST_HCINT15_NYET_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_NYET field value from a register. */ +#define ALT_USB_HOST_HCINT15_NYET_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_HOST_HCINT15_NYET register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_NYET_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transaction Error - xacterr + * + * Indicates one of the following errors occurred on the USB.-CRC check failure + * + * * Timeout + * + * * Bit stuff error + * + * * False EOP + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT15_XACTERR_E_INACT | 0x0 | No Transaction Error + * ALT_USB_HOST_HCINT15_XACTERR_E_ACT | 0x1 | Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_XACTERR + * + * No Transaction Error + */ +#define ALT_USB_HOST_HCINT15_XACTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_XACTERR + * + * Transaction Error + */ +#define ALT_USB_HOST_HCINT15_XACTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XACTERR register field. */ +#define ALT_USB_HOST_HCINT15_XACTERR_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XACTERR register field. */ +#define ALT_USB_HOST_HCINT15_XACTERR_MSB 7 +/* The width in bits of the ALT_USB_HOST_HCINT15_XACTERR register field. */ +#define ALT_USB_HOST_HCINT15_XACTERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT15_XACTERR_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_HOST_HCINT15_XACTERR register field value. */ +#define ALT_USB_HOST_HCINT15_XACTERR_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_HOST_HCINT15_XACTERR register field. */ +#define ALT_USB_HOST_HCINT15_XACTERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_XACTERR field value from a register. */ +#define ALT_USB_HOST_HCINT15_XACTERR_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_HOST_HCINT15_XACTERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_XACTERR_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Babble Error - bblerr + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core..This bit can be set only by the core and the application should write 1 to + * clear it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------- + * ALT_USB_HOST_HCINT15_BBLERR_E_INACT | 0x0 | No Babble Error + * ALT_USB_HOST_HCINT15_BBLERR_E_ACT | 0x1 | Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_BBLERR + * + * No Babble Error + */ +#define ALT_USB_HOST_HCINT15_BBLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_BBLERR + * + * Babble Error + */ +#define ALT_USB_HOST_HCINT15_BBLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_BBLERR register field. */ +#define ALT_USB_HOST_HCINT15_BBLERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_BBLERR register field. */ +#define ALT_USB_HOST_HCINT15_BBLERR_MSB 8 +/* The width in bits of the ALT_USB_HOST_HCINT15_BBLERR register field. */ +#define ALT_USB_HOST_HCINT15_BBLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT15_BBLERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_HOST_HCINT15_BBLERR register field value. */ +#define ALT_USB_HOST_HCINT15_BBLERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_HOST_HCINT15_BBLERR register field. */ +#define ALT_USB_HOST_HCINT15_BBLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_BBLERR field value from a register. */ +#define ALT_USB_HOST_HCINT15_BBLERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_HOST_HCINT15_BBLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_BBLERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Frame Overrun - frmovrun + * + * In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. + * This bit can be set only by the core and the application should write 1 to clear + * it. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT15_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun + * ALT_USB_HOST_HCINT15_FRMOVRUN_E_ACT | 0x1 | Frame Overrun + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_FRMOVRUN + * + * No Frame Overrun + */ +#define ALT_USB_HOST_HCINT15_FRMOVRUN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_FRMOVRUN + * + * Frame Overrun + */ +#define ALT_USB_HOST_HCINT15_FRMOVRUN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT15_FRMOVRUN_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT15_FRMOVRUN_MSB 9 +/* The width in bits of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT15_FRMOVRUN_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT15_FRMOVRUN_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_HOST_HCINT15_FRMOVRUN register field value. */ +#define ALT_USB_HOST_HCINT15_FRMOVRUN_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */ +#define ALT_USB_HOST_HCINT15_FRMOVRUN_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_FRMOVRUN field value from a register. */ +#define ALT_USB_HOST_HCINT15_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_HOST_HCINT15_FRMOVRUN register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Data Toggle Error - datatglerr + * + * This bit can be set only by the core and the application should write 1 to clear + * it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the + * core. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------- + * ALT_USB_HOST_HCINT15_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error + * ALT_USB_HOST_HCINT15_DATATGLERR_E_ACT | 0x1 | Data Toggle Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_DATATGLERR + * + * No Data Toggle Error + */ +#define ALT_USB_HOST_HCINT15_DATATGLERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_DATATGLERR + * + * Data Toggle Error + */ +#define ALT_USB_HOST_HCINT15_DATATGLERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT15_DATATGLERR_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT15_DATATGLERR_MSB 10 +/* The width in bits of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT15_DATATGLERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT15_DATATGLERR_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_HOST_HCINT15_DATATGLERR register field value. */ +#define ALT_USB_HOST_HCINT15_DATATGLERR_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */ +#define ALT_USB_HOST_HCINT15_DATATGLERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_DATATGLERR field value from a register. */ +#define ALT_USB_HOST_HCINT15_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_HOST_HCINT15_DATATGLERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_DATATGLERR_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process. BNA will not be generated for Isochronous channels. for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCINT15_BNAINTR_E_INACT | 0x0 | No BNA Interrupt + * ALT_USB_HOST_HCINT15_BNAINTR_E_ACT | 0x1 | BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_BNAINTR + * + * No BNA Interrupt + */ +#define ALT_USB_HOST_HCINT15_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_BNAINTR + * + * BNA Interrupt + */ +#define ALT_USB_HOST_HCINT15_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT15_BNAINTR_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT15_BNAINTR_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINT15_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT15_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT15_BNAINTR_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINT15_BNAINTR register field value. */ +#define ALT_USB_HOST_HCINT15_BNAINTR_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINT15_BNAINTR register field. */ +#define ALT_USB_HOST_HCINT15_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_BNAINTR field value from a register. */ +#define ALT_USB_HOST_HCINT15_BNAINTR_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINT15_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_BNAINTR_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Excessive Transaction Error - xcs_xact_err + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets + * this bit when 3 consecutive transaction errors occurred on the USB bus. + * XCS_XACT_ERR will not be generated for Isochronous channels.for non + * Scatter/Gather DMA mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:------------------------------- + * ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error + * ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_XCS_XACT_ERR + * + * No Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_XCS_XACT_ERR + * + * Excessive Transaction Error + */ +#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_ACVTIVE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_MSB 12 +/* The width in bits of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value. */ +#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */ +#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_XCS_XACT_ERR field value from a register. */ +#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : Descriptor rollover interrupt - desc_lst_rollintr + * + * Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when + * Scatter/Gather DMA mode is enabled. The core sets this bit when the + * corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA + * mode, this bit is reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:--------------------------------- + * ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt + * ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR + * + * No Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR + * + * Descriptor rollover interrupt + */ +#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value. */ +#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */ +#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR field value from a register. */ +#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINT15. + */ +struct ALT_USB_HOST_HCINT15_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed */ + const uint32_t chhltd : 1; /* Channel Halted */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t stall : 1; /* STALL Response Received Interrupt */ + const uint32_t nak : 1; /* NAK Response Received Interrupt */ + const uint32_t ack : 1; /* ACK Response Received Transmitted Interrupt */ + const uint32_t nyet : 1; /* NYET Response Received Interrupt */ + const uint32_t xacterr : 1; /* Transaction Error */ + const uint32_t bblerr : 1; /* Babble Error */ + const uint32_t frmovrun : 1; /* Frame Overrun */ + const uint32_t datatglerr : 1; /* Data Toggle Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + const uint32_t xcs_xact_err : 1; /* Excessive Transaction Error */ + const uint32_t desc_lst_rollintr : 1; /* Descriptor rollover interrupt */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINT15. */ +typedef volatile struct ALT_USB_HOST_HCINT15_s ALT_USB_HOST_HCINT15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINT15 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINT15_OFST 0x2e8 +/* The address of the ALT_USB_HOST_HCINT15 register. */ +#define ALT_USB_HOST_HCINT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT15_OFST)) + +/* + * Register : Host Channel 15 Interrupt Mask Register - hcintmsk15 + * + * This register reflects the mask for each channel status described in the + * previous section. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------- + * [0] | RW | 0x0 | Transfer Completed Mask + * [1] | RW | 0x0 | Channel Halted Mask + * [2] | RW | 0x0 | AHB Error Mask + * [10:3] | ??? | 0x0 | *UNDEFINED* + * [11] | RW | 0x0 | BNA Interrupt mask + * [12] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | Framelist Rollover Interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Mask - xfercomplmsk + * + * Transfer complete. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Channel Halted Mask - chhltdmsk + * + * Channel Halted. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_CHHLTDMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_CHHLTDMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_MSB 1 +/* The width in bits of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * In scatter/gather DMA mode for host, interrupts will not be generated due to + * the corresponding bits set in HCINTn. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_AHBERRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_AHBERRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK15_AHBERRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : BNA Interrupt mask - bnaintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_BNAINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_BNAINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_MSB 11 +/* The width in bits of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Framelist Rollover Interrupt Mask - frm_lst_rollintrmsk + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------------|:------|:------------ + * ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask + * ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK + * + * Mask + */ +#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK + * + * No mask + */ +#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_MSB 13 +/* The width in bits of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value. */ +#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */ +#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK field value from a register. */ +#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCINTMSK15. + */ +struct ALT_USB_HOST_HCINTMSK15_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Mask */ + uint32_t chhltdmsk : 1; /* Channel Halted Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t : 8; /* *UNDEFINED* */ + uint32_t bnaintrmsk : 1; /* BNA Interrupt mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t frm_lst_rollintrmsk : 1; /* Framelist Rollover Interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCINTMSK15. */ +typedef volatile struct ALT_USB_HOST_HCINTMSK15_s ALT_USB_HOST_HCINTMSK15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCINTMSK15 register from the beginning of the component. */ +#define ALT_USB_HOST_HCINTMSK15_OFST 0x2ec +/* The address of the ALT_USB_HOST_HCINTMSK15 register. */ +#define ALT_USB_HOST_HCINTMSK15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK15_OFST)) + +/* + * Register : Host Channel 15 Transfer Size Register - hctsiz15 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | PID + * [31] | RW | 0x0 | Do Ping + * + */ +/* + * Field : Transfer Size - xfersize + * + * for an OUT, this field is the number of data bytes the host sends during the + * transfer. for an IN, this field is the buffer size that the application has + * Reserved for the transfer. The application is expected to program this field as + * an integer multiple of the maximum packet size for IN transactions (periodic and + * non-periodic).The width of this counter is specified as 19 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value. */ +#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */ +#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ15_XFERSIZE field value from a register. */ +#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * This field is programmed by the application with the expected number of packets + * to be transmitted (OUT) or received (IN). The host decrements this count on + * every successful transmission or reception of an OUT/IN packet. Once this count + * reaches zero, the application is interrupted to indicate normal completion. The + * width of this counter is specified as 10 bits. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ15_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ15_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ15_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_HOST_HCTSIZ15_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ15_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_PKTCNT register field value. */ +#define ALT_USB_HOST_HCTSIZ15_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */ +#define ALT_USB_HOST_HCTSIZ15_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ15_PKTCNT field value from a register. */ +#define ALT_USB_HOST_HCTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_HOST_HCTSIZ15_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : PID - pid + * + * The application programs this field with the type of PID to use forthe initial + * transaction. The host maintains this field for the rest of the transfer. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------------------------ + * ALT_USB_HOST_HCTSIZ15_PID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_HOST_HCTSIZ15_PID_E_DATA2 | 0x1 | DATA2 + * ALT_USB_HOST_HCTSIZ15_PID_E_DATA1 | 0x2 | DATA1 + * ALT_USB_HOST_HCTSIZ15_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID + * + * DATA0 + */ +#define ALT_USB_HOST_HCTSIZ15_PID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID + * + * DATA2 + */ +#define ALT_USB_HOST_HCTSIZ15_PID_E_DATA2 0x1 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID + * + * DATA1 + */ +#define ALT_USB_HOST_HCTSIZ15_PID_E_DATA1 0x2 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID + * + * MDATA (non-control)/SETUP (control) + */ +#define ALT_USB_HOST_HCTSIZ15_PID_E_MDATA 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_PID register field. */ +#define ALT_USB_HOST_HCTSIZ15_PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_PID register field. */ +#define ALT_USB_HOST_HCTSIZ15_PID_MSB 30 +/* The width in bits of the ALT_USB_HOST_HCTSIZ15_PID register field. */ +#define ALT_USB_HOST_HCTSIZ15_PID_WIDTH 2 +/* The mask used to set the ALT_USB_HOST_HCTSIZ15_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ15_PID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_PID register field value. */ +#define ALT_USB_HOST_HCTSIZ15_PID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ15_PID register field. */ +#define ALT_USB_HOST_HCTSIZ15_PID_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ15_PID field value from a register. */ +#define ALT_USB_HOST_HCTSIZ15_PID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_HOST_HCTSIZ15_PID register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ15_PID_SET(value) (((value) << 29) & 0x60000000) + +/* + * Field : Do Ping - dopng + * + * This bit is used only for OUT transfers.Setting this field to 1 directs the host + * to do PING protocol. Do not Set this bit for IN transfers. If this bit is set + * for IN transfers it disables the channel. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------- + * ALT_USB_HOST_HCTSIZ15_DOPNG_E_NOPING | 0x0 | No ping protocol + * ALT_USB_HOST_HCTSIZ15_DOPNG_E_PING | 0x1 | Ping protocol + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_DOPNG + * + * No ping protocol + */ +#define ALT_USB_HOST_HCTSIZ15_DOPNG_E_NOPING 0x0 +/* + * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_DOPNG + * + * Ping protocol + */ +#define ALT_USB_HOST_HCTSIZ15_DOPNG_E_PING 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ15_DOPNG_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ15_DOPNG_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ15_DOPNG_WIDTH 1 +/* The mask used to set the ALT_USB_HOST_HCTSIZ15_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ15_DOPNG_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_DOPNG register field value. */ +#define ALT_USB_HOST_HCTSIZ15_DOPNG_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */ +#define ALT_USB_HOST_HCTSIZ15_DOPNG_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCTSIZ15_DOPNG field value from a register. */ +#define ALT_USB_HOST_HCTSIZ15_DOPNG_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_HOST_HCTSIZ15_DOPNG register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCTSIZ15_DOPNG_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCTSIZ15. + */ +struct ALT_USB_HOST_HCTSIZ15_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t pid : 2; /* PID */ + uint32_t dopng : 1; /* Do Ping */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCTSIZ15. */ +typedef volatile struct ALT_USB_HOST_HCTSIZ15_s ALT_USB_HOST_HCTSIZ15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCTSIZ15 register from the beginning of the component. */ +#define ALT_USB_HOST_HCTSIZ15_OFST 0x2f0 +/* The address of the ALT_USB_HOST_HCTSIZ15 register. */ +#define ALT_USB_HOST_HCTSIZ15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ15_OFST)) + +/* + * Register : Host Channel 15 DMA Address Register - hcdma15 + * + * This register is used by the OTG host in the internal DMA mode to maintain the + * current buffer pointer for IN/OUT transactions. The starting DMA address must be + * DWORD-aligned. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------ + * [31:0] | RW | 0x0 | DMA Address + * + */ +/* + * Field : DMA Address - hcdma15 + * + * Non-Isochronous: This field holds the start address of the 512 bytes page. The + * first descriptor in the list should be located in this address. The first + * descriptor may be or may not be ready. The core starts processing the list from + * the CTD value. This field holds the address of the 2*(nTD+1) bytes of locations + * in which the isochronous descriptors are present where N is based on nTD as per + * Table below + * + * [31:N] Base Address [N-1:3] Offset [2:0] 000 + * + * HS ISOC FS ISOC + * + * nTD N nTD N + * + * 7 6 1 4 + * + * 15 7 3 5 + * + * 31 8 7 6 + * + * 63 9 15 7 + * + * 127 10 31 8 + * + * 255 11 63 9 + * + * [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: + * This value is in terms of number of descriptors. The values can be from 0 to 63. + * 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current + * descriptor processed in the list. This field is updated both by application and + * the core. for example, if the application enables the channel after programming + * CTD=5, then the core will start processing the 6th descriptor. The address is + * obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. Isochronous: + * CTD for isochronous is based on the current frame/microframe value. Need to be + * set to zero by application. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */ +#define ALT_USB_HOST_HCDMA15_HCDMA15_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */ +#define ALT_USB_HOST_HCDMA15_HCDMA15_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */ +#define ALT_USB_HOST_HCDMA15_HCDMA15_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMA15_HCDMA15 register field value. */ +#define ALT_USB_HOST_HCDMA15_HCDMA15_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMA15_HCDMA15 register field value. */ +#define ALT_USB_HOST_HCDMA15_HCDMA15_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */ +#define ALT_USB_HOST_HCDMA15_HCDMA15_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMA15_HCDMA15 field value from a register. */ +#define ALT_USB_HOST_HCDMA15_HCDMA15_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMA15_HCDMA15 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMA15_HCDMA15_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMA15. + */ +struct ALT_USB_HOST_HCDMA15_s +{ + uint32_t hcdma15 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMA15. */ +typedef volatile struct ALT_USB_HOST_HCDMA15_s ALT_USB_HOST_HCDMA15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMA15 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMA15_OFST 0x2f4 +/* The address of the ALT_USB_HOST_HCDMA15 register. */ +#define ALT_USB_HOST_HCDMA15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA15_OFST)) + +/* + * Register : Host Channel 15 DMA Buffer Address Register - hcdmab15 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the + * data transfer for the corresponding end point is in progress. This + * register is present only in Scatter/Gather DMA mode. Otherwise this field + * is reserved. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:----------------------------------- + * [31:0] | RW | 0x0 | Host Channel 15 DMA Buffer Address + * + */ +/* + * Field : Host Channel 15 DMA Buffer Address - hcdmab15 + * + * These registers are present only in case of Scatter/Gather DMA. These + * registers are implemented in RAM instead of flop-based implementation. Holds + * the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. Otherwise this field is reserved. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */ +#define ALT_USB_HOST_HCDMAB15_HCDMAB15_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */ +#define ALT_USB_HOST_HCDMAB15_HCDMAB15_MSB 31 +/* The width in bits of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */ +#define ALT_USB_HOST_HCDMAB15_HCDMAB15_WIDTH 32 +/* The mask used to set the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value. */ +#define ALT_USB_HOST_HCDMAB15_HCDMAB15_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value. */ +#define ALT_USB_HOST_HCDMAB15_HCDMAB15_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */ +#define ALT_USB_HOST_HCDMAB15_HCDMAB15_RESET 0x0 +/* Extracts the ALT_USB_HOST_HCDMAB15_HCDMAB15 field value from a register. */ +#define ALT_USB_HOST_HCDMAB15_HCDMAB15_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value suitable for setting the register. */ +#define ALT_USB_HOST_HCDMAB15_HCDMAB15_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_HOST_HCDMAB15. + */ +struct ALT_USB_HOST_HCDMAB15_s +{ + uint32_t hcdmab15 : 32; /* Host Channel 15 DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_HOST_HCDMAB15. */ +typedef volatile struct ALT_USB_HOST_HCDMAB15_s ALT_USB_HOST_HCDMAB15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_HOST_HCDMAB15 register from the beginning of the component. */ +#define ALT_USB_HOST_HCDMAB15_OFST 0x2f8 +/* The address of the ALT_USB_HOST_HCDMAB15 register. */ +#define ALT_USB_HOST_HCDMAB15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB15_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_USB_HOST. + */ +struct ALT_USB_HOST_s +{ + volatile ALT_USB_HOST_HCFG_t hcfg; /* ALT_USB_HOST_HCFG */ + volatile ALT_USB_HOST_HFIR_t hfir; /* ALT_USB_HOST_HFIR */ + volatile ALT_USB_HOST_HFNUM_t hfnum; /* ALT_USB_HOST_HFNUM */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HPTXSTS_t hptxsts; /* ALT_USB_HOST_HPTXSTS */ + volatile ALT_USB_HOST_HAINT_t haint; /* ALT_USB_HOST_HAINT */ + volatile ALT_USB_HOST_HAINTMSK_t haintmsk; /* ALT_USB_HOST_HAINTMSK */ + volatile ALT_USB_HOST_HFLBADDR_t hflbaddr; /* ALT_USB_HOST_HFLBADDR */ + volatile uint32_t _pad_0x20_0x3f[8]; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HPRT_t hprt; /* ALT_USB_HOST_HPRT */ + volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR0_t hcchar0; /* ALT_USB_HOST_HCCHAR0 */ + volatile ALT_USB_HOST_HCSPLT0_t hcsplt0; /* ALT_USB_HOST_HCSPLT0 */ + volatile ALT_USB_HOST_HCINT0_t hcint0; /* ALT_USB_HOST_HCINT0 */ + volatile ALT_USB_HOST_HCINTMSK0_t hcintmsk0; /* ALT_USB_HOST_HCINTMSK0 */ + volatile ALT_USB_HOST_HCTSIZ0_t hctsiz0; /* ALT_USB_HOST_HCTSIZ0 */ + volatile ALT_USB_HOST_HCDMA0_t hcdma0; /* ALT_USB_HOST_HCDMA0 */ + volatile ALT_USB_HOST_HCDMAB0_t hcdmab0; /* ALT_USB_HOST_HCDMAB0 */ + volatile uint32_t _pad_0x11c_0x11f; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR1_t hcchar1; /* ALT_USB_HOST_HCCHAR1 */ + volatile ALT_USB_HOST_HCSPLT1_t hcsplt1; /* ALT_USB_HOST_HCSPLT1 */ + volatile ALT_USB_HOST_HCINT1_t hcint1; /* ALT_USB_HOST_HCINT1 */ + volatile ALT_USB_HOST_HCINTMSK1_t hcintmsk1; /* ALT_USB_HOST_HCINTMSK1 */ + volatile ALT_USB_HOST_HCTSIZ1_t hctsiz1; /* ALT_USB_HOST_HCTSIZ1 */ + volatile ALT_USB_HOST_HCDMA1_t hcdma1; /* ALT_USB_HOST_HCDMA1 */ + volatile ALT_USB_HOST_HCDMAB1_t hcdmab1; /* ALT_USB_HOST_HCDMAB1 */ + volatile uint32_t _pad_0x13c_0x13f; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR2_t hcchar2; /* ALT_USB_HOST_HCCHAR2 */ + volatile ALT_USB_HOST_HCSPLT2_t hcsplt2; /* ALT_USB_HOST_HCSPLT2 */ + volatile ALT_USB_HOST_HCINT2_t hcint2; /* ALT_USB_HOST_HCINT2 */ + volatile ALT_USB_HOST_HCINTMSK2_t hcintmsk2; /* ALT_USB_HOST_HCINTMSK2 */ + volatile ALT_USB_HOST_HCTSIZ2_t hctsiz2; /* ALT_USB_HOST_HCTSIZ2 */ + volatile ALT_USB_HOST_HCDMA2_t hcdma2; /* ALT_USB_HOST_HCDMA2 */ + volatile ALT_USB_HOST_HCDMAB2_t hcdmab2; /* ALT_USB_HOST_HCDMAB2 */ + volatile uint32_t _pad_0x15c_0x15f; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR3_t hcchar3; /* ALT_USB_HOST_HCCHAR3 */ + volatile ALT_USB_HOST_HCSPLT3_t hcsplt3; /* ALT_USB_HOST_HCSPLT3 */ + volatile ALT_USB_HOST_HCINT3_t hcint3; /* ALT_USB_HOST_HCINT3 */ + volatile ALT_USB_HOST_HCINTMSK3_t hcintmsk3; /* ALT_USB_HOST_HCINTMSK3 */ + volatile ALT_USB_HOST_HCTSIZ3_t hctsiz3; /* ALT_USB_HOST_HCTSIZ3 */ + volatile ALT_USB_HOST_HCDMA3_t hcdma3; /* ALT_USB_HOST_HCDMA3 */ + volatile ALT_USB_HOST_HCDMAB3_t hcdmab3; /* ALT_USB_HOST_HCDMAB3 */ + volatile uint32_t _pad_0x17c_0x17f; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR4_t hcchar4; /* ALT_USB_HOST_HCCHAR4 */ + volatile ALT_USB_HOST_HCSPLT4_t hcsplt4; /* ALT_USB_HOST_HCSPLT4 */ + volatile ALT_USB_HOST_HCINT4_t hcint4; /* ALT_USB_HOST_HCINT4 */ + volatile ALT_USB_HOST_HCINTMSK4_t hcintmsk4; /* ALT_USB_HOST_HCINTMSK4 */ + volatile ALT_USB_HOST_HCTSIZ4_t hctsiz4; /* ALT_USB_HOST_HCTSIZ4 */ + volatile ALT_USB_HOST_HCDMA4_t hcdma4; /* ALT_USB_HOST_HCDMA4 */ + volatile ALT_USB_HOST_HCDMAB4_t hcdmab4; /* ALT_USB_HOST_HCDMAB4 */ + volatile uint32_t _pad_0x19c_0x19f; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR5_t hcchar5; /* ALT_USB_HOST_HCCHAR5 */ + volatile ALT_USB_HOST_HCSPLT5_t hcsplt5; /* ALT_USB_HOST_HCSPLT5 */ + volatile ALT_USB_HOST_HCINT5_t hcint5; /* ALT_USB_HOST_HCINT5 */ + volatile ALT_USB_HOST_HCINTMSK5_t hcintmsk5; /* ALT_USB_HOST_HCINTMSK5 */ + volatile ALT_USB_HOST_HCTSIZ5_t hctsiz5; /* ALT_USB_HOST_HCTSIZ5 */ + volatile ALT_USB_HOST_HCDMA5_t hcdma5; /* ALT_USB_HOST_HCDMA5 */ + volatile ALT_USB_HOST_HCDMAB5_t hcdmab5; /* ALT_USB_HOST_HCDMAB5 */ + volatile uint32_t _pad_0x1bc_0x1bf; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR6_t hcchar6; /* ALT_USB_HOST_HCCHAR6 */ + volatile ALT_USB_HOST_HCSPLT6_t hcsplt6; /* ALT_USB_HOST_HCSPLT6 */ + volatile ALT_USB_HOST_HCINT6_t hcint6; /* ALT_USB_HOST_HCINT6 */ + volatile ALT_USB_HOST_HCINTMSK6_t hcintmsk6; /* ALT_USB_HOST_HCINTMSK6 */ + volatile ALT_USB_HOST_HCTSIZ6_t hctsiz6; /* ALT_USB_HOST_HCTSIZ6 */ + volatile ALT_USB_HOST_HCDMA6_t hcdma6; /* ALT_USB_HOST_HCDMA6 */ + volatile ALT_USB_HOST_HCDMAB6_t hcdmab6; /* ALT_USB_HOST_HCDMAB6 */ + volatile uint32_t _pad_0x1dc_0x1df; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR7_t hcchar7; /* ALT_USB_HOST_HCCHAR7 */ + volatile ALT_USB_HOST_HCSPLT7_t hcsplt7; /* ALT_USB_HOST_HCSPLT7 */ + volatile ALT_USB_HOST_HCINT7_t hcint7; /* ALT_USB_HOST_HCINT7 */ + volatile ALT_USB_HOST_HCINTMSK7_t hcintmsk7; /* ALT_USB_HOST_HCINTMSK7 */ + volatile ALT_USB_HOST_HCTSIZ7_t hctsiz7; /* ALT_USB_HOST_HCTSIZ7 */ + volatile ALT_USB_HOST_HCDMA7_t hcdma7; /* ALT_USB_HOST_HCDMA7 */ + volatile ALT_USB_HOST_HCDMAB7_t hcdmab7; /* ALT_USB_HOST_HCDMAB7 */ + volatile uint32_t _pad_0x1fc_0x1ff; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR8_t hcchar8; /* ALT_USB_HOST_HCCHAR8 */ + volatile ALT_USB_HOST_HCSPLT8_t hcsplt8; /* ALT_USB_HOST_HCSPLT8 */ + volatile ALT_USB_HOST_HCINT8_t hcint8; /* ALT_USB_HOST_HCINT8 */ + volatile ALT_USB_HOST_HCINTMSK8_t hcintmsk8; /* ALT_USB_HOST_HCINTMSK8 */ + volatile ALT_USB_HOST_HCTSIZ8_t hctsiz8; /* ALT_USB_HOST_HCTSIZ8 */ + volatile ALT_USB_HOST_HCDMA8_t hcdma8; /* ALT_USB_HOST_HCDMA8 */ + volatile ALT_USB_HOST_HCDMAB8_t hcdmab8; /* ALT_USB_HOST_HCDMAB8 */ + volatile uint32_t _pad_0x21c_0x21f; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR9_t hcchar9; /* ALT_USB_HOST_HCCHAR9 */ + volatile ALT_USB_HOST_HCSPLT9_t hcsplt9; /* ALT_USB_HOST_HCSPLT9 */ + volatile ALT_USB_HOST_HCINT9_t hcint9; /* ALT_USB_HOST_HCINT9 */ + volatile ALT_USB_HOST_HCINTMSK9_t hcintmsk9; /* ALT_USB_HOST_HCINTMSK9 */ + volatile ALT_USB_HOST_HCTSIZ9_t hctsiz9; /* ALT_USB_HOST_HCTSIZ9 */ + volatile ALT_USB_HOST_HCDMA9_t hcdma9; /* ALT_USB_HOST_HCDMA9 */ + volatile ALT_USB_HOST_HCDMAB9_t hcdmab9; /* ALT_USB_HOST_HCDMAB9 */ + volatile uint32_t _pad_0x23c_0x23f; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR10_t hcchar10; /* ALT_USB_HOST_HCCHAR10 */ + volatile ALT_USB_HOST_HCSPLT10_t hcsplt10; /* ALT_USB_HOST_HCSPLT10 */ + volatile ALT_USB_HOST_HCINT10_t hcint10; /* ALT_USB_HOST_HCINT10 */ + volatile ALT_USB_HOST_HCINTMSK10_t hcintmsk10; /* ALT_USB_HOST_HCINTMSK10 */ + volatile ALT_USB_HOST_HCTSIZ10_t hctsiz10; /* ALT_USB_HOST_HCTSIZ10 */ + volatile ALT_USB_HOST_HCDMA10_t hcdma10; /* ALT_USB_HOST_HCDMA10 */ + volatile ALT_USB_HOST_HCDMAB10_t hcdmab10; /* ALT_USB_HOST_HCDMAB10 */ + volatile uint32_t _pad_0x25c_0x25f; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR11_t hcchar11; /* ALT_USB_HOST_HCCHAR11 */ + volatile ALT_USB_HOST_HCSPLT11_t HCSPLT11; /* ALT_USB_HOST_HCSPLT11 */ + volatile ALT_USB_HOST_HCINT11_t hcint11; /* ALT_USB_HOST_HCINT11 */ + volatile ALT_USB_HOST_HCINTMSK11_t hcintmsk11; /* ALT_USB_HOST_HCINTMSK11 */ + volatile ALT_USB_HOST_HCTSIZ11_t hctsiz11; /* ALT_USB_HOST_HCTSIZ11 */ + volatile ALT_USB_HOST_HCDMA11_t hcdma11; /* ALT_USB_HOST_HCDMA11 */ + volatile ALT_USB_HOST_HCDMAB11_t hcdmab11; /* ALT_USB_HOST_HCDMAB11 */ + volatile uint32_t _pad_0x27c_0x27f; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR12_t hcchar12; /* ALT_USB_HOST_HCCHAR12 */ + volatile ALT_USB_HOST_HCSPLT12_t hcsplt12; /* ALT_USB_HOST_HCSPLT12 */ + volatile ALT_USB_HOST_HCINT12_t hcint12; /* ALT_USB_HOST_HCINT12 */ + volatile ALT_USB_HOST_HCINTMSK12_t hcintmsk12; /* ALT_USB_HOST_HCINTMSK12 */ + volatile ALT_USB_HOST_HCTSIZ12_t hctsiz12; /* ALT_USB_HOST_HCTSIZ12 */ + volatile ALT_USB_HOST_HCDMA12_t hcdma12; /* ALT_USB_HOST_HCDMA12 */ + volatile ALT_USB_HOST_HCDMAB12_t hcdmab12; /* ALT_USB_HOST_HCDMAB12 */ + volatile uint32_t _pad_0x29c_0x29f; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR13_t hcchar13; /* ALT_USB_HOST_HCCHAR13 */ + volatile ALT_USB_HOST_HCSPLT13_t hcsplt13; /* ALT_USB_HOST_HCSPLT13 */ + volatile ALT_USB_HOST_HCINT13_t hcint13; /* ALT_USB_HOST_HCINT13 */ + volatile ALT_USB_HOST_HCINTMSK13_t hcintmsk13; /* ALT_USB_HOST_HCINTMSK13 */ + volatile ALT_USB_HOST_HCTSIZ13_t hctsiz13; /* ALT_USB_HOST_HCTSIZ13 */ + volatile ALT_USB_HOST_HCDMA13_t hcdma13; /* ALT_USB_HOST_HCDMA13 */ + volatile ALT_USB_HOST_HCDMAB13_t hcdmab13; /* ALT_USB_HOST_HCDMAB13 */ + volatile uint32_t _pad_0x2bc_0x2bf; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR14_t hcchar14; /* ALT_USB_HOST_HCCHAR14 */ + volatile ALT_USB_HOST_HCSPLT14_t hcsplt14; /* ALT_USB_HOST_HCSPLT14 */ + volatile ALT_USB_HOST_HCINT14_t hcint14; /* ALT_USB_HOST_HCINT14 */ + volatile ALT_USB_HOST_HCINTMSK14_t hcintmsk14; /* ALT_USB_HOST_HCINTMSK14 */ + volatile ALT_USB_HOST_HCTSIZ14_t hctsiz14; /* ALT_USB_HOST_HCTSIZ14 */ + volatile ALT_USB_HOST_HCDMA14_t hcdma14; /* ALT_USB_HOST_HCDMA14 */ + volatile ALT_USB_HOST_HCDMAB14_t hcdmab14; /* ALT_USB_HOST_HCDMAB14 */ + volatile uint32_t _pad_0x2dc_0x2df; /* *UNDEFINED* */ + volatile ALT_USB_HOST_HCCHAR15_t hcchar15; /* ALT_USB_HOST_HCCHAR15 */ + volatile ALT_USB_HOST_HCSPLT15_t hcsplt15; /* ALT_USB_HOST_HCSPLT15 */ + volatile ALT_USB_HOST_HCINT15_t hcint15; /* ALT_USB_HOST_HCINT15 */ + volatile ALT_USB_HOST_HCINTMSK15_t hcintmsk15; /* ALT_USB_HOST_HCINTMSK15 */ + volatile ALT_USB_HOST_HCTSIZ15_t hctsiz15; /* ALT_USB_HOST_HCTSIZ15 */ + volatile ALT_USB_HOST_HCDMA15_t hcdma15; /* ALT_USB_HOST_HCDMA15 */ + volatile ALT_USB_HOST_HCDMAB15_t hcdmab15; /* ALT_USB_HOST_HCDMAB15 */ +}; + +/* The typedef declaration for register group ALT_USB_HOST. */ +typedef volatile struct ALT_USB_HOST_s ALT_USB_HOST_t; +/* The struct declaration for the raw register contents of register group ALT_USB_HOST. */ +struct ALT_USB_HOST_raw_s +{ + volatile uint32_t hcfg; /* ALT_USB_HOST_HCFG */ + volatile uint32_t hfir; /* ALT_USB_HOST_HFIR */ + volatile uint32_t hfnum; /* ALT_USB_HOST_HFNUM */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t hptxsts; /* ALT_USB_HOST_HPTXSTS */ + volatile uint32_t haint; /* ALT_USB_HOST_HAINT */ + volatile uint32_t haintmsk; /* ALT_USB_HOST_HAINTMSK */ + volatile uint32_t hflbaddr; /* ALT_USB_HOST_HFLBADDR */ + volatile uint32_t _pad_0x20_0x3f[8]; /* *UNDEFINED* */ + volatile uint32_t hprt; /* ALT_USB_HOST_HPRT */ + volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */ + volatile uint32_t hcchar0; /* ALT_USB_HOST_HCCHAR0 */ + volatile uint32_t hcsplt0; /* ALT_USB_HOST_HCSPLT0 */ + volatile uint32_t hcint0; /* ALT_USB_HOST_HCINT0 */ + volatile uint32_t hcintmsk0; /* ALT_USB_HOST_HCINTMSK0 */ + volatile uint32_t hctsiz0; /* ALT_USB_HOST_HCTSIZ0 */ + volatile uint32_t hcdma0; /* ALT_USB_HOST_HCDMA0 */ + volatile uint32_t hcdmab0; /* ALT_USB_HOST_HCDMAB0 */ + volatile uint32_t _pad_0x11c_0x11f; /* *UNDEFINED* */ + volatile uint32_t hcchar1; /* ALT_USB_HOST_HCCHAR1 */ + volatile uint32_t hcsplt1; /* ALT_USB_HOST_HCSPLT1 */ + volatile uint32_t hcint1; /* ALT_USB_HOST_HCINT1 */ + volatile uint32_t hcintmsk1; /* ALT_USB_HOST_HCINTMSK1 */ + volatile uint32_t hctsiz1; /* ALT_USB_HOST_HCTSIZ1 */ + volatile uint32_t hcdma1; /* ALT_USB_HOST_HCDMA1 */ + volatile uint32_t hcdmab1; /* ALT_USB_HOST_HCDMAB1 */ + volatile uint32_t _pad_0x13c_0x13f; /* *UNDEFINED* */ + volatile uint32_t hcchar2; /* ALT_USB_HOST_HCCHAR2 */ + volatile uint32_t hcsplt2; /* ALT_USB_HOST_HCSPLT2 */ + volatile uint32_t hcint2; /* ALT_USB_HOST_HCINT2 */ + volatile uint32_t hcintmsk2; /* ALT_USB_HOST_HCINTMSK2 */ + volatile uint32_t hctsiz2; /* ALT_USB_HOST_HCTSIZ2 */ + volatile uint32_t hcdma2; /* ALT_USB_HOST_HCDMA2 */ + volatile uint32_t hcdmab2; /* ALT_USB_HOST_HCDMAB2 */ + volatile uint32_t _pad_0x15c_0x15f; /* *UNDEFINED* */ + volatile uint32_t hcchar3; /* ALT_USB_HOST_HCCHAR3 */ + volatile uint32_t hcsplt3; /* ALT_USB_HOST_HCSPLT3 */ + volatile uint32_t hcint3; /* ALT_USB_HOST_HCINT3 */ + volatile uint32_t hcintmsk3; /* ALT_USB_HOST_HCINTMSK3 */ + volatile uint32_t hctsiz3; /* ALT_USB_HOST_HCTSIZ3 */ + volatile uint32_t hcdma3; /* ALT_USB_HOST_HCDMA3 */ + volatile uint32_t hcdmab3; /* ALT_USB_HOST_HCDMAB3 */ + volatile uint32_t _pad_0x17c_0x17f; /* *UNDEFINED* */ + volatile uint32_t hcchar4; /* ALT_USB_HOST_HCCHAR4 */ + volatile uint32_t hcsplt4; /* ALT_USB_HOST_HCSPLT4 */ + volatile uint32_t hcint4; /* ALT_USB_HOST_HCINT4 */ + volatile uint32_t hcintmsk4; /* ALT_USB_HOST_HCINTMSK4 */ + volatile uint32_t hctsiz4; /* ALT_USB_HOST_HCTSIZ4 */ + volatile uint32_t hcdma4; /* ALT_USB_HOST_HCDMA4 */ + volatile uint32_t hcdmab4; /* ALT_USB_HOST_HCDMAB4 */ + volatile uint32_t _pad_0x19c_0x19f; /* *UNDEFINED* */ + volatile uint32_t hcchar5; /* ALT_USB_HOST_HCCHAR5 */ + volatile uint32_t hcsplt5; /* ALT_USB_HOST_HCSPLT5 */ + volatile uint32_t hcint5; /* ALT_USB_HOST_HCINT5 */ + volatile uint32_t hcintmsk5; /* ALT_USB_HOST_HCINTMSK5 */ + volatile uint32_t hctsiz5; /* ALT_USB_HOST_HCTSIZ5 */ + volatile uint32_t hcdma5; /* ALT_USB_HOST_HCDMA5 */ + volatile uint32_t hcdmab5; /* ALT_USB_HOST_HCDMAB5 */ + volatile uint32_t _pad_0x1bc_0x1bf; /* *UNDEFINED* */ + volatile uint32_t hcchar6; /* ALT_USB_HOST_HCCHAR6 */ + volatile uint32_t hcsplt6; /* ALT_USB_HOST_HCSPLT6 */ + volatile uint32_t hcint6; /* ALT_USB_HOST_HCINT6 */ + volatile uint32_t hcintmsk6; /* ALT_USB_HOST_HCINTMSK6 */ + volatile uint32_t hctsiz6; /* ALT_USB_HOST_HCTSIZ6 */ + volatile uint32_t hcdma6; /* ALT_USB_HOST_HCDMA6 */ + volatile uint32_t hcdmab6; /* ALT_USB_HOST_HCDMAB6 */ + volatile uint32_t _pad_0x1dc_0x1df; /* *UNDEFINED* */ + volatile uint32_t hcchar7; /* ALT_USB_HOST_HCCHAR7 */ + volatile uint32_t hcsplt7; /* ALT_USB_HOST_HCSPLT7 */ + volatile uint32_t hcint7; /* ALT_USB_HOST_HCINT7 */ + volatile uint32_t hcintmsk7; /* ALT_USB_HOST_HCINTMSK7 */ + volatile uint32_t hctsiz7; /* ALT_USB_HOST_HCTSIZ7 */ + volatile uint32_t hcdma7; /* ALT_USB_HOST_HCDMA7 */ + volatile uint32_t hcdmab7; /* ALT_USB_HOST_HCDMAB7 */ + volatile uint32_t _pad_0x1fc_0x1ff; /* *UNDEFINED* */ + volatile uint32_t hcchar8; /* ALT_USB_HOST_HCCHAR8 */ + volatile uint32_t hcsplt8; /* ALT_USB_HOST_HCSPLT8 */ + volatile uint32_t hcint8; /* ALT_USB_HOST_HCINT8 */ + volatile uint32_t hcintmsk8; /* ALT_USB_HOST_HCINTMSK8 */ + volatile uint32_t hctsiz8; /* ALT_USB_HOST_HCTSIZ8 */ + volatile uint32_t hcdma8; /* ALT_USB_HOST_HCDMA8 */ + volatile uint32_t hcdmab8; /* ALT_USB_HOST_HCDMAB8 */ + volatile uint32_t _pad_0x21c_0x21f; /* *UNDEFINED* */ + volatile uint32_t hcchar9; /* ALT_USB_HOST_HCCHAR9 */ + volatile uint32_t hcsplt9; /* ALT_USB_HOST_HCSPLT9 */ + volatile uint32_t hcint9; /* ALT_USB_HOST_HCINT9 */ + volatile uint32_t hcintmsk9; /* ALT_USB_HOST_HCINTMSK9 */ + volatile uint32_t hctsiz9; /* ALT_USB_HOST_HCTSIZ9 */ + volatile uint32_t hcdma9; /* ALT_USB_HOST_HCDMA9 */ + volatile uint32_t hcdmab9; /* ALT_USB_HOST_HCDMAB9 */ + volatile uint32_t _pad_0x23c_0x23f; /* *UNDEFINED* */ + volatile uint32_t hcchar10; /* ALT_USB_HOST_HCCHAR10 */ + volatile uint32_t hcsplt10; /* ALT_USB_HOST_HCSPLT10 */ + volatile uint32_t hcint10; /* ALT_USB_HOST_HCINT10 */ + volatile uint32_t hcintmsk10; /* ALT_USB_HOST_HCINTMSK10 */ + volatile uint32_t hctsiz10; /* ALT_USB_HOST_HCTSIZ10 */ + volatile uint32_t hcdma10; /* ALT_USB_HOST_HCDMA10 */ + volatile uint32_t hcdmab10; /* ALT_USB_HOST_HCDMAB10 */ + volatile uint32_t _pad_0x25c_0x25f; /* *UNDEFINED* */ + volatile uint32_t hcchar11; /* ALT_USB_HOST_HCCHAR11 */ + volatile uint32_t HCSPLT11; /* ALT_USB_HOST_HCSPLT11 */ + volatile uint32_t hcint11; /* ALT_USB_HOST_HCINT11 */ + volatile uint32_t hcintmsk11; /* ALT_USB_HOST_HCINTMSK11 */ + volatile uint32_t hctsiz11; /* ALT_USB_HOST_HCTSIZ11 */ + volatile uint32_t hcdma11; /* ALT_USB_HOST_HCDMA11 */ + volatile uint32_t hcdmab11; /* ALT_USB_HOST_HCDMAB11 */ + volatile uint32_t _pad_0x27c_0x27f; /* *UNDEFINED* */ + volatile uint32_t hcchar12; /* ALT_USB_HOST_HCCHAR12 */ + volatile uint32_t hcsplt12; /* ALT_USB_HOST_HCSPLT12 */ + volatile uint32_t hcint12; /* ALT_USB_HOST_HCINT12 */ + volatile uint32_t hcintmsk12; /* ALT_USB_HOST_HCINTMSK12 */ + volatile uint32_t hctsiz12; /* ALT_USB_HOST_HCTSIZ12 */ + volatile uint32_t hcdma12; /* ALT_USB_HOST_HCDMA12 */ + volatile uint32_t hcdmab12; /* ALT_USB_HOST_HCDMAB12 */ + volatile uint32_t _pad_0x29c_0x29f; /* *UNDEFINED* */ + volatile uint32_t hcchar13; /* ALT_USB_HOST_HCCHAR13 */ + volatile uint32_t hcsplt13; /* ALT_USB_HOST_HCSPLT13 */ + volatile uint32_t hcint13; /* ALT_USB_HOST_HCINT13 */ + volatile uint32_t hcintmsk13; /* ALT_USB_HOST_HCINTMSK13 */ + volatile uint32_t hctsiz13; /* ALT_USB_HOST_HCTSIZ13 */ + volatile uint32_t hcdma13; /* ALT_USB_HOST_HCDMA13 */ + volatile uint32_t hcdmab13; /* ALT_USB_HOST_HCDMAB13 */ + volatile uint32_t _pad_0x2bc_0x2bf; /* *UNDEFINED* */ + volatile uint32_t hcchar14; /* ALT_USB_HOST_HCCHAR14 */ + volatile uint32_t hcsplt14; /* ALT_USB_HOST_HCSPLT14 */ + volatile uint32_t hcint14; /* ALT_USB_HOST_HCINT14 */ + volatile uint32_t hcintmsk14; /* ALT_USB_HOST_HCINTMSK14 */ + volatile uint32_t hctsiz14; /* ALT_USB_HOST_HCTSIZ14 */ + volatile uint32_t hcdma14; /* ALT_USB_HOST_HCDMA14 */ + volatile uint32_t hcdmab14; /* ALT_USB_HOST_HCDMAB14 */ + volatile uint32_t _pad_0x2dc_0x2df; /* *UNDEFINED* */ + volatile uint32_t hcchar15; /* ALT_USB_HOST_HCCHAR15 */ + volatile uint32_t hcsplt15; /* ALT_USB_HOST_HCSPLT15 */ + volatile uint32_t hcint15; /* ALT_USB_HOST_HCINT15 */ + volatile uint32_t hcintmsk15; /* ALT_USB_HOST_HCINTMSK15 */ + volatile uint32_t hctsiz15; /* ALT_USB_HOST_HCTSIZ15 */ + volatile uint32_t hcdma15; /* ALT_USB_HOST_HCDMA15 */ + volatile uint32_t hcdmab15; /* ALT_USB_HOST_HCDMAB15 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_USB_HOST. */ +typedef volatile struct ALT_USB_HOST_raw_s ALT_USB_HOST_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Device Mode Registers - ALT_USB_DEV + * Device Mode Registers + * + * These registers must be programmed every time the USB OTG Controller changes to + * Device mode. + * + */ +/* + * Register : Device Configuration Register - dcfg + * + * This register configures the core in Device mode after power-on or after certain + * control commands or enumeration. Do not make changes to this register after + * initial programming. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------- + * [1:0] | RW | 0x0 | Device Speed + * [2] | RW | 0x0 | Non-Zero-Length Status OUT Handshak + * [3] | RW | 0x0 | Enable 32 KHz Suspend mode + * [10:4] | RW | 0x0 | Device Address + * [12:11] | RW | 0x0 | Periodic Frame Interval + * [13] | RW | 0x0 | Enable Device OUT NA + * [22:14] | ??? | 0x0 | *UNDEFINED* + * [23] | RW | 0x0 | Enable Scatter gather DMA in device mode + * [25:24] | RW | 0x0 | Periodic Scheduling Interva + * [31:26] | RW | 0x2 | Resume Validation Period + * + */ +/* + * Field : Device Speed - devspd + * + * Indicates the speed at which the application requires the core to enumerate, or + * the maximum speed the application can support. However, the actual bus speed is + * determined only after the chirp sequence is completed, and is based on the speed + * of the USB host to which the core is connected. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20 | 0x0 | High speed USB 2.0 PHY clock is 30 MHz or 60 MHz + * ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20 | 0x1 | Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz + * ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116 | 0x2 | Low speed USB 1.1 transceiver clock is 6 MHz + * ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148 | 0x3 | Full speed USB 1.1 transceiver clock is 48 MHz + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD + * + * High speed USB 2.0 PHY clock is 30 MHz or 60 MHz + */ +#define ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD + * + * Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz + */ +#define ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD + * + * Low speed USB 1.1 transceiver clock is 6 MHz + */ +#define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD + * + * Full speed USB 1.1 transceiver clock is 48 MHz + */ +#define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DEVSPD register field. */ +#define ALT_USB_DEV_DCFG_DEVSPD_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DEVSPD register field. */ +#define ALT_USB_DEV_DCFG_DEVSPD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DCFG_DEVSPD register field. */ +#define ALT_USB_DEV_DCFG_DEVSPD_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DCFG_DEVSPD register field value. */ +#define ALT_USB_DEV_DCFG_DEVSPD_SET_MSK 0x00000003 +/* The mask used to clear the ALT_USB_DEV_DCFG_DEVSPD register field value. */ +#define ALT_USB_DEV_DCFG_DEVSPD_CLR_MSK 0xfffffffc +/* The reset value of the ALT_USB_DEV_DCFG_DEVSPD register field. */ +#define ALT_USB_DEV_DCFG_DEVSPD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCFG_DEVSPD field value from a register. */ +#define ALT_USB_DEV_DCFG_DEVSPD_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_USB_DEV_DCFG_DEVSPD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCFG_DEVSPD_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : Non-Zero-Length Status OUT Handshak - nzstsouthshk + * + * The application can use this field to select the handshake the core sends on + * receiving a nonzero-length data packet during the OUT transaction of a control + * transfer's Status stage. 1: Send a STALL handshake on a nonzero-length statusOUT + * transaction and do not send the received OUT packet tothe application. 0: Send + * the received OUT packet to the application (zerolengthor nonzero-length) and + * send a handshake based onthe NAK and STALL bits for the endpoint in the + * DeviceEndpoint Control register. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT | 0x0 | Send the received OUT packet to the application + * : | | zerolength + * ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL | 0x1 | Send a STALL handshake on a nonzero-length + * : | | status OUT transaction and do not send the + * : | | received OUT packet to the application + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_NZSTSOUTHSHK + * + * Send the received OUT packet to the application zerolength + */ +#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_NZSTSOUTHSHK + * + * Send a STALL handshake on a nonzero-length status OUT transaction and do not + * send the received OUT packet to the application + */ +#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */ +#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */ +#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_MSB 2 +/* The width in bits of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */ +#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value. */ +#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value. */ +#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */ +#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCFG_NZSTSOUTHSHK field value from a register. */ +#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Enable 32 KHz Suspend mode - ena32khzsusp + * + * When the USB 1.1 Full-Speed Serial Transceiver Interface is chosen and this bit + * is set, the core expects the 48-MHz PHY clock to be switched to 32 KHz during a + * suspend. This bit can only be set if USB 1.1 Full-Speed Serial Transceiver + * Interface has been selected. If USB 1.1 Full-Speed Serial Transceiver Interface + * has not been selected, this bit must be zero. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD | 0x0 | USB 1.1 Full-Speed Serial Transceiver not + * : | | selected + * ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END | 0x1 | USB 1.1 Full-Speed Serial Transceiver Interface + * : | | selected + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_ENA32KHZSUSP + * + * USB 1.1 Full-Speed Serial Transceiver not selected + */ +#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_ENA32KHZSUSP + * + * USB 1.1 Full-Speed Serial Transceiver Interface selected + */ +#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */ +#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */ +#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */ +#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value. */ +#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value. */ +#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */ +#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCFG_ENA32KHZSUSP field value from a register. */ +#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Device Address - devaddr + * + * The application must program this field after every SetAddress control command. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DEVADDR register field. */ +#define ALT_USB_DEV_DCFG_DEVADDR_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DEVADDR register field. */ +#define ALT_USB_DEV_DCFG_DEVADDR_MSB 10 +/* The width in bits of the ALT_USB_DEV_DCFG_DEVADDR register field. */ +#define ALT_USB_DEV_DCFG_DEVADDR_WIDTH 7 +/* The mask used to set the ALT_USB_DEV_DCFG_DEVADDR register field value. */ +#define ALT_USB_DEV_DCFG_DEVADDR_SET_MSK 0x000007f0 +/* The mask used to clear the ALT_USB_DEV_DCFG_DEVADDR register field value. */ +#define ALT_USB_DEV_DCFG_DEVADDR_CLR_MSK 0xfffff80f +/* The reset value of the ALT_USB_DEV_DCFG_DEVADDR register field. */ +#define ALT_USB_DEV_DCFG_DEVADDR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCFG_DEVADDR field value from a register. */ +#define ALT_USB_DEV_DCFG_DEVADDR_GET(value) (((value) & 0x000007f0) >> 4) +/* Produces a ALT_USB_DEV_DCFG_DEVADDR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCFG_DEVADDR_SET(value) (((value) << 4) & 0x000007f0) + +/* + * Field : Periodic Frame Interval - perfrint + * + * Indicates the time within a (micro)frame at which the application must be + * notified using the End Of Periodic Frame Interrupt. This can be used to + * determine If all the isochronous traffic for that (micro)frame is complete. 0x0: + * 80% of the (micro)frame interval 0x1: 85% 0x2: 90% 0x3: 95% + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------------------------- + * ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80 | 0x0 | 80% of the (micro)frame interval + * ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85 | 0x1 | 85% of the (micro)frame interval + * ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90 | 0x2 | 90% of the (micro)frame interval + * ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95 | 0x3 | 95% of the (micro)frame interval + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT + * + * 80% of the (micro)frame interval + */ +#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT + * + * 85% of the (micro)frame interval + */ +#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT + * + * 90% of the (micro)frame interval + */ +#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT + * + * 95% of the (micro)frame interval + */ +#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_PERFRINT register field. */ +#define ALT_USB_DEV_DCFG_PERFRINT_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_PERFRINT register field. */ +#define ALT_USB_DEV_DCFG_PERFRINT_MSB 12 +/* The width in bits of the ALT_USB_DEV_DCFG_PERFRINT register field. */ +#define ALT_USB_DEV_DCFG_PERFRINT_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DCFG_PERFRINT register field value. */ +#define ALT_USB_DEV_DCFG_PERFRINT_SET_MSK 0x00001800 +/* The mask used to clear the ALT_USB_DEV_DCFG_PERFRINT register field value. */ +#define ALT_USB_DEV_DCFG_PERFRINT_CLR_MSK 0xffffe7ff +/* The reset value of the ALT_USB_DEV_DCFG_PERFRINT register field. */ +#define ALT_USB_DEV_DCFG_PERFRINT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCFG_PERFRINT field value from a register. */ +#define ALT_USB_DEV_DCFG_PERFRINT_GET(value) (((value) & 0x00001800) >> 11) +/* Produces a ALT_USB_DEV_DCFG_PERFRINT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCFG_PERFRINT_SET(value) (((value) << 11) & 0x00001800) + +/* + * Field : Enable Device OUT NA - endevoutnak + * + * This bit enables setting NAK for Bulk OUT endpoints after the transfer is + * completed for Device mode Descriptor DMA It is one time programmable after reset + * like any other DCFG register bits. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------ + * ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD | 0x0 | The core does not set NAK after Bulk OUT + * : | | transfer complete + * ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END | 0x1 | The core sets NAK after Bulk OUT transfer + * : | | complete + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_ENDEVOUTNAK + * + * The core does not set NAK after Bulk OUT transfer complete + */ +#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_ENDEVOUTNAK + * + * The core sets NAK after Bulk OUT transfer complete + */ +#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */ +#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */ +#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_MSB 13 +/* The width in bits of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */ +#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value. */ +#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value. */ +#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */ +#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCFG_ENDEVOUTNAK field value from a register. */ +#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : Enable Scatter gather DMA in device mode - descdma + * + * When the Scatter/Gather DMA option selected during configuration of the RTL, the + * application can Set this bit during initialization to enable the Scatter/Gather + * DMA operation. This bit must be modified only once after a reset.The following + * combinations are available for programming: + * + * GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode + * + * GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid + * + * GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffered DMA + * + * mode GAHBCFG.DMAEn=1,DCFG.DescDMA=1 => Scatter/Gather DMA mode + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DCFG_DESCDMA_E_DISD | 0x0 | Disable Scatter gather DMA + * ALT_USB_DEV_DCFG_DESCDMA_E_END | 0x1 | Enable Scatter gather DMA + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_DESCDMA + * + * Disable Scatter gather DMA + */ +#define ALT_USB_DEV_DCFG_DESCDMA_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_DESCDMA + * + * Enable Scatter gather DMA + */ +#define ALT_USB_DEV_DCFG_DESCDMA_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DESCDMA register field. */ +#define ALT_USB_DEV_DCFG_DESCDMA_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DESCDMA register field. */ +#define ALT_USB_DEV_DCFG_DESCDMA_MSB 23 +/* The width in bits of the ALT_USB_DEV_DCFG_DESCDMA register field. */ +#define ALT_USB_DEV_DCFG_DESCDMA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCFG_DESCDMA register field value. */ +#define ALT_USB_DEV_DCFG_DESCDMA_SET_MSK 0x00800000 +/* The mask used to clear the ALT_USB_DEV_DCFG_DESCDMA register field value. */ +#define ALT_USB_DEV_DCFG_DESCDMA_CLR_MSK 0xff7fffff +/* The reset value of the ALT_USB_DEV_DCFG_DESCDMA register field. */ +#define ALT_USB_DEV_DCFG_DESCDMA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCFG_DESCDMA field value from a register. */ +#define ALT_USB_DEV_DCFG_DESCDMA_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_USB_DEV_DCFG_DESCDMA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCFG_DESCDMA_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : Periodic Scheduling Interva - perschintvl + * + * PerSchIntvl must be programmed only for Scatter/Gather DMAmode. Description: + * This field specifies the amount of time the Internal DMA engine must allocate + * for fetching periodic IN endpoint data. Based on the number of periodic + * endpoints, this value must be specified as 25,50 or 75% of (micro)frame. When + * any periodic endpoints are active, the internal DMA engine allocates the + * specified amount of time in fetching periodic IN endpoint data . When no + * periodic endpoints are active, Then the internal DMA engine services non- + * periodic endpoints, ignoring this field. After the specified time within a + * (micro)frame, the DMA switches to fetching for non-periodic endpoints. 2'b00: + * 25% of (micro)frame. 2'b01: 50% of (micro)frame. 2'b10: 75% of (micro)frame. + * 2'b11: Reserved.Reset: 2'b00Access: read-write + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25 | 0x0 | 25% of (micro)frame + * ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50 | 0x1 | 50% of (micro)frame + * ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75 | 0x2 | 75% of (micro)frame + * ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD | 0x3 | Reserved + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL + * + * 25% of (micro)frame + */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL + * + * 50% of (micro)frame + */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL + * + * 75% of (micro)frame + */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL + * + * Reserved + */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_MSB 25 +/* The width in bits of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DCFG_PERSCHINTVL register field value. */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_SET_MSK 0x03000000 +/* The mask used to clear the ALT_USB_DEV_DCFG_PERSCHINTVL register field value. */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_CLR_MSK 0xfcffffff +/* The reset value of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCFG_PERSCHINTVL field value from a register. */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_GET(value) (((value) & 0x03000000) >> 24) +/* Produces a ALT_USB_DEV_DCFG_PERSCHINTVL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCFG_PERSCHINTVL_SET(value) (((value) << 24) & 0x03000000) + +/* + * Field : Resume Validation Period - resvalid + * + * This field is effective only when DCFG.Ena32KHzSusp is set. It will control the + * resume period when the core resumes from suspend. The core counts for ResValid + * number of clock cycles to detect a valid resume when this is set + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_RESVALID register field. */ +#define ALT_USB_DEV_DCFG_RESVALID_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_RESVALID register field. */ +#define ALT_USB_DEV_DCFG_RESVALID_MSB 31 +/* The width in bits of the ALT_USB_DEV_DCFG_RESVALID register field. */ +#define ALT_USB_DEV_DCFG_RESVALID_WIDTH 6 +/* The mask used to set the ALT_USB_DEV_DCFG_RESVALID register field value. */ +#define ALT_USB_DEV_DCFG_RESVALID_SET_MSK 0xfc000000 +/* The mask used to clear the ALT_USB_DEV_DCFG_RESVALID register field value. */ +#define ALT_USB_DEV_DCFG_RESVALID_CLR_MSK 0x03ffffff +/* The reset value of the ALT_USB_DEV_DCFG_RESVALID register field. */ +#define ALT_USB_DEV_DCFG_RESVALID_RESET 0x2 +/* Extracts the ALT_USB_DEV_DCFG_RESVALID field value from a register. */ +#define ALT_USB_DEV_DCFG_RESVALID_GET(value) (((value) & 0xfc000000) >> 26) +/* Produces a ALT_USB_DEV_DCFG_RESVALID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCFG_RESVALID_SET(value) (((value) << 26) & 0xfc000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DCFG. + */ +struct ALT_USB_DEV_DCFG_s +{ + uint32_t devspd : 2; /* Device Speed */ + uint32_t nzstsouthshk : 1; /* Non-Zero-Length Status OUT Handshak */ + uint32_t ena32khzsusp : 1; /* Enable 32 KHz Suspend mode */ + uint32_t devaddr : 7; /* Device Address */ + uint32_t perfrint : 2; /* Periodic Frame Interval */ + uint32_t endevoutnak : 1; /* Enable Device OUT NA */ + uint32_t : 9; /* *UNDEFINED* */ + uint32_t descdma : 1; /* Enable Scatter gather DMA in device mode */ + uint32_t perschintvl : 2; /* Periodic Scheduling Interva */ + uint32_t resvalid : 6; /* Resume Validation Period */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DCFG. */ +typedef volatile struct ALT_USB_DEV_DCFG_s ALT_USB_DEV_DCFG_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DCFG register from the beginning of the component. */ +#define ALT_USB_DEV_DCFG_OFST 0x0 +/* The address of the ALT_USB_DEV_DCFG register. */ +#define ALT_USB_DEV_DCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DCFG_OFST)) + +/* + * Register : Device Control Register - dctl + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------------------------- + * [0] | RW | 0x0 | Remote Wakeup Signaling + * [1] | RW | 0x0 | Soft Disconnect + * [2] | R | 0x0 | Global Non-periodic IN NAK Status + * [3] | R | 0x0 | Global OUT NAK Status + * [6:4] | RW | 0x0 | Test Control + * [7] | W | 0x0 | Set Global Non-periodic IN NAK + * [8] | W | 0x0 | Clear Global Non-periodic IN NAK + * [9] | W | 0x0 | Set Global OUT NAK + * [10] | W | 0x0 | Clear Global OUT NAK + * [11] | RW | 0x0 | Power-On Programming Done + * [12] | ??? | 0x0 | *UNDEFINED* + * [14:13] | RW | 0x0 | Global Multi Count + * [15] | RW | 0x0 | Ignore Frame number for Isochronous Endpoints + * [16] | RW | 0x0 | NAK on Babble Error + * [31:17] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Remote Wakeup Signaling - rmtwkupsig + * + * When the application sets this bit, the core initiates remote signaling to wake + * up the USB host. The application must Set this bit to instruct the core to exit + * the Suspend state. As specified in the USB 2.0 specification, the application + * must clear this bit 115 ms after setting it. Remote Wakeup Signaling + * (RmtWkUpSig) When LPM is enabled, In L1 state the behavior of this bit is as + * follows: When the application sets this bit, the core initiates L1 remote + * signaling to wake up the USB host. The application must set this bit to instruct + * the core to exit the Sleep state. As specified in the LPM specification, the + * hardware will automatically clear this bit after a time of 50us + * (TL1DevDrvResume) after set by application. Application should not set this bit + * when GLPMCFG bRemoteWake from the previous LPM transaction was zero. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------- + * ALT_USB_DEV_DCTL_RMTWKUPSIG_E_NOEXIT | 0x0 | No exit suspend state + * ALT_USB_DEV_DCTL_RMTWKUPSIG_E_EXIT | 0x1 | Exit Suspend State + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_RMTWKUPSIG + * + * No exit suspend state + */ +#define ALT_USB_DEV_DCTL_RMTWKUPSIG_E_NOEXIT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_RMTWKUPSIG + * + * Exit Suspend State + */ +#define ALT_USB_DEV_DCTL_RMTWKUPSIG_E_EXIT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */ +#define ALT_USB_DEV_DCTL_RMTWKUPSIG_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */ +#define ALT_USB_DEV_DCTL_RMTWKUPSIG_MSB 0 +/* The width in bits of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */ +#define ALT_USB_DEV_DCTL_RMTWKUPSIG_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_RMTWKUPSIG register field value. */ +#define ALT_USB_DEV_DCTL_RMTWKUPSIG_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DCTL_RMTWKUPSIG register field value. */ +#define ALT_USB_DEV_DCTL_RMTWKUPSIG_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */ +#define ALT_USB_DEV_DCTL_RMTWKUPSIG_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_RMTWKUPSIG field value from a register. */ +#define ALT_USB_DEV_DCTL_RMTWKUPSIG_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DCTL_RMTWKUPSIG register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_RMTWKUPSIG_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Soft Disconnect - sftdiscon + * + * The application uses this bit to signal the otg core to do a soft disconnect. As + * long as this bit is Set, the host does not see that the device is connected, and + * the device does not receive signals on the USB. The core stays in the + * disconnected state until the application clears this bit. There is a minimum + * duration for which the core must keep this bit set. When this bit is cleared + * after a soft disconnect, the core drives the phy_opmode_o signal on the ULPI, + * which generates a device connect event to the USB host. When the device is + * reconnected, the USB host restarts device enumeration.; + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:----------------------------------------------- + * ALT_USB_DEV_DCTL_SFTDISCON_E_NODISCONNECT | 0x0 | Normal operation + * ALT_USB_DEV_DCTL_SFTDISCON_E_DISCONNECT | 0x1 | The core drives the phy_opmode_o signal on the + * : | | ULPI + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_SFTDISCON + * + * Normal operation + */ +#define ALT_USB_DEV_DCTL_SFTDISCON_E_NODISCONNECT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_SFTDISCON + * + * The core drives the phy_opmode_o signal on the ULPI + */ +#define ALT_USB_DEV_DCTL_SFTDISCON_E_DISCONNECT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SFTDISCON register field. */ +#define ALT_USB_DEV_DCTL_SFTDISCON_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SFTDISCON register field. */ +#define ALT_USB_DEV_DCTL_SFTDISCON_MSB 1 +/* The width in bits of the ALT_USB_DEV_DCTL_SFTDISCON register field. */ +#define ALT_USB_DEV_DCTL_SFTDISCON_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_SFTDISCON register field value. */ +#define ALT_USB_DEV_DCTL_SFTDISCON_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DCTL_SFTDISCON register field value. */ +#define ALT_USB_DEV_DCTL_SFTDISCON_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DCTL_SFTDISCON register field. */ +#define ALT_USB_DEV_DCTL_SFTDISCON_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_SFTDISCON field value from a register. */ +#define ALT_USB_DEV_DCTL_SFTDISCON_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DCTL_SFTDISCON register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_SFTDISCON_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Global Non-periodic IN NAK Status - gnpinnaksts + * + * Defines IN NAK conditions. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DCTL_GNPINNAKSTS_E_INACT | 0x0 | A handshake is sent out based on the data + * : | | availability in the transmit FIFO + * ALT_USB_DEV_DCTL_GNPINNAKSTS_E_ACT | 0x1 | A NAK handshake is sent out on all non-periodic + * : | | IN endpoints, irrespective of the data + * : | | availability in the transmit FIFO. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_GNPINNAKSTS + * + * A handshake is sent out based on the data availability in the transmit FIFO + */ +#define ALT_USB_DEV_DCTL_GNPINNAKSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_GNPINNAKSTS + * + * A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of + * the data availability in the transmit FIFO. + */ +#define ALT_USB_DEV_DCTL_GNPINNAKSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */ +#define ALT_USB_DEV_DCTL_GNPINNAKSTS_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */ +#define ALT_USB_DEV_DCTL_GNPINNAKSTS_MSB 2 +/* The width in bits of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */ +#define ALT_USB_DEV_DCTL_GNPINNAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_GNPINNAKSTS register field value. */ +#define ALT_USB_DEV_DCTL_GNPINNAKSTS_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DCTL_GNPINNAKSTS register field value. */ +#define ALT_USB_DEV_DCTL_GNPINNAKSTS_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */ +#define ALT_USB_DEV_DCTL_GNPINNAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_GNPINNAKSTS field value from a register. */ +#define ALT_USB_DEV_DCTL_GNPINNAKSTS_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DCTL_GNPINNAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_GNPINNAKSTS_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Global OUT NAK Status - goutnaksts + * + * Reports NAK status. All isochronous OUT packets aredropped. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------- + * ALT_USB_DEV_DCTL_GOUTNAKSTS_E_INACT | 0x0 | A handshake is sent based on the FIFO Status and + * : | | the NAK and STALL bit settings. + * ALT_USB_DEV_DCTL_GOUTNAKSTS_E_ACT | 0x1 | No data is written to the RxFIFO, irrespective + * : | | of space availability. Sends a NAK handshake on + * : | | all packets, except on SETUP transactions. All + * : | | isochronous OUT packets are dropped. + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_GOUTNAKSTS + * + * A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. + */ +#define ALT_USB_DEV_DCTL_GOUTNAKSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_GOUTNAKSTS + * + * No data is written to the RxFIFO, irrespective of space availability. Sends a + * NAK handshake on all packets, except on SETUP transactions. All isochronous OUT + * packets are dropped. + */ +#define ALT_USB_DEV_DCTL_GOUTNAKSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */ +#define ALT_USB_DEV_DCTL_GOUTNAKSTS_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */ +#define ALT_USB_DEV_DCTL_GOUTNAKSTS_MSB 3 +/* The width in bits of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */ +#define ALT_USB_DEV_DCTL_GOUTNAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_GOUTNAKSTS register field value. */ +#define ALT_USB_DEV_DCTL_GOUTNAKSTS_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DCTL_GOUTNAKSTS register field value. */ +#define ALT_USB_DEV_DCTL_GOUTNAKSTS_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */ +#define ALT_USB_DEV_DCTL_GOUTNAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_GOUTNAKSTS field value from a register. */ +#define ALT_USB_DEV_DCTL_GOUTNAKSTS_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DCTL_GOUTNAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_GOUTNAKSTS_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Test Control - tstctl + * + * Others: Reserved. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------- + * ALT_USB_DEV_DCTL_TSTCTL_E_DISD | 0x0 | Test mode disabled + * ALT_USB_DEV_DCTL_TSTCTL_E_TESTJ | 0x1 | Test_J mode + * ALT_USB_DEV_DCTL_TSTCTL_E_TESTK | 0x2 | Test_K mode + * ALT_USB_DEV_DCTL_TSTCTL_E_TESTSN | 0x3 | Test_SE0_NAK mode + * ALT_USB_DEV_DCTL_TSTCTL_E_TESTPM | 0x4 | Test_Packet mode + * ALT_USB_DEV_DCTL_TSTCTL_E_TESTFE | 0x5 | Test_force_Enable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL + * + * Test mode disabled + */ +#define ALT_USB_DEV_DCTL_TSTCTL_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL + * + * Test_J mode + */ +#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTJ 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL + * + * Test_K mode + */ +#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL + * + * Test_SE0_NAK mode + */ +#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTSN 0x3 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL + * + * Test_Packet mode + */ +#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTPM 0x4 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL + * + * Test_force_Enable + */ +#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTFE 0x5 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_TSTCTL register field. */ +#define ALT_USB_DEV_DCTL_TSTCTL_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_TSTCTL register field. */ +#define ALT_USB_DEV_DCTL_TSTCTL_MSB 6 +/* The width in bits of the ALT_USB_DEV_DCTL_TSTCTL register field. */ +#define ALT_USB_DEV_DCTL_TSTCTL_WIDTH 3 +/* The mask used to set the ALT_USB_DEV_DCTL_TSTCTL register field value. */ +#define ALT_USB_DEV_DCTL_TSTCTL_SET_MSK 0x00000070 +/* The mask used to clear the ALT_USB_DEV_DCTL_TSTCTL register field value. */ +#define ALT_USB_DEV_DCTL_TSTCTL_CLR_MSK 0xffffff8f +/* The reset value of the ALT_USB_DEV_DCTL_TSTCTL register field. */ +#define ALT_USB_DEV_DCTL_TSTCTL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_TSTCTL field value from a register. */ +#define ALT_USB_DEV_DCTL_TSTCTL_GET(value) (((value) & 0x00000070) >> 4) +/* Produces a ALT_USB_DEV_DCTL_TSTCTL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_TSTCTL_SET(value) (((value) << 4) & 0x00000070) + +/* + * Field : Set Global Non-periodic IN NAK - sgnpinnak + * + * A write to this field sets the Global Non-periodic IN NAK. The application uses + * this bit to send a NAK handshake on all nonperiodic IN endpoints. The core can + * also Set this bit when a timeout condition is detected on a non-periodic + * endpoint in shared FIFO operation. The application must Set this bit only after + * making sure that the Global IN NAK Effective bit in the Core Interrupt Register + * (GINTSTS.GINNakEff) is cleared + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------------- + * ALT_USB_DEV_DCTL_SGNPINNAK_E_DISD | 0x0 | Disable Global Non-periodic IN NAK + * ALT_USB_DEV_DCTL_SGNPINNAK_E_END | 0x1 | Global Non-periodic IN NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_SGNPINNAK + * + * Disable Global Non-periodic IN NAK + */ +#define ALT_USB_DEV_DCTL_SGNPINNAK_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_SGNPINNAK + * + * Global Non-periodic IN NAK + */ +#define ALT_USB_DEV_DCTL_SGNPINNAK_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */ +#define ALT_USB_DEV_DCTL_SGNPINNAK_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */ +#define ALT_USB_DEV_DCTL_SGNPINNAK_MSB 7 +/* The width in bits of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */ +#define ALT_USB_DEV_DCTL_SGNPINNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_SGNPINNAK register field value. */ +#define ALT_USB_DEV_DCTL_SGNPINNAK_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DCTL_SGNPINNAK register field value. */ +#define ALT_USB_DEV_DCTL_SGNPINNAK_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */ +#define ALT_USB_DEV_DCTL_SGNPINNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_SGNPINNAK field value from a register. */ +#define ALT_USB_DEV_DCTL_SGNPINNAK_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DCTL_SGNPINNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_SGNPINNAK_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Clear Global Non-periodic IN NAK - CGNPInNak + * + * A write to this field clears the Global Non-periodic IN NAK. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------------- + * ALT_USB_DEV_DCTL_CGNPINNAK_E_DIS | 0x0 | Disable Global Non-periodic IN NAK + * ALT_USB_DEV_DCTL_CGNPINNAK_E_EN | 0x1 | Clear Global Non-periodic IN NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_CGNPINNAK + * + * Disable Global Non-periodic IN NAK + */ +#define ALT_USB_DEV_DCTL_CGNPINNAK_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_CGNPINNAK + * + * Clear Global Non-periodic IN NAK + */ +#define ALT_USB_DEV_DCTL_CGNPINNAK_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */ +#define ALT_USB_DEV_DCTL_CGNPINNAK_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */ +#define ALT_USB_DEV_DCTL_CGNPINNAK_MSB 8 +/* The width in bits of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */ +#define ALT_USB_DEV_DCTL_CGNPINNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_CGNPINNAK register field value. */ +#define ALT_USB_DEV_DCTL_CGNPINNAK_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DCTL_CGNPINNAK register field value. */ +#define ALT_USB_DEV_DCTL_CGNPINNAK_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */ +#define ALT_USB_DEV_DCTL_CGNPINNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_CGNPINNAK field value from a register. */ +#define ALT_USB_DEV_DCTL_CGNPINNAK_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DCTL_CGNPINNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_CGNPINNAK_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : Set Global OUT NAK - sgoutnak + * + * A write to this field sets the Global OUT NAK.The application uses this bit to + * send a NAK handshake on all OUT endpoints. The application must Set the this bit + * only after making sure that the Global OUT NAK Effective bit in the Core + * Interrupt Register GINTSTS.GOUTNakEff) is cleared. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------- + * ALT_USB_DEV_DCTL_SGOUTNAK_E_DISD | 0x0 | Disable Global OUT NAK + * ALT_USB_DEV_DCTL_SGOUTNAK_E_END | 0x1 | Global OUT NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_SGOUTNAK + * + * Disable Global OUT NAK + */ +#define ALT_USB_DEV_DCTL_SGOUTNAK_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_SGOUTNAK + * + * Global OUT NAK + */ +#define ALT_USB_DEV_DCTL_SGOUTNAK_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */ +#define ALT_USB_DEV_DCTL_SGOUTNAK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */ +#define ALT_USB_DEV_DCTL_SGOUTNAK_MSB 9 +/* The width in bits of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */ +#define ALT_USB_DEV_DCTL_SGOUTNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_SGOUTNAK register field value. */ +#define ALT_USB_DEV_DCTL_SGOUTNAK_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DCTL_SGOUTNAK register field value. */ +#define ALT_USB_DEV_DCTL_SGOUTNAK_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */ +#define ALT_USB_DEV_DCTL_SGOUTNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_SGOUTNAK field value from a register. */ +#define ALT_USB_DEV_DCTL_SGOUTNAK_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DCTL_SGOUTNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_SGOUTNAK_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Clear Global OUT NAK - cgoutnak + * + * A write to this field clears the Global OUT NAK. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DCTL_CGOUTNAK_E_DISD | 0x0 | Disable Clear Global OUT NAK + * ALT_USB_DEV_DCTL_CGOUTNAK_E_END | 0x1 | Clear Global OUT NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_CGOUTNAK + * + * Disable Clear Global OUT NAK + */ +#define ALT_USB_DEV_DCTL_CGOUTNAK_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_CGOUTNAK + * + * Clear Global OUT NAK + */ +#define ALT_USB_DEV_DCTL_CGOUTNAK_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */ +#define ALT_USB_DEV_DCTL_CGOUTNAK_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */ +#define ALT_USB_DEV_DCTL_CGOUTNAK_MSB 10 +/* The width in bits of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */ +#define ALT_USB_DEV_DCTL_CGOUTNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_CGOUTNAK register field value. */ +#define ALT_USB_DEV_DCTL_CGOUTNAK_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_DEV_DCTL_CGOUTNAK register field value. */ +#define ALT_USB_DEV_DCTL_CGOUTNAK_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */ +#define ALT_USB_DEV_DCTL_CGOUTNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_CGOUTNAK field value from a register. */ +#define ALT_USB_DEV_DCTL_CGOUTNAK_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_DEV_DCTL_CGOUTNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_CGOUTNAK_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : Power-On Programming Done - pwronprgdone + * + * The application uses this bit to indicate that registerprogramming is completed + * after a wake-up from Power Downmode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DCTL_PWRONPRGDONE_E_NOTDONE | 0x0 | Power-On Programming not done + * ALT_USB_DEV_DCTL_PWRONPRGDONE_E_DONE | 0x1 | Power-On Programming Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_PWRONPRGDONE + * + * Power-On Programming not done + */ +#define ALT_USB_DEV_DCTL_PWRONPRGDONE_E_NOTDONE 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_PWRONPRGDONE + * + * Power-On Programming Done + */ +#define ALT_USB_DEV_DCTL_PWRONPRGDONE_E_DONE 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */ +#define ALT_USB_DEV_DCTL_PWRONPRGDONE_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */ +#define ALT_USB_DEV_DCTL_PWRONPRGDONE_MSB 11 +/* The width in bits of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */ +#define ALT_USB_DEV_DCTL_PWRONPRGDONE_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_PWRONPRGDONE register field value. */ +#define ALT_USB_DEV_DCTL_PWRONPRGDONE_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DCTL_PWRONPRGDONE register field value. */ +#define ALT_USB_DEV_DCTL_PWRONPRGDONE_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */ +#define ALT_USB_DEV_DCTL_PWRONPRGDONE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_PWRONPRGDONE field value from a register. */ +#define ALT_USB_DEV_DCTL_PWRONPRGDONE_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DCTL_PWRONPRGDONE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_PWRONPRGDONE_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : Global Multi Count - gmc + * + * GMC must be programmed only once after initialization.Applicable only for + * Scatter/Gather DMA mode. This indicates the number of packets to be serviced for + * that end point before moving to the next end point. It is only for non-periodic + * end points. When Scatter/Gather DMA mode is disabled, this field isreserved. and + * reads 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------ + * ALT_USB_DEV_DCTL_GMC_E_NOTVALID | 0x0 | Invalid + * ALT_USB_DEV_DCTL_GMC_E_ONEPKT | 0x1 | 1 packet + * ALT_USB_DEV_DCTL_GMC_E_TWOPKT | 0x2 | 2 packets + * ALT_USB_DEV_DCTL_GMC_E_THREEPKT | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_GMC + * + * Invalid + */ +#define ALT_USB_DEV_DCTL_GMC_E_NOTVALID 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_GMC + * + * 1 packet + */ +#define ALT_USB_DEV_DCTL_GMC_E_ONEPKT 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_GMC + * + * 2 packets + */ +#define ALT_USB_DEV_DCTL_GMC_E_TWOPKT 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_GMC + * + * 3 packets + */ +#define ALT_USB_DEV_DCTL_GMC_E_THREEPKT 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GMC register field. */ +#define ALT_USB_DEV_DCTL_GMC_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GMC register field. */ +#define ALT_USB_DEV_DCTL_GMC_MSB 14 +/* The width in bits of the ALT_USB_DEV_DCTL_GMC register field. */ +#define ALT_USB_DEV_DCTL_GMC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DCTL_GMC register field value. */ +#define ALT_USB_DEV_DCTL_GMC_SET_MSK 0x00006000 +/* The mask used to clear the ALT_USB_DEV_DCTL_GMC register field value. */ +#define ALT_USB_DEV_DCTL_GMC_CLR_MSK 0xffff9fff +/* The reset value of the ALT_USB_DEV_DCTL_GMC register field. */ +#define ALT_USB_DEV_DCTL_GMC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_GMC field value from a register. */ +#define ALT_USB_DEV_DCTL_GMC_GET(value) (((value) & 0x00006000) >> 13) +/* Produces a ALT_USB_DEV_DCTL_GMC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_GMC_SET(value) (((value) << 13) & 0x00006000) + +/* + * Field : Ignore Frame number for Isochronous Endpoints - ignrfrmnum + * + * Do NOT program IgnrFrmNum bit to 1'b1 when the core is operating in threshold + * mode. When Scatter/Gather DMA mode is enabled this feature is not applicable to + * High Speed, High bandwidth transfers. When this bit is enabled, there must be + * only one packet per descriptor. In Scatter/Gather DMA mode, if this bit is + * enabled, the packets are not flushed when a ISOC IN token is received for an + * elapsed frame. When Scatter/Gather DMA mode is disabled, this field is used by + * the application to enable periodic transfer interrupt. The application can + * program periodic endpoint transfers for multiple (micro)frames. 0: periodic + * transfer interrupt feature is disabled, application needs to program transfers + * for periodic endpoints every (micro)frame 1: periodic transfer interrupt + * feature is enabled, application can program transfers for multiple (micro)frames + * for periodic endpoints. In non Scatter/Gather DMA mode the application will + * receive transfer complete interrupt after transfers for multiple (micro)frames + * are completed. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------------------- + * ALT_USB_DEV_DCTL_IGNRFRMNUM_E_DISD | 0x0 | The core transmits the packets only in the frame + * : | | number in which they are intended to be + * : | | transmitted + * ALT_USB_DEV_DCTL_IGNRFRMNUM_E_END | 0x1 | The core ignores the frame number, sending + * : | | packets immediately as the packets are ready + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_IGNRFRMNUM + * + * The core transmits the packets only in the frame number in which they are + * intended to be transmitted + */ +#define ALT_USB_DEV_DCTL_IGNRFRMNUM_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_IGNRFRMNUM + * + * The core ignores the frame number, sending packets immediately as the packets + * are ready + */ +#define ALT_USB_DEV_DCTL_IGNRFRMNUM_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */ +#define ALT_USB_DEV_DCTL_IGNRFRMNUM_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */ +#define ALT_USB_DEV_DCTL_IGNRFRMNUM_MSB 15 +/* The width in bits of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */ +#define ALT_USB_DEV_DCTL_IGNRFRMNUM_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_IGNRFRMNUM register field value. */ +#define ALT_USB_DEV_DCTL_IGNRFRMNUM_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DCTL_IGNRFRMNUM register field value. */ +#define ALT_USB_DEV_DCTL_IGNRFRMNUM_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */ +#define ALT_USB_DEV_DCTL_IGNRFRMNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_IGNRFRMNUM field value from a register. */ +#define ALT_USB_DEV_DCTL_IGNRFRMNUM_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DCTL_IGNRFRMNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_IGNRFRMNUM_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : NAK on Babble Error - nakonbble + * + * Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for + * the endpoint on which babble is received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DCTL_NAKONBBLE_E_DISD | 0x0 | Disable NAK on Babble Error + * ALT_USB_DEV_DCTL_NAKONBBLE_E_END | 0x1 | NAK on Babble Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_NAKONBBLE + * + * Disable NAK on Babble Error + */ +#define ALT_USB_DEV_DCTL_NAKONBBLE_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DCTL_NAKONBBLE + * + * NAK on Babble Error + */ +#define ALT_USB_DEV_DCTL_NAKONBBLE_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */ +#define ALT_USB_DEV_DCTL_NAKONBBLE_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */ +#define ALT_USB_DEV_DCTL_NAKONBBLE_MSB 16 +/* The width in bits of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */ +#define ALT_USB_DEV_DCTL_NAKONBBLE_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DCTL_NAKONBBLE register field value. */ +#define ALT_USB_DEV_DCTL_NAKONBBLE_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DCTL_NAKONBBLE register field value. */ +#define ALT_USB_DEV_DCTL_NAKONBBLE_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */ +#define ALT_USB_DEV_DCTL_NAKONBBLE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DCTL_NAKONBBLE field value from a register. */ +#define ALT_USB_DEV_DCTL_NAKONBBLE_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DCTL_NAKONBBLE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DCTL_NAKONBBLE_SET(value) (((value) << 16) & 0x00010000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DCTL. + */ +struct ALT_USB_DEV_DCTL_s +{ + uint32_t rmtwkupsig : 1; /* Remote Wakeup Signaling */ + uint32_t sftdiscon : 1; /* Soft Disconnect */ + const uint32_t gnpinnaksts : 1; /* Global Non-periodic IN NAK Status */ + const uint32_t goutnaksts : 1; /* Global OUT NAK Status */ + uint32_t tstctl : 3; /* Test Control */ + uint32_t sgnpinnak : 1; /* Set Global Non-periodic IN NAK */ + uint32_t CGNPInNak : 1; /* Clear Global Non-periodic IN NAK */ + uint32_t sgoutnak : 1; /* Set Global OUT NAK */ + uint32_t cgoutnak : 1; /* Clear Global OUT NAK */ + uint32_t pwronprgdone : 1; /* Power-On Programming Done */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t gmc : 2; /* Global Multi Count */ + uint32_t ignrfrmnum : 1; /* Ignore Frame number for Isochronous Endpoints */ + uint32_t nakonbble : 1; /* NAK on Babble Error */ + uint32_t : 15; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DCTL. */ +typedef volatile struct ALT_USB_DEV_DCTL_s ALT_USB_DEV_DCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DCTL register from the beginning of the component. */ +#define ALT_USB_DEV_DCTL_OFST 0x4 +/* The address of the ALT_USB_DEV_DCTL register. */ +#define ALT_USB_DEV_DCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DCTL_OFST)) + +/* + * Register : Device Status Register - dsts + * + * This register indicates the status of the core with respect to USB-related + * events. It must be read on interrupts from Device All Interrupts (DAINT) + * register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------------- + * [0] | R | 0x0 | Suspend Status + * [2:1] | R | 0x1 | Enumerated Speed + * [3] | R | 0x0 | Erratic Error + * [7:4] | ??? | 0x0 | *UNDEFINED* + * [21:8] | R | 0x0 | Frame or Microframe Number of the Received SOF + * [31:22] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Suspend Status - suspsts + * + * In Device mode, this bit is Set as long as a Suspend condition is detected on + * the USB. The core enters the Suspended state when there is no activity on the + * phy_line_state_i signal for an extended period of time. The core comes out of + * the suspend: + * + * * When there is any activity on the phy_line_state_i signal + * + * * When the application writes to the Remote Wakeup Signaling bit in the Device + * Control register (DCTL.RmtWkUpSig). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:----------------- + * ALT_USB_DEV_DSTS_SUSPSTS_E_INACT | 0x0 | No suspend state + * ALT_USB_DEV_DSTS_SUSPSTS_E_ACT | 0x1 | Suspend state + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DSTS_SUSPSTS + * + * No suspend state + */ +#define ALT_USB_DEV_DSTS_SUSPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DSTS_SUSPSTS + * + * Suspend state + */ +#define ALT_USB_DEV_DSTS_SUSPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_SUSPSTS register field. */ +#define ALT_USB_DEV_DSTS_SUSPSTS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_SUSPSTS register field. */ +#define ALT_USB_DEV_DSTS_SUSPSTS_MSB 0 +/* The width in bits of the ALT_USB_DEV_DSTS_SUSPSTS register field. */ +#define ALT_USB_DEV_DSTS_SUSPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DSTS_SUSPSTS register field value. */ +#define ALT_USB_DEV_DSTS_SUSPSTS_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DSTS_SUSPSTS register field value. */ +#define ALT_USB_DEV_DSTS_SUSPSTS_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DSTS_SUSPSTS register field. */ +#define ALT_USB_DEV_DSTS_SUSPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DSTS_SUSPSTS field value from a register. */ +#define ALT_USB_DEV_DSTS_SUSPSTS_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DSTS_SUSPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DSTS_SUSPSTS_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Enumerated Speed - enumspd + * + * Indicates the speed at which the otg core has come up after speed detection + * through a chirp sequence. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060 | 0x0 | High speed (PHY clock is running at 30 or 60 + * : | | MHz) + * ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060 | 0x1 | Full speed (PHY clock is running at 30 or 60 + * : | | MHz) + * ALT_USB_DEV_DSTS_ENUMSPD_E_LS6 | 0x2 | Low speed (PHY clock is running at 6 MHz) + * ALT_USB_DEV_DSTS_ENUMSPD_E_FS48 | 0x3 | Full speed (PHY clock is running at 48 MHz) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD + * + * High speed (PHY clock is running at 30 or 60 MHz) + */ +#define ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD + * + * Full speed (PHY clock is running at 30 or 60 MHz) + */ +#define ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD + * + * Low speed (PHY clock is running at 6 MHz) + */ +#define ALT_USB_DEV_DSTS_ENUMSPD_E_LS6 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD + * + * Full speed (PHY clock is running at 48 MHz) + */ +#define ALT_USB_DEV_DSTS_ENUMSPD_E_FS48 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_ENUMSPD register field. */ +#define ALT_USB_DEV_DSTS_ENUMSPD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_ENUMSPD register field. */ +#define ALT_USB_DEV_DSTS_ENUMSPD_MSB 2 +/* The width in bits of the ALT_USB_DEV_DSTS_ENUMSPD register field. */ +#define ALT_USB_DEV_DSTS_ENUMSPD_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DSTS_ENUMSPD register field value. */ +#define ALT_USB_DEV_DSTS_ENUMSPD_SET_MSK 0x00000006 +/* The mask used to clear the ALT_USB_DEV_DSTS_ENUMSPD register field value. */ +#define ALT_USB_DEV_DSTS_ENUMSPD_CLR_MSK 0xfffffff9 +/* The reset value of the ALT_USB_DEV_DSTS_ENUMSPD register field. */ +#define ALT_USB_DEV_DSTS_ENUMSPD_RESET 0x1 +/* Extracts the ALT_USB_DEV_DSTS_ENUMSPD field value from a register. */ +#define ALT_USB_DEV_DSTS_ENUMSPD_GET(value) (((value) & 0x00000006) >> 1) +/* Produces a ALT_USB_DEV_DSTS_ENUMSPD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DSTS_ENUMSPD_SET(value) (((value) << 1) & 0x00000006) + +/* + * Field : Erratic Error - errticerr + * + * The core sets this bit to report any erratic errors (phy_rxvalid_i/phy_rxvldh_i + * or phy_rxactive_i is asserted for at least 2 ms, due to PHY error) seen on the + * UTMI+ . Due to erratic errors, the otg core goes into Suspended state and an + * interrupt is generated to the application with Early Suspend bit of the Core + * Interrupt register (GINTSTS.ErlySusp). If the early suspend is asserted due to + * an erratic error, the application can only perform a soft disconnect recover. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------- + * ALT_USB_DEV_DSTS_ERRTICERR_E_INACT | 0x0 | No Erratic Error + * ALT_USB_DEV_DSTS_ERRTICERR_E_ACT | 0x1 | Erratic Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DSTS_ERRTICERR + * + * No Erratic Error + */ +#define ALT_USB_DEV_DSTS_ERRTICERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DSTS_ERRTICERR + * + * Erratic Error + */ +#define ALT_USB_DEV_DSTS_ERRTICERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_ERRTICERR register field. */ +#define ALT_USB_DEV_DSTS_ERRTICERR_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_ERRTICERR register field. */ +#define ALT_USB_DEV_DSTS_ERRTICERR_MSB 3 +/* The width in bits of the ALT_USB_DEV_DSTS_ERRTICERR register field. */ +#define ALT_USB_DEV_DSTS_ERRTICERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DSTS_ERRTICERR register field value. */ +#define ALT_USB_DEV_DSTS_ERRTICERR_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DSTS_ERRTICERR register field value. */ +#define ALT_USB_DEV_DSTS_ERRTICERR_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DSTS_ERRTICERR register field. */ +#define ALT_USB_DEV_DSTS_ERRTICERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DSTS_ERRTICERR field value from a register. */ +#define ALT_USB_DEV_DSTS_ERRTICERR_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DSTS_ERRTICERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DSTS_ERRTICERR_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : Frame or Microframe Number of the Received SOF - soffn + * + * When the core is operating at high speed, this field contains a microframe + * number. When the core is operating at full or low speed, this field contains a + * Frame number. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_SOFFN register field. */ +#define ALT_USB_DEV_DSTS_SOFFN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_SOFFN register field. */ +#define ALT_USB_DEV_DSTS_SOFFN_MSB 21 +/* The width in bits of the ALT_USB_DEV_DSTS_SOFFN register field. */ +#define ALT_USB_DEV_DSTS_SOFFN_WIDTH 14 +/* The mask used to set the ALT_USB_DEV_DSTS_SOFFN register field value. */ +#define ALT_USB_DEV_DSTS_SOFFN_SET_MSK 0x003fff00 +/* The mask used to clear the ALT_USB_DEV_DSTS_SOFFN register field value. */ +#define ALT_USB_DEV_DSTS_SOFFN_CLR_MSK 0xffc000ff +/* The reset value of the ALT_USB_DEV_DSTS_SOFFN register field. */ +#define ALT_USB_DEV_DSTS_SOFFN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DSTS_SOFFN field value from a register. */ +#define ALT_USB_DEV_DSTS_SOFFN_GET(value) (((value) & 0x003fff00) >> 8) +/* Produces a ALT_USB_DEV_DSTS_SOFFN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DSTS_SOFFN_SET(value) (((value) << 8) & 0x003fff00) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DSTS. + */ +struct ALT_USB_DEV_DSTS_s +{ + const uint32_t suspsts : 1; /* Suspend Status */ + const uint32_t enumspd : 2; /* Enumerated Speed */ + const uint32_t errticerr : 1; /* Erratic Error */ + uint32_t : 4; /* *UNDEFINED* */ + const uint32_t soffn : 14; /* Frame or Microframe Number of the Received SOF */ + uint32_t : 10; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DSTS. */ +typedef volatile struct ALT_USB_DEV_DSTS_s ALT_USB_DEV_DSTS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DSTS register from the beginning of the component. */ +#define ALT_USB_DEV_DSTS_OFST 0x8 +/* The address of the ALT_USB_DEV_DSTS register. */ +#define ALT_USB_DEV_DSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DSTS_OFST)) + +/* + * Register : Device IN Endpoint Common Interrupt Mask Register - diepmsk + * + * This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) + * registers for all endpoints to generate an interrupt per IN endpoint. The IN + * endpoint interrupt for a specific status in the DIEPINTn register can be masked + * by writing to the corresponding bit in this register. Status bits are masked by + * default. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------- + * [0] | RW | 0x0 | Transfer Completed Interrupt Mask + * [1] | RW | 0x0 | Endpoint Disabled Interrupt Mask + * [2] | RW | 0x0 | AHB Error Mask + * [3] | RW | 0x0 | Timeout Condition Mask + * [4] | RW | 0x0 | IN Token Received When TxFIFO Empty Mask + * [5] | RW | 0x0 | IN Token received with EP Mismatch Mask + * [6] | RW | 0x0 | IN Endpoint NAK Effective Mask + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | Fifo Underrun Mask + * [9] | RW | 0x0 | BNA interrupt Mask + * [12:10] | ??? | 0x0 | *UNDEFINED* + * [13] | RW | 0x0 | NAK interrupt Mask + * [31:14] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt Mask - xfercomplmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------- + * ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_MSK | 0x0 | Mask Transfer Completed Interrupt + * ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_NOMSK | 0x1 | No Mask Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK + * + * Mask Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK + * + * No Mask Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt Mask - epdisbldmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_MSK | 0x0 | Mask Endpoint Disabled Interrupt + * ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_NOMSK | 0x1 | No Mask Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_EPDISBLDMSK + * + * Mask Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_EPDISBLDMSK + * + * No Mask Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK field value from a register. */ +#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_MSK | 0x0 | Mask AHB Error Interrupt + * ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_NOMSK | 0x1 | No Mask AHB Error Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_AHBERRMSK + * + * Mask AHB Error Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_AHBERRMSK + * + * No Mask AHB Error Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPMSK_AHBERRMSK field value from a register. */ +#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition Mask - timeoutmsk + * + * Non-isochronous endpoints + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPMSK_TMOMSK_E_MSK | 0x0 | Mask Timeout Condition Interrupt + * ALT_USB_DEV_DIEPMSK_TMOMSK_E_NOMSK | 0x1 | No Mask Timeout Condition Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TMOMSK + * + * Mask Timeout Condition Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_TMOMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TMOMSK + * + * No Mask Timeout Condition Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_TMOMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_TMOMSK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_TMOMSK_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_TMOMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPMSK_TMOMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_TMOMSK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPMSK_TMOMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_TMOMSK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_TMOMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPMSK_TMOMSK field value from a register. */ +#define ALT_USB_DEV_DIEPMSK_TMOMSK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPMSK_TMOMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPMSK_TMOMSK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO Empty Mask - intkntxfempmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------------------- + * ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_MSK | 0x0 | Mask IN Token Received When TxFIFO Empty + * : | | Interrupt + * ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_NOMSK | 0x1 | No Mask IN Token Received When TxFIFO Empty + * : | | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK + * + * Mask IN Token Received When TxFIFO Empty Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK + * + * No Mask IN Token Received When TxFIFO Empty Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK field value from a register. */ +#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token received with EP Mismatch Mask - intknepmismsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_MSK | 0x0 | Mask IN Token received with EP Mismatch + * : | | Interrupt + * ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_NOMSK | 0x1 | No Mask IN Token received with EP Mismatch + * : | | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK + * + * Mask IN Token received with EP Mismatch Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK + * + * No Mask IN Token received with EP Mismatch Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK field value from a register. */ +#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective Mask - inepnakeffmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:-------------------------------------------- + * ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_MSK | 0x0 | Mask IN Endpoint NAK Effective Interrupt + * ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_NOMSK | 0x1 | No Mask IN Endpoint NAK Effective Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK + * + * Mask IN Endpoint NAK Effective Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK + * + * No Mask IN Endpoint NAK Effective Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK field value from a register. */ +#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Fifo Underrun Mask - txfifoundrnmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------- + * ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_MSK | 0x0 | Mask Fifo Underrun Interrupt + * ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_NOMSK | 0x1 | No Mask Fifo Underrun Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK + * + * Mask Fifo Underrun Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK + * + * No Mask Fifo Underrun Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK field value from a register. */ +#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA interrupt Mask - bnainintrmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------- + * ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_MSK | 0x0 | Mask BNA Interrupt + * ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_NOMSK | 0x1 | No Mask BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_BNAININTRMSK + * + * Mask BNA Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_BNAININTRMSK + * + * No Mask BNA Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPMSK_BNAININTRMSK field value from a register. */ +#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : NAK interrupt Mask - nakmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------- + * ALT_USB_DEV_DIEPMSK_NAKMSK_E_MSK | 0x0 | Mask NAK Interrupt + * ALT_USB_DEV_DIEPMSK_NAKMSK_E_NOMSK | 0x1 | No Mask NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_NAKMSK + * + * Mask NAK Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_NAKMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPMSK_NAKMSK + * + * No Mask NAK Interrupt + */ +#define ALT_USB_DEV_DIEPMSK_NAKMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_NAKMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_NAKMSK_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_NAKMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPMSK_NAKMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_NAKMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPMSK_NAKMSK register field value. */ +#define ALT_USB_DEV_DIEPMSK_NAKMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */ +#define ALT_USB_DEV_DIEPMSK_NAKMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPMSK_NAKMSK field value from a register. */ +#define ALT_USB_DEV_DIEPMSK_NAKMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPMSK_NAKMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPMSK_NAKMSK_SET(value) (((value) << 13) & 0x00002000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPMSK. + */ +struct ALT_USB_DEV_DIEPMSK_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Interrupt Mask */ + uint32_t epdisbldmsk : 1; /* Endpoint Disabled Interrupt Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t timeoutmsk : 1; /* Timeout Condition Mask */ + uint32_t intkntxfempmsk : 1; /* IN Token Received When TxFIFO Empty Mask */ + uint32_t intknepmismsk : 1; /* IN Token received with EP Mismatch Mask */ + uint32_t inepnakeffmsk : 1; /* IN Endpoint NAK Effective Mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t txfifoundrnmsk : 1; /* Fifo Underrun Mask */ + uint32_t bnainintrmsk : 1; /* BNA interrupt Mask */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t nakmsk : 1; /* NAK interrupt Mask */ + uint32_t : 18; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPMSK. */ +typedef volatile struct ALT_USB_DEV_DIEPMSK_s ALT_USB_DEV_DIEPMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPMSK register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPMSK_OFST 0x10 +/* The address of the ALT_USB_DEV_DIEPMSK register. */ +#define ALT_USB_DEV_DIEPMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPMSK_OFST)) + +/* + * Register : Device OUT Endpoint Common Interrupt Mask Register - doepmsk + * + * This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) + * registers for all endpoints to generate an interrupt per OUT endpoint. The OUT + * endpoint interrupt for a specific status in the DOEPINTn register can be masked + * by writing into the corresponding bit in this register. Status bits are masked + * by default + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------------------------- + * [0] | RW | 0x0 | Transfer Completed Interrupt Mask + * [1] | RW | 0x0 | Endpoint Disabled Interrupt Mask + * [2] | RW | 0x0 | AHB Error Mask + * [3] | RW | 0x0 | SETUP Phase Done Mask + * [4] | RW | 0x0 | OUT Token Received when Endpoint Disabled Mask + * [5] | ??? | 0x0 | *UNDEFINED* + * [6] | RW | 0x0 | Back-to-Back SETUP Packets Received Mask + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | RW | 0x0 | OUT Packet Error Mask + * [9] | RW | 0x0 | BNA interrupt Mask + * [11:10] | ??? | 0x0 | *UNDEFINED* + * [12] | RW | 0x0 | Babble Error interrupt Mask + * [13] | RW | 0x0 | NAK interrupt Mask + * [14] | RW | 0x0 | NYET interrupt Mask + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt Mask - xfercomplmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------- + * ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_MSK | 0x0 | Mask Transfer Completed Interrupt + * ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_NOMSK | 0x1 | No Mask Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK + * + * Mask Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK + * + * No Mask Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt Mask - epdisbldmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_MSK | 0x0 | Mask Endpoint Disabled Interrupt + * ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_NOMSK | 0x1 | No Mask Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_EPDISBLDMSK + * + * Mask Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_EPDISBLDMSK + * + * No Mask Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error Mask - ahberrmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_MSK | 0x0 | Mask AHB Error Interrupt + * ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_NOMSK | 0x1 | No Mask AHB Error Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_AHBERRMSK + * + * Mask AHB Error Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_AHBERRMSK + * + * No Mask AHB Error Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_AHBERRMSK field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done Mask - setupmsk + * + * Applies to control endpoints only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------------------- + * ALT_USB_DEV_DOEPMSK_SETUPMSK_E_MSK | 0x0 | Mask SETUP Phase Done Interrupt + * ALT_USB_DEV_DOEPMSK_SETUPMSK_E_NOMSK | 0x1 | No Mask SETUP Phase Done Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_SETUPMSK + * + * Mask SETUP Phase Done Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_SETUPMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_SETUPMSK + * + * No Mask SETUP Phase Done Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_SETUPMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_SETUPMSK_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_SETUPMSK_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_SETUPMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_SETUPMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_SETUPMSK_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_SETUPMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_SETUPMSK_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_SETUPMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_SETUPMSK field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_SETUPMSK_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPMSK_SETUPMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_SETUPMSK_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received when Endpoint Disabled Mask - outtknepdismsk + * + * Applies to control OUT endpoints only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:----------------------------------------------- + * ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_MSK | 0x0 | Mask OUT Token Received when Endpoint Disabled + * : | | Interrupt + * ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_NOMSK | 0x1 | No Mask OUT Token Received when Endpoint + * : | | Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK + * + * Mask OUT Token Received when Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK + * + * No Mask OUT Token Received when Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Back-to-Back SETUP Packets Received Mask - back2backsetup + * + * Applies to control OUT endpoints only. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------------------------------- + * ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_MSK | 0x0 | Mask Back-to-Back SETUP Packets Received + * : | | Interrupt + * ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_NOMSK | 0x1 | No Mask Back-to-Back SETUP Packets Received + * : | | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP + * + * Mask Back-to-Back SETUP Packets Received Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP + * + * No Mask Back-to-Back SETUP Packets Received Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error Mask - outpkterrmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:----------------------------------- + * ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_MSK | 0x0 | Mask OUT Packet Error Interrupt + * ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_NOMSK | 0x1 | No Mask OUT Packet Error Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK + * + * Mask OUT Packet Error Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK + * + * No Mask OUT Packet Error Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA interrupt Mask - bnaoutintrmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------- + * ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_MSK | 0x0 | Mask BNA Interrupt + * ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_NOMSK | 0x1 | No Mask BNA Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK + * + * Mask BNA Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK + * + * No Mask BNA Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Babble Error interrupt Mask - bbleerrmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------- + * ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_MSK | 0x0 | Mask Babble Error Interrupt + * ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_NOMSK | 0x1 | No Mask Babble Error Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BBLEERRMSK + * + * Mask Babble Error Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BBLEERRMSK + * + * No Mask Babble Error Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_BBLEERRMSK field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK interrupt Mask - nakmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------- + * ALT_USB_DEV_DOEPMSK_NAKMSK_E_MSK | 0x0 | Mask NAK Interrupt + * ALT_USB_DEV_DOEPMSK_NAKMSK_E_NOMSK | 0x1 | No Mask NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NAKMSK + * + * Mask NAK Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_NAKMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NAKMSK + * + * No Mask NAK Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_NAKMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_NAKMSK_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_NAKMSK_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_NAKMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_NAKMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_NAKMSK_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_NAKMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_NAKMSK_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_NAKMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_NAKMSK field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_NAKMSK_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPMSK_NAKMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_NAKMSK_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET interrupt Mask - nyetmsk + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPMSK_NYETMSK_E_MSK | 0x0 | Mask NYET Interrupt + * ALT_USB_DEV_DOEPMSK_NYETMSK_E_NOMSK | 0x1 | No Mask NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NYETMSK + * + * Mask NYET Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_NYETMSK_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NYETMSK + * + * No Mask NYET Interrupt + */ +#define ALT_USB_DEV_DOEPMSK_NYETMSK_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_NYETMSK_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_NYETMSK_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_NYETMSK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPMSK_NYETMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_NYETMSK_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPMSK_NYETMSK register field value. */ +#define ALT_USB_DEV_DOEPMSK_NYETMSK_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */ +#define ALT_USB_DEV_DOEPMSK_NYETMSK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPMSK_NYETMSK field value from a register. */ +#define ALT_USB_DEV_DOEPMSK_NYETMSK_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPMSK_NYETMSK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPMSK_NYETMSK_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPMSK. + */ +struct ALT_USB_DEV_DOEPMSK_s +{ + uint32_t xfercomplmsk : 1; /* Transfer Completed Interrupt Mask */ + uint32_t epdisbldmsk : 1; /* Endpoint Disabled Interrupt Mask */ + uint32_t ahberrmsk : 1; /* AHB Error Mask */ + uint32_t setupmsk : 1; /* SETUP Phase Done Mask */ + uint32_t outtknepdismsk : 1; /* OUT Token Received when Endpoint Disabled Mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received Mask */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t outpkterrmsk : 1; /* OUT Packet Error Mask */ + uint32_t bnaoutintrmsk : 1; /* BNA interrupt Mask */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t bbleerrmsk : 1; /* Babble Error interrupt Mask */ + uint32_t nakmsk : 1; /* NAK interrupt Mask */ + uint32_t nyetmsk : 1; /* NYET interrupt Mask */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPMSK. */ +typedef volatile struct ALT_USB_DEV_DOEPMSK_s ALT_USB_DEV_DOEPMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPMSK register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPMSK_OFST 0x14 +/* The address of the ALT_USB_DEV_DOEPMSK register. */ +#define ALT_USB_DEV_DOEPMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPMSK_OFST)) + +/* + * Register : Device All Endpoints Interrupt Register - daint + * + * When a significant event occurs on an endpoint, a Device All Endpoints Interrupt + * register interrupts the application using the Device OUT Endpoints Interrupt bit + * or Device IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). This is shown in Figure 5-2. + * There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT + * endpoints and 16 bits for IN endpoints. for a bidirectional endpoint, the + * corresponding IN and OUT interrupt bits are used. Bits in this register are set + * and cleared when the application sets and clears bits in the corresponding + * Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:------------------------------ + * [0] | R | 0x0 | IN Endpoint 0 Interrupt Bit + * [1] | R | 0x0 | IN Endpoint 1 Interrupt Bit + * [2] | R | 0x0 | IN Endpoint 2 Interrupt Bit + * [3] | R | 0x0 | IN Endpoint 3 Interrupt Bit + * [4] | R | 0x0 | IN Endpoint 4 Interrupt Bit + * [5] | R | 0x0 | IN Endpoint 5 Interrupt Bit + * [6] | R | 0x0 | IN Endpoint 6 Interrupt Bit + * [7] | R | 0x0 | IN Endpoint 7 Interrupt Bit + * [8] | R | 0x0 | IN Endpoint 8 Interrupt Bit + * [9] | R | 0x0 | IN Endpoint 9 Interrupt Bit + * [10] | R | 0x0 | IN Endpoint 10 Interrupt Bit + * [11] | R | 0x0 | IN Endpoint 11 Interrupt Bit + * [12] | R | 0x0 | IN Endpoint 12 Interrupt Bit + * [13] | R | 0x0 | IN Endpoint 13 Interrupt Bit + * [14] | R | 0x0 | IN Endpoint 14 Interrupt Bit + * [15] | R | 0x0 | IN Endpoint 15 Interrupt Bit + * [16] | R | 0x0 | OUT Endpoint 0 Interrupt Bit + * [17] | R | 0x0 | OUT Endpoint 1 Interrupt Bi + * [18] | R | 0x0 | OUT Endpoint 2 Interrupt Bit + * [19] | R | 0x0 | OUT Endpoint 3 Interrupt Bit + * [20] | R | 0x0 | OUT Endpoint 4 Interrupt Bit + * [21] | R | 0x0 | OUT Endpoint 5 Interrupt Bit + * [22] | R | 0x0 | OUT Endpoint 6 Interrupt Bi + * [23] | R | 0x0 | OUT Endpoint 7 Interrupt Bit + * [24] | R | 0x0 | OUT Endpoint 8 Interrupt Bit + * [25] | R | 0x0 | OUT Endpoint 9 Interrupt Bit + * [26] | R | 0x0 | OUT Endpoint 10 Interrupt Bit + * [27] | R | 0x0 | OUT Endpoint 11 Interrupt Bit + * [28] | R | 0x0 | OUT Endpoint 12 Interrupt Bit + * [29] | R | 0x0 | OUT Endpoint 13 Interrupt Bit + * [30] | R | 0x0 | OUT Endpoint 14 Interrupt Bi + * [31] | R | 0x0 | OUT Endpoint 15 Interrupt Bit + * + */ +/* + * Field : IN Endpoint 0 Interrupt Bit - inepint0 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------ + * ALT_USB_DEV_DAINT_INEPINT0_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT0_E_ACT | 0x1 | IN Endpoint 0 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT0 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT0_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT0 + * + * IN Endpoint 0 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT0_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT0 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT0 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT0_MSB 0 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT0 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT0_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT0 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT0 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT0 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT0_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT0 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DAINT_INEPINT0 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IN Endpoint 1 Interrupt Bit - inepint1 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------ + * ALT_USB_DEV_DAINT_INEPINT1_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT1_E_ACT | 0x1 | IN Endpoint 1 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT1 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT1_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT1 + * + * IN Endpoint 1 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT1_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT1 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT1 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT1_MSB 1 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT1 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT1_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT1 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT1 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT1 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT1_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT1 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DAINT_INEPINT1 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IN Endpoint 2 Interrupt Bit - inepint2 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------ + * ALT_USB_DEV_DAINT_INEPINT2_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT2_E_ACT | 0x1 | IN Endpoint 2 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT2 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT2_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT2 + * + * IN Endpoint 2 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT2_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT2 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT2 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT2_MSB 2 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT2 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT2_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT2 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT2 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT2 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT2_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT2 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DAINT_INEPINT2 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IN Endpoint 3 Interrupt Bit - inepint3 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------ + * ALT_USB_DEV_DAINT_INEPINT3_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT3_E_ACT | 0x1 | IN Endpoint 3 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT3 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT3_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT3 + * + * IN Endpoint 3 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT3_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT3 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT3 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT3_MSB 3 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT3 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT3_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT3 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT3 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT3 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT3_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT3 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DAINT_INEPINT3 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Endpoint 4 Interrupt Bit - inepint4 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------ + * ALT_USB_DEV_DAINT_INEPINT4_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT4_E_ACT | 0x1 | IN Endpoint 4 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT4 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT4_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT4 + * + * IN Endpoint 4 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT4_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT4 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT4 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT4_MSB 4 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT4 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT4_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT4 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT4 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT4_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT4 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT4_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT4 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DAINT_INEPINT4 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Endpoint 5 Interrupt Bit - inepint5 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------ + * ALT_USB_DEV_DAINT_INEPINT5_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT5_E_ACT | 0x1 | IN Endpoint 5 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT5 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT5_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT5 + * + * IN Endpoint 5 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT5_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT5 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT5 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT5_MSB 5 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT5 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT5_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT5 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT5 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT5 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT5_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT5 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DAINT_INEPINT5 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint 6 Interrupt Bit - inepint6 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------ + * ALT_USB_DEV_DAINT_INEPINT6_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT6_E_ACT | 0x1 | IN Endpoint 6 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT6 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT6_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT6 + * + * IN Endpoint 6 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT6_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT6 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT6 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT6_MSB 6 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT6 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT6_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT6 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT6 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT6 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT6_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT6 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DAINT_INEPINT6 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IN Endpoint 7 Interrupt Bit - inepint7 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------ + * ALT_USB_DEV_DAINT_INEPINT7_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT7_E_ACT | 0x1 | IN Endpoint 7 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT7 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT7_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT7 + * + * IN Endpoint 7 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT7_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT7 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT7 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT7_MSB 7 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT7 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT7_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT7 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT7 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT7 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT7_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT7 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DAINT_INEPINT7 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : IN Endpoint 8 Interrupt Bit - inepint8 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------ + * ALT_USB_DEV_DAINT_INEPINT8_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT8_E_ACT | 0x1 | IN Endpoint 8 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT8 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT8_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT8 + * + * IN Endpoint 8 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT8_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT8 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT8 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT8_MSB 8 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT8 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT8_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT8 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT8 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT8 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT8_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT8 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DAINT_INEPINT8 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : IN Endpoint 9 Interrupt Bit - inepint9 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------ + * ALT_USB_DEV_DAINT_INEPINT9_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT9_E_ACT | 0x1 | IN Endpoint 9 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT9 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT9_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT9 + * + * IN Endpoint 9 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT9_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT9 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT9 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT9_MSB 9 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT9 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT9_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT9 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT9 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT9 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT9_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT9 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DAINT_INEPINT9 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : IN Endpoint 10 Interrupt Bit - inepint10 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_INEPINT10_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT10_E_ACT | 0x1 | IN Endpoint 10 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT10 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT10_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT10 + * + * IN Endpoint 10 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT10_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT10 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT10 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT10_MSB 10 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT10 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT10_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT10 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT10 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT10 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT10_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT10 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_DEV_DAINT_INEPINT10 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : IN Endpoint 11 Interrupt Bit - inepint11 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_INEPINT11_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT11_E_ACT | 0x1 | IN Endpoint 11 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT11 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT11_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT11 + * + * IN Endpoint 11 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT11_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT11 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT11 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT11_MSB 11 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT11 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT11_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT11 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT11 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT11 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT11_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT11 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DAINT_INEPINT11 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : IN Endpoint 12 Interrupt Bit - inepint12 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_INEPINT12_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT12_E_ACT | 0x1 | IN Endpoint 12 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT12 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT12_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT12 + * + * IN Endpoint 12 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT12_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT12 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT12 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT12_MSB 12 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT12 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT12_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT12 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT12 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT12_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT12 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT12_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT12 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DAINT_INEPINT12 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : IN Endpoint 13 Interrupt Bit - inepint13 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_INEPINT13_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT13_E_ACT | 0x1 | IN Endpoint 13 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT13 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT13_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT13 + * + * IN Endpoint 13 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT13_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT13 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT13 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT13_MSB 13 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT13 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT13_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT13 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT13 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT13 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT13_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT13 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DAINT_INEPINT13 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : IN Endpoint 14 Interrupt Bit - inepint14 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_INEPINT14_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT14_E_ACT | 0x1 | IN Endpoint 14 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT14 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT14_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT14 + * + * IN Endpoint 14 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT14_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT14 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT14 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT14_MSB 14 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT14 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT14_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT14 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT14 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT14 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT14_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT14 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DAINT_INEPINT14 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : IN Endpoint 15 Interrupt Bit - inepint15 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_INEPINT15_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_INEPINT15_E_ACT | 0x1 | IN Endpoint 15 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT15 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT15_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT15 + * + * IN Endpoint 15 Interrupt + */ +#define ALT_USB_DEV_DAINT_INEPINT15_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT15 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT15 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT15_MSB 15 +/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT15 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT15_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT15 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT15 register field value. */ +#define ALT_USB_DEV_DAINT_INEPINT15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DAINT_INEPINT15 register field. */ +#define ALT_USB_DEV_DAINT_INEPINT15_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_INEPINT15 field value from a register. */ +#define ALT_USB_DEV_DAINT_INEPINT15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DAINT_INEPINT15 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_INEPINT15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : OUT Endpoint 0 Interrupt Bit - outepint0 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT0_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT0_E_ACT | 0x1 | OUT Endpoint 0 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT0 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT0_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT0 + * + * OUT Endpoint 0 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT0_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT0_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT0_MSB 16 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT0_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT0 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT0_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT0 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT0_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT0_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT0 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT0_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT0 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT0_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : OUT Endpoint 1 Interrupt Bi - outepint1 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT1_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT1_E_ACT | 0x1 | OUT Endpoint 1 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT1 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT1_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT1 + * + * OUT Endpoint 1 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT1_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT1_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT1_MSB 17 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT1_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT1 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT1_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT1 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT1_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT1_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT1 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT1_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT1 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT1_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : OUT Endpoint 2 Interrupt Bit - outepint2 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT2_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT2_E_ACT | 0x1 | OUT Endpoint 2 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT2 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT2_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT2 + * + * OUT Endpoint 2 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT2_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT2_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT2_MSB 18 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT2_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT2 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT2_SET_MSK 0x00040000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT2 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT2_CLR_MSK 0xfffbffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT2_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT2 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT2_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT2 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT2_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : OUT Endpoint 3 Interrupt Bit - outepint3 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT3_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT3_E_ACT | 0x1 | OUT Endpoint 3 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT3 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT3_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT3 + * + * OUT Endpoint 3 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT3_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT3_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT3_MSB 19 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT3_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT3 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT3_SET_MSK 0x00080000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT3 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT3_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT3_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT3 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT3_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT3 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT3_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : OUT Endpoint 4 Interrupt Bit - outepint4 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT4_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT4_E_ACT | 0x1 | OUT Endpoint 4 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT4 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT4_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT4 + * + * OUT Endpoint 4 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT4_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT4_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT4_MSB 20 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT4_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT4 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT4_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT4 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT4_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT4_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT4 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT4_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT4 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT4_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : OUT Endpoint 5 Interrupt Bit - outepint5 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT5_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT5_E_ACT | 0x1 | OUT Endpoint 5 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT5 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT5_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT5 + * + * OUT Endpoint 5 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT5_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT5_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT5_MSB 21 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT5_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT5 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT5_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT5 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT5_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT5_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT5 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT5_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT5 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT5_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : OUT Endpoint 6 Interrupt Bi - outepint6 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT6_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT6_E_ACT | 0x1 | OUT Endpoint 6 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT6 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT6_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT6 + * + * OUT Endpoint 6 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT6_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT6_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT6_MSB 22 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT6_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT6 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT6_SET_MSK 0x00400000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT6 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT6_CLR_MSK 0xffbfffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT6_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT6 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT6_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT6 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT6_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : OUT Endpoint 7 Interrupt Bit - outepint7 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT7_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT7_E_ACT | 0x1 | OUT Endpoint 7 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT7 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT7_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT7 + * + * OUT Endpoint 7 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT7_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT7_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT7_MSB 23 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT7_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT7 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT7_SET_MSK 0x00800000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT7 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT7_CLR_MSK 0xff7fffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT7_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT7 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT7_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT7 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT7_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : OUT Endpoint 8 Interrupt Bit - outepint8 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT8_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT8_E_ACT | 0x1 | OUT Endpoint 8 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT8 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT8_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT8 + * + * OUT Endpoint 8 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT8_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT8_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT8_MSB 24 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT8_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT8 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT8_SET_MSK 0x01000000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT8 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT8_CLR_MSK 0xfeffffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT8_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT8 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT8_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT8 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT8_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : OUT Endpoint 9 Interrupt Bit - outepint9 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT9_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT9_E_ACT | 0x1 | OUT Endpoint 9 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT9 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT9_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT9 + * + * OUT Endpoint 9 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT9_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT9_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT9_MSB 25 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT9_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT9 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT9_SET_MSK 0x02000000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT9 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT9_CLR_MSK 0xfdffffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT9_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT9 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT9_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT9 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT9_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : OUT Endpoint 10 Interrupt Bit - outepint10 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT10_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT10_E_ACT | 0x1 | OUT Endpoint 10 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT10 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT10_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT10 + * + * OUT Endpoint 10 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT10_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT10_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT10_MSB 26 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT10_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT10 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT10_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT10 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT10_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT10_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT10 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT10_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT10 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT10_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : OUT Endpoint 11 Interrupt Bit - outepint11 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT11_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT11_E_ACT | 0x1 | OUT Endpoint 11 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT11 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT11_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT11 + * + * OUT Endpoint 11 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT11_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT11_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT11_MSB 27 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT11_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT11 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT11_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT11 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT11_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT11_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT11 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT11_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT11 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT11_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : OUT Endpoint 12 Interrupt Bit - outepint12 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT12_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT12_E_ACT | 0x1 | OUT Endpoint 12 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT12 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT12_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT12 + * + * OUT Endpoint 12 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT12_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT12_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT12_MSB 28 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT12_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT12 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT12_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT12 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT12_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT12_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT12 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT12_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT12 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT12_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : OUT Endpoint 13 Interrupt Bit - outepint13 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT13_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT13_E_ACT | 0x1 | OUT Endpoint 13 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT13 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT13_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT13 + * + * OUT Endpoint 13 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT13_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT13_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT13_MSB 29 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT13_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT13 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT13_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT13 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT13_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT13_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT13 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT13_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT13 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT13_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : OUT Endpoint 14 Interrupt Bi - outepint14 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT14_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT14_E_ACT | 0x1 | OUT Endpoint 14 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT14 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT14_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT14 + * + * OUT Endpoint 14 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT14_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT14_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT14_MSB 30 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT14_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT14 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT14_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT14 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT14_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT14_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT14 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT14_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT14 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT14_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : OUT Endpoint 15 Interrupt Bit - outepint15 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------------- + * ALT_USB_DEV_DAINT_OUTEPINT15_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DAINT_OUTEPINT15_E_ACT | 0x1 | OUT Endpoint 15 Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT15 + * + * No Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT15_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT15 + * + * OUT Endpoint 15 Interrupt + */ +#define ALT_USB_DEV_DAINT_OUTEPINT15_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT15_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT15_MSB 31 +/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT15_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT15 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT15_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT15 register field value. */ +#define ALT_USB_DEV_DAINT_OUTEPINT15_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */ +#define ALT_USB_DEV_DAINT_OUTEPINT15_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT15 field value from a register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT15_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DAINT_OUTEPINT15 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINT_OUTEPINT15_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DAINT. + */ +struct ALT_USB_DEV_DAINT_s +{ + const uint32_t inepint0 : 1; /* IN Endpoint 0 Interrupt Bit */ + const uint32_t inepint1 : 1; /* IN Endpoint 1 Interrupt Bit */ + const uint32_t inepint2 : 1; /* IN Endpoint 2 Interrupt Bit */ + const uint32_t inepint3 : 1; /* IN Endpoint 3 Interrupt Bit */ + const uint32_t inepint4 : 1; /* IN Endpoint 4 Interrupt Bit */ + const uint32_t inepint5 : 1; /* IN Endpoint 5 Interrupt Bit */ + const uint32_t inepint6 : 1; /* IN Endpoint 6 Interrupt Bit */ + const uint32_t inepint7 : 1; /* IN Endpoint 7 Interrupt Bit */ + const uint32_t inepint8 : 1; /* IN Endpoint 8 Interrupt Bit */ + const uint32_t inepint9 : 1; /* IN Endpoint 9 Interrupt Bit */ + const uint32_t inepint10 : 1; /* IN Endpoint 10 Interrupt Bit */ + const uint32_t inepint11 : 1; /* IN Endpoint 11 Interrupt Bit */ + const uint32_t inepint12 : 1; /* IN Endpoint 12 Interrupt Bit */ + const uint32_t inepint13 : 1; /* IN Endpoint 13 Interrupt Bit */ + const uint32_t inepint14 : 1; /* IN Endpoint 14 Interrupt Bit */ + const uint32_t inepint15 : 1; /* IN Endpoint 15 Interrupt Bit */ + const uint32_t outepint0 : 1; /* OUT Endpoint 0 Interrupt Bit */ + const uint32_t outepint1 : 1; /* OUT Endpoint 1 Interrupt Bi */ + const uint32_t outepint2 : 1; /* OUT Endpoint 2 Interrupt Bit */ + const uint32_t outepint3 : 1; /* OUT Endpoint 3 Interrupt Bit */ + const uint32_t outepint4 : 1; /* OUT Endpoint 4 Interrupt Bit */ + const uint32_t outepint5 : 1; /* OUT Endpoint 5 Interrupt Bit */ + const uint32_t outepint6 : 1; /* OUT Endpoint 6 Interrupt Bi */ + const uint32_t outepint7 : 1; /* OUT Endpoint 7 Interrupt Bit */ + const uint32_t outepint8 : 1; /* OUT Endpoint 8 Interrupt Bit */ + const uint32_t outepint9 : 1; /* OUT Endpoint 9 Interrupt Bit */ + const uint32_t outepint10 : 1; /* OUT Endpoint 10 Interrupt Bit */ + const uint32_t outepint11 : 1; /* OUT Endpoint 11 Interrupt Bit */ + const uint32_t outepint12 : 1; /* OUT Endpoint 12 Interrupt Bit */ + const uint32_t outepint13 : 1; /* OUT Endpoint 13 Interrupt Bit */ + const uint32_t outepint14 : 1; /* OUT Endpoint 14 Interrupt Bi */ + const uint32_t outepint15 : 1; /* OUT Endpoint 15 Interrupt Bit */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DAINT. */ +typedef volatile struct ALT_USB_DEV_DAINT_s ALT_USB_DEV_DAINT_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DAINT register from the beginning of the component. */ +#define ALT_USB_DEV_DAINT_OFST 0x18 +/* The address of the ALT_USB_DEV_DAINT register. */ +#define ALT_USB_DEV_DAINT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DAINT_OFST)) + +/* + * Register : Device All Endpoints Interrupt Mask Register - daintmsk + * + * The Device Endpoint Interrupt Mask register works with the Device Endpoint + * Interrupt register to interrupt the application when an event occurs on a device + * endpoint. However, the Device All Endpoints Interrupt (DAINT) register bit + * corresponding to that interrupt is still set. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-----|:-------|:------|:----------------------------------- + * [0] | RW | 0x0 | IN Endpoint 0 Interrupt mask Bit + * [1] | RW | 0x0 | IN Endpoint 1 Interrupt mask Bit + * [2] | RW | 0x0 | N Endpoint 2 Interrupt mask Bit + * [3] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK3 + * [4] | RW | 0x0 | IN Endpoint 4 Interrupt mask Bit + * [5] | RW | 0x0 | IN Endpoint 5 Interrupt mask Bit + * [6] | RW | 0x0 | IN Endpoint 6 Interrupt mask Bit + * [7] | RW | 0x0 | IN Endpoint 7 Interrupt mask Bit + * [8] | RW | 0x0 | IN Endpoint 8 Interrupt mask Bit + * [9] | RW | 0x0 | IN Endpoint 9 Interrupt mask Bit + * [10] | RW | 0x0 | IN Endpoint 10 Interrupt mask Bit + * [11] | RW | 0x0 | IN Endpoint 11 Interrupt mask Bit + * [12] | RW | 0x0 | IN Endpoint 12 Interrupt mask Bit + * [13] | RW | 0x0 | IN Endpoint 13 Interrupt mask Bit + * [14] | RW | 0x0 | IN Endpoint 14 Interrupt mask Bit + * [15] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK15 + * [16] | RW | 0x0 | OUT Endpoint 0 Interrupt mask Bit + * [17] | RW | 0x0 | OUT Endpoint 1 Interrupt mask Bit + * [18] | RW | 0x0 | OUT Endpoint 2 Interrupt mask Bi + * [19] | RW | 0x0 | OUT Endpoint 3 Interrupt mask Bi + * [20] | RW | 0x0 | OUT Endpoint 4 Interrupt mask Bit + * [21] | RW | 0x0 | OUT Endpoint 5 Interrupt mask Bit + * [22] | RW | 0x0 | OUT Endpoint 6 Interrupt mask Bit + * [23] | RW | 0x0 | OUT Endpoint 7 Interrupt mask Bit + * [24] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK8 + * [25] | RW | 0x0 | OUT Endpoint 9 Interrupt mask Bit + * [26] | RW | 0x0 | OUT Endpoint 10 Interrupt mask Bi + * [27] | RW | 0x0 | OUT Endpoint 11 Interrupt mask Bit + * [28] | RW | 0x0 | OUT Endpoint 12 Interrupt mask Bit + * [29] | RW | 0x0 | OUT Endpoint 13 Interrupt mask Bit + * [30] | RW | 0x0 | OUT Endpoint 14 Interrupt mask Bit + * [31] | RW | 0x0 | OUT Endpoint 15 Interrupt mask Bit + * + */ +/* + * Field : IN Endpoint 0 Interrupt mask Bit - inepmsk0 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK0_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK0_E_MSK | 0x0 | IN Endpoint 0 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK0 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK0_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK0 + * + * IN Endpoint 0 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK0_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK0_MSB 0 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK0_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK0_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK0 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IN Endpoint 1 Interrupt mask Bit - inepmsk1 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK1_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK1_E_MSK | 0x0 | IN Endpoint 1 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK1 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK1_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK1 + * + * IN Endpoint 1 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK1_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK1_MSB 1 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK1_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK1_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK1 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : N Endpoint 2 Interrupt mask Bit - inepmsk2 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK2_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK2_E_MSK | 0x0 | IN Endpoint 2 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK2 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK2_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK2 + * + * IN Endpoint 2 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK2_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK2_MSB 2 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK2_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK2_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK2 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : inepmsk3 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK3_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK3_E_MSK | 0x0 | IN Endpoint 3 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK3 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK3_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK3 + * + * IN Endpoint 3 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK3_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK3_MSB 3 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK3_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK3_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK3 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Endpoint 4 Interrupt mask Bit - inepmsk4 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK4_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK4_E_MSK | 0x0 | IN Endpoint 4 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK4 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK4_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK4 + * + * IN Endpoint 4 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK4_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK4_MSB 4 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK4_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK4_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK4_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK4 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Endpoint 5 Interrupt mask Bit - inepmsk5 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK5_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK5_E_MSK | 0x0 | IN Endpoint 5 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK5 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK5_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK5 + * + * IN Endpoint 5 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK5_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK5_MSB 5 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK5_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK5_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK5 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint 6 Interrupt mask Bit - inepmsk6 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK6_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK6_E_MSK | 0x0 | IN Endpoint 6 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK6 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK6_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK6 + * + * IN Endpoint 6 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK6_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK6_MSB 6 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK6_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK6_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK6 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IN Endpoint 7 Interrupt mask Bit - inepmsk7 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK7_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK7_E_MSK | 0x0 | IN Endpoint 7 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK7 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK7_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK7 + * + * IN Endpoint 7 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK7_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK7_MSB 7 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK7_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK7_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK7 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : IN Endpoint 8 Interrupt mask Bit - inepmsk8 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK8_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK8_E_MSK | 0x0 | IN Endpoint 8 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK8 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK8_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK8 + * + * IN Endpoint 8 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK8_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK8_MSB 8 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK8_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK8_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK8 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : IN Endpoint 9 Interrupt mask Bit - inepmsk9 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK9_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK9_E_MSK | 0x0 | IN Endpoint 0 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK9 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK9_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK9 + * + * IN Endpoint 0 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK9_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK9_MSB 9 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK9_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK9_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK9 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : IN Endpoint 10 Interrupt mask Bit - inepmsk10 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_INEPMSK10_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK10_E_MSK | 0x0 | IN Endpoint 10 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK10 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK10_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK10 + * + * IN Endpoint 10 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK10_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK10_MSB 10 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK10_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK10_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK10 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : IN Endpoint 11 Interrupt mask Bit - inepmsk11 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_INEPMSK11_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK11_E_MSK | 0x0 | IN Endpoint 11 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK11 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK11_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK11 + * + * IN Endpoint 11 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK11_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK11_MSB 11 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK11_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK11_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK11 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : IN Endpoint 12 Interrupt mask Bit - inepmsk12 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_INEPMSK12_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK12_E_MSK | 0x0 | IN Endpoint 12 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK12 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK12_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK12 + * + * IN Endpoint 12 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK12_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK12_MSB 12 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK12_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK12_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK12_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK12 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : IN Endpoint 13 Interrupt mask Bit - InEpMsk13 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_INEPMSK13_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK13_E_MSK | 0x0 | IN Endpoint 13 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK13 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK13_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK13 + * + * IN Endpoint 13 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK13_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK13_MSB 13 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK13_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK13_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK13 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : IN Endpoint 14 Interrupt mask Bit - inepmsk14 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_INEPMSK14_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK14_E_MSK | 0x0 | IN Endpoint 14 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK14 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK14_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK14 + * + * IN Endpoint 14 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK14_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK14_MSB 14 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK14_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK14_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK14 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : InEpMsk15 + * + * IN Endpoint 15 Interrupt mask Bit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DAINTMSK_INEPMSK15_E_INACT | 0x0 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_INEPMSK15_E_ACT | 0x1 | IN Endpoint 0 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK15 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK15_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK15 + * + * IN Endpoint 0 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK15_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK15_MSB 15 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK15_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK15_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK15 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_INEPMSK15_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : OUT Endpoint 0 Interrupt mask Bit - outepmsk0 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_MSK | 0x0 | OUT Endpoint 0 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK0 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK0 + * + * OUT Endpoint 0 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_MSB 16 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : OUT Endpoint 1 Interrupt mask Bit - outepmsk1 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_MSK | 0x0 | OUT Endpoint 1 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK1 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK1 + * + * OUT Endpoint 1 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_MSB 17 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : OUT Endpoint 2 Interrupt mask Bi - outepmsk2 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_MSK | 0x0 | OUT Endpoint 2 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK2 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK2 + * + * OUT Endpoint 2 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_MSB 18 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_SET_MSK 0x00040000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_CLR_MSK 0xfffbffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_GET(value) (((value) & 0x00040000) >> 18) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_SET(value) (((value) << 18) & 0x00040000) + +/* + * Field : OUT Endpoint 3 Interrupt mask Bi - OutEPMsk3 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_MSK | 0x0 | OUT Endpoint 3 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK3 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK3 + * + * OUT Endpoint 3 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_MSB 19 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_SET_MSK 0x00080000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : OUT Endpoint 4 Interrupt mask Bit - outepmsk4 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_MSK | 0x0 | OUT Endpoint 4 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK4 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK4 + * + * OUT Endpoint 4 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_MSB 20 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : OUT Endpoint 5 Interrupt mask Bit - outepmsk5 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_MSK | 0x0 | OUT Endpoint 5 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK5 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK5 + * + * OUT Endpoint 5 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_MSB 21 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : OUT Endpoint 6 Interrupt mask Bit - outepmsk6 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_MSK | 0x0 | OUT Endpoint 6 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK6 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK6 + * + * OUT Endpoint 6 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_MSB 22 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_SET_MSK 0x00400000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_CLR_MSK 0xffbfffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_GET(value) (((value) & 0x00400000) >> 22) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_SET(value) (((value) << 22) & 0x00400000) + +/* + * Field : OUT Endpoint 7 Interrupt mask Bit - outepmsk7 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_MSK | 0x0 | OUT Endpoint 7 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK7 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK7 + * + * OUT Endpoint 7 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_LSB 23 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_MSB 23 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_SET_MSK 0x00800000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_CLR_MSK 0xff7fffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_GET(value) (((value) & 0x00800000) >> 23) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_SET(value) (((value) << 23) & 0x00800000) + +/* + * Field : outepmsk8 + * + * OUT Endpoint 8 Interrupt mask Bit + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_MSK | 0x0 | OUT Endpoint 8 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK8 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK8 + * + * OUT Endpoint 8 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_LSB 24 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_MSB 24 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_SET_MSK 0x01000000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_CLR_MSK 0xfeffffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_GET(value) (((value) & 0x01000000) >> 24) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_SET(value) (((value) << 24) & 0x01000000) + +/* + * Field : OUT Endpoint 9 Interrupt mask Bit - outepmsk9 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_MSK | 0x0 | OUT Endpoint 9 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK9 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK9 + * + * OUT Endpoint 9 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_LSB 25 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_MSB 25 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_SET_MSK 0x02000000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_CLR_MSK 0xfdffffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_GET(value) (((value) & 0x02000000) >> 25) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_SET(value) (((value) << 25) & 0x02000000) + +/* + * Field : OUT Endpoint 10 Interrupt mask Bi - outepmsk10 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------- + * ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_MSK | 0x0 | OUT Endpoint 10 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK10 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK10 + * + * OUT Endpoint 10 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_MSB 26 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : OUT Endpoint 11 Interrupt mask Bit - outepmsk11 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------- + * ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_MSK | 0x0 | OUT Endpoint 11 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK11 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK11 + * + * OUT Endpoint 11 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_MSB 27 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : OUT Endpoint 12 Interrupt mask Bit - outepmsk12 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------- + * ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_MSK | 0x0 | OUT Endpoint 12 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK12 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK12 + * + * OUT Endpoint 12 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_MSB 28 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : OUT Endpoint 13 Interrupt mask Bit - outepmsk13 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------- + * ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_MSK | 0x0 | OUT Endpoint 13 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK13 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK13 + * + * OUT Endpoint 13 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_MSB 29 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : OUT Endpoint 14 Interrupt mask Bit - OutEPMsk14 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------- + * ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_MSK | 0x0 | OUT Endpoint 14 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK14 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK14 + * + * OUT Endpoint 14 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_MSB 30 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : OUT Endpoint 15 Interrupt mask Bit - outepmsk15 + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------- + * ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_NOMSK | 0x1 | No Interrupt mask + * ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_MSK | 0x0 | OUT Endpoint 15 Interrupt mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK15 + * + * No Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_NOMSK 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK15 + * + * OUT Endpoint 15 Interrupt mask + */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_MSK 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_MSB 31 +/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_RESET 0x0 +/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 field value from a register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DAINTMSK. + */ +struct ALT_USB_DEV_DAINTMSK_s +{ + uint32_t inepmsk0 : 1; /* IN Endpoint 0 Interrupt mask Bit */ + uint32_t inepmsk1 : 1; /* IN Endpoint 1 Interrupt mask Bit */ + uint32_t inepmsk2 : 1; /* N Endpoint 2 Interrupt mask Bit */ + uint32_t inepmsk3 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK3 */ + uint32_t inepmsk4 : 1; /* IN Endpoint 4 Interrupt mask Bit */ + uint32_t inepmsk5 : 1; /* IN Endpoint 5 Interrupt mask Bit */ + uint32_t inepmsk6 : 1; /* IN Endpoint 6 Interrupt mask Bit */ + uint32_t inepmsk7 : 1; /* IN Endpoint 7 Interrupt mask Bit */ + uint32_t inepmsk8 : 1; /* IN Endpoint 8 Interrupt mask Bit */ + uint32_t inepmsk9 : 1; /* IN Endpoint 9 Interrupt mask Bit */ + uint32_t inepmsk10 : 1; /* IN Endpoint 10 Interrupt mask Bit */ + uint32_t inepmsk11 : 1; /* IN Endpoint 11 Interrupt mask Bit */ + uint32_t inepmsk12 : 1; /* IN Endpoint 12 Interrupt mask Bit */ + uint32_t InEpMsk13 : 1; /* IN Endpoint 13 Interrupt mask Bit */ + uint32_t inepmsk14 : 1; /* IN Endpoint 14 Interrupt mask Bit */ + uint32_t InEpMsk15 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK15 */ + uint32_t outepmsk0 : 1; /* OUT Endpoint 0 Interrupt mask Bit */ + uint32_t outepmsk1 : 1; /* OUT Endpoint 1 Interrupt mask Bit */ + uint32_t outepmsk2 : 1; /* OUT Endpoint 2 Interrupt mask Bi */ + uint32_t OutEPMsk3 : 1; /* OUT Endpoint 3 Interrupt mask Bi */ + uint32_t outepmsk4 : 1; /* OUT Endpoint 4 Interrupt mask Bit */ + uint32_t outepmsk5 : 1; /* OUT Endpoint 5 Interrupt mask Bit */ + uint32_t outepmsk6 : 1; /* OUT Endpoint 6 Interrupt mask Bit */ + uint32_t outepmsk7 : 1; /* OUT Endpoint 7 Interrupt mask Bit */ + uint32_t outepmsk8 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK8 */ + uint32_t outepmsk9 : 1; /* OUT Endpoint 9 Interrupt mask Bit */ + uint32_t outepmsk10 : 1; /* OUT Endpoint 10 Interrupt mask Bi */ + uint32_t outepmsk11 : 1; /* OUT Endpoint 11 Interrupt mask Bit */ + uint32_t outepmsk12 : 1; /* OUT Endpoint 12 Interrupt mask Bit */ + uint32_t outepmsk13 : 1; /* OUT Endpoint 13 Interrupt mask Bit */ + uint32_t OutEPMsk14 : 1; /* OUT Endpoint 14 Interrupt mask Bit */ + uint32_t outepmsk15 : 1; /* OUT Endpoint 15 Interrupt mask Bit */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DAINTMSK. */ +typedef volatile struct ALT_USB_DEV_DAINTMSK_s ALT_USB_DEV_DAINTMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DAINTMSK register from the beginning of the component. */ +#define ALT_USB_DEV_DAINTMSK_OFST 0x1c +/* The address of the ALT_USB_DEV_DAINTMSK register. */ +#define ALT_USB_DEV_DAINTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DAINTMSK_OFST)) + +/* + * Register : Device VBUS Discharge Time Register - dvbusdis + * + * This register specifies the VBUS discharge time after VBUS pulsing during SRP. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:--------------------------- + * [15:0] | RW | 0x17d7 | Device VBUS Discharge Time + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Device VBUS Discharge Time - dvbusdis + * + * This value equals: + * + * VBUS discharge time in PHY clocks/1,024 The value you use depends whether the + * PHY is operating at 30 MHz (16-bit data width) or 60 MHz (8-bit data width). + * Depending on your VBUS load, this value can need adjustment. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */ +#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */ +#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_MSB 15 +/* The width in bits of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */ +#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value. */ +#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value. */ +#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */ +#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_RESET 0x17d7 +/* Extracts the ALT_USB_DEV_DVBUSDIS_DVBUSDIS field value from a register. */ +#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DVBUSDIS. + */ +struct ALT_USB_DEV_DVBUSDIS_s +{ + uint32_t dvbusdis : 16; /* Device VBUS Discharge Time */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DVBUSDIS. */ +typedef volatile struct ALT_USB_DEV_DVBUSDIS_s ALT_USB_DEV_DVBUSDIS_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DVBUSDIS register from the beginning of the component. */ +#define ALT_USB_DEV_DVBUSDIS_OFST 0x28 +/* The address of the ALT_USB_DEV_DVBUSDIS register. */ +#define ALT_USB_DEV_DVBUSDIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DVBUSDIS_OFST)) + +/* + * Register : Device VBUS Pulsing Time Register - dvbuspulse + * + * This register specifies the VBUS pulsing time during SRP. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------- + * [11:0] | RW | 0x5b8 | Device VBUS Pulsing Time + * [31:12] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Device VBUS Pulsing Time - dvbuspulse + * + * Specifies the VBUS pulsing time during SRP. This value equals: + * + * VBUS pulsing time in PHY clocks/1,024 + * + * The value you use depends whether the PHY is operating at 30MHz (16-bit data + * width) or 60 MHz (8-bit data width). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */ +#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */ +#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_MSB 11 +/* The width in bits of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */ +#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_WIDTH 12 +/* The mask used to set the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value. */ +#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_SET_MSK 0x00000fff +/* The mask used to clear the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value. */ +#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_CLR_MSK 0xfffff000 +/* The reset value of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */ +#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_RESET 0x5b8 +/* Extracts the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE field value from a register. */ +#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_GET(value) (((value) & 0x00000fff) >> 0) +/* Produces a ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_SET(value) (((value) << 0) & 0x00000fff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DVBUSPULSE. + */ +struct ALT_USB_DEV_DVBUSPULSE_s +{ + uint32_t dvbuspulse : 12; /* Device VBUS Pulsing Time */ + uint32_t : 20; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DVBUSPULSE. */ +typedef volatile struct ALT_USB_DEV_DVBUSPULSE_s ALT_USB_DEV_DVBUSPULSE_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DVBUSPULSE register from the beginning of the component. */ +#define ALT_USB_DEV_DVBUSPULSE_OFST 0x2c +/* The address of the ALT_USB_DEV_DVBUSPULSE register. */ +#define ALT_USB_DEV_DVBUSPULSE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DVBUSPULSE_OFST)) + +/* + * Register : Device Threshold Control Register - dthrctl + * + * Thresholding is not supported in Slave mode and so this register must not be + * programmed in Slave mode. for threshold support, the AHB must be run at 60 MHz + * or higher. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------------------------- + * [0] | RW | 0x0 | Non-ISO IN Endpoints Threshold Enable + * [1] | RW | 0x0 | ISO IN Endpoints Threshold Enable + * [10:2] | RW | 0x8 | Transmit Threshold + * [12:11] | RW | 0x0 | AHB Threshold Ratio + * [15:13] | ??? | 0x0 | *UNDEFINED* + * [16] | RW | 0x0 | Receive Threshold Enable + * [25:17] | RW | 0x8 | Receive Threshold Length + * [26] | ??? | 0x0 | *UNDEFINED* + * [27] | RW | 0x1 | Arbiter Parking Enable + * [31:28] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Non-ISO IN Endpoints Threshold Enable - nonisothren + * + * When this bit is Set, the core enables thresholding for Non Isochronous IN + * endpoints. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_DISD | 0x0 | No thresholding + * ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_END | 0x1 | Enable thresholding + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_NONISOTHREN + * + * No thresholding + */ +#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_NONISOTHREN + * + * Enable thresholding + */ +#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_MSB 0 +/* The width in bits of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value. */ +#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value. */ +#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DTHRCTL_NONISOTHREN field value from a register. */ +#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : ISO IN Endpoints Threshold Enable - isothren + * + * When this bit is Set, the core enables thresholding for isochronous IN + * endpoints. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:--------------------- + * ALT_USB_DEV_DTHRCTL_ISOTHREN_E_DISD | 0x0 | No thresholding + * ALT_USB_DEV_DTHRCTL_ISOTHREN_E_END | 0x1 | Enables thresholding + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ISOTHREN + * + * No thresholding + */ +#define ALT_USB_DEV_DTHRCTL_ISOTHREN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ISOTHREN + * + * Enables thresholding + */ +#define ALT_USB_DEV_DTHRCTL_ISOTHREN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_ISOTHREN_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_ISOTHREN_MSB 1 +/* The width in bits of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_ISOTHREN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DTHRCTL_ISOTHREN register field value. */ +#define ALT_USB_DEV_DTHRCTL_ISOTHREN_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DTHRCTL_ISOTHREN register field value. */ +#define ALT_USB_DEV_DTHRCTL_ISOTHREN_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_ISOTHREN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DTHRCTL_ISOTHREN field value from a register. */ +#define ALT_USB_DEV_DTHRCTL_ISOTHREN_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DTHRCTL_ISOTHREN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTHRCTL_ISOTHREN_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : Transmit Threshold - txthrlen + * + * This field specifies Transmit thresholding size in DWORDS. This also forms the + * MAC threshold and specifies the amount of data in bytes to be in the + * corresponding endpoint transmit FIFO, before the core can start transmit on the + * USB. The threshold length has to be at least eight DWORDS when the value of + * AHBThrRatio is 0. In case the AHBThrRatio is non zero the application needs to + * ensure that the AHB Threshold value does not go below the recommended eight + * DWORD. This field controls both isochronous and non-isochronous IN endpoint + * thresholds. The recommended value for ThrLen is to be the same as the programmed + * AHB Burst Length (GAHBCFG.HBstLen). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */ +#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */ +#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_MSB 10 +/* The width in bits of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */ +#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_WIDTH 9 +/* The mask used to set the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value. */ +#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_SET_MSK 0x000007fc +/* The mask used to clear the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value. */ +#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_CLR_MSK 0xfffff803 +/* The reset value of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */ +#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_RESET 0x8 +/* Extracts the ALT_USB_DEV_DTHRCTL_TXTHRLEN field value from a register. */ +#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_GET(value) (((value) & 0x000007fc) >> 2) +/* Produces a ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_SET(value) (((value) << 2) & 0x000007fc) + +/* + * Field : AHB Threshold Ratio - ahbthrratio + * + * These bits define the ratio between the AHB threshold and the MAC threshold for + * the transmit path only. The AHB threshold always remains less than or equal to + * the USB threshold, because this does not increase overhead. Both the AHB and the + * MAC threshold must be DWORD-aligned. The application needs to program TxThrLen + * and the AHBThrRatio to make the AHB Threshold value DWORD aligned. If the AHB + * threshold value is not DWORD aligned, the core might not behave correctly. When + * programming the TxThrLen and AHBThrRatio, the application must ensure that the + * minimum AHB threshold value does not go below 8 DWORDS to meet the USB + * turnaround time requirements. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:--------------------------------- + * ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESZERO | 0x0 | AHB threshold = MAC threshold + * ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESONE | 0x1 | AHB threshold = MAC threshold /2 + * ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTWO | 0x2 | AHB threshold = MAC threshold /4 + * ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTHREE | 0x3 | AHB threshold = MAC threshold / + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO + * + * AHB threshold = MAC threshold + */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESZERO 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO + * + * AHB threshold = MAC threshold /2 + */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO + * + * AHB threshold = MAC threshold /4 + */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO + * + * AHB threshold = MAC threshold / + */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_MSB 12 +/* The width in bits of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value. */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_SET_MSK 0x00001800 +/* The mask used to clear the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value. */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_CLR_MSK 0xffffe7ff +/* The reset value of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO field value from a register. */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_GET(value) (((value) & 0x00001800) >> 11) +/* Produces a ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_SET(value) (((value) << 11) & 0x00001800) + +/* + * Field : Receive Threshold Enable - rxthren + * + * When this bit is Set, the core enables thresholding in the receive direction. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DTHRCTL_RXTHREN_E_DISD | 0x0 | Disable thresholding + * ALT_USB_DEV_DTHRCTL_RXTHREN_E_END | 0x1 | Enable thresholding in the receive direction + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_RXTHREN + * + * Disable thresholding + */ +#define ALT_USB_DEV_DTHRCTL_RXTHREN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_RXTHREN + * + * Enable thresholding in the receive direction + */ +#define ALT_USB_DEV_DTHRCTL_RXTHREN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_RXTHREN_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_RXTHREN_MSB 16 +/* The width in bits of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_RXTHREN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DTHRCTL_RXTHREN register field value. */ +#define ALT_USB_DEV_DTHRCTL_RXTHREN_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DTHRCTL_RXTHREN register field value. */ +#define ALT_USB_DEV_DTHRCTL_RXTHREN_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */ +#define ALT_USB_DEV_DTHRCTL_RXTHREN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DTHRCTL_RXTHREN field value from a register. */ +#define ALT_USB_DEV_DTHRCTL_RXTHREN_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DTHRCTL_RXTHREN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTHRCTL_RXTHREN_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : Receive Threshold Length - rxthrlen + * + * This field specifies Receive thresholding size in DWORDS.This field also + * specifies the amount of data received on the USB before the core can start + * transmitting on the AHB. The threshold length has to be at least eight DWORDS. + * The recommended value for ThrLen is to be the same as the programmed AHB Burst + * Length (GAHBCFG.HBstLen). + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */ +#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */ +#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_MSB 25 +/* The width in bits of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */ +#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_WIDTH 9 +/* The mask used to set the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value. */ +#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_SET_MSK 0x03fe0000 +/* The mask used to clear the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value. */ +#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_CLR_MSK 0xfc01ffff +/* The reset value of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */ +#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_RESET 0x8 +/* Extracts the ALT_USB_DEV_DTHRCTL_RXTHRLEN field value from a register. */ +#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_GET(value) (((value) & 0x03fe0000) >> 17) +/* Produces a ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_SET(value) (((value) << 17) & 0x03fe0000) + +/* + * Field : Arbiter Parking Enable - arbprken + * + * This bit controls internal DMA arbiter parking for IN endpoints. When + * thresholding is enabled and this bit is Set to one, Then the arbiter parks on + * the IN endpoint for which there is a token received on the USB. This is done to + * avoid getting into underrun conditions. By Default the parking is enabled. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------------------------------- + * ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_DISD | 0x0 | Disable DMA arbiter parking + * ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_END | 0x1 | Enable DMA arbiter parking for IN endpoints + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ARBPRKEN + * + * Disable DMA arbiter parking + */ +#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ARBPRKEN + * + * Enable DMA arbiter parking for IN endpoints + */ +#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */ +#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */ +#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_MSB 27 +/* The width in bits of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */ +#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value. */ +#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value. */ +#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */ +#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_RESET 0x1 +/* Extracts the ALT_USB_DEV_DTHRCTL_ARBPRKEN field value from a register. */ +#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_SET(value) (((value) << 27) & 0x08000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTHRCTL. + */ +struct ALT_USB_DEV_DTHRCTL_s +{ + uint32_t nonisothren : 1; /* Non-ISO IN Endpoints Threshold Enable */ + uint32_t isothren : 1; /* ISO IN Endpoints Threshold Enable */ + uint32_t txthrlen : 9; /* Transmit Threshold */ + uint32_t ahbthrratio : 2; /* AHB Threshold Ratio */ + uint32_t : 3; /* *UNDEFINED* */ + uint32_t rxthren : 1; /* Receive Threshold Enable */ + uint32_t rxthrlen : 9; /* Receive Threshold Length */ + uint32_t : 1; /* *UNDEFINED* */ + uint32_t arbprken : 1; /* Arbiter Parking Enable */ + uint32_t : 4; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTHRCTL. */ +typedef volatile struct ALT_USB_DEV_DTHRCTL_s ALT_USB_DEV_DTHRCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTHRCTL register from the beginning of the component. */ +#define ALT_USB_DEV_DTHRCTL_OFST 0x30 +/* The address of the ALT_USB_DEV_DTHRCTL register. */ +#define ALT_USB_DEV_DTHRCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTHRCTL_OFST)) + +/* + * Register : Device IN Endpoint FIFO Empty Interrupt Mask Register - diepempmsk + * + * This register is used to control the IN endpoint FIFO empty interrupt generation + * (DIEPINTn.TxfEmp). + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------- + * [0] | RW | 0x0 | IN EP 0 Tx FIFO Empty Interrupt Mask Bits + * [1] | RW | 0x0 | IN EP 1 Tx FIFO Empty Interrupt Mask Bits + * [2] | RW | 0x0 | IN EP 2 Tx FIFO Empty Interrupt Mask Bits + * [3] | RW | 0x0 | IN EP 3 Tx FIFO Empty Interrupt Mask Bits + * [4] | RW | 0x0 | IN EP 4 Tx FIFO Empty Interrupt Mask Bits + * [5] | RW | 0x0 | IN EP 5 Tx FIFO Empty Interrupt Mask Bits + * [6] | RW | 0x0 | IN EP 6 Tx FIFO Empty Interrupt Mask Bits + * [7] | RW | 0x0 | IN EP 7 Tx FIFO Empty Interrupt Mask Bits + * [8] | RW | 0x0 | IN EP 8 Tx FIFO Empty Interrupt Mask Bits + * [9] | RW | 0x0 | IN EP 9 Tx FIFO Empty Interrupt Mask Bits + * [10] | RW | 0x0 | IN EP 10 Tx FIFO Empty Interrupt Mask Bits + * [11] | RW | 0x0 | IN EP 11 Tx FIFO Empty Interrupt Mask Bits + * [12] | RW | 0x0 | IN EP 12 Tx FIFO Empty Interrupt Mask Bits + * [13] | RW | 0x0 | IN EP 13 Tx FIFO Empty Interrupt Mask Bits + * [14] | RW | 0x0 | IN EP 14 Tx FIFO Empty Interrupt Mask Bits + * [15] | RW | 0x0 | IN EP 15 Tx FIFO Empty Interrupt Mask Bits + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN EP 0 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk0 + * + * This bit acts as mask bits for DIEPINT0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_MSK | 0x0 | Mask End point 0 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 + * + * Mask End point 0 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : IN EP 1 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk1 + * + * This bit acts as mask bits for DIEPINT1. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_MSK | 0x0 | Mask End point 1 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 + * + * Mask End point 1 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : IN EP 2 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk2 + * + * This bit acts as mask bits for DIEPINT2. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_MSK | 0x0 | Mask End point 2 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 + * + * Mask End point 2 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : IN EP 3 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk3 + * + * This bit acts as mask bits for DIEPINT3. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_MSK | 0x0 | Mask End point 3 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 + * + * Mask End point 3 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN EP 4 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk4 + * + * This bit acts as mask bits for DIEPINT4. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_MSK | 0x0 | Mask End point 4 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 + * + * Mask End point 4 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN EP 5 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk5 + * + * This bit acts as mask bits for DIEPINT5. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_MSK | 0x0 | Mask End point 5 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 + * + * Mask End point 5 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN EP 6 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk6 + * + * This bit acts as mask bits for DIEPINT6. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_MSK | 0x0 | Mask End point 6 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 + * + * Mask End point 6 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : IN EP 7 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk7 + * + * This bit acts as mask bits for DIEPINT7. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_MSK | 0x0 | Mask End point 7 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 + * + * Mask End point 7 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : IN EP 8 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk8 + * + * This bit acts as mask bits for DIEPINT8. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_MSK | 0x0 | Mask End point 8 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 + * + * Mask End point 8 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : IN EP 9 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk9 + * + * This bit acts as mask bits for DIEPINT9. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------------|:------|:--------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_MSK | 0x0 | Mask End point 9 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 + * + * Mask End point 9 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : IN EP 10 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk10 + * + * This bit acts as mask bits for DIEPINT10. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_MSK | 0x0 | Mask End point 10 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 + * + * Mask End point 10 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_LSB 10 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_SET_MSK 0x00000400 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_CLR_MSK 0xfffffbff +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_GET(value) (((value) & 0x00000400) >> 10) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_SET(value) (((value) << 10) & 0x00000400) + +/* + * Field : IN EP 11 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk11 + * + * This bit acts as mask bits for DIEPINT11. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_MSK | 0x0 | Mask End point 11 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 + * + * Mask End point 11 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : IN EP 12 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk12 + * + * This bit acts as mask bits for DIEPINT12. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_MSK | 0x0 | Mask End point 12 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 + * + * Mask End point 12 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : IN EP 13 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk13 + * + * This bit acts as mask bits for DIEPINT13. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_MSK | 0x0 | Mask End point 12 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 + * + * Mask End point 12 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : IN EP 14 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk14 + * + * This bit acts as mask bits for DIEPINT14. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_MSK | 0x0 | Mask End point 14 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 + * + * Mask End point 14 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_SET(value) (((value) << 14) & 0x00004000) + +/* + * Field : IN EP 15 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk15 + * + * This bit acts as mask bits for DIEPINT15. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_MSK | 0x0 | Mask End point 15 interrupt + * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_NOMSK | 0x1 | No mask + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 + * + * Mask End point 15 interrupt + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_MSK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 + * + * No mask + */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_NOMSK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 field value from a register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_SET(value) (((value) << 15) & 0x00008000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPEMPMSK. + */ +struct ALT_USB_DEV_DIEPEMPMSK_s +{ + uint32_t ineptxfempmsk0 : 1; /* IN EP 0 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk1 : 1; /* IN EP 1 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk2 : 1; /* IN EP 2 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk3 : 1; /* IN EP 3 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk4 : 1; /* IN EP 4 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk5 : 1; /* IN EP 5 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk6 : 1; /* IN EP 6 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk7 : 1; /* IN EP 7 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk8 : 1; /* IN EP 8 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk9 : 1; /* IN EP 9 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk10 : 1; /* IN EP 10 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk11 : 1; /* IN EP 11 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk12 : 1; /* IN EP 12 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk13 : 1; /* IN EP 13 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk14 : 1; /* IN EP 14 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t ineptxfempmsk15 : 1; /* IN EP 15 Tx FIFO Empty Interrupt Mask Bits */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPEMPMSK. */ +typedef volatile struct ALT_USB_DEV_DIEPEMPMSK_s ALT_USB_DEV_DIEPEMPMSK_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPEMPMSK register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPEMPMSK_OFST 0x34 +/* The address of the ALT_USB_DEV_DIEPEMPMSK register. */ +#define ALT_USB_DEV_DIEPEMPMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPEMPMSK_OFST)) + +/* + * Register : Device Control IN Endpoint 0 Control Register - diepctl0 + * + * This register covers Device Control IN Endpoint 0. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [1:0] | RW | 0x0 | Maximum Packet Size + * [14:2] | ??? | 0x0 | *UNDEFINED* + * [15] | R | 0x1 | USB Active Endpoint + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | R | 0x0 | NAK Status + * [19:18] | R | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [29:28] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints.The application must program this field with the + * maximum packet size for the current logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES64 | 0x0 | 64 bytes + * ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES32 | 0x1 | 32 bytes + * ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES16 | 0x2 | 16 bytes + * ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES8 | 0x3 | 8 bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS + * + * 64 bytes + */ +#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES64 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS + * + * 32 bytes + */ +#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES32 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS + * + * 16 bytes + */ +#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES16 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS + * + * 8 bytes + */ +#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES8 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL0_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL0_MPS_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPCTL0_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL0_MPS_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL0_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL0_MPS_SET_MSK 0x00000003 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL0_MPS_CLR_MSK 0xfffffffc +/* The reset value of the ALT_USB_DEV_DIEPCTL0_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL0_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL0_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL0_MPS_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL0_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL0_MPS_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : USB Active Endpoint - usbactep + * + * This bit is always SET to 1, indicating that control endpoint 0 is always active + * in all configurations and interfaces. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------------- + * ALT_USB_DEV_DIEPCTL0_USBACTEP_E_ACT0 | 0x1 | Control endpoint is always active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_USBACTEP + * + * Control endpoint is always active + */ +#define ALT_USB_DEV_DIEPCTL0_USBACTEP_E_ACT0 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL0_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL0_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL0_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL0_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL0_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL0_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL0_USBACTEP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPCTL0_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL0_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL0_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL0_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : NAK Status - naksts + * + * When this bit is Set, either by the application or core, the core stops + * transmitting data, even If there is data available in the TxFIFO. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL0_NAKSTS_E_INACT | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL0_NAKSTS_E_ACT | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL0_NAKSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL0_NAKSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL0_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL0_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL0_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL0_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL0_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL0_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL0_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL0_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL0_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL0_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL0_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Hardcoded to 00 for control. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_DEV_DIEPCTL0_EPTYPE_E_ACT | 0x0 | Endpoint Control 0 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPTYPE + * + * Endpoint Control 0 + */ +#define ALT_USB_DEV_DIEPCTL0_EPTYPE_E_ACT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL0_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL0_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL0_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL0_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * The application can only Set this bit, and the core clears it, when a SETUP + * token is received for this endpoint. If a NAK bit, Global Nonperiodic IN NAK, or + * Global OUT NAK is Set along with this bit, the STALL bit takes priority. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_DEV_DIEPCTL0_STALL_E_INACT | 0x0 | No Stall + * ALT_USB_DEV_DIEPCTL0_STALL_E_ACT | 0x1 | Stall Handshake + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_STALL + * + * No Stall + */ +#define ALT_USB_DEV_DIEPCTL0_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_STALL + * + * Stall Handshake + */ +#define ALT_USB_DEV_DIEPCTL0_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL0_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL0_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL0_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL0_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL0_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL0_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL0_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL0_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL0_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL0_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL0_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL0_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL0_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * for Shared FIFO operation, this value is always Set to 0, indicating that + * control IN endpoint 0 data is always written in the Non-Periodic Transmit FIFO. + * for Dedicated FIFO operation, this value is Set to the FIFO number that is + * assigned to IN Endpoint 0. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL0_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL0_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL0_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL0_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL0_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL0_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL0_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL0_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL0_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL0_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL0_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL0_CNAK_E_NOCLR | 0x0 | No action + * ALT_USB_DEV_DIEPCTL0_CNAK_E_CLR | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_CNAK + * + * No action + */ +#define ALT_USB_DEV_DIEPCTL0_CNAK_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL0_CNAK_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL0_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL0_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL0_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL0_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL0_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL0_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL0_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL0_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL0_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL0_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL0_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL0_SNAK_E_NOSET | 0x0 | No action + * ALT_USB_DEV_DIEPCTL0_SNAK_E_SET | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_SNAK + * + * No action + */ +#define ALT_USB_DEV_DIEPCTL0_SNAK_E_NOSET 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL0_SNAK_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL0_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL0_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL0_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL0_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL0_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL0_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL0_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL0_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL0_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL0_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL0_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Endpoint Disable - epdis + * + * The application sets this bit to stop transmitting data on an endpoint, even + * before the transfer for that endpoint is complete. The application must wait for + * the Endpoint Disabled interrupt before treating the endpoint as disabled. The + * core clears this bit before setting the Endpoint Disabled Interrupt. The + * application must Set this bit only If Endpoint Enable is already Set for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------------- + * ALT_USB_DEV_DIEPCTL0_EPDIS_E_INACT | 0x0 | No action + * ALT_USB_DEV_DIEPCTL0_EPDIS_E_ACT | 0x1 | Stop transmitting data on endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPDIS + * + * No action + */ +#define ALT_USB_DEV_DIEPCTL0_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPDIS + * + * Stop transmitting data on endpoint + */ +#define ALT_USB_DEV_DIEPCTL0_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL0_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL0_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL0_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL0_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL0_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL0_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * When Scatter/Gather DMA mode is enabled, for IN endpoints this bit indicates + * that the descriptor structure and data buffer with data ready to transmit is + * setup. When Scatter/Gather DMA mode is disabled such as in bufferpointer based + * DMA mode this bit indicates that data is ready to be transmitted on the + * endpoint. The core clears this bit before setting the following interrupts on + * this endpoint: + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------- + * ALT_USB_DEV_DIEPCTL0_EPENA_E_INACT | 0x0 | No action + * ALT_USB_DEV_DIEPCTL0_EPENA_E_ACT | 0x1 | Endpoint Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPENA + * + * No action + */ +#define ALT_USB_DEV_DIEPCTL0_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPENA + * + * Endpoint Enabled + */ +#define ALT_USB_DEV_DIEPCTL0_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL0_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL0_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL0_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL0_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL0_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL0_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL0_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL0. + */ +struct ALT_USB_DEV_DIEPCTL0_s +{ + uint32_t mps : 2; /* Maximum Packet Size */ + uint32_t : 13; /* *UNDEFINED* */ + const uint32_t usbactep : 1; /* USB Active Endpoint */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t naksts : 1; /* NAK Status */ + const uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL0. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL0_s ALT_USB_DEV_DIEPCTL0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL0 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL0_OFST 0x100 +/* The address of the ALT_USB_DEV_DIEPCTL0 register. */ +#define ALT_USB_DEV_DIEPCTL0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL0_OFST)) + +/* + * Register : Device IN Endpoint 0 Interrupt Register - diepint0 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT0_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT0_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT0_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT0_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT0_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT0_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT0_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT0_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT0_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT0_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT0_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT0_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT0_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT0_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT0_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT0_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT0_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT0_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT0_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT0_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT0_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT0_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT0_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT0_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TMO register field. */ +#define ALT_USB_DEV_DIEPINT0_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TMO register field. */ +#define ALT_USB_DEV_DIEPINT0_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_TMO register field. */ +#define ALT_USB_DEV_DIEPINT0_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT0_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT0_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT0_TMO register field. */ +#define ALT_USB_DEV_DIEPINT0_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT0_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT0_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT0_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT0_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT0_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT0_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT0_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT0_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT0_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT0_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT0_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT0_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT0_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT0_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT0_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT0_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT0_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT0_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT0_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT0_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT0_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT0_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT0_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT0_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT0_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT0_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT0_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT0_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT0_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT0_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT0. + */ +struct ALT_USB_DEV_DIEPINT0_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT0. */ +typedef volatile struct ALT_USB_DEV_DIEPINT0_s ALT_USB_DEV_DIEPINT0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT0 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT0_OFST 0x108 +/* The address of the ALT_USB_DEV_DIEPINT0 register. */ +#define ALT_USB_DEV_DIEPINT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT0_OFST)) + +/* + * Register : Device IN Endpoint 0 Transfer Size Register - dieptsiz0 + * + * The application must modify this register before enabling endpoint 0. Once + * endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 + * Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core modifies this + * register. The application can only read this register once the core has cleared + * the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 1 to + * 15. When Scatter/Gather DMA mode is enabled, this register must not be + * programmed by the application. If the application reads this register when + * Scatter/Gather DMA mode is enabled, the core returns all zeros. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------- + * [6:0] | RW | 0x0 | Transfer Size + * [18:7] | ??? | 0x0 | *UNDEFINED* + * [20:19] | RW | 0x0 | Packet Count + * [31:21] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_WIDTH 7 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0. This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_MSB 20 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_SET_MSK 0x00180000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_CLR_MSK 0xffe7ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ0_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_GET(value) (((value) & 0x00180000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x00180000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ0. + */ +struct ALT_USB_DEV_DIEPTSIZ0_s +{ + uint32_t xfersize : 7; /* Transfer Size */ + uint32_t : 12; /* *UNDEFINED* */ + uint32_t pktcnt : 2; /* Packet Count */ + uint32_t : 11; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ0. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ0_s ALT_USB_DEV_DIEPTSIZ0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ0 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ0_OFST 0x110 +/* The address of the ALT_USB_DEV_DIEPTSIZ0 register. */ +#define ALT_USB_DEV_DIEPTSIZ0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ0_OFST)) + +/* + * Register : Device IN Endpoint 0 DMA Address Register - diepdma0 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma0 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */ +#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */ +#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */ +#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value. */ +#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value. */ +#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA0. + */ +struct ALT_USB_DEV_DIEPDMA0_s +{ + uint32_t diepdma0 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA0. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA0_s ALT_USB_DEV_DIEPDMA0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA0 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA0_OFST 0x114 +/* The address of the ALT_USB_DEV_DIEPDMA0 register. */ +#define ALT_USB_DEV_DIEPDMA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA0_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 0 - dtxfsts0 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS0. + */ +struct ALT_USB_DEV_DTXFSTS0_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS0. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS0_s ALT_USB_DEV_DTXFSTS0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS0 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS0_OFST 0x118 +/* The address of the ALT_USB_DEV_DTXFSTS0 register. */ +#define ALT_USB_DEV_DTXFSTS0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS0_OFST)) + +/* + * Register : Device IN Endpoint 0 DMA Buffer Address Register - diepdmab0 + * + * Endpoint 16. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab0 + * + * Used with Scatter/Gather DMA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */ +#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */ +#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */ +#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value. */ +#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value. */ +#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB0. + */ +struct ALT_USB_DEV_DIEPDMAB0_s +{ + const uint32_t diepdmab0 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB0. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB0_s ALT_USB_DEV_DIEPDMAB0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB0 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB0_OFST 0x11c +/* The address of the ALT_USB_DEV_DIEPDMAB0 register. */ +#define ALT_USB_DEV_DIEPDMAB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB0_OFST)) + +/* + * Register : Device Control IN Endpoint 1 Control Register - diepctl1 + * + * Endpoint_number: 1 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL1_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL1_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL1_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL1_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL1_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL1_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL1_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL1_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL1_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL1_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL1_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL1_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL1_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL1_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL1_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL1_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL1_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL1_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL1_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL1_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL1_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL1_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL1_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL1_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL1_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL1_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL1_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL1_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL1_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL1_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL1_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL1_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL1_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL1_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL1_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL1_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL1_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL1_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL1_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL1_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL1_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL1_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL1_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL1_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL1_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL1_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL1_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL1_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL1_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL1_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL1_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL1_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL1_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL1_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL1_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL1_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL1_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL1_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL1_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL1_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL1_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL1_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL1_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL1_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL1_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL1_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL1_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL1_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL1_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL1_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL1_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL1_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL1_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL1_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL1_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL1_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL1_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL1_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL1_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL1_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL1_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL1_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL1_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL1_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL1_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL1_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL1_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL1_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL1_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL1_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL1_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL1_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL1_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL1_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL1_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL1_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL1_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL1_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL1_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL1_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL1_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL1_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL1_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL1_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL1_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL1_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL1_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL1_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL1_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL1_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL1_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL1_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL1_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL1_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL1_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL1_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL1_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL1_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL1_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL1_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL1_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL1_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL1. + */ +struct ALT_USB_DEV_DIEPCTL1_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL1. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL1_s ALT_USB_DEV_DIEPCTL1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL1 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL1_OFST 0x120 +/* The address of the ALT_USB_DEV_DIEPCTL1 register. */ +#define ALT_USB_DEV_DIEPCTL1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL1_OFST)) + +/* + * Register : Device IN Endpoint 1 Interrupt Register - diepint1 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt ( + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT1_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT1_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT1_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT1_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT1_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT1_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT1_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT1_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT1_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT1_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT1_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT1_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT1_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT1_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT1_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT1_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT1_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT1_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT1_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT1_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT1_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT1_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT1_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT1_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TMO register field. */ +#define ALT_USB_DEV_DIEPINT1_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TMO register field. */ +#define ALT_USB_DEV_DIEPINT1_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_TMO register field. */ +#define ALT_USB_DEV_DIEPINT1_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT1_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT1_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT1_TMO register field. */ +#define ALT_USB_DEV_DIEPINT1_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT1_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT1_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT1_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT1_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT1_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT1_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT1_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT1_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT1_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT1_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT1_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT1_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT1_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT1_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT1_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT1_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT1_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT1_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT1_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT1_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt ( - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT1_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT1_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT1_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT1_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT1_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT1_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT1_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT1_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT1_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT1_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT1. + */ +struct ALT_USB_DEV_DIEPINT1_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt ( */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT1. */ +typedef volatile struct ALT_USB_DEV_DIEPINT1_s ALT_USB_DEV_DIEPINT1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT1 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT1_OFST 0x128 +/* The address of the ALT_USB_DEV_DIEPINT1 register. */ +#define ALT_USB_DEV_DIEPINT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT1_OFST)) + +/* + * Register : Device IN Endpoint 1 Transfer Size Register - dieptsiz1 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ1_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ1_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ1_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ1_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ1. + */ +struct ALT_USB_DEV_DIEPTSIZ1_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ1. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ1_s ALT_USB_DEV_DIEPTSIZ1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ1 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ1_OFST 0x130 +/* The address of the ALT_USB_DEV_DIEPTSIZ1 register. */ +#define ALT_USB_DEV_DIEPTSIZ1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ1_OFST)) + +/* + * Register : Device IN Endpoint 1 DMA Address Registe - diepdma1 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma1 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */ +#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */ +#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */ +#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value. */ +#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value. */ +#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA1. + */ +struct ALT_USB_DEV_DIEPDMA1_s +{ + uint32_t diepdma1 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA1. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA1_s ALT_USB_DEV_DIEPDMA1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA1 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA1_OFST 0x134 +/* The address of the ALT_USB_DEV_DIEPDMA1 register. */ +#define ALT_USB_DEV_DIEPDMA1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA1_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 1 - dtxfsts1 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS1. + */ +struct ALT_USB_DEV_DTXFSTS1_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS1. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS1_s ALT_USB_DEV_DTXFSTS1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS1 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS1_OFST 0x138 +/* The address of the ALT_USB_DEV_DTXFSTS1 register. */ +#define ALT_USB_DEV_DTXFSTS1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS1_OFST)) + +/* + * Register : Device IN Endpoint 1 DMA Buffer Address Register - diepdmab1 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab1 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */ +#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */ +#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */ +#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value. */ +#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value. */ +#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB1. + */ +struct ALT_USB_DEV_DIEPDMAB1_s +{ + const uint32_t diepdmab1 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB1. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB1_s ALT_USB_DEV_DIEPDMAB1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB1 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB1_OFST 0x13c +/* The address of the ALT_USB_DEV_DIEPDMAB1 register. */ +#define ALT_USB_DEV_DIEPDMAB1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB1_OFST)) + +/* + * Register : Device Control IN Endpoint 2 Control Register - diepctl2 + * + * Endpoint_number: 2 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL2_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL2_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL2_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL2_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL2_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL2_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL2_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL2_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL2_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL2_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL2_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL2_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL2_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL2_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL2_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL2_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL2_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL2_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL2_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL2_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL2_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL2_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL2_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL2_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL2_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL2_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL2_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL2_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL2_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL2_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL2_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL2_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL2_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL2_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL2_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL2_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL2_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL2_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL2_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL2_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL2_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL2_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL2_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL2_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL2_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL2_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL2_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL2_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL2_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL2_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL2_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL2_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL2_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL2_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL2_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL2_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL2_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL2_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL2_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL2_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL2_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL2_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL2_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL2_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL2_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL2_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL2_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL2_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL2_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL2_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL2_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL2_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL2_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL2_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL2_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL2_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL2_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL2_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL2_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL2_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL2_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL2_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL2_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL2_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL2_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL2_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL2_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL2_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL2_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL2_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL2_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL2_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL2_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL2_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL2_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL2_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL2_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL2_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL2_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL2_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL2_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL2_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL2_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL2_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL2_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL2_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL2_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL2_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL2_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL2_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL2_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL2_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL2_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL2_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL2_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL2_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL2_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL2_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL2_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL2_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL2_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL2_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL2. + */ +struct ALT_USB_DEV_DIEPCTL2_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL2. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL2_s ALT_USB_DEV_DIEPCTL2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL2 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL2_OFST 0x140 +/* The address of the ALT_USB_DEV_DIEPCTL2 register. */ +#define ALT_USB_DEV_DIEPCTL2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL2_OFST)) + +/* + * Register : Device IN Endpoint 2 Interrupt Register - diepint2 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT2_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT2_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT2_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT2_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT2_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT2_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT2_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT2_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT2_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT2_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT2_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT2_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT2_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT2_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT2_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT2_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT2_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT2_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT2_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT2_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT2_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT2_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT2_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT2_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TMO register field. */ +#define ALT_USB_DEV_DIEPINT2_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TMO register field. */ +#define ALT_USB_DEV_DIEPINT2_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_TMO register field. */ +#define ALT_USB_DEV_DIEPINT2_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT2_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT2_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT2_TMO register field. */ +#define ALT_USB_DEV_DIEPINT2_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT2_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT2_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT2_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT2_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT2_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT2_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT2_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT2_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT2_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT2_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT2_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT2_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT2_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT2_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT2_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT2_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT2_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT2_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT2_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT2_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT2_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT2_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT2_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT2_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT2_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT2_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT2_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT2_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT2_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT2_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT2. + */ +struct ALT_USB_DEV_DIEPINT2_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT2. */ +typedef volatile struct ALT_USB_DEV_DIEPINT2_s ALT_USB_DEV_DIEPINT2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT2 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT2_OFST 0x148 +/* The address of the ALT_USB_DEV_DIEPINT2 register. */ +#define ALT_USB_DEV_DIEPINT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT2_OFST)) + +/* + * Register : Device IN Endpoint 2 Transfer Size Register - dieptsiz2 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ2_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ2_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ2_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ2_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ2. + */ +struct ALT_USB_DEV_DIEPTSIZ2_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ2. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ2_s ALT_USB_DEV_DIEPTSIZ2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ2 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ2_OFST 0x150 +/* The address of the ALT_USB_DEV_DIEPTSIZ2 register. */ +#define ALT_USB_DEV_DIEPTSIZ2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ2_OFST)) + +/* + * Register : Device IN Endpoint 2 DMA Address Register - diepdma2 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma2 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */ +#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */ +#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */ +#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value. */ +#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value. */ +#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA2. + */ +struct ALT_USB_DEV_DIEPDMA2_s +{ + uint32_t diepdma2 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA2. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA2_s ALT_USB_DEV_DIEPDMA2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA2 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA2_OFST 0x154 +/* The address of the ALT_USB_DEV_DIEPDMA2 register. */ +#define ALT_USB_DEV_DIEPDMA2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA2_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 2 - DTXFSTS2 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS2. + */ +struct ALT_USB_DEV_DTXFSTS2_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS2. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS2_s ALT_USB_DEV_DTXFSTS2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS2 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS2_OFST 0x158 +/* The address of the ALT_USB_DEV_DTXFSTS2 register. */ +#define ALT_USB_DEV_DTXFSTS2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS2_OFST)) + +/* + * Register : Device IN Endpoint 2 DMA Buffer Address Register - diepdmab2 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab2 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */ +#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */ +#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */ +#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value. */ +#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value. */ +#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB2. + */ +struct ALT_USB_DEV_DIEPDMAB2_s +{ + const uint32_t diepdmab2 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB2. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB2_s ALT_USB_DEV_DIEPDMAB2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB2 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB2_OFST 0x15c +/* The address of the ALT_USB_DEV_DIEPDMAB2 register. */ +#define ALT_USB_DEV_DIEPDMAB2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB2_OFST)) + +/* + * Register : Device Control IN Endpoint 3 Control Register - diepctl3 + * + * Endpoint_number: 3 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL3_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL3_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL3_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL3_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL3_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL3_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL3_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL3_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL3_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL3_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL3_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL3_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL3_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL3_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL3_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL3_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL3_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL3_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL3_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL3_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL3_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL3_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL3_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL3_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL3_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL3_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL3_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL3_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL3_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL3_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL3_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL3_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL3_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL3_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL3_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL3_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL3_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL3_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL3_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL3_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL3_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL3_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL3_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL3_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL3_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL3_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL3_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL3_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL3_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL3_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL3_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL3_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL3_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL3_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL3_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL3_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL3_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL3_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL3_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL3_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL3_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL3_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL3_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL3_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL3_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL3_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL3_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL3_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL3_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL3_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL3_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL3_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL3_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL3_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL3_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL3_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL3_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL3_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL3_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL3_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL3_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL3_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL3_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL3_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL3_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL3_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL3_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL3_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL3_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL3_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL3_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL3_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL3_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL3_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL3_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL3_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL3_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL3_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL3_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL3_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL3_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL3_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL3_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL3_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL3_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL3_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL3_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL3_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL3_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL3_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL3_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL3_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL3_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL3_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL3_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL3_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL3_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL3_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL3_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL3_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL3_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL3_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL3. + */ +struct ALT_USB_DEV_DIEPCTL3_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL3. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL3_s ALT_USB_DEV_DIEPCTL3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL3 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL3_OFST 0x160 +/* The address of the ALT_USB_DEV_DIEPCTL3 register. */ +#define ALT_USB_DEV_DIEPCTL3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL3_OFST)) + +/* + * Register : Device IN Endpoint 3 Interrupt Register - diepint3 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT3_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT3_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT3_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT3_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT3_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT3_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT3_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT3_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT3_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT3_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT3_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT3_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT3_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT3_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT3_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT3_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT3_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT3_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT3_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT3_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT3_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT3_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT3_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT3_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TMO register field. */ +#define ALT_USB_DEV_DIEPINT3_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TMO register field. */ +#define ALT_USB_DEV_DIEPINT3_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_TMO register field. */ +#define ALT_USB_DEV_DIEPINT3_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT3_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT3_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT3_TMO register field. */ +#define ALT_USB_DEV_DIEPINT3_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT3_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT3_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT3_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT3_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT3_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT3_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT3_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT3_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT3_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT3_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT3_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT3_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT3_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT3_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT3_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT3_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT3_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT3_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT3_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT3_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT3_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT3_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT3_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT3_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT3_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT3_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT3_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT3_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT3_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT3_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT3. + */ +struct ALT_USB_DEV_DIEPINT3_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT3. */ +typedef volatile struct ALT_USB_DEV_DIEPINT3_s ALT_USB_DEV_DIEPINT3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT3 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT3_OFST 0x168 +/* The address of the ALT_USB_DEV_DIEPINT3 register. */ +#define ALT_USB_DEV_DIEPINT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT3_OFST)) + +/* + * Register : Device IN Endpoint 3 Transfer Size Registe - dieptsiz3 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ3_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ3_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ3_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ3_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ3. + */ +struct ALT_USB_DEV_DIEPTSIZ3_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ3. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ3_s ALT_USB_DEV_DIEPTSIZ3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ3 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ3_OFST 0x170 +/* The address of the ALT_USB_DEV_DIEPTSIZ3 register. */ +#define ALT_USB_DEV_DIEPTSIZ3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ3_OFST)) + +/* + * Register : Device IN Endpoint 3 DMA Address Registe - diepdma3 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma3 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */ +#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */ +#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */ +#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value. */ +#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value. */ +#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA3. + */ +struct ALT_USB_DEV_DIEPDMA3_s +{ + uint32_t diepdma3 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA3. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA3_s ALT_USB_DEV_DIEPDMA3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA3 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA3_OFST 0x174 +/* The address of the ALT_USB_DEV_DIEPDMA3 register. */ +#define ALT_USB_DEV_DIEPDMA3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA3_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 3 - dtxfsts3 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS3. + */ +struct ALT_USB_DEV_DTXFSTS3_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS3. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS3_s ALT_USB_DEV_DTXFSTS3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS3 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS3_OFST 0x178 +/* The address of the ALT_USB_DEV_DTXFSTS3 register. */ +#define ALT_USB_DEV_DTXFSTS3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS3_OFST)) + +/* + * Register : Device IN Endpoint 3 DMA Buffer Address Register - diepdmab3 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab3 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */ +#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */ +#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */ +#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value. */ +#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value. */ +#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB3. + */ +struct ALT_USB_DEV_DIEPDMAB3_s +{ + const uint32_t diepdmab3 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB3. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB3_s ALT_USB_DEV_DIEPDMAB3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB3 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB3_OFST 0x17c +/* The address of the ALT_USB_DEV_DIEPDMAB3 register. */ +#define ALT_USB_DEV_DIEPDMAB3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB3_OFST)) + +/* + * Register : Device Control IN Endpoint 4 Control Register - diepctl4 + * + * Endpoint_number: 4 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL4_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL4_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL4_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL4_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL4_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL4_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL4_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL4_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL4_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL4_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL4_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL4_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL4_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL4_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL4_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL4_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL4_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL4_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL4_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL4_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL4_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL4_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL4_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL4_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL4_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL4_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL4_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL4_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL4_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL4_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL4_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL4_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL4_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL4_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL4_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL4_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL4_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL4_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL4_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL4_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL4_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL4_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL4_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL4_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL4_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL4_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL4_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL4_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL4_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL4_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL4_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL4_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL4_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL4_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL4_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL4_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL4_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL4_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL4_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL4_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL4_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL4_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL4_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL4_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL4_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL4_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL4_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL4_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL4_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL4_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL4_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL4_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL4_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL4_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL4_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL4_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL4_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL4_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL4_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL4_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL4_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL4_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL4_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL4_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL4_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL4_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL4_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL4_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL4_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL4_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL4_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL4_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL4_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL4_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL4_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL4_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL4_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL4_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL4_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL4_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL4_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL4_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL4_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL4_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL4_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL4_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL4_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL4_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL4_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL4_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL4_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL4_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL4_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL4_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL4_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL4_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL4_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL4_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL4_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL4_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL4_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL4_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL4. + */ +struct ALT_USB_DEV_DIEPCTL4_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL4. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL4_s ALT_USB_DEV_DIEPCTL4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL4 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL4_OFST 0x180 +/* The address of the ALT_USB_DEV_DIEPCTL4 register. */ +#define ALT_USB_DEV_DIEPCTL4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL4_OFST)) + +/* + * Register : Device IN Endpoint 4 Interrupt Register - diepint4 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT4_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT4_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT4_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT4_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT4_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT4_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT4_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT4_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT4_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT4_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT4_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT4_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT4_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT4_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT4_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT4_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT4_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT4_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT4_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT4_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT4_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT4_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT4_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT4_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TMO register field. */ +#define ALT_USB_DEV_DIEPINT4_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TMO register field. */ +#define ALT_USB_DEV_DIEPINT4_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_TMO register field. */ +#define ALT_USB_DEV_DIEPINT4_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT4_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT4_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT4_TMO register field. */ +#define ALT_USB_DEV_DIEPINT4_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT4_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT4_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT4_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT4_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT4_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT4_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT4_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT4_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT4_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT4_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT4_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT4_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT4_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT4_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT4_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT4_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT4_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT4_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT4_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT4_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT4_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT4_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT4_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT4_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT4_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT4_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT4_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT4_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT4_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT4_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT4. + */ +struct ALT_USB_DEV_DIEPINT4_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT4. */ +typedef volatile struct ALT_USB_DEV_DIEPINT4_s ALT_USB_DEV_DIEPINT4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT4 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT4_OFST 0x188 +/* The address of the ALT_USB_DEV_DIEPINT4 register. */ +#define ALT_USB_DEV_DIEPINT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT4_OFST)) + +/* + * Register : Device IN Endpoint 4 Transfer Size Register - dieptsiz4 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ4_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ4_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ4_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ4_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ4. + */ +struct ALT_USB_DEV_DIEPTSIZ4_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ4. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ4_s ALT_USB_DEV_DIEPTSIZ4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ4 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ4_OFST 0x190 +/* The address of the ALT_USB_DEV_DIEPTSIZ4 register. */ +#define ALT_USB_DEV_DIEPTSIZ4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ4_OFST)) + +/* + * Register : Device IN Endpoint 4 DMA Address Register - diepdma4 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma4 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */ +#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */ +#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */ +#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value. */ +#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value. */ +#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA4. + */ +struct ALT_USB_DEV_DIEPDMA4_s +{ + uint32_t diepdma4 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA4. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA4_s ALT_USB_DEV_DIEPDMA4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA4 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA4_OFST 0x194 +/* The address of the ALT_USB_DEV_DIEPDMA4 register. */ +#define ALT_USB_DEV_DIEPDMA4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA4_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 4 - dtxfsts4 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS4. + */ +struct ALT_USB_DEV_DTXFSTS4_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS4. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS4_s ALT_USB_DEV_DTXFSTS4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS4 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS4_OFST 0x198 +/* The address of the ALT_USB_DEV_DTXFSTS4 register. */ +#define ALT_USB_DEV_DTXFSTS4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS4_OFST)) + +/* + * Register : Device IN Endpoint 4 DMA Buffer Address Register - diepdmab4 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab4 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */ +#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */ +#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */ +#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value. */ +#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value. */ +#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB4. + */ +struct ALT_USB_DEV_DIEPDMAB4_s +{ + const uint32_t diepdmab4 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB4. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB4_s ALT_USB_DEV_DIEPDMAB4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB4 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB4_OFST 0x19c +/* The address of the ALT_USB_DEV_DIEPDMAB4 register. */ +#define ALT_USB_DEV_DIEPDMAB4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB4_OFST)) + +/* + * Register : Device Control IN Endpoint 5 Control Register - diepctl5 + * + * Endpoint_number: 5 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL5_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL5_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL5_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL5_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL5_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL5_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL5_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL5_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL5_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL5_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL5_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL5_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL5_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL5_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL5_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL5_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL5_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL5_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL5_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL5_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL5_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL5_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL5_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL5_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL5_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL5_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL5_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL5_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL5_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL5_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL5_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL5_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL5_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL5_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL5_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL5_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL5_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL5_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL5_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL5_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL5_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL5_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL5_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL5_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL5_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL5_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL5_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL5_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL5_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL5_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL5_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL5_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL5_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL5_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL5_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL5_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL5_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL5_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL5_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL5_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL5_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL5_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL5_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL5_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL5_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL5_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL5_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL5_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL5_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL5_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL5_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL5_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL5_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL5_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL5_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL5_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL5_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL5_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL5_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL5_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL5_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL5_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL5_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL5_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL5_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL5. + */ +struct ALT_USB_DEV_DIEPCTL5_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL5. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL5_s ALT_USB_DEV_DIEPCTL5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL5 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL5_OFST 0x1a0 +/* The address of the ALT_USB_DEV_DIEPCTL5 register. */ +#define ALT_USB_DEV_DIEPCTL5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL5_OFST)) + +/* + * Register : Device IN Endpoint 5 Interrupt Register - diepint5 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt ( + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT5_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT5_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT5_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT5_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT5_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT5_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT5_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT5_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT5_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT5_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT5_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT5_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT5_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT5_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT5_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT5_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT5_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT5_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT5_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT5_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT5_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT5_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT5_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT5_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TMO register field. */ +#define ALT_USB_DEV_DIEPINT5_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TMO register field. */ +#define ALT_USB_DEV_DIEPINT5_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_TMO register field. */ +#define ALT_USB_DEV_DIEPINT5_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT5_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT5_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT5_TMO register field. */ +#define ALT_USB_DEV_DIEPINT5_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT5_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT5_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT5_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT5_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT5_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT5_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT5_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT5_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT5_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT5_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT5_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT5_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT5_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT5_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT5_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT5_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT5_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT5_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT5_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT5_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt ( - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT5_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT5_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT5_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT5_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT5_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT5_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT5_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT5_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT5_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT5_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT5. + */ +struct ALT_USB_DEV_DIEPINT5_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt ( */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT5. */ +typedef volatile struct ALT_USB_DEV_DIEPINT5_s ALT_USB_DEV_DIEPINT5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT5 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT5_OFST 0x1a8 +/* The address of the ALT_USB_DEV_DIEPINT5 register. */ +#define ALT_USB_DEV_DIEPINT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT5_OFST)) + +/* + * Register : Device IN Endpoint 5 Transfer Size Register - dieptsiz5 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ5_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ5_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ5_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ5_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ5. + */ +struct ALT_USB_DEV_DIEPTSIZ5_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ5. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ5_s ALT_USB_DEV_DIEPTSIZ5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ5 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ5_OFST 0x1b0 +/* The address of the ALT_USB_DEV_DIEPTSIZ5 register. */ +#define ALT_USB_DEV_DIEPTSIZ5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ5_OFST)) + +/* + * Register : Device IN Endpoint 5 DMA Address Register - diepdma5 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma5 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */ +#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */ +#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */ +#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value. */ +#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value. */ +#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA5. + */ +struct ALT_USB_DEV_DIEPDMA5_s +{ + uint32_t diepdma5 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA5. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA5_s ALT_USB_DEV_DIEPDMA5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA5 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA5_OFST 0x1b4 +/* The address of the ALT_USB_DEV_DIEPDMA5 register. */ +#define ALT_USB_DEV_DIEPDMA5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA5_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 5 - dtxfsts5 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS5. + */ +struct ALT_USB_DEV_DTXFSTS5_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS5. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS5_s ALT_USB_DEV_DTXFSTS5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS5 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS5_OFST 0x1b8 +/* The address of the ALT_USB_DEV_DTXFSTS5 register. */ +#define ALT_USB_DEV_DTXFSTS5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS5_OFST)) + +/* + * Register : Device IN Endpoint 5 DMA Buffer Address Register - diepdmab5 + * + * Device IN Endpoint 1 Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------------------------ + * [31:0] | R | Unknown | Device IN Endpoint 1 Buffer Address + * + */ +/* + * Field : Device IN Endpoint 1 Buffer Address - diepdmab5 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */ +#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */ +#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */ +#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value. */ +#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value. */ +#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB5. + */ +struct ALT_USB_DEV_DIEPDMAB5_s +{ + const uint32_t diepdmab5 : 32; /* Device IN Endpoint 1 Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB5. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB5_s ALT_USB_DEV_DIEPDMAB5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB5 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB5_OFST 0x1bc +/* The address of the ALT_USB_DEV_DIEPDMAB5 register. */ +#define ALT_USB_DEV_DIEPDMAB5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB5_OFST)) + +/* + * Register : Device Control IN Endpoint 6 Control Register - diepctl6 + * + * Endpoint_number: 6 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL6_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL6_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL6_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL6_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL6_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL6_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL6_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL6_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL6_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL6_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL6_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL6_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL6_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL6_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL6_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL6_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL6_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL6_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL6_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL6_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL6_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL6_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL6_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL6_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL6_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL6_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL6_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL6_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL6_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL6_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL6_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL6_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL6_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL6_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL6_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL6_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL6_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL6_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL6_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL6_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL6_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL6_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL6_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL6_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL6_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL6_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL6_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL6_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL6_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL6_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL6_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL6_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL6_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL6_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL6_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL6_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL6_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL6_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL6_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL6_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL6_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL6_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL6_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL6_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL6_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL6_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL6_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL6_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL6_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL6_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL6_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL6_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL6_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL6_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL6_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL6_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL6_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL6_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL6_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL6_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL6_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL6_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL6_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL6_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL6_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL6_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL6_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL6_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL6_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL6_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL6_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL6_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL6_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL6_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL6_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL6_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL6_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL6_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL6_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL6_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL6_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL6_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL6_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL6_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL6_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL6_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL6_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL6_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL6_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL6_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL6_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL6_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL6_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL6_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL6_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL6_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL6_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL6_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL6_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL6_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL6_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL6_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL6. + */ +struct ALT_USB_DEV_DIEPCTL6_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL6. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL6_s ALT_USB_DEV_DIEPCTL6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL6 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL6_OFST 0x1c0 +/* The address of the ALT_USB_DEV_DIEPCTL6 register. */ +#define ALT_USB_DEV_DIEPCTL6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL6_OFST)) + +/* + * Register : Device IN Endpoint 6 Interrupt Register - diepint6 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT6_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT6_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT6_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT6_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT6_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT6_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT6_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT6_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT6_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT6_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT6_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT6_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT6_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT6_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT6_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT6_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT6_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT6_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT6_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT6_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT6_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT6_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT6_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT6_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TMO register field. */ +#define ALT_USB_DEV_DIEPINT6_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TMO register field. */ +#define ALT_USB_DEV_DIEPINT6_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_TMO register field. */ +#define ALT_USB_DEV_DIEPINT6_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT6_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT6_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT6_TMO register field. */ +#define ALT_USB_DEV_DIEPINT6_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT6_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT6_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT6_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT6_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT6_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT6_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT6_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT6_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT6_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT6_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT6_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT6_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT6_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT6_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT6_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT6_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT6_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT6_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT6_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT6_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT6_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT6_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT6_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT6_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT6_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT6_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT6_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT6_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT6_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT6_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT6. + */ +struct ALT_USB_DEV_DIEPINT6_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT6. */ +typedef volatile struct ALT_USB_DEV_DIEPINT6_s ALT_USB_DEV_DIEPINT6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT6 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT6_OFST 0x1c8 +/* The address of the ALT_USB_DEV_DIEPINT6 register. */ +#define ALT_USB_DEV_DIEPINT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT6_OFST)) + +/* + * Register : Device IN Endpoint 6 Transfer Size Register - dieptsiz6 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ6_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ6_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ6_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ6_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ6. + */ +struct ALT_USB_DEV_DIEPTSIZ6_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ6. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ6_s ALT_USB_DEV_DIEPTSIZ6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ6 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ6_OFST 0x1d0 +/* The address of the ALT_USB_DEV_DIEPTSIZ6 register. */ +#define ALT_USB_DEV_DIEPTSIZ6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ6_OFST)) + +/* + * Register : Device IN Endpoint 6 DMA Address Register - diepdma6 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma6 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */ +#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */ +#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */ +#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value. */ +#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value. */ +#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA6. + */ +struct ALT_USB_DEV_DIEPDMA6_s +{ + uint32_t diepdma6 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA6. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA6_s ALT_USB_DEV_DIEPDMA6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA6 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA6_OFST 0x1d4 +/* The address of the ALT_USB_DEV_DIEPDMA6 register. */ +#define ALT_USB_DEV_DIEPDMA6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA6_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 6 - dtxfsts6 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS6. + */ +struct ALT_USB_DEV_DTXFSTS6_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS6. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS6_s ALT_USB_DEV_DTXFSTS6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS6 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS6_OFST 0x1d8 +/* The address of the ALT_USB_DEV_DTXFSTS6 register. */ +#define ALT_USB_DEV_DTXFSTS6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS6_OFST)) + +/* + * Register : Device IN Endpoint 6 DMA Buffer Address Register - diepdmab6 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab6 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */ +#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */ +#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */ +#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value. */ +#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value. */ +#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB6. + */ +struct ALT_USB_DEV_DIEPDMAB6_s +{ + const uint32_t diepdmab6 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB6. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB6_s ALT_USB_DEV_DIEPDMAB6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB6 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB6_OFST 0x1dc +/* The address of the ALT_USB_DEV_DIEPDMAB6 register. */ +#define ALT_USB_DEV_DIEPDMAB6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB6_OFST)) + +/* + * Register : Device Control IN Endpoint 7 Control Register - diepctl7 + * + * Endpoint_number: 7 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL7_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL7_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL7_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL7_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL7_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL7_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL7_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL7_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL7_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL7_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL7_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL7_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL7_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL7_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL7_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL7_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL7_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL7_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL7_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL7_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL7_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL7_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL7_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL7_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL7_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL7_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL7_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL7_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL7_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL7_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL7_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL7_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL7_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL7_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL7_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL7_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL7_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL7_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL7_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL7_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL7_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL7_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL7_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL7_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL7_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL7_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL7_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL7_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL7_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL7_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL7_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL7_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL7_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL7_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL7_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL7_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL7_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL7_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL7_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL7_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL7_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL7_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL7_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL7_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL7_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL7_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL7_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL7_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL7_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL7_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL7_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL7_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL7_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL7_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL7_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL7_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL7_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL7_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL7_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL7_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL7_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL7_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL7_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL7_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL7_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL7_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL7_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL7_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL7_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL7_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL7_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL7_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL7_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL7_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL7_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL7_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL7_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL7_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL7_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL7_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL7_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL7_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL7_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL7_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL7_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL7_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL7_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL7_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL7_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL7_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL7_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL7_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL7_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL7_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL7_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL7_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL7_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL7_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL7_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL7_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL7_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL7_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL7. + */ +struct ALT_USB_DEV_DIEPCTL7_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL7. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL7_s ALT_USB_DEV_DIEPCTL7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL7 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL7_OFST 0x1e0 +/* The address of the ALT_USB_DEV_DIEPCTL7 register. */ +#define ALT_USB_DEV_DIEPCTL7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL7_OFST)) + +/* + * Register : Device IN Endpoint 7 Interrupt Register - diepint7 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT7_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT7_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT7_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT7_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT7_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT7_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT7_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT7_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT7_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT7_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT7_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT7_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT7_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT7_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT7_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT7_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT7_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT7_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT7_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT7_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT7_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT7_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT7_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT7_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TMO register field. */ +#define ALT_USB_DEV_DIEPINT7_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TMO register field. */ +#define ALT_USB_DEV_DIEPINT7_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_TMO register field. */ +#define ALT_USB_DEV_DIEPINT7_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT7_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT7_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT7_TMO register field. */ +#define ALT_USB_DEV_DIEPINT7_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT7_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT7_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT7_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT7_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT7_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT7_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT7_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT7_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT7_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT7_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT7_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT7_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT7_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT7_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT7_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT7_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT7_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT7_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT7_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT7_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT7_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT7_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT7_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT7_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT7_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT7_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT7_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT7_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT7_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT7_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT7. + */ +struct ALT_USB_DEV_DIEPINT7_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT7. */ +typedef volatile struct ALT_USB_DEV_DIEPINT7_s ALT_USB_DEV_DIEPINT7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT7 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT7_OFST 0x1e8 +/* The address of the ALT_USB_DEV_DIEPINT7 register. */ +#define ALT_USB_DEV_DIEPINT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT7_OFST)) + +/* + * Register : Device IN Endpoint 7 Transfer Size Register - dieptsiz7 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ7_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ7_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ7_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ7_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ7. + */ +struct ALT_USB_DEV_DIEPTSIZ7_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ7. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ7_s ALT_USB_DEV_DIEPTSIZ7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ7 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ7_OFST 0x1f0 +/* The address of the ALT_USB_DEV_DIEPTSIZ7 register. */ +#define ALT_USB_DEV_DIEPTSIZ7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ7_OFST)) + +/* + * Register : Device IN Endpoint 7 DMA Address Register - diepdma7 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma7 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */ +#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */ +#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */ +#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value. */ +#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value. */ +#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA7. + */ +struct ALT_USB_DEV_DIEPDMA7_s +{ + uint32_t diepdma7 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA7. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA7_s ALT_USB_DEV_DIEPDMA7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA7 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA7_OFST 0x1f4 +/* The address of the ALT_USB_DEV_DIEPDMA7 register. */ +#define ALT_USB_DEV_DIEPDMA7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA7_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 7 - dtxfsts7 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS7. + */ +struct ALT_USB_DEV_DTXFSTS7_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS7. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS7_s ALT_USB_DEV_DTXFSTS7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS7 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS7_OFST 0x1f8 +/* The address of the ALT_USB_DEV_DTXFSTS7 register. */ +#define ALT_USB_DEV_DTXFSTS7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS7_OFST)) + +/* + * Register : Device IN Endpoint 7 DMA Buffer Address Register - diepdmab7 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab7 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */ +#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */ +#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */ +#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value. */ +#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value. */ +#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB7. + */ +struct ALT_USB_DEV_DIEPDMAB7_s +{ + const uint32_t diepdmab7 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB7. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB7_s ALT_USB_DEV_DIEPDMAB7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB7 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB7_OFST 0x1fc +/* The address of the ALT_USB_DEV_DIEPDMAB7 register. */ +#define ALT_USB_DEV_DIEPDMAB7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB7_OFST)) + +/* + * Register : Device Control IN Endpoint 8 Control Register - diepctl8 + * + * Endpoint_number: 8 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL8_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL8_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL8_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL8_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL8_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL8_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL8_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL8_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL8_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL8_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL8_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL8_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL8_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL8_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL8_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL8_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL8_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL8_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL8_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL8_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL8_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL8_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL8_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL8_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL8_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL8_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL8_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL8_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL8_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL8_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL8_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL8_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL8_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL8_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL8_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL8_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL8_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL8_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL8_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL8_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL8_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL8_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL8_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL8_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL8_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL8_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL8_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL8_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL8_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL8_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL8_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL8_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL8_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL8_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL8_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL8_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL8_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL8_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL8_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL8_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL8_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL8_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL8_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL8_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL8_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL8_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL8_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL8_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL8_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL8_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL8_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL8_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL8_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL8_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL8_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL8_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL8_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL8_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL8_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL8_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL8_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL8_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL8_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL8_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL8_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL8_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL8_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL8_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL8_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL8_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL8_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL8_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL8_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL8_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL8_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL8_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL8_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL8_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL8_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL8_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL8_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL8_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL8_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL8_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL8_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL8_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL8_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL8_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL8_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL8_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL8_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL8_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL8_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL8_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL8_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL8_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL8_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL8_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL8_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL8_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL8_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL8_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL8. + */ +struct ALT_USB_DEV_DIEPCTL8_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL8. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL8_s ALT_USB_DEV_DIEPCTL8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL8 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL8_OFST 0x200 +/* The address of the ALT_USB_DEV_DIEPCTL8 register. */ +#define ALT_USB_DEV_DIEPCTL8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL8_OFST)) + +/* + * Register : Device IN Endpoint 8 Interrupt Register - diepint8 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt ( + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT8_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT8_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT8_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT8_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT8_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT8_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT8_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT8_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT8_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT8_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT8_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT8_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT8_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT8_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT8_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT8_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT8_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT8_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT8_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT8_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT8_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT8_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT8_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT8_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TMO register field. */ +#define ALT_USB_DEV_DIEPINT8_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TMO register field. */ +#define ALT_USB_DEV_DIEPINT8_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_TMO register field. */ +#define ALT_USB_DEV_DIEPINT8_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT8_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT8_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT8_TMO register field. */ +#define ALT_USB_DEV_DIEPINT8_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT8_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT8_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT8_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT8_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT8_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT8_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT8_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT8_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT8_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT8_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT8_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT8_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT8_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT8_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT8_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT8_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT8_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT8_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT8_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT8_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt ( - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT8_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT8_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT8_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT8_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT8_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT8_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT8_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT8_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT8_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT8_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT8. + */ +struct ALT_USB_DEV_DIEPINT8_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt ( */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT8. */ +typedef volatile struct ALT_USB_DEV_DIEPINT8_s ALT_USB_DEV_DIEPINT8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT8 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT8_OFST 0x208 +/* The address of the ALT_USB_DEV_DIEPINT8 register. */ +#define ALT_USB_DEV_DIEPINT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT8_OFST)) + +/* + * Register : Device IN Endpoint 8 Transfer Size Register - dieptsiz8 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints only + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ8_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints only - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ8_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ8_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ8_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ8. + */ +struct ALT_USB_DEV_DIEPTSIZ8_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints only */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ8. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ8_s ALT_USB_DEV_DIEPTSIZ8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ8 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ8_OFST 0x210 +/* The address of the ALT_USB_DEV_DIEPTSIZ8 register. */ +#define ALT_USB_DEV_DIEPTSIZ8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ8_OFST)) + +/* + * Register : Device IN Endpoint 8 DMA Address Register - diepdma8 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma8 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */ +#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */ +#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */ +#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value. */ +#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value. */ +#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA8. + */ +struct ALT_USB_DEV_DIEPDMA8_s +{ + uint32_t diepdma8 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA8. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA8_s ALT_USB_DEV_DIEPDMA8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA8 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA8_OFST 0x214 +/* The address of the ALT_USB_DEV_DIEPDMA8 register. */ +#define ALT_USB_DEV_DIEPDMA8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA8_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 8 - dtxfsts8 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS8. + */ +struct ALT_USB_DEV_DTXFSTS8_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS8. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS8_s ALT_USB_DEV_DTXFSTS8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS8 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS8_OFST 0x218 +/* The address of the ALT_USB_DEV_DTXFSTS8 register. */ +#define ALT_USB_DEV_DTXFSTS8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS8_OFST)) + +/* + * Register : Device IN Endpoint 8 DMA Buffer Address Register - diepdmab8 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab8 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */ +#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */ +#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */ +#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value. */ +#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value. */ +#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB8. + */ +struct ALT_USB_DEV_DIEPDMAB8_s +{ + const uint32_t diepdmab8 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB8. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB8_s ALT_USB_DEV_DIEPDMAB8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB8 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB8_OFST 0x21c +/* The address of the ALT_USB_DEV_DIEPDMAB8 register. */ +#define ALT_USB_DEV_DIEPDMAB8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB8_OFST)) + +/* + * Register : Device Control IN Endpoint 9 Control Register - diepctl9 + * + * Endpoint_number: 9 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL9_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL9_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL9_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL9_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL9_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL9_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL9_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL9_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL9_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL9_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL9_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL9_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL9_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL9_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL9_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL9_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL9_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL9_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL9_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL9_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL9_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL9_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL9_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL9_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL9_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL9_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL9_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL9_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL9_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL9_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL9_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL9_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL9_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL9_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL9_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL9_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL9_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL9_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL9_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL9_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL9_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL9_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL9_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL9_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL9_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL9_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL9_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL9_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL9_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL9_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL9_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL9_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL9_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL9_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL9_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL9_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL9_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL9_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL9_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL9_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL9_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL9_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL9_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL9_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL9_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL9_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL9_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL9_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL9_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL9_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL9_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL9_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL9_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL9_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL9_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL9_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL9_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL9_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL9_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL9_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL9_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL9_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL9_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL9_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL9_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL9_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL9_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL9_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL9_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL9_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL9_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL9_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL9_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL9_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL9_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL9_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL9_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL9_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL9_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL9_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL9_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL9_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL9_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL9_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL9_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL9_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL9_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL9_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL9_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL9_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL9_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL9_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL9_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL9_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL9_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL9_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL9_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL9_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL9_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL9_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL9_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL9_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL9. + */ +struct ALT_USB_DEV_DIEPCTL9_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL9. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL9_s ALT_USB_DEV_DIEPCTL9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL9 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL9_OFST 0x220 +/* The address of the ALT_USB_DEV_DIEPCTL9 register. */ +#define ALT_USB_DEV_DIEPCTL9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL9_OFST)) + +/* + * Register : Device IN Endpoint 9 Interrupt Register - diepint9 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT9_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT9_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT9_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT9_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT9_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT9_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT9_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT9_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT9_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT9_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT9_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT9_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT9_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT9_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT9_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT9_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT9_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT9_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT9_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT9_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT9_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT9_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT9_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT9_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TMO register field. */ +#define ALT_USB_DEV_DIEPINT9_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TMO register field. */ +#define ALT_USB_DEV_DIEPINT9_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_TMO register field. */ +#define ALT_USB_DEV_DIEPINT9_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT9_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT9_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT9_TMO register field. */ +#define ALT_USB_DEV_DIEPINT9_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT9_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT9_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT9_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT9_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT9_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT9_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT9_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT9_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT9_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT9_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT9_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT9_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT9_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT9_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT9_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT9_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT9_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT9_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT9_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT9_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT9_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT9_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT9_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT9_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT9_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT9_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT9_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT9_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT9_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT9_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT9. + */ +struct ALT_USB_DEV_DIEPINT9_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT9. */ +typedef volatile struct ALT_USB_DEV_DIEPINT9_s ALT_USB_DEV_DIEPINT9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT9 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT9_OFST 0x228 +/* The address of the ALT_USB_DEV_DIEPINT9 register. */ +#define ALT_USB_DEV_DIEPINT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT9_OFST)) + +/* + * Register : Device IN Endpoint 9 Transfer Size Register - dieptsiz9 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ9_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ9_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ9_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ9_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ9. + */ +struct ALT_USB_DEV_DIEPTSIZ9_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ9. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ9_s ALT_USB_DEV_DIEPTSIZ9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ9 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ9_OFST 0x230 +/* The address of the ALT_USB_DEV_DIEPTSIZ9 register. */ +#define ALT_USB_DEV_DIEPTSIZ9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ9_OFST)) + +/* + * Register : Device IN Endpoint 9 DMA Address Register - diepdma9 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma9 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */ +#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */ +#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */ +#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value. */ +#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value. */ +#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA9. + */ +struct ALT_USB_DEV_DIEPDMA9_s +{ + uint32_t diepdma9 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA9. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA9_s ALT_USB_DEV_DIEPDMA9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA9 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA9_OFST 0x234 +/* The address of the ALT_USB_DEV_DIEPDMA9 register. */ +#define ALT_USB_DEV_DIEPDMA9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA9_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 9 - dtxfsts9 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS9. + */ +struct ALT_USB_DEV_DTXFSTS9_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS9. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS9_s ALT_USB_DEV_DTXFSTS9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS9 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS9_OFST 0x238 +/* The address of the ALT_USB_DEV_DTXFSTS9 register. */ +#define ALT_USB_DEV_DTXFSTS9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS9_OFST)) + +/* + * Register : Device IN Endpoint 9 DMA Buffer Address Register - diepdmab9 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab9 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */ +#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */ +#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */ +#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value. */ +#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value. */ +#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB9. + */ +struct ALT_USB_DEV_DIEPDMAB9_s +{ + const uint32_t diepdmab9 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB9. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB9_s ALT_USB_DEV_DIEPDMAB9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB9 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB9_OFST 0x23c +/* The address of the ALT_USB_DEV_DIEPDMAB9 register. */ +#define ALT_USB_DEV_DIEPDMAB9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB9_OFST)) + +/* + * Register : Device Control IN Endpoint 10 Control Register - diepctl10 + * + * Endpoint_number: 10 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL10_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL10_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL10_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL10_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL10_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL10_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL10_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL10_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL10_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL10_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL10_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL10_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL10_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL10_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL10_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL10_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL10_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL10_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL10_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL10_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL10_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL10_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL10_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL10_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL10_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL10_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL10_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL10_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL10_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL10_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL10_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL10_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL10_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL10_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL10_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL10_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL10_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL10_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL10_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL10_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL10_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL10_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL10_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL10_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL10_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL10_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL10_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL10_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL10_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL10_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL10_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL10_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL10_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL10_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL10_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL10_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL10_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL10_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL10_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL10_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL10_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL10_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL10_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL10_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL10_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL10_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL10_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL10_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL10_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL10_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL10_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL10_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL10_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL10_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL10_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL10_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL10_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL10_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL10_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL10_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL10_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL10_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL10_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL10_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL10_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL10_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL10_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL10_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL10_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL10_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL10_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL10_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL10_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL10_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL10_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL10_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL10_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL10_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL10_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL10_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL10_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL10_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL10_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL10_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL10_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL10_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL10_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL10_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL10_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL10_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL10_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL10_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL10_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL10_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL10_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL10_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL10_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL10_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL10_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL10_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL10_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL10_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL10. + */ +struct ALT_USB_DEV_DIEPCTL10_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL10. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL10_s ALT_USB_DEV_DIEPCTL10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL10 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL10_OFST 0x240 +/* The address of the ALT_USB_DEV_DIEPCTL10 register. */ +#define ALT_USB_DEV_DIEPCTL10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL10_OFST)) + +/* + * Register : Device IN Endpoint 10 Interrupt Register - diepint10 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT10_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT10_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT10_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT10_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT10_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT10_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT10_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT10_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT10_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT10_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT10_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT10_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT10_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT10_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT10_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT10_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT10_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT10_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT10_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT10_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT10_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT10_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT10_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT10_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TMO register field. */ +#define ALT_USB_DEV_DIEPINT10_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TMO register field. */ +#define ALT_USB_DEV_DIEPINT10_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_TMO register field. */ +#define ALT_USB_DEV_DIEPINT10_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT10_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT10_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT10_TMO register field. */ +#define ALT_USB_DEV_DIEPINT10_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT10_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT10_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT10_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT10_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT10_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT10_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT10_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT10_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT10_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT10_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT10_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT10_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT10_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT10_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT10_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT10_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT10_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT10_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT10_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT10_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT10_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT10_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT10_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT10_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT10_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT10_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT10_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT10_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT10_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT10_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT10. + */ +struct ALT_USB_DEV_DIEPINT10_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT10. */ +typedef volatile struct ALT_USB_DEV_DIEPINT10_s ALT_USB_DEV_DIEPINT10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT10 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT10_OFST 0x248 +/* The address of the ALT_USB_DEV_DIEPINT10 register. */ +#define ALT_USB_DEV_DIEPINT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT10_OFST)) + +/* + * Register : Device IN Endpoint 10 Transfer Size Register - dieptsiz10 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ10_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ10_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ10_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ10_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ10. + */ +struct ALT_USB_DEV_DIEPTSIZ10_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ10. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ10_s ALT_USB_DEV_DIEPTSIZ10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ10 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ10_OFST 0x250 +/* The address of the ALT_USB_DEV_DIEPTSIZ10 register. */ +#define ALT_USB_DEV_DIEPTSIZ10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ10_OFST)) + +/* + * Register : Device IN Endpoint 10 DMA Address Register - diepdma10 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma10 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */ +#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */ +#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */ +#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value. */ +#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value. */ +#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA10. + */ +struct ALT_USB_DEV_DIEPDMA10_s +{ + uint32_t diepdma10 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA10. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA10_s ALT_USB_DEV_DIEPDMA10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA10 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA10_OFST 0x254 +/* The address of the ALT_USB_DEV_DIEPDMA10 register. */ +#define ALT_USB_DEV_DIEPDMA10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA10_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 10 - dtxfsts10 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS10. + */ +struct ALT_USB_DEV_DTXFSTS10_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS10. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS10_s ALT_USB_DEV_DTXFSTS10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS10 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS10_OFST 0x258 +/* The address of the ALT_USB_DEV_DTXFSTS10 register. */ +#define ALT_USB_DEV_DTXFSTS10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS10_OFST)) + +/* + * Register : Device IN Endpoint 10 DMA Buffer Address Register - diepdmab10 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab10 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */ +#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */ +#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */ +#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value. */ +#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value. */ +#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB10. + */ +struct ALT_USB_DEV_DIEPDMAB10_s +{ + const uint32_t diepdmab10 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB10. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB10_s ALT_USB_DEV_DIEPDMAB10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB10 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB10_OFST 0x25c +/* The address of the ALT_USB_DEV_DIEPDMAB10 register. */ +#define ALT_USB_DEV_DIEPDMAB10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB10_OFST)) + +/* + * Register : Device Control IN Endpoint 11 Control Register - diepctl11 + * + * Endpoint_number: 11 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL11_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL11_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL11_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL11_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL11_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL11_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL11_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL11_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL11_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL11_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL11_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL11_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL11_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL11_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL11_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL11_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL11_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL11_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL11_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL11_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL11_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL11_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL11_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL11_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL11_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL11_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL11_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL11_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL11_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL11_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL11_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL11_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL11_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL11_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL11_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL11_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL11_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL11_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL11_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL11_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL11_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL11_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL11_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL11_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL11_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL11_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL11_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL11_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL11_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL11_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL11_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL11_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL11_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL11_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL11_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL11_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL11_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL11_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL11_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL11_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL11_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL11_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL11_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL11_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL11_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL11_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL11_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL11_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL11_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL11_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL11_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL11_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL11_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL11_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL11_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL11_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL11_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL11_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL11_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL11_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL11_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL11_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL11_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL11_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL11_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL11_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL11_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL11_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL11_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL11_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL11_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL11_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL11_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL11_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL11_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL11_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL11_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL11_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL11_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL11_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL11_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL11_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL11_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL11_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL11_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL11_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL11_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL11_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL11_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL11_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL11_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL11_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL11_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL11_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL11_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL11_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL11_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL11_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL11_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL11_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL11_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL11_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL11. + */ +struct ALT_USB_DEV_DIEPCTL11_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL11. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL11_s ALT_USB_DEV_DIEPCTL11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL11 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL11_OFST 0x260 +/* The address of the ALT_USB_DEV_DIEPCTL11 register. */ +#define ALT_USB_DEV_DIEPCTL11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL11_OFST)) + +/* + * Register : Device IN Endpoint 11 Interrupt Register - diepint11 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT11_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT11_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT11_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT11_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT11_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT11_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT11_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT11_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT11_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT11_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT11_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT11_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT11_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT11_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT11_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT11_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT11_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT11_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT11_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT11_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT11_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT11_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT11_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT11_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TMO register field. */ +#define ALT_USB_DEV_DIEPINT11_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TMO register field. */ +#define ALT_USB_DEV_DIEPINT11_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_TMO register field. */ +#define ALT_USB_DEV_DIEPINT11_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT11_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT11_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT11_TMO register field. */ +#define ALT_USB_DEV_DIEPINT11_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT11_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT11_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT11_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT11_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT11_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT11_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT11_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT11_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT11_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT11_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT11_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT11_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT11_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT11_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT11_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT11_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT11_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT11_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT11_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT11_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT11_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT11_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT11_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT11_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT11_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT11_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT11_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT11_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT11_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT11_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT11. + */ +struct ALT_USB_DEV_DIEPINT11_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT11. */ +typedef volatile struct ALT_USB_DEV_DIEPINT11_s ALT_USB_DEV_DIEPINT11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT11 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT11_OFST 0x268 +/* The address of the ALT_USB_DEV_DIEPINT11 register. */ +#define ALT_USB_DEV_DIEPINT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT11_OFST)) + +/* + * Register : Device IN Endpoint 11 Transfer Size Register - dieptsiz11 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ11_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ11_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ11_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ11_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ11. + */ +struct ALT_USB_DEV_DIEPTSIZ11_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ11. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ11_s ALT_USB_DEV_DIEPTSIZ11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ11 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ11_OFST 0x270 +/* The address of the ALT_USB_DEV_DIEPTSIZ11 register. */ +#define ALT_USB_DEV_DIEPTSIZ11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ11_OFST)) + +/* + * Register : Device IN Endpoint 11 DMA Address Register - diepdma11 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma11 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */ +#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */ +#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */ +#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value. */ +#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value. */ +#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA11. + */ +struct ALT_USB_DEV_DIEPDMA11_s +{ + uint32_t diepdma11 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA11. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA11_s ALT_USB_DEV_DIEPDMA11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA11 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA11_OFST 0x274 +/* The address of the ALT_USB_DEV_DIEPDMA11 register. */ +#define ALT_USB_DEV_DIEPDMA11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA11_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 11 - dtxfsts11 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS11. + */ +struct ALT_USB_DEV_DTXFSTS11_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS11. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS11_s ALT_USB_DEV_DTXFSTS11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS11 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS11_OFST 0x278 +/* The address of the ALT_USB_DEV_DTXFSTS11 register. */ +#define ALT_USB_DEV_DTXFSTS11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS11_OFST)) + +/* + * Register : Device IN Endpoint 11 DMA Buffer Address Register - diepdmab11 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab11 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */ +#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */ +#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */ +#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value. */ +#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value. */ +#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB11. + */ +struct ALT_USB_DEV_DIEPDMAB11_s +{ + const uint32_t diepdmab11 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB11. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB11_s ALT_USB_DEV_DIEPDMAB11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB11 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB11_OFST 0x27c +/* The address of the ALT_USB_DEV_DIEPDMAB11 register. */ +#define ALT_USB_DEV_DIEPDMAB11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB11_OFST)) + +/* + * Register : Device Control IN Endpoint 12 Control Register - diepctl12 + * + * Endpoint_number: 12 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL12_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL12_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL12_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL12_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL12_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL12_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL12_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL12_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL12_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL12_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL12_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL12_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL12_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL12_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL12_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL12_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL12_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL12_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL12_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL12_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL12_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL12_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL12_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL12_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL12_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL12_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL12_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL12_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL12_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL12_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL12_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL12_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL12_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL12_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL12_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL12_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL12_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL12_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL12_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL12_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL12_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL12_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL12_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL12_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL12_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL12_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL12_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL12_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL12_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL12_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL12_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL12_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL12_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL12_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL12_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL12_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL12_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL12_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL12_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL12_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL12_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL12_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL12_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL12_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL12_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL12_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL12_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL12_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL12_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL12_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL12_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL12_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL12_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL12_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL12_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL12_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL12_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL12_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL12_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL12_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL12_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL12_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL12_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL12_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL12_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL12_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL12_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL12_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL12_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL12_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL12_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL12_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL12_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL12_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL12_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL12_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL12_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL12_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL12_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL12_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL12_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL12_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL12_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL12_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL12_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL12_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL12_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL12_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL12_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL12_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL12_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL12_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL12_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL12_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL12_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL12_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL12_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL12_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL12_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL12_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL12_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL12_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL12. + */ +struct ALT_USB_DEV_DIEPCTL12_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL12. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL12_s ALT_USB_DEV_DIEPCTL12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL12 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL12_OFST 0x280 +/* The address of the ALT_USB_DEV_DIEPCTL12 register. */ +#define ALT_USB_DEV_DIEPCTL12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL12_OFST)) + +/* + * Register : Device IN Endpoint 12 Interrupt Register - diepint12 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt ( + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT12_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT12_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT12_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT12_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT12_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT12_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT12_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT12_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT12_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT12_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT12_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT12_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT12_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT12_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT12_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT12_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT12_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT12_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT12_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT12_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT12_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT12_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT12_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT12_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TMO register field. */ +#define ALT_USB_DEV_DIEPINT12_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TMO register field. */ +#define ALT_USB_DEV_DIEPINT12_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_TMO register field. */ +#define ALT_USB_DEV_DIEPINT12_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT12_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT12_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT12_TMO register field. */ +#define ALT_USB_DEV_DIEPINT12_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT12_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT12_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT12_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT12_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT12_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT12_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT12_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT12_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT12_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT12_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT12_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT12_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT12_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT12_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT12_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT12_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT12_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT12_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT12_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT12_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt ( - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT12_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT12_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT12_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT12_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT12_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT12_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT12_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT12_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT12_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT12_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT12. + */ +struct ALT_USB_DEV_DIEPINT12_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt ( */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT12. */ +typedef volatile struct ALT_USB_DEV_DIEPINT12_s ALT_USB_DEV_DIEPINT12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT12 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT12_OFST 0x288 +/* The address of the ALT_USB_DEV_DIEPINT12 register. */ +#define ALT_USB_DEV_DIEPINT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT12_OFST)) + +/* + * Register : Device IN Endpoint 12 Transfer Size Register - dieptsiz12 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ12_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ12_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ12_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ12_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ12. + */ +struct ALT_USB_DEV_DIEPTSIZ12_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ12. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ12_s ALT_USB_DEV_DIEPTSIZ12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ12 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ12_OFST 0x290 +/* The address of the ALT_USB_DEV_DIEPTSIZ12 register. */ +#define ALT_USB_DEV_DIEPTSIZ12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ12_OFST)) + +/* + * Register : Device IN Endpoint 12 DMA Address Register - diepdma12 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma12 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */ +#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */ +#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */ +#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value. */ +#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value. */ +#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA12. + */ +struct ALT_USB_DEV_DIEPDMA12_s +{ + uint32_t diepdma12 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA12. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA12_s ALT_USB_DEV_DIEPDMA12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA12 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA12_OFST 0x294 +/* The address of the ALT_USB_DEV_DIEPDMA12 register. */ +#define ALT_USB_DEV_DIEPDMA12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA12_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 12 - dtxfsts12 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS12. + */ +struct ALT_USB_DEV_DTXFSTS12_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS12. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS12_s ALT_USB_DEV_DTXFSTS12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS12 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS12_OFST 0x298 +/* The address of the ALT_USB_DEV_DTXFSTS12 register. */ +#define ALT_USB_DEV_DTXFSTS12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS12_OFST)) + +/* + * Register : Device IN Endpoint 12 DMA Buffer Address Register - diepdmab12 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab12 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */ +#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */ +#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */ +#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value. */ +#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value. */ +#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB12. + */ +struct ALT_USB_DEV_DIEPDMAB12_s +{ + const uint32_t diepdmab12 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB12. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB12_s ALT_USB_DEV_DIEPDMAB12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB12 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB12_OFST 0x29c +/* The address of the ALT_USB_DEV_DIEPDMAB12 register. */ +#define ALT_USB_DEV_DIEPDMAB12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB12_OFST)) + +/* + * Register : Device Control IN Endpoint 13 Control Register - diepctl13 + * + * Endpoint_number: 13 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL13_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL13_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL13_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL13_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL13_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL13_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL13_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL13_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL13_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL13_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL13_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL13_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL13_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL13_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL13_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL13_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL13_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL13_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL13_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL13_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL13_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL13_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL13_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL13_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL13_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL13_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL13_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL13_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL13_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL13_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL13_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL13_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL13_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL13_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL13_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL13_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL13_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL13_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL13_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL13_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL13_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL13_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL13_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL13_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL13_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL13_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL13_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL13_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL13_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL13_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL13_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL13_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL13_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL13_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL13_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL13_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL13_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL13_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL13_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL13_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL13_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL13_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL13_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL13_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL13_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL13_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL13_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL13_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL13_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL13_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL13_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL13_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL13_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL13_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL13_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL13_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL13_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL13_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL13_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL13_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL13_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL13_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL13_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL13_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL13_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL13_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL13_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL13_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL13_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL13_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL13_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL13_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL13_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL13_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL13_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL13_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL13_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL13_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL13_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL13_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL13_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL13_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL13_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL13_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL13_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL13_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL13_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL13_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL13_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL13_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL13_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL13_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL13_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL13_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL13_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL13_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL13_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL13_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL13_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL13_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL13_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL13_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL13. + */ +struct ALT_USB_DEV_DIEPCTL13_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL13. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL13_s ALT_USB_DEV_DIEPCTL13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL13 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL13_OFST 0x2a0 +/* The address of the ALT_USB_DEV_DIEPCTL13 register. */ +#define ALT_USB_DEV_DIEPCTL13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL13_OFST)) + +/* + * Register : Device IN Endpoint 13 Interrupt Register - diepint13 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT13_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT13_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT13_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT13_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT13_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT13_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT13_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT13_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT13_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT13_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT13_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT13_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT13_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT13_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT13_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT13_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT13_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT13_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT13_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT13_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT13_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT13_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT13_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT13_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TMO register field. */ +#define ALT_USB_DEV_DIEPINT13_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TMO register field. */ +#define ALT_USB_DEV_DIEPINT13_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_TMO register field. */ +#define ALT_USB_DEV_DIEPINT13_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT13_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT13_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT13_TMO register field. */ +#define ALT_USB_DEV_DIEPINT13_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT13_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT13_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT13_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT13_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT13_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT13_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT13_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT13_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT13_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT13_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT13_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT13_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT13_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT13_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT13_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT13_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT13_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT13_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT13_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT13_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT13_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT13_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT13_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT13_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT13_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT13_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT13_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT13_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT13_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT13_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT13. + */ +struct ALT_USB_DEV_DIEPINT13_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT13. */ +typedef volatile struct ALT_USB_DEV_DIEPINT13_s ALT_USB_DEV_DIEPINT13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT13 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT13_OFST 0x2a8 +/* The address of the ALT_USB_DEV_DIEPINT13 register. */ +#define ALT_USB_DEV_DIEPINT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT13_OFST)) + +/* + * Register : Device IN Endpoint 13 Transfer Size Register - dieptsiz13 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ13_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ13_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ13_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ13_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ13. + */ +struct ALT_USB_DEV_DIEPTSIZ13_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ13. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ13_s ALT_USB_DEV_DIEPTSIZ13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ13 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ13_OFST 0x2b0 +/* The address of the ALT_USB_DEV_DIEPTSIZ13 register. */ +#define ALT_USB_DEV_DIEPTSIZ13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ13_OFST)) + +/* + * Register : Device IN Endpoint 13 DMA Address Register - diepdma13 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma13 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */ +#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */ +#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */ +#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value. */ +#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value. */ +#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA13. + */ +struct ALT_USB_DEV_DIEPDMA13_s +{ + uint32_t diepdma13 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA13. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA13_s ALT_USB_DEV_DIEPDMA13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA13 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA13_OFST 0x2b4 +/* The address of the ALT_USB_DEV_DIEPDMA13 register. */ +#define ALT_USB_DEV_DIEPDMA13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA13_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 13 - dtxfsts13 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS13. + */ +struct ALT_USB_DEV_DTXFSTS13_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS13. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS13_s ALT_USB_DEV_DTXFSTS13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS13 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS13_OFST 0x2b8 +/* The address of the ALT_USB_DEV_DTXFSTS13 register. */ +#define ALT_USB_DEV_DTXFSTS13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS13_OFST)) + +/* + * Register : Device IN Endpoint 13 DMA Buffer Address Register - diepdmab13 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab13 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */ +#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */ +#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */ +#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value. */ +#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value. */ +#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB13. + */ +struct ALT_USB_DEV_DIEPDMAB13_s +{ + const uint32_t diepdmab13 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB13. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB13_s ALT_USB_DEV_DIEPDMAB13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB13 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB13_OFST 0x2bc +/* The address of the ALT_USB_DEV_DIEPDMAB13 register. */ +#define ALT_USB_DEV_DIEPDMAB13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB13_OFST)) + +/* + * Register : Device Control IN Endpoint 14 Control Register - diepctl14 + * + * Endpoint_number: 14 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL14_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL14_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL14_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL14_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL14_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL14_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL14_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL14_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL14_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL14_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL14_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL14_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL14_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL14_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL14_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL14_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL14_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL14_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL14_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL14_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL14_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL14_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL14_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL14_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL14_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL14_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL14_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL14_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL14_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL14_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL14_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL14_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL14_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL14_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL14_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL14_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL14_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL14_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL14_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL14_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL14_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL14_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL14_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL14_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL14_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL14_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL14_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL14_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL14_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL14_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL14_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL14_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL14_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL14_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL14_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL14_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL14_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL14_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL14_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL14_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL14_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL14_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL14_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL14_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL14_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL14_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL14_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL14_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL14_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL14_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL14_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL14_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL14_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL14_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL14_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL14_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL14_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL14_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL14_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL14_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL14_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL14_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL14_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL14_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL14_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL14_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL14_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL14_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL14_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL14_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL14_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL14_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL14_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL14_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL14_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL14_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL14_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL14_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL14_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL14_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL14_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL14_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL14_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL14_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL14_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL14_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL14_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL14_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL14_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL14_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL14_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL14_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL14_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL14_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL14_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL14_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL14_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL14_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL14_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL14_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL14_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL14_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL14. + */ +struct ALT_USB_DEV_DIEPCTL14_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL14. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL14_s ALT_USB_DEV_DIEPCTL14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL14 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL14_OFST 0x2c0 +/* The address of the ALT_USB_DEV_DIEPCTL14 register. */ +#define ALT_USB_DEV_DIEPCTL14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL14_OFST)) + +/* + * Register : Device IN Endpoint 14 Interrupt Register - diepint14 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt ( + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT14_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT14_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT14_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT14_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT14_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT14_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT14_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT14_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT14_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT14_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT14_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT14_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT14_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT14_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT14_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT14_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT14_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT14_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT14_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT14_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT14_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT14_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT14_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT14_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TMO register field. */ +#define ALT_USB_DEV_DIEPINT14_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TMO register field. */ +#define ALT_USB_DEV_DIEPINT14_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_TMO register field. */ +#define ALT_USB_DEV_DIEPINT14_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT14_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT14_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT14_TMO register field. */ +#define ALT_USB_DEV_DIEPINT14_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT14_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT14_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT14_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT14_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT14_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT14_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT14_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT14_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT14_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT14_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT14_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT14_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT14_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT14_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT14_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT14_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT14_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT14_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT14_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT14_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt ( - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT14_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT14_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT14_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT14_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT14_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT14_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT14_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT14_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT14_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT14_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT14. + */ +struct ALT_USB_DEV_DIEPINT14_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt ( */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT14. */ +typedef volatile struct ALT_USB_DEV_DIEPINT14_s ALT_USB_DEV_DIEPINT14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT14 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT14_OFST 0x2c8 +/* The address of the ALT_USB_DEV_DIEPINT14 register. */ +#define ALT_USB_DEV_DIEPINT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT14_OFST)) + +/* + * Register : Device IN Endpoint 14 Transfer Size Register - dieptsiz14 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints only + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ14_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints only - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ14_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ14_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ14_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ14. + */ +struct ALT_USB_DEV_DIEPTSIZ14_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints only */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ14. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ14_s ALT_USB_DEV_DIEPTSIZ14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ14 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ14_OFST 0x2d0 +/* The address of the ALT_USB_DEV_DIEPTSIZ14 register. */ +#define ALT_USB_DEV_DIEPTSIZ14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ14_OFST)) + +/* + * Register : Device IN Endpoint 14 DMA Address Register - diepdma14 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma14 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */ +#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */ +#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */ +#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value. */ +#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value. */ +#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA14. + */ +struct ALT_USB_DEV_DIEPDMA14_s +{ + uint32_t diepdma14 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA14. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA14_s ALT_USB_DEV_DIEPDMA14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA14 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA14_OFST 0x2d4 +/* The address of the ALT_USB_DEV_DIEPDMA14 register. */ +#define ALT_USB_DEV_DIEPDMA14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA14_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 14 - dtxfsts14 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS14. + */ +struct ALT_USB_DEV_DTXFSTS14_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS14. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS14_s ALT_USB_DEV_DTXFSTS14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS14 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS14_OFST 0x2d8 +/* The address of the ALT_USB_DEV_DTXFSTS14 register. */ +#define ALT_USB_DEV_DTXFSTS14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS14_OFST)) + +/* + * Register : Device IN Endpoint 14 DMA Buffer Address Register - diepdmab14 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab14 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */ +#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */ +#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */ +#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value. */ +#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value. */ +#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB14. + */ +struct ALT_USB_DEV_DIEPDMAB14_s +{ + const uint32_t diepdmab14 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB14. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB14_s ALT_USB_DEV_DIEPDMAB14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB14 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB14_OFST 0x2dc +/* The address of the ALT_USB_DEV_DIEPDMAB14 register. */ +#define ALT_USB_DEV_DIEPDMAB14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB14_OFST)) + +/* + * Register : Device Control IN Endpoint 15 Control Registe - diepctl15 + * + * Endpoint_number: 15 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL15_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL15_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL15_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL15_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_MPS register field value. */ +#define ALT_USB_DEV_DIEPCTL15_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DIEPCTL15_MPS register field. */ +#define ALT_USB_DEV_DIEPCTL15_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_MPS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DIEPCTL15_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL15_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DIEPCTL15_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DIEPCTL15_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DIEPCTL15_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL15_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL15_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL15_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL15_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_USBACTEP register field value. */ +#define ALT_USB_DEV_DIEPCTL15_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */ +#define ALT_USB_DEV_DIEPCTL15_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DIEPCTL15_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPCTL15_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DIEPCTL15_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DIEPCTL15_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DIEPCTL15_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL15_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL15_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL15_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL15_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_DPID register field value. */ +#define ALT_USB_DEV_DIEPCTL15_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_DPID register field. */ +#define ALT_USB_DEV_DIEPCTL15_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_DPID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DIEPCTL15_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL15_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL15_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL15_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL15_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_NAKSTS register field value. */ +#define ALT_USB_DEV_DIEPCTL15_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */ +#define ALT_USB_DEV_DIEPCTL15_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DIEPCTL15_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL15_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DIEPCTL15_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DIEPCTL15_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DIEPCTL15_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPTYPE register field value. */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DIEPCTL15_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL15_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DIEPCTL15_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DIEPCTL15_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DIEPCTL15_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL15_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL15_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL15_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL15_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_STALL register field value. */ +#define ALT_USB_DEV_DIEPCTL15_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_STALL register field. */ +#define ALT_USB_DEV_DIEPCTL15_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_STALL field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DIEPCTL15_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL15_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL15_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL15_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL15_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_TXFNUM register field value. */ +#define ALT_USB_DEV_DIEPCTL15_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */ +#define ALT_USB_DEV_DIEPCTL15_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DIEPCTL15_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DIEPCTL15_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DIEPCTL15_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL15_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DIEPCTL15_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL15_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL15_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL15_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL15_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_CNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL15_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */ +#define ALT_USB_DEV_DIEPCTL15_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_CNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DIEPCTL15_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPCTL15_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DIEPCTL15_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DIEPCTL15_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DIEPCTL15_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL15_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL15_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL15_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL15_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SNAK register field value. */ +#define ALT_USB_DEV_DIEPCTL15_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */ +#define ALT_USB_DEV_DIEPCTL15_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_SNAK field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DIEPCTL15_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPCTL15_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DIEPCTL15_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DIEPCTL15_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DIEPCTL15_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL15_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL15_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL15_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL15_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SETD0PID register field value. */ +#define ALT_USB_DEV_DIEPCTL15_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */ +#define ALT_USB_DEV_DIEPCTL15_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DIEPCTL15_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DIEPCTL15_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DIEPCTL15_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL15_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DIEPCTL15_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL15_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL15_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL15_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL15_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SETD1PID register field value. */ +#define ALT_USB_DEV_DIEPCTL15_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */ +#define ALT_USB_DEV_DIEPCTL15_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPCTL15_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPCTL15_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DIEPCTL15_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL15_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DIEPCTL15_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL15_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPDIS register field value. */ +#define ALT_USB_DEV_DIEPCTL15_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_EPDIS field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DIEPCTL15_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DIEPCTL15_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DIEPCTL15_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DIEPCTL15_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DIEPCTL15_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL15_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPENA register field value. */ +#define ALT_USB_DEV_DIEPCTL15_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */ +#define ALT_USB_DEV_DIEPCTL15_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPCTL15_EPENA field value from a register. */ +#define ALT_USB_DEV_DIEPCTL15_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DIEPCTL15_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPCTL15_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPCTL15. + */ +struct ALT_USB_DEV_DIEPCTL15_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPCTL15. */ +typedef volatile struct ALT_USB_DEV_DIEPCTL15_s ALT_USB_DEV_DIEPCTL15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPCTL15 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPCTL15_OFST 0x2e0 +/* The address of the ALT_USB_DEV_DIEPCTL15 register. */ +#define ALT_USB_DEV_DIEPCTL15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL15_OFST)) + +/* + * Register : Device IN Endpoint 15 Interrupt Register - diepint15 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:--------------------------------------- + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | AHB Error + * [3] | R | 0x0 | Timeout Condition + * [4] | R | 0x0 | IN Token Received When TxFIFO is Empty + * [5] | R | 0x0 | IN Token Received with EP Mismatch + * [6] | R | 0x0 | IN Endpoint NAK Effective + * [7] | R | 0x1 | Transmit FIFO Empty + * [8] | R | 0x0 | Fifo Underrun + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled + * + * * for IN endpoint this field indicates that the requested data from the + * descriptor is moved from external system memory to internal FIFO. + * + * * for OUT endpoint this field indicates that the requested data from the + * internal FIFO is moved to external system memory. This interrupt is generated + * only when the corresponding endpoint descriptor is closed, and the IOC bit for + * the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, + * this field indicates that the programmed transfer is complete on the AHB as + * well as on the USB, for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */ +#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT15_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT15_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT15_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DIEPINT15_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT15_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT15_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT15_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT15_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_EPDISBLD register field value. */ +#define ALT_USB_DEV_DIEPINT15_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */ +#define ALT_USB_DEV_DIEPINT15_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DIEPINT15_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : AHB Error - ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DIEPINT15_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DIEPINT15_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DIEPINT15_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DIEPINT15_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT15_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT15_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT15_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT15_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_AHBERR register field value. */ +#define ALT_USB_DEV_DIEPINT15_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */ +#define ALT_USB_DEV_DIEPINT15_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_AHBERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DIEPINT15_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : Timeout Condition - timeout + * + * In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In + * dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather + * DMA mode, the TimeOUT interrupt is notasserted. Indicates that the core has + * detected a timeout condition on the USB for the last IN token on this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT15_TMO_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_TMO_E_ACT | 0x1 | Timeout interrupy + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TMO + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_TMO_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TMO + * + * Timeout interrupy + */ +#define ALT_USB_DEV_DIEPINT15_TMO_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TMO register field. */ +#define ALT_USB_DEV_DIEPINT15_TMO_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TMO register field. */ +#define ALT_USB_DEV_DIEPINT15_TMO_MSB 3 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_TMO register field. */ +#define ALT_USB_DEV_DIEPINT15_TMO_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT15_TMO_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_TMO register field value. */ +#define ALT_USB_DEV_DIEPINT15_TMO_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DIEPINT15_TMO register field. */ +#define ALT_USB_DEV_DIEPINT15_TMO_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_TMO field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_TMO_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DIEPINT15_TMO register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_TMO_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : IN Token Received When TxFIFO is Empty - intkntxfemp + * + * Applies to non-periodic IN endpoints only. Indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNTXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNTXFEMP + * + * IN Token Received Interrupt + */ +#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_MSB 4 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : IN Token Received with EP Mismatch - intknepmis + * + * Applies to non-periodic IN endpoints only. Indicates that the data in the top of + * the non-periodic TxFIFO belongs to an endpoint other than the one for which the + * IN token was received. This interrupt is asserted on the endpoint for which the + * IN token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNEPMIS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNEPMIS + * + * IN Token Received with EP Mismatch interrupt + */ +#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_MSB 5 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value. */ +#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */ +#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_INTKNEPMIS field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : IN Endpoint NAK Effective - inepnakeff + * + * Applies to periodic IN endpoints only. This bit can be cleared when the + * application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This + * interrupt indicates that the core has sampled the NAK bit Set (either by the + * application or by the core). The interrupt indicates that the IN endpoint NAK + * bit Set by the application has taken effect in the core.This interrupt does not + * guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority + * over a NAK bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INEPNAKEFF + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INEPNAKEFF + * + * IN Endpoint NAK Effective interrupt + */ +#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_MSB 6 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value. */ +#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */ +#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_INEPNAKEFF field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Transmit FIFO Empty - txfemp + * + * This bit is valid only for IN Endpoints This interrupt is asserted when the + * TxFIFO for this endpoint is either half or completely empty. The half or + * completely empty status is determined by the TxFIFO Empty Level bit in the Core + * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------ + * ALT_USB_DEV_DIEPINT15_TXFEMP_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFEMP + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_TXFEMP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFEMP + * + * Transmit FIFO Empty interrupt + */ +#define ALT_USB_DEV_DIEPINT15_TXFEMP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT15_TXFEMP_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT15_TXFEMP_MSB 7 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT15_TXFEMP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT15_TXFEMP_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_TXFEMP register field value. */ +#define ALT_USB_DEV_DIEPINT15_TXFEMP_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */ +#define ALT_USB_DEV_DIEPINT15_TXFEMP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DIEPINT15_TXFEMP field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_TXFEMP_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_DEV_DIEPINT15_TXFEMP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_TXFEMP_SET(value) (((value) << 7) & 0x00000080) + +/* + * Field : Fifo Underrun - txfifoundrn + * + * Applies to IN endpoints Only. The core generates this interrupt when it detects + * a transmit FIFO underrun condition for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------ + * ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN + * + * Fifo Underrun interrupt + */ +#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_MSB 8 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value. */ +#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */ +#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core + * generates this interrupt when the descriptor accessed is not ready for the Core + * to process, such as Host busy or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT15_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DIEPINT15_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT15_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT15_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT15_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT15_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_BNAINTR register field value. */ +#define ALT_USB_DEV_DIEPINT15_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */ +#define ALT_USB_DEV_DIEPINT15_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DIEPINT15_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DIEPINT15_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DIEPINT15_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT15_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT15_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT15_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT15_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_BBLEERR register field value. */ +#define ALT_USB_DEV_DIEPINT15_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */ +#define ALT_USB_DEV_DIEPINT15_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DIEPINT15_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */ +#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPINT15_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPINT15. + */ +struct ALT_USB_DEV_DIEPINT15_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* AHB Error */ + const uint32_t timeout : 1; /* Timeout Condition */ + const uint32_t intkntxfemp : 1; /* IN Token Received When TxFIFO is Empty */ + const uint32_t intknepmis : 1; /* IN Token Received with EP Mismatch */ + const uint32_t inepnakeff : 1; /* IN Endpoint NAK Effective */ + const uint32_t txfemp : 1; /* Transmit FIFO Empty */ + const uint32_t txfifoundrn : 1; /* Fifo Underrun */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPINT15. */ +typedef volatile struct ALT_USB_DEV_DIEPINT15_s ALT_USB_DEV_DIEPINT15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPINT15 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPINT15_OFST 0x2e8 +/* The address of the ALT_USB_DEV_DIEPINT15 register. */ +#define ALT_USB_DEV_DIEPINT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT15_OFST)) + +/* + * Register : Device IN Endpoint 15 Transfer Size Register - dieptsiz15 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:---------------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | RW | 0x0 | Applies to IN endpoints onl + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value. */ +#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - PktCnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the TxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value. */ +#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ15_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : Applies to IN endpoints onl - mc + * + * for periodic IN endpoints, this field indicates the number of packets that must + * be transmitted per microframe on the USB. The core uses this field to calculate + * the data PID for isochronous IN endpoints. for non-periodic IN endpoints, this + * field is valid only in Internal DMA mode. It specifies the number of packets the + * core must fetchfor an IN endpoint before it switches to the endpoint pointed to + * by the Next Endpoint field of the Device Endpoint-n Control register + * (DIEPCTLn.NextEp) + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------ + * ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTONE | 0x1 | 1 packet + * ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTWO | 0x2 | 2 packets + * ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTHREE | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC + * + * 1 packet + */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTONE 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC + * + * 2 packets + */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTWO 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC + * + * 3 packets + */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTHREE 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_MSB 30 +/* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_MC register field value. */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPTSIZ15_MC field value from a register. */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DIEPTSIZ15_MC register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPTSIZ15_MC_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPTSIZ15. + */ +struct ALT_USB_DEV_DIEPTSIZ15_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t PktCnt : 10; /* Packet Count */ + uint32_t mc : 2; /* Applies to IN endpoints onl */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ15. */ +typedef volatile struct ALT_USB_DEV_DIEPTSIZ15_s ALT_USB_DEV_DIEPTSIZ15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPTSIZ15 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPTSIZ15_OFST 0x2f0 +/* The address of the ALT_USB_DEV_DIEPTSIZ15 register. */ +#define ALT_USB_DEV_DIEPTSIZ15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ15_OFST)) + +/* + * Register : Device IN Endpoint 15 DMA Address Register - diepdma15 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - diepdma15 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */ +#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */ +#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */ +#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value. */ +#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value. */ +#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 field value from a register. */ +#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMA15. + */ +struct ALT_USB_DEV_DIEPDMA15_s +{ + uint32_t diepdma15 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMA15. */ +typedef volatile struct ALT_USB_DEV_DIEPDMA15_s ALT_USB_DEV_DIEPDMA15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMA15 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMA15_OFST 0x2f4 +/* The address of the ALT_USB_DEV_DIEPDMA15 register. */ +#define ALT_USB_DEV_DIEPDMA15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA15_OFST)) + +/* + * Register : Device IN Endpoint Transmit FIFO Status Register 15 - dtxfsts15 + * + * This register contains the free space information for the Device IN endpoint + * TxFIFO. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:-------|:------------------------------- + * [15:0] | R | 0x2000 | IN Endpoint TxFIFO Space Avail + * [31:16] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : IN Endpoint TxFIFO Space Avail - ineptxfspcavail + * + * Indicates the amount of free space available in the Endpoint TxFIFO. Values are + * in terms of 32-bit words. 16'h0: Endpoint TxFIFO is full 16'h1: 1 word available + * 16'h2: 2 words available 16'hn: n words available (where 0 n 32,768) 16'h8000: + * 32,768 words available Others: Reserved + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_MSB 15 +/* The width in bits of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_WIDTH 16 +/* The mask used to set the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff +/* The mask used to clear the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value. */ +#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000 +/* The reset value of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */ +#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_RESET 0x2000 +/* Extracts the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL field value from a register. */ +#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0) +/* Produces a ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DTXFSTS15. + */ +struct ALT_USB_DEV_DTXFSTS15_s +{ + const uint32_t ineptxfspcavail : 16; /* IN Endpoint TxFIFO Space Avail */ + uint32_t : 16; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DTXFSTS15. */ +typedef volatile struct ALT_USB_DEV_DTXFSTS15_s ALT_USB_DEV_DTXFSTS15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DTXFSTS15 register from the beginning of the component. */ +#define ALT_USB_DEV_DTXFSTS15_OFST 0x2f8 +/* The address of the ALT_USB_DEV_DTXFSTS15 register. */ +#define ALT_USB_DEV_DTXFSTS15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS15_OFST)) + +/* + * Register : Device IN Endpoint 15 DMA Buffer Address Register - diepdmab15 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - diepdmab15 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */ +#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */ +#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_MSB 31 +/* The width in bits of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */ +#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value. */ +#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value. */ +#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field is UNKNOWN. */ +#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_RESET 0x0 +/* Extracts the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 field value from a register. */ +#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DIEPDMAB15. + */ +struct ALT_USB_DEV_DIEPDMAB15_s +{ + const uint32_t diepdmab15 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB15. */ +typedef volatile struct ALT_USB_DEV_DIEPDMAB15_s ALT_USB_DEV_DIEPDMAB15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DIEPDMAB15 register from the beginning of the component. */ +#define ALT_USB_DEV_DIEPDMAB15_OFST 0x2fc +/* The address of the ALT_USB_DEV_DIEPDMAB15 register. */ +#define ALT_USB_DEV_DIEPDMAB15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB15_OFST)) + +/* + * Register : Device Control OUT Endpoint 0 Control Register - doepctl0 + * + * This is Control OUT Endpoint 0 Control register. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [1:0] | R | 0x0 | Maximum Packet Size + * [14:2] | ??? | 0x0 | *UNDEFINED* + * [15] | R | 0x1 | USB Active Endpoint + * [16] | ??? | 0x0 | *UNDEFINED* + * [17] | R | 0x0 | NAK Status + * [19:18] | R | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [29:28] | ??? | 0x0 | *UNDEFINED* + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * The maximum packet size for control OUT endpoint 0 is thesame as what is + * programmed in control IN Endpoint 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE64 | 0x0 | 64 bytes + * ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE32 | 0x1 | 32 bytes + * ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE16 | 0x2 | 16 bytes + * ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE8 | 0x3 | 8 bytes + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS + * + * 64 bytes + */ +#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE64 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS + * + * 32 bytes + */ +#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE32 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS + * + * 16 bytes + */ +#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE16 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS + * + * 8 bytes + */ +#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE8 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL0_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL0_MPS_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPCTL0_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL0_MPS_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL0_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL0_MPS_SET_MSK 0x00000003 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL0_MPS_CLR_MSK 0xfffffffc +/* The reset value of the ALT_USB_DEV_DOEPCTL0_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL0_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL0_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL0_MPS_GET(value) (((value) & 0x00000003) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL0_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL0_MPS_SET(value) (((value) << 0) & 0x00000003) + +/* + * Field : USB Active Endpoint - usbactep + * + * This bit is always Set to 1, indicating that a control endpoint 0 is always + * active in all configurations and interfaces. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------- + * ALT_USB_DEV_DOEPCTL0_USBACTEP_E_ACT | 0x1 | USB Active Endpoint 0 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_USBACTEP + * + * USB Active Endpoint 0 + */ +#define ALT_USB_DEV_DOEPCTL0_USBACTEP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL0_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL0_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL0_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL0_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL0_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL0_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL0_USBACTEP_RESET 0x1 +/* Extracts the ALT_USB_DEV_DOEPCTL0_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL0_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL0_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL0_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit, the core stops receiving + * data, even If there is space in the RxFIFO to accommodate the incoming packet. + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL0_NAKSTS_E_INACT | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL0_NAKSTS_E_ACT | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL0_NAKSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL0_NAKSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL0_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL0_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL0_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL0_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL0_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL0_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL0_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL0_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL0_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL0_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL0_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * Hardcoded to 0 for control. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL0_EPTYPE_E_ACT | 0x0 | Endpoint Control 0 + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPTYPE + * + * Endpoint Control 0 + */ +#define ALT_USB_DEV_DOEPCTL0_EPTYPE_E_ACT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL0_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL0_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL0_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL0_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not + * check the correctness of OUT packets before transferring them to application + * memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL0_SNP_E_DISD | 0x0 | Snoop Mode disabled + * ALT_USB_DEV_DOEPCTL0_SNP_E_END | 0x1 | Snoop Mode enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNP + * + * Snoop Mode disabled + */ +#define ALT_USB_DEV_DOEPCTL0_SNP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNP + * + * Snoop Mode enabled + */ +#define ALT_USB_DEV_DOEPCTL0_SNP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL0_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL0_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL0_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL0_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL0_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL0_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL0_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL0_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL0_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL0_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL0_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL0_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL0_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * The application can only Set this bit, and the core clears it, when a SETUP + * token is received for this endpoint. If a NAK bit or Global OUT NAK is Set along + * with this bit, the STALL bit takes priority. Irrespective of this bit's setting, + * the core always responds to SETUP data packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------- + * ALT_USB_DEV_DOEPCTL0_STALL_E_INACT | 0x0 | No Stall + * ALT_USB_DEV_DOEPCTL0_STALL_E_ACT | 0x1 | Stall Handshake + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_STALL + * + * No Stall + */ +#define ALT_USB_DEV_DOEPCTL0_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_STALL + * + * Stall Handshake + */ +#define ALT_USB_DEV_DOEPCTL0_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL0_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL0_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL0_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL0_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL0_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL0_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL0_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL0_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL0_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL0_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL0_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL0_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL0_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL0_CNAK_E_NOCLR | 0x0 | No action + * ALT_USB_DEV_DOEPCTL0_CNAK_E_CLR | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_CNAK + * + * No action + */ +#define ALT_USB_DEV_DOEPCTL0_CNAK_E_NOCLR 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL0_CNAK_E_CLR 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL0_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL0_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL0_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL0_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL0_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL0_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL0_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL0_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL0_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL0_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL0_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint.Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set bit on a Transfer Completed interrupt, or after a SETUP is + * received on the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL0_SNAK_E_NOSET | 0x0 | No action + * ALT_USB_DEV_DOEPCTL0_SNAK_E_SET | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNAK + * + * No action + */ +#define ALT_USB_DEV_DOEPCTL0_SNAK_E_NOSET 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL0_SNAK_E_SET 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL0_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL0_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL0_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL0_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL0_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL0_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL0_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL0_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL0_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL0_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL0_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Endpoint Disable - epdis + * + * The application cannot disable control OUT endpoint 0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL0_EPDIS_E_INACT | 0x0 | No Endpoint disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPDIS + * + * No Endpoint disable + */ +#define ALT_USB_DEV_DOEPCTL0_EPDIS_E_INACT 0x0 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL0_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL0_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL0_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL0_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL0_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL0_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * When Scatter/Gather DMA mode is enabled, for OUT endpoints this bit indicates + * that the descriptor structure and data buffer to receive data is setup. When + * Scatter/Gather DMA mode is disabled(such as for buffer-pointer based DMA + * mode)this bit indicates that the application has allocated the memory to start + * receiving data from the USB.The core clears this bit before setting any of the + * following interrupts on this endpoint: + * + * SETUP Phase Done + * + * Endpoint Disabled + * + * Transfer Completed + * + * In DMA mode, this bit must be Set for the core to transfer SETUP data packets + * into memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------- + * ALT_USB_DEV_DOEPCTL0_EPENA_E_INACT | 0x0 | No action + * ALT_USB_DEV_DOEPCTL0_EPENA_E_ACT | 0x1 | Endpoint Enabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPENA + * + * No action + */ +#define ALT_USB_DEV_DOEPCTL0_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPENA + * + * Endpoint Enabled + */ +#define ALT_USB_DEV_DOEPCTL0_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL0_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL0_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL0_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL0_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL0_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL0_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL0_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL0. + */ +struct ALT_USB_DEV_DOEPCTL0_s +{ + const uint32_t mps : 2; /* Maximum Packet Size */ + uint32_t : 13; /* *UNDEFINED* */ + const uint32_t usbactep : 1; /* USB Active Endpoint */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t naksts : 1; /* NAK Status */ + const uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL0. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL0_s ALT_USB_DEV_DOEPCTL0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL0 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL0_OFST 0x300 +/* The address of the ALT_USB_DEV_DOEPCTL0 register. */ +#define ALT_USB_DEV_DOEPCTL0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL0_OFST)) + +/* + * Register : Device OUT Endpoint 0 Interrupt Register - doepint0 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT0_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT0_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT0_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT0_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT0_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT0_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT0_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT0_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT0_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT0_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT0_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT0_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT0_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT0_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT0_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT0_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT0_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT0_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT0_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT0_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT0_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT0_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT0_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT0_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT0_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT0_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT0_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT0_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT0_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT0_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT0_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT0_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT0_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT0_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT0_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT0_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT0_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT0_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT0_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT0_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT0_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT0_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT0_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT0_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT0_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT0_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT0_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT0_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT0_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT0_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT0_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT0_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT0_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT0_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT0_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT0_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT0_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT0_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT0. + */ +struct ALT_USB_DEV_DOEPINT0_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT0_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT0. */ +typedef volatile struct ALT_USB_DEV_DOEPINT0_s ALT_USB_DEV_DOEPINT0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT0 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT0_OFST 0x308 +/* The address of the ALT_USB_DEV_DOEPINT0 register. */ +#define ALT_USB_DEV_DOEPINT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT0_OFST)) + +/* + * Register : Device OUT Endpoint 0 Transfer Size Register - doeptsiz0 + * + * The application must modify this register before enabling endpoint 0. Once + * endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 + * Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core modifies this + * register. The application can only read this register once the core has cleared + * the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 1 to + * 15. When Scatter/Gather DMA mode is enabled, this register must not be + * programmed by the application. If the application reads this register when + * Scatter/Gather DMA mode is enabled, the core returns all zeros. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:----------------------------- + * [6:0] | RW | 0x0 | Transfer Size + * [18:7] | ??? | 0x0 | *UNDEFINED* + * [19] | RW | 0x0 | Packet Count + * [28:20] | ??? | 0x0 | *UNDEFINED* + * [30:29] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ0_SUPCNT + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_WIDTH 7 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_SET_MSK 0x0000007f +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_CLR_MSK 0xffffff80 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_GET(value) (((value) & 0x0000007f) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0000007f) + +/* + * Field : Packet Count - pktcnt + * + * This field is decremented to zero after a packet is written into the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_SET_MSK 0x00080000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_CLR_MSK 0xfff7ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ0_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_GET(value) (((value) & 0x00080000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x00080000) + +/* + * Field : supcnt + * + * SETUP Packet Count (SUPCnt)This field specifies the number of back-to-back SETUP + * datapackets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_ONEPKT | 0x1 | 1 packet + * ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_TWOPKT | 0x2 | 2 packets + * ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_THREEPKT | 0x3 | 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT + * + * 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_ONEPKT 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT + * + * 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_TWOPKT 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT + * + * 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_THREEPKT 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ0_SUPCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ0. + */ +struct ALT_USB_DEV_DOEPTSIZ0_s +{ + uint32_t xfersize : 7; /* Transfer Size */ + uint32_t : 12; /* *UNDEFINED* */ + uint32_t pktcnt : 1; /* Packet Count */ + uint32_t : 9; /* *UNDEFINED* */ + uint32_t supcnt : 2; /* ALT_USB_DEV_DOEPTSIZ0_SUPCNT */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ0. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ0_s ALT_USB_DEV_DOEPTSIZ0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ0 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ0_OFST 0x310 +/* The address of the ALT_USB_DEV_DOEPTSIZ0 register. */ +#define ALT_USB_DEV_DOEPTSIZ0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ0_OFST)) + +/* + * Register : Device OUT Endpoint 0 DMA Address Register - doepdma0 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma0 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */ +#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */ +#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */ +#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value. */ +#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value. */ +#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA0. + */ +struct ALT_USB_DEV_DOEPDMA0_s +{ + uint32_t doepdma0 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA0. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA0_s ALT_USB_DEV_DOEPDMA0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA0 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA0_OFST 0x314 +/* The address of the ALT_USB_DEV_DOEPDMA0 register. */ +#define ALT_USB_DEV_DOEPDMA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA0_OFST)) + +/* + * Register : Device OUT Endpoint 16 DMA Buffer Address Register - doepdmab0 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab0 + * + * Used with Scatter/Gather DMA. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */ +#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */ +#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */ +#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value. */ +#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value. */ +#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB0. + */ +struct ALT_USB_DEV_DOEPDMAB0_s +{ + const uint32_t doepdmab0 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB0. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB0_s ALT_USB_DEV_DOEPDMAB0_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB0 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB0_OFST 0x31c +/* The address of the ALT_USB_DEV_DOEPDMAB0 register. */ +#define ALT_USB_DEV_DOEPDMAB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB0_OFST)) + +/* + * Register : Device Control OUT Endpoint 1 Control Register - doepctl1 + * + * Out Endpoint 1. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL1_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL1_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL1_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL1_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL1_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL1_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL1_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL1_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL1_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL1_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL1_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL1_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL1_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL1_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL1_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL1_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL1_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL1_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL1_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * h 1'b0'b0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL1_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL1_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL1_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL1_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL1_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL1_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL1_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL1_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL1_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL1_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL1_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL1_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL1_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL1_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL1_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL1_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL1_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL1_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL1_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL1_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL1_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL1_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL1_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL1_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL1_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL1_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL1_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL1_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL1_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL1_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL1_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL1_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL1_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL1_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL1_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL1_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL1_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL1_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL1_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL1_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL1_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL1_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL1_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL1_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL1_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL1_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL1_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL1_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL1_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL1_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL1_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL1_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL1_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL1_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL1_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL1_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL1_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL1_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL1_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL1_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL1_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL1_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL1_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL1_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL1_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL1_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL1_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL1_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL1_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL1_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL1_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL1_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL1_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL1_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL1_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL1_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL1_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL1_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL1_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL1_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL1_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL1_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL1_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL1_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL1_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL1_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL1_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL1_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL1_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL1_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL1_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL1_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL1_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL1_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL1_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL1_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL1_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL1_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL1_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL1_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL1_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL1_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL1_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL1_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL1_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL1_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL1_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL1. + */ +struct ALT_USB_DEV_DOEPCTL1_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL1. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL1_s ALT_USB_DEV_DOEPCTL1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL1 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL1_OFST 0x320 +/* The address of the ALT_USB_DEV_DOEPCTL1 register. */ +#define ALT_USB_DEV_DOEPCTL1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL1_OFST)) + +/* + * Register : Device OUT Endpoint 1 Interrupt Register - doepint1 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT1_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT1_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT1_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT1_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT1_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT1_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT1_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT1_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT1_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT1_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT1_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT1_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT1_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT1_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT1_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT1_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT1_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT1_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT1_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT1_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT1_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT1_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT1_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT1_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT1_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT1_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT1_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT1_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT1_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT1_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT1_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT1_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT1_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT1_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT1_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT1_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT1_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT1_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT1_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT1_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT1_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT1_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT1_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT1_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT1_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT1_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT1_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT1_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT1_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT1_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT1_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT1_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT1_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT1_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT1_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT1_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT1_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT1_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT1. + */ +struct ALT_USB_DEV_DOEPINT1_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT1_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT1. */ +typedef volatile struct ALT_USB_DEV_DOEPINT1_s ALT_USB_DEV_DOEPINT1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT1 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT1_OFST 0x328 +/* The address of the ALT_USB_DEV_DOEPINT1 register. */ +#define ALT_USB_DEV_DOEPINT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT1_OFST)) + +/* + * Register : Device OUT Endpoint 1 Transfer Size Register - doeptsiz1 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ1_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ1_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ1. + */ +struct ALT_USB_DEV_DOEPTSIZ1_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ1. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ1_s ALT_USB_DEV_DOEPTSIZ1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ1 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ1_OFST 0x330 +/* The address of the ALT_USB_DEV_DOEPTSIZ1 register. */ +#define ALT_USB_DEV_DOEPTSIZ1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ1_OFST)) + +/* + * Register : Device OUT Endpoint 1 DMA Address Register - doepdma1 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma1 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */ +#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */ +#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */ +#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value. */ +#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value. */ +#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA1. + */ +struct ALT_USB_DEV_DOEPDMA1_s +{ + uint32_t doepdma1 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA1. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA1_s ALT_USB_DEV_DOEPDMA1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA1 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA1_OFST 0x334 +/* The address of the ALT_USB_DEV_DOEPDMA1 register. */ +#define ALT_USB_DEV_DOEPDMA1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA1_OFST)) + +/* + * Register : Device OUT Endpoint 1 DMA Buffer Address Register - doepdmab1 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab1 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */ +#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */ +#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */ +#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value. */ +#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value. */ +#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB1. + */ +struct ALT_USB_DEV_DOEPDMAB1_s +{ + const uint32_t doepdmab1 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB1. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB1_s ALT_USB_DEV_DOEPDMAB1_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB1 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB1_OFST 0x33c +/* The address of the ALT_USB_DEV_DOEPDMAB1 register. */ +#define ALT_USB_DEV_DOEPDMAB1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB1_OFST)) + +/* + * Register : Device Control OUT Endpoint 2 Control Register - DOEPCTL2 + * + * Out Endpoint 2. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL2_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL2_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL2_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL2_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL2_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL2_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL2_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL2_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL2_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL2_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL2_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL2_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL2_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL2_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL2_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL2_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL2_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL2_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL2_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL2_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL2_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL2_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL2_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL2_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL2_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL2_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL2_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL2_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL2_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL2_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL2_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL2_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL2_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL2_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL2_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL2_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL2_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL2_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL2_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL2_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL2_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL2_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL2_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL2_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL2_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL2_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL2_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL2_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL2_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL2_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL2_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL2_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL2_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL2_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL2_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL2_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL2_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL2_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL2_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL2_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL2_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL2_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL2_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL2_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL2_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL2_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL2_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL2_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL2_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL2_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL2_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL2_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL2_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL2_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL2_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL2_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL2_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL2_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL2_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL2_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL2_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL2_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL2_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL2_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL2_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL2_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL2_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL2_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL2_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL2_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL2_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL2_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL2_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL2_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL2_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL2_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL2_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL2_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL2_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL2_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL2_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL2_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL2_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL2_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL2_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL2_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL2_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL2_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL2_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL2_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL2_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL2_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL2_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL2_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL2_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL2_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL2_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL2_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL2_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL2_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL2_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL2_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL2_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL2_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL2_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL2_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL2. + */ +struct ALT_USB_DEV_DOEPCTL2_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL2. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL2_s ALT_USB_DEV_DOEPCTL2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL2 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL2_OFST 0x340 +/* The address of the ALT_USB_DEV_DOEPCTL2 register. */ +#define ALT_USB_DEV_DOEPCTL2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL2_OFST)) + +/* + * Register : Device OUT Endpoint 2 Interrupt Register - doepint2 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT2_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT2_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT2_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT2_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT2_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT2_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT2_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT2_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT2_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT2_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT2_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT2_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT2_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT2_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT2_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT2_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT2_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT2_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT2_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT2_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT2_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT2_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT2_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT2_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT2_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT2_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT2_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT2_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT2_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT2_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT2_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT2_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT2_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT2_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT2_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT2_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT2_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT2_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT2_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT2_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT2_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT2_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT2_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT2_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT2_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT2_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT2_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT2_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT2_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT2_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT2_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT2_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT2_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT2_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT2_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT2_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT2_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT2_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT2. + */ +struct ALT_USB_DEV_DOEPINT2_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT2_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT2. */ +typedef volatile struct ALT_USB_DEV_DOEPINT2_s ALT_USB_DEV_DOEPINT2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT2 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT2_OFST 0x348 +/* The address of the ALT_USB_DEV_DOEPINT2 register. */ +#define ALT_USB_DEV_DOEPINT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT2_OFST)) + +/* + * Register : Device OUT Endpoint 2 Transfer Size Register - doeptsiz2 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ2_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ2_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ2. + */ +struct ALT_USB_DEV_DOEPTSIZ2_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ2. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ2_s ALT_USB_DEV_DOEPTSIZ2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ2 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ2_OFST 0x350 +/* The address of the ALT_USB_DEV_DOEPTSIZ2 register. */ +#define ALT_USB_DEV_DOEPTSIZ2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ2_OFST)) + +/* + * Register : Device OUT Endpoint 2 DMA Address Register - doepdma2 + * + * DMA Addressing. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma2 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */ +#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */ +#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */ +#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value. */ +#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value. */ +#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA2. + */ +struct ALT_USB_DEV_DOEPDMA2_s +{ + uint32_t doepdma2 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA2. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA2_s ALT_USB_DEV_DOEPDMA2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA2 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA2_OFST 0x354 +/* The address of the ALT_USB_DEV_DOEPDMA2 register. */ +#define ALT_USB_DEV_DOEPDMA2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA2_OFST)) + +/* + * Register : Device OUT Endpoint 2 DMA Buffer Address Register - doepdmab2 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------------------------ + * [31:0] | R | Unknown | Device IN Endpoint 1 Buffer Address + * + */ +/* + * Field : Device IN Endpoint 1 Buffer Address - doepdmab2 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */ +#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */ +#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */ +#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value. */ +#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value. */ +#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB2. + */ +struct ALT_USB_DEV_DOEPDMAB2_s +{ + const uint32_t doepdmab2 : 32; /* Device IN Endpoint 1 Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB2. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB2_s ALT_USB_DEV_DOEPDMAB2_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB2 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB2_OFST 0x35c +/* The address of the ALT_USB_DEV_DOEPDMAB2 register. */ +#define ALT_USB_DEV_DOEPDMAB2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB2_OFST)) + +/* + * Register : Device Control OUT Endpoint 3 Control Register - DOEPCTL3 + * + * Out Endpoint 3. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL3_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL3_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL3_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL3_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL3_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL3_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL3_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL3_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL3_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL3_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL3_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL3_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL3_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL3_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL3_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL3_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL3_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL3_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL3_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL3_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL3_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL3_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL3_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL3_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL3_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL3_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL3_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL3_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL3_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL3_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL3_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL3_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL3_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL3_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL3_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL3_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL3_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL3_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL3_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL3_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL3_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL3_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL3_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL3_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL3_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL3_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL3_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL3_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL3_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL3_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL3_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL3_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL3_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL3_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL3_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL3_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL3_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL3_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL3_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL3_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL3_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL3_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL3_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL3_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL3_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL3_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL3_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL3_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL3_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL3_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL3_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL3_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL3_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL3_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL3_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL3_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL3_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL3_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL3_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL3_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL3_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL3_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL3_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL3_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL3_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL3_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL3_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL3_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL3_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL3_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL3_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL3_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL3_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL3_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL3_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL3_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL3_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL3_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL3_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL3_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL3_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL3_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL3_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL3_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL3_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL3_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL3_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL3_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL3_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL3_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL3_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL3_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL3_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL3_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL3_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL3_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL3_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL3_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL3_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL3_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL3_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL3_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL3_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL3_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL3_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL3_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL3. + */ +struct ALT_USB_DEV_DOEPCTL3_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL3. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL3_s ALT_USB_DEV_DOEPCTL3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL3 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL3_OFST 0x360 +/* The address of the ALT_USB_DEV_DOEPCTL3 register. */ +#define ALT_USB_DEV_DOEPCTL3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL3_OFST)) + +/* + * Register : Device OUT Endpoint 3 Interrupt Register - doepint3 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT3_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT3_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT3_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT3_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT3_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT3_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT3_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT3_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT3_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT3_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT3_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT3_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT3_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT3_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT3_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT3_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT3_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT3_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT3_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT3_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT3_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT3_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT3_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT3_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT3_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT3_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT3_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT3_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT3_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT3_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT3_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT3_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT3_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT3_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT3_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT3_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT3_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT3_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT3_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT3_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT3_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT3_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT3_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT3_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT3_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT3_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT3_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT3_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT3_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT3_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT3_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT3_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT3_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT3_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT3_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT3_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT3_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT3_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT3. + */ +struct ALT_USB_DEV_DOEPINT3_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT3_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT3. */ +typedef volatile struct ALT_USB_DEV_DOEPINT3_s ALT_USB_DEV_DOEPINT3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT3 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT3_OFST 0x368 +/* The address of the ALT_USB_DEV_DOEPINT3 register. */ +#define ALT_USB_DEV_DOEPINT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT3_OFST)) + +/* + * Register : Device OUT Endpoint 3 Transfer Size Register - doeptsiz3 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ3_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ3_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ3. + */ +struct ALT_USB_DEV_DOEPTSIZ3_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ3. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ3_s ALT_USB_DEV_DOEPTSIZ3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ3 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ3_OFST 0x370 +/* The address of the ALT_USB_DEV_DOEPTSIZ3 register. */ +#define ALT_USB_DEV_DOEPTSIZ3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ3_OFST)) + +/* + * Register : Device OUT Endpoint 3 DMA Address Register - doepdma3 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma3 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */ +#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */ +#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */ +#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value. */ +#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value. */ +#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA3. + */ +struct ALT_USB_DEV_DOEPDMA3_s +{ + uint32_t doepdma3 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA3. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA3_s ALT_USB_DEV_DOEPDMA3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA3 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA3_OFST 0x374 +/* The address of the ALT_USB_DEV_DOEPDMA3 register. */ +#define ALT_USB_DEV_DOEPDMA3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA3_OFST)) + +/* + * Register : Device OUT Endpoint 3 DMA Buffer Address Register - doepdmab3 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab3 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */ +#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */ +#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */ +#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value. */ +#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value. */ +#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB3. + */ +struct ALT_USB_DEV_DOEPDMAB3_s +{ + const uint32_t doepdmab3 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB3. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB3_s ALT_USB_DEV_DOEPDMAB3_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB3 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB3_OFST 0x37c +/* The address of the ALT_USB_DEV_DOEPDMAB3 register. */ +#define ALT_USB_DEV_DOEPDMAB3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB3_OFST)) + +/* + * Register : Device Control OUT Endpoint 4 Control Register - doepctl4 + * + * Out Endpoint 4. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL4_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL4_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL4_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL4_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL4_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL4_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL4_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL4_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL4_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL4_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL4_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL4_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL4_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL4_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL4_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL4_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL4_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL4_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL4_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL4_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL4_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL4_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL4_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL4_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL4_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL4_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL4_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL4_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL4_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL4_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL4_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL4_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL4_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL4_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL4_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL4_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL4_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL4_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL4_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL4_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL4_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL4_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL4_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL4_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL4_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL4_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL4_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL4_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL4_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL4_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL4_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL4_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL4_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL4_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL4_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL4_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL4_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL4_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL4_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL4_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL4_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL4_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL4_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL4_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL4_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL4_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL4_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL4_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL4_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL4_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL4_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL4_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL4_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL4_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL4_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL4_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL4_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL4_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL4_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL4_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL4_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL4_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL4_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL4_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL4_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL4_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL4_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL4_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL4_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL4_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL4_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL4_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL4_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL4_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL4_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL4_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL4_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL4_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL4_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL4_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL4_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL4_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL4_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL4_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL4_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL4_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL4_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL4_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL4_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL4_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL4_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL4_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL4_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL4_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL4_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL4_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL4_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL4_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL4_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL4_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL4_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL4_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL4_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL4_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL4_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL4_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL4. + */ +struct ALT_USB_DEV_DOEPCTL4_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL4. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL4_s ALT_USB_DEV_DOEPCTL4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL4 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL4_OFST 0x380 +/* The address of the ALT_USB_DEV_DOEPCTL4 register. */ +#define ALT_USB_DEV_DOEPCTL4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL4_OFST)) + +/* + * Register : Device OUT Endpoint 4 Interrupt Register - Doepint4 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT4_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT4_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT4_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT4_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT4_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT4_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT4_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT4_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT4_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT4_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT4_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT4_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT4_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT4_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT4_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT4_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT4_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT4_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT4_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT4_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT4_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT4_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT4_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT4_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT4_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT4_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT4_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT4_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT4_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT4_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT4_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT4_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT4_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT4_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT4_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT4_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT4_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT4_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT4_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT4_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT4_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT4_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT4_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT4_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT4_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT4_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT4_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT4_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT4_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT4_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT4_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT4_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT4_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT4_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT4_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT4_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT4_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT4_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT4. + */ +struct ALT_USB_DEV_DOEPINT4_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT4_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT4. */ +typedef volatile struct ALT_USB_DEV_DOEPINT4_s ALT_USB_DEV_DOEPINT4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT4 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT4_OFST 0x388 +/* The address of the ALT_USB_DEV_DOEPINT4 register. */ +#define ALT_USB_DEV_DOEPINT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT4_OFST)) + +/* + * Register : Device OUT Endpoint 4 Transfer Size Register - doeptsiz4 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ4_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ4_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ4. + */ +struct ALT_USB_DEV_DOEPTSIZ4_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ4. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ4_s ALT_USB_DEV_DOEPTSIZ4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ4 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ4_OFST 0x390 +/* The address of the ALT_USB_DEV_DOEPTSIZ4 register. */ +#define ALT_USB_DEV_DOEPTSIZ4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ4_OFST)) + +/* + * Register : Device OUT Endpoint 4 DMA Address Register - doepdma4 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma4 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */ +#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */ +#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */ +#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value. */ +#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value. */ +#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA4. + */ +struct ALT_USB_DEV_DOEPDMA4_s +{ + uint32_t doepdma4 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA4. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA4_s ALT_USB_DEV_DOEPDMA4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA4 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA4_OFST 0x394 +/* The address of the ALT_USB_DEV_DOEPDMA4 register. */ +#define ALT_USB_DEV_DOEPDMA4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA4_OFST)) + +/* + * Register : Device OUT Endpoint 4 Buffer Address Register - doepdmab4 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab4 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */ +#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */ +#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */ +#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value. */ +#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value. */ +#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB4. + */ +struct ALT_USB_DEV_DOEPDMAB4_s +{ + const uint32_t doepdmab4 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB4. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB4_s ALT_USB_DEV_DOEPDMAB4_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB4 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB4_OFST 0x39c +/* The address of the ALT_USB_DEV_DOEPDMAB4 register. */ +#define ALT_USB_DEV_DOEPDMAB4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB4_OFST)) + +/* + * Register : Device Control OUT Endpoint 5 Control Register - doepctl5 + * + * Out Endpoint 5. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL5_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL5_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL5_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL5_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL5_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL5_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL5_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL5_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL5_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL5_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL5_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL5_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL5_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL5_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL5_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL5_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL5_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL5_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL5_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * + * 0: DATA0 1: DATA1This field is applicable both for Scatter/Gather DMA mode and + * non-Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non- + * Scatter/Gather DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL5_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL5_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL5_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL5_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL5_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL5_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL5_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL5_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL5_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL5_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL5_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL5_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL5_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL5_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL5_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL5_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL5_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL5_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL5_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL5_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL5_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL5_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL5_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL5_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL5_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL5_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL5_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL5_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL5_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL5_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL5_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL5_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL5_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL5_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL5_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL5_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL5_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL5_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL5_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL5_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL5_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL5_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL5_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL5_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL5_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL5_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL5_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL5_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL5_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL5_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL5_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL5_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL5_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL5_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL5_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL5_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL5_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL5_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL5_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL5_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL5_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL5_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL5_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL5_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL5_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL5_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL5_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL5_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL5_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL5_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL5_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL5_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL5_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL5_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL5_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL5_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL5_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL5_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL5_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL5_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL5_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL5_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL5_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL5_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL5_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL5_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL5_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL5_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL5_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL5_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL5_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL5_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL5_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL5_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL5_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL5_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL5_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL5_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL5_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL5_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL5_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL5_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL5_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL5_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL5_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL5_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL5_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL5. + */ +struct ALT_USB_DEV_DOEPCTL5_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL5. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL5_s ALT_USB_DEV_DOEPCTL5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL5 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL5_OFST 0x3a0 +/* The address of the ALT_USB_DEV_DOEPCTL5 register. */ +#define ALT_USB_DEV_DOEPCTL5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL5_OFST)) + +/* + * Register : Device OUT Endpoint 5 Interrupt Register - doepint5 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT5_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT5_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT5_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT5_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT5_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT5_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT5_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT5_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT5_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT5_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT5_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT5_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT5_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT5_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT5_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT5_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT5_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT5_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT5_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT5_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT5_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT5_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT5_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT5_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT5_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT5_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT5_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT5_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT5_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT5_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT5_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT5_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT5_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT5_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT5_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT5_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT5_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT5_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT5_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT5_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT5_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT5_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT5_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT5_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT5_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT5_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT5_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT5_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT5_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT5_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT5_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT5_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT5_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT5_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT5_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT5_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT5_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT5_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT5. + */ +struct ALT_USB_DEV_DOEPINT5_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT5_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT5. */ +typedef volatile struct ALT_USB_DEV_DOEPINT5_s ALT_USB_DEV_DOEPINT5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT5 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT5_OFST 0x3a8 +/* The address of the ALT_USB_DEV_DOEPINT5 register. */ +#define ALT_USB_DEV_DOEPINT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT5_OFST)) + +/* + * Register : Device OUT Endpoint 5 Transfer Size Register - doeptsiz5 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ5_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ5_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ5. + */ +struct ALT_USB_DEV_DOEPTSIZ5_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ5. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ5_s ALT_USB_DEV_DOEPTSIZ5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ5 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ5_OFST 0x3b0 +/* The address of the ALT_USB_DEV_DOEPTSIZ5 register. */ +#define ALT_USB_DEV_DOEPTSIZ5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ5_OFST)) + +/* + * Register : Device OUT Endpoint 5 DMA Address Register - doepdma5 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma5 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */ +#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */ +#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */ +#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value. */ +#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value. */ +#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA5. + */ +struct ALT_USB_DEV_DOEPDMA5_s +{ + uint32_t doepdma5 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA5. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA5_s ALT_USB_DEV_DOEPDMA5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA5 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA5_OFST 0x3b4 +/* The address of the ALT_USB_DEV_DOEPDMA5 register. */ +#define ALT_USB_DEV_DOEPDMA5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA5_OFST)) + +/* + * Register : Device OUT Endpoint 5 DMA Buffer Address Register - doepdmab5 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab5 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */ +#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */ +#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */ +#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value. */ +#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value. */ +#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB5. + */ +struct ALT_USB_DEV_DOEPDMAB5_s +{ + const uint32_t doepdmab5 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB5. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB5_s ALT_USB_DEV_DOEPDMAB5_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB5 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB5_OFST 0x3bc +/* The address of the ALT_USB_DEV_DOEPDMAB5 register. */ +#define ALT_USB_DEV_DOEPDMAB5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB5_OFST)) + +/* + * Register : Device Control OUT Endpoint 6 Control Register - doepctl6 + * + * Out Endpoint 6. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL6_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL6_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL6_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL6_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL6_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL6_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL6_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL6_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL6_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL6_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL6_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL6_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL6_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL6_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL6_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL6_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL6_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL6_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL6_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * + * 0: DATA0 1: DATA1This field is applicable both for Scatter/Gather DMA mode and + * non-Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non- + * Scatter/Gather DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL6_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL6_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL6_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL6_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL6_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL6_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL6_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL6_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL6_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL6_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL6_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL6_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL6_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL6_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL6_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL6_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL6_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL6_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL6_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL6_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL6_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL6_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL6_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL6_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL6_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL6_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL6_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL6_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL6_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL6_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL6_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL6_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL6_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL6_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL6_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL6_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL6_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL6_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL6_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL6_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL6_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL6_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL6_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL6_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL6_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL6_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL6_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL6_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL6_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL6_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL6_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL6_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL6_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL6_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL6_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL6_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL6_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL6_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL6_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL6_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL6_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL6_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL6_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL6_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL6_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL6_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL6_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL6_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL6_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL6_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL6_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL6_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL6_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL6_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL6_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL6_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL6_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL6_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL6_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL6_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL6_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL6_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL6_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL6_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL6_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL6_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL6_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL6_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL6_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL6_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL6_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL6_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL6_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL6_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL6_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL6_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL6_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL6_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL6_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL6_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL6_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL6_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL6_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL6_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL6_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL6_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL6_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL6. + */ +struct ALT_USB_DEV_DOEPCTL6_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL6. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL6_s ALT_USB_DEV_DOEPCTL6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL6 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL6_OFST 0x3c0 +/* The address of the ALT_USB_DEV_DOEPCTL6 register. */ +#define ALT_USB_DEV_DOEPCTL6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL6_OFST)) + +/* + * Register : Device OUT Endpoint 6 Interrupt Register - doepint6 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT6_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT6_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT6_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT6_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT6_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT6_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT6_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT6_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT6_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT6_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT6_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT6_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT6_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT6_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT6_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT6_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT6_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT6_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT6_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT6_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT6_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT6_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT6_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT6_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT6_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT6_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT6_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT6_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT6_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT6_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT6_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT6_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT6_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT6_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT6_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT6_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT6_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT6_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT6_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT6_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT6_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT6_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT6_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT6_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT6_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT6_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT6_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT6_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT6_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT6_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT6_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT6_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT6_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT6_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT6_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT6_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT6_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT6_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT6. + */ +struct ALT_USB_DEV_DOEPINT6_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT6_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT6. */ +typedef volatile struct ALT_USB_DEV_DOEPINT6_s ALT_USB_DEV_DOEPINT6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT6 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT6_OFST 0x3c8 +/* The address of the ALT_USB_DEV_DOEPINT6 register. */ +#define ALT_USB_DEV_DOEPINT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT6_OFST)) + +/* + * Register : Device OUT Endpoint 6 Transfer Size Register - doeptsiz6 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ6_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ6_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ6. + */ +struct ALT_USB_DEV_DOEPTSIZ6_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ6. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ6_s ALT_USB_DEV_DOEPTSIZ6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ6 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ6_OFST 0x3d0 +/* The address of the ALT_USB_DEV_DOEPTSIZ6 register. */ +#define ALT_USB_DEV_DOEPTSIZ6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ6_OFST)) + +/* + * Register : Device OUT Endpoint 6 DMA Address Register - doepdma6 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma6 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */ +#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */ +#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */ +#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value. */ +#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value. */ +#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA6. + */ +struct ALT_USB_DEV_DOEPDMA6_s +{ + uint32_t doepdma6 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA6. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA6_s ALT_USB_DEV_DOEPDMA6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA6 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA6_OFST 0x3d4 +/* The address of the ALT_USB_DEV_DOEPDMA6 register. */ +#define ALT_USB_DEV_DOEPDMA6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA6_OFST)) + +/* + * Register : Device OUT Endpoint 6 DMA Buffer Address Register - doepdmab6 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab6 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */ +#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */ +#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */ +#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value. */ +#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value. */ +#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB6. + */ +struct ALT_USB_DEV_DOEPDMAB6_s +{ + const uint32_t doepdmab6 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB6. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB6_s ALT_USB_DEV_DOEPDMAB6_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB6 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB6_OFST 0x3dc +/* The address of the ALT_USB_DEV_DOEPDMAB6 register. */ +#define ALT_USB_DEV_DOEPDMAB6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB6_OFST)) + +/* + * Register : Device Control OUT Endpoint 7 Control Register - doepctl7 + * + * Endpoint_number: 7 + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | ??? | 0x0 | *UNDEFINED* + * [21] | R | 0x0 | STALL Handshake + * [25:22] | RW | 0x0 | TxFIFO Number + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL7_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL7_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL7_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL7_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL7_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL7_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL7_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL7_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL7_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL7_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL7_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL7_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL7_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL7_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL7_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL7_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL7_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL7_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL7_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * + * 0: DATA0 1: DATA1This field is applicable both for Scatter/Gather DMA mode and + * non-Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non- + * Scatter/Gather DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL7_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL7_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL7_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL7_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL7_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL7_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL7_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL7_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL7_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL7_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL7_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL7_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL7_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL7_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL7_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL7_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL7_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL7_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL7_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL7_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL7_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL7_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL7_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL7_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL7_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL7_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL7_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL7_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL7_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL7_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL7_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL7_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL7_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL7_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : TxFIFO Number - txfnum + * + * Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic + * endpoints must map this to the corresponding Periodic TxFIFO number. + * + * 4'h0: Non-Periodic TxFIFO + * + * Others: Specified Periodic TxFIFO.number + * + * An interrupt IN endpoint can be configured as a non-periodic endpoint for + * applications such as mass storage. The core treats an IN endpoint as a non- + * periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN + * endpoint as a non-periodic endpoint saves the extra periodic FIFO area. + * Dedicated FIFO Operation-these bits specify the FIFO number associated with this + * endpoint. Each active IN endpoint must be programmed to a separate FIFO number. + * This field is valid only for IN endpoints. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_TXFNUM register field. */ +#define ALT_USB_DEV_DOEPCTL7_TXFNUM_LSB 22 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_TXFNUM register field. */ +#define ALT_USB_DEV_DOEPCTL7_TXFNUM_MSB 25 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_TXFNUM register field. */ +#define ALT_USB_DEV_DOEPCTL7_TXFNUM_WIDTH 4 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_TXFNUM register field value. */ +#define ALT_USB_DEV_DOEPCTL7_TXFNUM_SET_MSK 0x03c00000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_TXFNUM register field value. */ +#define ALT_USB_DEV_DOEPCTL7_TXFNUM_CLR_MSK 0xfc3fffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_TXFNUM register field. */ +#define ALT_USB_DEV_DOEPCTL7_TXFNUM_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_TXFNUM field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) +/* Produces a ALT_USB_DEV_DOEPCTL7_TXFNUM register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL7_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL7_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL7_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL7_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL7_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL7_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL7_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL7_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL7_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL7_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL7_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL7_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL7_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL7_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL7_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL7_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL7_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL7_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL7_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL7_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL7_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL7_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL7_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL7_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL7_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD0PID + * + * Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL7_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL7_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL7_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL7_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL7_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL7_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL7_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL7_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL7_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL7_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL7_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL7_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL7_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL7_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL7_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL7_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL7_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL7_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL7_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL7_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL7_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL7_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL7_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL7_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL7_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL7_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL7_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL7_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL7_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL7_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL7_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL7_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL7_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL7_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL7_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL7_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL7_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL7. + */ +struct ALT_USB_DEV_DOEPCTL7_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t txfnum : 4; /* TxFIFO Number */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL7. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL7_s ALT_USB_DEV_DOEPCTL7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL7 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL7_OFST 0x3e0 +/* The address of the ALT_USB_DEV_DOEPCTL7 register. */ +#define ALT_USB_DEV_DOEPCTL7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL7_OFST)) + +/* + * Register : Device OUT Endpoint 7 Interrupt Register - doepint7 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT7_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT7_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT7_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT7_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT7_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT7_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT7_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT7_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT7_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT7_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT7_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT7_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT7_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT7_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT7_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT7_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT7_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT7_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT7_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT7_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT7_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT7_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT7_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT7_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT7_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT7_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT7_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT7_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT7_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT7_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT7_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT7_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT7_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT7_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT7_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT7_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT7_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT7_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT7_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT7_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT7_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT7_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT7_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT7_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT7_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT7_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT7_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT7_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT7_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT7_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT7_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT7_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT7_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT7_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT7_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT7_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT7_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT7_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT7. + */ +struct ALT_USB_DEV_DOEPINT7_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT7_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT7. */ +typedef volatile struct ALT_USB_DEV_DOEPINT7_s ALT_USB_DEV_DOEPINT7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT7 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT7_OFST 0x3e8 +/* The address of the ALT_USB_DEV_DOEPINT7 register. */ +#define ALT_USB_DEV_DOEPINT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT7_OFST)) + +/* + * Register : Device OUT Endpoint 7 Transfer Size Register - doeptsiz7 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ7_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ7_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ7. + */ +struct ALT_USB_DEV_DOEPTSIZ7_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ7. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ7_s ALT_USB_DEV_DOEPTSIZ7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ7 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ7_OFST 0x3f0 +/* The address of the ALT_USB_DEV_DOEPTSIZ7 register. */ +#define ALT_USB_DEV_DOEPTSIZ7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ7_OFST)) + +/* + * Register : Device OUT Endpoint 7 DMA Address Register - doepdma7 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma7 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */ +#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */ +#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */ +#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value. */ +#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value. */ +#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA7. + */ +struct ALT_USB_DEV_DOEPDMA7_s +{ + uint32_t doepdma7 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA7. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA7_s ALT_USB_DEV_DOEPDMA7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA7 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA7_OFST 0x3f4 +/* The address of the ALT_USB_DEV_DOEPDMA7 register. */ +#define ALT_USB_DEV_DOEPDMA7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA7_OFST)) + +/* + * Register : Device OUT Endpoint 7 Buffer Address - doepdmab7 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab7 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */ +#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */ +#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */ +#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value. */ +#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value. */ +#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB7. + */ +struct ALT_USB_DEV_DOEPDMAB7_s +{ + const uint32_t doepdmab7 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB7. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB7_s ALT_USB_DEV_DOEPDMAB7_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB7 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB7_OFST 0x3fc +/* The address of the ALT_USB_DEV_DOEPDMAB7 register. */ +#define ALT_USB_DEV_DOEPDMAB7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB7_OFST)) + +/* + * Register : Device Control OUT Endpoint 8 Control Register - doepctl8 + * + * Out Endpoint 8. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL8_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL8_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL8_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL8_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL8_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL8_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL8_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL8_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL8_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL8_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL8_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL8_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL8_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL8_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL8_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL8_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL8_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL8_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL8_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * + * 0: DATA0 + * + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL8_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL8_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL8_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL8_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL8_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL8_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL8_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL8_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL8_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL8_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL8_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL8_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL8_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL8_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL8_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL8_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL8_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL8_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL8_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL8_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL8_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL8_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL8_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL8_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL8_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL8_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL8_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL8_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL8_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL8_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL8_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL8_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL8_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL8_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL8_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL8_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL8_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL8_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL8_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL8_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL8_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL8_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL8_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL8_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL8_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL8_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL8_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL8_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL8_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL8_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL8_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL8_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL8_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL8_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL8_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL8_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL8_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL8_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL8_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL8_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL8_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL8_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL8_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL8_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL8_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL8_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL8_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL8_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL8_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL8_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL8_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL8_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL8_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL8_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL8_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL8_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL8_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL8_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL8_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL8_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL8_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL8_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL8_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL8_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL8_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL8_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL8_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL8_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL8_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL8_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL8_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL8_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL8_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL8_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL8_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL8_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL8_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL8_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL8_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL8_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL8_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL8_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL8_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL8_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL8_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL8_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL8_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL8. + */ +struct ALT_USB_DEV_DOEPCTL8_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL8. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL8_s ALT_USB_DEV_DOEPCTL8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL8 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL8_OFST 0x400 +/* The address of the ALT_USB_DEV_DOEPCTL8 register. */ +#define ALT_USB_DEV_DOEPCTL8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL8_OFST)) + +/* + * Register : Device OUT Endpoint 8 Interrupt Register - doepint8 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT8_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT8_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT8_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT8_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT8_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT8_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT8_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT8_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT8_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT8_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT8_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT8_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT8_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT8_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT8_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT8_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT8_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT8_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT8_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT8_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT8_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT8_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT8_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT8_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT8_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT8_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT8_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT8_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT8_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT8_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT8_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT8_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT8_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT8_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT8_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT8_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT8_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT8_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT8_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT8_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT8_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT8_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT8_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT8_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT8_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT8_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT8_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT8_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT8_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT8_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT8_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT8_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT8_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT8_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT8_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT8_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT8_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT8_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT8. + */ +struct ALT_USB_DEV_DOEPINT8_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT8_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT8. */ +typedef volatile struct ALT_USB_DEV_DOEPINT8_s ALT_USB_DEV_DOEPINT8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT8 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT8_OFST 0x408 +/* The address of the ALT_USB_DEV_DOEPINT8 register. */ +#define ALT_USB_DEV_DOEPINT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT8_OFST)) + +/* + * Register : Device OUT Endpoint 8 Transfer Size Register - doeptsiz8 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ8_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ8_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ8. + */ +struct ALT_USB_DEV_DOEPTSIZ8_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ8. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ8_s ALT_USB_DEV_DOEPTSIZ8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ8 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ8_OFST 0x410 +/* The address of the ALT_USB_DEV_DOEPTSIZ8 register. */ +#define ALT_USB_DEV_DOEPTSIZ8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ8_OFST)) + +/* + * Register : Device OUT Endpoint 8 DMA Address Register - doepdma8 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma8 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */ +#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */ +#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */ +#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value. */ +#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value. */ +#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA8. + */ +struct ALT_USB_DEV_DOEPDMA8_s +{ + uint32_t doepdma8 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA8. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA8_s ALT_USB_DEV_DOEPDMA8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA8 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA8_OFST 0x414 +/* The address of the ALT_USB_DEV_DOEPDMA8 register. */ +#define ALT_USB_DEV_DOEPDMA8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA8_OFST)) + +/* + * Register : Device OUT Endpoint 8 DMA Buffer Address Register - doepdmab8 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab8 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */ +#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */ +#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */ +#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value. */ +#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value. */ +#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB8. + */ +struct ALT_USB_DEV_DOEPDMAB8_s +{ + const uint32_t doepdmab8 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB8. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB8_s ALT_USB_DEV_DOEPDMAB8_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB8 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB8_OFST 0x41c +/* The address of the ALT_USB_DEV_DOEPDMAB8 register. */ +#define ALT_USB_DEV_DOEPDMAB8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB8_OFST)) + +/* + * Register : Device Control OUT Endpoint 9 Control Register - doepctl9 + * + * Out Endpoint 9. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL9_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL9_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL9_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL9_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL9_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL9_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL9_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL9_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL9_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL9_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL9_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL9_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL9_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL9_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL9_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL9_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL9_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL9_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL9_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * + * 0: DATA0 + * + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL9_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL9_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL9_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL9_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL9_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL9_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL9_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL9_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL9_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL9_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL9_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL9_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL9_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL9_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL9_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL9_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL9_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL9_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL9_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL9_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL9_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL9_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL9_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL9_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL9_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL9_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL9_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL9_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL9_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL9_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL9_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL9_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL9_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL9_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL9_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL9_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL9_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL9_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL9_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL9_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL9_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL9_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL9_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL9_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL9_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL9_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL9_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL9_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL9_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL9_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL9_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL9_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL9_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL9_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL9_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL9_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL9_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL9_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL9_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL9_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL9_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL9_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL9_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL9_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL9_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL9_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL9_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL9_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL9_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL9_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL9_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL9_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL9_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL9_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL9_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL9_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL9_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL9_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL9_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL9_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL9_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL9_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL9_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL9_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL9_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL9_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL9_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL9_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL9_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL9_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL9_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL9_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL9_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL9_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL9_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL9_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL9_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL9_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL9_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL9_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL9_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL9_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL9_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL9_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL9_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL9_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL9_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL9. + */ +struct ALT_USB_DEV_DOEPCTL9_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL9. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL9_s ALT_USB_DEV_DOEPCTL9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL9 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL9_OFST 0x420 +/* The address of the ALT_USB_DEV_DOEPCTL9 register. */ +#define ALT_USB_DEV_DOEPCTL9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL9_OFST)) + +/* + * Register : Device OUT Endpoint 9 Interrupt Register - doepint9 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT9_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT9_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT9_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT9_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT9_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT9_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT9_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT9_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT9_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT9_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT9_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT9_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT9_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT9_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT9_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT9_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT9_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT9_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT9_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT9_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT9_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT9_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT9_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT9_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT9_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT9_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT9_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT9_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT9_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT9_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT9_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT9_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT9_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT9_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT9_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT9_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT9_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT9_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT9_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT9_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT9_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT9_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT9_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT9_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT9_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT9_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT9_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT9_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT9_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT9_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT9_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT9_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT9_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT9_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT9_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT9_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT9_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT9_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT9. + */ +struct ALT_USB_DEV_DOEPINT9_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT9_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT9. */ +typedef volatile struct ALT_USB_DEV_DOEPINT9_s ALT_USB_DEV_DOEPINT9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT9 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT9_OFST 0x428 +/* The address of the ALT_USB_DEV_DOEPINT9 register. */ +#define ALT_USB_DEV_DOEPINT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT9_OFST)) + +/* + * Register : Device OUT Endpoint 9 Transfer Size Register - doeptsiz9 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ9_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ9_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ9. + */ +struct ALT_USB_DEV_DOEPTSIZ9_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ9. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ9_s ALT_USB_DEV_DOEPTSIZ9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ9 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ9_OFST 0x430 +/* The address of the ALT_USB_DEV_DOEPTSIZ9 register. */ +#define ALT_USB_DEV_DOEPTSIZ9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ9_OFST)) + +/* + * Register : Device OUT Endpoint 9 DMA Address Register - doepdma9 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma9 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */ +#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */ +#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */ +#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value. */ +#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value. */ +#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA9. + */ +struct ALT_USB_DEV_DOEPDMA9_s +{ + uint32_t doepdma9 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA9. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA9_s ALT_USB_DEV_DOEPDMA9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA9 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA9_OFST 0x434 +/* The address of the ALT_USB_DEV_DOEPDMA9 register. */ +#define ALT_USB_DEV_DOEPDMA9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA9_OFST)) + +/* + * Register : Device OUT Endpoint 9 DMA Buffer Address Register - doepdmab9 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab9 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */ +#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */ +#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */ +#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value. */ +#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value. */ +#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB9. + */ +struct ALT_USB_DEV_DOEPDMAB9_s +{ + const uint32_t doepdmab9 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB9. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB9_s ALT_USB_DEV_DOEPDMAB9_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB9 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB9_OFST 0x43c +/* The address of the ALT_USB_DEV_DOEPDMAB9 register. */ +#define ALT_USB_DEV_DOEPDMAB9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB9_OFST)) + +/* + * Register : Device Control OUT Endpoint 10 Control Register - doepctl10 + * + * Out Endpoint 10. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL10_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL10_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL10_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL10_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL10_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL10_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL10_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL10_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL10_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL10_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL10_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL10_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL10_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL10_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL10_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL10_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL10_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL10_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL10_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL10_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL10_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL10_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL10_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL10_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL10_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL10_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL10_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL10_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL10_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL10_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL10_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL10_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL10_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL10_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL10_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL10_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL10_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL10_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL10_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL10_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL10_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL10_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL10_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL10_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL10_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL10_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL10_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL10_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL10_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL10_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL10_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL10_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL10_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL10_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL10_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL10_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL10_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL10_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL10_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL10_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL10_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL10_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL10_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL10_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL10_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL10_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL10_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL10_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL10_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL10_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL10_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL10_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL10_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL10_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL10_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL10_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL10_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL10_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL10_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL10_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL10_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL10_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL10_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL10_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL10_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL10_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL10_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL10_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL10_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL10_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL10_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL10_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL10_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL10_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL10_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL10_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL10_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL10_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL10_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL10_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL10_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL10_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL10_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL10_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL10_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL10_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL10_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL10_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL10_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL10_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL10_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL10_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL10_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL10_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL10_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL10_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL10_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL10_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL10_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL10_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL10_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL10_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL10_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL10_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL10_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL10_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL10. + */ +struct ALT_USB_DEV_DOEPCTL10_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL10. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL10_s ALT_USB_DEV_DOEPCTL10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL10 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL10_OFST 0x440 +/* The address of the ALT_USB_DEV_DOEPCTL10 register. */ +#define ALT_USB_DEV_DOEPCTL10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL10_OFST)) + +/* + * Register : Device OUT Endpoint 10 Interrupt Register - doepint10 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT10_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT10_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT10_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT10_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT10_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT10_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT10_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT10_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT10_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT10_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT10_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT10_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT10_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT10_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT10_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT10_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT10_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT10_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT10_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT10_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT10_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT10_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT10_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT10_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT10_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT10_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT10_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT10_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT10_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT10_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT10_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT10_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT10_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT10_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT10_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT10_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT10_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT10_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT10_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT10_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT10_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT10_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT10_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT10_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT10_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT10_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT10_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT10_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT10_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT10_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT10_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT10_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT10_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT10_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT10_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT10_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT10_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT10_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT10. + */ +struct ALT_USB_DEV_DOEPINT10_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT10_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT10. */ +typedef volatile struct ALT_USB_DEV_DOEPINT10_s ALT_USB_DEV_DOEPINT10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT10 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT10_OFST 0x448 +/* The address of the ALT_USB_DEV_DOEPINT10 register. */ +#define ALT_USB_DEV_DOEPINT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT10_OFST)) + +/* + * Register : Device OUT Endpoint 10 Transfer Size Register - doeptsiz10 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ10_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ10_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ10. + */ +struct ALT_USB_DEV_DOEPTSIZ10_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ10. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ10_s ALT_USB_DEV_DOEPTSIZ10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ10 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ10_OFST 0x450 +/* The address of the ALT_USB_DEV_DOEPTSIZ10 register. */ +#define ALT_USB_DEV_DOEPTSIZ10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ10_OFST)) + +/* + * Register : Device OUT Endpoint 10 DMA Address Register - doepdma10 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma10 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */ +#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */ +#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */ +#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value. */ +#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value. */ +#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA10. + */ +struct ALT_USB_DEV_DOEPDMA10_s +{ + uint32_t doepdma10 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA10. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA10_s ALT_USB_DEV_DOEPDMA10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA10 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA10_OFST 0x454 +/* The address of the ALT_USB_DEV_DOEPDMA10 register. */ +#define ALT_USB_DEV_DOEPDMA10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA10_OFST)) + +/* + * Register : Device OUT Endpoint 10 DMA Buffer Address Register - doepdmab10 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab10 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */ +#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */ +#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */ +#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value. */ +#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value. */ +#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB10. + */ +struct ALT_USB_DEV_DOEPDMAB10_s +{ + const uint32_t doepdmab10 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB10. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB10_s ALT_USB_DEV_DOEPDMAB10_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB10 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB10_OFST 0x45c +/* The address of the ALT_USB_DEV_DOEPDMAB10 register. */ +#define ALT_USB_DEV_DOEPDMAB10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB10_OFST)) + +/* + * Register : Device Control OUT Endpoint 11 Control Register - doepctl11 + * + * Out Endpoint 11. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL11_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL11_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL11_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL11_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL11_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL11_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL11_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL11_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL11_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL11_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL11_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL11_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL11_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL11_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL11_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL11_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL11_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL11_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL11_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * + * 0: DATA0 + * + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL11_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL11_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL11_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL11_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL11_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL11_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL11_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL11_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL11_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL11_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL11_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL11_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL11_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL11_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL11_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL11_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL11_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL11_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL11_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL11_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL11_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL11_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL11_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL11_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL11_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL11_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL11_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL11_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL11_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL11_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL11_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL11_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL11_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL11_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL11_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL11_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL11_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL11_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL11_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL11_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL11_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL11_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL11_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL11_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL11_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL11_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL11_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL11_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL11_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL11_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL11_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL11_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL11_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL11_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL11_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL11_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL11_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL11_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL11_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL11_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL11_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL11_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL11_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL11_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL11_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL11_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL11_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL11_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL11_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL11_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL11_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL11_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL11_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL11_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL11_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL11_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL11_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL11_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL11_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL11_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL11_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL11_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL11_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL11_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL11_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL11_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL11_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL11_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL11_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL11_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL11_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL11_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL11_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL11_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL11_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL11_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL11_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL11_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL11_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL11_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL11_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL11_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL11_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL11_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL11_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL11_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL11_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL11. + */ +struct ALT_USB_DEV_DOEPCTL11_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL11. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL11_s ALT_USB_DEV_DOEPCTL11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL11 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL11_OFST 0x460 +/* The address of the ALT_USB_DEV_DOEPCTL11 register. */ +#define ALT_USB_DEV_DOEPCTL11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL11_OFST)) + +/* + * Register : Device OUT Endpoint 11 Interrupt Register - doepint11 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT11_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT11_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT11_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT11_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT11_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT11_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT11_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT11_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT11_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT11_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT11_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT11_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT11_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT11_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT11_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT11_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT11_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT11_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT11_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT11_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT11_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT11_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT11_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT11_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT11_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT11_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT11_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT11_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT11_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT11_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT11_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT11_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT11_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT11_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT11_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT11_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT11_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT11_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT11_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT11_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT11_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT11_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT11_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT11_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT11_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT11_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT11_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT11_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT11_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT11_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT11_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT11_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT11_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT11_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT11_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT11_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT11_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT11_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT11. + */ +struct ALT_USB_DEV_DOEPINT11_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT11_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT11. */ +typedef volatile struct ALT_USB_DEV_DOEPINT11_s ALT_USB_DEV_DOEPINT11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT11 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT11_OFST 0x468 +/* The address of the ALT_USB_DEV_DOEPINT11 register. */ +#define ALT_USB_DEV_DOEPINT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT11_OFST)) + +/* + * Register : Device OUT Endpoint 11 Transfer Size Register - doeptsiz11 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ11_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ11_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ11. + */ +struct ALT_USB_DEV_DOEPTSIZ11_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ11. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ11_s ALT_USB_DEV_DOEPTSIZ11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ11 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ11_OFST 0x470 +/* The address of the ALT_USB_DEV_DOEPTSIZ11 register. */ +#define ALT_USB_DEV_DOEPTSIZ11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ11_OFST)) + +/* + * Register : Device OUT Endpoint 11 DMA Address Register - doepdma11 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma11 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */ +#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */ +#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */ +#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value. */ +#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value. */ +#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA11. + */ +struct ALT_USB_DEV_DOEPDMA11_s +{ + uint32_t doepdma11 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA11. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA11_s ALT_USB_DEV_DOEPDMA11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA11 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA11_OFST 0x474 +/* The address of the ALT_USB_DEV_DOEPDMA11 register. */ +#define ALT_USB_DEV_DOEPDMA11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA11_OFST)) + +/* + * Register : Device OUT Endpoint 11 DMA Buffer Address Register - doepdmab11 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab11 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */ +#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */ +#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */ +#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value. */ +#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value. */ +#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB11. + */ +struct ALT_USB_DEV_DOEPDMAB11_s +{ + const uint32_t doepdmab11 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB11. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB11_s ALT_USB_DEV_DOEPDMAB11_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB11 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB11_OFST 0x47c +/* The address of the ALT_USB_DEV_DOEPDMAB11 register. */ +#define ALT_USB_DEV_DOEPDMAB11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB11_OFST)) + +/* + * Register : Device Control OUT Endpoint 12 Control Register - doepctl12 + * + * Out Endpoint 12. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL12_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL12_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL12_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL12_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL12_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL12_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL12_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL12_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL12_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL12_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL12_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL12_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL12_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL12_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL12_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL12_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL12_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL12_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL12_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * + * 0: DATA0 + * + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL12_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL12_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL12_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL12_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL12_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL12_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL12_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL12_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL12_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL12_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL12_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL12_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL12_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL12_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL12_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL12_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL12_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL12_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL12_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL12_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL12_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL12_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL12_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL12_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL12_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL12_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL12_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL12_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL12_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL12_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL12_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL12_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL12_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL12_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL12_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL12_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL12_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL12_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL12_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL12_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL12_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL12_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL12_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL12_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL12_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL12_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL12_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL12_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL12_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL12_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL12_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL12_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL12_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL12_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL12_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL12_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL12_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL12_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL12_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL12_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL12_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL12_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL12_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL12_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL12_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL12_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL12_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL12_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL12_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL12_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL12_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL12_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL12_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL12_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL12_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL12_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL12_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL12_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL12_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL12_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL12_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL12_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL12_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL12_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL12_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL12_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL12_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL12_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL12_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL12_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL12_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL12_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL12_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL12_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL12_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL12_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL12_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL12_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL12_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL12_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL12_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL12_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL12_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL12_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL12_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL12_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL12_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL12. + */ +struct ALT_USB_DEV_DOEPCTL12_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL12. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL12_s ALT_USB_DEV_DOEPCTL12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL12 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL12_OFST 0x480 +/* The address of the ALT_USB_DEV_DOEPCTL12 register. */ +#define ALT_USB_DEV_DOEPCTL12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL12_OFST)) + +/* + * Register : Device OUT Endpoint 12 Interrupt Register - doepint12 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT12_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT12_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT12_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT12_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT12_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT12_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT12_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT12_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT12_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT12_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT12_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT12_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT12_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT12_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT12_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT12_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT12_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT12_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT12_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT12_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT12_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT12_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT12_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT12_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT12_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT12_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT12_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT12_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT12_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT12_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT12_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT12_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT12_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT12_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT12_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT12_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT12_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT12_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT12_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT12_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT12_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT12_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT12_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT12_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT12_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT12_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT12_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT12_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT12_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT12_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT12_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT12_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT12_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT12_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT12_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT12_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT12_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT12_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT12. + */ +struct ALT_USB_DEV_DOEPINT12_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT12_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT12. */ +typedef volatile struct ALT_USB_DEV_DOEPINT12_s ALT_USB_DEV_DOEPINT12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT12 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT12_OFST 0x488 +/* The address of the ALT_USB_DEV_DOEPINT12 register. */ +#define ALT_USB_DEV_DOEPINT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT12_OFST)) + +/* + * Register : Device OUT Endpoint 12 Transfer Size Register - doeptsiz12 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ12_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ12_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ12. + */ +struct ALT_USB_DEV_DOEPTSIZ12_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ12. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ12_s ALT_USB_DEV_DOEPTSIZ12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ12 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ12_OFST 0x490 +/* The address of the ALT_USB_DEV_DOEPTSIZ12 register. */ +#define ALT_USB_DEV_DOEPTSIZ12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ12_OFST)) + +/* + * Register : Device OUT Endpoint 12 DMA Address Register - doepdma12 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma12 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */ +#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */ +#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */ +#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value. */ +#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value. */ +#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA12. + */ +struct ALT_USB_DEV_DOEPDMA12_s +{ + uint32_t doepdma12 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA12. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA12_s ALT_USB_DEV_DOEPDMA12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA12 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA12_OFST 0x494 +/* The address of the ALT_USB_DEV_DOEPDMA12 register. */ +#define ALT_USB_DEV_DOEPDMA12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA12_OFST)) + +/* + * Register : Device OUT Endpoint 12 DMA Buffer Address Register - doepdmab12 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab12 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */ +#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */ +#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */ +#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value. */ +#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value. */ +#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB12. + */ +struct ALT_USB_DEV_DOEPDMAB12_s +{ + const uint32_t doepdmab12 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB12. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB12_s ALT_USB_DEV_DOEPDMAB12_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB12 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB12_OFST 0x49c +/* The address of the ALT_USB_DEV_DOEPDMAB12 register. */ +#define ALT_USB_DEV_DOEPDMAB12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB12_OFST)) + +/* + * Register : Device Control OUT Endpoint 13 Control Register - doepctl13 + * + * Out Endpoint 13. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL13_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL13_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL13_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL13_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL13_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL13_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL13_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL13_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL13_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL13_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL13_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL13_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL13_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL13_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL13_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL13_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL13_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL13_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL13_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * + * 0: DATA0 + * + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL13_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL13_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL13_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL13_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL13_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL13_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL13_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL13_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL13_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL13_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL13_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL13_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL13_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL13_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL13_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL13_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL13_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL13_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL13_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL13_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL13_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL13_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL13_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL13_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL13_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL13_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL13_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL13_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL13_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL13_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL13_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL13_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL13_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL13_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL13_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL13_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL13_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL13_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL13_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL13_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL13_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL13_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL13_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL13_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL13_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL13_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL13_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL13_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL13_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL13_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL13_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL13_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL13_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL13_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL13_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL13_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL13_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL13_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL13_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL13_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL13_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL13_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL13_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL13_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL13_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL13_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL13_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL13_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL13_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL13_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL13_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL13_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL13_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL13_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL13_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL13_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL13_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL13_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL13_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL13_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL13_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL13_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL13_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL13_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL13_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL13_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL13_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL13_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL13_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL13_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL13_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL13_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL13_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL13_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL13_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL13_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL13_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL13_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL13_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL13_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL13_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL13_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL13_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL13_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL13_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL13_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL13_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL13. + */ +struct ALT_USB_DEV_DOEPCTL13_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL13. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL13_s ALT_USB_DEV_DOEPCTL13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL13 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL13_OFST 0x4a0 +/* The address of the ALT_USB_DEV_DOEPCTL13 register. */ +#define ALT_USB_DEV_DOEPCTL13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL13_OFST)) + +/* + * Register : Device OUT Endpoint 13 Interrupt Register - doepint13 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT13_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT13_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT13_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT13_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT13_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT13_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT13_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT13_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT13_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT13_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT13_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT13_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT13_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT13_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT13_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT13_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT13_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT13_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT13_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT13_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT13_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT13_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT13_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT13_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT13_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT13_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT13_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT13_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT13_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT13_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT13_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT13_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT13_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT13_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT13_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT13_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT13_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT13_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT13_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT13_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT13_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT13_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT13_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT13_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT13_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT13_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT13_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT13_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT13_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT13_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT13_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT13_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT13_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT13_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT13_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT13_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT13_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT13_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT13. + */ +struct ALT_USB_DEV_DOEPINT13_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT13_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT13. */ +typedef volatile struct ALT_USB_DEV_DOEPINT13_s ALT_USB_DEV_DOEPINT13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT13 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT13_OFST 0x4a8 +/* The address of the ALT_USB_DEV_DOEPINT13 register. */ +#define ALT_USB_DEV_DOEPINT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT13_OFST)) + +/* + * Register : Device OUT Endpoint 13 Transfer Size Register - doeptsiz13 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ13_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ13_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ13. + */ +struct ALT_USB_DEV_DOEPTSIZ13_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ13. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ13_s ALT_USB_DEV_DOEPTSIZ13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ13 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ13_OFST 0x4b0 +/* The address of the ALT_USB_DEV_DOEPTSIZ13 register. */ +#define ALT_USB_DEV_DOEPTSIZ13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ13_OFST)) + +/* + * Register : Device OUT Endpoint 13 DMA Address Register - doepdma13 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma13 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */ +#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */ +#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */ +#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value. */ +#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value. */ +#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA13. + */ +struct ALT_USB_DEV_DOEPDMA13_s +{ + uint32_t doepdma13 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA13. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA13_s ALT_USB_DEV_DOEPDMA13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA13 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA13_OFST 0x4b4 +/* The address of the ALT_USB_DEV_DOEPDMA13 register. */ +#define ALT_USB_DEV_DOEPDMA13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA13_OFST)) + +/* + * Register : Device OUT Endpoint 13 DMA Buffer Address Register - doepdmab13 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab13 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */ +#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */ +#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */ +#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value. */ +#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value. */ +#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB13. + */ +struct ALT_USB_DEV_DOEPDMAB13_s +{ + const uint32_t doepdmab13 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB13. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB13_s ALT_USB_DEV_DOEPDMAB13_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB13 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB13_OFST 0x4bc +/* The address of the ALT_USB_DEV_DOEPDMAB13 register. */ +#define ALT_USB_DEV_DOEPDMAB13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB13_OFST)) + +/* + * Register : Device Control OUT Endpoint 14 Control Register - doepctl14 + * + * Out Endpoint 14. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL14_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL14_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL14_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL14_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL14_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL14_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL14_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL14_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL14_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL14_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL14_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL14_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL14_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL14_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL14_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL14_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL14_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL14_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL14_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * + * 0: DATA0 + * + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL14_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL14_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL14_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL14_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL14_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL14_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL14_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL14_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL14_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL14_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL14_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL14_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL14_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL14_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL14_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL14_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL14_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL14_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL14_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL14_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL14_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL14_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL14_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL14_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL14_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL14_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL14_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL14_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL14_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL14_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL14_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL14_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL14_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL14_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL14_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL14_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL14_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL14_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL14_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL14_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL14_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL14_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL14_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL14_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL14_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL14_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL14_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL14_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL14_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL14_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL14_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL14_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL14_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL14_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL14_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL14_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL14_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL14_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL14_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL14_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL14_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL14_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL14_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL14_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL14_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL14_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL14_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL14_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL14_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL14_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL14_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL14_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL14_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL14_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL14_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL14_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL14_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL14_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL14_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL14_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL14_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL14_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL14_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL14_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL14_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL14_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL14_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL14_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL14_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL14_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL14_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL14_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL14_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL14_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL14_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL14_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL14_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL14_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL14_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL14_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL14_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL14_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL14_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL14_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL14_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL14_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL14_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL14. + */ +struct ALT_USB_DEV_DOEPCTL14_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL14. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL14_s ALT_USB_DEV_DOEPCTL14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL14 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL14_OFST 0x4c0 +/* The address of the ALT_USB_DEV_DOEPCTL14 register. */ +#define ALT_USB_DEV_DOEPCTL14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL14_OFST)) + +/* + * Register : Device OUT Endpoint 14 Interrupt Register - doepint14 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT14_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT14_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT14_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT14_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT14_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT14_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT14_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT14_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT14_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT14_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT14_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT14_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT14_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT14_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT14_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT14_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT14_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT14_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT14_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT14_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT14_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT14_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT14_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT14_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT14_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT14_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT14_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT14_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT14_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT14_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT14_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT14_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT14_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT14_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT14_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT14_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT14_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT14_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT14_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT14_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT14_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT14_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT14_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT14_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT14_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT14_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT14_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT14_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT14_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT14_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT14_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT14_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT14_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT14_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT14_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT14_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT14_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT14_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT14. + */ +struct ALT_USB_DEV_DOEPINT14_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT14_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT14. */ +typedef volatile struct ALT_USB_DEV_DOEPINT14_s ALT_USB_DEV_DOEPINT14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT14 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT14_OFST 0x4c8 +/* The address of the ALT_USB_DEV_DOEPINT14 register. */ +#define ALT_USB_DEV_DOEPINT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT14_OFST)) + +/* + * Register : Device OUT Endpoint 14 Transfer Size Register - doeptsiz14 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ14_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ14_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ14. + */ +struct ALT_USB_DEV_DOEPTSIZ14_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ14. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ14_s ALT_USB_DEV_DOEPTSIZ14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ14 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ14_OFST 0x4d0 +/* The address of the ALT_USB_DEV_DOEPTSIZ14 register. */ +#define ALT_USB_DEV_DOEPTSIZ14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ14_OFST)) + +/* + * Register : Device OUT Endpoint 14 DMA Address Register - doepdma14 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma14 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */ +#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */ +#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */ +#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value. */ +#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value. */ +#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA14. + */ +struct ALT_USB_DEV_DOEPDMA14_s +{ + uint32_t doepdma14 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA14. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA14_s ALT_USB_DEV_DOEPDMA14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA14 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA14_OFST 0x4d4 +/* The address of the ALT_USB_DEV_DOEPDMA14 register. */ +#define ALT_USB_DEV_DOEPDMA14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA14_OFST)) + +/* + * Register : Device OUT Endpoint 14 DMA Buffer Address Register - doepdmab14 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab14 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */ +#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */ +#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */ +#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value. */ +#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value. */ +#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB14. + */ +struct ALT_USB_DEV_DOEPDMAB14_s +{ + const uint32_t doepdmab14 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB14. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB14_s ALT_USB_DEV_DOEPDMAB14_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB14 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB14_OFST 0x4dc +/* The address of the ALT_USB_DEV_DOEPDMAB14 register. */ +#define ALT_USB_DEV_DOEPDMAB14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB14_OFST)) + +/* + * Register : Device Control OUT Endpoint 15 Control Register - doepctl15 + * + * Out Endpoint 15. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:-------------------- + * [10:0] | RW | 0x0 | Maximum Packet Size + * [14:11] | ??? | 0x0 | *UNDEFINED* + * [15] | RW | 0x0 | USB Active Endpoint + * [16] | R | 0x0 | Endpoint Data PID + * [17] | R | 0x0 | NAK Status + * [19:18] | RW | 0x0 | Endpoint Type + * [20] | RW | 0x0 | Snoop Mode + * [21] | R | 0x0 | STALL Handshake + * [25:22] | ??? | 0x0 | *UNDEFINED* + * [26] | W | 0x0 | Clear NAK + * [27] | W | 0x0 | Set NAK + * [28] | W | 0x0 | Set DATA0 PID + * [29] | W | 0x0 | Set DATA1 PID + * [30] | R | 0x0 | Endpoint Disable + * [31] | R | 0x0 | Endpoint Enable + * + */ +/* + * Field : Maximum Packet Size - mps + * + * Applies to IN and OUT endpoints. The application must program this field with + * the maximum packet size for the current logical endpoint. This value is in + * bytes. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL15_MPS_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL15_MPS_MSB 10 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL15_MPS_WIDTH 11 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL15_MPS_SET_MSK 0x000007ff +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_MPS register field value. */ +#define ALT_USB_DEV_DOEPCTL15_MPS_CLR_MSK 0xfffff800 +/* The reset value of the ALT_USB_DEV_DOEPCTL15_MPS register field. */ +#define ALT_USB_DEV_DOEPCTL15_MPS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_MPS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_MPS_GET(value) (((value) & 0x000007ff) >> 0) +/* Produces a ALT_USB_DEV_DOEPCTL15_MPS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_MPS_SET(value) (((value) << 0) & 0x000007ff) + +/* + * Field : USB Active Endpoint - usbactep + * + * Indicates whether this endpoint is active in the current configuration and + * interface. The core clears this bit for all endpoints (other than EP 0) after + * detecting a USB reset. After receiving the SetConfiguration and SetInterface + * commands, the application must program endpoint registers accordingly and set + * this bit. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL15_USBACTEP_E_DISD | 0x0 | Not Active + * ALT_USB_DEV_DOEPCTL15_USBACTEP_E_END | 0x1 | USB Active Endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_USBACTEP + * + * Not Active + */ +#define ALT_USB_DEV_DOEPCTL15_USBACTEP_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_USBACTEP + * + * USB Active Endpoint + */ +#define ALT_USB_DEV_DOEPCTL15_USBACTEP_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL15_USBACTEP_LSB 15 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL15_USBACTEP_MSB 15 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL15_USBACTEP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL15_USBACTEP_SET_MSK 0x00008000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_USBACTEP register field value. */ +#define ALT_USB_DEV_DOEPCTL15_USBACTEP_CLR_MSK 0xffff7fff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */ +#define ALT_USB_DEV_DOEPCTL15_USBACTEP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_USBACTEP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) +/* Produces a ALT_USB_DEV_DOEPCTL15_USBACTEP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_USBACTEP_SET(value) (((value) << 15) & 0x00008000) + +/* + * Field : Endpoint Data PID - dpid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the + * packet to be received or transmitted on this endpoint. The application must + * program the PID of the first packet to be received or transmitted on this + * endpoint, after the endpoint is activated. The applications use the SetD1PID and + * SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * + * 0: DATA0 + * + * 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- + * Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather + * DMA mode: + * + * Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame + * number in which the core transmits/receives isochronous data for this endpoint. + * The application must program the even/odd (micro) frame number in which it + * intends to transmit/receive isochronous data for this endpoint using the + * SetEvnFr and SetOddFr fields in this register. + * + * 0: Even (micro)frame + * + * 1: Odd (micro)frame + * + * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame + * number in which to send data is provided in the transmit descriptor structure. + * The frame in which data is received is updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPCTL15_DPID_E_INACT | 0x0 | Endpoint Data PID not active + * ALT_USB_DEV_DOEPCTL15_DPID_E_ACT | 0x1 | Endpoint Data PID active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_DPID + * + * Endpoint Data PID not active + */ +#define ALT_USB_DEV_DOEPCTL15_DPID_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_DPID + * + * Endpoint Data PID active + */ +#define ALT_USB_DEV_DOEPCTL15_DPID_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL15_DPID_LSB 16 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL15_DPID_MSB 16 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL15_DPID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL15_DPID_SET_MSK 0x00010000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_DPID register field value. */ +#define ALT_USB_DEV_DOEPCTL15_DPID_CLR_MSK 0xfffeffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_DPID register field. */ +#define ALT_USB_DEV_DOEPCTL15_DPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_DPID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_DPID_GET(value) (((value) & 0x00010000) >> 16) +/* Produces a ALT_USB_DEV_DOEPCTL15_DPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_DPID_SET(value) (((value) << 16) & 0x00010000) + +/* + * Field : NAK Status - naksts + * + * When either the application or the core sets this bit: + * + * * The core stops receiving any data on an OUT endpoint, even if there is space + * in the RxFIFO to accommodate the incoming packet. + * + * * for non-isochronous IN endpoints: The core stops transmitting any data on an + * IN endpoint, even if there data is available in the TxFIFO. + * + * * for isochronous IN endpoints: The core sends out a zero-length data packet, + * even if there data is available in the TxFIFO. + * + * Irrespective of this bit's setting, the core always responds to SETUP data + * packets with an ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------------------ + * ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes + * : | | based on the FIFO status + * ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this + * : | | endpoint + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_NAKSTS + * + * The core is transmitting non-NAK handshakes based on the FIFO status + */ +#define ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NONNAK 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_NAKSTS + * + * The core is transmitting NAK handshakes on this endpoint + */ +#define ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NAK 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL15_NAKSTS_LSB 17 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL15_NAKSTS_MSB 17 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL15_NAKSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL15_NAKSTS_SET_MSK 0x00020000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_NAKSTS register field value. */ +#define ALT_USB_DEV_DOEPCTL15_NAKSTS_CLR_MSK 0xfffdffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */ +#define ALT_USB_DEV_DOEPCTL15_NAKSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_NAKSTS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) +/* Produces a ALT_USB_DEV_DOEPCTL15_NAKSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_NAKSTS_SET(value) (((value) << 17) & 0x00020000) + +/* + * Field : Endpoint Type - eptype + * + * This is the transfer type supported by this logical endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL15_EPTYPE_E_CTL | 0x0 | Control + * ALT_USB_DEV_DOEPCTL15_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous + * ALT_USB_DEV_DOEPCTL15_EPTYPE_E_BULK | 0x2 | Bulk + * ALT_USB_DEV_DOEPCTL15_EPTYPE_E_INTERRUP | 0x3 | Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE + * + * Control + */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_CTL 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE + * + * Isochronous + */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_ISOCHRONOUS 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE + * + * Bulk + */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_BULK 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE + * + * Interrupt + */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_INTERRUP 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_LSB 18 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_MSB 19 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_SET_MSK 0x000c0000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPTYPE register field value. */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_CLR_MSK 0xfff3ffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_EPTYPE field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18) +/* Produces a ALT_USB_DEV_DOEPCTL15_EPTYPE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000) + +/* + * Field : Snoop Mode - snp + * + * Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. + * In Snoop mode, the core does not check the correctness of OUT packets before + * transferring them to application memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPCTL15_SNP_E_DIS | 0x0 | Disable Snoop Mode + * ALT_USB_DEV_DOEPCTL15_SNP_E_EN | 0x1 | Enable Snoop Mode + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNP + * + * Disable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL15_SNP_E_DIS 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNP + * + * Enable Snoop Mode + */ +#define ALT_USB_DEV_DOEPCTL15_SNP_E_EN 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL15_SNP_LSB 20 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL15_SNP_MSB 20 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL15_SNP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL15_SNP_SET_MSK 0x00100000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SNP register field value. */ +#define ALT_USB_DEV_DOEPCTL15_SNP_CLR_MSK 0xffefffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_SNP register field. */ +#define ALT_USB_DEV_DOEPCTL15_SNP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_SNP field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_SNP_GET(value) (((value) & 0x00100000) >> 20) +/* Produces a ALT_USB_DEV_DOEPCTL15_SNP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_SNP_SET(value) (((value) << 20) & 0x00100000) + +/* + * Field : STALL Handshake - stall + * + * Applies to non-control, non-isochronous IN and OUT endpoints only. The + * application sets this bit to stall all tokens from the USB host to this + * endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set + * along with this bit, the STALL bit takes priority. Only the application can + * clear this bit, never the core. Applies to control endpoints only. The + * application can only set this bit, and the core clears it, when a SETUP token is + * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global + * OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective + * of this bit's setting, the core always responds to SETUP data packets with an + * ACK handshake. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPCTL15_STALL_E_INACT | 0x0 | STALL All Tokens not active + * ALT_USB_DEV_DOEPCTL15_STALL_E_ACT | 0x1 | STALL All Tokens active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_STALL + * + * STALL All Tokens not active + */ +#define ALT_USB_DEV_DOEPCTL15_STALL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_STALL + * + * STALL All Tokens active + */ +#define ALT_USB_DEV_DOEPCTL15_STALL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL15_STALL_LSB 21 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL15_STALL_MSB 21 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL15_STALL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL15_STALL_SET_MSK 0x00200000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_STALL register field value. */ +#define ALT_USB_DEV_DOEPCTL15_STALL_CLR_MSK 0xffdfffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_STALL register field. */ +#define ALT_USB_DEV_DOEPCTL15_STALL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_STALL field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_STALL_GET(value) (((value) & 0x00200000) >> 21) +/* Produces a ALT_USB_DEV_DOEPCTL15_STALL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_STALL_SET(value) (((value) << 21) & 0x00200000) + +/* + * Field : Clear NAK - cnak + * + * A write to this bit clears the NAK bit for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------- + * ALT_USB_DEV_DOEPCTL15_CNAK_E_INACT | 0x0 | No Clear NAK + * ALT_USB_DEV_DOEPCTL15_CNAK_E_ACT | 0x1 | Clear NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_CNAK + * + * No Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL15_CNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_CNAK + * + * Clear NAK + */ +#define ALT_USB_DEV_DOEPCTL15_CNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL15_CNAK_LSB 26 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL15_CNAK_MSB 26 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL15_CNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL15_CNAK_SET_MSK 0x04000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_CNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL15_CNAK_CLR_MSK 0xfbffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */ +#define ALT_USB_DEV_DOEPCTL15_CNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_CNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_CNAK_GET(value) (((value) & 0x04000000) >> 26) +/* Produces a ALT_USB_DEV_DOEPCTL15_CNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_CNAK_SET(value) (((value) << 26) & 0x04000000) + +/* + * Field : Set NAK - snak + * + * A write to this bit sets the NAK bit for the endpoint. Using this bit, the + * application can control the transmission of NAK handshakes on an endpoint. The + * core can also Set this bit for an endpoint after a SETUP packet is received on + * that endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------|:------|:------------ + * ALT_USB_DEV_DOEPCTL15_SNAK_E_INACT | 0x0 | No Set NAK + * ALT_USB_DEV_DOEPCTL15_SNAK_E_ACT | 0x1 | Set NAK + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNAK + * + * No Set NAK + */ +#define ALT_USB_DEV_DOEPCTL15_SNAK_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNAK + * + * Set NAK + */ +#define ALT_USB_DEV_DOEPCTL15_SNAK_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL15_SNAK_LSB 27 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL15_SNAK_MSB 27 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL15_SNAK_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL15_SNAK_SET_MSK 0x08000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SNAK register field value. */ +#define ALT_USB_DEV_DOEPCTL15_SNAK_CLR_MSK 0xf7ffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */ +#define ALT_USB_DEV_DOEPCTL15_SNAK_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_SNAK field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_SNAK_GET(value) (((value) & 0x08000000) >> 27) +/* Produces a ALT_USB_DEV_DOEPCTL15_SNAK register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_SNAK_SET(value) (((value) << 27) & 0x08000000) + +/* + * Field : Set DATA0 PID - setd0pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA0. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In + * non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to + * isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA + * mode is enabled, this field is reserved. The frame number in which to send data + * is in the transmit descriptor structure. The frame in which to receive data is + * updated in receive descriptor structure. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------------------------ + * ALT_USB_DEV_DOEPCTL15_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID + * ALT_USB_DEV_DOEPCTL15_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0) + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD0PID + * + * Disables Set DATA0 PID + */ +#define ALT_USB_DEV_DOEPCTL15_SETD0PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD0PID + * + * Enables Endpoint Data PID to DATA0) + */ +#define ALT_USB_DEV_DOEPCTL15_SETD0PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL15_SETD0PID_LSB 28 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL15_SETD0PID_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL15_SETD0PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL15_SETD0PID_SET_MSK 0x10000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SETD0PID register field value. */ +#define ALT_USB_DEV_DOEPCTL15_SETD0PID_CLR_MSK 0xefffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */ +#define ALT_USB_DEV_DOEPCTL15_SETD0PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_SETD0PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) +/* Produces a ALT_USB_DEV_DOEPCTL15_SETD0PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_SETD0PID_SET(value) (((value) << 28) & 0x10000000) + +/* + * Field : Set DATA1 PID - setd1pid + * + * Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets + * the Endpoint Data PID (DPID) field in this register to DATA1. This field is + * applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. + * + * Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints + * only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to + * odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:----------------------- + * ALT_USB_DEV_DOEPCTL15_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID + * ALT_USB_DEV_DOEPCTL15_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD1PID + * + * Disables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL15_SETD1PID_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD1PID + * + * Enables Set DATA1 PID + */ +#define ALT_USB_DEV_DOEPCTL15_SETD1PID_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL15_SETD1PID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL15_SETD1PID_MSB 29 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL15_SETD1PID_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL15_SETD1PID_SET_MSK 0x20000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SETD1PID register field value. */ +#define ALT_USB_DEV_DOEPCTL15_SETD1PID_CLR_MSK 0xdfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */ +#define ALT_USB_DEV_DOEPCTL15_SETD1PID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_SETD1PID field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPCTL15_SETD1PID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_SETD1PID_SET(value) (((value) << 29) & 0x20000000) + +/* + * Field : Endpoint Disable - epdis + * + * Applies to IN and OUT endpoints. The application sets this bit to stop + * transmitting/receiving data on an endpoint, even before the transfer for that + * endpoint is complete. The application must wait for the Endpoint Disabled + * interrupt before treating the endpoint as disabled. The core clears this bit + * before setting the Endpoint Disabled interrupt. The application must set this + * bit only if Endpoint Enable is already set for this endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPCTL15_EPDIS_E_INACT | 0x0 | No Endpoint Disable + * ALT_USB_DEV_DOEPCTL15_EPDIS_E_ACT | 0x1 | Endpoint Disable + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPDIS + * + * No Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL15_EPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPDIS + * + * Endpoint Disable + */ +#define ALT_USB_DEV_DOEPCTL15_EPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPDIS_LSB 30 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPDIS_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL15_EPDIS_SET_MSK 0x40000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPDIS register field value. */ +#define ALT_USB_DEV_DOEPCTL15_EPDIS_CLR_MSK 0xbfffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_EPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_EPDIS_GET(value) (((value) & 0x40000000) >> 30) +/* Produces a ALT_USB_DEV_DOEPCTL15_EPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_EPDIS_SET(value) (((value) << 30) & 0x40000000) + +/* + * Field : Endpoint Enable - epena + * + * Applies to IN and OUT endpoints. + * + * * When Scatter/Gather DMA mode is enabled, + * + * * for IN endpoints this bit indicates that the descriptor structure and data + * buffer with data ready to transmit is setup. + * + * * for OUT endpoint it indicates that the descriptor structure and data buffer to + * receive data is setup. + * + * * When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA + * mode: + * + * * for IN endpoints, this bit indicates that data is ready to be transmitted on + * the endpoint. + * + * * for OUT endpoints, this bit indicates that the application has allocated the + * memory to start receiving data from the USB. + * + * * The core clears this bit before setting any of the following interrupts on + * this endpoint: + * + * * SETUP Phase Done + * + * * Endpoint Disabled + * + * * Transfer Completed + * + * for control endpoints in DMA mode, this bit must be set to be able to transfer + * SETUP data packets in memory. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:------------------------- + * ALT_USB_DEV_DOEPCTL15_EPENA_E_INACT | 0x0 | Endpoint Enable inactive + * ALT_USB_DEV_DOEPCTL15_EPENA_E_ACT | 0x1 | Endpoint Enable active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPENA + * + * Endpoint Enable inactive + */ +#define ALT_USB_DEV_DOEPCTL15_EPENA_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPENA + * + * Endpoint Enable active + */ +#define ALT_USB_DEV_DOEPCTL15_EPENA_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPENA_LSB 31 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPENA_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPENA_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL15_EPENA_SET_MSK 0x80000000 +/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPENA register field value. */ +#define ALT_USB_DEV_DOEPCTL15_EPENA_CLR_MSK 0x7fffffff +/* The reset value of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */ +#define ALT_USB_DEV_DOEPCTL15_EPENA_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPCTL15_EPENA field value from a register. */ +#define ALT_USB_DEV_DOEPCTL15_EPENA_GET(value) (((value) & 0x80000000) >> 31) +/* Produces a ALT_USB_DEV_DOEPCTL15_EPENA register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPCTL15_EPENA_SET(value) (((value) << 31) & 0x80000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPCTL15. + */ +struct ALT_USB_DEV_DOEPCTL15_s +{ + uint32_t mps : 11; /* Maximum Packet Size */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t usbactep : 1; /* USB Active Endpoint */ + const uint32_t dpid : 1; /* Endpoint Data PID */ + const uint32_t naksts : 1; /* NAK Status */ + uint32_t eptype : 2; /* Endpoint Type */ + uint32_t snp : 1; /* Snoop Mode */ + const uint32_t stall : 1; /* STALL Handshake */ + uint32_t : 4; /* *UNDEFINED* */ + uint32_t cnak : 1; /* Clear NAK */ + uint32_t snak : 1; /* Set NAK */ + uint32_t setd0pid : 1; /* Set DATA0 PID */ + uint32_t setd1pid : 1; /* Set DATA1 PID */ + const uint32_t epdis : 1; /* Endpoint Disable */ + const uint32_t epena : 1; /* Endpoint Enable */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPCTL15. */ +typedef volatile struct ALT_USB_DEV_DOEPCTL15_s ALT_USB_DEV_DOEPCTL15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPCTL15 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPCTL15_OFST 0x4e0 +/* The address of the ALT_USB_DEV_DOEPCTL15 register. */ +#define ALT_USB_DEV_DOEPCTL15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL15_OFST)) + +/* + * Register : Device OUT Endpoint 15 Interrupt Register - doepint15 + * + * This register indicates the status of an endpoint with respect to USB- and AHB- + * related events. The application must read this register when the OUT Endpoints + * Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register + * (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application + * can read this register, it must first read the Device All Endpoints Interrupt + * (DAINT) register to get the exact endpoint number for the Device Endpoint-n + * Interrupt register. The application must clear the appropriate bit in this + * register to clear the corresponding bits in the DAINT and GINTSTS registers. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------------------------------ + * [0] | R | 0x0 | Transfer Completed Interrupt + * [1] | R | 0x0 | Endpoint Disabled Interrupt + * [2] | R | 0x0 | ALT_USB_DEV_DOEPINT15_AHBERR + * [3] | R | 0x0 | SETUP Phase Done + * [4] | R | 0x0 | OUT Token Received When Endpoint Disabled + * [5] | R | 0x0 | Status Phase Received for Control Write + * [6] | R | 0x0 | Back-to-Back SETUP Packets Received + * [7] | ??? | 0x0 | *UNDEFINED* + * [8] | R | 0x0 | OUT Packet Error + * [9] | R | 0x0 | BNA (Buffer Not Available) Interrupt + * [10] | ??? | 0x0 | *UNDEFINED* + * [11] | R | 0x0 | Packet Drop Status + * [12] | R | 0x0 | BbleErr Interrupt + * [13] | R | 0x0 | NAK Interrupt + * [14] | R | 0x0 | NYET Interrupt + * [31:15] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Completed Interrupt - xfercompl + * + * Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled + * + * This field indicates that the requested data from the internal FIFO is moved to + * external system memory. This interrupt is generated only when the corresponding + * endpoint descriptor is closed, and the IOC bit for the corresponding descriptor + * is Set. + * + * When Scatter/Gather DMA mode is disabled, this field indicates that the + * programmed transfer is complete on the AHB as well as on the USB, for this + * endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_XFERCOMPL + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_XFERCOMPL + * + * Transfer Completed Interrupt + */ +#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_MSB 0 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value. */ +#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */ +#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_XFERCOMPL field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Endpoint Disabled Interrupt - epdisbld + * + * Applies to IN and OUT endpoints. This bit indicates that the endpoint is + * disabled per the application's request. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:---------------------------- + * ALT_USB_DEV_DOEPINT15_EPDISBLD_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT15_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_EPDISBLD + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT15_EPDISBLD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_EPDISBLD + * + * Endpoint Disabled Interrupt + */ +#define ALT_USB_DEV_DOEPINT15_EPDISBLD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT15_EPDISBLD_LSB 1 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT15_EPDISBLD_MSB 1 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT15_EPDISBLD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT15_EPDISBLD_SET_MSK 0x00000002 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_EPDISBLD register field value. */ +#define ALT_USB_DEV_DOEPINT15_EPDISBLD_CLR_MSK 0xfffffffd +/* The reset value of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */ +#define ALT_USB_DEV_DOEPINT15_EPDISBLD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_EPDISBLD field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1) +/* Produces a ALT_USB_DEV_DOEPINT15_EPDISBLD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_EPDISBLD_SET(value) (((value) << 1) & 0x00000002) + +/* + * Field : ahberr + * + * Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when + * there is an AHB error during an AHB read/write. The application can read the + * corresponding endpoint DMA address register to get the error address. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT15_AHBERR_E_INACT | 0x0 | No Interrupt + * ALT_USB_DEV_DOEPINT15_AHBERR_E_ACT | 0x1 | AHB Error interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_AHBERR + * + * No Interrupt + */ +#define ALT_USB_DEV_DOEPINT15_AHBERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_AHBERR + * + * AHB Error interrupt + */ +#define ALT_USB_DEV_DOEPINT15_AHBERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT15_AHBERR_LSB 2 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT15_AHBERR_MSB 2 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT15_AHBERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT15_AHBERR_SET_MSK 0x00000004 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_AHBERR register field value. */ +#define ALT_USB_DEV_DOEPINT15_AHBERR_CLR_MSK 0xfffffffb +/* The reset value of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */ +#define ALT_USB_DEV_DOEPINT15_AHBERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_AHBERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2) +/* Produces a ALT_USB_DEV_DOEPINT15_AHBERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004) + +/* + * Field : SETUP Phase Done - setup + * + * Applies to control OUT endpoints only. Indicates that the SETUP phase for the + * control endpoint is complete and no more back-to-back SETUP packets were + * received for the current control transfer. On this interrupt, the application + * can decode the received SETUP data packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT15_SETUP_E_INACT | 0x0 | No SETUP Phase Done + * ALT_USB_DEV_DOEPINT15_SETUP_E_ACT | 0x1 | SETUP Phase Done + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_SETUP + * + * No SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT15_SETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_SETUP + * + * SETUP Phase Done + */ +#define ALT_USB_DEV_DOEPINT15_SETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT15_SETUP_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT15_SETUP_MSB 3 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT15_SETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT15_SETUP_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_SETUP register field value. */ +#define ALT_USB_DEV_DOEPINT15_SETUP_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_DEV_DOEPINT15_SETUP register field. */ +#define ALT_USB_DEV_DOEPINT15_SETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_SETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_SETUP_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_DEV_DOEPINT15_SETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_SETUP_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : OUT Token Received When Endpoint Disabled - outtknepdis + * + * Applies only to control OUT endpoints. Indicates that an OUT token was received + * when the endpoint was not yet enabled. This interrupt is asserted on the + * endpoint for which the OUT token was received. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:--------------------------------------------- + * ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled + * ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS + * + * No OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS + * + * OUT Token Received When Endpoint Disabled + */ +#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_LSB 4 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_MSB 4 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_SET_MSK 0x00000010 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value. */ +#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_CLR_MSK 0xffffffef +/* The reset value of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */ +#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4) +/* Produces a ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010) + +/* + * Field : Status Phase Received for Control Write - stsphsercvd + * + * This interrupt is valid only for Control OUT endpoints and only in Scatter + * Gather DMA mode. This interrupt is generated only after the core has transferred + * all the data that the host has sent during the data phase of a control write + * transfer, to the system memory buffer. The interrupt indicates to the + * application that the host has switched from data phase to the status phase of a + * Control Write transfer. The application can use this interrupt to ACK or STALL + * the Status phase, after it has decoded the data phase. This is applicable only + * in Case of Scatter Gather DMA mode. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------------------------------- + * ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write + * ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_STSPHSERCVD + * + * No Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_STSPHSERCVD + * + * Status Phase Received for Control Write + */ +#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_LSB 5 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_MSB 5 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_SET_MSK 0x00000020 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value. */ +#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_CLR_MSK 0xffffffdf +/* The reset value of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */ +#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_STSPHSERCVD field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5) +/* Produces a ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020) + +/* + * Field : Back-to-Back SETUP Packets Received - back2backsetup + * + * Applies to Control OUT endpoints only. This bit indicates that the core has + * received more than three back-to-back SETUP packets for this particular + * endpoint. for information about handling this interrupt, + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------------|:------|:--------------------------------------- + * ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received + * ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP + * + * No Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP + * + * Back-to-Back SETUP Packets Received + */ +#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_MSB 6 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value. */ +#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */ +#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : OUT Packet Error - outpkterr + * + * Applies to OUT endpoints Only This interrupt is asserted when the core detects + * an overflow or a CRC error for non-Isochronous OUT packet. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------------- + * ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error + * ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTPKTERR + * + * No OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTPKTERR + * + * OUT Packet Error + */ +#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_LSB 8 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_MSB 8 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_SET_MSK 0x00000100 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value. */ +#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_CLR_MSK 0xfffffeff +/* The reset value of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */ +#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_OUTPKTERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8) +/* Produces a ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100) + +/* + * Field : BNA (Buffer Not Available) Interrupt - bnaintr + * + * This bit is valid only when Scatter/Gather DMA mode is This bit is valid only + * when Scatter/Gather DMA mode is enabled. The core generates this interrupt when + * the descriptor accessed is not ready for the Core to process, such as Host busy + * or DMA done + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT15_BNAINTR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT15_BNAINTR_E_ACT | 0x1 | BNA interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BNAINTR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT15_BNAINTR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BNAINTR + * + * BNA interrupt + */ +#define ALT_USB_DEV_DOEPINT15_BNAINTR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT15_BNAINTR_LSB 9 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT15_BNAINTR_MSB 9 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT15_BNAINTR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT15_BNAINTR_SET_MSK 0x00000200 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_BNAINTR register field value. */ +#define ALT_USB_DEV_DOEPINT15_BNAINTR_CLR_MSK 0xfffffdff +/* The reset value of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */ +#define ALT_USB_DEV_DOEPINT15_BNAINTR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_BNAINTR field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_BNAINTR_GET(value) (((value) & 0x00000200) >> 9) +/* Produces a ALT_USB_DEV_DOEPINT15_BNAINTR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_BNAINTR_SET(value) (((value) << 9) & 0x00000200) + +/* + * Field : Packet Drop Status - pktdrpsts + * + * This bit indicates to the application that an ISOC OUT packet has been dropped. + * This bit does not have an associated mask bit and does not generate an + * interrupt. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:----------------------------- + * ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_PKTDRPSTS + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_PKTDRPSTS + * + * Packet Drop Status interrupt + */ +#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_LSB 11 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_MSB 11 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_SET_MSK 0x00000800 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value. */ +#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_CLR_MSK 0xfffff7ff +/* The reset value of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */ +#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_PKTDRPSTS field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11) +/* Produces a ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800) + +/* + * Field : BbleErr Interrupt - bbleerr + * + * The core generates this interrupt when babble is received for the endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :--------------------------------------|:------|:------------------ + * ALT_USB_DEV_DOEPINT15_BBLEERR_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT15_BBLEERR_E_ACT | 0x1 | BbleErr interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BBLEERR + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT15_BBLEERR_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BBLEERR + * + * BbleErr interrupt + */ +#define ALT_USB_DEV_DOEPINT15_BBLEERR_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT15_BBLEERR_LSB 12 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT15_BBLEERR_MSB 12 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT15_BBLEERR_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT15_BBLEERR_SET_MSK 0x00001000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_BBLEERR register field value. */ +#define ALT_USB_DEV_DOEPINT15_BBLEERR_CLR_MSK 0xffffefff +/* The reset value of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */ +#define ALT_USB_DEV_DOEPINT15_BBLEERR_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_BBLEERR field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_BBLEERR_GET(value) (((value) & 0x00001000) >> 12) +/* Produces a ALT_USB_DEV_DOEPINT15_BBLEERR register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_BBLEERR_SET(value) (((value) << 12) & 0x00001000) + +/* + * Field : NAK Interrupt - nakintrpt + * + * The core generates this interrupt when a NAK is transmitted or received by the + * device. In case of isochronous IN endpoints the interrupt gets generated when a + * zero length packet is transmitted due to un-availability of data in the TXFifo. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:-------------- + * ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NAKINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NAKINTRPT + * + * NAK Interrupt + */ +#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_LSB 13 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_MSB 13 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_SET_MSK 0x00002000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_CLR_MSK 0xffffdfff +/* The reset value of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_NAKINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13) +/* Produces a ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000) + +/* + * Field : NYET Interrupt - nyetintrpt + * + * The core generates this interrupt when a NYET response is transmitted for a non + * isochronous OUT endpoint. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-----------------------------------------|:------|:--------------- + * ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_INACT | 0x0 | No interrupt + * ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NYETINTRPT + * + * No interrupt + */ +#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NYETINTRPT + * + * NYET Interrupt + */ +#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_LSB 14 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_MSB 14 +/* The width in bits of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_WIDTH 1 +/* The mask used to set the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_SET_MSK 0x00004000 +/* The mask used to clear the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value. */ +#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_CLR_MSK 0xffffbfff +/* The reset value of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */ +#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPINT15_NYETINTRPT field value from a register. */ +#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14) +/* Produces a ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPINT15. + */ +struct ALT_USB_DEV_DOEPINT15_s +{ + const uint32_t xfercompl : 1; /* Transfer Completed Interrupt */ + const uint32_t epdisbld : 1; /* Endpoint Disabled Interrupt */ + const uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT15_AHBERR */ + const uint32_t setup : 1; /* SETUP Phase Done */ + const uint32_t outtknepdis : 1; /* OUT Token Received When Endpoint Disabled */ + const uint32_t stsphsercvd : 1; /* Status Phase Received for Control Write */ + const uint32_t back2backsetup : 1; /* Back-to-Back SETUP Packets Received */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t outpkterr : 1; /* OUT Packet Error */ + const uint32_t bnaintr : 1; /* BNA (Buffer Not Available) Interrupt */ + uint32_t : 1; /* *UNDEFINED* */ + const uint32_t pktdrpsts : 1; /* Packet Drop Status */ + const uint32_t bbleerr : 1; /* BbleErr Interrupt */ + const uint32_t nakintrpt : 1; /* NAK Interrupt */ + const uint32_t nyetintrpt : 1; /* NYET Interrupt */ + uint32_t : 17; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPINT15. */ +typedef volatile struct ALT_USB_DEV_DOEPINT15_s ALT_USB_DEV_DOEPINT15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPINT15 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPINT15_OFST 0x4e8 +/* The address of the ALT_USB_DEV_DOEPINT15 register. */ +#define ALT_USB_DEV_DOEPINT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT15_OFST)) + +/* + * Register : Device OUT Endpoint 15 Transfer Size Register - doeptsiz15 + * + * The application must modify this register before enabling the endpoint. Once the + * endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control + * registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The + * application can only read this register once the core has cleared the Endpoint + * Enable bit. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :--------|:-------|:------|:------------------- + * [18:0] | RW | 0x0 | Transfer Size + * [28:19] | RW | 0x0 | Packet Count + * [30:29] | R | 0x0 | SETUP Packet Count + * [31] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Transfer Size - xfersize + * + * Indicates the transfer size in bytes for endpoint 0. The core interrupts the + * application only after it has exhausted the transfer size amount of data. The + * transfer size can be Set to the maximum packet size of the endpoint, to be + * interrupted at the end of each packet. The core decrements this field every time + * a packet from the external memory is written to the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_MSB 18 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_WIDTH 19 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_SET_MSK 0x0007ffff +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value. */ +#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_CLR_MSK 0xfff80000 +/* The reset value of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff) + +/* + * Field : Packet Count - pktcnt + * + * Indicates the total number of USB packets that constitute the Transfer Size + * amount of data for endpoint 0.This field is decremented every time a packet + * (maximum size or short packet) is read from the RxFIFO. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_LSB 19 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_MSB 28 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_WIDTH 10 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_SET_MSK 0x1ff80000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value. */ +#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_CLR_MSK 0xe007ffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ15_PKTCNT field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19) +/* Produces a ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000) + +/* + * Field : SETUP Packet Count - rxdpid + * + * Applies to isochronous OUT endpoints only.This is the data PID received in the + * last packet for this endpoint. Use datax. + * + * Applies to control OUT Endpoints only. Use packetx. This field specifies the + * number of back-to-back SETUP data packets the endpoint can receive. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :------------------------------------------|:------|:------------------- + * ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA0 | 0x0 | DATA0 + * ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet + * ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets + * ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID + * + * DATA0 + */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA0 0x0 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID + * + * DATA2 or 1 packet + */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA2PKT1 0x1 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID + * + * DATA1 or 2 packets + */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA1PKT2 0x2 +/* + * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID + * + * MDATA or 3 packets + */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_MDATAPKT3 0x3 + +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_LSB 29 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_MSB 30 +/* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_WIDTH 2 +/* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_SET_MSK 0x60000000 +/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value. */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_CLR_MSK 0x9fffffff +/* The reset value of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPTSIZ15_RXDPID field value from a register. */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_GET(value) (((value) & 0x60000000) >> 29) +/* Produces a ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_SET(value) (((value) << 29) & 0x60000000) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPTSIZ15. + */ +struct ALT_USB_DEV_DOEPTSIZ15_s +{ + uint32_t xfersize : 19; /* Transfer Size */ + uint32_t pktcnt : 10; /* Packet Count */ + const uint32_t rxdpid : 2; /* SETUP Packet Count */ + uint32_t : 1; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ15. */ +typedef volatile struct ALT_USB_DEV_DOEPTSIZ15_s ALT_USB_DEV_DOEPTSIZ15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPTSIZ15 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPTSIZ15_OFST 0x4f0 +/* The address of the ALT_USB_DEV_DOEPTSIZ15 register. */ +#define ALT_USB_DEV_DOEPTSIZ15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ15_OFST)) + +/* + * Register : Device OUT Endpoint 15 DMA Address Register - doepdma15 + * + * DMA OUT Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------ + * [31:0] | RW | Unknown | DMA Address + * + */ +/* + * Field : DMA Address - doepdma15 + * + * Holds the start address of the external memory for storing or fetching endpoint + * data. for control endpoints, this field stores control OUT data packets as well + * as SETUP transaction data packets. When more than three SETUP packets are + * received back-to-back, the SETUP data packet in the memory is overwritten. This + * register is incremented on every AHB transaction. The application can give only + * a DWORD-aligned address. + * + * When Scatter/Gather DMA mode is not enabled, the application programs the start + * address value in this field. + * + * When Scatter/Gather DMA mode is enabled, this field indicates the base pointer + * for the descriptor list. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */ +#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */ +#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */ +#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value. */ +#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value. */ +#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 field value from a register. */ +#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMA15. + */ +struct ALT_USB_DEV_DOEPDMA15_s +{ + uint32_t doepdma15 : 32; /* DMA Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMA15. */ +typedef volatile struct ALT_USB_DEV_DOEPDMA15_s ALT_USB_DEV_DOEPDMA15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMA15 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMA15_OFST 0x4f4 +/* The address of the ALT_USB_DEV_DOEPDMA15 register. */ +#define ALT_USB_DEV_DOEPDMA15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA15_OFST)) + +/* + * Register : Device OUT Endpoint 15 DMA Buffer Address Register - doepdmab15 + * + * DMA Buffer Address. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:--------|:------------------- + * [31:0] | R | Unknown | DMA Buffer Address + * + */ +/* + * Field : DMA Buffer Address - doepdmab15 + * + * Holds the current buffer address. This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is + * present only in Scatter/Gather DMA mode. + * + * Field Access Macros: + * + */ +/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */ +#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */ +#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_MSB 31 +/* The width in bits of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */ +#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_WIDTH 32 +/* The mask used to set the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value. */ +#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_SET_MSK 0xffffffff +/* The mask used to clear the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value. */ +#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_CLR_MSK 0x00000000 +/* The reset value of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field is UNKNOWN. */ +#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_RESET 0x0 +/* Extracts the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 field value from a register. */ +#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_GET(value) (((value) & 0xffffffff) >> 0) +/* Produces a ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value suitable for setting the register. */ +#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_SET(value) (((value) << 0) & 0xffffffff) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_DEV_DOEPDMAB15. + */ +struct ALT_USB_DEV_DOEPDMAB15_s +{ + const uint32_t doepdmab15 : 32; /* DMA Buffer Address */ +}; + +/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB15. */ +typedef volatile struct ALT_USB_DEV_DOEPDMAB15_s ALT_USB_DEV_DOEPDMAB15_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_DEV_DOEPDMAB15 register from the beginning of the component. */ +#define ALT_USB_DEV_DOEPDMAB15_OFST 0x4fc +/* The address of the ALT_USB_DEV_DOEPDMAB15 register. */ +#define ALT_USB_DEV_DOEPDMAB15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB15_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_USB_DEV. + */ +struct ALT_USB_DEV_s +{ + volatile ALT_USB_DEV_DCFG_t dcfg; /* ALT_USB_DEV_DCFG */ + volatile ALT_USB_DEV_DCTL_t dctl; /* ALT_USB_DEV_DCTL */ + volatile ALT_USB_DEV_DSTS_t dsts; /* ALT_USB_DEV_DSTS */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPMSK_t diepmsk; /* ALT_USB_DEV_DIEPMSK */ + volatile ALT_USB_DEV_DOEPMSK_t doepmsk; /* ALT_USB_DEV_DOEPMSK */ + volatile ALT_USB_DEV_DAINT_t daint; /* ALT_USB_DEV_DAINT */ + volatile ALT_USB_DEV_DAINTMSK_t daintmsk; /* ALT_USB_DEV_DAINTMSK */ + volatile uint32_t _pad_0x20_0x27[2]; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DVBUSDIS_t dvbusdis; /* ALT_USB_DEV_DVBUSDIS */ + volatile ALT_USB_DEV_DVBUSPULSE_t dvbuspulse; /* ALT_USB_DEV_DVBUSPULSE */ + volatile ALT_USB_DEV_DTHRCTL_t dthrctl; /* ALT_USB_DEV_DTHRCTL */ + volatile ALT_USB_DEV_DIEPEMPMSK_t diepempmsk; /* ALT_USB_DEV_DIEPEMPMSK */ + volatile uint32_t _pad_0x38_0xff[50]; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPCTL0_t diepctl0; /* ALT_USB_DEV_DIEPCTL0 */ + volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT0_t diepint0; /* ALT_USB_DEV_DIEPINT0 */ + volatile uint32_t _pad_0x10c_0x10f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ0_t dieptsiz0; /* ALT_USB_DEV_DIEPTSIZ0 */ + volatile ALT_USB_DEV_DIEPDMA0_t diepdma0; /* ALT_USB_DEV_DIEPDMA0 */ + volatile ALT_USB_DEV_DTXFSTS0_t dtxfsts0; /* ALT_USB_DEV_DTXFSTS0 */ + volatile ALT_USB_DEV_DIEPDMAB0_t diepdmab0; /* ALT_USB_DEV_DIEPDMAB0 */ + volatile ALT_USB_DEV_DIEPCTL1_t diepctl1; /* ALT_USB_DEV_DIEPCTL1 */ + volatile uint32_t _pad_0x124_0x127; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT1_t diepint1; /* ALT_USB_DEV_DIEPINT1 */ + volatile uint32_t _pad_0x12c_0x12f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ1_t dieptsiz1; /* ALT_USB_DEV_DIEPTSIZ1 */ + volatile ALT_USB_DEV_DIEPDMA1_t diepdma1; /* ALT_USB_DEV_DIEPDMA1 */ + volatile ALT_USB_DEV_DTXFSTS1_t dtxfsts1; /* ALT_USB_DEV_DTXFSTS1 */ + volatile ALT_USB_DEV_DIEPDMAB1_t diepdmab1; /* ALT_USB_DEV_DIEPDMAB1 */ + volatile ALT_USB_DEV_DIEPCTL2_t diepctl2; /* ALT_USB_DEV_DIEPCTL2 */ + volatile uint32_t _pad_0x144_0x147; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT2_t diepint2; /* ALT_USB_DEV_DIEPINT2 */ + volatile uint32_t _pad_0x14c_0x14f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ2_t dieptsiz2; /* ALT_USB_DEV_DIEPTSIZ2 */ + volatile ALT_USB_DEV_DIEPDMA2_t diepdma2; /* ALT_USB_DEV_DIEPDMA2 */ + volatile ALT_USB_DEV_DTXFSTS2_t DTXFSTS2; /* ALT_USB_DEV_DTXFSTS2 */ + volatile ALT_USB_DEV_DIEPDMAB2_t diepdmab2; /* ALT_USB_DEV_DIEPDMAB2 */ + volatile ALT_USB_DEV_DIEPCTL3_t diepctl3; /* ALT_USB_DEV_DIEPCTL3 */ + volatile uint32_t _pad_0x164_0x167; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT3_t diepint3; /* ALT_USB_DEV_DIEPINT3 */ + volatile uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ3_t dieptsiz3; /* ALT_USB_DEV_DIEPTSIZ3 */ + volatile ALT_USB_DEV_DIEPDMA3_t diepdma3; /* ALT_USB_DEV_DIEPDMA3 */ + volatile ALT_USB_DEV_DTXFSTS3_t dtxfsts3; /* ALT_USB_DEV_DTXFSTS3 */ + volatile ALT_USB_DEV_DIEPDMAB3_t diepdmab3; /* ALT_USB_DEV_DIEPDMAB3 */ + volatile ALT_USB_DEV_DIEPCTL4_t diepctl4; /* ALT_USB_DEV_DIEPCTL4 */ + volatile uint32_t _pad_0x184_0x187; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT4_t diepint4; /* ALT_USB_DEV_DIEPINT4 */ + volatile uint32_t _pad_0x18c_0x18f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ4_t dieptsiz4; /* ALT_USB_DEV_DIEPTSIZ4 */ + volatile ALT_USB_DEV_DIEPDMA4_t diepdma4; /* ALT_USB_DEV_DIEPDMA4 */ + volatile ALT_USB_DEV_DTXFSTS4_t dtxfsts4; /* ALT_USB_DEV_DTXFSTS4 */ + volatile ALT_USB_DEV_DIEPDMAB4_t diepdmab4; /* ALT_USB_DEV_DIEPDMAB4 */ + volatile ALT_USB_DEV_DIEPCTL5_t diepctl5; /* ALT_USB_DEV_DIEPCTL5 */ + volatile uint32_t _pad_0x1a4_0x1a7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT5_t diepint5; /* ALT_USB_DEV_DIEPINT5 */ + volatile uint32_t _pad_0x1ac_0x1af; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ5_t dieptsiz5; /* ALT_USB_DEV_DIEPTSIZ5 */ + volatile ALT_USB_DEV_DIEPDMA5_t diepdma5; /* ALT_USB_DEV_DIEPDMA5 */ + volatile ALT_USB_DEV_DTXFSTS5_t dtxfsts5; /* ALT_USB_DEV_DTXFSTS5 */ + volatile ALT_USB_DEV_DIEPDMAB5_t diepdmab5; /* ALT_USB_DEV_DIEPDMAB5 */ + volatile ALT_USB_DEV_DIEPCTL6_t diepctl6; /* ALT_USB_DEV_DIEPCTL6 */ + volatile uint32_t _pad_0x1c4_0x1c7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT6_t diepint6; /* ALT_USB_DEV_DIEPINT6 */ + volatile uint32_t _pad_0x1cc_0x1cf; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ6_t dieptsiz6; /* ALT_USB_DEV_DIEPTSIZ6 */ + volatile ALT_USB_DEV_DIEPDMA6_t diepdma6; /* ALT_USB_DEV_DIEPDMA6 */ + volatile ALT_USB_DEV_DTXFSTS6_t dtxfsts6; /* ALT_USB_DEV_DTXFSTS6 */ + volatile ALT_USB_DEV_DIEPDMAB6_t diepdmab6; /* ALT_USB_DEV_DIEPDMAB6 */ + volatile ALT_USB_DEV_DIEPCTL7_t diepctl7; /* ALT_USB_DEV_DIEPCTL7 */ + volatile uint32_t _pad_0x1e4_0x1e7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT7_t diepint7; /* ALT_USB_DEV_DIEPINT7 */ + volatile uint32_t _pad_0x1ec_0x1ef; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ7_t dieptsiz7; /* ALT_USB_DEV_DIEPTSIZ7 */ + volatile ALT_USB_DEV_DIEPDMA7_t diepdma7; /* ALT_USB_DEV_DIEPDMA7 */ + volatile ALT_USB_DEV_DTXFSTS7_t dtxfsts7; /* ALT_USB_DEV_DTXFSTS7 */ + volatile ALT_USB_DEV_DIEPDMAB7_t diepdmab7; /* ALT_USB_DEV_DIEPDMAB7 */ + volatile ALT_USB_DEV_DIEPCTL8_t diepctl8; /* ALT_USB_DEV_DIEPCTL8 */ + volatile uint32_t _pad_0x204_0x207; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT8_t diepint8; /* ALT_USB_DEV_DIEPINT8 */ + volatile uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ8_t dieptsiz8; /* ALT_USB_DEV_DIEPTSIZ8 */ + volatile ALT_USB_DEV_DIEPDMA8_t diepdma8; /* ALT_USB_DEV_DIEPDMA8 */ + volatile ALT_USB_DEV_DTXFSTS8_t dtxfsts8; /* ALT_USB_DEV_DTXFSTS8 */ + volatile ALT_USB_DEV_DIEPDMAB8_t diepdmab8; /* ALT_USB_DEV_DIEPDMAB8 */ + volatile ALT_USB_DEV_DIEPCTL9_t diepctl9; /* ALT_USB_DEV_DIEPCTL9 */ + volatile uint32_t _pad_0x224_0x227; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT9_t diepint9; /* ALT_USB_DEV_DIEPINT9 */ + volatile uint32_t _pad_0x22c_0x22f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ9_t dieptsiz9; /* ALT_USB_DEV_DIEPTSIZ9 */ + volatile ALT_USB_DEV_DIEPDMA9_t diepdma9; /* ALT_USB_DEV_DIEPDMA9 */ + volatile ALT_USB_DEV_DTXFSTS9_t dtxfsts9; /* ALT_USB_DEV_DTXFSTS9 */ + volatile ALT_USB_DEV_DIEPDMAB9_t diepdmab9; /* ALT_USB_DEV_DIEPDMAB9 */ + volatile ALT_USB_DEV_DIEPCTL10_t diepctl10; /* ALT_USB_DEV_DIEPCTL10 */ + volatile uint32_t _pad_0x244_0x247; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT10_t diepint10; /* ALT_USB_DEV_DIEPINT10 */ + volatile uint32_t _pad_0x24c_0x24f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ10_t dieptsiz10; /* ALT_USB_DEV_DIEPTSIZ10 */ + volatile ALT_USB_DEV_DIEPDMA10_t diepdma10; /* ALT_USB_DEV_DIEPDMA10 */ + volatile ALT_USB_DEV_DTXFSTS10_t dtxfsts10; /* ALT_USB_DEV_DTXFSTS10 */ + volatile ALT_USB_DEV_DIEPDMAB10_t diepdmab10; /* ALT_USB_DEV_DIEPDMAB10 */ + volatile ALT_USB_DEV_DIEPCTL11_t diepctl11; /* ALT_USB_DEV_DIEPCTL11 */ + volatile uint32_t _pad_0x264_0x267; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT11_t diepint11; /* ALT_USB_DEV_DIEPINT11 */ + volatile uint32_t _pad_0x26c_0x26f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ11_t dieptsiz11; /* ALT_USB_DEV_DIEPTSIZ11 */ + volatile ALT_USB_DEV_DIEPDMA11_t diepdma11; /* ALT_USB_DEV_DIEPDMA11 */ + volatile ALT_USB_DEV_DTXFSTS11_t dtxfsts11; /* ALT_USB_DEV_DTXFSTS11 */ + volatile ALT_USB_DEV_DIEPDMAB11_t diepdmab11; /* ALT_USB_DEV_DIEPDMAB11 */ + volatile ALT_USB_DEV_DIEPCTL12_t diepctl12; /* ALT_USB_DEV_DIEPCTL12 */ + volatile uint32_t _pad_0x284_0x287; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT12_t diepint12; /* ALT_USB_DEV_DIEPINT12 */ + volatile uint32_t _pad_0x28c_0x28f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ12_t dieptsiz12; /* ALT_USB_DEV_DIEPTSIZ12 */ + volatile ALT_USB_DEV_DIEPDMA12_t diepdma12; /* ALT_USB_DEV_DIEPDMA12 */ + volatile ALT_USB_DEV_DTXFSTS12_t dtxfsts12; /* ALT_USB_DEV_DTXFSTS12 */ + volatile ALT_USB_DEV_DIEPDMAB12_t diepdmab12; /* ALT_USB_DEV_DIEPDMAB12 */ + volatile ALT_USB_DEV_DIEPCTL13_t diepctl13; /* ALT_USB_DEV_DIEPCTL13 */ + volatile uint32_t _pad_0x2a4_0x2a7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT13_t diepint13; /* ALT_USB_DEV_DIEPINT13 */ + volatile uint32_t _pad_0x2ac_0x2af; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ13_t dieptsiz13; /* ALT_USB_DEV_DIEPTSIZ13 */ + volatile ALT_USB_DEV_DIEPDMA13_t diepdma13; /* ALT_USB_DEV_DIEPDMA13 */ + volatile ALT_USB_DEV_DTXFSTS13_t dtxfsts13; /* ALT_USB_DEV_DTXFSTS13 */ + volatile ALT_USB_DEV_DIEPDMAB13_t diepdmab13; /* ALT_USB_DEV_DIEPDMAB13 */ + volatile ALT_USB_DEV_DIEPCTL14_t diepctl14; /* ALT_USB_DEV_DIEPCTL14 */ + volatile uint32_t _pad_0x2c4_0x2c7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT14_t diepint14; /* ALT_USB_DEV_DIEPINT14 */ + volatile uint32_t _pad_0x2cc_0x2cf; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ14_t dieptsiz14; /* ALT_USB_DEV_DIEPTSIZ14 */ + volatile ALT_USB_DEV_DIEPDMA14_t diepdma14; /* ALT_USB_DEV_DIEPDMA14 */ + volatile ALT_USB_DEV_DTXFSTS14_t dtxfsts14; /* ALT_USB_DEV_DTXFSTS14 */ + volatile ALT_USB_DEV_DIEPDMAB14_t diepdmab14; /* ALT_USB_DEV_DIEPDMAB14 */ + volatile ALT_USB_DEV_DIEPCTL15_t diepctl15; /* ALT_USB_DEV_DIEPCTL15 */ + volatile uint32_t _pad_0x2e4_0x2e7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPINT15_t diepint15; /* ALT_USB_DEV_DIEPINT15 */ + volatile uint32_t _pad_0x2ec_0x2ef; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DIEPTSIZ15_t dieptsiz15; /* ALT_USB_DEV_DIEPTSIZ15 */ + volatile ALT_USB_DEV_DIEPDMA15_t diepdma15; /* ALT_USB_DEV_DIEPDMA15 */ + volatile ALT_USB_DEV_DTXFSTS15_t dtxfsts15; /* ALT_USB_DEV_DTXFSTS15 */ + volatile ALT_USB_DEV_DIEPDMAB15_t diepdmab15; /* ALT_USB_DEV_DIEPDMAB15 */ + volatile ALT_USB_DEV_DOEPCTL0_t doepctl0; /* ALT_USB_DEV_DOEPCTL0 */ + volatile uint32_t _pad_0x304_0x307; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT0_t doepint0; /* ALT_USB_DEV_DOEPINT0 */ + volatile uint32_t _pad_0x30c_0x30f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ0_t doeptsiz0; /* ALT_USB_DEV_DOEPTSIZ0 */ + volatile ALT_USB_DEV_DOEPDMA0_t doepdma0; /* ALT_USB_DEV_DOEPDMA0 */ + volatile uint32_t _pad_0x318_0x31b; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB0_t doepdmab0; /* ALT_USB_DEV_DOEPDMAB0 */ + volatile ALT_USB_DEV_DOEPCTL1_t doepctl1; /* ALT_USB_DEV_DOEPCTL1 */ + volatile uint32_t _pad_0x324_0x327; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT1_t doepint1; /* ALT_USB_DEV_DOEPINT1 */ + volatile uint32_t _pad_0x32c_0x32f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ1_t doeptsiz1; /* ALT_USB_DEV_DOEPTSIZ1 */ + volatile ALT_USB_DEV_DOEPDMA1_t doepdma1; /* ALT_USB_DEV_DOEPDMA1 */ + volatile uint32_t _pad_0x338_0x33b; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB1_t doepdmab1; /* ALT_USB_DEV_DOEPDMAB1 */ + volatile ALT_USB_DEV_DOEPCTL2_t DOEPCTL2; /* ALT_USB_DEV_DOEPCTL2 */ + volatile uint32_t _pad_0x344_0x347; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT2_t doepint2; /* ALT_USB_DEV_DOEPINT2 */ + volatile uint32_t _pad_0x34c_0x34f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ2_t doeptsiz2; /* ALT_USB_DEV_DOEPTSIZ2 */ + volatile ALT_USB_DEV_DOEPDMA2_t doepdma2; /* ALT_USB_DEV_DOEPDMA2 */ + volatile uint32_t _pad_0x358_0x35b; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB2_t doepdmab2; /* ALT_USB_DEV_DOEPDMAB2 */ + volatile ALT_USB_DEV_DOEPCTL3_t DOEPCTL3; /* ALT_USB_DEV_DOEPCTL3 */ + volatile uint32_t _pad_0x364_0x367; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT3_t doepint3; /* ALT_USB_DEV_DOEPINT3 */ + volatile uint32_t _pad_0x36c_0x36f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ3_t doeptsiz3; /* ALT_USB_DEV_DOEPTSIZ3 */ + volatile ALT_USB_DEV_DOEPDMA3_t doepdma3; /* ALT_USB_DEV_DOEPDMA3 */ + volatile uint32_t _pad_0x378_0x37b; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB3_t doepdmab3; /* ALT_USB_DEV_DOEPDMAB3 */ + volatile ALT_USB_DEV_DOEPCTL4_t doepctl4; /* ALT_USB_DEV_DOEPCTL4 */ + volatile uint32_t _pad_0x384_0x387; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT4_t Doepint4; /* ALT_USB_DEV_DOEPINT4 */ + volatile uint32_t _pad_0x38c_0x38f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ4_t doeptsiz4; /* ALT_USB_DEV_DOEPTSIZ4 */ + volatile ALT_USB_DEV_DOEPDMA4_t doepdma4; /* ALT_USB_DEV_DOEPDMA4 */ + volatile uint32_t _pad_0x398_0x39b; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB4_t doepdmab4; /* ALT_USB_DEV_DOEPDMAB4 */ + volatile ALT_USB_DEV_DOEPCTL5_t doepctl5; /* ALT_USB_DEV_DOEPCTL5 */ + volatile uint32_t _pad_0x3a4_0x3a7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT5_t doepint5; /* ALT_USB_DEV_DOEPINT5 */ + volatile uint32_t _pad_0x3ac_0x3af; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ5_t doeptsiz5; /* ALT_USB_DEV_DOEPTSIZ5 */ + volatile ALT_USB_DEV_DOEPDMA5_t doepdma5; /* ALT_USB_DEV_DOEPDMA5 */ + volatile uint32_t _pad_0x3b8_0x3bb; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB5_t doepdmab5; /* ALT_USB_DEV_DOEPDMAB5 */ + volatile ALT_USB_DEV_DOEPCTL6_t doepctl6; /* ALT_USB_DEV_DOEPCTL6 */ + volatile uint32_t _pad_0x3c4_0x3c7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT6_t doepint6; /* ALT_USB_DEV_DOEPINT6 */ + volatile uint32_t _pad_0x3cc_0x3cf; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ6_t doeptsiz6; /* ALT_USB_DEV_DOEPTSIZ6 */ + volatile ALT_USB_DEV_DOEPDMA6_t doepdma6; /* ALT_USB_DEV_DOEPDMA6 */ + volatile uint32_t _pad_0x3d8_0x3db; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB6_t doepdmab6; /* ALT_USB_DEV_DOEPDMAB6 */ + volatile ALT_USB_DEV_DOEPCTL7_t doepctl7; /* ALT_USB_DEV_DOEPCTL7 */ + volatile uint32_t _pad_0x3e4_0x3e7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT7_t doepint7; /* ALT_USB_DEV_DOEPINT7 */ + volatile uint32_t _pad_0x3ec_0x3ef; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ7_t doeptsiz7; /* ALT_USB_DEV_DOEPTSIZ7 */ + volatile ALT_USB_DEV_DOEPDMA7_t doepdma7; /* ALT_USB_DEV_DOEPDMA7 */ + volatile uint32_t _pad_0x3f8_0x3fb; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB7_t doepdmab7; /* ALT_USB_DEV_DOEPDMAB7 */ + volatile ALT_USB_DEV_DOEPCTL8_t doepctl8; /* ALT_USB_DEV_DOEPCTL8 */ + volatile uint32_t _pad_0x404_0x407; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT8_t doepint8; /* ALT_USB_DEV_DOEPINT8 */ + volatile uint32_t _pad_0x40c_0x40f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ8_t doeptsiz8; /* ALT_USB_DEV_DOEPTSIZ8 */ + volatile ALT_USB_DEV_DOEPDMA8_t doepdma8; /* ALT_USB_DEV_DOEPDMA8 */ + volatile uint32_t _pad_0x418_0x41b; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB8_t doepdmab8; /* ALT_USB_DEV_DOEPDMAB8 */ + volatile ALT_USB_DEV_DOEPCTL9_t doepctl9; /* ALT_USB_DEV_DOEPCTL9 */ + volatile uint32_t _pad_0x424_0x427; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT9_t doepint9; /* ALT_USB_DEV_DOEPINT9 */ + volatile uint32_t _pad_0x42c_0x42f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ9_t doeptsiz9; /* ALT_USB_DEV_DOEPTSIZ9 */ + volatile ALT_USB_DEV_DOEPDMA9_t doepdma9; /* ALT_USB_DEV_DOEPDMA9 */ + volatile uint32_t _pad_0x438_0x43b; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB9_t doepdmab9; /* ALT_USB_DEV_DOEPDMAB9 */ + volatile ALT_USB_DEV_DOEPCTL10_t doepctl10; /* ALT_USB_DEV_DOEPCTL10 */ + volatile uint32_t _pad_0x444_0x447; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT10_t doepint10; /* ALT_USB_DEV_DOEPINT10 */ + volatile uint32_t _pad_0x44c_0x44f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ10_t doeptsiz10; /* ALT_USB_DEV_DOEPTSIZ10 */ + volatile ALT_USB_DEV_DOEPDMA10_t doepdma10; /* ALT_USB_DEV_DOEPDMA10 */ + volatile uint32_t _pad_0x458_0x45b; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB10_t doepdmab10; /* ALT_USB_DEV_DOEPDMAB10 */ + volatile ALT_USB_DEV_DOEPCTL11_t doepctl11; /* ALT_USB_DEV_DOEPCTL11 */ + volatile uint32_t _pad_0x464_0x467; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT11_t doepint11; /* ALT_USB_DEV_DOEPINT11 */ + volatile uint32_t _pad_0x46c_0x46f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ11_t doeptsiz11; /* ALT_USB_DEV_DOEPTSIZ11 */ + volatile ALT_USB_DEV_DOEPDMA11_t doepdma11; /* ALT_USB_DEV_DOEPDMA11 */ + volatile uint32_t _pad_0x478_0x47b; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB11_t doepdmab11; /* ALT_USB_DEV_DOEPDMAB11 */ + volatile ALT_USB_DEV_DOEPCTL12_t doepctl12; /* ALT_USB_DEV_DOEPCTL12 */ + volatile uint32_t _pad_0x484_0x487; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT12_t doepint12; /* ALT_USB_DEV_DOEPINT12 */ + volatile uint32_t _pad_0x48c_0x48f; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ12_t doeptsiz12; /* ALT_USB_DEV_DOEPTSIZ12 */ + volatile ALT_USB_DEV_DOEPDMA12_t doepdma12; /* ALT_USB_DEV_DOEPDMA12 */ + volatile uint32_t _pad_0x498_0x49b; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB12_t doepdmab12; /* ALT_USB_DEV_DOEPDMAB12 */ + volatile ALT_USB_DEV_DOEPCTL13_t doepctl13; /* ALT_USB_DEV_DOEPCTL13 */ + volatile uint32_t _pad_0x4a4_0x4a7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT13_t doepint13; /* ALT_USB_DEV_DOEPINT13 */ + volatile uint32_t _pad_0x4ac_0x4af; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ13_t doeptsiz13; /* ALT_USB_DEV_DOEPTSIZ13 */ + volatile ALT_USB_DEV_DOEPDMA13_t doepdma13; /* ALT_USB_DEV_DOEPDMA13 */ + volatile uint32_t _pad_0x4b8_0x4bb; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB13_t doepdmab13; /* ALT_USB_DEV_DOEPDMAB13 */ + volatile ALT_USB_DEV_DOEPCTL14_t doepctl14; /* ALT_USB_DEV_DOEPCTL14 */ + volatile uint32_t _pad_0x4c4_0x4c7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT14_t doepint14; /* ALT_USB_DEV_DOEPINT14 */ + volatile uint32_t _pad_0x4cc_0x4cf; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ14_t doeptsiz14; /* ALT_USB_DEV_DOEPTSIZ14 */ + volatile ALT_USB_DEV_DOEPDMA14_t doepdma14; /* ALT_USB_DEV_DOEPDMA14 */ + volatile uint32_t _pad_0x4d8_0x4db; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB14_t doepdmab14; /* ALT_USB_DEV_DOEPDMAB14 */ + volatile ALT_USB_DEV_DOEPCTL15_t doepctl15; /* ALT_USB_DEV_DOEPCTL15 */ + volatile uint32_t _pad_0x4e4_0x4e7; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPINT15_t doepint15; /* ALT_USB_DEV_DOEPINT15 */ + volatile uint32_t _pad_0x4ec_0x4ef; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPTSIZ15_t doeptsiz15; /* ALT_USB_DEV_DOEPTSIZ15 */ + volatile ALT_USB_DEV_DOEPDMA15_t doepdma15; /* ALT_USB_DEV_DOEPDMA15 */ + volatile uint32_t _pad_0x4f8_0x4fb; /* *UNDEFINED* */ + volatile ALT_USB_DEV_DOEPDMAB15_t doepdmab15; /* ALT_USB_DEV_DOEPDMAB15 */ +}; + +/* The typedef declaration for register group ALT_USB_DEV. */ +typedef volatile struct ALT_USB_DEV_s ALT_USB_DEV_t; +/* The struct declaration for the raw register contents of register group ALT_USB_DEV. */ +struct ALT_USB_DEV_raw_s +{ + volatile uint32_t dcfg; /* ALT_USB_DEV_DCFG */ + volatile uint32_t dctl; /* ALT_USB_DEV_DCTL */ + volatile uint32_t dsts; /* ALT_USB_DEV_DSTS */ + volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ + volatile uint32_t diepmsk; /* ALT_USB_DEV_DIEPMSK */ + volatile uint32_t doepmsk; /* ALT_USB_DEV_DOEPMSK */ + volatile uint32_t daint; /* ALT_USB_DEV_DAINT */ + volatile uint32_t daintmsk; /* ALT_USB_DEV_DAINTMSK */ + volatile uint32_t _pad_0x20_0x27[2]; /* *UNDEFINED* */ + volatile uint32_t dvbusdis; /* ALT_USB_DEV_DVBUSDIS */ + volatile uint32_t dvbuspulse; /* ALT_USB_DEV_DVBUSPULSE */ + volatile uint32_t dthrctl; /* ALT_USB_DEV_DTHRCTL */ + volatile uint32_t diepempmsk; /* ALT_USB_DEV_DIEPEMPMSK */ + volatile uint32_t _pad_0x38_0xff[50]; /* *UNDEFINED* */ + volatile uint32_t diepctl0; /* ALT_USB_DEV_DIEPCTL0 */ + volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */ + volatile uint32_t diepint0; /* ALT_USB_DEV_DIEPINT0 */ + volatile uint32_t _pad_0x10c_0x10f; /* *UNDEFINED* */ + volatile uint32_t dieptsiz0; /* ALT_USB_DEV_DIEPTSIZ0 */ + volatile uint32_t diepdma0; /* ALT_USB_DEV_DIEPDMA0 */ + volatile uint32_t dtxfsts0; /* ALT_USB_DEV_DTXFSTS0 */ + volatile uint32_t diepdmab0; /* ALT_USB_DEV_DIEPDMAB0 */ + volatile uint32_t diepctl1; /* ALT_USB_DEV_DIEPCTL1 */ + volatile uint32_t _pad_0x124_0x127; /* *UNDEFINED* */ + volatile uint32_t diepint1; /* ALT_USB_DEV_DIEPINT1 */ + volatile uint32_t _pad_0x12c_0x12f; /* *UNDEFINED* */ + volatile uint32_t dieptsiz1; /* ALT_USB_DEV_DIEPTSIZ1 */ + volatile uint32_t diepdma1; /* ALT_USB_DEV_DIEPDMA1 */ + volatile uint32_t dtxfsts1; /* ALT_USB_DEV_DTXFSTS1 */ + volatile uint32_t diepdmab1; /* ALT_USB_DEV_DIEPDMAB1 */ + volatile uint32_t diepctl2; /* ALT_USB_DEV_DIEPCTL2 */ + volatile uint32_t _pad_0x144_0x147; /* *UNDEFINED* */ + volatile uint32_t diepint2; /* ALT_USB_DEV_DIEPINT2 */ + volatile uint32_t _pad_0x14c_0x14f; /* *UNDEFINED* */ + volatile uint32_t dieptsiz2; /* ALT_USB_DEV_DIEPTSIZ2 */ + volatile uint32_t diepdma2; /* ALT_USB_DEV_DIEPDMA2 */ + volatile uint32_t DTXFSTS2; /* ALT_USB_DEV_DTXFSTS2 */ + volatile uint32_t diepdmab2; /* ALT_USB_DEV_DIEPDMAB2 */ + volatile uint32_t diepctl3; /* ALT_USB_DEV_DIEPCTL3 */ + volatile uint32_t _pad_0x164_0x167; /* *UNDEFINED* */ + volatile uint32_t diepint3; /* ALT_USB_DEV_DIEPINT3 */ + volatile uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */ + volatile uint32_t dieptsiz3; /* ALT_USB_DEV_DIEPTSIZ3 */ + volatile uint32_t diepdma3; /* ALT_USB_DEV_DIEPDMA3 */ + volatile uint32_t dtxfsts3; /* ALT_USB_DEV_DTXFSTS3 */ + volatile uint32_t diepdmab3; /* ALT_USB_DEV_DIEPDMAB3 */ + volatile uint32_t diepctl4; /* ALT_USB_DEV_DIEPCTL4 */ + volatile uint32_t _pad_0x184_0x187; /* *UNDEFINED* */ + volatile uint32_t diepint4; /* ALT_USB_DEV_DIEPINT4 */ + volatile uint32_t _pad_0x18c_0x18f; /* *UNDEFINED* */ + volatile uint32_t dieptsiz4; /* ALT_USB_DEV_DIEPTSIZ4 */ + volatile uint32_t diepdma4; /* ALT_USB_DEV_DIEPDMA4 */ + volatile uint32_t dtxfsts4; /* ALT_USB_DEV_DTXFSTS4 */ + volatile uint32_t diepdmab4; /* ALT_USB_DEV_DIEPDMAB4 */ + volatile uint32_t diepctl5; /* ALT_USB_DEV_DIEPCTL5 */ + volatile uint32_t _pad_0x1a4_0x1a7; /* *UNDEFINED* */ + volatile uint32_t diepint5; /* ALT_USB_DEV_DIEPINT5 */ + volatile uint32_t _pad_0x1ac_0x1af; /* *UNDEFINED* */ + volatile uint32_t dieptsiz5; /* ALT_USB_DEV_DIEPTSIZ5 */ + volatile uint32_t diepdma5; /* ALT_USB_DEV_DIEPDMA5 */ + volatile uint32_t dtxfsts5; /* ALT_USB_DEV_DTXFSTS5 */ + volatile uint32_t diepdmab5; /* ALT_USB_DEV_DIEPDMAB5 */ + volatile uint32_t diepctl6; /* ALT_USB_DEV_DIEPCTL6 */ + volatile uint32_t _pad_0x1c4_0x1c7; /* *UNDEFINED* */ + volatile uint32_t diepint6; /* ALT_USB_DEV_DIEPINT6 */ + volatile uint32_t _pad_0x1cc_0x1cf; /* *UNDEFINED* */ + volatile uint32_t dieptsiz6; /* ALT_USB_DEV_DIEPTSIZ6 */ + volatile uint32_t diepdma6; /* ALT_USB_DEV_DIEPDMA6 */ + volatile uint32_t dtxfsts6; /* ALT_USB_DEV_DTXFSTS6 */ + volatile uint32_t diepdmab6; /* ALT_USB_DEV_DIEPDMAB6 */ + volatile uint32_t diepctl7; /* ALT_USB_DEV_DIEPCTL7 */ + volatile uint32_t _pad_0x1e4_0x1e7; /* *UNDEFINED* */ + volatile uint32_t diepint7; /* ALT_USB_DEV_DIEPINT7 */ + volatile uint32_t _pad_0x1ec_0x1ef; /* *UNDEFINED* */ + volatile uint32_t dieptsiz7; /* ALT_USB_DEV_DIEPTSIZ7 */ + volatile uint32_t diepdma7; /* ALT_USB_DEV_DIEPDMA7 */ + volatile uint32_t dtxfsts7; /* ALT_USB_DEV_DTXFSTS7 */ + volatile uint32_t diepdmab7; /* ALT_USB_DEV_DIEPDMAB7 */ + volatile uint32_t diepctl8; /* ALT_USB_DEV_DIEPCTL8 */ + volatile uint32_t _pad_0x204_0x207; /* *UNDEFINED* */ + volatile uint32_t diepint8; /* ALT_USB_DEV_DIEPINT8 */ + volatile uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */ + volatile uint32_t dieptsiz8; /* ALT_USB_DEV_DIEPTSIZ8 */ + volatile uint32_t diepdma8; /* ALT_USB_DEV_DIEPDMA8 */ + volatile uint32_t dtxfsts8; /* ALT_USB_DEV_DTXFSTS8 */ + volatile uint32_t diepdmab8; /* ALT_USB_DEV_DIEPDMAB8 */ + volatile uint32_t diepctl9; /* ALT_USB_DEV_DIEPCTL9 */ + volatile uint32_t _pad_0x224_0x227; /* *UNDEFINED* */ + volatile uint32_t diepint9; /* ALT_USB_DEV_DIEPINT9 */ + volatile uint32_t _pad_0x22c_0x22f; /* *UNDEFINED* */ + volatile uint32_t dieptsiz9; /* ALT_USB_DEV_DIEPTSIZ9 */ + volatile uint32_t diepdma9; /* ALT_USB_DEV_DIEPDMA9 */ + volatile uint32_t dtxfsts9; /* ALT_USB_DEV_DTXFSTS9 */ + volatile uint32_t diepdmab9; /* ALT_USB_DEV_DIEPDMAB9 */ + volatile uint32_t diepctl10; /* ALT_USB_DEV_DIEPCTL10 */ + volatile uint32_t _pad_0x244_0x247; /* *UNDEFINED* */ + volatile uint32_t diepint10; /* ALT_USB_DEV_DIEPINT10 */ + volatile uint32_t _pad_0x24c_0x24f; /* *UNDEFINED* */ + volatile uint32_t dieptsiz10; /* ALT_USB_DEV_DIEPTSIZ10 */ + volatile uint32_t diepdma10; /* ALT_USB_DEV_DIEPDMA10 */ + volatile uint32_t dtxfsts10; /* ALT_USB_DEV_DTXFSTS10 */ + volatile uint32_t diepdmab10; /* ALT_USB_DEV_DIEPDMAB10 */ + volatile uint32_t diepctl11; /* ALT_USB_DEV_DIEPCTL11 */ + volatile uint32_t _pad_0x264_0x267; /* *UNDEFINED* */ + volatile uint32_t diepint11; /* ALT_USB_DEV_DIEPINT11 */ + volatile uint32_t _pad_0x26c_0x26f; /* *UNDEFINED* */ + volatile uint32_t dieptsiz11; /* ALT_USB_DEV_DIEPTSIZ11 */ + volatile uint32_t diepdma11; /* ALT_USB_DEV_DIEPDMA11 */ + volatile uint32_t dtxfsts11; /* ALT_USB_DEV_DTXFSTS11 */ + volatile uint32_t diepdmab11; /* ALT_USB_DEV_DIEPDMAB11 */ + volatile uint32_t diepctl12; /* ALT_USB_DEV_DIEPCTL12 */ + volatile uint32_t _pad_0x284_0x287; /* *UNDEFINED* */ + volatile uint32_t diepint12; /* ALT_USB_DEV_DIEPINT12 */ + volatile uint32_t _pad_0x28c_0x28f; /* *UNDEFINED* */ + volatile uint32_t dieptsiz12; /* ALT_USB_DEV_DIEPTSIZ12 */ + volatile uint32_t diepdma12; /* ALT_USB_DEV_DIEPDMA12 */ + volatile uint32_t dtxfsts12; /* ALT_USB_DEV_DTXFSTS12 */ + volatile uint32_t diepdmab12; /* ALT_USB_DEV_DIEPDMAB12 */ + volatile uint32_t diepctl13; /* ALT_USB_DEV_DIEPCTL13 */ + volatile uint32_t _pad_0x2a4_0x2a7; /* *UNDEFINED* */ + volatile uint32_t diepint13; /* ALT_USB_DEV_DIEPINT13 */ + volatile uint32_t _pad_0x2ac_0x2af; /* *UNDEFINED* */ + volatile uint32_t dieptsiz13; /* ALT_USB_DEV_DIEPTSIZ13 */ + volatile uint32_t diepdma13; /* ALT_USB_DEV_DIEPDMA13 */ + volatile uint32_t dtxfsts13; /* ALT_USB_DEV_DTXFSTS13 */ + volatile uint32_t diepdmab13; /* ALT_USB_DEV_DIEPDMAB13 */ + volatile uint32_t diepctl14; /* ALT_USB_DEV_DIEPCTL14 */ + volatile uint32_t _pad_0x2c4_0x2c7; /* *UNDEFINED* */ + volatile uint32_t diepint14; /* ALT_USB_DEV_DIEPINT14 */ + volatile uint32_t _pad_0x2cc_0x2cf; /* *UNDEFINED* */ + volatile uint32_t dieptsiz14; /* ALT_USB_DEV_DIEPTSIZ14 */ + volatile uint32_t diepdma14; /* ALT_USB_DEV_DIEPDMA14 */ + volatile uint32_t dtxfsts14; /* ALT_USB_DEV_DTXFSTS14 */ + volatile uint32_t diepdmab14; /* ALT_USB_DEV_DIEPDMAB14 */ + volatile uint32_t diepctl15; /* ALT_USB_DEV_DIEPCTL15 */ + volatile uint32_t _pad_0x2e4_0x2e7; /* *UNDEFINED* */ + volatile uint32_t diepint15; /* ALT_USB_DEV_DIEPINT15 */ + volatile uint32_t _pad_0x2ec_0x2ef; /* *UNDEFINED* */ + volatile uint32_t dieptsiz15; /* ALT_USB_DEV_DIEPTSIZ15 */ + volatile uint32_t diepdma15; /* ALT_USB_DEV_DIEPDMA15 */ + volatile uint32_t dtxfsts15; /* ALT_USB_DEV_DTXFSTS15 */ + volatile uint32_t diepdmab15; /* ALT_USB_DEV_DIEPDMAB15 */ + volatile uint32_t doepctl0; /* ALT_USB_DEV_DOEPCTL0 */ + volatile uint32_t _pad_0x304_0x307; /* *UNDEFINED* */ + volatile uint32_t doepint0; /* ALT_USB_DEV_DOEPINT0 */ + volatile uint32_t _pad_0x30c_0x30f; /* *UNDEFINED* */ + volatile uint32_t doeptsiz0; /* ALT_USB_DEV_DOEPTSIZ0 */ + volatile uint32_t doepdma0; /* ALT_USB_DEV_DOEPDMA0 */ + volatile uint32_t _pad_0x318_0x31b; /* *UNDEFINED* */ + volatile uint32_t doepdmab0; /* ALT_USB_DEV_DOEPDMAB0 */ + volatile uint32_t doepctl1; /* ALT_USB_DEV_DOEPCTL1 */ + volatile uint32_t _pad_0x324_0x327; /* *UNDEFINED* */ + volatile uint32_t doepint1; /* ALT_USB_DEV_DOEPINT1 */ + volatile uint32_t _pad_0x32c_0x32f; /* *UNDEFINED* */ + volatile uint32_t doeptsiz1; /* ALT_USB_DEV_DOEPTSIZ1 */ + volatile uint32_t doepdma1; /* ALT_USB_DEV_DOEPDMA1 */ + volatile uint32_t _pad_0x338_0x33b; /* *UNDEFINED* */ + volatile uint32_t doepdmab1; /* ALT_USB_DEV_DOEPDMAB1 */ + volatile uint32_t DOEPCTL2; /* ALT_USB_DEV_DOEPCTL2 */ + volatile uint32_t _pad_0x344_0x347; /* *UNDEFINED* */ + volatile uint32_t doepint2; /* ALT_USB_DEV_DOEPINT2 */ + volatile uint32_t _pad_0x34c_0x34f; /* *UNDEFINED* */ + volatile uint32_t doeptsiz2; /* ALT_USB_DEV_DOEPTSIZ2 */ + volatile uint32_t doepdma2; /* ALT_USB_DEV_DOEPDMA2 */ + volatile uint32_t _pad_0x358_0x35b; /* *UNDEFINED* */ + volatile uint32_t doepdmab2; /* ALT_USB_DEV_DOEPDMAB2 */ + volatile uint32_t DOEPCTL3; /* ALT_USB_DEV_DOEPCTL3 */ + volatile uint32_t _pad_0x364_0x367; /* *UNDEFINED* */ + volatile uint32_t doepint3; /* ALT_USB_DEV_DOEPINT3 */ + volatile uint32_t _pad_0x36c_0x36f; /* *UNDEFINED* */ + volatile uint32_t doeptsiz3; /* ALT_USB_DEV_DOEPTSIZ3 */ + volatile uint32_t doepdma3; /* ALT_USB_DEV_DOEPDMA3 */ + volatile uint32_t _pad_0x378_0x37b; /* *UNDEFINED* */ + volatile uint32_t doepdmab3; /* ALT_USB_DEV_DOEPDMAB3 */ + volatile uint32_t doepctl4; /* ALT_USB_DEV_DOEPCTL4 */ + volatile uint32_t _pad_0x384_0x387; /* *UNDEFINED* */ + volatile uint32_t Doepint4; /* ALT_USB_DEV_DOEPINT4 */ + volatile uint32_t _pad_0x38c_0x38f; /* *UNDEFINED* */ + volatile uint32_t doeptsiz4; /* ALT_USB_DEV_DOEPTSIZ4 */ + volatile uint32_t doepdma4; /* ALT_USB_DEV_DOEPDMA4 */ + volatile uint32_t _pad_0x398_0x39b; /* *UNDEFINED* */ + volatile uint32_t doepdmab4; /* ALT_USB_DEV_DOEPDMAB4 */ + volatile uint32_t doepctl5; /* ALT_USB_DEV_DOEPCTL5 */ + volatile uint32_t _pad_0x3a4_0x3a7; /* *UNDEFINED* */ + volatile uint32_t doepint5; /* ALT_USB_DEV_DOEPINT5 */ + volatile uint32_t _pad_0x3ac_0x3af; /* *UNDEFINED* */ + volatile uint32_t doeptsiz5; /* ALT_USB_DEV_DOEPTSIZ5 */ + volatile uint32_t doepdma5; /* ALT_USB_DEV_DOEPDMA5 */ + volatile uint32_t _pad_0x3b8_0x3bb; /* *UNDEFINED* */ + volatile uint32_t doepdmab5; /* ALT_USB_DEV_DOEPDMAB5 */ + volatile uint32_t doepctl6; /* ALT_USB_DEV_DOEPCTL6 */ + volatile uint32_t _pad_0x3c4_0x3c7; /* *UNDEFINED* */ + volatile uint32_t doepint6; /* ALT_USB_DEV_DOEPINT6 */ + volatile uint32_t _pad_0x3cc_0x3cf; /* *UNDEFINED* */ + volatile uint32_t doeptsiz6; /* ALT_USB_DEV_DOEPTSIZ6 */ + volatile uint32_t doepdma6; /* ALT_USB_DEV_DOEPDMA6 */ + volatile uint32_t _pad_0x3d8_0x3db; /* *UNDEFINED* */ + volatile uint32_t doepdmab6; /* ALT_USB_DEV_DOEPDMAB6 */ + volatile uint32_t doepctl7; /* ALT_USB_DEV_DOEPCTL7 */ + volatile uint32_t _pad_0x3e4_0x3e7; /* *UNDEFINED* */ + volatile uint32_t doepint7; /* ALT_USB_DEV_DOEPINT7 */ + volatile uint32_t _pad_0x3ec_0x3ef; /* *UNDEFINED* */ + volatile uint32_t doeptsiz7; /* ALT_USB_DEV_DOEPTSIZ7 */ + volatile uint32_t doepdma7; /* ALT_USB_DEV_DOEPDMA7 */ + volatile uint32_t _pad_0x3f8_0x3fb; /* *UNDEFINED* */ + volatile uint32_t doepdmab7; /* ALT_USB_DEV_DOEPDMAB7 */ + volatile uint32_t doepctl8; /* ALT_USB_DEV_DOEPCTL8 */ + volatile uint32_t _pad_0x404_0x407; /* *UNDEFINED* */ + volatile uint32_t doepint8; /* ALT_USB_DEV_DOEPINT8 */ + volatile uint32_t _pad_0x40c_0x40f; /* *UNDEFINED* */ + volatile uint32_t doeptsiz8; /* ALT_USB_DEV_DOEPTSIZ8 */ + volatile uint32_t doepdma8; /* ALT_USB_DEV_DOEPDMA8 */ + volatile uint32_t _pad_0x418_0x41b; /* *UNDEFINED* */ + volatile uint32_t doepdmab8; /* ALT_USB_DEV_DOEPDMAB8 */ + volatile uint32_t doepctl9; /* ALT_USB_DEV_DOEPCTL9 */ + volatile uint32_t _pad_0x424_0x427; /* *UNDEFINED* */ + volatile uint32_t doepint9; /* ALT_USB_DEV_DOEPINT9 */ + volatile uint32_t _pad_0x42c_0x42f; /* *UNDEFINED* */ + volatile uint32_t doeptsiz9; /* ALT_USB_DEV_DOEPTSIZ9 */ + volatile uint32_t doepdma9; /* ALT_USB_DEV_DOEPDMA9 */ + volatile uint32_t _pad_0x438_0x43b; /* *UNDEFINED* */ + volatile uint32_t doepdmab9; /* ALT_USB_DEV_DOEPDMAB9 */ + volatile uint32_t doepctl10; /* ALT_USB_DEV_DOEPCTL10 */ + volatile uint32_t _pad_0x444_0x447; /* *UNDEFINED* */ + volatile uint32_t doepint10; /* ALT_USB_DEV_DOEPINT10 */ + volatile uint32_t _pad_0x44c_0x44f; /* *UNDEFINED* */ + volatile uint32_t doeptsiz10; /* ALT_USB_DEV_DOEPTSIZ10 */ + volatile uint32_t doepdma10; /* ALT_USB_DEV_DOEPDMA10 */ + volatile uint32_t _pad_0x458_0x45b; /* *UNDEFINED* */ + volatile uint32_t doepdmab10; /* ALT_USB_DEV_DOEPDMAB10 */ + volatile uint32_t doepctl11; /* ALT_USB_DEV_DOEPCTL11 */ + volatile uint32_t _pad_0x464_0x467; /* *UNDEFINED* */ + volatile uint32_t doepint11; /* ALT_USB_DEV_DOEPINT11 */ + volatile uint32_t _pad_0x46c_0x46f; /* *UNDEFINED* */ + volatile uint32_t doeptsiz11; /* ALT_USB_DEV_DOEPTSIZ11 */ + volatile uint32_t doepdma11; /* ALT_USB_DEV_DOEPDMA11 */ + volatile uint32_t _pad_0x478_0x47b; /* *UNDEFINED* */ + volatile uint32_t doepdmab11; /* ALT_USB_DEV_DOEPDMAB11 */ + volatile uint32_t doepctl12; /* ALT_USB_DEV_DOEPCTL12 */ + volatile uint32_t _pad_0x484_0x487; /* *UNDEFINED* */ + volatile uint32_t doepint12; /* ALT_USB_DEV_DOEPINT12 */ + volatile uint32_t _pad_0x48c_0x48f; /* *UNDEFINED* */ + volatile uint32_t doeptsiz12; /* ALT_USB_DEV_DOEPTSIZ12 */ + volatile uint32_t doepdma12; /* ALT_USB_DEV_DOEPDMA12 */ + volatile uint32_t _pad_0x498_0x49b; /* *UNDEFINED* */ + volatile uint32_t doepdmab12; /* ALT_USB_DEV_DOEPDMAB12 */ + volatile uint32_t doepctl13; /* ALT_USB_DEV_DOEPCTL13 */ + volatile uint32_t _pad_0x4a4_0x4a7; /* *UNDEFINED* */ + volatile uint32_t doepint13; /* ALT_USB_DEV_DOEPINT13 */ + volatile uint32_t _pad_0x4ac_0x4af; /* *UNDEFINED* */ + volatile uint32_t doeptsiz13; /* ALT_USB_DEV_DOEPTSIZ13 */ + volatile uint32_t doepdma13; /* ALT_USB_DEV_DOEPDMA13 */ + volatile uint32_t _pad_0x4b8_0x4bb; /* *UNDEFINED* */ + volatile uint32_t doepdmab13; /* ALT_USB_DEV_DOEPDMAB13 */ + volatile uint32_t doepctl14; /* ALT_USB_DEV_DOEPCTL14 */ + volatile uint32_t _pad_0x4c4_0x4c7; /* *UNDEFINED* */ + volatile uint32_t doepint14; /* ALT_USB_DEV_DOEPINT14 */ + volatile uint32_t _pad_0x4cc_0x4cf; /* *UNDEFINED* */ + volatile uint32_t doeptsiz14; /* ALT_USB_DEV_DOEPTSIZ14 */ + volatile uint32_t doepdma14; /* ALT_USB_DEV_DOEPDMA14 */ + volatile uint32_t _pad_0x4d8_0x4db; /* *UNDEFINED* */ + volatile uint32_t doepdmab14; /* ALT_USB_DEV_DOEPDMAB14 */ + volatile uint32_t doepctl15; /* ALT_USB_DEV_DOEPCTL15 */ + volatile uint32_t _pad_0x4e4_0x4e7; /* *UNDEFINED* */ + volatile uint32_t doepint15; /* ALT_USB_DEV_DOEPINT15 */ + volatile uint32_t _pad_0x4ec_0x4ef; /* *UNDEFINED* */ + volatile uint32_t doeptsiz15; /* ALT_USB_DEV_DOEPTSIZ15 */ + volatile uint32_t doepdma15; /* ALT_USB_DEV_DOEPDMA15 */ + volatile uint32_t _pad_0x4f8_0x4fb; /* *UNDEFINED* */ + volatile uint32_t doepdmab15; /* ALT_USB_DEV_DOEPDMAB15 */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_USB_DEV. */ +typedef volatile struct ALT_USB_DEV_raw_s ALT_USB_DEV_raw_t; +#endif /* __ASSEMBLY__ */ + + +/* + * Register Group : Power and Clock Gating Register - ALT_USB_PWRCLK + * Power and Clock Gating Register + * + * There is a single register for power and clock gating. It is available in both + * Host and Device modes. + * + */ +/* + * Register : Power and Clock Gating Control Register - pcgcctl + * + * This register is available in Host and Device modes. The application can use + * this register to control the core's power-down and clock gating features. + * Because the CSR module is turned off during power-down, this register is + * implemented in the AHB Slave BIU module. + * + * Register Layout + * + * Bits | Access | Reset | Description + * :-------|:-------|:------|:------------------------- + * [0] | RW | 0x0 | Stop Pclk + * [2:1] | ??? | 0x0 | *UNDEFINED* + * [3] | RW | 0x0 | Reset Power-Down Modules + * [5:4] | ??? | 0x0 | *UNDEFINED* + * [6] | R | 0x0 | PHY In Sleep + * [7] | R | 0x0 | Deep Sleep + * [31:8] | ??? | 0x0 | *UNDEFINED* + * + */ +/* + * Field : Stop Pclk - stoppclk + * + * The application sets this bit to stop the PHY clock (phy_clk) when the USB is + * suspended, the session is not valid, or the device is disconnected. The + * application clears this bit when the USB is resumed or a new session starts. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :---------------------------------------|:------|:------------------ + * ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD | 0x0 | Disable Stop Pclk + * ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END | 0x1 | Enable Stop Pclk + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_STOPPCLK + * + * Disable Stop Pclk + */ +#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD 0x0 +/* + * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_STOPPCLK + * + * Enable Stop Pclk + */ +#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_LSB 0 +/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_MSB 0 +/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_WIDTH 1 +/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value. */ +#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET_MSK 0x00000001 +/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value. */ +#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_CLR_MSK 0xfffffffe +/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_RESET 0x0 +/* Extracts the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK field value from a register. */ +#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_GET(value) (((value) & 0x00000001) >> 0) +/* Produces a ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value suitable for setting the register. */ +#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET(value) (((value) << 0) & 0x00000001) + +/* + * Field : Reset Power-Down Modules - rstpdwnmodule + * + * This bit is valid only in Partial Power-Down mode. Theapplication sets this bit + * when the power is turned off. The application clears this bit after the power is + * turned on and the PHY clock is up. The R/W of all core registers are possible + * only when this bit is set to 1b0. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:-------------------- + * ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON | 0x0 | Power is turned on + * ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF | 0x1 | Power is turned off + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE + * + * Power is turned on + */ +#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON 0x0 +/* + * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE + * + * Power is turned off + */ +#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_LSB 3 +/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_MSB 3 +/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_WIDTH 1 +/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value. */ +#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET_MSK 0x00000008 +/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value. */ +#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_CLR_MSK 0xfffffff7 +/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_RESET 0x0 +/* Extracts the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE field value from a register. */ +#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_GET(value) (((value) & 0x00000008) >> 3) +/* Produces a ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value suitable for setting the register. */ +#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET(value) (((value) << 3) & 0x00000008) + +/* + * Field : PHY In Sleep - physleep + * + * Indicates that the PHY is in Sleep State. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :----------------------------------------|:------|:---------------- + * ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT | 0x0 | Phy non-sleep + * ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT | 0x1 | Phy sleep state + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP + * + * Phy non-sleep + */ +#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP + * + * Phy sleep state + */ +#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_LSB 6 +/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_MSB 6 +/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_WIDTH 1 +/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value. */ +#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET_MSK 0x00000040 +/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value. */ +#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_CLR_MSK 0xffffffbf +/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_RESET 0x0 +/* Extracts the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP field value from a register. */ +#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_GET(value) (((value) & 0x00000040) >> 6) +/* Produces a ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value suitable for setting the register. */ +#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET(value) (((value) << 6) & 0x00000040) + +/* + * Field : Deep Sleep - l1suspended + * + * Indicates that the PHY is in deep sleep when in L1 state. + * + * Field Enumeration Values: + * + * Enum | Value | Description + * :-------------------------------------------|:------|:------------------ + * ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT | 0x0 | Non Deep Sleep + * ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT | 0x1 | Deep Sleep active + * + * Field Access Macros: + * + */ +/* + * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED + * + * Non Deep Sleep + */ +#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT 0x0 +/* + * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED + * + * Deep Sleep active + */ +#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT 0x1 + +/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_LSB 7 +/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_MSB 7 +/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_WIDTH 1 +/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value. */ +#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET_MSK 0x00000080 +/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value. */ +#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_CLR_MSK 0xffffff7f +/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */ +#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_RESET 0x0 +/* Extracts the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED field value from a register. */ +#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_GET(value) (((value) & 0x00000080) >> 7) +/* Produces a ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value suitable for setting the register. */ +#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET(value) (((value) << 7) & 0x00000080) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register ALT_USB_PWRCLK_PCGCCTL. + */ +struct ALT_USB_PWRCLK_PCGCCTL_s +{ + uint32_t stoppclk : 1; /* Stop Pclk */ + uint32_t : 2; /* *UNDEFINED* */ + uint32_t rstpdwnmodule : 1; /* Reset Power-Down Modules */ + uint32_t : 2; /* *UNDEFINED* */ + const uint32_t physleep : 1; /* PHY In Sleep */ + const uint32_t l1suspended : 1; /* Deep Sleep */ + uint32_t : 24; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register ALT_USB_PWRCLK_PCGCCTL. */ +typedef volatile struct ALT_USB_PWRCLK_PCGCCTL_s ALT_USB_PWRCLK_PCGCCTL_t; +#endif /* __ASSEMBLY__ */ + +/* The byte offset of the ALT_USB_PWRCLK_PCGCCTL register from the beginning of the component. */ +#define ALT_USB_PWRCLK_PCGCCTL_OFST 0x0 +/* The address of the ALT_USB_PWRCLK_PCGCCTL register. */ +#define ALT_USB_PWRCLK_PCGCCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_PWRCLK_PCGCCTL_OFST)) + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_USB_PWRCLK. + */ +struct ALT_USB_PWRCLK_s +{ + volatile ALT_USB_PWRCLK_PCGCCTL_t pcgcctl; /* ALT_USB_PWRCLK_PCGCCTL */ +}; + +/* The typedef declaration for register group ALT_USB_PWRCLK. */ +typedef volatile struct ALT_USB_PWRCLK_s ALT_USB_PWRCLK_t; +/* The struct declaration for the raw register contents of register group ALT_USB_PWRCLK. */ +struct ALT_USB_PWRCLK_raw_s +{ + volatile uint32_t pcgcctl; /* ALT_USB_PWRCLK_PCGCCTL */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_USB_PWRCLK. */ +typedef volatile struct ALT_USB_PWRCLK_raw_s ALT_USB_PWRCLK_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifndef __ASSEMBLY__ +/* + * WARNING: The C register and register group struct declarations are provided for + * convenience and illustrative purposes. They should, however, be used with + * caution as the C language standard provides no guarantees about the alignment or + * atomicity of device memory accesses. The recommended practice for writing + * hardware drivers is to use the SoCAL access macros and alt_read_word() and + * alt_write_word() functions. + * + * The struct declaration for register group ALT_USB. + */ +struct ALT_USB_s +{ + volatile ALT_USB_GLOB_t globgrp; /* ALT_USB_GLOB */ + volatile uint32_t _pad_0x140_0x3ff[176]; /* *UNDEFINED* */ + volatile ALT_USB_HOST_t hostgrp; /* ALT_USB_HOST */ + volatile uint32_t _pad_0x6fc_0x7ff[65]; /* *UNDEFINED* */ + volatile ALT_USB_DEV_t devgrp; /* ALT_USB_DEV */ + volatile uint32_t _pad_0xd00_0xdff[64]; /* *UNDEFINED* */ + volatile ALT_USB_PWRCLK_t pwrclkgrp; /* ALT_USB_PWRCLK */ + volatile uint32_t _pad_0xe04_0x40000[64639]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for register group ALT_USB. */ +typedef volatile struct ALT_USB_s ALT_USB_t; +/* The struct declaration for the raw register contents of register group ALT_USB. */ +struct ALT_USB_raw_s +{ + volatile ALT_USB_GLOB_raw_t globgrp; /* ALT_USB_GLOB */ + volatile uint32_t _pad_0x140_0x3ff[176]; /* *UNDEFINED* */ + volatile ALT_USB_HOST_raw_t hostgrp; /* ALT_USB_HOST */ + volatile uint32_t _pad_0x6fc_0x7ff[65]; /* *UNDEFINED* */ + volatile ALT_USB_DEV_raw_t devgrp; /* ALT_USB_DEV */ + volatile uint32_t _pad_0xd00_0xdff[64]; /* *UNDEFINED* */ + volatile ALT_USB_PWRCLK_raw_t pwrclkgrp; /* ALT_USB_PWRCLK */ + volatile uint32_t _pad_0xe04_0x40000[64639]; /* *UNDEFINED* */ +}; + +/* The typedef declaration for the raw register contents of register group ALT_USB. */ +typedef volatile struct ALT_USB_raw_s ALT_USB_raw_t; +#endif /* __ASSEMBLY__ */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_ALT_USB_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/hps.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/hps.h new file mode 100644 index 000000000..dee744e84 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/hps.h @@ -0,0 +1,8026 @@ +/******************************************************************************* +* * +* Copyright 2013 Altera Corporation. All Rights Reserved. * +* * +* Redistribution and use in source and binary forms, with or without * +* modification, are permitted provided that the following conditions are met: * +* * +* 1. Redistributions of source code must retain the above copyright notice, * +* this list of conditions and the following disclaimer. * +* * +* 2. Redistributions in binary form must reproduce the above copyright notice, * +* this list of conditions and the following disclaimer in the documentation * +* and/or other materials provided with the distribution. * +* * +* 3. The name of the author may not be used to endorse or promote products * +* derived from this software without specific prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * +* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * +* * +*******************************************************************************/ + +/* Altera - hps */ + +#ifndef __ALTERA_HPS_H__ +#define __ALTERA_HPS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#define ALT_HPS_ADDR 0 +/* + * Address Space : ALT_HPS + * + */ +/* + * Component Instance : stm + * + * Instance stm of component ALT_STM. + * + * + */ +/* The address of the ALT_STM_REG register for the ALT_STM instance. */ +#define ALT_STM_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_STM_ADDR) + ALT_STM_REG_OFST)) +/* The base address byte offset for the start of the ALT_STM component. */ +#define ALT_STM_OFST 0xfc000000 +/* The start address of the ALT_STM component. */ +#define ALT_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_STM_OFST)) +/* The lower bound address range of the ALT_STM component. */ +#define ALT_STM_LB_ADDR ALT_STM_ADDR +/* The upper bound address range of the ALT_STM component. */ +#define ALT_STM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_STM_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : dap + * + * Instance dap of component ALT_DAP. + * + * + */ +/* The address of the ALT_DAP_REG register for the ALT_DAP instance. */ +#define ALT_DAP_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DAP_ADDR) + ALT_DAP_REG_OFST)) +/* The base address byte offset for the start of the ALT_DAP component. */ +#define ALT_DAP_OFST 0xff000000 +/* The start address of the ALT_DAP component. */ +#define ALT_DAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DAP_OFST)) +/* The lower bound address range of the ALT_DAP component. */ +#define ALT_DAP_LB_ADDR ALT_DAP_ADDR +/* The upper bound address range of the ALT_DAP component. */ +#define ALT_DAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DAP_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : lwfpgaslaves + * + * Instance lwfpgaslaves of component ALT_LWFPGASLVS. + * + * + */ +/* The base address byte offset for the start of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_OFST 0xff200000 +/* The start address of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_LWFPGASLVS_OFST)) +/* The lower bound address range of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_LB_ADDR ALT_LWFPGASLVS_ADDR +/* The upper bound address range of the ALT_LWFPGASLVS component. */ +#define ALT_LWFPGASLVS_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWFPGASLVS_ADDR) + 0x200000) - 1)) + + +/* + * Component Instance : lwhps2fpgaregs + * + * Instance lwhps2fpgaregs of component ALT_LWH2F. + * + * + */ +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_LWH2F_ID. + * + * + */ +/* The address of the ALT_LWH2F_ID_PERIPH_ID_4 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_0 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_1 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_2 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_LWH2F_ID_PERIPH_ID_3 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_0 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_0_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_1 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_1_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_2 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_2_OFST)) +/* The address of the ALT_LWH2F_ID_COMP_ID_3 register for the ALT_LWH2F_ID instance. */ +#define ALT_LWH2F_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_OFST 0x1000 +/* The start address of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_ID_OFST)) +/* The lower bound address range of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_LB_ADDR ALT_LWH2F_ID_ADDR +/* The upper bound address range of the ALT_LWH2F_ID component. */ +#define ALT_LWH2F_ID_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : mastergrp + * + * Instance mastergrp of register group ALT_LWH2F_MST. + * + * + */ +/* + * Register Group Instance : mastergrp_fpga2hpsregs + * + * Instance mastergrp_fpga2hpsregs of register group ALT_LWH2F_MST_F2H. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_F2H instance. */ +#define ALT_LWH2F_MST_MST_F2H_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_F2H_ADDR) +/* The address of the ALT_LWH2F_AHB_CNTL register for the ALT_LWH2F_MST_MST_F2H instance. */ +#define ALT_LWH2F_MST_MST_F2H_AHB_CNTL_ADDR ALT_LWH2F_AHB_CNTL_ADDR(ALT_LWH2F_MST_MST_F2H_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_OFST 0x0 +/* The start address of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_F2H_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_LB_ADDR ALT_LWH2F_MST_MST_F2H_ADDR +/* The upper bound address range of the ALT_LWH2F_MST_MST_F2H component. */ +#define ALT_LWH2F_MST_MST_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_F2H_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_hps2fpgaregs + * + * Instance mastergrp_hps2fpgaregs of register group ALT_LWH2F_MST_H2F. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_H2F instance. */ +#define ALT_LWH2F_MST_MST_H2F_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_H2F_ADDR) +/* The address of the ALT_LWH2F_AHB_CNTL register for the ALT_LWH2F_MST_MST_H2F instance. */ +#define ALT_LWH2F_MST_MST_H2F_AHB_CNTL_ADDR ALT_LWH2F_AHB_CNTL_ADDR(ALT_LWH2F_MST_MST_H2F_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_OFST 0x1000 +/* The start address of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_H2F_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_LB_ADDR ALT_LWH2F_MST_MST_H2F_ADDR +/* The upper bound address range of the ALT_LWH2F_MST_MST_H2F component. */ +#define ALT_LWH2F_MST_MST_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_H2F_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_b32 + * + * Instance mastergrp_b32 of register group ALT_LWH2F_MST_B32. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_B32 instance. */ +#define ALT_LWH2F_MST_MST_B32_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) +/* The address of the ALT_LWH2F_WR_TIDEMARK register for the ALT_LWH2F_MST_MST_B32 instance. */ +#define ALT_LWH2F_MST_MST_B32_WR_TIDEMARK_ADDR ALT_LWH2F_WR_TIDEMARK_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) +/* The address of the ALT_LWH2F_FN_MOD register for the ALT_LWH2F_MST_MST_B32 instance. */ +#define ALT_LWH2F_MST_MST_B32_FN_MOD_ADDR ALT_LWH2F_FN_MOD_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_OFST 0x3000 +/* The start address of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_B32_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_LB_ADDR ALT_LWH2F_MST_MST_B32_ADDR +/* The upper bound address range of the ALT_LWH2F_MST_MST_B32 component. */ +#define ALT_LWH2F_MST_MST_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_B32_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_OFST 0x2000 +/* The start address of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_MST_OFST)) +/* The lower bound address range of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_LB_ADDR ALT_LWH2F_MST_ADDR +/* The upper bound address range of the ALT_LWH2F_MST component. */ +#define ALT_LWH2F_MST_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + 0x310c) - 1)) + + +/* + * Register Group Instance : slavegrp + * + * Instance slavegrp of register group ALT_LWH2F_SLV. + * + * + */ +/* + * Register Group Instance : slavegrp_b32 + * + * Instance slavegrp_b32 of register group ALT_LWH2F_SLV_B32. + * + * + */ +/* The address of the ALT_LWH2F_FN_MOD register for the ALT_LWH2F_SLV_SLV_B32 instance. */ +#define ALT_LWH2F_SLV_SLV_B32_FN_MOD_ADDR ALT_LWH2F_FN_MOD_ADDR(ALT_LWH2F_SLV_SLV_B32_ADDR) +/* The base address byte offset for the start of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_OFST 0x3000 +/* The start address of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_SLV_ADDR) + ALT_LWH2F_SLV_SLV_B32_OFST)) +/* The lower bound address range of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_LB_ADDR ALT_LWH2F_SLV_SLV_B32_ADDR +/* The upper bound address range of the ALT_LWH2F_SLV_SLV_B32 component. */ +#define ALT_LWH2F_SLV_SLV_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_SLV_SLV_B32_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_OFST 0x42000 +/* The start address of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_SLV_OFST)) +/* The lower bound address range of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_LB_ADDR ALT_LWH2F_SLV_ADDR +/* The upper bound address range of the ALT_LWH2F_SLV component. */ +#define ALT_LWH2F_SLV_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_SLV_ADDR) + 0x310c) - 1)) + + +/* The base address byte offset for the start of the ALT_LWH2F component. */ +#define ALT_LWH2F_OFST 0xff400000 +/* The start address of the ALT_LWH2F component. */ +#define ALT_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_LWH2F_OFST)) +/* The lower bound address range of the ALT_LWH2F component. */ +#define ALT_LWH2F_LB_ADDR ALT_LWH2F_ADDR +/* The upper bound address range of the ALT_LWH2F component. */ +#define ALT_LWH2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_ADDR) + 0x80000) - 1)) + + +/* + * Component Instance : hps2fpgaregs + * + * Instance hps2fpgaregs of component ALT_H2F. + * + * + */ +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_H2F_IDGRP. + * + * + */ +/* The address of the ALT_H2F_ID_PERIPH_ID_4 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_0 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_1 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_2 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_H2F_ID_PERIPH_ID_3 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_0 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_0_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_1 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_1_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_2 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_2_OFST)) +/* The address of the ALT_H2F_ID_COMP_ID_3 register for the ALT_H2F_IDGRP instance. */ +#define ALT_H2F_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_OFST 0x1000 +/* The start address of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_ADDR) + ALT_H2F_IDGRP_OFST)) +/* The lower bound address range of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_LB_ADDR ALT_H2F_IDGRP_ADDR +/* The upper bound address range of the ALT_H2F_IDGRP component. */ +#define ALT_H2F_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : mastergrp + * + * Instance mastergrp of register group ALT_H2F_MSTGRP. + * + * + */ +/* + * Register Group Instance : mastergrp_b32 + * + * Instance mastergrp_b32 of register group ALT_H2F_MST_B32. + * + * + */ +/* The address of the ALT_H2F_FN_MOD2 register for the ALT_H2F_MST_MST_B32 instance. */ +#define ALT_H2F_MST_MST_B32_FN_MOD2_ADDR ALT_H2F_FN_MOD2_ADDR(ALT_H2F_MST_MST_B32_ADDR) +/* The address of the ALT_H2F_FN_MOD register for the ALT_H2F_MST_MST_B32 instance. */ +#define ALT_H2F_MST_MST_B32_FN_MOD_ADDR ALT_H2F_FN_MOD_ADDR(ALT_H2F_MST_MST_B32_ADDR) +/* The base address byte offset for the start of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_OFST 0x0 +/* The start address of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + ALT_H2F_MST_MST_B32_OFST)) +/* The lower bound address range of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_LB_ADDR ALT_H2F_MST_MST_B32_ADDR +/* The upper bound address range of the ALT_H2F_MST_MST_B32 component. */ +#define ALT_H2F_MST_MST_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MST_MST_B32_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_b128 + * + * Instance mastergrp_b128 of register group ALT_H2F_MST_B128. + * + * + */ +/* The address of the ALT_H2F_FN_MOD2 register for the ALT_H2F_MST_MST_B128 instance. */ +#define ALT_H2F_MST_MST_B128_FN_MOD2_ADDR ALT_H2F_FN_MOD2_ADDR(ALT_H2F_MST_MST_B128_ADDR) +/* The address of the ALT_H2F_FN_MOD register for the ALT_H2F_MST_MST_B128 instance. */ +#define ALT_H2F_MST_MST_B128_FN_MOD_ADDR ALT_H2F_FN_MOD_ADDR(ALT_H2F_MST_MST_B128_ADDR) +/* The base address byte offset for the start of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_OFST 0x2000 +/* The start address of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + ALT_H2F_MST_MST_B128_OFST)) +/* The lower bound address range of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_LB_ADDR ALT_H2F_MST_MST_B128_ADDR +/* The upper bound address range of the ALT_H2F_MST_MST_B128 component. */ +#define ALT_H2F_MST_MST_B128_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MST_MST_B128_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_OFST 0x2000 +/* The start address of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_ADDR) + ALT_H2F_MSTGRP_OFST)) +/* The lower bound address range of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_LB_ADDR ALT_H2F_MSTGRP_ADDR +/* The upper bound address range of the ALT_H2F_MSTGRP component. */ +#define ALT_H2F_MSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + 0x210c) - 1)) + + +/* The base address byte offset for the start of the ALT_H2F component. */ +#define ALT_H2F_OFST 0xff500000 +/* The start address of the ALT_H2F component. */ +#define ALT_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_H2F_OFST)) +/* The lower bound address range of the ALT_H2F component. */ +#define ALT_H2F_LB_ADDR ALT_H2F_ADDR +/* The upper bound address range of the ALT_H2F component. */ +#define ALT_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_ADDR) + 0x8000) - 1)) + + +/* + * Component Instance : fpga2hpsregs + * + * Instance fpga2hpsregs of component ALT_F2H. + * + * + */ +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_F2H_IDGRP. + * + * + */ +/* The address of the ALT_F2H_ID_PERIPH_ID_4 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_0 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_1 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_2 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_F2H_ID_PERIPH_ID_3 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_0 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_0_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_1 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_1_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_2 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_2_OFST)) +/* The address of the ALT_F2H_ID_COMP_ID_3 register for the ALT_F2H_IDGRP instance. */ +#define ALT_F2H_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_OFST 0x1000 +/* The start address of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_ADDR) + ALT_F2H_IDGRP_OFST)) +/* The lower bound address range of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_LB_ADDR ALT_F2H_IDGRP_ADDR +/* The upper bound address range of the ALT_F2H_IDGRP component. */ +#define ALT_F2H_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : slavegrp + * + * Instance slavegrp of register group ALT_F2H_SLVGRP. + * + * + */ +/* + * Register Group Instance : slavegrp_b32 + * + * Instance slavegrp_b32 of register group ALT_F2H_SLV_B32. + * + * + */ +/* The address of the ALT_F2H_FN_MOD2 register for the ALT_F2H_SLV_SLV_B32 instance. */ +#define ALT_F2H_SLV_SLV_B32_FN_MOD2_ADDR ALT_F2H_FN_MOD2_ADDR(ALT_F2H_SLV_SLV_B32_ADDR) +/* The address of the ALT_F2H_FN_MOD register for the ALT_F2H_SLV_SLV_B32 instance. */ +#define ALT_F2H_SLV_SLV_B32_FN_MOD_ADDR ALT_F2H_FN_MOD_ADDR(ALT_F2H_SLV_SLV_B32_ADDR) +/* The base address byte offset for the start of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_OFST 0x0 +/* The start address of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + ALT_F2H_SLV_SLV_B32_OFST)) +/* The lower bound address range of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_LB_ADDR ALT_F2H_SLV_SLV_B32_ADDR +/* The upper bound address range of the ALT_F2H_SLV_SLV_B32 component. */ +#define ALT_F2H_SLV_SLV_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLV_SLV_B32_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_b128 + * + * Instance slavegrp_b128 of register group ALT_F2H_SLV_B128. + * + * + */ +/* The address of the ALT_F2H_FN_MOD2 register for the ALT_F2H_SLV_SLV_B128 instance. */ +#define ALT_F2H_SLV_SLV_B128_FN_MOD2_ADDR ALT_F2H_FN_MOD2_ADDR(ALT_F2H_SLV_SLV_B128_ADDR) +/* The address of the ALT_F2H_FN_MOD register for the ALT_F2H_SLV_SLV_B128 instance. */ +#define ALT_F2H_SLV_SLV_B128_FN_MOD_ADDR ALT_F2H_FN_MOD_ADDR(ALT_F2H_SLV_SLV_B128_ADDR) +/* The base address byte offset for the start of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_OFST 0x2000 +/* The start address of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + ALT_F2H_SLV_SLV_B128_OFST)) +/* The lower bound address range of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_LB_ADDR ALT_F2H_SLV_SLV_B128_ADDR +/* The upper bound address range of the ALT_F2H_SLV_SLV_B128 component. */ +#define ALT_F2H_SLV_SLV_B128_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLV_SLV_B128_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_OFST 0x42000 +/* The start address of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_ADDR) + ALT_F2H_SLVGRP_OFST)) +/* The lower bound address range of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_LB_ADDR ALT_F2H_SLVGRP_ADDR +/* The upper bound address range of the ALT_F2H_SLVGRP component. */ +#define ALT_F2H_SLVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + 0x210c) - 1)) + + +/* The base address byte offset for the start of the ALT_F2H component. */ +#define ALT_F2H_OFST 0xff600000 +/* The start address of the ALT_F2H component. */ +#define ALT_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_F2H_OFST)) +/* The lower bound address range of the ALT_F2H component. */ +#define ALT_F2H_LB_ADDR ALT_F2H_ADDR +/* The upper bound address range of the ALT_F2H component. */ +#define ALT_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_ADDR) + 0x80000) - 1)) + + +/* + * Component Instance : emac0 + * + * Instance emac0 of component ALT_EMAC. + * + * + */ +/* + * Register Group Instance : gmacgrp + * + * Instance gmacgrp of register group ALT_EMAC_GMAC. + * + * + */ +/* The address of the ALT_EMAC_GMAC_MAC_CFG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_CFG_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_FRM_FLT_ADDR ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_ADDR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_GMII_ADDR_ADDR ALT_EMAC_GMAC_GMII_ADDR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_DATA register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_GMII_DATA_ADDR ALT_EMAC_GMAC_GMII_DATA_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_FLOW_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_FLOW_CTL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_TAG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VLAN_TAG_ADDR ALT_EMAC_GMAC_VLAN_TAG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VER register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VER_ADDR ALT_EMAC_GMAC_VER_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_DBG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_DBG_ADDR ALT_EMAC_GMAC_DBG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LPI_CTL_STAT_ADDR ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LPI_TMRS_CTL_ADDR ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_INT_STAT_ADDR ALT_EMAC_GMAC_INT_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_INT_MSK_ADDR ALT_EMAC_GMAC_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR0_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR0_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR1_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR1_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR2_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR2_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR3_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR3_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR4_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR4_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR5_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR5_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR6_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR6_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR7_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR7_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR8_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR8_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR9_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR9_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR10_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR10_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR11_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR11_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR12_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR12_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR13_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR13_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR14_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR14_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR15_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR15_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SGMII_RGMII_SMII_CTL_STAT_ADDR ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_CTL_ADDR ALT_EMAC_GMAC_MMC_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_RX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_TX_INT_ADDR ALT_EMAC_GMAC_MMC_TX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_TX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX64OCTETS_GB_ADDR ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXUNICASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXMCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXBCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXUNDERFLOWERROR_ADDR ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXSINGLECOL_G_ADDR ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXMULTICOL_G_ADDR ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXDEFERRED register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXDEFERRED_ADDR ALT_EMAC_GMAC_TXDEFERRED_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXLATECOL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXLATECOL_ADDR ALT_EMAC_GMAC_TXLATECOL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXESSCOL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXEXESSCOL_ADDR ALT_EMAC_GMAC_TXEXESSCOL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXCARRIERERR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXCARRIERERR_ADDR ALT_EMAC_GMAC_TXCARRIERERR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCNT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXOCTETCNT_ADDR ALT_EMAC_GMAC_TXOCTETCNT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXFRMCOUNT_G_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXEXCESSDEF_ADDR ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXPAUSEFRMS_ADDR ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXVLANFRMS_G_ADDR ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TXOVERSIZE_G_ADDR ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOCTETCOUNT_G_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCRCERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXCRCERROR_ADDR ALT_EMAC_GMAC_RXCRCERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXALIGNMENTERROR_ADDR ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRUNTERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXRUNTERROR_ADDR ALT_EMAC_GMAC_RXRUNTERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXJABBERERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXJABBERERROR_ADDR ALT_EMAC_GMAC_RXJABBERERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUNDERSIZE_G_ADDR ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOVERSIZE_G_ADDR ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX64OCTETS_GB_ADDR ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUNICASTFRMS_G_ADDR ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXLENERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXLENERROR_ADDR ALT_EMAC_GMAC_RXLENERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXOUTOFRANGETYPE_ADDR ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXPAUSEFRMS_ADDR ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFIFOOVF register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXFIFOOVF_ADDR ALT_EMAC_GMAC_RXFIFOOVF_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXVLANFRMS_GB_ADDR ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXWDERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXWDERROR_ADDR ALT_EMAC_GMAC_RXWDERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRCVERROR register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXRCVERROR_ADDR ALT_EMAC_GMAC_RXRCVERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXCTLFRMS_G_ADDR ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_IPC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MMC_IPC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_FRAG_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_UDSBL_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_FRAG_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV4_UDSBL_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXIPV6_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXUDP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXTCPERROCTETS_ADDR ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_RXICMP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL0_ADDR ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR0_ADDR ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL1_ADDR ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR1_ADDR ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL2_ADDR ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR2_ADDR ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_L3_L4_CTL3_ADDR ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR4_ADDR3_ADDR ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG0_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG1_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG2_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG3_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG4_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG5_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG6_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_HASH_TABLE_REG7_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VLAN_INCL_REG_ADDR ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_VLAN_HASH_TABLE_REG_ADDR ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TS_CTL_ADDR ALT_EMAC_GMAC_TS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SUB_SEC_INCREMENT_ADDR ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_SECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_ADDEND register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TS_ADDEND_ADDR ALT_EMAC_GMAC_TS_ADDEND_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TGT_TIME_SECS_ADDR ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TGT_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_STAT register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_TS_STAT_ADDR ALT_EMAC_GMAC_TS_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS_CTL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_PPS_CTL_ADDR ALT_EMAC_GMAC_PPS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_AUX_TS_NANOSECS_ADDR ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_AUX_TS_SECS_ADDR ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_PPS0_INTERVAL_ADDR ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_PPS0_WIDTH_ADDR ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR16_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR16_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR17_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR17_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR18_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR18_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR19_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR19_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR20_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR20_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR21_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR21_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR22_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR22_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR23_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR23_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR24_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR24_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR25_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR25_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR26_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR26_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR27_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR27_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR28_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR28_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR29_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR29_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR30_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR30_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR31_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR31_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR32_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR32_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR33_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR33_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR34_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR34_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR35_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR35_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR36_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR36_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR37_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR37_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR38_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR38_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR39_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR39_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR40_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR40_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR41_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR41_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR42_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR42_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR43_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR43_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR44_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR44_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR45_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR45_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR46_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR46_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR47_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR47_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR48_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR48_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR49_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR49_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR50_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR50_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR51_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR51_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR52_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR52_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR53_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR53_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR54_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR54_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR55_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR55_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR56_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR56_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR57_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR57_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR58_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR58_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR59_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR59_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR60_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR60_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR61_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR61_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR62_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR62_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR63_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR63_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR64_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR64_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR65_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR65_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR66_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR66_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR67_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR67_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR68_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR68_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR69_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR69_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR70_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR70_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR71_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR71_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR72_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR72_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR73_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR73_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR74_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR74_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR75_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR75_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR76_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR76_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR77_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR77_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR78_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR78_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR79_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR79_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR80_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR80_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR81_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR81_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR82_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR82_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR83_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR83_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR84_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR84_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR85_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR85_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR86_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR86_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR87_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR87_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR88_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR88_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR89_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR89_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR90_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR90_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR91_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR91_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR92_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR92_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR93_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR93_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR94_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR94_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR95_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR95_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR96_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR96_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR97_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR97_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR98_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR98_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR99_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR99_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR100_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR100_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR101_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR101_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR102_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR102_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR103_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR103_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR104_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR104_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR105_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR105_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR106_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR106_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR107_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR107_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR108_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR108_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR109_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR109_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR110_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR110_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR111_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR111_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR112_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR112_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR113_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR113_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR114_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR114_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR115_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR115_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR116_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR116_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR117_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR117_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR118_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR118_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR119_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR119_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR120_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR120_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR121_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR121_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR122_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR122_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR123_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR123_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR124_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR124_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR125_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR125_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR126_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR126_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR127_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register for the ALT_EMAC0_GMACGRP instance. */ +#define ALT_EMAC0_GMAC_MAC_ADDR127_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_OFST 0x0 +/* The start address of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC0_ADDR) + ALT_EMAC0_GMACGRP_OFST)) +/* The lower bound address range of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_LB_ADDR ALT_EMAC0_GMACGRP_ADDR +/* The upper bound address range of the ALT_EMAC0_GMACGRP component. */ +#define ALT_EMAC0_GMACGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_GMACGRP_ADDR) + 0xb80) - 1)) + + +/* + * Register Group Instance : dmagrp + * + * Instance dmagrp of register group ALT_EMAC_DMA. + * + * + */ +/* The address of the ALT_EMAC_DMA_BUS_MOD register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_BUS_MOD_ADDR ALT_EMAC_DMA_BUS_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_TX_POLL_DEMAND_ADDR ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_RX_POLL_DEMAND_ADDR ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_RX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_TX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_STAT register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_STAT_ADDR ALT_EMAC_DMA_STAT_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_OP_MOD register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_OP_MOD_ADDR ALT_EMAC_DMA_OP_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_INT_EN register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_INT_EN_ADDR ALT_EMAC_DMA_INT_EN_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_MISSED_FRM_AND_BUF_OVF_CNTR_ADDR ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_INT_WDT register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_RX_INT_WDT_ADDR ALT_EMAC_DMA_RX_INT_WDT_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_AXI_BUS_MOD_ADDR ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_AHB_OR_AXI_STAT_ADDR ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_TX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_RX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_TX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_CUR_HOST_RX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_HW_FEATURE register for the ALT_EMAC0_DMAGRP instance. */ +#define ALT_EMAC0_DMA_HW_FEATURE_ADDR ALT_EMAC_DMA_HW_FEATURE_ADDR(ALT_EMAC0_DMAGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_OFST 0x1000 +/* The start address of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC0_ADDR) + ALT_EMAC0_DMAGRP_OFST)) +/* The lower bound address range of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_LB_ADDR ALT_EMAC0_DMAGRP_ADDR +/* The upper bound address range of the ALT_EMAC0_DMAGRP component. */ +#define ALT_EMAC0_DMAGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_DMAGRP_ADDR) + 0x5c) - 1)) + + +/* The base address byte offset for the start of the ALT_EMAC0 component. */ +#define ALT_EMAC0_OFST 0xff700000 +/* The start address of the ALT_EMAC0 component. */ +#define ALT_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_EMAC0_OFST)) +/* The lower bound address range of the ALT_EMAC0 component. */ +#define ALT_EMAC0_LB_ADDR ALT_EMAC0_ADDR +/* The upper bound address range of the ALT_EMAC0 component. */ +#define ALT_EMAC0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_ADDR) + 0x2000) - 1)) + + +/* + * Component Instance : emac1 + * + * Instance emac1 of component ALT_EMAC. + * + * + */ +/* + * Register Group Instance : gmacgrp + * + * Instance gmacgrp of register group ALT_EMAC_GMAC. + * + * + */ +/* The address of the ALT_EMAC_GMAC_MAC_CFG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_CFG_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_FRM_FLT_ADDR ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_ADDR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_GMII_ADDR_ADDR ALT_EMAC_GMAC_GMII_ADDR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_GMII_DATA register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_GMII_DATA_ADDR ALT_EMAC_GMAC_GMII_DATA_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_FLOW_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_FLOW_CTL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_TAG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VLAN_TAG_ADDR ALT_EMAC_GMAC_VLAN_TAG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VER register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VER_ADDR ALT_EMAC_GMAC_VER_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_DBG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_DBG_ADDR ALT_EMAC_GMAC_DBG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LPI_CTL_STAT_ADDR ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LPI_TMRS_CTL_ADDR ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_INT_STAT_ADDR ALT_EMAC_GMAC_INT_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_INT_MSK_ADDR ALT_EMAC_GMAC_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR0_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR0_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR1_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR1_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR2_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR2_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR3_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR3_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR4_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR4_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR5_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR5_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR6_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR6_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR7_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR7_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR8_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR8_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR9_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR9_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR10_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR10_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR11_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR11_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR12_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR12_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR13_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR13_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR14_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR14_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR15_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR15_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SGMII_RGMII_SMII_CTL_STAT_ADDR ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_CTL_ADDR ALT_EMAC_GMAC_MMC_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_RX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_TX_INT_ADDR ALT_EMAC_GMAC_MMC_TX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_TX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX64OCTETS_GB_ADDR ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXUNICASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXMCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXBCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXUNDERFLOWERROR_ADDR ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXSINGLECOL_G_ADDR ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXMULTICOL_G_ADDR ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXDEFERRED register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXDEFERRED_ADDR ALT_EMAC_GMAC_TXDEFERRED_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXLATECOL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXLATECOL_ADDR ALT_EMAC_GMAC_TXLATECOL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXESSCOL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXEXESSCOL_ADDR ALT_EMAC_GMAC_TXEXESSCOL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXCARRIERERR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXCARRIERERR_ADDR ALT_EMAC_GMAC_TXCARRIERERR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOCTETCNT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXOCTETCNT_ADDR ALT_EMAC_GMAC_TXOCTETCNT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXFRMCOUNT_G_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXEXCESSDEF_ADDR ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXPAUSEFRMS_ADDR ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXVLANFRMS_G_ADDR ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TXOVERSIZE_G_ADDR ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOCTETCOUNT_G_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCRCERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXCRCERROR_ADDR ALT_EMAC_GMAC_RXCRCERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXALIGNMENTERROR_ADDR ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRUNTERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXRUNTERROR_ADDR ALT_EMAC_GMAC_RXRUNTERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXJABBERERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXJABBERERROR_ADDR ALT_EMAC_GMAC_RXJABBERERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUNDERSIZE_G_ADDR ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOVERSIZE_G_ADDR ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX64OCTETS_GB_ADDR ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUNICASTFRMS_G_ADDR ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXLENERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXLENERROR_ADDR ALT_EMAC_GMAC_RXLENERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXOUTOFRANGETYPE_ADDR ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXPAUSEFRMS_ADDR ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXFIFOOVF register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXFIFOOVF_ADDR ALT_EMAC_GMAC_RXFIFOOVF_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXVLANFRMS_GB_ADDR ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXWDERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXWDERROR_ADDR ALT_EMAC_GMAC_RXWDERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXRCVERROR register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXRCVERROR_ADDR ALT_EMAC_GMAC_RXRCVERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXCTLFRMS_G_ADDR ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_IPC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MMC_IPC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_FRAG_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_UDSBL_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_FRAG_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV4_UDSBL_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXIPV6_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXUDP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXTCPERROCTETS_ADDR ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_RXICMP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL0_ADDR ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR0_ADDR ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL1_ADDR ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR1_ADDR ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL2_ADDR ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR2_ADDR ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_L3_L4_CTL3_ADDR ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR4_ADDR3_ADDR ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG0_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG1_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG2_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG3_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG4_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG5_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG6_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_HASH_TABLE_REG7_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VLAN_INCL_REG_ADDR ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_VLAN_HASH_TABLE_REG_ADDR ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TS_CTL_ADDR ALT_EMAC_GMAC_TS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SUB_SEC_INCREMENT_ADDR ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_SECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_ADDEND register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TS_ADDEND_ADDR ALT_EMAC_GMAC_TS_ADDEND_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TGT_TIME_SECS_ADDR ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TGT_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_TS_STAT register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_TS_STAT_ADDR ALT_EMAC_GMAC_TS_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS_CTL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_PPS_CTL_ADDR ALT_EMAC_GMAC_PPS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_AUX_TS_NANOSECS_ADDR ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_AUX_TS_SECS_ADDR ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_PPS0_INTERVAL_ADDR ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_PPS0_WIDTH_ADDR ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR16_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR16_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR17_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR17_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR18_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR18_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR19_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR19_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR20_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR20_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR21_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR21_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR22_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR22_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR23_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR23_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR24_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR24_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR25_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR25_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR26_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR26_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR27_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR27_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR28_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR28_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR29_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR29_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR30_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR30_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR31_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR31_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR32_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR32_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR33_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR33_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR34_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR34_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR35_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR35_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR36_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR36_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR37_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR37_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR38_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR38_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR39_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR39_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR40_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR40_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR41_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR41_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR42_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR42_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR43_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR43_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR44_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR44_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR45_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR45_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR46_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR46_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR47_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR47_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR48_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR48_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR49_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR49_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR50_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR50_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR51_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR51_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR52_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR52_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR53_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR53_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR54_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR54_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR55_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR55_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR56_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR56_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR57_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR57_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR58_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR58_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR59_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR59_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR60_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR60_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR61_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR61_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR62_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR62_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR63_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR63_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR64_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR64_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR65_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR65_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR66_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR66_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR67_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR67_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR68_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR68_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR69_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR69_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR70_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR70_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR71_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR71_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR72_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR72_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR73_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR73_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR74_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR74_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR75_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR75_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR76_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR76_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR77_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR77_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR78_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR78_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR79_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR79_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR80_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR80_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR81_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR81_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR82_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR82_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR83_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR83_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR84_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR84_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR85_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR85_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR86_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR86_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR87_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR87_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR88_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR88_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR89_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR89_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR90_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR90_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR91_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR91_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR92_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR92_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR93_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR93_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR94_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR94_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR95_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR95_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR96_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR96_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR97_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR97_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR98_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR98_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR99_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR99_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR100_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR100_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR101_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR101_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR102_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR102_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR103_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR103_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR104_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR104_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR105_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR105_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR106_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR106_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR107_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR107_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR108_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR108_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR109_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR109_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR110_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR110_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR111_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR111_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR112_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR112_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR113_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR113_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR114_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR114_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR115_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR115_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR116_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR116_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR117_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR117_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR118_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR118_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR119_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR119_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR120_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR120_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR121_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR121_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR122_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR122_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR123_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR123_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR124_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR124_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR125_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR125_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR126_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR126_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR127_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register for the ALT_EMAC1_GMACGRP instance. */ +#define ALT_EMAC1_GMAC_MAC_ADDR127_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_OFST 0x0 +/* The start address of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC1_ADDR) + ALT_EMAC1_GMACGRP_OFST)) +/* The lower bound address range of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_LB_ADDR ALT_EMAC1_GMACGRP_ADDR +/* The upper bound address range of the ALT_EMAC1_GMACGRP component. */ +#define ALT_EMAC1_GMACGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_GMACGRP_ADDR) + 0xb80) - 1)) + + +/* + * Register Group Instance : dmagrp + * + * Instance dmagrp of register group ALT_EMAC_DMA. + * + * + */ +/* The address of the ALT_EMAC_DMA_BUS_MOD register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_BUS_MOD_ADDR ALT_EMAC_DMA_BUS_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_TX_POLL_DEMAND_ADDR ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_RX_POLL_DEMAND_ADDR ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_RX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_TX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_STAT register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_STAT_ADDR ALT_EMAC_DMA_STAT_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_OP_MOD register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_OP_MOD_ADDR ALT_EMAC_DMA_OP_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_INT_EN register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_INT_EN_ADDR ALT_EMAC_DMA_INT_EN_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_MISSED_FRM_AND_BUF_OVF_CNTR_ADDR ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_RX_INT_WDT register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_RX_INT_WDT_ADDR ALT_EMAC_DMA_RX_INT_WDT_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_AXI_BUS_MOD_ADDR ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_AHB_OR_AXI_STAT_ADDR ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_TX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_RX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_TX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_CUR_HOST_RX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The address of the ALT_EMAC_DMA_HW_FEATURE register for the ALT_EMAC1_DMAGRP instance. */ +#define ALT_EMAC1_DMA_HW_FEATURE_ADDR ALT_EMAC_DMA_HW_FEATURE_ADDR(ALT_EMAC1_DMAGRP_ADDR) +/* The base address byte offset for the start of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_OFST 0x1000 +/* The start address of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC1_ADDR) + ALT_EMAC1_DMAGRP_OFST)) +/* The lower bound address range of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_LB_ADDR ALT_EMAC1_DMAGRP_ADDR +/* The upper bound address range of the ALT_EMAC1_DMAGRP component. */ +#define ALT_EMAC1_DMAGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_DMAGRP_ADDR) + 0x5c) - 1)) + + +/* The base address byte offset for the start of the ALT_EMAC1 component. */ +#define ALT_EMAC1_OFST 0xff702000 +/* The start address of the ALT_EMAC1 component. */ +#define ALT_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_EMAC1_OFST)) +/* The lower bound address range of the ALT_EMAC1 component. */ +#define ALT_EMAC1_LB_ADDR ALT_EMAC1_ADDR +/* The upper bound address range of the ALT_EMAC1 component. */ +#define ALT_EMAC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_ADDR) + 0x2000) - 1)) + + +/* + * Component Instance : sdmmc + * + * Instance sdmmc of component ALT_SDMMC. + * + * + */ +/* The address of the ALT_SDMMC_CTL register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CTL_OFST)) +/* The address of the ALT_SDMMC_PWREN register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_PWREN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_PWREN_OFST)) +/* The address of the ALT_SDMMC_CLKDIV register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CLKDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKDIV_OFST)) +/* The address of the ALT_SDMMC_CLKSRC register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CLKSRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKSRC_OFST)) +/* The address of the ALT_SDMMC_CLKENA register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CLKENA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKENA_OFST)) +/* The address of the ALT_SDMMC_TMOUT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_TMOUT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TMOUT_OFST)) +/* The address of the ALT_SDMMC_CTYPE register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CTYPE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CTYPE_OFST)) +/* The address of the ALT_SDMMC_BLKSIZ register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BLKSIZ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BLKSIZ_OFST)) +/* The address of the ALT_SDMMC_BYTCNT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BYTCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BYTCNT_OFST)) +/* The address of the ALT_SDMMC_INTMSK register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_INTMSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_INTMSK_OFST)) +/* The address of the ALT_SDMMC_CMDARG register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CMDARG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CMDARG_OFST)) +/* The address of the ALT_SDMMC_CMD register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CMD_OFST)) +/* The address of the ALT_SDMMC_RESP0 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP0_OFST)) +/* The address of the ALT_SDMMC_RESP1 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP1_OFST)) +/* The address of the ALT_SDMMC_RESP2 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP2_OFST)) +/* The address of the ALT_SDMMC_RESP3 register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RESP3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP3_OFST)) +/* The address of the ALT_SDMMC_MINTSTS register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_MINTSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_MINTSTS_OFST)) +/* The address of the ALT_SDMMC_RINTSTS register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RINTSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RINTSTS_OFST)) +/* The address of the ALT_SDMMC_STAT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_STAT_OFST)) +/* The address of the ALT_SDMMC_FIFOTH register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_FIFOTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_FIFOTH_OFST)) +/* The address of the ALT_SDMMC_CDETECT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CDETECT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CDETECT_OFST)) +/* The address of the ALT_SDMMC_WRTPRT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_WRTPRT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_WRTPRT_OFST)) +/* The address of the ALT_SDMMC_TCBCNT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_TCBCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TCBCNT_OFST)) +/* The address of the ALT_SDMMC_TBBCNT register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_TBBCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TBBCNT_OFST)) +/* The address of the ALT_SDMMC_DEBNCE register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DEBNCE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DEBNCE_OFST)) +/* The address of the ALT_SDMMC_USRID register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_USRID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_USRID_OFST)) +/* The address of the ALT_SDMMC_VERID register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_VERID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_VERID_OFST)) +/* The address of the ALT_SDMMC_HCON register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_HCON_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_HCON_OFST)) +/* The address of the ALT_SDMMC_UHS_REG register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_UHS_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_UHS_REG_OFST)) +/* The address of the ALT_SDMMC_RST_N register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_RST_N_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RST_N_OFST)) +/* The address of the ALT_SDMMC_BMOD register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BMOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BMOD_OFST)) +/* The address of the ALT_SDMMC_PLDMND register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_PLDMND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_PLDMND_OFST)) +/* The address of the ALT_SDMMC_DBADDR register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DBADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DBADDR_OFST)) +/* The address of the ALT_SDMMC_IDSTS register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_IDSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_IDSTS_OFST)) +/* The address of the ALT_SDMMC_IDINTEN register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_IDINTEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_IDINTEN_OFST)) +/* The address of the ALT_SDMMC_DSCADDR register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DSCADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DSCADDR_OFST)) +/* The address of the ALT_SDMMC_BUFADDR register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BUFADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BUFADDR_OFST)) +/* The address of the ALT_SDMMC_CARDTHRCTL register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_CARDTHRCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CARDTHRCTL_OFST)) +/* The address of the ALT_SDMMC_BACK_END_POWER_R register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_BACK_END_POWER_R_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BACK_END_POWER_R_OFST)) +/* The address of the ALT_SDMMC_DATA register for the ALT_SDMMC instance. */ +#define ALT_SDMMC_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DATA_OFST)) +/* The base address byte offset for the start of the ALT_SDMMC component. */ +#define ALT_SDMMC_OFST 0xff704000 +/* The start address of the ALT_SDMMC component. */ +#define ALT_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SDMMC_OFST)) +/* The lower bound address range of the ALT_SDMMC component. */ +#define ALT_SDMMC_LB_ADDR ALT_SDMMC_ADDR +/* The upper bound address range of the ALT_SDMMC component. */ +#define ALT_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDMMC_ADDR) + 0x400) - 1)) + + +/* + * Component Instance : qspiregs + * + * Instance qspiregs of component ALT_QSPI. + * + * + */ +/* The address of the ALT_QSPI_CFG register for the ALT_QSPI instance. */ +#define ALT_QSPI_CFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_CFG_OFST)) +/* The address of the ALT_QSPI_DEVRD register for the ALT_QSPI instance. */ +#define ALT_QSPI_DEVRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVRD_OFST)) +/* The address of the ALT_QSPI_DEVWR register for the ALT_QSPI instance. */ +#define ALT_QSPI_DEVWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVWR_OFST)) +/* The address of the ALT_QSPI_DELAY register for the ALT_QSPI instance. */ +#define ALT_QSPI_DELAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DELAY_OFST)) +/* The address of the ALT_QSPI_RDDATACAP register for the ALT_QSPI instance. */ +#define ALT_QSPI_RDDATACAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_RDDATACAP_OFST)) +/* The address of the ALT_QSPI_DEVSZ register for the ALT_QSPI instance. */ +#define ALT_QSPI_DEVSZ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVSZ_OFST)) +/* The address of the ALT_QSPI_SRAMPART register for the ALT_QSPI instance. */ +#define ALT_QSPI_SRAMPART_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_SRAMPART_OFST)) +/* The address of the ALT_QSPI_INDADDRTRIG register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDADDRTRIG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDADDRTRIG_OFST)) +/* The address of the ALT_QSPI_DMAPER register for the ALT_QSPI instance. */ +#define ALT_QSPI_DMAPER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DMAPER_OFST)) +/* The address of the ALT_QSPI_REMAPADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_REMAPADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_REMAPADDR_OFST)) +/* The address of the ALT_QSPI_MODBIT register for the ALT_QSPI instance. */ +#define ALT_QSPI_MODBIT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_MODBIT_OFST)) +/* The address of the ALT_QSPI_SRAMFILL register for the ALT_QSPI instance. */ +#define ALT_QSPI_SRAMFILL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_SRAMFILL_OFST)) +/* The address of the ALT_QSPI_TXTHRESH register for the ALT_QSPI instance. */ +#define ALT_QSPI_TXTHRESH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_TXTHRESH_OFST)) +/* The address of the ALT_QSPI_RXTHRESH register for the ALT_QSPI instance. */ +#define ALT_QSPI_RXTHRESH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_RXTHRESH_OFST)) +/* The address of the ALT_QSPI_IRQSTAT register for the ALT_QSPI instance. */ +#define ALT_QSPI_IRQSTAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_IRQSTAT_OFST)) +/* The address of the ALT_QSPI_IRQMSK register for the ALT_QSPI instance. */ +#define ALT_QSPI_IRQMSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_IRQMSK_OFST)) +/* The address of the ALT_QSPI_LOWWRPROT register for the ALT_QSPI instance. */ +#define ALT_QSPI_LOWWRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_LOWWRPROT_OFST)) +/* The address of the ALT_QSPI_UPPWRPROT register for the ALT_QSPI instance. */ +#define ALT_QSPI_UPPWRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_UPPWRPROT_OFST)) +/* The address of the ALT_QSPI_WRPROT register for the ALT_QSPI instance. */ +#define ALT_QSPI_WRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_WRPROT_OFST)) +/* The address of the ALT_QSPI_INDRD register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRD_OFST)) +/* The address of the ALT_QSPI_INDRDWATER register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRDWATER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDWATER_OFST)) +/* The address of the ALT_QSPI_INDRDSTADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRDSTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDSTADDR_OFST)) +/* The address of the ALT_QSPI_INDRDCNT register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDRDCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDCNT_OFST)) +/* The address of the ALT_QSPI_INDWR register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWR_OFST)) +/* The address of the ALT_QSPI_INDWRWATER register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWRWATER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRWATER_OFST)) +/* The address of the ALT_QSPI_INDWRSTADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWRSTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRSTADDR_OFST)) +/* The address of the ALT_QSPI_INDWRCNT register for the ALT_QSPI instance. */ +#define ALT_QSPI_INDWRCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRCNT_OFST)) +/* The address of the ALT_QSPI_FLSHCMD register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMD_OFST)) +/* The address of the ALT_QSPI_FLSHCMDADDR register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDADDR_OFST)) +/* The address of the ALT_QSPI_FLSHCMDRDDATALO register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDRDDATALO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDRDDATALO_OFST)) +/* The address of the ALT_QSPI_FLSHCMDRDDATAUP register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDRDDATAUP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDRDDATAUP_OFST)) +/* The address of the ALT_QSPI_FLSHCMDWRDATALO register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDWRDATALO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDWRDATALO_OFST)) +/* The address of the ALT_QSPI_FLSHCMDWRDATAUP register for the ALT_QSPI instance. */ +#define ALT_QSPI_FLSHCMDWRDATAUP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDWRDATAUP_OFST)) +/* The address of the ALT_QSPI_MODULEID register for the ALT_QSPI instance. */ +#define ALT_QSPI_MODULEID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_MODULEID_OFST)) +/* The base address byte offset for the start of the ALT_QSPI component. */ +#define ALT_QSPI_OFST 0xff705000 +/* The start address of the ALT_QSPI component. */ +#define ALT_QSPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_QSPI_OFST)) +/* The lower bound address range of the ALT_QSPI component. */ +#define ALT_QSPI_LB_ADDR ALT_QSPI_ADDR +/* The upper bound address range of the ALT_QSPI component. */ +#define ALT_QSPI_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_QSPI_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : fpgamgrregs + * + * Instance fpgamgrregs of component ALT_FPGAMGR. + * + * + */ +/* The address of the ALT_FPGAMGR_STAT register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_STAT_OFST)) +/* The address of the ALT_FPGAMGR_CTL register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_CTL_OFST)) +/* The address of the ALT_FPGAMGR_DCLKCNT register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_DCLKCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_DCLKCNT_OFST)) +/* The address of the ALT_FPGAMGR_DCLKSTAT register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_DCLKSTAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_DCLKSTAT_OFST)) +/* The address of the ALT_FPGAMGR_GPO register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_GPO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_GPO_OFST)) +/* The address of the ALT_FPGAMGR_GPI register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_GPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_GPI_OFST)) +/* The address of the ALT_FPGAMGR_MISCI register for the ALT_FPGAMGR instance. */ +#define ALT_FPGAMGR_MISCI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_MISCI_OFST)) +/* + * Register Group Instance : mon + * + * Instance mon of register group ALT_MON. + * + * + */ +/* The address of the ALT_MON_GPIO_INTEN register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTEN_ADDR ALT_MON_GPIO_INTEN_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INTMSK register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTMSK_ADDR ALT_MON_GPIO_INTMSK_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INTTYPE_LEVEL register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTTYPE_LEVEL_ADDR ALT_MON_GPIO_INTTYPE_LEVEL_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INT_POL register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INT_POL_ADDR ALT_MON_GPIO_INT_POL_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_INTSTAT register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_INTSTAT_ADDR ALT_MON_GPIO_INTSTAT_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_RAW_INTSTAT register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_RAW_INTSTAT_ADDR ALT_MON_GPIO_RAW_INTSTAT_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_PORTA_EOI register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_PORTA_EOI_ADDR ALT_MON_GPIO_PORTA_EOI_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_EXT_PORTA register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_EXT_PORTA_ADDR ALT_MON_GPIO_EXT_PORTA_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_LS_SYNC register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_LS_SYNC_ADDR ALT_MON_GPIO_LS_SYNC_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_VER_ID_CODE register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_VER_ID_CODE_ADDR ALT_MON_GPIO_VER_ID_CODE_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_CFG_REG2 register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_CFG_REG2_ADDR ALT_MON_GPIO_CFG_REG2_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The address of the ALT_MON_GPIO_CFG_REG1 register for the ALT_FPGAMGR_MON instance. */ +#define ALT_FPGAMGR_MON_GPIO_CFG_REG1_ADDR ALT_MON_GPIO_CFG_REG1_ADDR(ALT_FPGAMGR_MON_ADDR) +/* The base address byte offset for the start of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_OFST 0x800 +/* The start address of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_MON_OFST)) +/* The lower bound address range of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_LB_ADDR ALT_FPGAMGR_MON_ADDR +/* The upper bound address range of the ALT_FPGAMGR_MON component. */ +#define ALT_FPGAMGR_MON_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGR_MON_ADDR) + 0x80) - 1)) + + +/* The base address byte offset for the start of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_OFST 0xff706000 +/* The start address of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_FPGAMGR_OFST)) +/* The lower bound address range of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_LB_ADDR ALT_FPGAMGR_ADDR +/* The upper bound address range of the ALT_FPGAMGR component. */ +#define ALT_FPGAMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGR_ADDR) + 0x1000) - 1)) + + +/* + * Component Instance : acpidmap + * + * Instance acpidmap of component ALT_ACPIDMAP. + * + * + */ +/* The address of the ALT_ACPIDMAP_VID2RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID2WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID3RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID3WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID4RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID4WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID5RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID5WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5WR_OFST)) +/* The address of the ALT_ACPIDMAP_VID6RD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6RD_OFST)) +/* The address of the ALT_ACPIDMAP_VID6WR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6WR_OFST)) +/* The address of the ALT_ACPIDMAP_DYNRD register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNRD_OFST)) +/* The address of the ALT_ACPIDMAP_DYNWR register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNWR_OFST)) +/* The address of the ALT_ACPIDMAP_VID2RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID2WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID2WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID3RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID3WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID3WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID4RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID4WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID4WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID5RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID5WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID5WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID6RD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6RD_S_OFST)) +/* The address of the ALT_ACPIDMAP_VID6WR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_VID6WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6WR_S_OFST)) +/* The address of the ALT_ACPIDMAP_DYNRD_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNRD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNRD_S_OFST)) +/* The address of the ALT_ACPIDMAP_DYNWR_S register for the ALT_ACPIDMAP instance. */ +#define ALT_ACPIDMAP_DYNWR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNWR_S_OFST)) +/* The base address byte offset for the start of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_OFST 0xff707000 +/* The start address of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_ACPIDMAP_OFST)) +/* The lower bound address range of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_LB_ADDR ALT_ACPIDMAP_ADDR +/* The upper bound address range of the ALT_ACPIDMAP component. */ +#define ALT_ACPIDMAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + 0x1000) - 1)) + + +/* + * Component Instance : gpio0 + * + * Instance gpio0 of component ALT_GPIO. + * + * + */ +/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO0_ADDR) +/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO0 instance. */ +#define ALT_GPIO0_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO0_ADDR) +/* The base address byte offset for the start of the ALT_GPIO0 component. */ +#define ALT_GPIO0_OFST 0xff708000 +/* The start address of the ALT_GPIO0 component. */ +#define ALT_GPIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO0_OFST)) +/* The lower bound address range of the ALT_GPIO0 component. */ +#define ALT_GPIO0_LB_ADDR ALT_GPIO0_ADDR +/* The upper bound address range of the ALT_GPIO0 component. */ +#define ALT_GPIO0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO0_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : gpio1 + * + * Instance gpio1 of component ALT_GPIO. + * + * + */ +/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO1_ADDR) +/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO1 instance. */ +#define ALT_GPIO1_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO1_ADDR) +/* The base address byte offset for the start of the ALT_GPIO1 component. */ +#define ALT_GPIO1_OFST 0xff709000 +/* The start address of the ALT_GPIO1 component. */ +#define ALT_GPIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO1_OFST)) +/* The lower bound address range of the ALT_GPIO1 component. */ +#define ALT_GPIO1_LB_ADDR ALT_GPIO1_ADDR +/* The upper bound address range of the ALT_GPIO1 component. */ +#define ALT_GPIO1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO1_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : gpio2 + * + * Instance gpio2 of component ALT_GPIO. + * + * + */ +/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO2_ADDR) +/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO2 instance. */ +#define ALT_GPIO2_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO2_ADDR) +/* The base address byte offset for the start of the ALT_GPIO2 component. */ +#define ALT_GPIO2_OFST 0xff70a000 +/* The start address of the ALT_GPIO2 component. */ +#define ALT_GPIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO2_OFST)) +/* The lower bound address range of the ALT_GPIO2 component. */ +#define ALT_GPIO2_LB_ADDR ALT_GPIO2_ADDR +/* The upper bound address range of the ALT_GPIO2 component. */ +#define ALT_GPIO2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO2_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : l3regs + * + * Instance l3regs of component ALT_L3. + * + * + */ +/* The address of the ALT_L3_REMAP register for the ALT_L3 instance. */ +#define ALT_L3_REMAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_REMAP_OFST)) +/* + * Register Group Instance : secgrp + * + * Instance secgrp of register group ALT_L3_SECGRP. + * + * + */ +/* The address of the ALT_L3_SEC_L4MAIN register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4MAIN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4MAIN_OFST)) +/* The address of the ALT_L3_SEC_L4SP register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4SP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4SP_OFST)) +/* The address of the ALT_L3_SEC_L4MP register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4MP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4MP_OFST)) +/* The address of the ALT_L3_SEC_L4OSC1 register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4OSC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4OSC1_OFST)) +/* The address of the ALT_L3_SEC_L4SPIM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_L4SPIM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4SPIM_OFST)) +/* The address of the ALT_L3_SEC_STM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_STM_OFST)) +/* The address of the ALT_L3_SEC_LWH2F register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_LWH2F_OFST)) +/* The address of the ALT_L3_SEC_USB1 register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_USB1_OFST)) +/* The address of the ALT_L3_SEC_NANDDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_NANDDATA_OFST)) +/* The address of the ALT_L3_SEC_USB0 register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_USB0_OFST)) +/* The address of the ALT_L3_SEC_NAND register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_NAND_OFST)) +/* The address of the ALT_L3_SEC_QSPIDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_QSPIDATA_OFST)) +/* The address of the ALT_L3_SEC_FPGAMGRDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_FPGAMGRDATA_OFST)) +/* The address of the ALT_L3_SEC_H2F register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_H2F_OFST)) +/* The address of the ALT_L3_SEC_ACP register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_ACP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_ACP_OFST)) +/* The address of the ALT_L3_SEC_ROM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_ROM_OFST)) +/* The address of the ALT_L3_SEC_OCRAM register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_OCRAM_OFST)) +/* The address of the ALT_L3_SEC_SDRDATA register for the ALT_L3_SECGRP instance. */ +#define ALT_L3_SEC_SDRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_SDRDATA_OFST)) +/* The base address byte offset for the start of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_OFST 0x8 +/* The start address of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_SECGRP_OFST)) +/* The lower bound address range of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_LB_ADDR ALT_L3_SECGRP_ADDR +/* The upper bound address range of the ALT_L3_SECGRP component. */ +#define ALT_L3_SECGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + 0x9c) - 1)) + + +/* + * Register Group Instance : idgrp + * + * Instance idgrp of register group ALT_L3_IDGRP. + * + * + */ +/* The address of the ALT_L3_ID_PERIPH_ID_4 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_4_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_0 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_0_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_1 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_1_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_2 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_2_OFST)) +/* The address of the ALT_L3_ID_PERIPH_ID_3 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_3_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_0 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_0_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_1 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_1_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_2 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_2_OFST)) +/* The address of the ALT_L3_ID_COMP_ID_3 register for the ALT_L3_IDGRP instance. */ +#define ALT_L3_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_3_OFST)) +/* The base address byte offset for the start of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_OFST 0x1000 +/* The start address of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_IDGRP_OFST)) +/* The lower bound address range of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_LB_ADDR ALT_L3_IDGRP_ADDR +/* The upper bound address range of the ALT_L3_IDGRP component. */ +#define ALT_L3_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + 0x1000) - 1)) + + +/* + * Register Group Instance : mastergrp + * + * Instance mastergrp of register group ALT_L3_MSTGRP. + * + * + */ +/* + * Register Group Instance : mastergrp_l4main + * + * Instance mastergrp_l4main of register group ALT_L3_MST_L4MAIN. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4MAIN instance. */ +#define ALT_L3_MST_MST_L4MAIN_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4MAIN_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_OFST 0x0 +/* The start address of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4MAIN_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_LB_ADDR ALT_L3_MST_MST_L4MAIN_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4MAIN component. */ +#define ALT_L3_MST_MST_L4MAIN_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4MAIN_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4sp + * + * Instance mastergrp_l4sp of register group ALT_L3_MST_L4SP. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4SP instance. */ +#define ALT_L3_MST_MST_L4SP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4SP_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_OFST 0x1000 +/* The start address of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4SP_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_LB_ADDR ALT_L3_MST_MST_L4SP_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4SP component. */ +#define ALT_L3_MST_MST_L4SP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4SP_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4mp + * + * Instance mastergrp_l4mp of register group ALT_L3_MST_L4MP. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4MP instance. */ +#define ALT_L3_MST_MST_L4MP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4MP_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_OFST 0x2000 +/* The start address of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4MP_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_LB_ADDR ALT_L3_MST_MST_L4MP_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4MP component. */ +#define ALT_L3_MST_MST_L4MP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4MP_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4osc1 + * + * Instance mastergrp_l4osc1 of register group ALT_L3_MST_L4OSC1. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4OSC1 instance. */ +#define ALT_L3_MST_MST_L4OSC1_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4OSC1_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_OFST 0x3000 +/* The start address of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4OSC1_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_LB_ADDR ALT_L3_MST_MST_L4OSC1_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4OSC1 component. */ +#define ALT_L3_MST_MST_L4OSC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4OSC1_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_l4spim + * + * Instance mastergrp_l4spim of register group ALT_L3_MST_L4SPIM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4SPIM instance. */ +#define ALT_L3_MST_MST_L4SPIM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4SPIM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_OFST 0x4000 +/* The start address of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4SPIM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_LB_ADDR ALT_L3_MST_MST_L4SPIM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_L4SPIM component. */ +#define ALT_L3_MST_MST_L4SPIM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4SPIM_ADDR) + 0xc) - 1)) + + +/* + * Register Group Instance : mastergrp_stm + * + * Instance mastergrp_stm of register group ALT_L3_MST_STM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_STM instance. */ +#define ALT_L3_MST_MST_STM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_STM_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_STM instance. */ +#define ALT_L3_MST_MST_STM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_STM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_OFST 0x5000 +/* The start address of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_STM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_LB_ADDR ALT_L3_MST_MST_STM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_STM component. */ +#define ALT_L3_MST_MST_STM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_STM_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_lwhps2fpga + * + * Instance mastergrp_lwhps2fpga of register group ALT_L3_MST_LWH2F. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_LWH2F instance. */ +#define ALT_L3_MST_MST_LWH2F_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_LWH2F_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_LWH2F instance. */ +#define ALT_L3_MST_MST_LWH2F_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_LWH2F_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_OFST 0x6000 +/* The start address of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_LWH2F_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_LB_ADDR ALT_L3_MST_MST_LWH2F_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_LWH2F component. */ +#define ALT_L3_MST_MST_LWH2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_LWH2F_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_usb1 + * + * Instance mastergrp_usb1 of register group ALT_L3_MST_USB1. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_USB1 instance. */ +#define ALT_L3_MST_MST_USB1_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_USB1_ADDR) +/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_USB1 instance. */ +#define ALT_L3_MST_MST_USB1_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_USB1_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_OFST 0x8000 +/* The start address of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_USB1_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_LB_ADDR ALT_L3_MST_MST_USB1_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_USB1 component. */ +#define ALT_L3_MST_MST_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_USB1_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_nanddata + * + * Instance mastergrp_nanddata of register group ALT_L3_MST_NANDDATA. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_NANDDATA instance. */ +#define ALT_L3_MST_MST_NANDDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_NANDDATA_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_NANDDATA instance. */ +#define ALT_L3_MST_MST_NANDDATA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_NANDDATA_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_OFST 0x9000 +/* The start address of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_NANDDATA_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_LB_ADDR ALT_L3_MST_MST_NANDDATA_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_NANDDATA component. */ +#define ALT_L3_MST_MST_NANDDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_NANDDATA_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_usb0 + * + * Instance mastergrp_usb0 of register group ALT_L3_MST_USB0. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_USB0 instance. */ +#define ALT_L3_MST_MST_USB0_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_USB0_ADDR) +/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_USB0 instance. */ +#define ALT_L3_MST_MST_USB0_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_USB0_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_OFST 0x1e000 +/* The start address of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_USB0_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_LB_ADDR ALT_L3_MST_MST_USB0_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_USB0 component. */ +#define ALT_L3_MST_MST_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_USB0_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_nandregs + * + * Instance mastergrp_nandregs of register group ALT_L3_MST_NAND. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_NAND instance. */ +#define ALT_L3_MST_MST_NAND_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_NAND_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_NAND instance. */ +#define ALT_L3_MST_MST_NAND_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_NAND_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_OFST 0x1f000 +/* The start address of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_NAND_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_LB_ADDR ALT_L3_MST_MST_NAND_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_NAND component. */ +#define ALT_L3_MST_MST_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_NAND_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_qspidata + * + * Instance mastergrp_qspidata of register group ALT_L3_MST_QSPIDATA. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_QSPIDATA instance. */ +#define ALT_L3_MST_MST_QSPIDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_QSPIDATA_ADDR) +/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_QSPIDATA instance. */ +#define ALT_L3_MST_MST_QSPIDATA_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_QSPIDATA_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_OFST 0x20000 +/* The start address of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_QSPIDATA_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_LB_ADDR ALT_L3_MST_MST_QSPIDATA_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_QSPIDATA component. */ +#define ALT_L3_MST_MST_QSPIDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_QSPIDATA_ADDR) + 0x48) - 1)) + + +/* + * Register Group Instance : mastergrp_fpgamgrdata + * + * Instance mastergrp_fpgamgrdata of register group ALT_L3_MST_FPGAMGRDATA. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_OFST 0x21000 +/* The start address of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_FPGAMGRDATA_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_LB_ADDR ALT_L3_MST_MST_FPGAMGRDATA_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_FPGAMGRDATA component. */ +#define ALT_L3_MST_MST_FPGAMGRDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_FPGAMGRDATA_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_hps2fpga + * + * Instance mastergrp_hps2fpga of register group ALT_L3_MST_H2F. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_H2F instance. */ +#define ALT_L3_MST_MST_H2F_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_H2F_ADDR) +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_H2F instance. */ +#define ALT_L3_MST_MST_H2F_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_H2F_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_H2F instance. */ +#define ALT_L3_MST_MST_H2F_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_H2F_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_OFST 0x22000 +/* The start address of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_H2F_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_LB_ADDR ALT_L3_MST_MST_H2F_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_H2F component. */ +#define ALT_L3_MST_MST_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_H2F_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_acp + * + * Instance mastergrp_acp of register group ALT_L3_MST_ACP. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_ACP instance. */ +#define ALT_L3_MST_MST_ACP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_ACP_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_ACP instance. */ +#define ALT_L3_MST_MST_ACP_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_ACP_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_OFST 0x23000 +/* The start address of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_ACP_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_LB_ADDR ALT_L3_MST_MST_ACP_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_ACP component. */ +#define ALT_L3_MST_MST_ACP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_ACP_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_rom + * + * Instance mastergrp_rom of register group ALT_L3_MST_ROM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_ROM instance. */ +#define ALT_L3_MST_MST_ROM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_ROM_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_ROM instance. */ +#define ALT_L3_MST_MST_ROM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_ROM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_OFST 0x24000 +/* The start address of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_ROM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_LB_ADDR ALT_L3_MST_MST_ROM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_ROM component. */ +#define ALT_L3_MST_MST_ROM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_ROM_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : mastergrp_ocram + * + * Instance mastergrp_ocram of register group ALT_L3_MST_OCRAM. + * + * + */ +/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_OCRAM instance. */ +#define ALT_L3_MST_MST_OCRAM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_OCRAM instance. */ +#define ALT_L3_MST_MST_OCRAM_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_OCRAM instance. */ +#define ALT_L3_MST_MST_OCRAM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) +/* The base address byte offset for the start of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_OFST 0x25000 +/* The start address of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_OCRAM_OFST)) +/* The lower bound address range of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_LB_ADDR ALT_L3_MST_MST_OCRAM_ADDR +/* The upper bound address range of the ALT_L3_MST_MST_OCRAM component. */ +#define ALT_L3_MST_MST_OCRAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_OCRAM_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_OFST 0x2000 +/* The start address of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_MSTGRP_OFST)) +/* The lower bound address range of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_LB_ADDR ALT_L3_MSTGRP_ADDR +/* The upper bound address range of the ALT_L3_MSTGRP component. */ +#define ALT_L3_MSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + 0x2510c) - 1)) + + +/* + * Register Group Instance : slavegrp + * + * Instance slavegrp of register group ALT_L3_SLVGRP. + * + * + */ +/* + * Register Group Instance : slavegrp_dap + * + * Instance slavegrp_dap of register group ALT_L3_SLV_DAP. + * + * + */ +/* The address of the ALT_L3_FN_MOD2 register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_FN_MOD2_ADDR ALT_L3_FN_MOD2_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_DAP instance. */ +#define ALT_L3_SLV_SLV_DAP_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_OFST 0x0 +/* The start address of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_DAP_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_LB_ADDR ALT_L3_SLV_SLV_DAP_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_DAP component. */ +#define ALT_L3_SLV_SLV_DAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_DAP_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_mpu + * + * Instance slavegrp_mpu of register group ALT_L3_SLV_MPU. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_MPU instance. */ +#define ALT_L3_SLV_SLV_MPU_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_MPU instance. */ +#define ALT_L3_SLV_SLV_MPU_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_MPU instance. */ +#define ALT_L3_SLV_SLV_MPU_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_OFST 0x1000 +/* The start address of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_MPU_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_LB_ADDR ALT_L3_SLV_SLV_MPU_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_MPU component. */ +#define ALT_L3_SLV_SLV_MPU_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_MPU_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_sdmmc + * + * Instance slavegrp_sdmmc of register group ALT_L3_SLV_SDMMC. + * + * + */ +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_SDMMC instance. */ +#define ALT_L3_SLV_SLV_SDMMC_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_OFST 0x2000 +/* The start address of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_SDMMC_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_LB_ADDR ALT_L3_SLV_SLV_SDMMC_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_SDMMC component. */ +#define ALT_L3_SLV_SLV_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_SDMMC_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_dma + * + * Instance slavegrp_dma of register group ALT_L3_SLV_DMA. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_DMA instance. */ +#define ALT_L3_SLV_SLV_DMA_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_DMA instance. */ +#define ALT_L3_SLV_SLV_DMA_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_DMA instance. */ +#define ALT_L3_SLV_SLV_DMA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_OFST 0x3000 +/* The start address of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_DMA_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_LB_ADDR ALT_L3_SLV_SLV_DMA_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_DMA component. */ +#define ALT_L3_SLV_SLV_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_DMA_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_fpga2hps + * + * Instance slavegrp_fpga2hps of register group ALT_L3_SLV_F2H. + * + * + */ +/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_F2H instance. */ +#define ALT_L3_SLV_SLV_FPGA2FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_OFST 0x4000 +/* The start address of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_F2H_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_LB_ADDR ALT_L3_SLV_SLV_F2H_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_F2H component. */ +#define ALT_L3_SLV_SLV_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_F2H_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_etr + * + * Instance slavegrp_etr of register group ALT_L3_SLV_ETR. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_ETR instance. */ +#define ALT_L3_SLV_SLV_ETR_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_ETR instance. */ +#define ALT_L3_SLV_SLV_ETR_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_ETR instance. */ +#define ALT_L3_SLV_SLV_ETR_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_OFST 0x5000 +/* The start address of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_ETR_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_LB_ADDR ALT_L3_SLV_SLV_ETR_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_ETR component. */ +#define ALT_L3_SLV_SLV_ETR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_ETR_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_emac0 + * + * Instance slavegrp_emac0 of register group ALT_L3_SLV_EMAC0. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_EMAC0 instance. */ +#define ALT_L3_SLV_SLV_EMAC0_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_EMAC0 instance. */ +#define ALT_L3_SLV_SLV_EMAC0_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_EMAC0 instance. */ +#define ALT_L3_SLV_SLV_EMAC0_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_OFST 0x6000 +/* The start address of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_EMAC0_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_LB_ADDR ALT_L3_SLV_SLV_EMAC0_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_EMAC0 component. */ +#define ALT_L3_SLV_SLV_EMAC0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_EMAC0_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_emac1 + * + * Instance slavegrp_emac1 of register group ALT_L3_SLV_EMAC1. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_EMAC1 instance. */ +#define ALT_L3_SLV_SLV_EMAC1_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_EMAC1 instance. */ +#define ALT_L3_SLV_SLV_EMAC1_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_EMAC1 instance. */ +#define ALT_L3_SLV_SLV_EMAC1_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_OFST 0x7000 +/* The start address of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_EMAC1_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_LB_ADDR ALT_L3_SLV_SLV_EMAC1_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_EMAC1 component. */ +#define ALT_L3_SLV_SLV_EMAC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_EMAC1_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_usb0 + * + * Instance slavegrp_usb0 of register group ALT_L3_SLV_USB0. + * + * + */ +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_USB0 instance. */ +#define ALT_L3_SLV_SLV_USB0_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_OFST 0x8000 +/* The start address of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_USB0_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_LB_ADDR ALT_L3_SLV_SLV_USB0_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_USB0 component. */ +#define ALT_L3_SLV_SLV_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_USB0_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_nand + * + * Instance slavegrp_nand of register group ALT_L3_SLV_NAND. + * + * + */ +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_NAND instance. */ +#define ALT_L3_SLV_SLV_NAND_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_NAND instance. */ +#define ALT_L3_SLV_SLV_NAND_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_NAND instance. */ +#define ALT_L3_SLV_SLV_NAND_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_OFST 0x9000 +/* The start address of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_NAND_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_LB_ADDR ALT_L3_SLV_SLV_NAND_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_NAND component. */ +#define ALT_L3_SLV_SLV_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_NAND_ADDR) + 0x10c) - 1)) + + +/* + * Register Group Instance : slavegrp_usb1 + * + * Instance slavegrp_usb1 of register group ALT_L3_SLV_USB1. + * + * + */ +/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_USB1 instance. */ +#define ALT_L3_SLV_SLV_USB1_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) +/* The base address byte offset for the start of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_OFST 0xa000 +/* The start address of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_USB1_OFST)) +/* The lower bound address range of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_LB_ADDR ALT_L3_SLV_SLV_USB1_ADDR +/* The upper bound address range of the ALT_L3_SLV_SLV_USB1 component. */ +#define ALT_L3_SLV_SLV_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_USB1_ADDR) + 0x10c) - 1)) + + +/* The base address byte offset for the start of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_OFST 0x42000 +/* The start address of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_SLVGRP_OFST)) +/* The lower bound address range of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_LB_ADDR ALT_L3_SLVGRP_ADDR +/* The upper bound address range of the ALT_L3_SLVGRP component. */ +#define ALT_L3_SLVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + 0xa10c) - 1)) + + +/* The base address byte offset for the start of the ALT_L3 component. */ +#define ALT_L3_OFST 0xff800000 +/* The start address of the ALT_L3 component. */ +#define ALT_L3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L3_OFST)) +/* The lower bound address range of the ALT_L3 component. */ +#define ALT_L3_LB_ADDR ALT_L3_ADDR +/* The upper bound address range of the ALT_L3 component. */ +#define ALT_L3_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_ADDR) + 0x80000) - 1)) + + +/* + * Component Instance : nanddata + * + * Instance nanddata of component ALT_NANDDATA. + * + * + */ +/* The base address byte offset for the start of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_OFST 0xff900000 +/* The start address of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_NANDDATA_OFST)) +/* The lower bound address range of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_LB_ADDR ALT_NANDDATA_ADDR +/* The upper bound address range of the ALT_NANDDATA component. */ +#define ALT_NANDDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NANDDATA_ADDR) + 0x100000) - 1)) + + +/* + * Component Instance : qspidata + * + * Instance qspidata of component ALT_QSPIDATA. + * + * + */ +/* The base address byte offset for the start of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_OFST 0xffa00000 +/* The start address of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_QSPIDATA_OFST)) +/* The lower bound address range of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_LB_ADDR ALT_QSPIDATA_ADDR +/* The upper bound address range of the ALT_QSPIDATA component. */ +#define ALT_QSPIDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_QSPIDATA_ADDR) + 0x100000) - 1)) + + +/* + * Component Instance : usb0 + * + * Instance usb0 of component ALT_USB. + * + * + */ +/* + * Register Group Instance : globgrp + * + * Instance globgrp of register group ALT_USB_GLOB. + * + * + */ +/* The address of the ALT_USB_GLOB_GOTGCTL register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GOTGCTL_ADDR ALT_USB_GLOB_GOTGCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GOTGINT register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GOTGINT_ADDR ALT_USB_GLOB_GOTGINT_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GAHBCFG register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GAHBCFG_ADDR ALT_USB_GLOB_GAHBCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUSBCFG register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GUSBCFG_ADDR ALT_USB_GLOB_GUSBCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRSTCTL register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRSTCTL_ADDR ALT_USB_GLOB_GRSTCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTSTS register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GINTSTS_ADDR ALT_USB_GLOB_GINTSTS_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTMSK register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GINTMSK_ADDR ALT_USB_GLOB_GINTMSK_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSR register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRXSTSR_ADDR ALT_USB_GLOB_GRXSTSR_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSP register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRXSTSP_ADDR ALT_USB_GLOB_GRXSTSP_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXFSIZ register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GRXFSIZ_ADDR ALT_USB_GLOB_GRXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXFSIZ register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GNPTXFSIZ_ADDR ALT_USB_GLOB_GNPTXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXSTS register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GNPTXSTS_ADDR ALT_USB_GLOB_GNPTXSTS_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GPVNDCTL register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GPVNDCTL_ADDR ALT_USB_GLOB_GPVNDCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GGPIO register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GGPIO_ADDR ALT_USB_GLOB_GGPIO_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUID register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GUID_ADDR ALT_USB_GLOB_GUID_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GSNPSID register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GSNPSID_ADDR ALT_USB_GLOB_GSNPSID_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG1 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG1_ADDR ALT_USB_GLOB_GHWCFG1_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG2 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG2_ADDR ALT_USB_GLOB_GHWCFG2_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG3 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG3_ADDR ALT_USB_GLOB_GHWCFG3_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG4 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GHWCFG4_ADDR ALT_USB_GLOB_GHWCFG4_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GDFIFOCFG register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_GDFIFOCFG_ADDR ALT_USB_GLOB_GDFIFOCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_HPTXFSIZ register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_HPTXFSIZ_ADDR ALT_USB_GLOB_HPTXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF1 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF1_ADDR ALT_USB_GLOB_DIEPTXF1_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF2 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF2_ADDR ALT_USB_GLOB_DIEPTXF2_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF3 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF3_ADDR ALT_USB_GLOB_DIEPTXF3_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF4 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF4_ADDR ALT_USB_GLOB_DIEPTXF4_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF5 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF5_ADDR ALT_USB_GLOB_DIEPTXF5_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF6 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF6_ADDR ALT_USB_GLOB_DIEPTXF6_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF7 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF7_ADDR ALT_USB_GLOB_DIEPTXF7_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF8 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF8_ADDR ALT_USB_GLOB_DIEPTXF8_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF9 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF9_ADDR ALT_USB_GLOB_DIEPTXF9_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF10 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF10_ADDR ALT_USB_GLOB_DIEPTXF10_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF11 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF11_ADDR ALT_USB_GLOB_DIEPTXF11_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF12 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF12_ADDR ALT_USB_GLOB_DIEPTXF12_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF13 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF13_ADDR ALT_USB_GLOB_DIEPTXF13_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF14 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF14_ADDR ALT_USB_GLOB_DIEPTXF14_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF15 register for the ALT_USB0_GLOBGRP instance. */ +#define ALT_USB0_GLOB_DIEPTXF15_ADDR ALT_USB_GLOB_DIEPTXF15_ADDR(ALT_USB0_GLOBGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_OFST 0x0 +/* The start address of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_GLOBGRP_OFST)) +/* The lower bound address range of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_LB_ADDR ALT_USB0_GLOBGRP_ADDR +/* The upper bound address range of the ALT_USB0_GLOBGRP component. */ +#define ALT_USB0_GLOBGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_GLOBGRP_ADDR) + 0x140) - 1)) + + +/* + * Register Group Instance : hostgrp + * + * Instance hostgrp of register group ALT_USB_HOST. + * + * + */ +/* The address of the ALT_USB_HOST_HCFG register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCFG_ADDR ALT_USB_HOST_HCFG_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFIR register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HFIR_ADDR ALT_USB_HOST_HFIR_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFNUM register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HFNUM_ADDR ALT_USB_HOST_HFNUM_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPTXSTS register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HPTXSTS_ADDR ALT_USB_HOST_HPTXSTS_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINT register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HAINT_ADDR ALT_USB_HOST_HAINT_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINTMSK register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HAINTMSK_ADDR ALT_USB_HOST_HAINTMSK_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFLBADDR register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HFLBADDR_ADDR ALT_USB_HOST_HFLBADDR_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPRT register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HPRT_ADDR ALT_USB_HOST_HPRT_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR0_ADDR ALT_USB_HOST_HCCHAR0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT0_ADDR ALT_USB_HOST_HCSPLT0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT0_ADDR ALT_USB_HOST_HCINT0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK0_ADDR ALT_USB_HOST_HCINTMSK0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ0_ADDR ALT_USB_HOST_HCTSIZ0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA0_ADDR ALT_USB_HOST_HCDMA0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB0 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB0_ADDR ALT_USB_HOST_HCDMAB0_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR1_ADDR ALT_USB_HOST_HCCHAR1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT1_ADDR ALT_USB_HOST_HCSPLT1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT1_ADDR ALT_USB_HOST_HCINT1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK1_ADDR ALT_USB_HOST_HCINTMSK1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ1_ADDR ALT_USB_HOST_HCTSIZ1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA1_ADDR ALT_USB_HOST_HCDMA1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB1 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB1_ADDR ALT_USB_HOST_HCDMAB1_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR2_ADDR ALT_USB_HOST_HCCHAR2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT2_ADDR ALT_USB_HOST_HCSPLT2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT2_ADDR ALT_USB_HOST_HCINT2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK2_ADDR ALT_USB_HOST_HCINTMSK2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ2_ADDR ALT_USB_HOST_HCTSIZ2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA2_ADDR ALT_USB_HOST_HCDMA2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB2 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB2_ADDR ALT_USB_HOST_HCDMAB2_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR3_ADDR ALT_USB_HOST_HCCHAR3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT3_ADDR ALT_USB_HOST_HCSPLT3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT3_ADDR ALT_USB_HOST_HCINT3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK3_ADDR ALT_USB_HOST_HCINTMSK3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ3_ADDR ALT_USB_HOST_HCTSIZ3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA3_ADDR ALT_USB_HOST_HCDMA3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB3 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB3_ADDR ALT_USB_HOST_HCDMAB3_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR4_ADDR ALT_USB_HOST_HCCHAR4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT4_ADDR ALT_USB_HOST_HCSPLT4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT4_ADDR ALT_USB_HOST_HCINT4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK4_ADDR ALT_USB_HOST_HCINTMSK4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ4_ADDR ALT_USB_HOST_HCTSIZ4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA4_ADDR ALT_USB_HOST_HCDMA4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB4 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB4_ADDR ALT_USB_HOST_HCDMAB4_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR5_ADDR ALT_USB_HOST_HCCHAR5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT5_ADDR ALT_USB_HOST_HCSPLT5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT5_ADDR ALT_USB_HOST_HCINT5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK5_ADDR ALT_USB_HOST_HCINTMSK5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ5_ADDR ALT_USB_HOST_HCTSIZ5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA5_ADDR ALT_USB_HOST_HCDMA5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB5 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB5_ADDR ALT_USB_HOST_HCDMAB5_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR6_ADDR ALT_USB_HOST_HCCHAR6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT6_ADDR ALT_USB_HOST_HCSPLT6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT6_ADDR ALT_USB_HOST_HCINT6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK6_ADDR ALT_USB_HOST_HCINTMSK6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ6_ADDR ALT_USB_HOST_HCTSIZ6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA6_ADDR ALT_USB_HOST_HCDMA6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB6 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB6_ADDR ALT_USB_HOST_HCDMAB6_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR7_ADDR ALT_USB_HOST_HCCHAR7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT7_ADDR ALT_USB_HOST_HCSPLT7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT7_ADDR ALT_USB_HOST_HCINT7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK7_ADDR ALT_USB_HOST_HCINTMSK7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ7_ADDR ALT_USB_HOST_HCTSIZ7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA7_ADDR ALT_USB_HOST_HCDMA7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB7 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB7_ADDR ALT_USB_HOST_HCDMAB7_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR8_ADDR ALT_USB_HOST_HCCHAR8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT8_ADDR ALT_USB_HOST_HCSPLT8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT8_ADDR ALT_USB_HOST_HCINT8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK8_ADDR ALT_USB_HOST_HCINTMSK8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ8_ADDR ALT_USB_HOST_HCTSIZ8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA8_ADDR ALT_USB_HOST_HCDMA8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB8 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB8_ADDR ALT_USB_HOST_HCDMAB8_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR9_ADDR ALT_USB_HOST_HCCHAR9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT9_ADDR ALT_USB_HOST_HCSPLT9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT9_ADDR ALT_USB_HOST_HCINT9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK9_ADDR ALT_USB_HOST_HCINTMSK9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ9_ADDR ALT_USB_HOST_HCTSIZ9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA9_ADDR ALT_USB_HOST_HCDMA9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB9 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB9_ADDR ALT_USB_HOST_HCDMAB9_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR10_ADDR ALT_USB_HOST_HCCHAR10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT10_ADDR ALT_USB_HOST_HCSPLT10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT10_ADDR ALT_USB_HOST_HCINT10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK10_ADDR ALT_USB_HOST_HCINTMSK10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ10_ADDR ALT_USB_HOST_HCTSIZ10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA10_ADDR ALT_USB_HOST_HCDMA10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB10 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB10_ADDR ALT_USB_HOST_HCDMAB10_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR11_ADDR ALT_USB_HOST_HCCHAR11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT11_ADDR ALT_USB_HOST_HCSPLT11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT11_ADDR ALT_USB_HOST_HCINT11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK11_ADDR ALT_USB_HOST_HCINTMSK11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ11_ADDR ALT_USB_HOST_HCTSIZ11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA11_ADDR ALT_USB_HOST_HCDMA11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB11 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB11_ADDR ALT_USB_HOST_HCDMAB11_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR12_ADDR ALT_USB_HOST_HCCHAR12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT12_ADDR ALT_USB_HOST_HCSPLT12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT12_ADDR ALT_USB_HOST_HCINT12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK12_ADDR ALT_USB_HOST_HCINTMSK12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ12_ADDR ALT_USB_HOST_HCTSIZ12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA12_ADDR ALT_USB_HOST_HCDMA12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB12 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB12_ADDR ALT_USB_HOST_HCDMAB12_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR13_ADDR ALT_USB_HOST_HCCHAR13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT13_ADDR ALT_USB_HOST_HCSPLT13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT13_ADDR ALT_USB_HOST_HCINT13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK13_ADDR ALT_USB_HOST_HCINTMSK13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ13_ADDR ALT_USB_HOST_HCTSIZ13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA13_ADDR ALT_USB_HOST_HCDMA13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB13 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB13_ADDR ALT_USB_HOST_HCDMAB13_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR14_ADDR ALT_USB_HOST_HCCHAR14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT14_ADDR ALT_USB_HOST_HCSPLT14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT14_ADDR ALT_USB_HOST_HCINT14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK14_ADDR ALT_USB_HOST_HCINTMSK14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ14_ADDR ALT_USB_HOST_HCTSIZ14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA14_ADDR ALT_USB_HOST_HCDMA14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB14 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB14_ADDR ALT_USB_HOST_HCDMAB14_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCCHAR15_ADDR ALT_USB_HOST_HCCHAR15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCSPLT15_ADDR ALT_USB_HOST_HCSPLT15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINT15_ADDR ALT_USB_HOST_HCINT15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCINTMSK15_ADDR ALT_USB_HOST_HCINTMSK15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCTSIZ15_ADDR ALT_USB_HOST_HCTSIZ15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMA15_ADDR ALT_USB_HOST_HCDMA15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB15 register for the ALT_USB0_HOSTGRP instance. */ +#define ALT_USB0_HOST_HCDMAB15_ADDR ALT_USB_HOST_HCDMAB15_ADDR(ALT_USB0_HOSTGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_OFST 0x400 +/* The start address of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_HOSTGRP_OFST)) +/* The lower bound address range of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_LB_ADDR ALT_USB0_HOSTGRP_ADDR +/* The upper bound address range of the ALT_USB0_HOSTGRP component. */ +#define ALT_USB0_HOSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_HOSTGRP_ADDR) + 0x2fc) - 1)) + + +/* + * Register Group Instance : devgrp + * + * Instance devgrp of register group ALT_USB_DEV. + * + * + */ +/* The address of the ALT_USB_DEV_DCFG register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DCFG_ADDR ALT_USB_DEV_DCFG_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DCTL register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DCTL_ADDR ALT_USB_DEV_DCTL_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DSTS register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DSTS_ADDR ALT_USB_DEV_DSTS_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPMSK_ADDR ALT_USB_DEV_DIEPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPMSK_ADDR ALT_USB_DEV_DOEPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINT register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DAINT_ADDR ALT_USB_DEV_DAINT_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINTMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DAINTMSK_ADDR ALT_USB_DEV_DAINTMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSDIS register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DVBUSDIS_ADDR ALT_USB_DEV_DVBUSDIS_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSPULSE register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DVBUSPULSE_ADDR ALT_USB_DEV_DVBUSPULSE_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTHRCTL register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTHRCTL_ADDR ALT_USB_DEV_DTHRCTL_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPEMPMSK register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPEMPMSK_ADDR ALT_USB_DEV_DIEPEMPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL0_ADDR ALT_USB_DEV_DIEPCTL0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT0_ADDR ALT_USB_DEV_DIEPINT0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ0_ADDR ALT_USB_DEV_DIEPTSIZ0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA0_ADDR ALT_USB_DEV_DIEPDMA0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS0_ADDR ALT_USB_DEV_DTXFSTS0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB0_ADDR ALT_USB_DEV_DIEPDMAB0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL1_ADDR ALT_USB_DEV_DIEPCTL1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT1_ADDR ALT_USB_DEV_DIEPINT1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ1_ADDR ALT_USB_DEV_DIEPTSIZ1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA1_ADDR ALT_USB_DEV_DIEPDMA1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS1_ADDR ALT_USB_DEV_DTXFSTS1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB1_ADDR ALT_USB_DEV_DIEPDMAB1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL2_ADDR ALT_USB_DEV_DIEPCTL2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT2_ADDR ALT_USB_DEV_DIEPINT2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ2_ADDR ALT_USB_DEV_DIEPTSIZ2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA2_ADDR ALT_USB_DEV_DIEPDMA2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS2_ADDR ALT_USB_DEV_DTXFSTS2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB2_ADDR ALT_USB_DEV_DIEPDMAB2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL3_ADDR ALT_USB_DEV_DIEPCTL3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT3_ADDR ALT_USB_DEV_DIEPINT3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ3_ADDR ALT_USB_DEV_DIEPTSIZ3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA3_ADDR ALT_USB_DEV_DIEPDMA3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS3_ADDR ALT_USB_DEV_DTXFSTS3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB3_ADDR ALT_USB_DEV_DIEPDMAB3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL4_ADDR ALT_USB_DEV_DIEPCTL4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT4_ADDR ALT_USB_DEV_DIEPINT4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ4_ADDR ALT_USB_DEV_DIEPTSIZ4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA4_ADDR ALT_USB_DEV_DIEPDMA4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS4_ADDR ALT_USB_DEV_DTXFSTS4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB4_ADDR ALT_USB_DEV_DIEPDMAB4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL5_ADDR ALT_USB_DEV_DIEPCTL5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT5_ADDR ALT_USB_DEV_DIEPINT5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ5_ADDR ALT_USB_DEV_DIEPTSIZ5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA5_ADDR ALT_USB_DEV_DIEPDMA5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS5_ADDR ALT_USB_DEV_DTXFSTS5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB5_ADDR ALT_USB_DEV_DIEPDMAB5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL6_ADDR ALT_USB_DEV_DIEPCTL6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT6_ADDR ALT_USB_DEV_DIEPINT6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ6_ADDR ALT_USB_DEV_DIEPTSIZ6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA6_ADDR ALT_USB_DEV_DIEPDMA6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS6_ADDR ALT_USB_DEV_DTXFSTS6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB6_ADDR ALT_USB_DEV_DIEPDMAB6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL7_ADDR ALT_USB_DEV_DIEPCTL7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT7_ADDR ALT_USB_DEV_DIEPINT7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ7_ADDR ALT_USB_DEV_DIEPTSIZ7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA7_ADDR ALT_USB_DEV_DIEPDMA7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS7_ADDR ALT_USB_DEV_DTXFSTS7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB7_ADDR ALT_USB_DEV_DIEPDMAB7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL8_ADDR ALT_USB_DEV_DIEPCTL8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT8_ADDR ALT_USB_DEV_DIEPINT8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ8_ADDR ALT_USB_DEV_DIEPTSIZ8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA8_ADDR ALT_USB_DEV_DIEPDMA8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS8_ADDR ALT_USB_DEV_DTXFSTS8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB8_ADDR ALT_USB_DEV_DIEPDMAB8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL9_ADDR ALT_USB_DEV_DIEPCTL9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT9_ADDR ALT_USB_DEV_DIEPINT9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ9_ADDR ALT_USB_DEV_DIEPTSIZ9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA9_ADDR ALT_USB_DEV_DIEPDMA9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS9_ADDR ALT_USB_DEV_DTXFSTS9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB9_ADDR ALT_USB_DEV_DIEPDMAB9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL10_ADDR ALT_USB_DEV_DIEPCTL10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT10_ADDR ALT_USB_DEV_DIEPINT10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ10_ADDR ALT_USB_DEV_DIEPTSIZ10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA10_ADDR ALT_USB_DEV_DIEPDMA10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS10_ADDR ALT_USB_DEV_DTXFSTS10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB10_ADDR ALT_USB_DEV_DIEPDMAB10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL11_ADDR ALT_USB_DEV_DIEPCTL11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT11_ADDR ALT_USB_DEV_DIEPINT11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ11_ADDR ALT_USB_DEV_DIEPTSIZ11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA11_ADDR ALT_USB_DEV_DIEPDMA11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS11_ADDR ALT_USB_DEV_DTXFSTS11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB11_ADDR ALT_USB_DEV_DIEPDMAB11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL12_ADDR ALT_USB_DEV_DIEPCTL12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT12_ADDR ALT_USB_DEV_DIEPINT12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ12_ADDR ALT_USB_DEV_DIEPTSIZ12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA12_ADDR ALT_USB_DEV_DIEPDMA12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS12_ADDR ALT_USB_DEV_DTXFSTS12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB12_ADDR ALT_USB_DEV_DIEPDMAB12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL13_ADDR ALT_USB_DEV_DIEPCTL13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT13_ADDR ALT_USB_DEV_DIEPINT13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ13_ADDR ALT_USB_DEV_DIEPTSIZ13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA13_ADDR ALT_USB_DEV_DIEPDMA13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS13_ADDR ALT_USB_DEV_DTXFSTS13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB13_ADDR ALT_USB_DEV_DIEPDMAB13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL14_ADDR ALT_USB_DEV_DIEPCTL14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT14_ADDR ALT_USB_DEV_DIEPINT14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ14_ADDR ALT_USB_DEV_DIEPTSIZ14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA14_ADDR ALT_USB_DEV_DIEPDMA14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS14_ADDR ALT_USB_DEV_DTXFSTS14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB14_ADDR ALT_USB_DEV_DIEPDMAB14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPCTL15_ADDR ALT_USB_DEV_DIEPCTL15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPINT15_ADDR ALT_USB_DEV_DIEPINT15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPTSIZ15_ADDR ALT_USB_DEV_DIEPTSIZ15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMA15_ADDR ALT_USB_DEV_DIEPDMA15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DTXFSTS15_ADDR ALT_USB_DEV_DTXFSTS15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DIEPDMAB15_ADDR ALT_USB_DEV_DIEPDMAB15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL0_ADDR ALT_USB_DEV_DOEPCTL0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT0_ADDR ALT_USB_DEV_DOEPINT0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ0_ADDR ALT_USB_DEV_DOEPTSIZ0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA0_ADDR ALT_USB_DEV_DOEPDMA0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB0 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB0_ADDR ALT_USB_DEV_DOEPDMAB0_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL1_ADDR ALT_USB_DEV_DOEPCTL1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT1_ADDR ALT_USB_DEV_DOEPINT1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ1_ADDR ALT_USB_DEV_DOEPTSIZ1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA1_ADDR ALT_USB_DEV_DOEPDMA1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB1 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB1_ADDR ALT_USB_DEV_DOEPDMAB1_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL2_ADDR ALT_USB_DEV_DOEPCTL2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT2_ADDR ALT_USB_DEV_DOEPINT2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ2_ADDR ALT_USB_DEV_DOEPTSIZ2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA2_ADDR ALT_USB_DEV_DOEPDMA2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB2 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB2_ADDR ALT_USB_DEV_DOEPDMAB2_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL3_ADDR ALT_USB_DEV_DOEPCTL3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT3_ADDR ALT_USB_DEV_DOEPINT3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ3_ADDR ALT_USB_DEV_DOEPTSIZ3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA3_ADDR ALT_USB_DEV_DOEPDMA3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB3 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB3_ADDR ALT_USB_DEV_DOEPDMAB3_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL4_ADDR ALT_USB_DEV_DOEPCTL4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT4_ADDR ALT_USB_DEV_DOEPINT4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ4_ADDR ALT_USB_DEV_DOEPTSIZ4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA4_ADDR ALT_USB_DEV_DOEPDMA4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB4 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB4_ADDR ALT_USB_DEV_DOEPDMAB4_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL5_ADDR ALT_USB_DEV_DOEPCTL5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT5_ADDR ALT_USB_DEV_DOEPINT5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ5_ADDR ALT_USB_DEV_DOEPTSIZ5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA5_ADDR ALT_USB_DEV_DOEPDMA5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB5 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB5_ADDR ALT_USB_DEV_DOEPDMAB5_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL6_ADDR ALT_USB_DEV_DOEPCTL6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT6_ADDR ALT_USB_DEV_DOEPINT6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ6_ADDR ALT_USB_DEV_DOEPTSIZ6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA6_ADDR ALT_USB_DEV_DOEPDMA6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB6 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB6_ADDR ALT_USB_DEV_DOEPDMAB6_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL7_ADDR ALT_USB_DEV_DOEPCTL7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT7_ADDR ALT_USB_DEV_DOEPINT7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ7_ADDR ALT_USB_DEV_DOEPTSIZ7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA7_ADDR ALT_USB_DEV_DOEPDMA7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB7 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB7_ADDR ALT_USB_DEV_DOEPDMAB7_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL8_ADDR ALT_USB_DEV_DOEPCTL8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT8_ADDR ALT_USB_DEV_DOEPINT8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ8_ADDR ALT_USB_DEV_DOEPTSIZ8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA8_ADDR ALT_USB_DEV_DOEPDMA8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB8 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB8_ADDR ALT_USB_DEV_DOEPDMAB8_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL9_ADDR ALT_USB_DEV_DOEPCTL9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT9_ADDR ALT_USB_DEV_DOEPINT9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ9_ADDR ALT_USB_DEV_DOEPTSIZ9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA9_ADDR ALT_USB_DEV_DOEPDMA9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB9 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB9_ADDR ALT_USB_DEV_DOEPDMAB9_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL10_ADDR ALT_USB_DEV_DOEPCTL10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT10_ADDR ALT_USB_DEV_DOEPINT10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ10_ADDR ALT_USB_DEV_DOEPTSIZ10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA10_ADDR ALT_USB_DEV_DOEPDMA10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB10 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB10_ADDR ALT_USB_DEV_DOEPDMAB10_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL11_ADDR ALT_USB_DEV_DOEPCTL11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT11_ADDR ALT_USB_DEV_DOEPINT11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ11_ADDR ALT_USB_DEV_DOEPTSIZ11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA11_ADDR ALT_USB_DEV_DOEPDMA11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB11 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB11_ADDR ALT_USB_DEV_DOEPDMAB11_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL12_ADDR ALT_USB_DEV_DOEPCTL12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT12_ADDR ALT_USB_DEV_DOEPINT12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ12_ADDR ALT_USB_DEV_DOEPTSIZ12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA12_ADDR ALT_USB_DEV_DOEPDMA12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB12 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB12_ADDR ALT_USB_DEV_DOEPDMAB12_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL13_ADDR ALT_USB_DEV_DOEPCTL13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT13_ADDR ALT_USB_DEV_DOEPINT13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ13_ADDR ALT_USB_DEV_DOEPTSIZ13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA13_ADDR ALT_USB_DEV_DOEPDMA13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB13 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB13_ADDR ALT_USB_DEV_DOEPDMAB13_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL14_ADDR ALT_USB_DEV_DOEPCTL14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT14_ADDR ALT_USB_DEV_DOEPINT14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ14_ADDR ALT_USB_DEV_DOEPTSIZ14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA14_ADDR ALT_USB_DEV_DOEPDMA14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB14 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB14_ADDR ALT_USB_DEV_DOEPDMAB14_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPCTL15_ADDR ALT_USB_DEV_DOEPCTL15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPINT15_ADDR ALT_USB_DEV_DOEPINT15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPTSIZ15_ADDR ALT_USB_DEV_DOEPTSIZ15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMA15_ADDR ALT_USB_DEV_DOEPDMA15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB15 register for the ALT_USB0_DEVGRP instance. */ +#define ALT_USB0_DEV_DOEPDMAB15_ADDR ALT_USB_DEV_DOEPDMAB15_ADDR(ALT_USB0_DEVGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_OFST 0x800 +/* The start address of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_DEVGRP_OFST)) +/* The lower bound address range of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_LB_ADDR ALT_USB0_DEVGRP_ADDR +/* The upper bound address range of the ALT_USB0_DEVGRP component. */ +#define ALT_USB0_DEVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_DEVGRP_ADDR) + 0x500) - 1)) + + +/* + * Register Group Instance : pwrclkgrp + * + * Instance pwrclkgrp of register group ALT_USB_PWRCLK. + * + * + */ +/* The address of the ALT_USB_PWRCLK_PCGCCTL register for the ALT_USB0_PWRCLKGRP instance. */ +#define ALT_USB0_PWRCLK_PCGCCTL_ADDR ALT_USB_PWRCLK_PCGCCTL_ADDR(ALT_USB0_PWRCLKGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_OFST 0xe00 +/* The start address of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_PWRCLKGRP_OFST)) +/* The lower bound address range of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_LB_ADDR ALT_USB0_PWRCLKGRP_ADDR +/* The upper bound address range of the ALT_USB0_PWRCLKGRP component. */ +#define ALT_USB0_PWRCLKGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_PWRCLKGRP_ADDR) + 0x4) - 1)) + + +/* The base address byte offset for the start of the ALT_USB0 component. */ +#define ALT_USB0_OFST 0xffb00000 +/* The start address of the ALT_USB0 component. */ +#define ALT_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_USB0_OFST)) +/* The lower bound address range of the ALT_USB0 component. */ +#define ALT_USB0_LB_ADDR ALT_USB0_ADDR +/* The upper bound address range of the ALT_USB0 component. */ +#define ALT_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_ADDR) + 0x40000) - 1)) + + +/* + * Component Instance : usb1 + * + * Instance usb1 of component ALT_USB. + * + * + */ +/* + * Register Group Instance : globgrp + * + * Instance globgrp of register group ALT_USB_GLOB. + * + * + */ +/* The address of the ALT_USB_GLOB_GOTGCTL register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GOTGCTL_ADDR ALT_USB_GLOB_GOTGCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GOTGINT register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GOTGINT_ADDR ALT_USB_GLOB_GOTGINT_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GAHBCFG register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GAHBCFG_ADDR ALT_USB_GLOB_GAHBCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUSBCFG register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GUSBCFG_ADDR ALT_USB_GLOB_GUSBCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRSTCTL register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRSTCTL_ADDR ALT_USB_GLOB_GRSTCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTSTS register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GINTSTS_ADDR ALT_USB_GLOB_GINTSTS_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GINTMSK register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GINTMSK_ADDR ALT_USB_GLOB_GINTMSK_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSR register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRXSTSR_ADDR ALT_USB_GLOB_GRXSTSR_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXSTSP register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRXSTSP_ADDR ALT_USB_GLOB_GRXSTSP_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GRXFSIZ register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GRXFSIZ_ADDR ALT_USB_GLOB_GRXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXFSIZ register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GNPTXFSIZ_ADDR ALT_USB_GLOB_GNPTXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GNPTXSTS register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GNPTXSTS_ADDR ALT_USB_GLOB_GNPTXSTS_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GPVNDCTL register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GPVNDCTL_ADDR ALT_USB_GLOB_GPVNDCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GGPIO register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GGPIO_ADDR ALT_USB_GLOB_GGPIO_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GUID register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GUID_ADDR ALT_USB_GLOB_GUID_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GSNPSID register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GSNPSID_ADDR ALT_USB_GLOB_GSNPSID_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG1 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG1_ADDR ALT_USB_GLOB_GHWCFG1_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG2 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG2_ADDR ALT_USB_GLOB_GHWCFG2_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG3 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG3_ADDR ALT_USB_GLOB_GHWCFG3_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GHWCFG4 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GHWCFG4_ADDR ALT_USB_GLOB_GHWCFG4_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_GDFIFOCFG register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_GDFIFOCFG_ADDR ALT_USB_GLOB_GDFIFOCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_HPTXFSIZ register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_HPTXFSIZ_ADDR ALT_USB_GLOB_HPTXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF1 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF1_ADDR ALT_USB_GLOB_DIEPTXF1_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF2 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF2_ADDR ALT_USB_GLOB_DIEPTXF2_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF3 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF3_ADDR ALT_USB_GLOB_DIEPTXF3_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF4 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF4_ADDR ALT_USB_GLOB_DIEPTXF4_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF5 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF5_ADDR ALT_USB_GLOB_DIEPTXF5_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF6 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF6_ADDR ALT_USB_GLOB_DIEPTXF6_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF7 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF7_ADDR ALT_USB_GLOB_DIEPTXF7_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF8 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF8_ADDR ALT_USB_GLOB_DIEPTXF8_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF9 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF9_ADDR ALT_USB_GLOB_DIEPTXF9_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF10 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF10_ADDR ALT_USB_GLOB_DIEPTXF10_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF11 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF11_ADDR ALT_USB_GLOB_DIEPTXF11_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF12 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF12_ADDR ALT_USB_GLOB_DIEPTXF12_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF13 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF13_ADDR ALT_USB_GLOB_DIEPTXF13_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF14 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF14_ADDR ALT_USB_GLOB_DIEPTXF14_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The address of the ALT_USB_GLOB_DIEPTXF15 register for the ALT_USB1_GLOBGRP instance. */ +#define ALT_USB1_GLOB_DIEPTXF15_ADDR ALT_USB_GLOB_DIEPTXF15_ADDR(ALT_USB1_GLOBGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_OFST 0x0 +/* The start address of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_GLOBGRP_OFST)) +/* The lower bound address range of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_LB_ADDR ALT_USB1_GLOBGRP_ADDR +/* The upper bound address range of the ALT_USB1_GLOBGRP component. */ +#define ALT_USB1_GLOBGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_GLOBGRP_ADDR) + 0x140) - 1)) + + +/* + * Register Group Instance : hostgrp + * + * Instance hostgrp of register group ALT_USB_HOST. + * + * + */ +/* The address of the ALT_USB_HOST_HCFG register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCFG_ADDR ALT_USB_HOST_HCFG_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFIR register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HFIR_ADDR ALT_USB_HOST_HFIR_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFNUM register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HFNUM_ADDR ALT_USB_HOST_HFNUM_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPTXSTS register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HPTXSTS_ADDR ALT_USB_HOST_HPTXSTS_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINT register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HAINT_ADDR ALT_USB_HOST_HAINT_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HAINTMSK register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HAINTMSK_ADDR ALT_USB_HOST_HAINTMSK_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HFLBADDR register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HFLBADDR_ADDR ALT_USB_HOST_HFLBADDR_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HPRT register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HPRT_ADDR ALT_USB_HOST_HPRT_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR0_ADDR ALT_USB_HOST_HCCHAR0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT0_ADDR ALT_USB_HOST_HCSPLT0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT0_ADDR ALT_USB_HOST_HCINT0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK0_ADDR ALT_USB_HOST_HCINTMSK0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ0_ADDR ALT_USB_HOST_HCTSIZ0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA0_ADDR ALT_USB_HOST_HCDMA0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB0 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB0_ADDR ALT_USB_HOST_HCDMAB0_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR1_ADDR ALT_USB_HOST_HCCHAR1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT1_ADDR ALT_USB_HOST_HCSPLT1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT1_ADDR ALT_USB_HOST_HCINT1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK1_ADDR ALT_USB_HOST_HCINTMSK1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ1_ADDR ALT_USB_HOST_HCTSIZ1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA1_ADDR ALT_USB_HOST_HCDMA1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB1 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB1_ADDR ALT_USB_HOST_HCDMAB1_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR2_ADDR ALT_USB_HOST_HCCHAR2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT2_ADDR ALT_USB_HOST_HCSPLT2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT2_ADDR ALT_USB_HOST_HCINT2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK2_ADDR ALT_USB_HOST_HCINTMSK2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ2_ADDR ALT_USB_HOST_HCTSIZ2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA2_ADDR ALT_USB_HOST_HCDMA2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB2 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB2_ADDR ALT_USB_HOST_HCDMAB2_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR3_ADDR ALT_USB_HOST_HCCHAR3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT3_ADDR ALT_USB_HOST_HCSPLT3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT3_ADDR ALT_USB_HOST_HCINT3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK3_ADDR ALT_USB_HOST_HCINTMSK3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ3_ADDR ALT_USB_HOST_HCTSIZ3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA3_ADDR ALT_USB_HOST_HCDMA3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB3 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB3_ADDR ALT_USB_HOST_HCDMAB3_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR4_ADDR ALT_USB_HOST_HCCHAR4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT4_ADDR ALT_USB_HOST_HCSPLT4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT4_ADDR ALT_USB_HOST_HCINT4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK4_ADDR ALT_USB_HOST_HCINTMSK4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ4_ADDR ALT_USB_HOST_HCTSIZ4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA4_ADDR ALT_USB_HOST_HCDMA4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB4 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB4_ADDR ALT_USB_HOST_HCDMAB4_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR5_ADDR ALT_USB_HOST_HCCHAR5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT5_ADDR ALT_USB_HOST_HCSPLT5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT5_ADDR ALT_USB_HOST_HCINT5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK5_ADDR ALT_USB_HOST_HCINTMSK5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ5_ADDR ALT_USB_HOST_HCTSIZ5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA5_ADDR ALT_USB_HOST_HCDMA5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB5 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB5_ADDR ALT_USB_HOST_HCDMAB5_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR6_ADDR ALT_USB_HOST_HCCHAR6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT6_ADDR ALT_USB_HOST_HCSPLT6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT6_ADDR ALT_USB_HOST_HCINT6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK6_ADDR ALT_USB_HOST_HCINTMSK6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ6_ADDR ALT_USB_HOST_HCTSIZ6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA6_ADDR ALT_USB_HOST_HCDMA6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB6 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB6_ADDR ALT_USB_HOST_HCDMAB6_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR7_ADDR ALT_USB_HOST_HCCHAR7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT7_ADDR ALT_USB_HOST_HCSPLT7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT7_ADDR ALT_USB_HOST_HCINT7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK7_ADDR ALT_USB_HOST_HCINTMSK7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ7_ADDR ALT_USB_HOST_HCTSIZ7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA7_ADDR ALT_USB_HOST_HCDMA7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB7 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB7_ADDR ALT_USB_HOST_HCDMAB7_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR8_ADDR ALT_USB_HOST_HCCHAR8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT8_ADDR ALT_USB_HOST_HCSPLT8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT8_ADDR ALT_USB_HOST_HCINT8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK8_ADDR ALT_USB_HOST_HCINTMSK8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ8_ADDR ALT_USB_HOST_HCTSIZ8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA8_ADDR ALT_USB_HOST_HCDMA8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB8 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB8_ADDR ALT_USB_HOST_HCDMAB8_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR9_ADDR ALT_USB_HOST_HCCHAR9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT9_ADDR ALT_USB_HOST_HCSPLT9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT9_ADDR ALT_USB_HOST_HCINT9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK9_ADDR ALT_USB_HOST_HCINTMSK9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ9_ADDR ALT_USB_HOST_HCTSIZ9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA9_ADDR ALT_USB_HOST_HCDMA9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB9 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB9_ADDR ALT_USB_HOST_HCDMAB9_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR10_ADDR ALT_USB_HOST_HCCHAR10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT10_ADDR ALT_USB_HOST_HCSPLT10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT10_ADDR ALT_USB_HOST_HCINT10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK10_ADDR ALT_USB_HOST_HCINTMSK10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ10_ADDR ALT_USB_HOST_HCTSIZ10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA10_ADDR ALT_USB_HOST_HCDMA10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB10 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB10_ADDR ALT_USB_HOST_HCDMAB10_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR11_ADDR ALT_USB_HOST_HCCHAR11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT11_ADDR ALT_USB_HOST_HCSPLT11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT11_ADDR ALT_USB_HOST_HCINT11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK11_ADDR ALT_USB_HOST_HCINTMSK11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ11_ADDR ALT_USB_HOST_HCTSIZ11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA11_ADDR ALT_USB_HOST_HCDMA11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB11 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB11_ADDR ALT_USB_HOST_HCDMAB11_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR12_ADDR ALT_USB_HOST_HCCHAR12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT12_ADDR ALT_USB_HOST_HCSPLT12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT12_ADDR ALT_USB_HOST_HCINT12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK12_ADDR ALT_USB_HOST_HCINTMSK12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ12_ADDR ALT_USB_HOST_HCTSIZ12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA12_ADDR ALT_USB_HOST_HCDMA12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB12 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB12_ADDR ALT_USB_HOST_HCDMAB12_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR13_ADDR ALT_USB_HOST_HCCHAR13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT13_ADDR ALT_USB_HOST_HCSPLT13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT13_ADDR ALT_USB_HOST_HCINT13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK13_ADDR ALT_USB_HOST_HCINTMSK13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ13_ADDR ALT_USB_HOST_HCTSIZ13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA13_ADDR ALT_USB_HOST_HCDMA13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB13 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB13_ADDR ALT_USB_HOST_HCDMAB13_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR14_ADDR ALT_USB_HOST_HCCHAR14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT14_ADDR ALT_USB_HOST_HCSPLT14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT14_ADDR ALT_USB_HOST_HCINT14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK14_ADDR ALT_USB_HOST_HCINTMSK14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ14_ADDR ALT_USB_HOST_HCTSIZ14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA14_ADDR ALT_USB_HOST_HCDMA14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB14 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB14_ADDR ALT_USB_HOST_HCDMAB14_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCCHAR15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCCHAR15_ADDR ALT_USB_HOST_HCCHAR15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCSPLT15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCSPLT15_ADDR ALT_USB_HOST_HCSPLT15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINT15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINT15_ADDR ALT_USB_HOST_HCINT15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCINTMSK15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCINTMSK15_ADDR ALT_USB_HOST_HCINTMSK15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCTSIZ15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCTSIZ15_ADDR ALT_USB_HOST_HCTSIZ15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMA15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMA15_ADDR ALT_USB_HOST_HCDMA15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The address of the ALT_USB_HOST_HCDMAB15 register for the ALT_USB1_HOSTGRP instance. */ +#define ALT_USB1_HOST_HCDMAB15_ADDR ALT_USB_HOST_HCDMAB15_ADDR(ALT_USB1_HOSTGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_OFST 0x400 +/* The start address of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_HOSTGRP_OFST)) +/* The lower bound address range of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_LB_ADDR ALT_USB1_HOSTGRP_ADDR +/* The upper bound address range of the ALT_USB1_HOSTGRP component. */ +#define ALT_USB1_HOSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_HOSTGRP_ADDR) + 0x2fc) - 1)) + + +/* + * Register Group Instance : devgrp + * + * Instance devgrp of register group ALT_USB_DEV. + * + * + */ +/* The address of the ALT_USB_DEV_DCFG register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DCFG_ADDR ALT_USB_DEV_DCFG_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DCTL register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DCTL_ADDR ALT_USB_DEV_DCTL_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DSTS register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DSTS_ADDR ALT_USB_DEV_DSTS_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPMSK_ADDR ALT_USB_DEV_DIEPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPMSK_ADDR ALT_USB_DEV_DOEPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINT register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DAINT_ADDR ALT_USB_DEV_DAINT_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DAINTMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DAINTMSK_ADDR ALT_USB_DEV_DAINTMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSDIS register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DVBUSDIS_ADDR ALT_USB_DEV_DVBUSDIS_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DVBUSPULSE register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DVBUSPULSE_ADDR ALT_USB_DEV_DVBUSPULSE_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTHRCTL register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTHRCTL_ADDR ALT_USB_DEV_DTHRCTL_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPEMPMSK register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPEMPMSK_ADDR ALT_USB_DEV_DIEPEMPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL0_ADDR ALT_USB_DEV_DIEPCTL0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT0_ADDR ALT_USB_DEV_DIEPINT0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ0_ADDR ALT_USB_DEV_DIEPTSIZ0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA0_ADDR ALT_USB_DEV_DIEPDMA0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS0_ADDR ALT_USB_DEV_DTXFSTS0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB0_ADDR ALT_USB_DEV_DIEPDMAB0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL1_ADDR ALT_USB_DEV_DIEPCTL1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT1_ADDR ALT_USB_DEV_DIEPINT1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ1_ADDR ALT_USB_DEV_DIEPTSIZ1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA1_ADDR ALT_USB_DEV_DIEPDMA1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS1_ADDR ALT_USB_DEV_DTXFSTS1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB1_ADDR ALT_USB_DEV_DIEPDMAB1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL2_ADDR ALT_USB_DEV_DIEPCTL2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT2_ADDR ALT_USB_DEV_DIEPINT2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ2_ADDR ALT_USB_DEV_DIEPTSIZ2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA2_ADDR ALT_USB_DEV_DIEPDMA2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS2_ADDR ALT_USB_DEV_DTXFSTS2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB2_ADDR ALT_USB_DEV_DIEPDMAB2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL3_ADDR ALT_USB_DEV_DIEPCTL3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT3_ADDR ALT_USB_DEV_DIEPINT3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ3_ADDR ALT_USB_DEV_DIEPTSIZ3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA3_ADDR ALT_USB_DEV_DIEPDMA3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS3_ADDR ALT_USB_DEV_DTXFSTS3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB3_ADDR ALT_USB_DEV_DIEPDMAB3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL4_ADDR ALT_USB_DEV_DIEPCTL4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT4_ADDR ALT_USB_DEV_DIEPINT4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ4_ADDR ALT_USB_DEV_DIEPTSIZ4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA4_ADDR ALT_USB_DEV_DIEPDMA4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS4_ADDR ALT_USB_DEV_DTXFSTS4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB4_ADDR ALT_USB_DEV_DIEPDMAB4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL5_ADDR ALT_USB_DEV_DIEPCTL5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT5_ADDR ALT_USB_DEV_DIEPINT5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ5_ADDR ALT_USB_DEV_DIEPTSIZ5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA5_ADDR ALT_USB_DEV_DIEPDMA5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS5_ADDR ALT_USB_DEV_DTXFSTS5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB5_ADDR ALT_USB_DEV_DIEPDMAB5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL6_ADDR ALT_USB_DEV_DIEPCTL6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT6_ADDR ALT_USB_DEV_DIEPINT6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ6_ADDR ALT_USB_DEV_DIEPTSIZ6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA6_ADDR ALT_USB_DEV_DIEPDMA6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS6_ADDR ALT_USB_DEV_DTXFSTS6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB6_ADDR ALT_USB_DEV_DIEPDMAB6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL7_ADDR ALT_USB_DEV_DIEPCTL7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT7_ADDR ALT_USB_DEV_DIEPINT7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ7_ADDR ALT_USB_DEV_DIEPTSIZ7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA7_ADDR ALT_USB_DEV_DIEPDMA7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS7_ADDR ALT_USB_DEV_DTXFSTS7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB7_ADDR ALT_USB_DEV_DIEPDMAB7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL8_ADDR ALT_USB_DEV_DIEPCTL8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT8_ADDR ALT_USB_DEV_DIEPINT8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ8_ADDR ALT_USB_DEV_DIEPTSIZ8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA8_ADDR ALT_USB_DEV_DIEPDMA8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS8_ADDR ALT_USB_DEV_DTXFSTS8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB8_ADDR ALT_USB_DEV_DIEPDMAB8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL9_ADDR ALT_USB_DEV_DIEPCTL9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT9_ADDR ALT_USB_DEV_DIEPINT9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ9_ADDR ALT_USB_DEV_DIEPTSIZ9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA9_ADDR ALT_USB_DEV_DIEPDMA9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS9_ADDR ALT_USB_DEV_DTXFSTS9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB9_ADDR ALT_USB_DEV_DIEPDMAB9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL10_ADDR ALT_USB_DEV_DIEPCTL10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT10_ADDR ALT_USB_DEV_DIEPINT10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ10_ADDR ALT_USB_DEV_DIEPTSIZ10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA10_ADDR ALT_USB_DEV_DIEPDMA10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS10_ADDR ALT_USB_DEV_DTXFSTS10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB10_ADDR ALT_USB_DEV_DIEPDMAB10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL11_ADDR ALT_USB_DEV_DIEPCTL11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT11_ADDR ALT_USB_DEV_DIEPINT11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ11_ADDR ALT_USB_DEV_DIEPTSIZ11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA11_ADDR ALT_USB_DEV_DIEPDMA11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS11_ADDR ALT_USB_DEV_DTXFSTS11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB11_ADDR ALT_USB_DEV_DIEPDMAB11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL12_ADDR ALT_USB_DEV_DIEPCTL12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT12_ADDR ALT_USB_DEV_DIEPINT12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ12_ADDR ALT_USB_DEV_DIEPTSIZ12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA12_ADDR ALT_USB_DEV_DIEPDMA12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS12_ADDR ALT_USB_DEV_DTXFSTS12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB12_ADDR ALT_USB_DEV_DIEPDMAB12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL13_ADDR ALT_USB_DEV_DIEPCTL13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT13_ADDR ALT_USB_DEV_DIEPINT13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ13_ADDR ALT_USB_DEV_DIEPTSIZ13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA13_ADDR ALT_USB_DEV_DIEPDMA13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS13_ADDR ALT_USB_DEV_DTXFSTS13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB13_ADDR ALT_USB_DEV_DIEPDMAB13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL14_ADDR ALT_USB_DEV_DIEPCTL14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT14_ADDR ALT_USB_DEV_DIEPINT14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ14_ADDR ALT_USB_DEV_DIEPTSIZ14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA14_ADDR ALT_USB_DEV_DIEPDMA14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS14_ADDR ALT_USB_DEV_DTXFSTS14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB14_ADDR ALT_USB_DEV_DIEPDMAB14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPCTL15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPCTL15_ADDR ALT_USB_DEV_DIEPCTL15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPINT15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPINT15_ADDR ALT_USB_DEV_DIEPINT15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPTSIZ15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPTSIZ15_ADDR ALT_USB_DEV_DIEPTSIZ15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMA15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMA15_ADDR ALT_USB_DEV_DIEPDMA15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DTXFSTS15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DTXFSTS15_ADDR ALT_USB_DEV_DTXFSTS15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DIEPDMAB15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DIEPDMAB15_ADDR ALT_USB_DEV_DIEPDMAB15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL0_ADDR ALT_USB_DEV_DOEPCTL0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT0_ADDR ALT_USB_DEV_DOEPINT0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ0_ADDR ALT_USB_DEV_DOEPTSIZ0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA0_ADDR ALT_USB_DEV_DOEPDMA0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB0 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB0_ADDR ALT_USB_DEV_DOEPDMAB0_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL1_ADDR ALT_USB_DEV_DOEPCTL1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT1_ADDR ALT_USB_DEV_DOEPINT1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ1_ADDR ALT_USB_DEV_DOEPTSIZ1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA1_ADDR ALT_USB_DEV_DOEPDMA1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB1 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB1_ADDR ALT_USB_DEV_DOEPDMAB1_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL2_ADDR ALT_USB_DEV_DOEPCTL2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT2_ADDR ALT_USB_DEV_DOEPINT2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ2_ADDR ALT_USB_DEV_DOEPTSIZ2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA2_ADDR ALT_USB_DEV_DOEPDMA2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB2 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB2_ADDR ALT_USB_DEV_DOEPDMAB2_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL3_ADDR ALT_USB_DEV_DOEPCTL3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT3_ADDR ALT_USB_DEV_DOEPINT3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ3_ADDR ALT_USB_DEV_DOEPTSIZ3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA3_ADDR ALT_USB_DEV_DOEPDMA3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB3 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB3_ADDR ALT_USB_DEV_DOEPDMAB3_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL4_ADDR ALT_USB_DEV_DOEPCTL4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT4_ADDR ALT_USB_DEV_DOEPINT4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ4_ADDR ALT_USB_DEV_DOEPTSIZ4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA4_ADDR ALT_USB_DEV_DOEPDMA4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB4 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB4_ADDR ALT_USB_DEV_DOEPDMAB4_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL5_ADDR ALT_USB_DEV_DOEPCTL5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT5_ADDR ALT_USB_DEV_DOEPINT5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ5_ADDR ALT_USB_DEV_DOEPTSIZ5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA5_ADDR ALT_USB_DEV_DOEPDMA5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB5 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB5_ADDR ALT_USB_DEV_DOEPDMAB5_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL6_ADDR ALT_USB_DEV_DOEPCTL6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT6_ADDR ALT_USB_DEV_DOEPINT6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ6_ADDR ALT_USB_DEV_DOEPTSIZ6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA6_ADDR ALT_USB_DEV_DOEPDMA6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB6 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB6_ADDR ALT_USB_DEV_DOEPDMAB6_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL7_ADDR ALT_USB_DEV_DOEPCTL7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT7_ADDR ALT_USB_DEV_DOEPINT7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ7_ADDR ALT_USB_DEV_DOEPTSIZ7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA7_ADDR ALT_USB_DEV_DOEPDMA7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB7 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB7_ADDR ALT_USB_DEV_DOEPDMAB7_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL8_ADDR ALT_USB_DEV_DOEPCTL8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT8_ADDR ALT_USB_DEV_DOEPINT8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ8_ADDR ALT_USB_DEV_DOEPTSIZ8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA8_ADDR ALT_USB_DEV_DOEPDMA8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB8 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB8_ADDR ALT_USB_DEV_DOEPDMAB8_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL9_ADDR ALT_USB_DEV_DOEPCTL9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT9_ADDR ALT_USB_DEV_DOEPINT9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ9_ADDR ALT_USB_DEV_DOEPTSIZ9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA9_ADDR ALT_USB_DEV_DOEPDMA9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB9 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB9_ADDR ALT_USB_DEV_DOEPDMAB9_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL10_ADDR ALT_USB_DEV_DOEPCTL10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT10_ADDR ALT_USB_DEV_DOEPINT10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ10_ADDR ALT_USB_DEV_DOEPTSIZ10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA10_ADDR ALT_USB_DEV_DOEPDMA10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB10 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB10_ADDR ALT_USB_DEV_DOEPDMAB10_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL11_ADDR ALT_USB_DEV_DOEPCTL11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT11_ADDR ALT_USB_DEV_DOEPINT11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ11_ADDR ALT_USB_DEV_DOEPTSIZ11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA11_ADDR ALT_USB_DEV_DOEPDMA11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB11 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB11_ADDR ALT_USB_DEV_DOEPDMAB11_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL12_ADDR ALT_USB_DEV_DOEPCTL12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT12_ADDR ALT_USB_DEV_DOEPINT12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ12_ADDR ALT_USB_DEV_DOEPTSIZ12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA12_ADDR ALT_USB_DEV_DOEPDMA12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB12 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB12_ADDR ALT_USB_DEV_DOEPDMAB12_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL13_ADDR ALT_USB_DEV_DOEPCTL13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT13_ADDR ALT_USB_DEV_DOEPINT13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ13_ADDR ALT_USB_DEV_DOEPTSIZ13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA13_ADDR ALT_USB_DEV_DOEPDMA13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB13 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB13_ADDR ALT_USB_DEV_DOEPDMAB13_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL14_ADDR ALT_USB_DEV_DOEPCTL14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT14_ADDR ALT_USB_DEV_DOEPINT14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ14_ADDR ALT_USB_DEV_DOEPTSIZ14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA14_ADDR ALT_USB_DEV_DOEPDMA14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB14 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB14_ADDR ALT_USB_DEV_DOEPDMAB14_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPCTL15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPCTL15_ADDR ALT_USB_DEV_DOEPCTL15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPINT15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPINT15_ADDR ALT_USB_DEV_DOEPINT15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPTSIZ15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPTSIZ15_ADDR ALT_USB_DEV_DOEPTSIZ15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMA15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMA15_ADDR ALT_USB_DEV_DOEPDMA15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The address of the ALT_USB_DEV_DOEPDMAB15 register for the ALT_USB1_DEVGRP instance. */ +#define ALT_USB1_DEV_DOEPDMAB15_ADDR ALT_USB_DEV_DOEPDMAB15_ADDR(ALT_USB1_DEVGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_OFST 0x800 +/* The start address of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_DEVGRP_OFST)) +/* The lower bound address range of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_LB_ADDR ALT_USB1_DEVGRP_ADDR +/* The upper bound address range of the ALT_USB1_DEVGRP component. */ +#define ALT_USB1_DEVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_DEVGRP_ADDR) + 0x500) - 1)) + + +/* + * Register Group Instance : pwrclkgrp + * + * Instance pwrclkgrp of register group ALT_USB_PWRCLK. + * + * + */ +/* The address of the ALT_USB_PWRCLK_PCGCCTL register for the ALT_USB1_PWRCLKGRP instance. */ +#define ALT_USB1_PWRCLK_PCGCCTL_ADDR ALT_USB_PWRCLK_PCGCCTL_ADDR(ALT_USB1_PWRCLKGRP_ADDR) +/* The base address byte offset for the start of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_OFST 0xe00 +/* The start address of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_PWRCLKGRP_OFST)) +/* The lower bound address range of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_LB_ADDR ALT_USB1_PWRCLKGRP_ADDR +/* The upper bound address range of the ALT_USB1_PWRCLKGRP component. */ +#define ALT_USB1_PWRCLKGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_PWRCLKGRP_ADDR) + 0x4) - 1)) + + +/* The base address byte offset for the start of the ALT_USB1 component. */ +#define ALT_USB1_OFST 0xffb40000 +/* The start address of the ALT_USB1 component. */ +#define ALT_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_USB1_OFST)) +/* The lower bound address range of the ALT_USB1 component. */ +#define ALT_USB1_LB_ADDR ALT_USB1_ADDR +/* The upper bound address range of the ALT_USB1 component. */ +#define ALT_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_ADDR) + 0x40000) - 1)) + + +/* + * Component Instance : nandregs + * + * Instance nandregs of component ALT_NAND. + * + * + */ +/* + * Register Group Instance : config + * + * Instance config of register group ALT_NAND_CFG. + * + * + */ +/* The address of the ALT_NAND_CFG_DEVICE_RST register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_RST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_RST_OFST)) +/* The address of the ALT_NAND_CFG_TFR_SPARE_REG register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TFR_SPARE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TFR_SPARE_REG_OFST)) +/* The address of the ALT_NAND_CFG_LD_WAIT_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_LD_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_LD_WAIT_CNT_OFST)) +/* The address of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST)) +/* The address of the ALT_NAND_CFG_ERASE_WAIT_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ERASE_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ERASE_WAIT_CNT_OFST)) +/* The address of the ALT_NAND_CFG_INT_MON_CYCCNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_INT_MON_CYCCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_INT_MON_CYCCNT_OFST)) +/* The address of the ALT_NAND_CFG_RB_PIN_END register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RB_PIN_END_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RB_PIN_END_OFST)) +/* The address of the ALT_NAND_CFG_MULTIPLANE_OP register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MULTIPLANE_OP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_OP_OFST)) +/* The address of the ALT_NAND_CFG_MULTIPLANE_RD_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MULTIPLANE_RD_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST)) +/* The address of the ALT_NAND_CFG_COPYBACK_DIS register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_COPYBACK_DIS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_COPYBACK_DIS_OFST)) +/* The address of the ALT_NAND_CFG_CACHE_WR_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CACHE_WR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CACHE_WR_EN_OFST)) +/* The address of the ALT_NAND_CFG_CACHE_RD_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CACHE_RD_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CACHE_RD_EN_OFST)) +/* The address of the ALT_NAND_CFG_PREFETCH_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_PREFETCH_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PREFETCH_MOD_OFST)) +/* The address of the ALT_NAND_CFG_CHIP_EN_DONT_CARE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST)) +/* The address of the ALT_NAND_CFG_ECC_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ECC_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ECC_EN_OFST)) +/* The address of the ALT_NAND_CFG_GLOB_INT_EN register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_GLOB_INT_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_GLOB_INT_EN_OFST)) +/* The address of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST)) +/* The address of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST)) +/* The address of the ALT_NAND_CFG_RE_2_WE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RE_2_WE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RE_2_WE_OFST)) +/* The address of the ALT_NAND_CFG_ACC_CLKS register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ACC_CLKS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ACC_CLKS_OFST)) +/* The address of the ALT_NAND_CFG_NUMBER_OF_PLANES register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_NUMBER_OF_PLANES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_NUMBER_OF_PLANES_OFST)) +/* The address of the ALT_NAND_CFG_PAGES_PER_BLOCK register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_PAGES_PER_BLOCK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PAGES_PER_BLOCK_OFST)) +/* The address of the ALT_NAND_CFG_DEVICE_WIDTH register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_WIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_WIDTH_OFST)) +/* The address of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST)) +/* The address of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST)) +/* The address of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST)) +/* The address of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST)) +/* The address of the ALT_NAND_CFG_ECC_CORRECTION register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_ECC_CORRECTION_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ECC_CORRECTION_OFST)) +/* The address of the ALT_NAND_CFG_RD_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RD_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RD_MOD_OFST)) +/* The address of the ALT_NAND_CFG_WR_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_WR_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WR_MOD_OFST)) +/* The address of the ALT_NAND_CFG_COPYBACK_MOD register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_COPYBACK_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_COPYBACK_MOD_OFST)) +/* The address of the ALT_NAND_CFG_RDWR_EN_LO_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RDWR_EN_LO_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST)) +/* The address of the ALT_NAND_CFG_RDWR_EN_HI_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RDWR_EN_HI_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST)) +/* The address of the ALT_NAND_CFG_MAX_RD_DELAY register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_MAX_RD_DELAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MAX_RD_DELAY_OFST)) +/* The address of the ALT_NAND_CFG_CS_SETUP_CNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_CS_SETUP_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CS_SETUP_CNT_OFST)) +/* The address of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST)) +/* The address of the ALT_NAND_CFG_SPARE_AREA_MARKER register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_SPARE_AREA_MARKER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_SPARE_AREA_MARKER_OFST)) +/* The address of the ALT_NAND_CFG_DEVICES_CONNECTED register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DEVICES_CONNECTED_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICES_CONNECTED_OFST)) +/* The address of the ALT_NAND_CFG_DIE_MSK register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_DIE_MSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DIE_MSK_OFST)) +/* The address of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST)) +/* The address of the ALT_NAND_CFG_WR_PROTECT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_WR_PROTECT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WR_PROTECT_OFST)) +/* The address of the ALT_NAND_CFG_RE_2_RE register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_RE_2_RE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RE_2_RE_OFST)) +/* The address of the ALT_NAND_CFG_POR_RST_COUNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_POR_RST_COUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_POR_RST_COUNT_OFST)) +/* The address of the ALT_NAND_CFG_WD_RST_COUNT register for the ALT_NAND_CFG instance. */ +#define ALT_NAND_CFG_WD_RST_COUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WD_RST_COUNT_OFST)) +/* The base address byte offset for the start of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_OFST 0x0 +/* The start address of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_CFG_OFST)) +/* The lower bound address range of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_LB_ADDR ALT_NAND_CFG_ADDR +/* The upper bound address range of the ALT_NAND_CFG component. */ +#define ALT_NAND_CFG_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_CFG_ADDR) + 0x2b4) - 1)) + + +/* + * Register Group Instance : param + * + * Instance param of register group ALT_NAND_PARAM. + * + * + */ +/* The address of the ALT_NAND_PARAM_MANUFACTURER_ID register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_MANUFACTURER_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_MANUFACTURER_ID_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_ID register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_ID_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_0 register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_0_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_1 register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_1_OFST)) +/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_2 register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_DEVICE_PARAM_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_2_OFST)) +/* The address of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST)) +/* The address of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST)) +/* The address of the ALT_NAND_PARAM_REVISION register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_REVISION_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_REVISION_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_FEATURES register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_TIMING_MOD register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_TIMING_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST)) +/* The address of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST)) +/* The address of the ALT_NAND_PARAM_FEATURES register for the ALT_NAND_PARAM instance. */ +#define ALT_NAND_PARAM_FEATURES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_FEATURES_OFST)) +/* The base address byte offset for the start of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_OFST 0x300 +/* The start address of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_PARAM_OFST)) +/* The lower bound address range of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_LB_ADDR ALT_NAND_PARAM_ADDR +/* The upper bound address range of the ALT_NAND_PARAM component. */ +#define ALT_NAND_PARAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + 0xf4) - 1)) + + +/* + * Register Group Instance : status + * + * Instance status of register group ALT_NAND_STAT. + * + * + */ +/* The address of the ALT_NAND_STAT_TFR_MOD register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_TFR_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_TFR_MOD_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT0_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN0_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT0_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT1_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN1_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT1_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT2_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN2_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT2_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST)) +/* The address of the ALT_NAND_STAT_INTR_STAT3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_STAT3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT3_OFST)) +/* The address of the ALT_NAND_STAT_INTR_EN3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_INTR_EN3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN3_OFST)) +/* The address of the ALT_NAND_STAT_PAGE_CNT3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_PAGE_CNT3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT3_OFST)) +/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_PAGE_ADDR3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST)) +/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register for the ALT_NAND_STAT instance. */ +#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST)) +/* The base address byte offset for the start of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_OFST 0x400 +/* The start address of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_STAT_OFST)) +/* The lower bound address range of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_LB_ADDR ALT_NAND_STAT_ADDR +/* The upper bound address range of the ALT_NAND_STAT component. */ +#define ALT_NAND_STAT_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_STAT_ADDR) + 0x144) - 1)) + + +/* + * Register Group Instance : ecc + * + * Instance ecc of register group ALT_NAND_ECC. + * + * + */ +/* The address of the ALT_NAND_ECC_ECCCORINFO_B01 register for the ALT_NAND_ECC instance. */ +#define ALT_NAND_ECC_ECCCORINFO_B01_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ECC_ADDR) + ALT_NAND_ECC_ECCCORINFO_B01_OFST)) +/* The address of the ALT_NAND_ECC_ECCCORINFO_B23 register for the ALT_NAND_ECC instance. */ +#define ALT_NAND_ECC_ECCCORINFO_B23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ECC_ADDR) + ALT_NAND_ECC_ECCCORINFO_B23_OFST)) +/* The base address byte offset for the start of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_OFST 0x650 +/* The start address of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_ECC_OFST)) +/* The lower bound address range of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_LB_ADDR ALT_NAND_ECC_ADDR +/* The upper bound address range of the ALT_NAND_ECC component. */ +#define ALT_NAND_ECC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_ECC_ADDR) + 0x14) - 1)) + + +/* + * Register Group Instance : dma + * + * Instance dma of register group ALT_NAND_DMA. + * + * + */ +/* The address of the ALT_NAND_DMA_DMA_EN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_DMA_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_EN_OFST)) +/* The address of the ALT_NAND_DMA_DMA_INTR register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_DMA_INTR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_INTR_OFST)) +/* The address of the ALT_NAND_DMA_DMA_INTR_EN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_DMA_INTR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_INTR_EN_OFST)) +/* The address of the ALT_NAND_DMA_TGT_ERR_ADDR_LO register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST)) +/* The address of the ALT_NAND_DMA_TGT_ERR_ADDR_HI register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST)) +/* The address of the ALT_NAND_DMA_FLSH_BURST_LEN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_FLSH_BURST_LEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_FLSH_BURST_LEN_OFST)) +/* The address of the ALT_NAND_DMA_INTRLV register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_INTRLV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_INTRLV_OFST)) +/* The address of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST)) +/* The address of the ALT_NAND_DMA_LUN_STAT_CMD register for the ALT_NAND_DMA instance. */ +#define ALT_NAND_DMA_LUN_STAT_CMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_LUN_STAT_CMD_OFST)) +/* The base address byte offset for the start of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_OFST 0x700 +/* The start address of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_DMA_OFST)) +/* The lower bound address range of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_LB_ADDR ALT_NAND_DMA_ADDR +/* The upper bound address range of the ALT_NAND_DMA component. */ +#define ALT_NAND_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_DMA_ADDR) + 0xa4) - 1)) + + +/* The base address byte offset for the start of the ALT_NAND component. */ +#define ALT_NAND_OFST 0xffb80000 +/* The start address of the ALT_NAND component. */ +#define ALT_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_NAND_OFST)) +/* The lower bound address range of the ALT_NAND component. */ +#define ALT_NAND_LB_ADDR ALT_NAND_ADDR +/* The upper bound address range of the ALT_NAND component. */ +#define ALT_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_ADDR) + 0x800) - 1)) + + +/* + * Component Instance : fpgamgrdata + * + * Instance fpgamgrdata of component ALT_FPGAMGRDATA. + * + * + */ +/* The address of the ALT_FPGAMGRDATA_DATA register for the ALT_FPGAMGRDATA instance. */ +#define ALT_FPGAMGRDATA_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGRDATA_ADDR) + ALT_FPGAMGRDATA_DATA_OFST)) +/* The base address byte offset for the start of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_OFST 0xffb90000 +/* The start address of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_FPGAMGRDATA_OFST)) +/* The lower bound address range of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_LB_ADDR ALT_FPGAMGRDATA_ADDR +/* The upper bound address range of the ALT_FPGAMGRDATA component. */ +#define ALT_FPGAMGRDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGRDATA_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : can0 + * + * Instance can0 of component ALT_CAN. + * + * + */ +/* + * Register Group Instance : protogrp + * + * Instance protogrp of register group ALT_CAN_PROTO. + * + * + */ +/* The address of the ALT_CAN_PROTO_CCTL register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CCTL_ADDR ALT_CAN_PROTO_CCTL_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CSTS register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CSTS_ADDR ALT_CAN_PROTO_CSTS_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CERC register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CERC_ADDR ALT_CAN_PROTO_CERC_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CBT register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CBT_ADDR ALT_CAN_PROTO_CBT_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CIR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CIR_ADDR ALT_CAN_PROTO_CIR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CTR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CTR_ADDR ALT_CAN_PROTO_CTR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CFR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CFR_ADDR ALT_CAN_PROTO_CFR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CRR register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_CRR_ADDR ALT_CAN_PROTO_CRR_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_HWS register for the ALT_CAN0_PROTOGRP instance. */ +#define ALT_CAN0_PROTO_HWS_ADDR ALT_CAN_PROTO_HWS_ADDR(ALT_CAN0_PROTOGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_OFST 0x0 +/* The start address of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_PROTOGRP_OFST)) +/* The lower bound address range of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_LB_ADDR ALT_CAN0_PROTOGRP_ADDR +/* The upper bound address range of the ALT_CAN0_PROTOGRP component. */ +#define ALT_CAN0_PROTOGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_PROTOGRP_ADDR) + 0x28) - 1)) + + +/* + * Register Group Instance : msghandgrp + * + * Instance msghandgrp of register group ALT_CAN_MSGHAND. + * + * + */ +/* The address of the ALT_CAN_MSGHAND_MOTRX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRX_ADDR ALT_CAN_MSGHAND_MOTRX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRA_ADDR ALT_CAN_MSGHAND_MOTRA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRB_ADDR ALT_CAN_MSGHAND_MOTRB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRC_ADDR ALT_CAN_MSGHAND_MOTRC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOTRD_ADDR ALT_CAN_MSGHAND_MOTRD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDX_ADDR ALT_CAN_MSGHAND_MONDX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDA_ADDR ALT_CAN_MSGHAND_MONDA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDB_ADDR ALT_CAN_MSGHAND_MONDB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDC_ADDR ALT_CAN_MSGHAND_MONDC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MONDD_ADDR ALT_CAN_MSGHAND_MONDD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPX_ADDR ALT_CAN_MSGHAND_MOIPX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPA_ADDR ALT_CAN_MSGHAND_MOIPA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPB_ADDR ALT_CAN_MSGHAND_MOIPB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPC_ADDR ALT_CAN_MSGHAND_MOIPC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOIPD_ADDR ALT_CAN_MSGHAND_MOIPD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALX register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALX_ADDR ALT_CAN_MSGHAND_MOVALX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALA register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALA_ADDR ALT_CAN_MSGHAND_MOVALA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALB register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALB_ADDR ALT_CAN_MSGHAND_MOVALB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALC register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALC_ADDR ALT_CAN_MSGHAND_MOVALC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALD register for the ALT_CAN0_MSGHANDGRP instance. */ +#define ALT_CAN0_MSGHAND_MOVALD_ADDR ALT_CAN_MSGHAND_MOVALD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_OFST 0x84 +/* The start address of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_MSGHANDGRP_OFST)) +/* The lower bound address range of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_LB_ADDR ALT_CAN0_MSGHANDGRP_ADDR +/* The upper bound address range of the ALT_CAN0_MSGHANDGRP component. */ +#define ALT_CAN0_MSGHANDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_MSGHANDGRP_ADDR) + 0x50) - 1)) + + +/* + * Register Group Instance : msgifgrp + * + * Instance msgifgrp of register group ALT_CAN_MSGIF. + * + * + */ +/* The address of the ALT_CAN_MSGIF_IF1CMR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1CMR_ADDR ALT_CAN_MSGIF_IF1CMR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MSK register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1MSK_ADDR ALT_CAN_MSGIF_IF1MSK_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1ARB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1ARB_ADDR ALT_CAN_MSGIF_IF1ARB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MCTR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1MCTR_ADDR ALT_CAN_MSGIF_IF1MCTR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DA register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1DA_ADDR ALT_CAN_MSGIF_IF1DA_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF1DB_ADDR ALT_CAN_MSGIF_IF1DB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2CMR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2CMR_ADDR ALT_CAN_MSGIF_IF2CMR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MSK register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2MSK_ADDR ALT_CAN_MSGIF_IF2MSK_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2ARB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2ARB_ADDR ALT_CAN_MSGIF_IF2ARB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MCTR register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2MCTR_ADDR ALT_CAN_MSGIF_IF2MCTR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DA register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2DA_ADDR ALT_CAN_MSGIF_IF2DA_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DB register for the ALT_CAN0_MSGIFGRP instance. */ +#define ALT_CAN0_MSGIF_IF2DB_ADDR ALT_CAN_MSGIF_IF2DB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_OFST 0x100 +/* The start address of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_MSGIFGRP_OFST)) +/* The lower bound address range of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_LB_ADDR ALT_CAN0_MSGIFGRP_ADDR +/* The upper bound address range of the ALT_CAN0_MSGIFGRP component. */ +#define ALT_CAN0_MSGIFGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_MSGIFGRP_ADDR) + 0x38) - 1)) + + +/* The base address byte offset for the start of the ALT_CAN0 component. */ +#define ALT_CAN0_OFST 0xffc00000 +/* The start address of the ALT_CAN0 component. */ +#define ALT_CAN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CAN0_OFST)) +/* The lower bound address range of the ALT_CAN0 component. */ +#define ALT_CAN0_LB_ADDR ALT_CAN0_ADDR +/* The upper bound address range of the ALT_CAN0 component. */ +#define ALT_CAN0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_ADDR) + 0x200) - 1)) + + +/* + * Component Instance : can1 + * + * Instance can1 of component ALT_CAN. + * + * + */ +/* + * Register Group Instance : protogrp + * + * Instance protogrp of register group ALT_CAN_PROTO. + * + * + */ +/* The address of the ALT_CAN_PROTO_CCTL register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CCTL_ADDR ALT_CAN_PROTO_CCTL_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CSTS register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CSTS_ADDR ALT_CAN_PROTO_CSTS_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CERC register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CERC_ADDR ALT_CAN_PROTO_CERC_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CBT register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CBT_ADDR ALT_CAN_PROTO_CBT_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CIR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CIR_ADDR ALT_CAN_PROTO_CIR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CTR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CTR_ADDR ALT_CAN_PROTO_CTR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CFR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CFR_ADDR ALT_CAN_PROTO_CFR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_CRR register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_CRR_ADDR ALT_CAN_PROTO_CRR_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The address of the ALT_CAN_PROTO_HWS register for the ALT_CAN1_PROTOGRP instance. */ +#define ALT_CAN1_PROTO_HWS_ADDR ALT_CAN_PROTO_HWS_ADDR(ALT_CAN1_PROTOGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_OFST 0x0 +/* The start address of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_PROTOGRP_OFST)) +/* The lower bound address range of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_LB_ADDR ALT_CAN1_PROTOGRP_ADDR +/* The upper bound address range of the ALT_CAN1_PROTOGRP component. */ +#define ALT_CAN1_PROTOGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_PROTOGRP_ADDR) + 0x28) - 1)) + + +/* + * Register Group Instance : msghandgrp + * + * Instance msghandgrp of register group ALT_CAN_MSGHAND. + * + * + */ +/* The address of the ALT_CAN_MSGHAND_MOTRX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRX_ADDR ALT_CAN_MSGHAND_MOTRX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRA_ADDR ALT_CAN_MSGHAND_MOTRA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRB_ADDR ALT_CAN_MSGHAND_MOTRB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRC_ADDR ALT_CAN_MSGHAND_MOTRC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOTRD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOTRD_ADDR ALT_CAN_MSGHAND_MOTRD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDX_ADDR ALT_CAN_MSGHAND_MONDX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDA_ADDR ALT_CAN_MSGHAND_MONDA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDB_ADDR ALT_CAN_MSGHAND_MONDB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDC_ADDR ALT_CAN_MSGHAND_MONDC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MONDD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MONDD_ADDR ALT_CAN_MSGHAND_MONDD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPX_ADDR ALT_CAN_MSGHAND_MOIPX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPA_ADDR ALT_CAN_MSGHAND_MOIPA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPB_ADDR ALT_CAN_MSGHAND_MOIPB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPC_ADDR ALT_CAN_MSGHAND_MOIPC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOIPD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOIPD_ADDR ALT_CAN_MSGHAND_MOIPD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALX register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALX_ADDR ALT_CAN_MSGHAND_MOVALX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALA register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALA_ADDR ALT_CAN_MSGHAND_MOVALA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALB register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALB_ADDR ALT_CAN_MSGHAND_MOVALB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALC register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALC_ADDR ALT_CAN_MSGHAND_MOVALC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The address of the ALT_CAN_MSGHAND_MOVALD register for the ALT_CAN1_MSGHANDGRP instance. */ +#define ALT_CAN1_MSGHAND_MOVALD_ADDR ALT_CAN_MSGHAND_MOVALD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_OFST 0x84 +/* The start address of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_MSGHANDGRP_OFST)) +/* The lower bound address range of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_LB_ADDR ALT_CAN1_MSGHANDGRP_ADDR +/* The upper bound address range of the ALT_CAN1_MSGHANDGRP component. */ +#define ALT_CAN1_MSGHANDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_MSGHANDGRP_ADDR) + 0x50) - 1)) + + +/* + * Register Group Instance : msgifgrp + * + * Instance msgifgrp of register group ALT_CAN_MSGIF. + * + * + */ +/* The address of the ALT_CAN_MSGIF_IF1CMR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1CMR_ADDR ALT_CAN_MSGIF_IF1CMR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MSK register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1MSK_ADDR ALT_CAN_MSGIF_IF1MSK_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1ARB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1ARB_ADDR ALT_CAN_MSGIF_IF1ARB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1MCTR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1MCTR_ADDR ALT_CAN_MSGIF_IF1MCTR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DA register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1DA_ADDR ALT_CAN_MSGIF_IF1DA_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF1DB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF1DB_ADDR ALT_CAN_MSGIF_IF1DB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2CMR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2CMR_ADDR ALT_CAN_MSGIF_IF2CMR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MSK register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2MSK_ADDR ALT_CAN_MSGIF_IF2MSK_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2ARB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2ARB_ADDR ALT_CAN_MSGIF_IF2ARB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2MCTR register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2MCTR_ADDR ALT_CAN_MSGIF_IF2MCTR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DA register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2DA_ADDR ALT_CAN_MSGIF_IF2DA_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The address of the ALT_CAN_MSGIF_IF2DB register for the ALT_CAN1_MSGIFGRP instance. */ +#define ALT_CAN1_MSGIF_IF2DB_ADDR ALT_CAN_MSGIF_IF2DB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) +/* The base address byte offset for the start of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_OFST 0x100 +/* The start address of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_MSGIFGRP_OFST)) +/* The lower bound address range of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_LB_ADDR ALT_CAN1_MSGIFGRP_ADDR +/* The upper bound address range of the ALT_CAN1_MSGIFGRP component. */ +#define ALT_CAN1_MSGIFGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_MSGIFGRP_ADDR) + 0x38) - 1)) + + +/* The base address byte offset for the start of the ALT_CAN1 component. */ +#define ALT_CAN1_OFST 0xffc01000 +/* The start address of the ALT_CAN1 component. */ +#define ALT_CAN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CAN1_OFST)) +/* The lower bound address range of the ALT_CAN1 component. */ +#define ALT_CAN1_LB_ADDR ALT_CAN1_ADDR +/* The upper bound address range of the ALT_CAN1 component. */ +#define ALT_CAN1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_ADDR) + 0x200) - 1)) + + +/* + * Component Instance : uart0 + * + * Instance uart0 of component ALT_UART. + * + * + */ +/* The address of the ALT_UART_RBR_THR_DLL register for the ALT_UART0 instance. */ +#define ALT_UART0_RBR_THR_DLL_ADDR ALT_UART_RBR_THR_DLL_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_IER_DLH register for the ALT_UART0 instance. */ +#define ALT_UART0_IER_DLH_ADDR ALT_UART_IER_DLH_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_IIR register for the ALT_UART0 instance. */ +#define ALT_UART0_IIR_ADDR ALT_UART_IIR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_FCR register for the ALT_UART0 instance. */ +#define ALT_UART0_FCR_ADDR ALT_UART_FCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_LCR register for the ALT_UART0 instance. */ +#define ALT_UART0_LCR_ADDR ALT_UART_LCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_MCR register for the ALT_UART0 instance. */ +#define ALT_UART0_MCR_ADDR ALT_UART_MCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_LSR register for the ALT_UART0 instance. */ +#define ALT_UART0_LSR_ADDR ALT_UART_LSR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_MSR register for the ALT_UART0 instance. */ +#define ALT_UART0_MSR_ADDR ALT_UART_MSR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SCR register for the ALT_UART0 instance. */ +#define ALT_UART0_SCR_ADDR ALT_UART_SCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRBR register for the ALT_UART0 instance. */ +#define ALT_UART0_SRBR_ADDR ALT_UART_SRBR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_STHR register for the ALT_UART0 instance. */ +#define ALT_UART0_STHR_ADDR ALT_UART_STHR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_FAR register for the ALT_UART0 instance. */ +#define ALT_UART0_FAR_ADDR ALT_UART_FAR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_TFR register for the ALT_UART0 instance. */ +#define ALT_UART0_TFR_ADDR ALT_UART_TFR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_RFW register for the ALT_UART0 instance. */ +#define ALT_UART0_RFW_ADDR ALT_UART_RFW_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_USR register for the ALT_UART0 instance. */ +#define ALT_UART0_USR_ADDR ALT_UART_USR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_TFL register for the ALT_UART0 instance. */ +#define ALT_UART0_TFL_ADDR ALT_UART_TFL_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_RFL register for the ALT_UART0 instance. */ +#define ALT_UART0_RFL_ADDR ALT_UART_RFL_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRR register for the ALT_UART0 instance. */ +#define ALT_UART0_SRR_ADDR ALT_UART_SRR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRTS register for the ALT_UART0 instance. */ +#define ALT_UART0_SRTS_ADDR ALT_UART_SRTS_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SBCR register for the ALT_UART0 instance. */ +#define ALT_UART0_SBCR_ADDR ALT_UART_SBCR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SDMAM register for the ALT_UART0 instance. */ +#define ALT_UART0_SDMAM_ADDR ALT_UART_SDMAM_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SFE register for the ALT_UART0 instance. */ +#define ALT_UART0_SFE_ADDR ALT_UART_SFE_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_SRT register for the ALT_UART0 instance. */ +#define ALT_UART0_SRT_ADDR ALT_UART_SRT_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_STET register for the ALT_UART0 instance. */ +#define ALT_UART0_STET_ADDR ALT_UART_STET_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_HTX register for the ALT_UART0 instance. */ +#define ALT_UART0_HTX_ADDR ALT_UART_HTX_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_DMASA register for the ALT_UART0 instance. */ +#define ALT_UART0_DMASA_ADDR ALT_UART_DMASA_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_CPR register for the ALT_UART0 instance. */ +#define ALT_UART0_CPR_ADDR ALT_UART_CPR_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_UCV register for the ALT_UART0 instance. */ +#define ALT_UART0_UCV_ADDR ALT_UART_UCV_ADDR(ALT_UART0_ADDR) +/* The address of the ALT_UART_CTR register for the ALT_UART0 instance. */ +#define ALT_UART0_CTR_ADDR ALT_UART_CTR_ADDR(ALT_UART0_ADDR) +/* The base address byte offset for the start of the ALT_UART0 component. */ +#define ALT_UART0_OFST 0xffc02000 +/* The start address of the ALT_UART0 component. */ +#define ALT_UART0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_UART0_OFST)) +/* The lower bound address range of the ALT_UART0 component. */ +#define ALT_UART0_LB_ADDR ALT_UART0_ADDR +/* The upper bound address range of the ALT_UART0 component. */ +#define ALT_UART0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_UART0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : uart1 + * + * Instance uart1 of component ALT_UART. + * + * + */ +/* The address of the ALT_UART_RBR_THR_DLL register for the ALT_UART1 instance. */ +#define ALT_UART1_RBR_THR_DLL_ADDR ALT_UART_RBR_THR_DLL_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_IER_DLH register for the ALT_UART1 instance. */ +#define ALT_UART1_IER_DLH_ADDR ALT_UART_IER_DLH_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_IIR register for the ALT_UART1 instance. */ +#define ALT_UART1_IIR_ADDR ALT_UART_IIR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_FCR register for the ALT_UART1 instance. */ +#define ALT_UART1_FCR_ADDR ALT_UART_FCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_LCR register for the ALT_UART1 instance. */ +#define ALT_UART1_LCR_ADDR ALT_UART_LCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_MCR register for the ALT_UART1 instance. */ +#define ALT_UART1_MCR_ADDR ALT_UART_MCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_LSR register for the ALT_UART1 instance. */ +#define ALT_UART1_LSR_ADDR ALT_UART_LSR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_MSR register for the ALT_UART1 instance. */ +#define ALT_UART1_MSR_ADDR ALT_UART_MSR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SCR register for the ALT_UART1 instance. */ +#define ALT_UART1_SCR_ADDR ALT_UART_SCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRBR register for the ALT_UART1 instance. */ +#define ALT_UART1_SRBR_ADDR ALT_UART_SRBR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_STHR register for the ALT_UART1 instance. */ +#define ALT_UART1_STHR_ADDR ALT_UART_STHR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_FAR register for the ALT_UART1 instance. */ +#define ALT_UART1_FAR_ADDR ALT_UART_FAR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_TFR register for the ALT_UART1 instance. */ +#define ALT_UART1_TFR_ADDR ALT_UART_TFR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_RFW register for the ALT_UART1 instance. */ +#define ALT_UART1_RFW_ADDR ALT_UART_RFW_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_USR register for the ALT_UART1 instance. */ +#define ALT_UART1_USR_ADDR ALT_UART_USR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_TFL register for the ALT_UART1 instance. */ +#define ALT_UART1_TFL_ADDR ALT_UART_TFL_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_RFL register for the ALT_UART1 instance. */ +#define ALT_UART1_RFL_ADDR ALT_UART_RFL_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRR register for the ALT_UART1 instance. */ +#define ALT_UART1_SRR_ADDR ALT_UART_SRR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRTS register for the ALT_UART1 instance. */ +#define ALT_UART1_SRTS_ADDR ALT_UART_SRTS_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SBCR register for the ALT_UART1 instance. */ +#define ALT_UART1_SBCR_ADDR ALT_UART_SBCR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SDMAM register for the ALT_UART1 instance. */ +#define ALT_UART1_SDMAM_ADDR ALT_UART_SDMAM_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SFE register for the ALT_UART1 instance. */ +#define ALT_UART1_SFE_ADDR ALT_UART_SFE_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_SRT register for the ALT_UART1 instance. */ +#define ALT_UART1_SRT_ADDR ALT_UART_SRT_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_STET register for the ALT_UART1 instance. */ +#define ALT_UART1_STET_ADDR ALT_UART_STET_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_HTX register for the ALT_UART1 instance. */ +#define ALT_UART1_HTX_ADDR ALT_UART_HTX_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_DMASA register for the ALT_UART1 instance. */ +#define ALT_UART1_DMASA_ADDR ALT_UART_DMASA_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_CPR register for the ALT_UART1 instance. */ +#define ALT_UART1_CPR_ADDR ALT_UART_CPR_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_UCV register for the ALT_UART1 instance. */ +#define ALT_UART1_UCV_ADDR ALT_UART_UCV_ADDR(ALT_UART1_ADDR) +/* The address of the ALT_UART_CTR register for the ALT_UART1 instance. */ +#define ALT_UART1_CTR_ADDR ALT_UART_CTR_ADDR(ALT_UART1_ADDR) +/* The base address byte offset for the start of the ALT_UART1 component. */ +#define ALT_UART1_OFST 0xffc03000 +/* The start address of the ALT_UART1 component. */ +#define ALT_UART1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_UART1_OFST)) +/* The lower bound address range of the ALT_UART1 component. */ +#define ALT_UART1_LB_ADDR ALT_UART1_ADDR +/* The upper bound address range of the ALT_UART1 component. */ +#define ALT_UART1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_UART1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c0 + * + * Instance i2c0 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C0_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C0 instance. */ +#define ALT_I2C0_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C0_ADDR) +/* The base address byte offset for the start of the ALT_I2C0 component. */ +#define ALT_I2C0_OFST 0xffc04000 +/* The start address of the ALT_I2C0 component. */ +#define ALT_I2C0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C0_OFST)) +/* The lower bound address range of the ALT_I2C0 component. */ +#define ALT_I2C0_LB_ADDR ALT_I2C0_ADDR +/* The upper bound address range of the ALT_I2C0 component. */ +#define ALT_I2C0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c1 + * + * Instance i2c1 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C1_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C1 instance. */ +#define ALT_I2C1_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C1_ADDR) +/* The base address byte offset for the start of the ALT_I2C1 component. */ +#define ALT_I2C1_OFST 0xffc05000 +/* The start address of the ALT_I2C1 component. */ +#define ALT_I2C1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C1_OFST)) +/* The lower bound address range of the ALT_I2C1 component. */ +#define ALT_I2C1_LB_ADDR ALT_I2C1_ADDR +/* The upper bound address range of the ALT_I2C1 component. */ +#define ALT_I2C1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c2 + * + * Instance i2c2 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C2_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C2 instance. */ +#define ALT_I2C2_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C2_ADDR) +/* The base address byte offset for the start of the ALT_I2C2 component. */ +#define ALT_I2C2_OFST 0xffc06000 +/* The start address of the ALT_I2C2 component. */ +#define ALT_I2C2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C2_OFST)) +/* The lower bound address range of the ALT_I2C2 component. */ +#define ALT_I2C2_LB_ADDR ALT_I2C2_ADDR +/* The upper bound address range of the ALT_I2C2 component. */ +#define ALT_I2C2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C2_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : i2c3 + * + * Instance i2c3 of component ALT_I2C. + * + * + */ +/* The address of the ALT_I2C_CON register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TAR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SAR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_RX_TL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TX_TL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_EN register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TXFLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_RXFLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C3_ADDR) +/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C3 instance. */ +#define ALT_I2C3_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C3_ADDR) +/* The base address byte offset for the start of the ALT_I2C3 component. */ +#define ALT_I2C3_OFST 0xffc07000 +/* The start address of the ALT_I2C3 component. */ +#define ALT_I2C3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C3_OFST)) +/* The lower bound address range of the ALT_I2C3 component. */ +#define ALT_I2C3_LB_ADDR ALT_I2C3_ADDR +/* The upper bound address range of the ALT_I2C3 component. */ +#define ALT_I2C3_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C3_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sptimer0 + * + * Instance sptimer0 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_SPTMR0_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_SPTMR0 instance. */ +#define ALT_SPTMR0_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_SPTMR0_ADDR) +/* The base address byte offset for the start of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_OFST 0xffc08000 +/* The start address of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPTMR0_OFST)) +/* The lower bound address range of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_LB_ADDR ALT_SPTMR0_ADDR +/* The upper bound address range of the ALT_SPTMR0 component. */ +#define ALT_SPTMR0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPTMR0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sptimer1 + * + * Instance sptimer1 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_SPTMR1_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_SPTMR1 instance. */ +#define ALT_SPTMR1_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_SPTMR1_ADDR) +/* The base address byte offset for the start of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_OFST 0xffc09000 +/* The start address of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPTMR1_OFST)) +/* The lower bound address range of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_LB_ADDR ALT_SPTMR1_ADDR +/* The upper bound address range of the ALT_SPTMR1 component. */ +#define ALT_SPTMR1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPTMR1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sdr + * + * Instance sdr of component ALT_SDR. + * + * + */ +/* + * Register Group Instance : ctrlgrp + * + * Instance ctrlgrp of register group ALT_SDR_CTL. + * + * + */ +/* The address of the ALT_SDR_CTL_CTLCFG register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_CTLCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTLCFG_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING1 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING1_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING2 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING2_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING3 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING3_OFST)) +/* The address of the ALT_SDR_CTL_DRAMTIMING4 register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMTIMING4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING4_OFST)) +/* The address of the ALT_SDR_CTL_LOWPWRTIMING register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_LOWPWRTIMING_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWRTIMING_OFST)) +/* The address of the ALT_SDR_CTL_DRAMODT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMODT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMODT_OFST)) +/* The address of the ALT_SDR_CTL_DRAMADDRW register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMADDRW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMADDRW_OFST)) +/* The address of the ALT_SDR_CTL_DRAMIFWIDTH register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMIFWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMIFWIDTH_OFST)) +/* The address of the ALT_SDR_CTL_DRAMDEVWIDTH register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMDEVWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMDEVWIDTH_OFST)) +/* The address of the ALT_SDR_CTL_DRAMSTS register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMSTS_OFST)) +/* The address of the ALT_SDR_CTL_DRAMINTR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DRAMINTR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMINTR_OFST)) +/* The address of the ALT_SDR_CTL_SBECOUNT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_SBECOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_SBECOUNT_OFST)) +/* The address of the ALT_SDR_CTL_DBECOUNT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DBECOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DBECOUNT_OFST)) +/* The address of the ALT_SDR_CTL_ERRADDR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_ERRADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_ERRADDR_OFST)) +/* The address of the ALT_SDR_CTL_DROPCOUNT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DROPCOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DROPCOUNT_OFST)) +/* The address of the ALT_SDR_CTL_DROPADDR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_DROPADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DROPADDR_OFST)) +/* The address of the ALT_SDR_CTL_LOWPWREQ register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_LOWPWREQ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWREQ_OFST)) +/* The address of the ALT_SDR_CTL_LOWPWRACK register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_LOWPWRACK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWRACK_OFST)) +/* The address of the ALT_SDR_CTL_STATICCFG register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_STATICCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_STATICCFG_OFST)) +/* The address of the ALT_SDR_CTL_CTLWIDTH register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_CTLWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTLWIDTH_OFST)) +/* The address of the ALT_SDR_CTL_PORTCFG register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PORTCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PORTCFG_OFST)) +/* The address of the ALT_SDR_CTL_FPGAPORTRST register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_FPGAPORTRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_FPGAPORTRST_OFST)) +/* The address of the ALT_SDR_CTL_PROTPORTDEFAULT register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTPORTDEFAULT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTPORTDEFAULT_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULEADDR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULEADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEADDR_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULEID register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULEID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEID_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULEDATA register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULEDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEDATA_OFST)) +/* The address of the ALT_SDR_CTL_PROTRULERDWR register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_PROTRULERDWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULERDWR_OFST)) +/* The address of the ALT_SDR_CTL_QOSLOWPRI register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_QOSLOWPRI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSLOWPRI_OFST)) +/* The address of the ALT_SDR_CTL_QOSHIGHPRI register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_QOSHIGHPRI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSHIGHPRI_OFST)) +/* The address of the ALT_SDR_CTL_QOSPRIORITYEN register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_QOSPRIORITYEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSPRIORITYEN_OFST)) +/* The address of the ALT_SDR_CTL_MPPRIORITY register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_MPPRIORITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_MPPRIORITY_OFST)) +/* The address of the ALT_SDR_CTL_REMAPPRIORITY register for the ALT_SDR_CTL instance. */ +#define ALT_SDR_CTL_REMAPPRIORITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_REMAPPRIORITY_OFST)) +/* + * Register Group Instance : ctrlgrp_mpweight + * + * Instance ctrlgrp_mpweight of register group ALT_SDR_CTL_MPWT. + * + * + */ +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_0_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_1_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_2_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_3_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) +/* The base address byte offset for the start of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_OFST 0xb0 +/* The start address of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTL_MPWEIGHT_OFST)) +/* The lower bound address range of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_LB_ADDR ALT_SDR_CTL_CTL_MPWEIGHT_ADDR +/* The upper bound address range of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ +#define ALT_SDR_CTL_CTL_MPWEIGHT_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) + 0x10) - 1)) + + +/* The base address byte offset for the start of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_OFST 0x5000 +/* The start address of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_ADDR) + ALT_SDR_CTL_OFST)) +/* The lower bound address range of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_LB_ADDR ALT_SDR_CTL_ADDR +/* The upper bound address range of the ALT_SDR_CTL component. */ +#define ALT_SDR_CTL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_CTL_ADDR) + 0x1000) - 1)) + + +/* The base address byte offset for the start of the ALT_SDR component. */ +#define ALT_SDR_OFST 0xffc20000 +/* The start address of the ALT_SDR component. */ +#define ALT_SDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SDR_OFST)) +/* The lower bound address range of the ALT_SDR component. */ +#define ALT_SDR_LB_ADDR ALT_SDR_ADDR +/* The upper bound address range of the ALT_SDR component. */ +#define ALT_SDR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_ADDR) + 0x20000) - 1)) + + +/* + * Component Instance : osc1timer0 + * + * Instance osc1timer0 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_OSC1TMR0_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_OSC1TMR0 instance. */ +#define ALT_OSC1TMR0_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_OSC1TMR0_ADDR) +/* The base address byte offset for the start of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_OFST 0xffd00000 +/* The start address of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OSC1TMR0_OFST)) +/* The lower bound address range of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_LB_ADDR ALT_OSC1TMR0_ADDR +/* The upper bound address range of the ALT_OSC1TMR0 component. */ +#define ALT_OSC1TMR0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OSC1TMR0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : osc1timer1 + * + * Instance osc1timer1 of component ALT_TMR. + * + * + */ +/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1EOI register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSEOI register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_OSC1TMR1_ADDR) +/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_OSC1TMR1 instance. */ +#define ALT_OSC1TMR1_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_OSC1TMR1_ADDR) +/* The base address byte offset for the start of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_OFST 0xffd01000 +/* The start address of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OSC1TMR1_OFST)) +/* The lower bound address range of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_LB_ADDR ALT_OSC1TMR1_ADDR +/* The upper bound address range of the ALT_OSC1TMR1 component. */ +#define ALT_OSC1TMR1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OSC1TMR1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : l4wd0 + * + * Instance l4wd0 of component ALT_L4WD. + * + * + */ +/* The address of the ALT_L4WD_CR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_CR_ADDR ALT_L4WD_CR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_TORR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_TORR_ADDR ALT_L4WD_TORR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CCVR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_CCVR_ADDR ALT_L4WD_CCVR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CRR register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_CRR_ADDR ALT_L4WD_CRR_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_STAT register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_STAT_ADDR ALT_L4WD_STAT_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_EOI register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_EOI_ADDR ALT_L4WD_EOI_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CP_WDT_USER_TOP_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CP_WDT_USER_TOP_INIT_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CD_WDT_TOP_RST register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CD_WDT_TOP_RST_ADDR ALT_L4WD_CD_WDT_TOP_RST_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_CP_WDT_CNT_RST register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_CP_WDT_CNT_RST_ADDR ALT_L4WD_CP_WDT_CNT_RST_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_COMP_PARAM_1 register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_COMP_PARAM_1_ADDR ALT_L4WD_COMP_PARAM_1_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_COMP_VER register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_COMP_VER_ADDR ALT_L4WD_COMP_VER_ADDR(ALT_L4WD0_ADDR) +/* The address of the ALT_L4WD_COMP_TYPE register for the ALT_L4WD0 instance. */ +#define ALT_L4WD0_WDT_COMP_TYPE_ADDR ALT_L4WD_COMP_TYPE_ADDR(ALT_L4WD0_ADDR) +/* The base address byte offset for the start of the ALT_L4WD0 component. */ +#define ALT_L4WD0_OFST 0xffd02000 +/* The start address of the ALT_L4WD0 component. */ +#define ALT_L4WD0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L4WD0_OFST)) +/* The lower bound address range of the ALT_L4WD0 component. */ +#define ALT_L4WD0_LB_ADDR ALT_L4WD0_ADDR +/* The upper bound address range of the ALT_L4WD0 component. */ +#define ALT_L4WD0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L4WD0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : l4wd1 + * + * Instance l4wd1 of component ALT_L4WD. + * + * + */ +/* The address of the ALT_L4WD_CR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_CR_ADDR ALT_L4WD_CR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_TORR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_TORR_ADDR ALT_L4WD_TORR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CCVR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_CCVR_ADDR ALT_L4WD_CCVR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CRR register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_CRR_ADDR ALT_L4WD_CRR_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_STAT register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_STAT_ADDR ALT_L4WD_STAT_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_EOI register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_EOI_ADDR ALT_L4WD_EOI_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CP_WDT_USER_TOP_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CP_WDT_USER_TOP_INIT_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CD_WDT_TOP_RST register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CD_WDT_TOP_RST_ADDR ALT_L4WD_CD_WDT_TOP_RST_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_CP_WDT_CNT_RST register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_CP_WDT_CNT_RST_ADDR ALT_L4WD_CP_WDT_CNT_RST_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_COMP_PARAM_1 register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_COMP_PARAM_1_ADDR ALT_L4WD_COMP_PARAM_1_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_COMP_VER register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_COMP_VER_ADDR ALT_L4WD_COMP_VER_ADDR(ALT_L4WD1_ADDR) +/* The address of the ALT_L4WD_COMP_TYPE register for the ALT_L4WD1 instance. */ +#define ALT_L4WD1_WDT_COMP_TYPE_ADDR ALT_L4WD_COMP_TYPE_ADDR(ALT_L4WD1_ADDR) +/* The base address byte offset for the start of the ALT_L4WD1 component. */ +#define ALT_L4WD1_OFST 0xffd03000 +/* The start address of the ALT_L4WD1 component. */ +#define ALT_L4WD1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L4WD1_OFST)) +/* The lower bound address range of the ALT_L4WD1 component. */ +#define ALT_L4WD1_LB_ADDR ALT_L4WD1_ADDR +/* The upper bound address range of the ALT_L4WD1 component. */ +#define ALT_L4WD1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L4WD1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : clkmgr + * + * Instance clkmgr of component ALT_CLKMGR. + * + * + */ +/* The address of the ALT_CLKMGR_CTL register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_CTL_OFST)) +/* The address of the ALT_CLKMGR_BYPASS register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_BYPASS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_BYPASS_OFST)) +/* The address of the ALT_CLKMGR_INTER register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_INTER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_INTER_OFST)) +/* The address of the ALT_CLKMGR_INTREN register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_INTREN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_INTREN_OFST)) +/* The address of the ALT_CLKMGR_DBCTL register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_DBCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_DBCTL_OFST)) +/* The address of the ALT_CLKMGR_STAT register for the ALT_CLKMGR instance. */ +#define ALT_CLKMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_STAT_OFST)) +/* + * Register Group Instance : mainpllgrp + * + * Instance mainpllgrp of register group ALT_CLKMGR_MAINPLL. + * + * + */ +/* The address of the ALT_CLKMGR_MAINPLL_VCO register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_VCO_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MISC register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MISC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MISC_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MPUCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MPUCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MPUCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_DBGATCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_DBGATCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_EN register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_EN_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_MAINDIV register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_MAINDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINDIV_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_DBGDIV register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_DBGDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_DBGDIV_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_TRACEDIV register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_TRACEDIV_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_L4SRC register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_L4SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_L4SRC_OFST)) +/* The address of the ALT_CLKMGR_MAINPLL_STAT register for the ALT_CLKMGR_MAINPLL instance. */ +#define ALT_CLKMGR_MAINPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_STAT_OFST)) +/* The base address byte offset for the start of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_OFST 0x40 +/* The start address of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_MAINPLL_OFST)) +/* The lower bound address range of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_LB_ADDR ALT_CLKMGR_MAINPLL_ADDR +/* The upper bound address range of the ALT_CLKMGR_MAINPLL component. */ +#define ALT_CLKMGR_MAINPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : perpllgrp + * + * Instance perpllgrp of register group ALT_CLKMGR_PERPLL. + * + * + */ +/* The address of the ALT_CLKMGR_PERPLL_VCO register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_VCO_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_MISC register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_MISC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_MISC_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_EMAC0CLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EMAC0CLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_EMAC1CLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EMAC1CLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_PERQSPICLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERQSPICLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_PERBASECLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_PERBASECLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERBASECLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_EN register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EN_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_DIV register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_DIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_DIV_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_GPIODIV register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_GPIODIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_GPIODIV_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_SRC register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_SRC_OFST)) +/* The address of the ALT_CLKMGR_PERPLL_STAT register for the ALT_CLKMGR_PERPLL instance. */ +#define ALT_CLKMGR_PERPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_STAT_OFST)) +/* The base address byte offset for the start of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_OFST 0x80 +/* The start address of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_PERPLL_OFST)) +/* The lower bound address range of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_LB_ADDR ALT_CLKMGR_PERPLL_ADDR +/* The upper bound address range of the ALT_CLKMGR_PERPLL component. */ +#define ALT_CLKMGR_PERPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : sdrpllgrp + * + * Instance sdrpllgrp of register group ALT_CLKMGR_SDRPLL. + * + * + */ +/* The address of the ALT_CLKMGR_SDRPLL_VCO register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_VCO_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_CTL register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_CTL_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_DDRDQCLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_EN register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_EN_OFST)) +/* The address of the ALT_CLKMGR_SDRPLL_STAT register for the ALT_CLKMGR_SDRPLL instance. */ +#define ALT_CLKMGR_SDRPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_STAT_OFST)) +/* The base address byte offset for the start of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_OFST 0xc0 +/* The start address of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_SDRPLL_OFST)) +/* The lower bound address range of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_LB_ADDR ALT_CLKMGR_SDRPLL_ADDR +/* The upper bound address range of the ALT_CLKMGR_SDRPLL component. */ +#define ALT_CLKMGR_SDRPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + 0x20) - 1)) + + +/* The base address byte offset for the start of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_OFST 0xffd04000 +/* The start address of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CLKMGR_OFST)) +/* The lower bound address range of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_LB_ADDR ALT_CLKMGR_ADDR +/* The upper bound address range of the ALT_CLKMGR component. */ +#define ALT_CLKMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_ADDR) + 0x200) - 1)) + + +/* + * Component Instance : rstmgr + * + * Instance rstmgr of component ALT_RSTMGR. + * + * + */ +/* The address of the ALT_RSTMGR_STAT register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_STAT_OFST)) +/* The address of the ALT_RSTMGR_CTL register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_CTL_OFST)) +/* The address of the ALT_RSTMGR_COUNTS register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_COUNTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_COUNTS_OFST)) +/* The address of the ALT_RSTMGR_MPUMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_MPUMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_MPUMODRST_OFST)) +/* The address of the ALT_RSTMGR_PERMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_PERMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_PERMODRST_OFST)) +/* The address of the ALT_RSTMGR_PER2MODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_PER2MODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_PER2MODRST_OFST)) +/* The address of the ALT_RSTMGR_BRGMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_BRGMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_BRGMODRST_OFST)) +/* The address of the ALT_RSTMGR_MISCMODRST register for the ALT_RSTMGR instance. */ +#define ALT_RSTMGR_MISCMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_MISCMODRST_OFST)) +/* The base address byte offset for the start of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_OFST 0xffd05000 +/* The start address of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_RSTMGR_OFST)) +/* The lower bound address range of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_LB_ADDR ALT_RSTMGR_ADDR +/* The upper bound address range of the ALT_RSTMGR component. */ +#define ALT_RSTMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_RSTMGR_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : sysmgr + * + * Instance sysmgr of component ALT_SYSMGR. + * + * + */ +/* The address of the ALT_SYSMGR_SILICONID1 register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_SILICONID1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SILICONID1_OFST)) +/* The address of the ALT_SYSMGR_SILICONID2 register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_SILICONID2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SILICONID2_OFST)) +/* The address of the ALT_SYSMGR_WDDBG register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_WDDBG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_WDDBG_OFST)) +/* The address of the ALT_SYSMGR_BOOT register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_BOOT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_BOOT_OFST)) +/* The address of the ALT_SYSMGR_HPSINFO register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_HPSINFO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_HPSINFO_OFST)) +/* The address of the ALT_SYSMGR_PARITYINJ register for the ALT_SYSMGR instance. */ +#define ALT_SYSMGR_PARITYINJ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_PARITYINJ_OFST)) +/* + * Register Group Instance : fpgaintfgrp + * + * Instance fpgaintfgrp of register group ALT_SYSMGR_FPGAINTF. + * + * + */ +/* The address of the ALT_SYSMGR_FPGAINTF_GBL register for the ALT_SYSMGR_FPGAINTF instance. */ +#define ALT_SYSMGR_FPGAINTF_GBL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_GBL_OFST)) +/* The address of the ALT_SYSMGR_FPGAINTF_INDIV register for the ALT_SYSMGR_FPGAINTF instance. */ +#define ALT_SYSMGR_FPGAINTF_INDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_INDIV_OFST)) +/* The address of the ALT_SYSMGR_FPGAINTF_MODULE register for the ALT_SYSMGR_FPGAINTF instance. */ +#define ALT_SYSMGR_FPGAINTF_MODULE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_MODULE_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_OFST 0x20 +/* The start address of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_FPGAINTF_OFST)) +/* The lower bound address range of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_LB_ADDR ALT_SYSMGR_FPGAINTF_ADDR +/* The upper bound address range of the ALT_SYSMGR_FPGAINTF component. */ +#define ALT_SYSMGR_FPGAINTF_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + 0x10) - 1)) + + +/* + * Register Group Instance : scanmgrgrp + * + * Instance scanmgrgrp of register group ALT_SYSMGR_SCANMGR. + * + * + */ +/* The address of the ALT_SYSMGR_SCANMGR_CTL register for the ALT_SYSMGR_SCANMGR instance. */ +#define ALT_SYSMGR_SCANMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SCANMGR_ADDR) + ALT_SYSMGR_SCANMGR_CTL_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_OFST 0x30 +/* The start address of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SCANMGR_OFST)) +/* The lower bound address range of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_LB_ADDR ALT_SYSMGR_SCANMGR_ADDR +/* The upper bound address range of the ALT_SYSMGR_SCANMGR component. */ +#define ALT_SYSMGR_SCANMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_SCANMGR_ADDR) + 0x4) - 1)) + + +/* + * Register Group Instance : frzctrl + * + * Instance frzctrl of register group ALT_SYSMGR_FRZCTL. + * + * + */ +/* The address of the ALT_SYSMGR_FRZCTL_VIOCTL register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_VIOCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_VIOCTL_OFST)) +/* The address of the ALT_SYSMGR_FRZCTL_HIOCTL register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_HIOCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_HIOCTL_OFST)) +/* The address of the ALT_SYSMGR_FRZCTL_SRC register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_SRC_OFST)) +/* The address of the ALT_SYSMGR_FRZCTL_HWCTL register for the ALT_SYSMGR_FRZCTL instance. */ +#define ALT_SYSMGR_FRZCTL_HWCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_HWCTL_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_OFST 0x40 +/* The start address of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_FRZCTL_OFST)) +/* The lower bound address range of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_LB_ADDR ALT_SYSMGR_FRZCTL_ADDR +/* The upper bound address range of the ALT_SYSMGR_FRZCTL component. */ +#define ALT_SYSMGR_FRZCTL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + 0x20) - 1)) + + +/* + * Register Group Instance : emacgrp + * + * Instance emacgrp of register group ALT_SYSMGR_EMAC. + * + * + */ +/* The address of the ALT_SYSMGR_EMAC_CTL register for the ALT_SYSMGR_EMAC instance. */ +#define ALT_SYSMGR_EMAC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + ALT_SYSMGR_EMAC_CTL_OFST)) +/* The address of the ALT_SYSMGR_EMAC_L3MST register for the ALT_SYSMGR_EMAC instance. */ +#define ALT_SYSMGR_EMAC_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + ALT_SYSMGR_EMAC_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_OFST 0x60 +/* The start address of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_EMAC_OFST)) +/* The lower bound address range of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_LB_ADDR ALT_SYSMGR_EMAC_ADDR +/* The upper bound address range of the ALT_SYSMGR_EMAC component. */ +#define ALT_SYSMGR_EMAC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + 0x10) - 1)) + + +/* + * Register Group Instance : dmagrp + * + * Instance dmagrp of register group ALT_SYSMGR_DMA. + * + * + */ +/* The address of the ALT_SYSMGR_DMA_CTL register for the ALT_SYSMGR_DMA instance. */ +#define ALT_SYSMGR_DMA_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + ALT_SYSMGR_DMA_CTL_OFST)) +/* The address of the ALT_SYSMGR_DMA_PERSECURITY register for the ALT_SYSMGR_DMA instance. */ +#define ALT_SYSMGR_DMA_PERSECURITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + ALT_SYSMGR_DMA_PERSECURITY_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_OFST 0x70 +/* The start address of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_DMA_OFST)) +/* The lower bound address range of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_LB_ADDR ALT_SYSMGR_DMA_ADDR +/* The upper bound address range of the ALT_SYSMGR_DMA component. */ +#define ALT_SYSMGR_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + 0x8) - 1)) + + +/* + * Register Group Instance : iswgrp + * + * Instance iswgrp of register group ALT_SYSMGR_ISW. + * + * + */ +/* The address of the ALT_SYSMGR_ISW_HANDOFF register for the ALT_SYSMGR_ISW instance. */ +#define ALT_SYSMGR_ISW_HANDOFF_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ISW_ADDR) + ALT_SYSMGR_ISW_HANDOFF_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_OFST 0x80 +/* The start address of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ISW_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_LB_ADDR ALT_SYSMGR_ISW_ADDR +/* The upper bound address range of the ALT_SYSMGR_ISW component. */ +#define ALT_SYSMGR_ISW_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ISW_ADDR) + 0x20) - 1)) + + +/* + * Register Group Instance : romcodegrp + * + * Instance romcodegrp of register group ALT_SYSMGR_ROMCODE. + * + * + */ +/* The address of the ALT_SYSMGR_ROMCODE_CTL register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_CTL_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_INITSWSTATE register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_INITSWSTATE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_INITSWLASTLD register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST)) +/* The address of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE register for the ALT_SYSMGR_ROMCODE instance. */ +#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST)) +/* + * Register Group Instance : romcodegrp_warmramgrp + * + * Instance romcodegrp_warmramgrp of register group ALT_SYSMGR_ROMCODE_WARMRAM. + * + * + */ +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_EN_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_DATASTART_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_LEN_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_EXECUTION_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_CRC_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) +/* The base address byte offset for the start of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_OFST 0x20 +/* The start address of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_LB_ADDR ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR +/* The upper bound address range of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ +#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) + 0x20) - 1)) + + +/* The base address byte offset for the start of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_OFST 0xc0 +/* The start address of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ROMCODE_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_LB_ADDR ALT_SYSMGR_ROMCODE_ADDR +/* The upper bound address range of the ALT_SYSMGR_ROMCODE component. */ +#define ALT_SYSMGR_ROMCODE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : romhwgrp + * + * Instance romhwgrp of register group ALT_SYSMGR_ROMHW. + * + * + */ +/* The address of the ALT_SYSMGR_ROMHW_CTL register for the ALT_SYSMGR_ROMHW instance. */ +#define ALT_SYSMGR_ROMHW_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMHW_ADDR) + ALT_SYSMGR_ROMHW_CTL_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_OFST 0x100 +/* The start address of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ROMHW_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_LB_ADDR ALT_SYSMGR_ROMHW_ADDR +/* The upper bound address range of the ALT_SYSMGR_ROMHW component. */ +#define ALT_SYSMGR_ROMHW_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMHW_ADDR) + 0x4) - 1)) + + +/* + * Register Group Instance : sdmmcgrp + * + * Instance sdmmcgrp of register group ALT_SYSMGR_SDMMC. + * + * + */ +/* The address of the ALT_SYSMGR_SDMMC_CTL register for the ALT_SYSMGR_SDMMC instance. */ +#define ALT_SYSMGR_SDMMC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + ALT_SYSMGR_SDMMC_CTL_OFST)) +/* The address of the ALT_SYSMGR_SDMMC_L3MST register for the ALT_SYSMGR_SDMMC instance. */ +#define ALT_SYSMGR_SDMMC_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + ALT_SYSMGR_SDMMC_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_OFST 0x108 +/* The start address of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SDMMC_OFST)) +/* The lower bound address range of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_LB_ADDR ALT_SYSMGR_SDMMC_ADDR +/* The upper bound address range of the ALT_SYSMGR_SDMMC component. */ +#define ALT_SYSMGR_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + 0x8) - 1)) + + +/* + * Register Group Instance : nandgrp + * + * Instance nandgrp of register group ALT_SYSMGR_NAND. + * + * + */ +/* The address of the ALT_SYSMGR_NAND_BOOTSTRAP register for the ALT_SYSMGR_NAND instance. */ +#define ALT_SYSMGR_NAND_BOOTSTRAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + ALT_SYSMGR_NAND_BOOTSTRAP_OFST)) +/* The address of the ALT_SYSMGR_NAND_L3MST register for the ALT_SYSMGR_NAND instance. */ +#define ALT_SYSMGR_NAND_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + ALT_SYSMGR_NAND_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_OFST 0x110 +/* The start address of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_NAND_OFST)) +/* The lower bound address range of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_LB_ADDR ALT_SYSMGR_NAND_ADDR +/* The upper bound address range of the ALT_SYSMGR_NAND component. */ +#define ALT_SYSMGR_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + 0x8) - 1)) + + +/* + * Register Group Instance : usbgrp + * + * Instance usbgrp of register group ALT_SYSMGR_USB. + * + * + */ +/* The address of the ALT_SYSMGR_USB_L3MST register for the ALT_SYSMGR_USB instance. */ +#define ALT_SYSMGR_USB_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_USB_ADDR) + ALT_SYSMGR_USB_L3MST_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_OFST 0x118 +/* The start address of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_USB_OFST)) +/* The lower bound address range of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_LB_ADDR ALT_SYSMGR_USB_ADDR +/* The upper bound address range of the ALT_SYSMGR_USB component. */ +#define ALT_SYSMGR_USB_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_USB_ADDR) + 0x4) - 1)) + + +/* + * Register Group Instance : eccgrp + * + * Instance eccgrp of register group ALT_SYSMGR_ECC. + * + * + */ +/* The address of the ALT_SYSMGR_ECC_L2 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_L2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_L2_OFST)) +/* The address of the ALT_SYSMGR_ECC_OCRAM register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_OCRAM_OFST)) +/* The address of the ALT_SYSMGR_ECC_USB0 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_USB0_OFST)) +/* The address of the ALT_SYSMGR_ECC_USB1 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_USB1_OFST)) +/* The address of the ALT_SYSMGR_ECC_EMAC0 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_EMAC0_OFST)) +/* The address of the ALT_SYSMGR_ECC_EMAC1 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_EMAC1_OFST)) +/* The address of the ALT_SYSMGR_ECC_DMA register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_DMA_OFST)) +/* The address of the ALT_SYSMGR_ECC_CAN0 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_CAN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_CAN0_OFST)) +/* The address of the ALT_SYSMGR_ECC_CAN1 register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_CAN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_CAN1_OFST)) +/* The address of the ALT_SYSMGR_ECC_NAND register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_NAND_OFST)) +/* The address of the ALT_SYSMGR_ECC_QSPI register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_QSPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_QSPI_OFST)) +/* The address of the ALT_SYSMGR_ECC_SDMMC register for the ALT_SYSMGR_ECC instance. */ +#define ALT_SYSMGR_ECC_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_SDMMC_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_OFST 0x140 +/* The start address of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ECC_OFST)) +/* The lower bound address range of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_LB_ADDR ALT_SYSMGR_ECC_ADDR +/* The upper bound address range of the ALT_SYSMGR_ECC component. */ +#define ALT_SYSMGR_ECC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + 0x40) - 1)) + + +/* + * Register Group Instance : pinmuxgrp + * + * Instance pinmuxgrp of register group ALT_SYSMGR_PINMUX. + * + * + */ +/* The address of the ALT_SYSMGR_PINMUX_EMACIO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_EMACIO19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_EMACIO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_FLSHIO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_FLSHIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO20 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO20_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO21 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO21_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO22 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO22_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO22_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO23 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO23_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO24 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO24_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO24_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO25 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO25_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO25_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO26 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO26_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO26_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO27 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO27_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO27_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO28 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO28_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO28_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO29 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO29_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO29_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO30 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO30_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO30_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GENERALIO31 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GENERALIO31_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO31_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO20 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO20_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO21 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED1IO21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO21_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_MIXED2IO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX48 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX48_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX48_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX49 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX49_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX49_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX50 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX50_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX50_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX51 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX51_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX51_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX52 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX52_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX52_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX53 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX53_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX53_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX54 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX54_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX54_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX55 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX55_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX55_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX56 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX56_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX56_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX57 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX57_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX57_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX58 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX58_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX58_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX59 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX59_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX59_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX60 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX60_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX60_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX61 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX61_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX61_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX62 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX62_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX62_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX63 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX63_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX63_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX64 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX64_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX64_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX65 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX65_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX65_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX66 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX66_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX66_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX67 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX67_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX67_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX68 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX68_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX68_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX69 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX69_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX69_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX70 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLINMUX70_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX70_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX0 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX0_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX1 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX1_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX2 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX2_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX3 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX3_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX4 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX4_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX5 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX5_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX6 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX6_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX7 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX7_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX8 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX8_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX9 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX9_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX10 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX10_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX11 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX11_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX12 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX12_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX13 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX13_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX14 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX14_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX15 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX15_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX16 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX16_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX17 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX17_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX18 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX18_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX19 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX19_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX20 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX20_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX21 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX21_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX22 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX22_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX22_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX23 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX23_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX24 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX24_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX24_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX25 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX25_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX25_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX26 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX26_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX26_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX27 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX27_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX27_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX28 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX28_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX28_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX29 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX29_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX29_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX30 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX30_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX30_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX31 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX31_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX31_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX32 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX32_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX33 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX33_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX33_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX34 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX34_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX34_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX35 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX35_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX35_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX36 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX36_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX36_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX37 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX37_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX37_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX38 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX38_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX38_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX39 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX39_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX39_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX40 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX40_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX40_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX41 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX41_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX41_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX42 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX42_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX42_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX43 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX43_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX43_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX44 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX44_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX44_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX45 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX45_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX45_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX46 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX46_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX46_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX47 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX47_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX47_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX48 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX48_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX48_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX49 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX49_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX49_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX50 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX50_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX50_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX51 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX51_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX51_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX52 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX52_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX52_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX53 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX53_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX53_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX54 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX54_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX54_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX55 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX55_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX55_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX56 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX56_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX56_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX57 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX57_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX57_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX58 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX58_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX58_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX59 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX59_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX59_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX60 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX60_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX60_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX61 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX61_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX61_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX62 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX62_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX62_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX63 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX63_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX63_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX64 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX64_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX64_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX65 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX65_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX65_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX66 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX66_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX66_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX67 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX67_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX67_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX68 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX68_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX68_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX69 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX69_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX69_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_GPLMUX70 register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_GPLMUX70_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX70_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_NANDUSEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C3USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C2USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_I2C1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST)) +/* The address of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ +#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST)) +/* The base address byte offset for the start of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_OFST 0x400 +/* The start address of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_PINMUX_OFST)) +/* The lower bound address range of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_LB_ADDR ALT_SYSMGR_PINMUX_ADDR +/* The upper bound address range of the ALT_SYSMGR_PINMUX component. */ +#define ALT_SYSMGR_PINMUX_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + 0x400) - 1)) + + +/* The base address byte offset for the start of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_OFST 0xffd08000 +/* The start address of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SYSMGR_OFST)) +/* The lower bound address range of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_LB_ADDR ALT_SYSMGR_ADDR +/* The upper bound address range of the ALT_SYSMGR component. */ +#define ALT_SYSMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ADDR) + 0x4000) - 1)) + + +/* + * Component Instance : dmanonsecure + * + * Instance dmanonsecure of component ALT_DMANONSECURE. + * + * + */ +/* The address of the ALT_DMANONSECURE_REG register for the ALT_DMANONSECURE instance. */ +#define ALT_DMANONSECURE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DMANONSECURE_ADDR) + ALT_DMANONSECURE_REG_OFST)) +/* The base address byte offset for the start of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_OFST 0xffe00000 +/* The start address of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DMANONSECURE_OFST)) +/* The lower bound address range of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_LB_ADDR ALT_DMANONSECURE_ADDR +/* The upper bound address range of the ALT_DMANONSECURE component. */ +#define ALT_DMANONSECURE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DMANONSECURE_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : dmasecure + * + * Instance dmasecure of component ALT_DMASECURE. + * + * + */ +/* The address of the ALT_DMASECURE_REG register for the ALT_DMASECURE instance. */ +#define ALT_DMASECURE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DMASECURE_ADDR) + ALT_DMASECURE_REG_OFST)) +/* The base address byte offset for the start of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_OFST 0xffe01000 +/* The start address of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DMASECURE_OFST)) +/* The lower bound address range of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_LB_ADDR ALT_DMASECURE_ADDR +/* The upper bound address range of the ALT_DMASECURE component. */ +#define ALT_DMASECURE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DMASECURE_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : spis0 + * + * Instance spis0 of component ALT_SPIS. + * + * + */ +/* The address of the ALT_SPIS_CTLR0 register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_CTLR0_ADDR ALT_SPIS_CTLR0_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_SPIENR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_SPIENR_ADDR ALT_SPIS_SPIENR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_MWCR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_MWCR_ADDR ALT_SPIS_MWCR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_TXFTLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_TXFTLR_ADDR ALT_SPIS_TXFTLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXFTLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXFTLR_ADDR ALT_SPIS_RXFTLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_TXFLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_TXFLR_ADDR ALT_SPIS_TXFLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXFLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXFLR_ADDR ALT_SPIS_RXFLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_SR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_SR_ADDR ALT_SPIS_SR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_IMR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_IMR_ADDR ALT_SPIS_IMR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_ISR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_ISR_ADDR ALT_SPIS_ISR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RISR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RISR_ADDR ALT_SPIS_RISR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_TXOICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_TXOICR_ADDR ALT_SPIS_TXOICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXOICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXOICR_ADDR ALT_SPIS_RXOICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_RXUICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_RXUICR_ADDR ALT_SPIS_RXUICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_ICR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_ICR_ADDR ALT_SPIS_ICR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DMACR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DMACR_ADDR ALT_SPIS_DMACR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DMATDLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DMATDLR_ADDR ALT_SPIS_DMATDLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DMARDLR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DMARDLR_ADDR ALT_SPIS_DMARDLR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_IDR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_IDR_ADDR ALT_SPIS_IDR_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_SPI_VER_ID register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_SPI_VER_ID_ADDR ALT_SPIS_SPI_VER_ID_ADDR(ALT_SPIS0_ADDR) +/* The address of the ALT_SPIS_DR register for the ALT_SPIS0 instance. */ +#define ALT_SPIS0_DR_ADDR ALT_SPIS_DR_ADDR(ALT_SPIS0_ADDR) +/* The base address byte offset for the start of the ALT_SPIS0 component. */ +#define ALT_SPIS0_OFST 0xffe02000 +/* The start address of the ALT_SPIS0 component. */ +#define ALT_SPIS0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIS0_OFST)) +/* The lower bound address range of the ALT_SPIS0 component. */ +#define ALT_SPIS0_LB_ADDR ALT_SPIS0_ADDR +/* The upper bound address range of the ALT_SPIS0 component. */ +#define ALT_SPIS0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIS0_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : spis1 + * + * Instance spis1 of component ALT_SPIS. + * + * + */ +/* The address of the ALT_SPIS_CTLR0 register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_CTLR0_ADDR ALT_SPIS_CTLR0_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_SPIENR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_SPIENR_ADDR ALT_SPIS_SPIENR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_MWCR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_MWCR_ADDR ALT_SPIS_MWCR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_TXFTLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_TXFTLR_ADDR ALT_SPIS_TXFTLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXFTLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXFTLR_ADDR ALT_SPIS_RXFTLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_TXFLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_TXFLR_ADDR ALT_SPIS_TXFLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXFLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXFLR_ADDR ALT_SPIS_RXFLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_SR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_SR_ADDR ALT_SPIS_SR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_IMR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_IMR_ADDR ALT_SPIS_IMR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_ISR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_ISR_ADDR ALT_SPIS_ISR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RISR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RISR_ADDR ALT_SPIS_RISR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_TXOICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_TXOICR_ADDR ALT_SPIS_TXOICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXOICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXOICR_ADDR ALT_SPIS_RXOICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_RXUICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_RXUICR_ADDR ALT_SPIS_RXUICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_ICR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_ICR_ADDR ALT_SPIS_ICR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DMACR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DMACR_ADDR ALT_SPIS_DMACR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DMATDLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DMATDLR_ADDR ALT_SPIS_DMATDLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DMARDLR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DMARDLR_ADDR ALT_SPIS_DMARDLR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_IDR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_IDR_ADDR ALT_SPIS_IDR_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_SPI_VER_ID register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_SPI_VER_ID_ADDR ALT_SPIS_SPI_VER_ID_ADDR(ALT_SPIS1_ADDR) +/* The address of the ALT_SPIS_DR register for the ALT_SPIS1 instance. */ +#define ALT_SPIS1_DR_ADDR ALT_SPIS_DR_ADDR(ALT_SPIS1_ADDR) +/* The base address byte offset for the start of the ALT_SPIS1 component. */ +#define ALT_SPIS1_OFST 0xffe03000 +/* The start address of the ALT_SPIS1 component. */ +#define ALT_SPIS1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIS1_OFST)) +/* The lower bound address range of the ALT_SPIS1 component. */ +#define ALT_SPIS1_LB_ADDR ALT_SPIS1_ADDR +/* The upper bound address range of the ALT_SPIS1 component. */ +#define ALT_SPIS1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIS1_ADDR) + 0x80) - 1)) + + +/* + * Component Instance : spim0 + * + * Instance spim0 of component ALT_SPIM. + * + * + */ +/* The address of the ALT_SPIM_CTLR0 register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_CTLR0_ADDR ALT_SPIM_CTLR0_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_CTLR1 register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_CTLR1_ADDR ALT_SPIM_CTLR1_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SPIENR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SPIENR_ADDR ALT_SPIM_SPIENR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_MWCR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_MWCR_ADDR ALT_SPIM_MWCR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SER register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SER_ADDR ALT_SPIM_SER_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_BAUDR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_BAUDR_ADDR ALT_SPIM_BAUDR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_TXFTLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_TXFTLR_ADDR ALT_SPIM_TXFTLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXFTLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXFTLR_ADDR ALT_SPIM_RXFTLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_TXFLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_TXFLR_ADDR ALT_SPIM_TXFLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXFLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXFLR_ADDR ALT_SPIM_RXFLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SR_ADDR ALT_SPIM_SR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_IMR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_IMR_ADDR ALT_SPIM_IMR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_ISR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_ISR_ADDR ALT_SPIM_ISR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RISR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RISR_ADDR ALT_SPIM_RISR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_TXOICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_TXOICR_ADDR ALT_SPIM_TXOICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXOICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXOICR_ADDR ALT_SPIM_RXOICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RXUICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RXUICR_ADDR ALT_SPIM_RXUICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_ICR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_ICR_ADDR ALT_SPIM_ICR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DMACR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DMACR_ADDR ALT_SPIM_DMACR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DMATDLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DMATDLR_ADDR ALT_SPIM_DMATDLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DMARDLR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DMARDLR_ADDR ALT_SPIM_DMARDLR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_IDR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_IDR_ADDR ALT_SPIM_IDR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_SPI_VER_ID register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_SPI_VER_ID_ADDR ALT_SPIM_SPI_VER_ID_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_DR register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_DR_ADDR ALT_SPIM_DR_ADDR(ALT_SPIM0_ADDR) +/* The address of the ALT_SPIM_RX_SMPL_DLY register for the ALT_SPIM0 instance. */ +#define ALT_SPIM0_RX_SMPL_DLY_ADDR ALT_SPIM_RX_SMPL_DLY_ADDR(ALT_SPIM0_ADDR) +/* The base address byte offset for the start of the ALT_SPIM0 component. */ +#define ALT_SPIM0_OFST 0xfff00000 +/* The start address of the ALT_SPIM0 component. */ +#define ALT_SPIM0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIM0_OFST)) +/* The lower bound address range of the ALT_SPIM0 component. */ +#define ALT_SPIM0_LB_ADDR ALT_SPIM0_ADDR +/* The upper bound address range of the ALT_SPIM0 component. */ +#define ALT_SPIM0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIM0_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : spim1 + * + * Instance spim1 of component ALT_SPIM. + * + * + */ +/* The address of the ALT_SPIM_CTLR0 register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_CTLR0_ADDR ALT_SPIM_CTLR0_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_CTLR1 register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_CTLR1_ADDR ALT_SPIM_CTLR1_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SPIENR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SPIENR_ADDR ALT_SPIM_SPIENR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_MWCR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_MWCR_ADDR ALT_SPIM_MWCR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SER register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SER_ADDR ALT_SPIM_SER_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_BAUDR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_BAUDR_ADDR ALT_SPIM_BAUDR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_TXFTLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_TXFTLR_ADDR ALT_SPIM_TXFTLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXFTLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXFTLR_ADDR ALT_SPIM_RXFTLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_TXFLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_TXFLR_ADDR ALT_SPIM_TXFLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXFLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXFLR_ADDR ALT_SPIM_RXFLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SR_ADDR ALT_SPIM_SR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_IMR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_IMR_ADDR ALT_SPIM_IMR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_ISR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_ISR_ADDR ALT_SPIM_ISR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RISR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RISR_ADDR ALT_SPIM_RISR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_TXOICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_TXOICR_ADDR ALT_SPIM_TXOICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXOICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXOICR_ADDR ALT_SPIM_RXOICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RXUICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RXUICR_ADDR ALT_SPIM_RXUICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_ICR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_ICR_ADDR ALT_SPIM_ICR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DMACR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DMACR_ADDR ALT_SPIM_DMACR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DMATDLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DMATDLR_ADDR ALT_SPIM_DMATDLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DMARDLR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DMARDLR_ADDR ALT_SPIM_DMARDLR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_IDR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_IDR_ADDR ALT_SPIM_IDR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_SPI_VER_ID register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_SPI_VER_ID_ADDR ALT_SPIM_SPI_VER_ID_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_DR register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_DR_ADDR ALT_SPIM_DR_ADDR(ALT_SPIM1_ADDR) +/* The address of the ALT_SPIM_RX_SMPL_DLY register for the ALT_SPIM1 instance. */ +#define ALT_SPIM1_RX_SMPL_DLY_ADDR ALT_SPIM_RX_SMPL_DLY_ADDR(ALT_SPIM1_ADDR) +/* The base address byte offset for the start of the ALT_SPIM1 component. */ +#define ALT_SPIM1_OFST 0xfff01000 +/* The start address of the ALT_SPIM1 component. */ +#define ALT_SPIM1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIM1_OFST)) +/* The lower bound address range of the ALT_SPIM1 component. */ +#define ALT_SPIM1_LB_ADDR ALT_SPIM1_ADDR +/* The upper bound address range of the ALT_SPIM1 component. */ +#define ALT_SPIM1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIM1_ADDR) + 0x100) - 1)) + + +/* + * Component Instance : scanmgr + * + * Instance scanmgr of component ALT_SCANMGR. + * + * + */ +/* The address of the ALT_SCANMGR_STAT register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_STAT_OFST)) +/* The address of the ALT_SCANMGR_EN register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_EN_OFST)) +/* The address of the ALT_SCANMGR_FIFOSINGLEBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFOSINGLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOSINGLEBYTE_OFST)) +/* The address of the ALT_SCANMGR_FIFODOUBLEBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFODOUBLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFODOUBLEBYTE_OFST)) +/* The address of the ALT_SCANMGR_FIFOTRIPLEBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFOTRIPLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOTRIPLEBYTE_OFST)) +/* The address of the ALT_SCANMGR_FIFOQUADBYTE register for the ALT_SCANMGR instance. */ +#define ALT_SCANMGR_FIFOQUADBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOQUADBYTE_OFST)) +/* The base address byte offset for the start of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_OFST 0xfff02000 +/* The start address of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SCANMGR_OFST)) +/* The lower bound address range of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_LB_ADDR ALT_SCANMGR_ADDR +/* The upper bound address range of the ALT_SCANMGR component. */ +#define ALT_SCANMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SCANMGR_ADDR) + 0x20) - 1)) + + +/* + * Component Instance : rom + * + * Instance rom of component ALT_ROM. + * + * + */ +/* The base address byte offset for the start of the ALT_ROM component. */ +#define ALT_ROM_OFST 0xfffd0000 +/* The start address of the ALT_ROM component. */ +#define ALT_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_ROM_OFST)) +/* The lower bound address range of the ALT_ROM component. */ +#define ALT_ROM_LB_ADDR ALT_ROM_ADDR +/* The upper bound address range of the ALT_ROM component. */ +#define ALT_ROM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_ROM_ADDR) + 0x10000) - 1)) + + +/* + * Component Instance : mpuscu + * + * Instance mpuscu of component ALT_MPUSCU. + * + * + */ +/* The address of the ALT_MPUSCU_REG register for the ALT_MPUSCU instance. */ +#define ALT_MPUSCU_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUSCU_ADDR) + ALT_MPUSCU_REG_OFST)) +/* The base address byte offset for the start of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_OFST 0xfffec000 +/* The start address of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_MPUSCU_OFST)) +/* The lower bound address range of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_LB_ADDR ALT_MPUSCU_ADDR +/* The upper bound address range of the ALT_MPUSCU component. */ +#define ALT_MPUSCU_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_MPUSCU_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : mpul2 + * + * Instance mpul2 of component ALT_MPUL2. + * + * + */ +/* The address of the ALT_MPUL2_REG register for the ALT_MPUL2 instance. */ +#define ALT_MPUL2_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_REG_OFST)) +/* The base address byte offset for the start of the ALT_MPUL2 component. */ +#define ALT_MPUL2_OFST 0xfffef000 +/* The start address of the ALT_MPUL2 component. */ +#define ALT_MPUL2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_MPUL2_OFST)) +/* The lower bound address range of the ALT_MPUL2 component. */ +#define ALT_MPUL2_LB_ADDR ALT_MPUL2_ADDR +/* The upper bound address range of the ALT_MPUL2 component. */ +#define ALT_MPUL2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_MPUL2_ADDR) + 0x4) - 1)) + + +/* + * Component Instance : ocram + * + * Instance ocram of component ALT_OCRAM. + * + * + */ +/* The base address byte offset for the start of the ALT_OCRAM component. */ +#define ALT_OCRAM_OFST 0xffff0000 +/* The start address of the ALT_OCRAM component. */ +#define ALT_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OCRAM_OFST)) +/* The lower bound address range of the ALT_OCRAM component. */ +#define ALT_OCRAM_LB_ADDR ALT_OCRAM_ADDR +/* The upper bound address range of the ALT_OCRAM component. */ +#define ALT_OCRAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OCRAM_ADDR) + 0x10000) - 1)) + + +/* + * Address Space : ALT_HPS + * + * Address Map + * + * Address Range | Component + * :------------------------|:----------------- + * 0x00000000 - 0xfbffffff | Undefined + * 0xfc000000 - 0xfc000003 | ALT_STM + * 0xfc000004 - 0xfeffffff | Undefined + * 0xff000000 - 0xff000003 | ALT_DAP + * 0xff000004 - 0xff1fffff | Undefined + * 0xff200000 - 0xff3fffff | ALT_LWFPGASLVS + * 0xff400000 - 0xff47ffff | ALT_LWH2F + * 0xff480000 - 0xff4fffff | Undefined + * 0xff500000 - 0xff507fff | ALT_H2F + * 0xff508000 - 0xff5fffff | Undefined + * 0xff600000 - 0xff67ffff | ALT_F2H + * 0xff680000 - 0xff6fffff | Undefined + * 0xff700000 - 0xff701fff | ALT_EMAC0 + * 0xff702000 - 0xff703fff | ALT_EMAC1 + * 0xff704000 - 0xff7043ff | ALT_SDMMC + * 0xff704400 - 0xff704fff | Undefined + * 0xff705000 - 0xff7050ff | ALT_QSPI + * 0xff705100 - 0xff705fff | Undefined + * 0xff706000 - 0xff706fff | ALT_FPGAMGR + * 0xff707000 - 0xff707fff | ALT_ACPIDMAP + * 0xff708000 - 0xff70807f | ALT_GPIO0 + * 0xff708080 - 0xff708fff | Undefined + * 0xff709000 - 0xff70907f | ALT_GPIO1 + * 0xff709080 - 0xff709fff | Undefined + * 0xff70a000 - 0xff70a07f | ALT_GPIO2 + * 0xff70a080 - 0xff7fffff | Undefined + * 0xff800000 - 0xff87ffff | ALT_L3 + * 0xff880000 - 0xff8fffff | Undefined + * 0xff900000 - 0xff9fffff | ALT_NANDDATA + * 0xffa00000 - 0xffafffff | ALT_QSPIDATA + * 0xffb00000 - 0xffb3ffff | ALT_USB0 + * 0xffb40000 - 0xffb7ffff | ALT_USB1 + * 0xffb80000 - 0xffb807ff | ALT_NAND + * 0xffb80800 - 0xffb8ffff | Undefined + * 0xffb90000 - 0xffb90003 | ALT_FPGAMGRDATA + * 0xffb90004 - 0xffbfffff | Undefined + * 0xffc00000 - 0xffc001ff | ALT_CAN0 + * 0xffc00200 - 0xffc00fff | Undefined + * 0xffc01000 - 0xffc011ff | ALT_CAN1 + * 0xffc01200 - 0xffc01fff | Undefined + * 0xffc02000 - 0xffc020ff | ALT_UART0 + * 0xffc02100 - 0xffc02fff | Undefined + * 0xffc03000 - 0xffc030ff | ALT_UART1 + * 0xffc03100 - 0xffc03fff | Undefined + * 0xffc04000 - 0xffc040ff | ALT_I2C0 + * 0xffc04100 - 0xffc04fff | Undefined + * 0xffc05000 - 0xffc050ff | ALT_I2C1 + * 0xffc05100 - 0xffc05fff | Undefined + * 0xffc06000 - 0xffc060ff | ALT_I2C2 + * 0xffc06100 - 0xffc06fff | Undefined + * 0xffc07000 - 0xffc070ff | ALT_I2C3 + * 0xffc07100 - 0xffc07fff | Undefined + * 0xffc08000 - 0xffc080ff | ALT_SPTMR0 + * 0xffc08100 - 0xffc08fff | Undefined + * 0xffc09000 - 0xffc090ff | ALT_SPTMR1 + * 0xffc09100 - 0xffc1ffff | Undefined + * 0xffc20000 - 0xffc3ffff | ALT_SDR + * 0xffc40000 - 0xffcfffff | Undefined + * 0xffd00000 - 0xffd000ff | ALT_OSC1TMR0 + * 0xffd00100 - 0xffd00fff | Undefined + * 0xffd01000 - 0xffd010ff | ALT_OSC1TMR1 + * 0xffd01100 - 0xffd01fff | Undefined + * 0xffd02000 - 0xffd020ff | ALT_L4WD0 + * 0xffd02100 - 0xffd02fff | Undefined + * 0xffd03000 - 0xffd030ff | ALT_L4WD1 + * 0xffd03100 - 0xffd03fff | Undefined + * 0xffd04000 - 0xffd041ff | ALT_CLKMGR + * 0xffd04200 - 0xffd04fff | Undefined + * 0xffd05000 - 0xffd050ff | ALT_RSTMGR + * 0xffd05100 - 0xffd07fff | Undefined + * 0xffd08000 - 0xffd0bfff | ALT_SYSMGR + * 0xffd0c000 - 0xffdfffff | Undefined + * 0xffe00000 - 0xffe00003 | ALT_DMANONSECURE + * 0xffe00004 - 0xffe00fff | Undefined + * 0xffe01000 - 0xffe01003 | ALT_DMASECURE + * 0xffe01004 - 0xffe01fff | Undefined + * 0xffe02000 - 0xffe0207f | ALT_SPIS0 + * 0xffe02080 - 0xffe02fff | Undefined + * 0xffe03000 - 0xffe0307f | ALT_SPIS1 + * 0xffe03080 - 0xffefffff | Undefined + * 0xfff00000 - 0xfff000ff | ALT_SPIM0 + * 0xfff00100 - 0xfff00fff | Undefined + * 0xfff01000 - 0xfff010ff | ALT_SPIM1 + * 0xfff01100 - 0xfff01fff | Undefined + * 0xfff02000 - 0xfff0201f | ALT_SCANMGR + * 0xfff02020 - 0xfffcffff | Undefined + * 0xfffd0000 - 0xfffdffff | ALT_ROM + * 0xfffe0000 - 0xfffebfff | Undefined + * 0xfffec000 - 0xfffec003 | ALT_MPUSCU + * 0xfffec004 - 0xfffeefff | Undefined + * 0xfffef000 - 0xfffef003 | ALT_MPUL2 + * 0xfffef004 - 0xfffeffff | Undefined + * 0xffff0000 - 0xffffffff | ALT_OCRAM + */ + +#ifdef __ASSEMBLY__ +#define ALT_CAST(type, ptr) ptr +#else /* __ASSEMBLY__ */ +#define ALT_CAST(type, ptr) ((type) (ptr)) +#endif /* __ASSEMBLY__ */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_HPS_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/socal.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/socal.h new file mode 100644 index 000000000..40a043218 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/socal.h @@ -0,0 +1,259 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + + +/*! \file Altera - ALT_SOCAL */ + +#ifndef __ALTERA_SOCAL_H__ +#define __ALTERA_SOCAL_H__ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#include +#include +#include +#else /* __cplusplus */ +#include +#include +#include +#endif /* __cplusplus */ +#endif /* __ASSEMBLY__ */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * \addtogroup ALT_SOCAL_UTIL SoCAL Utilities + * + * This file contains utility and support functions for the Altera SoCAL. + * @{ + */ + +#ifdef __ASSEMBLY__ +#define ALT_CAST(type, ptr) ptr +#else /* __ASSEMBLY__ */ +/*! Cast the pointer to specified pointer type. + * + * Note: This macro expands to \e ptr value only for assembler language + * targets. + * + * \param type The pointer type to cast to + * \param ptr The pointer to apply the type cast to + */ +#define ALT_CAST(type, ptr) ((type) (ptr)) +#endif /* __ASSEMBLY__ */ + +/*! + * \addtogroup ALT_SOCAL_UTIL_RW_FUNC SoCAL Memory Read/Write Utilities + * + * This section implements read and write functionality for various + * memory untis. The memory unit terms used for these functions are + * consistent with those used in the ARM Architecture Reference Manual + * ARMv7-A and ARMv7-R edition manual. The terms used for units of memory are: + * + * Unit of Memory | Abbreviation | Size in Bits + * :---------------|:-------------|:------------: + * Byte | byte | 8 + * Half Word | hword | 16 + * Word | word | 32 + * Double Word | dword | 64 + * + * @{ + */ + +/*! Write the 8 bit byte to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 8 bit data byte to write to memory + */ +#define alt_write_byte(dest, src) (*ALT_CAST(volatile uint8_t *, (dest)) = (src)) + +/*! Read and return the 8 bit byte from the source address in device memory. + * \param src Read source pointer address + * \returns 8 bit data byte value + */ +#define alt_read_byte(src) (*ALT_CAST(volatile uint8_t *, (src))) + +/*! Write the 16 bit half word to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 16 bit data half word to write to memory + */ +#define alt_write_hword(dest, src) (*ALT_CAST(volatile uint16_t *, (dest)) = (src)) + +/*! Read and return the 16 bit half word from the source address in device memory. + * \param src Read source pointer address + * \returns 16 bit data half word value + */ +#define alt_read_hword(src) (*ALT_CAST(volatile uint16_t *, (src))) + +/*! Write the 32 bit word to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 32 bit data word to write to memory + */ +#define alt_write_word(dest, src) (*ALT_CAST(volatile uint32_t *, (dest)) = (src)) + +/*! Read and return the 32 bit word from the source address in device memory. + * \param src Read source pointer address + * \returns 32 bit data word value + */ +#define alt_read_word(src) (*ALT_CAST(volatile uint32_t *, (src))) + +/*! Write the 64 bit double word to the destination address in device memory. + * \param dest - Write destination pointer address + * \param src - 64 bit data double word to write to memory + */ +#define alt_write_dword(dest, src) (*ALT_CAST(volatile uint64_t *, (dest)) = (src)) + +/*! Read and return the 64 bit double word from the source address in device memory. + * \param src Read source pointer address + * \returns 64 bit data double word value + */ +#define alt_read_dword(src) (*ALT_CAST(volatile uint64_t *, (src))) + +/*! @} */ + +/*! + * \addtogroup ALT_SOCAL_UTIL_SC_FUNC SoCAL Memory Bit Set/Clr/XOR/Replace Utilities + * + * This section implements useful macros to set, clear, change, and replace + * selected bits within a word in memory or a memory-mapped register. + * @{ + * + */ + +/*! Set selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination byte + */ +#define alt_setbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) | (bits))) + +/*! Clear selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination byte + */ +#define alt_clrbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination byte + */ +#define alt_xorbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) ^ (bits))) + +/*! Replace selected bits in the 8 bit byte at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination byte + * \param src - Source bits to write to cleared bits in destination byte + */ +#define alt_replbits_byte(dest, msk, src) (alt_write_byte(dest,(alt_read_byte(dest) & ~(msk)) | ((src) & (msk)))) + +/*! Set selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination halfword + */ +#define alt_setbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) | (bits))) + +/*! Clear selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination halfword + */ +#define alt_clrbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination halfword + */ +#define alt_xorbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) ^ (bits))) + +/*! Replace selected bits in the 16 bit halfword at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination halfword + * \param src - Source bits to write to cleared bits in destination halfword + */ +#define alt_replbits_hword(dest, msk, src) (alt_write_hword(dest,(alt_read_hword(dest) & ~(msk)) | ((src) & (msk)))) + +/*! Set selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination word + */ +#define alt_setbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) | (bits))) + +/*! Clear selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination word + */ +#define alt_clrbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination word + */ +#define alt_xorbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) ^ (bits))) + +/*! Replace selected bits in the 32 bit word at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination word + * \param src - Source bits to write to cleared bits in destination word + */ +#define alt_replbits_word(dest, msk, src) (alt_write_word(dest,(alt_read_word(dest) & ~(msk)) | ((src) & (msk)))) + +/*! Set selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to set in destination doubleword + */ +#define alt_setbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) | (bits))) + +/*! Clear selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to clear in destination doubleword + */ +#define alt_clrbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) & ~(bits))) + +/*! Change or toggle selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param bits - Bits to change in destination doubleword + */ +#define alt_xorbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) ^ (bits))) + +/*! Replace selected bits in the 64 bit doubleword at the destination address in device memory. + * \param dest - Destination pointer address + * \param msk - Bits to replace in destination doubleword + * \param src - Source bits to write to cleared bits in destination word + */ +#define alt_replbits_dword(dest, msk, src) (alt_write_dword(dest,(alt_read_dword(dest) & ~(msk)) | ((src) & (msk)))) + +/*! @} */ + +/*! @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALTERA_SOCAL_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/cache_support.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/cache_support.c new file mode 100644 index 000000000..65ad644e4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/cache_support.c @@ -0,0 +1,97 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "alt_cache.h" +#include "socal/hps.h" +#include "socal/socal.h" +#include "cache_support.h" +//#include "boot_support.h" + +ALT_STATUS_CODE cache_init(void) { + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + + // + // The 13.1 release of alt_cache.c does not appear to initialize the L2 + // cache latency registers properly so we'll do that here. + // + configure_L2_ram_latency(); + + // + // Enable the shared attribute override enable bit in the L2 aux control register + // + enable_shared_attribute_override_enable(); + + status = alt_cache_system_enable(); +// BOOT_CHECK_STATUS; + + return status; +} + +ALT_STATUS_CODE cache_uninit(void) { + + return alt_cache_system_disable(); +} + +void enable_shared_attribute_override_enable(void) { + + bool l2_enabled = alt_cache_l2_is_enabled(); + + if (l2_enabled) + { + alt_cache_l2_disable(); + } + + alt_setbits_word(ALT_MPUL2_AUX_CONTROL_ADDR, SHARED_ATTRIBUTE_OVERRIDE_ENABLE_MASK); + + if (l2_enabled) + { + alt_cache_l2_enable(); + } +} + +void configure_L2_ram_latency(void) { + + bool l2_enabled = alt_cache_l2_is_enabled(); + + if (l2_enabled) + { + alt_cache_l2_disable(); + } + + alt_write_word(ALT_MPUL2_TAG_RAM_CONTROL_ADDR, ALT_MPUL2_TAG_RAM_CONTROL_VALUE); + alt_write_word(ALT_MPUL2_DATA_RAM_CONTROL_ADDR, ALT_MPUL2_DATA_RAM_CONTROL_VALUE); + + if (l2_enabled) + { + alt_cache_l2_enable(); + } +} +/* md5sum:ec3ba66ee5cff385248a93a050de2432 2013-09-28 20:48:16 */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/fpga_support.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/fpga_support.c new file mode 100644 index 000000000..66b9dce58 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/fpga_support.c @@ -0,0 +1,80 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "alt_fpga_manager.h" +#include "fpga_support.h" + +#define printf( ... ) + +ALT_STATUS_CODE fpga_init(void) { + + // Program the FPGA + uint32_t status = ALT_E_SUCCESS; + uint32_t i; + + // This is the symbol name for the SOF file contents linked in. + extern char _binary_soc_system_dc_rbf_start; + extern char _binary_soc_system_dc_rbf_end; + + // Use the above symbols to extract the FPGA image information. + const char * fpga_image = &_binary_soc_system_dc_rbf_start; + const uint32_t fpga_image_size = &_binary_soc_system_dc_rbf_end - &_binary_soc_system_dc_rbf_start; + + // Trace the FPGA image information. + printf("INFO: FPGA Image binary at %p.\n", fpga_image); + printf("INFO: FPGA Image size is %u bytes.\n", (unsigned int)fpga_image_size); + + // Try the full configuration a few times. + const uint32_t full_config_retry = 5; + for (i = 0; i < full_config_retry; ++i) + { + status = alt_fpga_configure(fpga_image, fpga_image_size); + if (status == ALT_E_SUCCESS) + { + printf("INFO: alt_fpga_configure() successful on the %u of %u retry(s).\n", + (unsigned int)(i + 1), + (unsigned int)full_config_retry); + break; + } + } + + + if (status == ALT_E_SUCCESS) + { + printf("INFO: Setup of FPGA successful.\n\n"); + } + else + { + printf("ERROR: Setup of FPGA return non-SUCCESS %d.\n\n", (int)status); + } + + return status; +} +/* md5sum:e268b2157060033c39e9ea2c5068165f 2013-09-28 20:48:16 */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/cache_support.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/cache_support.h new file mode 100644 index 000000000..c2237aa94 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/cache_support.h @@ -0,0 +1,55 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef CACHE_SUPPORT_H_ +#define CACHE_SUPPORT_H_ + +#include "hwlib.h" + +#define ALT_MPUL2_AUX_CONTROL_OFST 0x104 +#define ALT_MPUL2_TAG_RAM_CONTROL_OFST 0x108 +#define ALT_MPUL2_DATA_RAM_CONTROL_OFST 0x10c + +#define ALT_MPUL2_AUX_CONTROL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_AUX_CONTROL_OFST)) +#define ALT_MPUL2_TAG_RAM_CONTROL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_TAG_RAM_CONTROL_OFST)) +#define ALT_MPUL2_DATA_RAM_CONTROL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_DATA_RAM_CONTROL_OFST)) + +#define ALT_MPUL2_TAG_RAM_CONTROL_VALUE 0x00000000 +#define ALT_MPUL2_DATA_RAM_CONTROL_VALUE 0x00000010 + +#define SHARED_ATTRIBUTE_OVERRIDE_ENABLE_MASK 0x00400000 + +ALT_STATUS_CODE cache_init(void); +ALT_STATUS_CODE cache_uninit(void); +void enable_shared_attribute_override_enable(void); +void configure_L2_ram_latency(void); + +#endif /* CACHE_SUPPORT_H_ */ +/* md5sum:58fb245f969aec44340df388edf9806b 2013-09-28 20:48:16 */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/fpga_support.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/fpga_support.h new file mode 100644 index 000000000..ffe07e66a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/fpga_support.h @@ -0,0 +1,42 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef FPGA_SUPPORT_H_ +#define FPGA_SUPPORT_H_ + +#include "hwlib.h" + +extern char _binary_soc_system_rbf_start; +extern char _binary_soc_system_rbf_end; + +ALT_STATUS_CODE fpga_init(void); + +#endif /* FPGA_SUPPORT_H_ */ +/* md5sum:887b9ebee4569ce8bd823342a5ce847e 2013-09-28 20:48:16 */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/mmu_support.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/mmu_support.h new file mode 100644 index 000000000..09f83ab32 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/include/mmu_support.h @@ -0,0 +1,40 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef MMU_SUPPORT_H_ +#define MMU_SUPPORT_H_ + +#include "hwlib.h" + +ALT_STATUS_CODE mmu_init(void); +ALT_STATUS_CODE mmu_uninit(void); + +#endif /* MMU_SUPPORT_H_ */ +/* md5sum:dfae487bb7fe641d39c46b8c06396d48 2013-09-28 20:48:16 */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/mmu_support.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/mmu_support.c new file mode 100644 index 000000000..fc214cc1e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/mmu_support.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* +* Copyright 2013 Altera Corporation. All Rights Reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO +* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +* OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "alt_mmu.h" +#include "mmu_support.h" +//#include "boot_support.h" +#define ARRAY_COUNT(array) (sizeof(array) / sizeof(array[0])) + + +static uint32_t __attribute__ ((aligned (0x4000))) mmu_pt_storage[4096]; + +static void * mmu_pt_alloc(const size_t size, void * context) { + + return context; +} + +ALT_STATUS_CODE mmu_init(void) { + + // + // Populate the page table with sections (1 MiB regions). + // + ALT_MMU_MEM_REGION_t regions[] = + { + // Cacheable Memory area: 1 GiB + { + .va = (void *)0x00000000, + .pa = (void *)0x00000000, + .size = 0x40000000, + .access = ALT_MMU_AP_FULL_ACCESS, + .attributes = ALT_MMU_ATTR_WBA, + .shareable = ALT_MMU_TTB_S_NON_SHAREABLE, + .execute = ALT_MMU_TTB_XN_DISABLE, + .security = ALT_MMU_TTB_NS_SECURE + }, + + // Non-cacheable Memory area: 1 GiB + { + .va = (void *)0x40000000, + .pa = (void *)0x00000000, + .size = 0x40000000, + .access = ALT_MMU_AP_FULL_ACCESS, + .attributes = ALT_MMU_ATTR_NC, + .shareable = ALT_MMU_TTB_S_SHAREABLE, + .execute = ALT_MMU_TTB_XN_DISABLE, + .security = ALT_MMU_TTB_NS_SECURE + }, + + // Device area: Everything else + { + .va = (void *)0x80000000, + .pa = (void *)0x40000000, + .size = 0x40000000, + .access = ALT_MMU_AP_NO_ACCESS, + .attributes = ALT_MMU_ATTR_FAULT, + .shareable = ALT_MMU_TTB_S_SHAREABLE, + .execute = ALT_MMU_TTB_XN_ENABLE, + .security = ALT_MMU_TTB_NS_SECURE + }, + + // Device area: Everything else + { + .va = (void *)0xC0000000, + .pa = (void *)0xC0000000, + .size = 0x40000000, + .access = ALT_MMU_AP_FULL_ACCESS, + .attributes = ALT_MMU_ATTR_DEVICE, + .shareable = ALT_MMU_TTB_S_SHAREABLE, + .execute = ALT_MMU_TTB_XN_ENABLE, + .security = ALT_MMU_TTB_NS_SECURE + } + }; + + ALT_STATUS_CODE status = ALT_E_SUCCESS; + uint32_t * ttb1 = NULL; + + status |= alt_mmu_init(); +// BOOT_CHECK_STATUS; + + size_t reqsize = alt_mmu_va_space_storage_required(regions, + ARRAY_COUNT(regions)); + if (reqsize > sizeof(mmu_pt_storage)) + status = ALT_E_ERROR; +// BOOT_CHECK_STATUS; + + status |= alt_mmu_va_space_create(&ttb1, regions, ARRAY_COUNT(regions), mmu_pt_alloc, mmu_pt_storage); +// BOOT_CHECK_STATUS; + + status |= alt_mmu_va_space_enable(ttb1); +// BOOT_CHECK_STATUS; + + return status; +} + +ALT_STATUS_CODE mmu_uninit(void) { + + return alt_mmu_disable(); +} +/* md5sum:4fc6b96893e8e619490fad33b17c96d7 2013-09-28 20:48:16 */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/FreeRTOSConfig.h new file mode 100644 index 000000000..30c8e0a42 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/FreeRTOSConfig.h @@ -0,0 +1,232 @@ +/* + FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* + * The FreeRTOS Cortex-A port implements a full interrupt nesting model. + * + * Interrupts that are assigned a priority at or below + * configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM + * generic interrupt controller [GIC] means a priority that has a numerical + * value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API + * functions and will nest. + * + * Interrupts that are assigned a priority above + * configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical + * value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS + * API functions, will nest, and will not be masked by FreeRTOS critical + * sections (although it is necessary for interrupts to be globally disabled + * extremely briefly as the interrupt mask is updated in the GIC). + * + * FreeRTOS functions that can be called from an interrupt are those that end in + * "FromISR". FreeRTOS maintains a separate interrupt safe API to enable + * interrupt entry to be shorter, faster, simpler and smaller. + * + * The Cyclone V SoC implements 256 unique interrupt priorities. For the + * purpose of setting configMAX_API_CALL_INTERRUPT_PRIORITY 255 represents the + * lowest priority. + */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY 18 + +#define configCPU_CLOCK_HZ /* Not used in this portabsciex.com. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configMAX_PRIORITIES ( 7 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 ) +#define configTOTAL_HEAP_SIZE ( 5 * 1024 ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_eTaskGetState 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + + +#define configGENERATE_RUN_TIME_STATS 0 + +/* The size of the global output buffer that is available for use when there +are multiple command interpreters running at once (for example, one on a UART +and one on TCP/IP). This is done to prevent an output buffer being defined by +each implementation - which would waste RAM. In this case, there is only one +command interpreter running. */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096 + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +void vAssertCalled( const char * pcFile, unsigned long ulLine ); +#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ); + +/* If configTASK_RETURN_ADDRESS is not defined then a task that attempts to +return from its implementing function will end up in a "task exit error" +function - which contains a call to configASSERT(). However this can give GCC +some problems when it tries to unwind the stack, as the exit error function has +nothing to return to. To avoid this define configTASK_RETURN_ADDRESS to 0. */ +#define configTASK_RETURN_ADDRESS NULL + + +/****** Hardware specific settings. *******************************************/ + +/* Rename the FreeRTOS interrupt handlers to the names used in the vector +table. */ +//#define FreeRTOS_IRQ_Handler __cs3_isr_irq +//#define FreeRTOS_SWI_Handler __cs3_isr_swi +// --defsym=__cs3_isr_irq=FreeRTOS_IRQ_Handler --defsym=__cs3_isr_swi=FreeRTOS_SWI_Handler + + +/* Altera library includes. */ +#include "hwlib.h" +#include "alt_timers.h" +#include "alt_clock_manager.h" +#include "alt_interrupt.h" +#include "alt_globaltmr.h" +#include "alt_address_space.h" +#include "alt_watchdog.h" +#include "mmu_support.h" +#include "cache_support.h" +#include "fpga_support.h" + + typedef struct INT_DISPATCH_s + { + alt_int_callback_t pxISR; + void * pvContext; + } + INT_DISPATCH_t; + +void vRegisterIRQHandler( uint32_t ulID, alt_int_callback_t pxHandlerFunction, void *pvContext ); +void vApplicationIRQHandler( uint32_t ulICCIAR ); + +/* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. This file contains a function + * that is suitable for use on the Zynq MPU. FreeRTOS_Tick_Handler() must + * be installed as the peripheral's interrupt handler. + */ +void vConfigureTickInterrupt( void ); +#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt(); + +void vClearTickInterrupt( void ); +#define configCLEAR_TICK_INTERRUPT() alt_gpt_int_clear_pending( ALT_GPT_CPU_PRIVATE_TMR ); + +/* The following constant describe the hardware, and are correct for the +Cyclone V SoC. */ +#define configINTERRUPT_CONTROLLER_BASE_ADDRESS ( 0xFFFED000 ) +#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ( -0xf00 ) +#define configUNIQUE_INTERRUPT_PRIORITIES 32 + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/cycloneV-dk-oc-ram.ld b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/cycloneV-dk-oc-ram.ld new file mode 100644 index 000000000..35697225d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/cycloneV-dk-oc-ram.ld @@ -0,0 +1,257 @@ +/* Linker script for Altera CycloneV-DK (On-Chip) + * + * Version: Sourcery CodeBench Lite 2013.11-67 + * Support: https://sourcery.mentor.com/GNUToolchain/ + * + * Copyright (c) 2007-2010 CodeSourcery, Inc. + * Copyright (c) 2010-2014 Mentor Graphics, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(__cs3_reset) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3arm) + +MEMORY +{ + boot_rom (rx) : ORIGIN = 0xfffd0000, LENGTH = 64K + ram (rwx) : ORIGIN = 0xffff0000, LENGTH = 64K + ddr_sdram (rwx) : ORIGIN = 0x100000, LENGTH = 1023M +} + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(__cs3_reset __cs3_reset_cycloneV_dk_oc_ram) +EXTERN(__cs3_start_asm _start) +/* Bring in the interrupt routines & vector */ +INCLUDE arm-names.inc +EXTERN(__cs3_interrupt_vector_arm) +EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) + +/* Provide fall-back values */ +PROVIDE(__cs3_heap_start = _end); +PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); +PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20); +PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); + +SECTIONS +{ + .text : + { + CREATE_OBJECT_SYMBOLS + __cs3_region_start_ram = .; + _ftext = .; + *(.cs3.region-head.ram) + ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted"); + __cs3_interrupt_vector = __cs3_interrupt_vector_arm; + *(.cs3.interrupt_vector) + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cs3_interrupt_vector_arm, "No interrupt vector"); + + PROVIDE(__cs3_reset = __cs3_reset_cycloneV_dk_oc_ram); + *(.cs3.reset) + _start = DEFINED(__cs3_start_asm) ? __cs3_start_asm : _start; + + *(.text.cs3.init) + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + } >ram + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + *(.eh_frame_entry .eh_frame_entry.*) + } >ram + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) *(.eh_frame.*) + } >ram + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >ram + PROVIDE_HIDDEN (__exidx_end = .); + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cs3_regions = .; + LONG (0) + LONG (__cs3_region_init_ram) + LONG (__cs3_region_start_ram) + LONG (__cs3_region_init_size_ram) + LONG (__cs3_region_zero_size_ram) + LONG (0) + LONG (__cs3_region_init_ddr_sdram) + LONG (__cs3_region_start_ddr_sdram) + LONG (__cs3_region_init_size_ddr_sdram) + LONG (__cs3_region_zero_size_ddr_sdram) + __cs3_regions_end = .; + . = ALIGN (8); + _etext = .; + } >ram + + ASSERT (!(__cs3_region_init_ram & 7), "__cs3_region_init_ram not aligned") + ASSERT (!(__cs3_region_start_ram & 7), "__cs3_region_start_ram not aligned") + ASSERT (!(__cs3_region_init_size_ram & 7), "__cs3_region_init_size_ram not aligned") + ASSERT (!(__cs3_region_zero_size_ram & 7), "__cs3_region_zero_size_ram not aligned") + ASSERT (!(__cs3_region_init_ddr_sdram & 7), "__cs3_region_init_ddr_sdram not aligned") + ASSERT (!(__cs3_region_start_ddr_sdram & 7), "__cs3_region_start_ddr_sdram not aligned") + ASSERT (!(__cs3_region_init_size_ddr_sdram & 7), "__cs3_region_init_size_ddr_sdram not aligned") + ASSERT (!(__cs3_region_zero_size_ddr_sdram & 7), "__cs3_region_zero_size_ddr_sdram not aligned") + .cs3.boot_rom : ALIGN (8) + { + __cs3_region_start_boot_rom = .; + *(.cs3.region-head.boot_rom) + *(.boot_rom) + . = ALIGN (8); + } >boot_rom + .cs3.boot_rom.bss : + { + *(.boot_rom.b .bss.boot_rom) + . = ALIGN (8); + } >boot_rom + /* __cs3_region_end_boot_rom is deprecated */ + __cs3_region_end_boot_rom = __cs3_region_start_boot_rom + LENGTH(boot_rom); + __cs3_region_size_boot_rom = LENGTH(boot_rom); + __cs3_region_init_boot_rom = LOADADDR (.cs3.boot_rom); + __cs3_region_init_size_boot_rom = LOADADDR (.cs3.boot_rom.bss) - LOADADDR (.cs3.boot_rom); + __cs3_region_zero_size_boot_rom = SIZEOF(.cs3.boot_rom.bss); + + .cs3.ddr_sdram : ALIGN (8) + { + __cs3_region_start_ddr_sdram = .; + *(.cs3.region-head.ddr_sdram) + *(.ddr_sdram) + . = ALIGN (8); + } >ddr_sdram + .cs3.ddr_sdram.bss : + { + *(.ddr_sdram.b .bss.ddr_sdram) + . = ALIGN (8); + } >ddr_sdram + /* __cs3_region_end_ddr_sdram is deprecated */ + __cs3_region_end_ddr_sdram = __cs3_region_start_ddr_sdram + LENGTH(ddr_sdram); + __cs3_region_size_ddr_sdram = LENGTH(ddr_sdram); + __cs3_region_init_ddr_sdram = LOADADDR (.cs3.ddr_sdram); + __cs3_region_init_size_ddr_sdram = LOADADDR (.cs3.ddr_sdram.bss) - LOADADDR (.cs3.ddr_sdram); + __cs3_region_zero_size_ddr_sdram = SIZEOF(.cs3.ddr_sdram.bss); + + .data : ALIGN (8) + { + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + . = ALIGN (8); + _edata = .; + } >ram + .bss : ALIGN (8) + { + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b .bss.ram) + . = ALIGN (8); + _end = .; + __end = .; + } >ram + /* __cs3_region_end_ram is deprecated */ + __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram); + __cs3_region_size_ram = LENGTH(ram); + __cs3_region_init_ram = LOADADDR (.text); + __cs3_region_init_size_ram = _edata - ADDR (.text); + __cs3_region_zero_size_ram = _end - _edata; + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to + * the beginning of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} +/* checksum: 5147380005b11342f0da6db */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/cycloneV-dk-ram.ld b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/cycloneV-dk-ram.ld new file mode 100644 index 000000000..89078a264 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/cycloneV-dk-ram.ld @@ -0,0 +1,257 @@ +/* Linker script for Altera CycloneV-DK + * + * Version: Sourcery CodeBench Lite 2013.11-67 + * Support: https://sourcery.mentor.com/GNUToolchain/ + * + * Copyright (c) 2007-2010 CodeSourcery, Inc. + * Copyright (c) 2010-2014 Mentor Graphics, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(__cs3_reset) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3arm) + +MEMORY +{ + boot_rom (rx) : ORIGIN = 0xfffd0000, LENGTH = 64K + oc_ram (rwx) : ORIGIN = 0xffff0000, LENGTH = 64K + ram (rwx) : ORIGIN = 0x100000, LENGTH = 1023M +} + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(__cs3_reset __cs3_reset_cycloneV_dk_ram) +EXTERN(__cs3_start_asm _start) +/* Bring in the interrupt routines & vector */ +INCLUDE arm-names.inc +EXTERN(__cs3_interrupt_vector_arm) +EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) + +/* Provide fall-back values */ +PROVIDE(__cs3_heap_start = _end); +PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); +PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20); +PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); + +SECTIONS +{ + .text : + { + CREATE_OBJECT_SYMBOLS + __cs3_region_start_ram = .; + _ftext = .; + *(.cs3.region-head.ram) + ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted"); + __cs3_interrupt_vector = __cs3_interrupt_vector_arm; + *(.cs3.interrupt_vector) + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cs3_interrupt_vector_arm, "No interrupt vector"); + + PROVIDE(__cs3_reset = __cs3_reset_cycloneV_dk_ram); + *(.cs3.reset) + _start = DEFINED(__cs3_start_asm) ? __cs3_start_asm : _start; + + *(.text.cs3.init) + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + } >ram + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + *(.eh_frame_entry .eh_frame_entry.*) + } >ram + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) *(.eh_frame.*) + } >ram + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >ram + PROVIDE_HIDDEN (__exidx_end = .); + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cs3_regions = .; + LONG (0) + LONG (__cs3_region_init_oc_ram) + LONG (__cs3_region_start_oc_ram) + LONG (__cs3_region_init_size_oc_ram) + LONG (__cs3_region_zero_size_oc_ram) + LONG (0) + LONG (__cs3_region_init_ram) + LONG (__cs3_region_start_ram) + LONG (__cs3_region_init_size_ram) + LONG (__cs3_region_zero_size_ram) + __cs3_regions_end = .; + . = ALIGN (8); + _etext = .; + } >ram + + ASSERT (!(__cs3_region_init_oc_ram & 7), "__cs3_region_init_oc_ram not aligned") + ASSERT (!(__cs3_region_start_oc_ram & 7), "__cs3_region_start_oc_ram not aligned") + ASSERT (!(__cs3_region_init_size_oc_ram & 7), "__cs3_region_init_size_oc_ram not aligned") + ASSERT (!(__cs3_region_zero_size_oc_ram & 7), "__cs3_region_zero_size_oc_ram not aligned") + ASSERT (!(__cs3_region_init_ram & 7), "__cs3_region_init_ram not aligned") + ASSERT (!(__cs3_region_start_ram & 7), "__cs3_region_start_ram not aligned") + ASSERT (!(__cs3_region_init_size_ram & 7), "__cs3_region_init_size_ram not aligned") + ASSERT (!(__cs3_region_zero_size_ram & 7), "__cs3_region_zero_size_ram not aligned") + .cs3.boot_rom : ALIGN (8) + { + __cs3_region_start_boot_rom = .; + *(.cs3.region-head.boot_rom) + *(.boot_rom) + . = ALIGN (8); + } >boot_rom + .cs3.boot_rom.bss : + { + *(.boot_rom.b .bss.boot_rom) + . = ALIGN (8); + } >boot_rom + /* __cs3_region_end_boot_rom is deprecated */ + __cs3_region_end_boot_rom = __cs3_region_start_boot_rom + LENGTH(boot_rom); + __cs3_region_size_boot_rom = LENGTH(boot_rom); + __cs3_region_init_boot_rom = LOADADDR (.cs3.boot_rom); + __cs3_region_init_size_boot_rom = LOADADDR (.cs3.boot_rom.bss) - LOADADDR (.cs3.boot_rom); + __cs3_region_zero_size_boot_rom = SIZEOF(.cs3.boot_rom.bss); + + .cs3.oc_ram : ALIGN (8) + { + __cs3_region_start_oc_ram = .; + *(.cs3.region-head.oc_ram) + *(.oc_ram) + . = ALIGN (8); + } >oc_ram + .cs3.oc_ram.bss : + { + *(.oc_ram.b .bss.oc_ram) + . = ALIGN (8); + } >oc_ram + /* __cs3_region_end_oc_ram is deprecated */ + __cs3_region_end_oc_ram = __cs3_region_start_oc_ram + LENGTH(oc_ram); + __cs3_region_size_oc_ram = LENGTH(oc_ram); + __cs3_region_init_oc_ram = LOADADDR (.cs3.oc_ram); + __cs3_region_init_size_oc_ram = LOADADDR (.cs3.oc_ram.bss) - LOADADDR (.cs3.oc_ram); + __cs3_region_zero_size_oc_ram = SIZEOF(.cs3.oc_ram.bss); + + .data : ALIGN (8) + { + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + . = ALIGN (8); + _edata = .; + } >ram + .bss : ALIGN (8) + { + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b .bss.ram) + . = ALIGN (8); + _end = .; + __end = .; + } >ram + /* __cs3_region_end_ram is deprecated */ + __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram); + __cs3_region_size_ram = LENGTH(ram); + __cs3_region_init_ram = LOADADDR (.text); + __cs3_region_init_size_ram = _edata - ADDR (.text); + __cs3_region_zero_size_ram = _end - _edata; + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to + * the beginning of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} +/* checksum: 107f7843360731655cf27621 */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c new file mode 100644 index 000000000..f2345e7e1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c @@ -0,0 +1,196 @@ +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*-----------------------------------------------------------*/ + +/* Perform any hardware initialisation necessary. */ +static void prvSetupHardware( void ); + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + prvSetupHardware(); + vTaskStartScheduler(); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + alt_int_global_init(); + cache_init(); + //_RB_mmu_init(); +} +/*-----------------------------------------------------------*/ + +void vConfigureTickInterrupt( void ) +{ +alt_freq_t ulTempFrequency; +const alt_freq_t ulMicroSecondsPerSecond = 1000000UL; +void FreeRTOS_Tick_Handler( void ); + + /* Interrupts are disabled when this function is called. */ + + /* Initialise the general purpose timer modules. */ + alt_gpt_all_tmr_init(); + + /* ALT_CLK_MPU_PERIPH = mpu_periph_clk */ + alt_clk_freq_get( ALT_CLK_MPU_PERIPH, &ulTempFrequency ); + + /* Use the local private timer. */ + alt_gpt_counter_set( ALT_GPT_CPU_PRIVATE_TMR, ulTempFrequency / configTICK_RATE_HZ ); + + /* Sanity check. */ + configASSERT( alt_gpt_time_microsecs_get( ALT_GPT_CPU_PRIVATE_TMR ) == ( ulMicroSecondsPerSecond / configTICK_RATE_HZ ) ); + + /* Set to periodic mode. */ + alt_gpt_mode_set( ALT_GPT_CPU_PRIVATE_TMR, ALT_GPT_RESTART_MODE_PERIODIC ); + + /* The timer can be started here as interrupts are disabled. */ + alt_gpt_tmr_start( ALT_GPT_CPU_PRIVATE_TMR ); + + /* Register the standard FreeRTOS Cortex-A tick handler as the timer's + interrupt handler. The handler clears the interrupt using the + configCLEAR_TICK_INTERRUPT() macro, which is defined in FreeRTOSConfig.h. */ + vRegisterIRQHandler( ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE, ( alt_int_callback_t ) FreeRTOS_Tick_Handler, NULL ); + + /* Ensure the interrupt is forwarded to the CPU. */ + alt_int_dist_enable( ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE ); + + /* Finally, enable the interrupt. */ + alt_gpt_int_clear_pending( ALT_GPT_CPU_PRIVATE_TMR ); + alt_gpt_int_enable( ALT_GPT_CPU_PRIVATE_TMR ); + +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vAssertCalled( const char * pcFile, unsigned long ulLine ) +{ +volatile unsigned long ul = 0; + + ( void ) pcFile; + ( void ) ulLine; + + taskENTER_CRITICAL(); + { + /* Set ul to a non-zero value using the debugger to step out of this + function. */ + while( ul == 0 ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if( mainSELECTED_APPLICATION == 1 ) + { + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + } + #endif +} +/*-----------------------------------------------------------*/ + + +#warning A separate array of handlers is maintained as the drivers array is static so cannot be reached and the handler is incompatible. +static INT_DISPATCH_t xISRHandlers[ ALT_INT_PROVISION_INT_COUNT ]; + +void vRegisterIRQHandler( uint32_t ulID, alt_int_callback_t pxHandlerFunction, void *pvContext ) +{ + if( ulID < ALT_INT_PROVISION_INT_COUNT ) + { + xISRHandlers[ ulID ].pxISR = pxHandlerFunction; + xISRHandlers[ ulID ].pvContext = pvContext; + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIRQHandler( uint32_t ulICCIAR ) +{ +uint32_t ulInterruptID; +void *pvContext; +alt_int_callback_t pxISR; + + /* Re-enable interrupts. */ + __asm ( "cpsie i" ); + + /* The ID of the interrupt is obtained by bitwise anding the ICCIAR value + with 0x3FF. */ + ulInterruptID = ulICCIAR & 0x3FFUL; + + if( ulInterruptID < ALT_INT_PROVISION_INT_COUNT ) + { + /* Call the function installed in the array of installed handler + functions. */ + pxISR = xISRHandlers[ ulInterruptID ].pxISR; + pvContext = xISRHandlers[ ulInterruptID ].pvContext; + pxISR( ulICCIAR, pvContext ); + } +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/preloader.ds b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/preloader.ds new file mode 100644 index 000000000..68300f92d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/preloader.ds @@ -0,0 +1,48 @@ +############################################################ +# +# Copyright Altera 2013 +# All Rights Reserved +# File: preloader.ds +# +############################################################ + +# +# stop processor if running +# +stop +wait 5s +reset system +wait 5s + +#set semihosting enabled 0 + +# +# load the preloader (a.k.a the spl from our uboot dist) +# +loadfile "$sdir/uboot-socfpga/spl/u-boot-spl" 0x0 + +# +# set pc to entry point +# +set debug-from *$entrypoint # Set start-at setting to address of $entrypoint +start + +# +# delete any breakpoints +# +delete + +# +# set hw breakpoint in spl in function, spl_boot_device, +# The function, spl_boot_device, is called right before the spl tries +# to load. We stop here so we don't have to change any spl. +# +tbreak spl_boot_device + +# tell target to continue executing spl +cont + +# wait for breakpoint +wait 60s + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/printf-stdarg.c b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/printf-stdarg.c new file mode 100644 index 000000000..a25cab6ce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/printf-stdarg.c @@ -0,0 +1,312 @@ +/* + Copyright 2001, 2002 Georges Menie (www.menie.org) + stdarg version contributed by Christian Ettinger + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +/* + putchar is the only external dependency for this file, + if you have a working putchar, leave it commented out. + If not, uncomment the define below and + replace outbyte(c) by your own function call. + +*/ + +#define putchar(c) c + +#include + +static int tiny_print( char **out, const char *format, va_list args, unsigned int buflen ); + +static void printchar(char **str, int c, char *buflimit) +{ + //extern int putchar(int c); + + if (str) { + if( buflimit == ( char * ) 0 ) { + /* Limit of buffer not known, write charater to buffer. */ + **str = (char)c; + ++(*str); + } + else if( ( ( unsigned long ) *str ) < ( ( unsigned long ) buflimit ) ) { + /* Withing known limit of buffer, write character. */ + **str = (char)c; + ++(*str); + } + } + else + { + (void)putchar(c); + } +} + +#define PAD_RIGHT 1 +#define PAD_ZERO 2 + +static int prints(char **out, const char *string, int width, int pad, char *buflimit) +{ + register int pc = 0, padchar = ' '; + + if (width > 0) { + register int len = 0; + register const char *ptr; + for (ptr = string; *ptr; ++ptr) ++len; + if (len >= width) width = 0; + else width -= len; + if (pad & PAD_ZERO) padchar = '0'; + } + if (!(pad & PAD_RIGHT)) { + for ( ; width > 0; --width) { + printchar (out, padchar, buflimit); + ++pc; + } + } + for ( ; *string ; ++string) { + printchar (out, *string, buflimit); + ++pc; + } + for ( ; width > 0; --width) { + printchar (out, padchar, buflimit); + ++pc; + } + + return pc; +} + +/* the following should be enough for 32 bit int */ +#define PRINT_BUF_LEN 12 + +static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase, char *buflimit) +{ + char print_buf[PRINT_BUF_LEN]; + register char *s; + register int t, neg = 0, pc = 0; + register unsigned int u = (unsigned int)i; + + if (i == 0) { + print_buf[0] = '0'; + print_buf[1] = '\0'; + return prints (out, print_buf, width, pad, buflimit); + } + + if (sg && b == 10 && i < 0) { + neg = 1; + u = (unsigned int)-i; + } + + s = print_buf + PRINT_BUF_LEN-1; + *s = '\0'; + + while (u) { + t = (unsigned int)u % b; + if( t >= 10 ) + t += letbase - '0' - 10; + *--s = (char)(t + '0'); + u /= b; + } + + if (neg) { + if( width && (pad & PAD_ZERO) ) { + printchar (out, '-', buflimit); + ++pc; + --width; + } + else { + *--s = '-'; + } + } + + return pc + prints (out, s, width, pad, buflimit); +} + +static int tiny_print( char **out, const char *format, va_list args, unsigned int buflen ) +{ + register int width, pad; + register int pc = 0; + char scr[2], *buflimit; + + if( buflen == 0 ){ + buflimit = ( char * ) 0; + } + else { + /* Calculate the last valid buffer space, leaving space for the NULL + terminator. */ + buflimit = ( *out ) + ( buflen - 1 ); + } + + for (; *format != 0; ++format) { + if (*format == '%') { + ++format; + width = pad = 0; + if (*format == '\0') break; + if (*format == '%') goto out; + if (*format == '-') { + ++format; + pad = PAD_RIGHT; + } + while (*format == '0') { + ++format; + pad |= PAD_ZERO; + } + for ( ; *format >= '0' && *format <= '9'; ++format) { + width *= 10; + width += *format - '0'; + } + if( *format == 's' ) { + register char *s = (char *)va_arg( args, int ); + pc += prints (out, s?s:"(null)", width, pad, buflimit); + continue; + } + if( *format == 'd' ) { + pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a', buflimit); + continue; + } + if( *format == 'x' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a', buflimit); + continue; + } + if( *format == 'X' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A', buflimit); + continue; + } + if( *format == 'u' ) { + pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a', buflimit); + continue; + } + if( *format == 'c' ) { + /* char are converted to int then pushed on the stack */ + scr[0] = (char)va_arg( args, int ); + scr[1] = '\0'; + pc += prints (out, scr, width, pad, buflimit); + continue; + } + } + else { + out: + printchar (out, *format, buflimit); + ++pc; + } + } + if (out) **out = '\0'; + va_end( args ); + return pc; +} + +int printf(const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return tiny_print( 0, format, args, 0 ); +} + +int sprintf(char *out, const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return tiny_print( &out, format, args, 0 ); +} + + +int snprintf( char *buf, unsigned int count, const char *format, ... ) +{ + va_list args; + + ( void ) count; + + va_start( args, format ); + return tiny_print( &buf, format, args, count ); +} + + +#ifdef TEST_PRINTF +int main(void) +{ + char *ptr = "Hello world!"; + char *np = 0; + int i = 5; + unsigned int bs = sizeof(int)*8; + int mi; + char buf[80]; + + mi = (1 << (bs-1)) + 1; + printf("%s\n", ptr); + printf("printf test\n"); + printf("%s is null pointer\n", np); + printf("%d = 5\n", i); + printf("%d = - max int\n", mi); + printf("char %c = 'a'\n", 'a'); + printf("hex %x = ff\n", 0xff); + printf("hex %02x = 00\n", 0); + printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3); + printf("%d %s(s)%", 0, "message"); + printf("\n"); + printf("%d %s(s) with %%\n", 0, "message"); + sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf); + sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf); + sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf); + sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf); + sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf); + sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf); + sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf); + sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf); + + return 0; +} + +/* + * if you compile this file with + * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c + * you will get a normal warning: + * printf.c:214: warning: spurious trailing `%' in format + * this line is testing an invalid % at the end of the format string. + * + * this should display (on 32bit int machine) : + * + * Hello world! + * printf test + * (null) is null pointer + * 5 = 5 + * -2147483647 = - max int + * char a = 'a' + * hex ff = ff + * hex 00 = 00 + * signed -3 = unsigned 4294967293 = hex fffffffd + * 0 message(s) + * 0 message(s) with % + * justif: "left " + * justif: " right" + * 3: 0003 zero padded + * 3: 3 left justif. + * 3: 3 right justif. + * -3: -003 zero padded + * -3: -3 left justif. + * -3: -3 right justif. + */ + +#endif + + +/* To keep linker happy. */ +int write( int i, char* c, int n) +{ + (void)i; + (void)n; + (void)c; + return 0; +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/uboot-socfpga/spl/u-boot-spl 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It must be a hardware +# breakpoint because this is after relocation. +# +thbreak board_init_r +cont +wait 60s + + -- 2.39.5